Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 40
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 29
1 12:25:22.274493 lava-dispatcher, installed at version: 2023.05.1
2 12:25:22.274703 start: 0 validate
3 12:25:22.274834 Start time: 2023-06-06 12:25:22.274826+00:00 (UTC)
4 12:25:22.274964 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:25:22.275099 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 12:25:22.566770 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:25:22.566970 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:25:23.350946 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:25:23.351133 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:25:45.832439 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:25:45.832620 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:25:46.415878 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:25:46.416060 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:25:46.702547 validate duration: 24.43
16 12:25:46.702815 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:25:46.702929 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:25:46.703021 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:25:46.703153 Not decompressing ramdisk as can be used compressed.
20 12:25:46.703251 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/initrd.cpio.gz
21 12:25:46.703333 saving as /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/ramdisk/initrd.cpio.gz
22 12:25:46.703417 total size: 5624321 (5MB)
23 12:25:49.975395 progress 0% (0MB)
24 12:25:49.977068 progress 5% (0MB)
25 12:25:49.978683 progress 10% (0MB)
26 12:25:49.980462 progress 15% (0MB)
27 12:25:49.982209 progress 20% (1MB)
28 12:25:49.983794 progress 25% (1MB)
29 12:25:49.985464 progress 30% (1MB)
30 12:25:49.987123 progress 35% (1MB)
31 12:25:49.988614 progress 40% (2MB)
32 12:25:49.990341 progress 45% (2MB)
33 12:25:49.991776 progress 50% (2MB)
34 12:25:49.993404 progress 55% (2MB)
35 12:25:49.994947 progress 60% (3MB)
36 12:25:49.996650 progress 65% (3MB)
37 12:25:49.998309 progress 70% (3MB)
38 12:25:49.999728 progress 75% (4MB)
39 12:25:50.001367 progress 80% (4MB)
40 12:25:50.002902 progress 85% (4MB)
41 12:25:50.004751 progress 90% (4MB)
42 12:25:50.006419 progress 95% (5MB)
43 12:25:50.007917 progress 100% (5MB)
44 12:25:50.008121 5MB downloaded in 3.30s (1.62MB/s)
45 12:25:50.008283 end: 1.1.1 http-download (duration 00:00:03) [common]
47 12:25:50.008550 end: 1.1 download-retry (duration 00:00:03) [common]
48 12:25:50.008645 start: 1.2 download-retry (timeout 00:09:57) [common]
49 12:25:50.008746 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 12:25:50.008905 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:25:50.008990 saving as /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/kernel/Image
52 12:25:50.009068 total size: 45746688 (43MB)
53 12:25:50.009132 No compression specified
54 12:25:50.010313 progress 0% (0MB)
55 12:25:50.022548 progress 5% (2MB)
56 12:25:50.035038 progress 10% (4MB)
57 12:25:50.047453 progress 15% (6MB)
58 12:25:50.059870 progress 20% (8MB)
59 12:25:50.072398 progress 25% (10MB)
60 12:25:50.084574 progress 30% (13MB)
61 12:25:50.097393 progress 35% (15MB)
62 12:25:50.109699 progress 40% (17MB)
63 12:25:50.122033 progress 45% (19MB)
64 12:25:50.134306 progress 50% (21MB)
65 12:25:50.146564 progress 55% (24MB)
66 12:25:50.159221 progress 60% (26MB)
67 12:25:50.171857 progress 65% (28MB)
68 12:25:50.184192 progress 70% (30MB)
69 12:25:50.196645 progress 75% (32MB)
70 12:25:50.208784 progress 80% (34MB)
71 12:25:50.221378 progress 85% (37MB)
72 12:25:50.233913 progress 90% (39MB)
73 12:25:50.246063 progress 95% (41MB)
74 12:25:50.258850 progress 100% (43MB)
75 12:25:50.259037 43MB downloaded in 0.25s (174.54MB/s)
76 12:25:50.259254 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:25:50.259668 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:25:50.259807 start: 1.3 download-retry (timeout 00:09:56) [common]
80 12:25:50.259914 start: 1.3.1 http-download (timeout 00:09:56) [common]
81 12:25:50.260070 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:25:50.260177 saving as /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/dtb/mt8192-asurada-spherion-r0.dtb
83 12:25:50.260276 total size: 46924 (0MB)
84 12:25:50.260381 No compression specified
85 12:25:50.262133 progress 69% (0MB)
86 12:25:50.262451 progress 100% (0MB)
87 12:25:50.262660 0MB downloaded in 0.00s (18.80MB/s)
88 12:25:50.262850 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:25:50.263257 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:25:50.263382 start: 1.4 download-retry (timeout 00:09:56) [common]
92 12:25:50.263521 start: 1.4.1 http-download (timeout 00:09:56) [common]
93 12:25:50.263678 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 12:25:50.263779 saving as /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/nfsrootfs/full.rootfs.tar
95 12:25:50.263891 total size: 195125384 (186MB)
96 12:25:50.263986 Using unxz to decompress xz
97 12:25:50.268468 progress 0% (0MB)
98 12:25:50.854324 progress 5% (9MB)
99 12:25:51.388556 progress 10% (18MB)
100 12:25:52.031650 progress 15% (27MB)
101 12:25:52.316327 progress 20% (37MB)
102 12:25:52.808873 progress 25% (46MB)
103 12:25:53.430471 progress 30% (55MB)
104 12:25:54.030347 progress 35% (65MB)
105 12:25:54.638255 progress 40% (74MB)
106 12:25:55.265072 progress 45% (83MB)
107 12:25:55.937014 progress 50% (93MB)
108 12:25:56.589318 progress 55% (102MB)
109 12:25:57.310488 progress 60% (111MB)
110 12:25:57.757979 progress 65% (120MB)
111 12:25:57.842596 progress 70% (130MB)
112 12:25:57.997277 progress 75% (139MB)
113 12:25:58.073353 progress 80% (148MB)
114 12:25:58.126703 progress 85% (158MB)
115 12:25:58.221752 progress 90% (167MB)
116 12:25:58.631239 progress 95% (176MB)
117 12:25:59.228561 progress 100% (186MB)
118 12:25:59.235123 186MB downloaded in 8.97s (20.74MB/s)
119 12:25:59.235431 end: 1.4.1 http-download (duration 00:00:09) [common]
121 12:25:59.235734 end: 1.4 download-retry (duration 00:00:09) [common]
122 12:25:59.235868 start: 1.5 download-retry (timeout 00:09:47) [common]
123 12:25:59.236000 start: 1.5.1 http-download (timeout 00:09:47) [common]
124 12:25:59.236190 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:25:59.236297 saving as /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/modules/modules.tar
126 12:25:59.236401 total size: 8539116 (8MB)
127 12:25:59.236507 Using unxz to decompress xz
128 12:25:59.530808 progress 0% (0MB)
129 12:25:59.552836 progress 5% (0MB)
130 12:25:59.578679 progress 10% (0MB)
131 12:25:59.604084 progress 15% (1MB)
132 12:25:59.633306 progress 20% (1MB)
133 12:25:59.659362 progress 25% (2MB)
134 12:25:59.685722 progress 30% (2MB)
135 12:25:59.711562 progress 35% (2MB)
136 12:25:59.736355 progress 40% (3MB)
137 12:25:59.760571 progress 45% (3MB)
138 12:25:59.785375 progress 50% (4MB)
139 12:25:59.809509 progress 55% (4MB)
140 12:25:59.834942 progress 60% (4MB)
141 12:25:59.860485 progress 65% (5MB)
142 12:25:59.886012 progress 70% (5MB)
143 12:25:59.912898 progress 75% (6MB)
144 12:25:59.944728 progress 80% (6MB)
145 12:25:59.970234 progress 85% (6MB)
146 12:25:59.995246 progress 90% (7MB)
147 12:26:00.020143 progress 95% (7MB)
148 12:26:00.046067 progress 100% (8MB)
149 12:26:00.051838 8MB downloaded in 0.82s (9.99MB/s)
150 12:26:00.052116 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:26:00.052420 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:26:00.052556 start: 1.6 prepare-tftp-overlay (timeout 00:09:47) [common]
154 12:26:00.052697 start: 1.6.1 extract-nfsrootfs (timeout 00:09:47) [common]
155 12:26:04.034360 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10605755/extract-nfsrootfs-o4xbtzwu
156 12:26:04.034602 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 12:26:04.034752 start: 1.6.2 lava-overlay (timeout 00:09:43) [common]
158 12:26:04.034950 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5
159 12:26:04.035133 makedir: /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin
160 12:26:04.035262 makedir: /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/tests
161 12:26:04.035382 makedir: /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/results
162 12:26:04.035515 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-add-keys
163 12:26:04.035690 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-add-sources
164 12:26:04.035836 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-background-process-start
165 12:26:04.035971 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-background-process-stop
166 12:26:04.036114 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-common-functions
167 12:26:04.036273 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-echo-ipv4
168 12:26:04.036481 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-install-packages
169 12:26:04.036639 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-installed-packages
170 12:26:04.036784 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-os-build
171 12:26:04.037024 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-probe-channel
172 12:26:04.037210 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-probe-ip
173 12:26:04.037333 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-target-ip
174 12:26:04.037503 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-target-mac
175 12:26:04.037626 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-target-storage
176 12:26:04.037807 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-test-case
177 12:26:04.037963 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-test-event
178 12:26:04.038087 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-test-feedback
179 12:26:04.038237 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-test-raise
180 12:26:04.038463 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-test-reference
181 12:26:04.038587 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-test-runner
182 12:26:04.038719 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-test-set
183 12:26:04.038862 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-test-shell
184 12:26:04.038986 Updating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-add-keys (debian)
185 12:26:04.039136 Updating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-add-sources (debian)
186 12:26:04.039280 Updating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-install-packages (debian)
187 12:26:04.039424 Updating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-installed-packages (debian)
188 12:26:04.039564 Updating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/bin/lava-os-build (debian)
189 12:26:04.039688 Creating /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/environment
190 12:26:04.039789 LAVA metadata
191 12:26:04.039859 - LAVA_JOB_ID=10605755
192 12:26:04.039927 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:26:04.040027 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:43) [common]
194 12:26:04.040097 skipped lava-vland-overlay
195 12:26:04.040177 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:26:04.040256 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:43) [common]
197 12:26:04.040321 skipped lava-multinode-overlay
198 12:26:04.040394 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:26:04.040475 start: 1.6.2.3 test-definition (timeout 00:09:43) [common]
200 12:26:04.040553 Loading test definitions
201 12:26:04.040641 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:43) [common]
202 12:26:04.040715 Using /lava-10605755 at stage 0
203 12:26:04.041035 uuid=10605755_1.6.2.3.1 testdef=None
204 12:26:04.041130 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:26:04.041218 start: 1.6.2.3.2 test-overlay (timeout 00:09:43) [common]
206 12:26:04.041669 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:26:04.041900 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:43) [common]
209 12:26:04.042458 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:26:04.042702 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:43) [common]
212 12:26:04.043247 runner path: /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/0/tests/0_timesync-off test_uuid 10605755_1.6.2.3.1
213 12:26:04.043405 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:26:04.043634 start: 1.6.2.3.5 git-repo-action (timeout 00:09:43) [common]
216 12:26:04.043707 Using /lava-10605755 at stage 0
217 12:26:04.043810 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:26:04.043888 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/0/tests/1_kselftest-alsa'
219 12:26:09.937855 Running '/usr/bin/git checkout kernelci.org
220 12:26:10.081597 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 12:26:10.082321 uuid=10605755_1.6.2.3.5 testdef=None
222 12:26:10.082484 end: 1.6.2.3.5 git-repo-action (duration 00:00:06) [common]
224 12:26:10.082740 start: 1.6.2.3.6 test-overlay (timeout 00:09:37) [common]
225 12:26:10.083504 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:26:10.083761 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:37) [common]
228 12:26:10.084740 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:26:10.085032 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:37) [common]
231 12:26:10.085988 runner path: /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/0/tests/1_kselftest-alsa test_uuid 10605755_1.6.2.3.5
232 12:26:10.086083 BOARD='mt8192-asurada-spherion-r0'
233 12:26:10.086154 BRANCH='cip'
234 12:26:10.086218 SKIPFILE='/dev/null'
235 12:26:10.086287 SKIP_INSTALL='True'
236 12:26:10.086350 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:26:10.086410 TST_CASENAME=''
238 12:26:10.086469 TST_CMDFILES='alsa'
239 12:26:10.086615 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:26:10.086825 Creating lava-test-runner.conf files
242 12:26:10.086894 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605755/lava-overlay-c1ijlvr5/lava-10605755/0 for stage 0
243 12:26:10.086990 - 0_timesync-off
244 12:26:10.087063 - 1_kselftest-alsa
245 12:26:10.087161 end: 1.6.2.3 test-definition (duration 00:00:06) [common]
246 12:26:10.087252 start: 1.6.2.4 compress-overlay (timeout 00:09:37) [common]
247 12:26:17.766236 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 12:26:17.766407 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:29) [common]
249 12:26:17.766541 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:26:17.766651 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
251 12:26:17.766747 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:29) [common]
252 12:26:17.936999 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:26:17.937385 start: 1.6.4 extract-modules (timeout 00:09:29) [common]
254 12:26:17.937527 extracting modules file /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605755/extract-nfsrootfs-o4xbtzwu
255 12:26:18.192127 extracting modules file /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605755/extract-overlay-ramdisk-sg3r52ta/ramdisk
256 12:26:18.475597 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 12:26:18.475842 start: 1.6.5 apply-overlay-tftp (timeout 00:09:28) [common]
258 12:26:18.475967 [common] Applying overlay to NFS
259 12:26:18.476057 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605755/compress-overlay-y21mquhm/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605755/extract-nfsrootfs-o4xbtzwu
260 12:26:19.506718 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:26:19.506928 start: 1.6.6 configure-preseed-file (timeout 00:09:27) [common]
262 12:26:19.507056 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:26:19.507183 start: 1.6.7 compress-ramdisk (timeout 00:09:27) [common]
264 12:26:19.507305 Building ramdisk /var/lib/lava/dispatcher/tmp/10605755/extract-overlay-ramdisk-sg3r52ta/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605755/extract-overlay-ramdisk-sg3r52ta/ramdisk
265 12:26:19.804931 >> 128929 blocks
266 12:26:21.887130 rename /var/lib/lava/dispatcher/tmp/10605755/extract-overlay-ramdisk-sg3r52ta/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/ramdisk/ramdisk.cpio.gz
267 12:26:21.887812 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:26:21.887981 start: 1.6.8 prepare-kernel (timeout 00:09:25) [common]
269 12:26:21.888093 start: 1.6.8.1 prepare-fit (timeout 00:09:25) [common]
270 12:26:21.888201 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/kernel/Image'
271 12:26:34.155324 Returned 0 in 12 seconds
272 12:26:34.255946 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/kernel/image.itb
273 12:26:34.568269 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:26:34.568648 output: Created: Tue Jun 6 13:26:34 2023
275 12:26:34.568792 output: Image 0 (kernel-1)
276 12:26:34.568904 output: Description:
277 12:26:34.568998 output: Created: Tue Jun 6 13:26:34 2023
278 12:26:34.569089 output: Type: Kernel Image
279 12:26:34.569172 output: Compression: lzma compressed
280 12:26:34.569234 output: Data Size: 10086749 Bytes = 9850.34 KiB = 9.62 MiB
281 12:26:34.569295 output: Architecture: AArch64
282 12:26:34.569356 output: OS: Linux
283 12:26:34.569414 output: Load Address: 0x00000000
284 12:26:34.569472 output: Entry Point: 0x00000000
285 12:26:34.569542 output: Hash algo: crc32
286 12:26:34.569600 output: Hash value: a26c3f91
287 12:26:34.569654 output: Image 1 (fdt-1)
288 12:26:34.569708 output: Description: mt8192-asurada-spherion-r0
289 12:26:34.569765 output: Created: Tue Jun 6 13:26:34 2023
290 12:26:34.569820 output: Type: Flat Device Tree
291 12:26:34.569888 output: Compression: uncompressed
292 12:26:34.569945 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 12:26:34.570000 output: Architecture: AArch64
294 12:26:34.570054 output: Hash algo: crc32
295 12:26:34.570108 output: Hash value: 1df858fa
296 12:26:34.570161 output: Image 2 (ramdisk-1)
297 12:26:34.570219 output: Description: unavailable
298 12:26:34.570278 output: Created: Tue Jun 6 13:26:34 2023
299 12:26:34.570335 output: Type: RAMDisk Image
300 12:26:34.570390 output: Compression: Unknown Compression
301 12:26:34.570443 output: Data Size: 18605545 Bytes = 18169.48 KiB = 17.74 MiB
302 12:26:34.570502 output: Architecture: AArch64
303 12:26:34.570555 output: OS: Linux
304 12:26:34.570609 output: Load Address: unavailable
305 12:26:34.570689 output: Entry Point: unavailable
306 12:26:34.570778 output: Hash algo: crc32
307 12:26:34.570865 output: Hash value: c7679049
308 12:26:34.570949 output: Default Configuration: 'conf-1'
309 12:26:34.571035 output: Configuration 0 (conf-1)
310 12:26:34.571118 output: Description: mt8192-asurada-spherion-r0
311 12:26:34.571201 output: Kernel: kernel-1
312 12:26:34.571296 output: Init Ramdisk: ramdisk-1
313 12:26:34.571382 output: FDT: fdt-1
314 12:26:34.571465 output: Loadables: kernel-1
315 12:26:34.571550 output:
316 12:26:34.571775 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 12:26:34.571901 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 12:26:34.572010 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 12:26:34.572143 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:12) [common]
320 12:26:34.572252 No LXC device requested
321 12:26:34.572362 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:26:34.572481 start: 1.8 deploy-device-env (timeout 00:09:12) [common]
323 12:26:34.572590 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:26:34.572692 Checking files for TFTP limit of 4294967296 bytes.
325 12:26:34.573252 end: 1 tftp-deploy (duration 00:00:48) [common]
326 12:26:34.573386 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:26:34.573512 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:26:34.573688 substitutions:
329 12:26:34.573783 - {DTB}: 10605755/tftp-deploy-d9nntriy/dtb/mt8192-asurada-spherion-r0.dtb
330 12:26:34.573882 - {INITRD}: 10605755/tftp-deploy-d9nntriy/ramdisk/ramdisk.cpio.gz
331 12:26:34.573974 - {KERNEL}: 10605755/tftp-deploy-d9nntriy/kernel/Image
332 12:26:34.574065 - {LAVA_MAC}: None
333 12:26:34.574154 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10605755/extract-nfsrootfs-o4xbtzwu
334 12:26:34.574243 - {NFS_SERVER_IP}: 192.168.201.1
335 12:26:34.574331 - {PRESEED_CONFIG}: None
336 12:26:34.574418 - {PRESEED_LOCAL}: None
337 12:26:34.574504 - {RAMDISK}: 10605755/tftp-deploy-d9nntriy/ramdisk/ramdisk.cpio.gz
338 12:26:34.574592 - {ROOT_PART}: None
339 12:26:34.574683 - {ROOT}: None
340 12:26:34.574771 - {SERVER_IP}: 192.168.201.1
341 12:26:34.574856 - {TEE}: None
342 12:26:34.574942 Parsed boot commands:
343 12:26:34.575027 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:26:34.575243 Parsed boot commands: tftpboot 192.168.201.1 10605755/tftp-deploy-d9nntriy/kernel/image.itb 10605755/tftp-deploy-d9nntriy/kernel/cmdline
345 12:26:34.575367 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:26:34.575488 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:26:34.575615 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:26:34.575739 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:26:34.575839 Not connected, no need to disconnect.
350 12:26:34.575943 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:26:34.576049 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:26:34.576151 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
353 12:26:34.579624 Setting prompt string to ['lava-test: # ']
354 12:26:34.579991 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:26:34.580136 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:26:34.580267 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:26:34.580389 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:26:34.580712 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 12:26:39.711942 >> Command sent successfully.
360 12:26:39.714255 Returned 0 in 5 seconds
361 12:26:39.814667 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:26:39.815000 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:26:39.815103 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:26:39.815192 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:26:39.815264 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:26:39.815338 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:26:39.815594 [Enter `^Ec?' for help]
369 12:26:39.986589
370 12:26:39.986757
371 12:26:39.986828 F0: 102B 0000
372 12:26:39.986893
373 12:26:39.986954 F3: 1001 0000 [0200]
374 12:26:39.987032
375 12:26:39.990468 F3: 1001 0000
376 12:26:39.990553
377 12:26:39.990615 F7: 102D 0000
378 12:26:39.990674
379 12:26:39.993740 F1: 0000 0000
380 12:26:39.993825
381 12:26:39.993897 V0: 0000 0000 [0001]
382 12:26:39.993971
383 12:26:39.994031 00: 0007 8000
384 12:26:39.994092
385 12:26:39.997623 01: 0000 0000
386 12:26:39.997709
387 12:26:39.997776 BP: 0C00 0209 [0000]
388 12:26:39.997857
389 12:26:40.001014 G0: 1182 0000
390 12:26:40.001099
391 12:26:40.001165 EC: 0000 0021 [4000]
392 12:26:40.001226
393 12:26:40.004354 S7: 0000 0000 [0000]
394 12:26:40.004497
395 12:26:40.004624 CC: 0000 0000 [0001]
396 12:26:40.004718
397 12:26:40.007700 T0: 0000 0040 [010F]
398 12:26:40.007785
399 12:26:40.007850 Jump to BL
400 12:26:40.007912
401 12:26:40.033418
402 12:26:40.033511
403 12:26:40.033579
404 12:26:40.040702 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:26:40.043911 ARM64: Exception handlers installed.
406 12:26:40.047111 ARM64: Testing exception
407 12:26:40.050359 ARM64: Done test exception
408 12:26:40.057429 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:26:40.068534 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:26:40.074955 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:26:40.085013 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:26:40.091524 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:26:40.097799 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:26:40.109595 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:26:40.116812 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:26:40.136067 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:26:40.139371 WDT: Last reset was cold boot
418 12:26:40.142688 SPI1(PAD0) initialized at 2873684 Hz
419 12:26:40.146282 SPI5(PAD0) initialized at 992727 Hz
420 12:26:40.149444 VBOOT: Loading verstage.
421 12:26:40.156162 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:26:40.159718 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:26:40.162876 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:26:40.166069 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:26:40.173755 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:26:40.179967 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:26:40.191011 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:26:40.191099
429 12:26:40.191168
430 12:26:40.201437 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:26:40.204665 ARM64: Exception handlers installed.
432 12:26:40.208117 ARM64: Testing exception
433 12:26:40.208202 ARM64: Done test exception
434 12:26:40.214705 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:26:40.217955 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:26:40.232026 Probing TPM: . done!
437 12:26:40.232112 TPM ready after 0 ms
438 12:26:40.238937 Connected to device vid:did:rid of 1ae0:0028:00
439 12:26:40.245872 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 12:26:40.303967 Initialized TPM device CR50 revision 0
441 12:26:40.315137 tlcl_send_startup: Startup return code is 0
442 12:26:40.315246 TPM: setup succeeded
443 12:26:40.326472 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:26:40.335491 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:26:40.342375 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:26:40.354421 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:26:40.357581 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:26:40.367599 in-header: 03 07 00 00 08 00 00 00
449 12:26:40.371348 in-data: aa e4 47 04 13 02 00 00
450 12:26:40.374828 Chrome EC: UHEPI supported
451 12:26:40.381920 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:26:40.385743 in-header: 03 ad 00 00 08 00 00 00
453 12:26:40.389612 in-data: 00 20 20 08 00 00 00 00
454 12:26:40.389697 Phase 1
455 12:26:40.392974 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:26:40.400491 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:26:40.404266 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:26:40.407653 Recovery requested (1009000e)
459 12:26:40.417453 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:26:40.423729 tlcl_extend: response is 0
461 12:26:40.433703 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:26:40.439695 tlcl_extend: response is 0
463 12:26:40.446605 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:26:40.467039 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 12:26:40.473787 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:26:40.473875
467 12:26:40.473943
468 12:26:40.483788 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:26:40.487664 ARM64: Exception handlers installed.
470 12:26:40.487753 ARM64: Testing exception
471 12:26:40.490970 ARM64: Done test exception
472 12:26:40.512483 pmic_efuse_setting: Set efuses in 11 msecs
473 12:26:40.515852 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:26:40.523134 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:26:40.526505 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:26:40.529326 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:26:40.535870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:26:40.539943 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:26:40.547405 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:26:40.550711 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:26:40.554481 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:26:40.558231 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:26:40.565381 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:26:40.568644 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:26:40.575358 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:26:40.578792 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:26:40.585143 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:26:40.588743 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:26:40.595491 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:26:40.602931 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:26:40.606672 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:26:40.613658 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:26:40.616745 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:26:40.623915 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:26:40.631038 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:26:40.634309 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:26:40.640536 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:26:40.644285 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:26:40.650754 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:26:40.657203 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:26:40.660558 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:26:40.667337 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:26:40.670649 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:26:40.677336 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:26:40.680373 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:26:40.687011 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:26:40.690773 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:26:40.697181 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:26:40.700369 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:26:40.707286 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:26:40.710376 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:26:40.717195 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:26:40.720456 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:26:40.723828 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:26:40.727119 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:26:40.734218 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:26:40.738063 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:26:40.741246 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:26:40.744686 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:26:40.751337 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:26:40.754516 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:26:40.757903 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:26:40.764603 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:26:40.767942 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:26:40.774629 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:26:40.784444 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:26:40.788126 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:26:40.797839 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:26:40.804566 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:26:40.807906 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:26:40.814325 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:26:40.817903 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:26:40.825047 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 12:26:40.831613 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:26:40.834899 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 12:26:40.838098 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:26:40.849913 [RTC]rtc_get_frequency_meter,154: input=15, output=773
538 12:26:40.858874 [RTC]rtc_get_frequency_meter,154: input=23, output=958
539 12:26:40.868564 [RTC]rtc_get_frequency_meter,154: input=19, output=864
540 12:26:40.878185 [RTC]rtc_get_frequency_meter,154: input=17, output=817
541 12:26:40.887506 [RTC]rtc_get_frequency_meter,154: input=16, output=794
542 12:26:40.890770 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 12:26:40.898028 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 12:26:40.901582 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
545 12:26:40.905737 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 12:26:40.909276 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
547 12:26:40.913099 ADC[4]: Raw value=903614 ID=7
548 12:26:40.913185 ADC[3]: Raw value=213179 ID=1
549 12:26:40.916691 RAM Code: 0x71
550 12:26:40.920169 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 12:26:40.927153 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 12:26:40.933883 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 12:26:40.939997 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 12:26:40.943374 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 12:26:40.946716 in-header: 03 07 00 00 08 00 00 00
556 12:26:40.949985 in-data: aa e4 47 04 13 02 00 00
557 12:26:40.953706 Chrome EC: UHEPI supported
558 12:26:40.960269 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 12:26:40.963554 in-header: 03 ed 00 00 08 00 00 00
560 12:26:40.966691 in-data: 80 20 60 08 00 00 00 00
561 12:26:40.970150 MRC: failed to locate region type 0.
562 12:26:40.977088 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 12:26:40.980901 DRAM-K: Running full calibration
564 12:26:40.984706 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 12:26:40.988495 header.status = 0x0
566 12:26:40.991835 header.version = 0x6 (expected: 0x6)
567 12:26:40.995774 header.size = 0xd00 (expected: 0xd00)
568 12:26:40.995893 header.flags = 0x0
569 12:26:41.002305 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 12:26:41.019240 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
571 12:26:41.025888 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 12:26:41.029252 dram_init: ddr_geometry: 2
573 12:26:41.032575 [EMI] MDL number = 2
574 12:26:41.032662 [EMI] Get MDL freq = 0
575 12:26:41.035825 dram_init: ddr_type: 0
576 12:26:41.035909 is_discrete_lpddr4: 1
577 12:26:41.039293 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 12:26:41.039382
579 12:26:41.039449
580 12:26:41.042654 [Bian_co] ETT version 0.0.0.1
581 12:26:41.049260 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 12:26:41.049345
583 12:26:41.052673 dramc_set_vcore_voltage set vcore to 650000
584 12:26:41.052759 Read voltage for 800, 4
585 12:26:41.055995 Vio18 = 0
586 12:26:41.056079 Vcore = 650000
587 12:26:41.056146 Vdram = 0
588 12:26:41.059394 Vddq = 0
589 12:26:41.059478 Vmddr = 0
590 12:26:41.062761 dram_init: config_dvfs: 1
591 12:26:41.065922 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 12:26:41.072396 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 12:26:41.075856 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
594 12:26:41.079222 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
595 12:26:41.082585 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 12:26:41.085888 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 12:26:41.089177 MEM_TYPE=3, freq_sel=18
598 12:26:41.092468 sv_algorithm_assistance_LP4_1600
599 12:26:41.095916 ============ PULL DRAM RESETB DOWN ============
600 12:26:41.099265 ========== PULL DRAM RESETB DOWN end =========
601 12:26:41.105735 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 12:26:41.108967 ===================================
603 12:26:41.112264 LPDDR4 DRAM CONFIGURATION
604 12:26:41.115414 ===================================
605 12:26:41.115514 EX_ROW_EN[0] = 0x0
606 12:26:41.118785 EX_ROW_EN[1] = 0x0
607 12:26:41.118870 LP4Y_EN = 0x0
608 12:26:41.122366 WORK_FSP = 0x0
609 12:26:41.122451 WL = 0x2
610 12:26:41.125847 RL = 0x2
611 12:26:41.125931 BL = 0x2
612 12:26:41.128821 RPST = 0x0
613 12:26:41.128907 RD_PRE = 0x0
614 12:26:41.132323 WR_PRE = 0x1
615 12:26:41.132408 WR_PST = 0x0
616 12:26:41.135560 DBI_WR = 0x0
617 12:26:41.135646 DBI_RD = 0x0
618 12:26:41.138794 OTF = 0x1
619 12:26:41.142202 ===================================
620 12:26:41.145424 ===================================
621 12:26:41.145509 ANA top config
622 12:26:41.148624 ===================================
623 12:26:41.152403 DLL_ASYNC_EN = 0
624 12:26:41.155776 ALL_SLAVE_EN = 1
625 12:26:41.158520 NEW_RANK_MODE = 1
626 12:26:41.162195 DLL_IDLE_MODE = 1
627 12:26:41.162280 LP45_APHY_COMB_EN = 1
628 12:26:41.165680 TX_ODT_DIS = 1
629 12:26:41.168821 NEW_8X_MODE = 1
630 12:26:41.172028 ===================================
631 12:26:41.175416 ===================================
632 12:26:41.178565 data_rate = 1600
633 12:26:41.182205 CKR = 1
634 12:26:41.182289 DQ_P2S_RATIO = 8
635 12:26:41.185417 ===================================
636 12:26:41.188732 CA_P2S_RATIO = 8
637 12:26:41.192112 DQ_CA_OPEN = 0
638 12:26:41.195401 DQ_SEMI_OPEN = 0
639 12:26:41.198766 CA_SEMI_OPEN = 0
640 12:26:41.198851 CA_FULL_RATE = 0
641 12:26:41.202167 DQ_CKDIV4_EN = 1
642 12:26:41.205436 CA_CKDIV4_EN = 1
643 12:26:41.208607 CA_PREDIV_EN = 0
644 12:26:41.211940 PH8_DLY = 0
645 12:26:41.215216 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 12:26:41.215302 DQ_AAMCK_DIV = 4
647 12:26:41.218429 CA_AAMCK_DIV = 4
648 12:26:41.221914 CA_ADMCK_DIV = 4
649 12:26:41.225132 DQ_TRACK_CA_EN = 0
650 12:26:41.228657 CA_PICK = 800
651 12:26:41.232197 CA_MCKIO = 800
652 12:26:41.235275 MCKIO_SEMI = 0
653 12:26:41.235375 PLL_FREQ = 3068
654 12:26:41.238412 DQ_UI_PI_RATIO = 32
655 12:26:41.241826 CA_UI_PI_RATIO = 0
656 12:26:41.244985 ===================================
657 12:26:41.248680 ===================================
658 12:26:41.251972 memory_type:LPDDR4
659 12:26:41.252055 GP_NUM : 10
660 12:26:41.255834 SRAM_EN : 1
661 12:26:41.255918 MD32_EN : 0
662 12:26:41.259141 ===================================
663 12:26:41.262467 [ANA_INIT] >>>>>>>>>>>>>>
664 12:26:41.265856 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 12:26:41.269623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 12:26:41.272911 ===================================
667 12:26:41.276642 data_rate = 1600,PCW = 0X7600
668 12:26:41.279938 ===================================
669 12:26:41.283585 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 12:26:41.287348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 12:26:41.294615 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 12:26:41.298466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 12:26:41.302256 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 12:26:41.305591 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 12:26:41.305676 [ANA_INIT] flow start
676 12:26:41.309449 [ANA_INIT] PLL >>>>>>>>
677 12:26:41.312609 [ANA_INIT] PLL <<<<<<<<
678 12:26:41.312720 [ANA_INIT] MIDPI >>>>>>>>
679 12:26:41.316382 [ANA_INIT] MIDPI <<<<<<<<
680 12:26:41.320256 [ANA_INIT] DLL >>>>>>>>
681 12:26:41.320341 [ANA_INIT] flow end
682 12:26:41.324014 ============ LP4 DIFF to SE enter ============
683 12:26:41.327655 ============ LP4 DIFF to SE exit ============
684 12:26:41.331671 [ANA_INIT] <<<<<<<<<<<<<
685 12:26:41.335252 [Flow] Enable top DCM control >>>>>
686 12:26:41.338897 [Flow] Enable top DCM control <<<<<
687 12:26:41.338982 Enable DLL master slave shuffle
688 12:26:41.346469 ==============================================================
689 12:26:41.346555 Gating Mode config
690 12:26:41.353792 ==============================================================
691 12:26:41.353878 Config description:
692 12:26:41.364595 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 12:26:41.371818 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 12:26:41.375645 SELPH_MODE 0: By rank 1: By Phase
695 12:26:41.383494 ==============================================================
696 12:26:41.383616 GAT_TRACK_EN = 1
697 12:26:41.386678 RX_GATING_MODE = 2
698 12:26:41.390537 RX_GATING_TRACK_MODE = 2
699 12:26:41.394343 SELPH_MODE = 1
700 12:26:41.398184 PICG_EARLY_EN = 1
701 12:26:41.398288 VALID_LAT_VALUE = 1
702 12:26:41.405337 ==============================================================
703 12:26:41.409208 Enter into Gating configuration >>>>
704 12:26:41.412959 Exit from Gating configuration <<<<
705 12:26:41.416685 Enter into DVFS_PRE_config >>>>>
706 12:26:41.427666 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 12:26:41.427775 Exit from DVFS_PRE_config <<<<<
708 12:26:41.431435 Enter into PICG configuration >>>>
709 12:26:41.434696 Exit from PICG configuration <<<<
710 12:26:41.438539 [RX_INPUT] configuration >>>>>
711 12:26:41.442111 [RX_INPUT] configuration <<<<<
712 12:26:41.445828 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 12:26:41.452951 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 12:26:41.456754 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 12:26:41.464491 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 12:26:41.471765 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 12:26:41.475651 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 12:26:41.478985 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 12:26:41.482717 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 12:26:41.490105 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 12:26:41.494363 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 12:26:41.497715 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 12:26:41.501691 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 12:26:41.505035 ===================================
725 12:26:41.508813 LPDDR4 DRAM CONFIGURATION
726 12:26:41.508901 ===================================
727 12:26:41.512279 EX_ROW_EN[0] = 0x0
728 12:26:41.516018 EX_ROW_EN[1] = 0x0
729 12:26:41.516106 LP4Y_EN = 0x0
730 12:26:41.516192 WORK_FSP = 0x0
731 12:26:41.520018 WL = 0x2
732 12:26:41.520105 RL = 0x2
733 12:26:41.523463 BL = 0x2
734 12:26:41.523550 RPST = 0x0
735 12:26:41.527242 RD_PRE = 0x0
736 12:26:41.527374 WR_PRE = 0x1
737 12:26:41.531032 WR_PST = 0x0
738 12:26:41.531120 DBI_WR = 0x0
739 12:26:41.534831 DBI_RD = 0x0
740 12:26:41.534918 OTF = 0x1
741 12:26:41.538115 ===================================
742 12:26:41.541455 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 12:26:41.544946 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 12:26:41.551789 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 12:26:41.554768 ===================================
746 12:26:41.554856 LPDDR4 DRAM CONFIGURATION
747 12:26:41.558377 ===================================
748 12:26:41.561795 EX_ROW_EN[0] = 0x10
749 12:26:41.565091 EX_ROW_EN[1] = 0x0
750 12:26:41.565179 LP4Y_EN = 0x0
751 12:26:41.568415 WORK_FSP = 0x0
752 12:26:41.568503 WL = 0x2
753 12:26:41.571705 RL = 0x2
754 12:26:41.571793 BL = 0x2
755 12:26:41.575042 RPST = 0x0
756 12:26:41.575129 RD_PRE = 0x0
757 12:26:41.578350 WR_PRE = 0x1
758 12:26:41.578437 WR_PST = 0x0
759 12:26:41.581541 DBI_WR = 0x0
760 12:26:41.581630 DBI_RD = 0x0
761 12:26:41.584812 OTF = 0x1
762 12:26:41.588047 ===================================
763 12:26:41.595027 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 12:26:41.598360 nWR fixed to 40
765 12:26:41.598460 [ModeRegInit_LP4] CH0 RK0
766 12:26:41.601653 [ModeRegInit_LP4] CH0 RK1
767 12:26:41.605035 [ModeRegInit_LP4] CH1 RK0
768 12:26:41.607953 [ModeRegInit_LP4] CH1 RK1
769 12:26:41.608040 match AC timing 13
770 12:26:41.614545 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 12:26:41.617917 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 12:26:41.621688 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 12:26:41.628076 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 12:26:41.631384 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 12:26:41.631469 [EMI DOE] emi_dcm 0
776 12:26:41.637967 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 12:26:41.638052 ==
778 12:26:41.641319 Dram Type= 6, Freq= 0, CH_0, rank 0
779 12:26:41.644597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 12:26:41.644683 ==
781 12:26:41.651411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 12:26:41.654522 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 12:26:41.665175 [CA 0] Center 37 (7~68) winsize 62
784 12:26:41.668217 [CA 1] Center 38 (7~69) winsize 63
785 12:26:41.671588 [CA 2] Center 35 (5~66) winsize 62
786 12:26:41.674955 [CA 3] Center 35 (5~66) winsize 62
787 12:26:41.678227 [CA 4] Center 34 (4~65) winsize 62
788 12:26:41.681580 [CA 5] Center 33 (3~64) winsize 62
789 12:26:41.681668
790 12:26:41.684896 [CmdBusTrainingLP45] Vref(ca) range 1: 32
791 12:26:41.684981
792 12:26:41.688263 [CATrainingPosCal] consider 1 rank data
793 12:26:41.691932 u2DelayCellTimex100 = 270/100 ps
794 12:26:41.695121 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
795 12:26:41.698376 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 12:26:41.705076 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 12:26:41.708348 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
798 12:26:41.711720 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 12:26:41.714981 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 12:26:41.715066
801 12:26:41.718358 CA PerBit enable=1, Macro0, CA PI delay=33
802 12:26:41.718443
803 12:26:41.721630 [CBTSetCACLKResult] CA Dly = 33
804 12:26:41.721715 CS Dly: 6 (0~37)
805 12:26:41.725281 ==
806 12:26:41.728455 Dram Type= 6, Freq= 0, CH_0, rank 1
807 12:26:41.731667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 12:26:41.731753 ==
809 12:26:41.734938 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 12:26:41.741495 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 12:26:41.751464 [CA 0] Center 38 (7~69) winsize 63
812 12:26:41.755155 [CA 1] Center 38 (7~69) winsize 63
813 12:26:41.758231 [CA 2] Center 35 (5~66) winsize 62
814 12:26:41.761568 [CA 3] Center 35 (5~66) winsize 62
815 12:26:41.765122 [CA 4] Center 35 (4~66) winsize 63
816 12:26:41.768288 [CA 5] Center 34 (4~64) winsize 61
817 12:26:41.768374
818 12:26:41.771767 [CmdBusTrainingLP45] Vref(ca) range 1: 30
819 12:26:41.771852
820 12:26:41.775276 [CATrainingPosCal] consider 2 rank data
821 12:26:41.778638 u2DelayCellTimex100 = 270/100 ps
822 12:26:41.781968 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
823 12:26:41.785307 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 12:26:41.791883 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
825 12:26:41.795130 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 12:26:41.798425 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 12:26:41.801718 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 12:26:41.801803
829 12:26:41.804888 CA PerBit enable=1, Macro0, CA PI delay=34
830 12:26:41.804973
831 12:26:41.808205 [CBTSetCACLKResult] CA Dly = 34
832 12:26:41.808291 CS Dly: 6 (0~38)
833 12:26:41.808359
834 12:26:41.811388 ----->DramcWriteLeveling(PI) begin...
835 12:26:41.815105 ==
836 12:26:41.818406 Dram Type= 6, Freq= 0, CH_0, rank 0
837 12:26:41.821749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 12:26:41.821834 ==
839 12:26:41.825075 Write leveling (Byte 0): 30 => 30
840 12:26:41.828386 Write leveling (Byte 1): 29 => 29
841 12:26:41.831443 DramcWriteLeveling(PI) end<-----
842 12:26:41.831527
843 12:26:41.831594 ==
844 12:26:41.834662 Dram Type= 6, Freq= 0, CH_0, rank 0
845 12:26:41.837934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 12:26:41.838072 ==
847 12:26:41.841773 [Gating] SW mode calibration
848 12:26:41.848224 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 12:26:41.851542 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 12:26:41.858029 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
851 12:26:41.861216 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
852 12:26:41.864806 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 12:26:41.871484 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
854 12:26:41.874640 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 12:26:41.878173 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:26:41.884664 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:26:41.888423 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:26:41.891767 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:26:41.895332 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:26:41.902275 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:26:41.905589 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:26:41.909201 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:26:41.915410 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:26:41.919276 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:26:41.922636 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:26:41.925967 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
867 12:26:41.932671 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
868 12:26:41.936300 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
869 12:26:41.939522 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:26:41.946011 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 12:26:41.949219 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 12:26:41.952937 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:26:41.959553 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:26:41.962966 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:26:41.966329 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:26:41.972676 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
877 12:26:41.975792 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
878 12:26:41.979287 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 12:26:41.985984 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 12:26:41.989206 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 12:26:41.992527 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:26:41.999123 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:26:42.002823 0 10 4 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
884 12:26:42.005956 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
885 12:26:42.012472 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 12:26:42.015837 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 12:26:42.019097 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 12:26:42.025771 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 12:26:42.029088 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:26:42.032402 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:26:42.038944 0 11 4 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
892 12:26:42.042625 0 11 8 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
893 12:26:42.045812 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 12:26:42.049087 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 12:26:42.055822 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 12:26:42.058946 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 12:26:42.062371 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:26:42.068923 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:26:42.072194 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
900 12:26:42.077959 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
901 12:26:42.082203 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 12:26:42.085731 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 12:26:42.088709 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 12:26:42.095544 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:26:42.098954 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:26:42.102161 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:26:42.109031 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:26:42.112247 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:26:42.115622 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:26:42.122151 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:26:42.125594 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:26:42.128722 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:26:42.135871 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:26:42.139088 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:26:42.142455 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
916 12:26:42.145736 Total UI for P1: 0, mck2ui 16
917 12:26:42.148757 best dqsien dly found for B0: ( 0, 14, 2)
918 12:26:42.152516 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
919 12:26:42.158732 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 12:26:42.162050 Total UI for P1: 0, mck2ui 16
921 12:26:42.165450 best dqsien dly found for B1: ( 0, 14, 6)
922 12:26:42.168734 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
923 12:26:42.172109 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
924 12:26:42.172202
925 12:26:42.175470 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
926 12:26:42.178920 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
927 12:26:42.182112 [Gating] SW calibration Done
928 12:26:42.182200 ==
929 12:26:42.185327 Dram Type= 6, Freq= 0, CH_0, rank 0
930 12:26:42.188800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 12:26:42.188940 ==
932 12:26:42.191977 RX Vref Scan: 0
933 12:26:42.192066
934 12:26:42.192134 RX Vref 0 -> 0, step: 1
935 12:26:42.195586
936 12:26:42.195672 RX Delay -130 -> 252, step: 16
937 12:26:42.201958 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
938 12:26:42.205316 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 12:26:42.208576 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
940 12:26:42.212146 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
941 12:26:42.215436 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
942 12:26:42.222284 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
943 12:26:42.225637 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
944 12:26:42.228925 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 12:26:42.232175 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 12:26:42.235554 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
947 12:26:42.242185 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
948 12:26:42.245435 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 12:26:42.248697 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
950 12:26:42.251872 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 12:26:42.254967 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 12:26:42.261591 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
953 12:26:42.261724 ==
954 12:26:42.265405 Dram Type= 6, Freq= 0, CH_0, rank 0
955 12:26:42.268704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 12:26:42.268826 ==
957 12:26:42.268895 DQS Delay:
958 12:26:42.272023 DQS0 = 0, DQS1 = 0
959 12:26:42.272108 DQM Delay:
960 12:26:42.274898 DQM0 = 91, DQM1 = 81
961 12:26:42.274982 DQ Delay:
962 12:26:42.278658 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
963 12:26:42.281983 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
964 12:26:42.285313 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
965 12:26:42.288419 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
966 12:26:42.288504
967 12:26:42.288571
968 12:26:42.288635 ==
969 12:26:42.292026 Dram Type= 6, Freq= 0, CH_0, rank 0
970 12:26:42.295068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 12:26:42.298710 ==
972 12:26:42.298799
973 12:26:42.298867
974 12:26:42.298928 TX Vref Scan disable
975 12:26:42.301748 == TX Byte 0 ==
976 12:26:42.305172 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
977 12:26:42.308254 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
978 12:26:42.311761 == TX Byte 1 ==
979 12:26:42.315021 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
980 12:26:42.318646 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
981 12:26:42.321932 ==
982 12:26:42.322018 Dram Type= 6, Freq= 0, CH_0, rank 0
983 12:26:42.328374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 12:26:42.328460 ==
985 12:26:42.340698 TX Vref=22, minBit 8, minWin=26, winSum=436
986 12:26:42.344085 TX Vref=24, minBit 6, minWin=27, winSum=438
987 12:26:42.347361 TX Vref=26, minBit 6, minWin=27, winSum=446
988 12:26:42.350730 TX Vref=28, minBit 6, minWin=27, winSum=450
989 12:26:42.353823 TX Vref=30, minBit 0, minWin=28, winSum=454
990 12:26:42.360622 TX Vref=32, minBit 13, minWin=27, winSum=453
991 12:26:42.363945 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
992 12:26:42.364031
993 12:26:42.367173 Final TX Range 1 Vref 30
994 12:26:42.367258
995 12:26:42.367329 ==
996 12:26:42.370447 Dram Type= 6, Freq= 0, CH_0, rank 0
997 12:26:42.373987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 12:26:42.374073 ==
999 12:26:42.377471
1000 12:26:42.377557
1001 12:26:42.377625 TX Vref Scan disable
1002 12:26:42.380647 == TX Byte 0 ==
1003 12:26:42.383989 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1004 12:26:42.390798 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1005 12:26:42.390883 == TX Byte 1 ==
1006 12:26:42.393906 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1007 12:26:42.400668 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1008 12:26:42.400753
1009 12:26:42.400886 [DATLAT]
1010 12:26:42.400975 Freq=800, CH0 RK0
1011 12:26:42.401078
1012 12:26:42.403823 DATLAT Default: 0xa
1013 12:26:42.403908 0, 0xFFFF, sum = 0
1014 12:26:42.407401 1, 0xFFFF, sum = 0
1015 12:26:42.407487 2, 0xFFFF, sum = 0
1016 12:26:42.410832 3, 0xFFFF, sum = 0
1017 12:26:42.410920 4, 0xFFFF, sum = 0
1018 12:26:42.413820 5, 0xFFFF, sum = 0
1019 12:26:42.417019 6, 0xFFFF, sum = 0
1020 12:26:42.417105 7, 0xFFFF, sum = 0
1021 12:26:42.420673 8, 0xFFFF, sum = 0
1022 12:26:42.420831 9, 0x0, sum = 1
1023 12:26:42.420912 10, 0x0, sum = 2
1024 12:26:42.424114 11, 0x0, sum = 3
1025 12:26:42.424212 12, 0x0, sum = 4
1026 12:26:42.427128 best_step = 10
1027 12:26:42.427236
1028 12:26:42.427330 ==
1029 12:26:42.430892 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 12:26:42.433749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 12:26:42.433858 ==
1032 12:26:42.437058 RX Vref Scan: 1
1033 12:26:42.437160
1034 12:26:42.437228 Set Vref Range= 32 -> 127
1035 12:26:42.437289
1036 12:26:42.440409 RX Vref 32 -> 127, step: 1
1037 12:26:42.440518
1038 12:26:42.443749 RX Delay -95 -> 252, step: 8
1039 12:26:42.443833
1040 12:26:42.447073 Set Vref, RX VrefLevel [Byte0]: 32
1041 12:26:42.450398 [Byte1]: 32
1042 12:26:42.450481
1043 12:26:42.453672 Set Vref, RX VrefLevel [Byte0]: 33
1044 12:26:42.456955 [Byte1]: 33
1045 12:26:42.460931
1046 12:26:42.461049 Set Vref, RX VrefLevel [Byte0]: 34
1047 12:26:42.464309 [Byte1]: 34
1048 12:26:42.468510
1049 12:26:42.468613 Set Vref, RX VrefLevel [Byte0]: 35
1050 12:26:42.471771 [Byte1]: 35
1051 12:26:42.476023
1052 12:26:42.476104 Set Vref, RX VrefLevel [Byte0]: 36
1053 12:26:42.479378 [Byte1]: 36
1054 12:26:42.483612
1055 12:26:42.483695 Set Vref, RX VrefLevel [Byte0]: 37
1056 12:26:42.486849 [Byte1]: 37
1057 12:26:42.491540
1058 12:26:42.491656 Set Vref, RX VrefLevel [Byte0]: 38
1059 12:26:42.494823 [Byte1]: 38
1060 12:26:42.498618
1061 12:26:42.498701 Set Vref, RX VrefLevel [Byte0]: 39
1062 12:26:42.502202 [Byte1]: 39
1063 12:26:42.506231
1064 12:26:42.506313 Set Vref, RX VrefLevel [Byte0]: 40
1065 12:26:42.509741 [Byte1]: 40
1066 12:26:42.514277
1067 12:26:42.514360 Set Vref, RX VrefLevel [Byte0]: 41
1068 12:26:42.517306 [Byte1]: 41
1069 12:26:42.521456
1070 12:26:42.521538 Set Vref, RX VrefLevel [Byte0]: 42
1071 12:26:42.525014 [Byte1]: 42
1072 12:26:42.529266
1073 12:26:42.529353 Set Vref, RX VrefLevel [Byte0]: 43
1074 12:26:42.532498 [Byte1]: 43
1075 12:26:42.536652
1076 12:26:42.536760 Set Vref, RX VrefLevel [Byte0]: 44
1077 12:26:42.540035 [Byte1]: 44
1078 12:26:42.544208
1079 12:26:42.544316 Set Vref, RX VrefLevel [Byte0]: 45
1080 12:26:42.547595 [Byte1]: 45
1081 12:26:42.551943
1082 12:26:42.552029 Set Vref, RX VrefLevel [Byte0]: 46
1083 12:26:42.555669 [Byte1]: 46
1084 12:26:42.559950
1085 12:26:42.560033 Set Vref, RX VrefLevel [Byte0]: 47
1086 12:26:42.563491 [Byte1]: 47
1087 12:26:42.567091
1088 12:26:42.570580 Set Vref, RX VrefLevel [Byte0]: 48
1089 12:26:42.570696 [Byte1]: 48
1090 12:26:42.575349
1091 12:26:42.575423 Set Vref, RX VrefLevel [Byte0]: 49
1092 12:26:42.578291 [Byte1]: 49
1093 12:26:42.582765
1094 12:26:42.582836 Set Vref, RX VrefLevel [Byte0]: 50
1095 12:26:42.586024 [Byte1]: 50
1096 12:26:42.590339
1097 12:26:42.590422 Set Vref, RX VrefLevel [Byte0]: 51
1098 12:26:42.593170 [Byte1]: 51
1099 12:26:42.597539
1100 12:26:42.597621 Set Vref, RX VrefLevel [Byte0]: 52
1101 12:26:42.600903 [Byte1]: 52
1102 12:26:42.605072
1103 12:26:42.605180 Set Vref, RX VrefLevel [Byte0]: 53
1104 12:26:42.608547 [Byte1]: 53
1105 12:26:42.612850
1106 12:26:42.612933 Set Vref, RX VrefLevel [Byte0]: 54
1107 12:26:42.616449 [Byte1]: 54
1108 12:26:42.620612
1109 12:26:42.620695 Set Vref, RX VrefLevel [Byte0]: 55
1110 12:26:42.623632 [Byte1]: 55
1111 12:26:42.628025
1112 12:26:42.628108 Set Vref, RX VrefLevel [Byte0]: 56
1113 12:26:42.631256 [Byte1]: 56
1114 12:26:42.635502
1115 12:26:42.635602 Set Vref, RX VrefLevel [Byte0]: 57
1116 12:26:42.639009 [Byte1]: 57
1117 12:26:42.643285
1118 12:26:42.643368 Set Vref, RX VrefLevel [Byte0]: 58
1119 12:26:42.646610 [Byte1]: 58
1120 12:26:42.650857
1121 12:26:42.650940 Set Vref, RX VrefLevel [Byte0]: 59
1122 12:26:42.654054 [Byte1]: 59
1123 12:26:42.658320
1124 12:26:42.658403 Set Vref, RX VrefLevel [Byte0]: 60
1125 12:26:42.661553 [Byte1]: 60
1126 12:26:42.665749
1127 12:26:42.669301 Set Vref, RX VrefLevel [Byte0]: 61
1128 12:26:42.669384 [Byte1]: 61
1129 12:26:42.673492
1130 12:26:42.673579 Set Vref, RX VrefLevel [Byte0]: 62
1131 12:26:42.676754 [Byte1]: 62
1132 12:26:42.681099
1133 12:26:42.681182 Set Vref, RX VrefLevel [Byte0]: 63
1134 12:26:42.684493 [Byte1]: 63
1135 12:26:42.688841
1136 12:26:42.688925 Set Vref, RX VrefLevel [Byte0]: 64
1137 12:26:42.692127 [Byte1]: 64
1138 12:26:42.696386
1139 12:26:42.696495 Set Vref, RX VrefLevel [Byte0]: 65
1140 12:26:42.702594 [Byte1]: 65
1141 12:26:42.702677
1142 12:26:42.705895 Set Vref, RX VrefLevel [Byte0]: 66
1143 12:26:42.709629 [Byte1]: 66
1144 12:26:42.709738
1145 12:26:42.713002 Set Vref, RX VrefLevel [Byte0]: 67
1146 12:26:42.716154 [Byte1]: 67
1147 12:26:42.716236
1148 12:26:42.719591 Set Vref, RX VrefLevel [Byte0]: 68
1149 12:26:42.722540 [Byte1]: 68
1150 12:26:42.726780
1151 12:26:42.726863 Set Vref, RX VrefLevel [Byte0]: 69
1152 12:26:42.730163 [Byte1]: 69
1153 12:26:42.734347
1154 12:26:42.734429 Set Vref, RX VrefLevel [Byte0]: 70
1155 12:26:42.737416 [Byte1]: 70
1156 12:26:42.741914
1157 12:26:42.741990 Set Vref, RX VrefLevel [Byte0]: 71
1158 12:26:42.745321 [Byte1]: 71
1159 12:26:42.749581
1160 12:26:42.749665 Set Vref, RX VrefLevel [Byte0]: 72
1161 12:26:42.752782 [Byte1]: 72
1162 12:26:42.757179
1163 12:26:42.757256 Set Vref, RX VrefLevel [Byte0]: 73
1164 12:26:42.760495 [Byte1]: 73
1165 12:26:42.765193
1166 12:26:42.765280 Set Vref, RX VrefLevel [Byte0]: 74
1167 12:26:42.768017 [Byte1]: 74
1168 12:26:42.772260
1169 12:26:42.772342 Set Vref, RX VrefLevel [Byte0]: 75
1170 12:26:42.775873 [Byte1]: 75
1171 12:26:42.779912
1172 12:26:42.779994 Set Vref, RX VrefLevel [Byte0]: 76
1173 12:26:42.783283 [Byte1]: 76
1174 12:26:42.787664
1175 12:26:42.787747 Set Vref, RX VrefLevel [Byte0]: 77
1176 12:26:42.790909 [Byte1]: 77
1177 12:26:42.795301
1178 12:26:42.795384 Final RX Vref Byte 0 = 61 to rank0
1179 12:26:42.798522 Final RX Vref Byte 1 = 62 to rank0
1180 12:26:42.801851 Final RX Vref Byte 0 = 61 to rank1
1181 12:26:42.805166 Final RX Vref Byte 1 = 62 to rank1==
1182 12:26:42.808042 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 12:26:42.815010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 12:26:42.815094 ==
1185 12:26:42.815161 DQS Delay:
1186 12:26:42.818348 DQS0 = 0, DQS1 = 0
1187 12:26:42.818430 DQM Delay:
1188 12:26:42.818495 DQM0 = 93, DQM1 = 82
1189 12:26:42.821524 DQ Delay:
1190 12:26:42.824686 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1191 12:26:42.828270 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1192 12:26:42.831803 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1193 12:26:42.834882 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1194 12:26:42.834966
1195 12:26:42.835032
1196 12:26:42.841458 [DQSOSCAuto] RK0, (LSB)MR18= 0x3732, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
1197 12:26:42.844822 CH0 RK0: MR19=606, MR18=3732
1198 12:26:42.851416 CH0_RK0: MR19=0x606, MR18=0x3732, DQSOSC=395, MR23=63, INC=94, DEC=63
1199 12:26:42.851503
1200 12:26:42.854823 ----->DramcWriteLeveling(PI) begin...
1201 12:26:42.854910 ==
1202 12:26:42.858107 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 12:26:42.861492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 12:26:42.861577 ==
1205 12:26:42.864918 Write leveling (Byte 0): 33 => 33
1206 12:26:42.868215 Write leveling (Byte 1): 27 => 27
1207 12:26:42.871567 DramcWriteLeveling(PI) end<-----
1208 12:26:42.871651
1209 12:26:42.871715 ==
1210 12:26:42.874897 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 12:26:42.878015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 12:26:42.878102 ==
1213 12:26:42.881494 [Gating] SW mode calibration
1214 12:26:42.888152 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 12:26:42.894834 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 12:26:42.898173 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 12:26:42.904662 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1218 12:26:42.908012 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 12:26:42.911406 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:26:42.955196 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:26:42.955486 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:26:42.955562 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:26:42.955637 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:26:42.955737 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:26:42.955851 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:26:42.955927 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:26:42.956001 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:26:42.956079 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:26:42.956149 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:26:42.999282 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:26:42.999665 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:26:42.999739 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1233 12:26:42.999803 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1234 12:26:42.999865 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1235 12:26:42.999923 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:26:43.000263 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:26:43.000551 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:26:43.000658 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:26:43.000762 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 12:26:43.035189 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 12:26:43.035463 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1242 12:26:43.035550 0 9 8 | B1->B0 | 2c2c 3333 | 0 0 | (0 0) (0 0)
1243 12:26:43.035615 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 12:26:43.035686 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 12:26:43.036064 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 12:26:43.036337 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 12:26:43.039184 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 12:26:43.039269 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1249 12:26:43.042399 0 10 4 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 0)
1250 12:26:43.049117 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1251 12:26:43.052203 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 12:26:43.055695 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 12:26:43.062282 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 12:26:43.065785 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 12:26:43.068957 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 12:26:43.075447 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 12:26:43.078847 0 11 4 | B1->B0 | 2727 2d2d | 0 0 | (0 0) (1 1)
1258 12:26:43.082103 0 11 8 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
1259 12:26:43.088704 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 12:26:43.092492 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 12:26:43.095811 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 12:26:43.101879 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 12:26:43.105591 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 12:26:43.108902 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 12:26:43.115585 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1266 12:26:43.118940 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1267 12:26:43.122186 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 12:26:43.125451 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 12:26:43.132492 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 12:26:43.135673 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 12:26:43.138922 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 12:26:43.146182 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 12:26:43.150025 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 12:26:43.153207 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 12:26:43.156808 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 12:26:43.163467 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 12:26:43.166907 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 12:26:43.170893 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 12:26:43.173951 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 12:26:43.180647 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 12:26:43.183972 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1282 12:26:43.187224 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 12:26:43.190398 Total UI for P1: 0, mck2ui 16
1284 12:26:43.194064 best dqsien dly found for B0: ( 0, 14, 4)
1285 12:26:43.197196 Total UI for P1: 0, mck2ui 16
1286 12:26:43.200546 best dqsien dly found for B1: ( 0, 14, 6)
1287 12:26:43.203861 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1288 12:26:43.207128 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1289 12:26:43.207215
1290 12:26:43.213783 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1291 12:26:43.217095 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1292 12:26:43.217183 [Gating] SW calibration Done
1293 12:26:43.220367 ==
1294 12:26:43.223729 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 12:26:43.227097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 12:26:43.227220 ==
1297 12:26:43.227326 RX Vref Scan: 0
1298 12:26:43.227431
1299 12:26:43.230509 RX Vref 0 -> 0, step: 1
1300 12:26:43.230619
1301 12:26:43.233808 RX Delay -130 -> 252, step: 16
1302 12:26:43.237053 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1303 12:26:43.240160 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1304 12:26:43.247126 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1305 12:26:43.250344 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1306 12:26:43.253685 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1307 12:26:43.256896 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1308 12:26:43.260086 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1309 12:26:43.266694 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1310 12:26:43.270432 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1311 12:26:43.273358 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1312 12:26:43.276933 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1313 12:26:43.279862 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1314 12:26:43.286881 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1315 12:26:43.290049 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1316 12:26:43.293403 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1317 12:26:43.296619 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1318 12:26:43.296727 ==
1319 12:26:43.300250 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 12:26:43.306847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 12:26:43.306951 ==
1322 12:26:43.307049 DQS Delay:
1323 12:26:43.307144 DQS0 = 0, DQS1 = 0
1324 12:26:43.310218 DQM Delay:
1325 12:26:43.310321 DQM0 = 91, DQM1 = 82
1326 12:26:43.313532 DQ Delay:
1327 12:26:43.316543 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1328 12:26:43.320287 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1329 12:26:43.323628 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =85
1330 12:26:43.326890 DQ12 =77, DQ13 =93, DQ14 =93, DQ15 =93
1331 12:26:43.326988
1332 12:26:43.327079
1333 12:26:43.327170 ==
1334 12:26:43.329815 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 12:26:43.333049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 12:26:43.333148 ==
1337 12:26:43.333242
1338 12:26:43.333333
1339 12:26:43.336319 TX Vref Scan disable
1340 12:26:43.336418 == TX Byte 0 ==
1341 12:26:43.343055 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1342 12:26:43.346493 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1343 12:26:43.346582 == TX Byte 1 ==
1344 12:26:43.353181 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1345 12:26:43.356659 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1346 12:26:43.356743 ==
1347 12:26:43.359834 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 12:26:43.363089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 12:26:43.363174 ==
1350 12:26:43.378042 TX Vref=22, minBit 1, minWin=27, winSum=446
1351 12:26:43.381611 TX Vref=24, minBit 12, minWin=27, winSum=452
1352 12:26:43.384687 TX Vref=26, minBit 10, minWin=27, winSum=452
1353 12:26:43.387810 TX Vref=28, minBit 10, minWin=27, winSum=456
1354 12:26:43.391220 TX Vref=30, minBit 8, minWin=28, winSum=457
1355 12:26:43.397894 TX Vref=32, minBit 6, minWin=28, winSum=458
1356 12:26:43.401480 [TxChooseVref] Worse bit 6, Min win 28, Win sum 458, Final Vref 32
1357 12:26:43.401563
1358 12:26:43.404683 Final TX Range 1 Vref 32
1359 12:26:43.404828
1360 12:26:43.404896 ==
1361 12:26:43.408187 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 12:26:43.411423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 12:26:43.414724 ==
1364 12:26:43.414805
1365 12:26:43.414868
1366 12:26:43.414927 TX Vref Scan disable
1367 12:26:43.418557 == TX Byte 0 ==
1368 12:26:43.421646 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1369 12:26:43.428221 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1370 12:26:43.428335 == TX Byte 1 ==
1371 12:26:43.431599 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1372 12:26:43.438040 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1373 12:26:43.438151
1374 12:26:43.438246 [DATLAT]
1375 12:26:43.438365 Freq=800, CH0 RK1
1376 12:26:43.438501
1377 12:26:43.441222 DATLAT Default: 0xa
1378 12:26:43.441326 0, 0xFFFF, sum = 0
1379 12:26:43.444513 1, 0xFFFF, sum = 0
1380 12:26:43.447869 2, 0xFFFF, sum = 0
1381 12:26:43.447958 3, 0xFFFF, sum = 0
1382 12:26:43.451567 4, 0xFFFF, sum = 0
1383 12:26:43.451677 5, 0xFFFF, sum = 0
1384 12:26:43.454805 6, 0xFFFF, sum = 0
1385 12:26:43.454888 7, 0xFFFF, sum = 0
1386 12:26:43.458019 8, 0xFFFF, sum = 0
1387 12:26:43.458101 9, 0x0, sum = 1
1388 12:26:43.461274 10, 0x0, sum = 2
1389 12:26:43.461358 11, 0x0, sum = 3
1390 12:26:43.464167 12, 0x0, sum = 4
1391 12:26:43.464269 best_step = 10
1392 12:26:43.464334
1393 12:26:43.464394 ==
1394 12:26:43.468117 Dram Type= 6, Freq= 0, CH_0, rank 1
1395 12:26:43.470884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 12:26:43.470993 ==
1397 12:26:43.474176 RX Vref Scan: 0
1398 12:26:43.474348
1399 12:26:43.477590 RX Vref 0 -> 0, step: 1
1400 12:26:43.477701
1401 12:26:43.477790 RX Delay -79 -> 252, step: 8
1402 12:26:43.484915 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1403 12:26:43.488329 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1404 12:26:43.491456 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1405 12:26:43.494665 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1406 12:26:43.498210 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1407 12:26:43.504518 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1408 12:26:43.508189 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1409 12:26:43.511594 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1410 12:26:43.514900 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1411 12:26:43.518283 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1412 12:26:43.524440 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1413 12:26:43.527778 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1414 12:26:43.531076 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1415 12:26:43.534433 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1416 12:26:43.541426 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1417 12:26:43.544276 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1418 12:26:43.544394 ==
1419 12:26:43.547995 Dram Type= 6, Freq= 0, CH_0, rank 1
1420 12:26:43.551253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 12:26:43.551375 ==
1422 12:26:43.554517 DQS Delay:
1423 12:26:43.554630 DQS0 = 0, DQS1 = 0
1424 12:26:43.554728 DQM Delay:
1425 12:26:43.557854 DQM0 = 91, DQM1 = 82
1426 12:26:43.557938 DQ Delay:
1427 12:26:43.561317 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =84
1428 12:26:43.564655 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1429 12:26:43.567877 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1430 12:26:43.570764 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1431 12:26:43.570852
1432 12:26:43.570919
1433 12:26:43.581108 [DQSOSCAuto] RK1, (LSB)MR18= 0x421d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1434 12:26:43.584369 CH0 RK1: MR19=606, MR18=421D
1435 12:26:43.587444 CH0_RK1: MR19=0x606, MR18=0x421D, DQSOSC=393, MR23=63, INC=95, DEC=63
1436 12:26:43.590995 [RxdqsGatingPostProcess] freq 800
1437 12:26:43.597587 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1438 12:26:43.601078 Pre-setting of DQS Precalculation
1439 12:26:43.604314 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1440 12:26:43.604431 ==
1441 12:26:43.607606 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 12:26:43.614211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 12:26:43.614304 ==
1444 12:26:43.617467 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1445 12:26:43.624057 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1446 12:26:43.633629 [CA 0] Center 36 (6~67) winsize 62
1447 12:26:43.636744 [CA 1] Center 36 (6~67) winsize 62
1448 12:26:43.639951 [CA 2] Center 35 (5~65) winsize 61
1449 12:26:43.643287 [CA 3] Center 34 (4~65) winsize 62
1450 12:26:43.646437 [CA 4] Center 34 (4~65) winsize 62
1451 12:26:43.650207 [CA 5] Center 33 (3~64) winsize 62
1452 12:26:43.650313
1453 12:26:43.653280 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1454 12:26:43.653389
1455 12:26:43.656615 [CATrainingPosCal] consider 1 rank data
1456 12:26:43.660220 u2DelayCellTimex100 = 270/100 ps
1457 12:26:43.663468 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1458 12:26:43.666691 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1459 12:26:43.673200 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1460 12:26:43.676427 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1461 12:26:43.680269 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1462 12:26:43.683519 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1463 12:26:43.683603
1464 12:26:43.686935 CA PerBit enable=1, Macro0, CA PI delay=33
1465 12:26:43.687018
1466 12:26:43.690147 [CBTSetCACLKResult] CA Dly = 33
1467 12:26:43.690228 CS Dly: 4 (0~35)
1468 12:26:43.693326 ==
1469 12:26:43.696472 Dram Type= 6, Freq= 0, CH_1, rank 1
1470 12:26:43.700144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1471 12:26:43.700284 ==
1472 12:26:43.703200 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1473 12:26:43.709997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1474 12:26:43.719963 [CA 0] Center 36 (6~67) winsize 62
1475 12:26:43.723134 [CA 1] Center 36 (6~67) winsize 62
1476 12:26:43.726487 [CA 2] Center 35 (5~66) winsize 62
1477 12:26:43.729885 [CA 3] Center 34 (4~65) winsize 62
1478 12:26:43.733202 [CA 4] Center 34 (4~65) winsize 62
1479 12:26:43.736569 [CA 5] Center 34 (4~64) winsize 61
1480 12:26:43.736682
1481 12:26:43.739826 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1482 12:26:43.739912
1483 12:26:43.743100 [CATrainingPosCal] consider 2 rank data
1484 12:26:43.746536 u2DelayCellTimex100 = 270/100 ps
1485 12:26:43.749474 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1486 12:26:43.752985 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1487 12:26:43.759634 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1488 12:26:43.762741 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1489 12:26:43.766457 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1490 12:26:43.769557 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1491 12:26:43.769643
1492 12:26:43.772674 CA PerBit enable=1, Macro0, CA PI delay=34
1493 12:26:43.772760
1494 12:26:43.775952 [CBTSetCACLKResult] CA Dly = 34
1495 12:26:43.776037 CS Dly: 5 (0~38)
1496 12:26:43.776104
1497 12:26:43.779737 ----->DramcWriteLeveling(PI) begin...
1498 12:26:43.783005 ==
1499 12:26:43.785923 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 12:26:43.789193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1501 12:26:43.789280 ==
1502 12:26:43.792787 Write leveling (Byte 0): 25 => 25
1503 12:26:43.796172 Write leveling (Byte 1): 30 => 30
1504 12:26:43.799302 DramcWriteLeveling(PI) end<-----
1505 12:26:43.799388
1506 12:26:43.799456 ==
1507 12:26:43.802636 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 12:26:43.806321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 12:26:43.806433 ==
1510 12:26:43.809726 [Gating] SW mode calibration
1511 12:26:43.817394 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1512 12:26:43.820892 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1513 12:26:43.824437 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1514 12:26:43.828021 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1515 12:26:43.835587 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1516 12:26:43.839005 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 12:26:43.842878 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:26:43.846057 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:26:43.852710 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:26:43.855956 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:26:43.859245 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:26:43.865816 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:26:43.869142 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:26:43.872364 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:26:43.879109 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:26:43.882365 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:26:43.885671 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:26:43.892733 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:26:43.896000 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1530 12:26:43.899167 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1531 12:26:43.905721 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1532 12:26:43.909028 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:26:43.912674 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:26:43.918925 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:26:43.922460 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:26:43.925558 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:26:43.932581 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 12:26:43.935899 0 9 4 | B1->B0 | 2323 2525 | 1 0 | (1 1) (0 0)
1539 12:26:43.939102 0 9 8 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1540 12:26:43.945682 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 12:26:43.948935 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 12:26:43.952374 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 12:26:43.955537 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 12:26:43.962269 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 12:26:43.965699 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1546 12:26:43.969059 0 10 4 | B1->B0 | 2d2d 2c2c | 1 0 | (1 0) (0 0)
1547 12:26:43.975465 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 12:26:43.978742 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 12:26:43.982149 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 12:26:43.988688 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 12:26:43.992120 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 12:26:43.995508 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 12:26:44.002169 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 12:26:44.005340 0 11 4 | B1->B0 | 2f2f 3333 | 0 0 | (1 1) (0 0)
1555 12:26:44.008757 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1556 12:26:44.015409 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 12:26:44.018790 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 12:26:44.021994 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 12:26:44.028481 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 12:26:44.032065 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 12:26:44.035215 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1562 12:26:44.041755 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1563 12:26:44.045076 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 12:26:44.048650 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 12:26:44.055331 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 12:26:44.058479 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 12:26:44.061861 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:26:44.068545 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 12:26:44.071833 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 12:26:44.075095 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:26:44.081742 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 12:26:44.085077 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:26:44.088361 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 12:26:44.094811 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 12:26:44.098188 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 12:26:44.101515 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 12:26:44.108149 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1578 12:26:44.111839 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1579 12:26:44.114745 Total UI for P1: 0, mck2ui 16
1580 12:26:44.118079 best dqsien dly found for B1: ( 0, 14, 2)
1581 12:26:44.121372 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 12:26:44.124671 Total UI for P1: 0, mck2ui 16
1583 12:26:44.127997 best dqsien dly found for B0: ( 0, 14, 2)
1584 12:26:44.131554 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1585 12:26:44.134673 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1586 12:26:44.134756
1587 12:26:44.137873 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1588 12:26:44.144692 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1589 12:26:44.144831 [Gating] SW calibration Done
1590 12:26:44.144919 ==
1591 12:26:44.147672 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 12:26:44.154599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 12:26:44.154691 ==
1594 12:26:44.154777 RX Vref Scan: 0
1595 12:26:44.154856
1596 12:26:44.157870 RX Vref 0 -> 0, step: 1
1597 12:26:44.157946
1598 12:26:44.161135 RX Delay -130 -> 252, step: 16
1599 12:26:44.164533 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1600 12:26:44.167860 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1601 12:26:44.171246 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1602 12:26:44.177875 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1603 12:26:44.181156 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1604 12:26:44.184481 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1605 12:26:44.187738 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1606 12:26:44.191122 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1607 12:26:44.197913 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1608 12:26:44.201331 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1609 12:26:44.204621 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1610 12:26:44.207586 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1611 12:26:44.211255 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1612 12:26:44.217847 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1613 12:26:44.221077 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1614 12:26:44.224476 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1615 12:26:44.224563 ==
1616 12:26:44.227789 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 12:26:44.231046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 12:26:44.231161 ==
1619 12:26:44.234200 DQS Delay:
1620 12:26:44.234311 DQS0 = 0, DQS1 = 0
1621 12:26:44.237826 DQM Delay:
1622 12:26:44.237940 DQM0 = 93, DQM1 = 86
1623 12:26:44.238036 DQ Delay:
1624 12:26:44.241085 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1625 12:26:44.244483 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =93
1626 12:26:44.247536 DQ8 =69, DQ9 =77, DQ10 =93, DQ11 =77
1627 12:26:44.250898 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1628 12:26:44.250984
1629 12:26:44.251060
1630 12:26:44.254305 ==
1631 12:26:44.257541 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 12:26:44.261109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 12:26:44.261198 ==
1634 12:26:44.261266
1635 12:26:44.261329
1636 12:26:44.263966 TX Vref Scan disable
1637 12:26:44.264058 == TX Byte 0 ==
1638 12:26:44.270989 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1639 12:26:44.274309 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1640 12:26:44.274421 == TX Byte 1 ==
1641 12:26:44.280873 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1642 12:26:44.284401 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1643 12:26:44.284489 ==
1644 12:26:44.287679 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 12:26:44.290988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 12:26:44.291112 ==
1647 12:26:44.304529 TX Vref=22, minBit 8, minWin=27, winSum=443
1648 12:26:44.307872 TX Vref=24, minBit 8, minWin=27, winSum=448
1649 12:26:44.311244 TX Vref=26, minBit 10, minWin=27, winSum=452
1650 12:26:44.314437 TX Vref=28, minBit 8, minWin=27, winSum=455
1651 12:26:44.317709 TX Vref=30, minBit 15, minWin=27, winSum=457
1652 12:26:44.324566 TX Vref=32, minBit 11, minWin=27, winSum=456
1653 12:26:44.327411 [TxChooseVref] Worse bit 15, Min win 27, Win sum 457, Final Vref 30
1654 12:26:44.327559
1655 12:26:44.330809 Final TX Range 1 Vref 30
1656 12:26:44.330948
1657 12:26:44.331072 ==
1658 12:26:44.334156 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 12:26:44.340864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1660 12:26:44.341126 ==
1661 12:26:44.341283
1662 12:26:44.341406
1663 12:26:44.341528 TX Vref Scan disable
1664 12:26:44.344736 == TX Byte 0 ==
1665 12:26:44.348123 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1666 12:26:44.354560 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1667 12:26:44.354686 == TX Byte 1 ==
1668 12:26:44.358077 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1669 12:26:44.364726 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1670 12:26:44.364882
1671 12:26:44.364964 [DATLAT]
1672 12:26:44.365064 Freq=800, CH1 RK0
1673 12:26:44.365123
1674 12:26:44.368069 DATLAT Default: 0xa
1675 12:26:44.368153 0, 0xFFFF, sum = 0
1676 12:26:44.371480 1, 0xFFFF, sum = 0
1677 12:26:44.371596 2, 0xFFFF, sum = 0
1678 12:26:44.374738 3, 0xFFFF, sum = 0
1679 12:26:44.378045 4, 0xFFFF, sum = 0
1680 12:26:44.378130 5, 0xFFFF, sum = 0
1681 12:26:44.381352 6, 0xFFFF, sum = 0
1682 12:26:44.381465 7, 0xFFFF, sum = 0
1683 12:26:44.384719 8, 0xFFFF, sum = 0
1684 12:26:44.384843 9, 0x0, sum = 1
1685 12:26:44.388388 10, 0x0, sum = 2
1686 12:26:44.388473 11, 0x0, sum = 3
1687 12:26:44.388540 12, 0x0, sum = 4
1688 12:26:44.392293 best_step = 10
1689 12:26:44.392378
1690 12:26:44.392443 ==
1691 12:26:44.395636 Dram Type= 6, Freq= 0, CH_1, rank 0
1692 12:26:44.399029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1693 12:26:44.399115 ==
1694 12:26:44.399197 RX Vref Scan: 1
1695 12:26:44.402332
1696 12:26:44.402416 Set Vref Range= 32 -> 127
1697 12:26:44.402481
1698 12:26:44.405485 RX Vref 32 -> 127, step: 1
1699 12:26:44.405617
1700 12:26:44.408719 RX Delay -95 -> 252, step: 8
1701 12:26:44.408872
1702 12:26:44.412139 Set Vref, RX VrefLevel [Byte0]: 32
1703 12:26:44.415399 [Byte1]: 32
1704 12:26:44.415474
1705 12:26:44.418642 Set Vref, RX VrefLevel [Byte0]: 33
1706 12:26:44.422279 [Byte1]: 33
1707 12:26:44.422352
1708 12:26:44.425478 Set Vref, RX VrefLevel [Byte0]: 34
1709 12:26:44.428757 [Byte1]: 34
1710 12:26:44.432632
1711 12:26:44.432751 Set Vref, RX VrefLevel [Byte0]: 35
1712 12:26:44.435816 [Byte1]: 35
1713 12:26:44.440559
1714 12:26:44.440662 Set Vref, RX VrefLevel [Byte0]: 36
1715 12:26:44.443682 [Byte1]: 36
1716 12:26:44.447936
1717 12:26:44.448032 Set Vref, RX VrefLevel [Byte0]: 37
1718 12:26:44.451297 [Byte1]: 37
1719 12:26:44.455811
1720 12:26:44.455896 Set Vref, RX VrefLevel [Byte0]: 38
1721 12:26:44.459061 [Byte1]: 38
1722 12:26:44.463232
1723 12:26:44.463315 Set Vref, RX VrefLevel [Byte0]: 39
1724 12:26:44.466298 [Byte1]: 39
1725 12:26:44.470576
1726 12:26:44.470661 Set Vref, RX VrefLevel [Byte0]: 40
1727 12:26:44.474167 [Byte1]: 40
1728 12:26:44.478237
1729 12:26:44.478322 Set Vref, RX VrefLevel [Byte0]: 41
1730 12:26:44.481507 [Byte1]: 41
1731 12:26:44.485816
1732 12:26:44.485899 Set Vref, RX VrefLevel [Byte0]: 42
1733 12:26:44.489222 [Byte1]: 42
1734 12:26:44.493776
1735 12:26:44.493860 Set Vref, RX VrefLevel [Byte0]: 43
1736 12:26:44.496688 [Byte1]: 43
1737 12:26:44.501352
1738 12:26:44.501436 Set Vref, RX VrefLevel [Byte0]: 44
1739 12:26:44.504653 [Byte1]: 44
1740 12:26:44.508814
1741 12:26:44.508898 Set Vref, RX VrefLevel [Byte0]: 45
1742 12:26:44.511989 [Byte1]: 45
1743 12:26:44.516263
1744 12:26:44.516348 Set Vref, RX VrefLevel [Byte0]: 46
1745 12:26:44.519677 [Byte1]: 46
1746 12:26:44.523983
1747 12:26:44.524086 Set Vref, RX VrefLevel [Byte0]: 47
1748 12:26:44.527101 [Byte1]: 47
1749 12:26:44.531436
1750 12:26:44.531513 Set Vref, RX VrefLevel [Byte0]: 48
1751 12:26:44.534792 [Byte1]: 48
1752 12:26:44.539096
1753 12:26:44.539182 Set Vref, RX VrefLevel [Byte0]: 49
1754 12:26:44.542468 [Byte1]: 49
1755 12:26:44.546645
1756 12:26:44.546721 Set Vref, RX VrefLevel [Byte0]: 50
1757 12:26:44.549858 [Byte1]: 50
1758 12:26:44.554196
1759 12:26:44.554366 Set Vref, RX VrefLevel [Byte0]: 51
1760 12:26:44.557381 [Byte1]: 51
1761 12:26:44.562130
1762 12:26:44.562214 Set Vref, RX VrefLevel [Byte0]: 52
1763 12:26:44.565431 [Byte1]: 52
1764 12:26:44.569656
1765 12:26:44.569764 Set Vref, RX VrefLevel [Byte0]: 53
1766 12:26:44.572784 [Byte1]: 53
1767 12:26:44.576950
1768 12:26:44.577036 Set Vref, RX VrefLevel [Byte0]: 54
1769 12:26:44.580460 [Byte1]: 54
1770 12:26:44.584633
1771 12:26:44.584748 Set Vref, RX VrefLevel [Byte0]: 55
1772 12:26:44.587988 [Byte1]: 55
1773 12:26:44.592357
1774 12:26:44.592465 Set Vref, RX VrefLevel [Byte0]: 56
1775 12:26:44.595593 [Byte1]: 56
1776 12:26:44.599771
1777 12:26:44.599878 Set Vref, RX VrefLevel [Byte0]: 57
1778 12:26:44.603072 [Byte1]: 57
1779 12:26:44.607318
1780 12:26:44.607421 Set Vref, RX VrefLevel [Byte0]: 58
1781 12:26:44.610662 [Byte1]: 58
1782 12:26:44.615176
1783 12:26:44.615257 Set Vref, RX VrefLevel [Byte0]: 59
1784 12:26:44.618620 [Byte1]: 59
1785 12:26:44.622743
1786 12:26:44.622816 Set Vref, RX VrefLevel [Byte0]: 60
1787 12:26:44.626088 [Byte1]: 60
1788 12:26:44.630229
1789 12:26:44.630332 Set Vref, RX VrefLevel [Byte0]: 61
1790 12:26:44.633430 [Byte1]: 61
1791 12:26:44.637785
1792 12:26:44.637863 Set Vref, RX VrefLevel [Byte0]: 62
1793 12:26:44.641102 [Byte1]: 62
1794 12:26:44.645416
1795 12:26:44.645494 Set Vref, RX VrefLevel [Byte0]: 63
1796 12:26:44.648666 [Byte1]: 63
1797 12:26:44.653196
1798 12:26:44.653276 Set Vref, RX VrefLevel [Byte0]: 64
1799 12:26:44.656503 [Byte1]: 64
1800 12:26:44.660694
1801 12:26:44.660874 Set Vref, RX VrefLevel [Byte0]: 65
1802 12:26:44.663962 [Byte1]: 65
1803 12:26:44.668098
1804 12:26:44.668182 Set Vref, RX VrefLevel [Byte0]: 66
1805 12:26:44.671490 [Byte1]: 66
1806 12:26:44.676110
1807 12:26:44.676194 Set Vref, RX VrefLevel [Byte0]: 67
1808 12:26:44.679034 [Byte1]: 67
1809 12:26:44.683220
1810 12:26:44.683307 Set Vref, RX VrefLevel [Byte0]: 68
1811 12:26:44.686616 [Byte1]: 68
1812 12:26:44.690991
1813 12:26:44.694011 Set Vref, RX VrefLevel [Byte0]: 69
1814 12:26:44.694095 [Byte1]: 69
1815 12:26:44.698711
1816 12:26:44.698795 Set Vref, RX VrefLevel [Byte0]: 70
1817 12:26:44.701982 [Byte1]: 70
1818 12:26:44.706189
1819 12:26:44.706273 Set Vref, RX VrefLevel [Byte0]: 71
1820 12:26:44.709375 [Byte1]: 71
1821 12:26:44.713880
1822 12:26:44.713963 Set Vref, RX VrefLevel [Byte0]: 72
1823 12:26:44.717176 [Byte1]: 72
1824 12:26:44.721187
1825 12:26:44.721271 Set Vref, RX VrefLevel [Byte0]: 73
1826 12:26:44.724524 [Byte1]: 73
1827 12:26:44.729167
1828 12:26:44.729250 Set Vref, RX VrefLevel [Byte0]: 74
1829 12:26:44.732475 [Byte1]: 74
1830 12:26:44.736683
1831 12:26:44.736823 Set Vref, RX VrefLevel [Byte0]: 75
1832 12:26:44.739969 [Byte1]: 75
1833 12:26:44.744215
1834 12:26:44.744299 Set Vref, RX VrefLevel [Byte0]: 76
1835 12:26:44.747667 [Byte1]: 76
1836 12:26:44.751823
1837 12:26:44.751953 Final RX Vref Byte 0 = 51 to rank0
1838 12:26:44.755086 Final RX Vref Byte 1 = 63 to rank0
1839 12:26:44.758410 Final RX Vref Byte 0 = 51 to rank1
1840 12:26:44.761734 Final RX Vref Byte 1 = 63 to rank1==
1841 12:26:44.764919 Dram Type= 6, Freq= 0, CH_1, rank 0
1842 12:26:44.771772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1843 12:26:44.771957 ==
1844 12:26:44.772085 DQS Delay:
1845 12:26:44.772202 DQS0 = 0, DQS1 = 0
1846 12:26:44.775071 DQM Delay:
1847 12:26:44.775171 DQM0 = 93, DQM1 = 84
1848 12:26:44.778435 DQ Delay:
1849 12:26:44.781636 DQ0 =100, DQ1 =84, DQ2 =84, DQ3 =88
1850 12:26:44.785058 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1851 12:26:44.788304 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =80
1852 12:26:44.791737 DQ12 =96, DQ13 =88, DQ14 =88, DQ15 =88
1853 12:26:44.791887
1854 12:26:44.792012
1855 12:26:44.798498 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1856 12:26:44.801724 CH1 RK0: MR19=606, MR18=2E4B
1857 12:26:44.808420 CH1_RK0: MR19=0x606, MR18=0x2E4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1858 12:26:44.808517
1859 12:26:44.811741 ----->DramcWriteLeveling(PI) begin...
1860 12:26:44.811833 ==
1861 12:26:44.814985 Dram Type= 6, Freq= 0, CH_1, rank 1
1862 12:26:44.818352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1863 12:26:44.818436 ==
1864 12:26:44.821770 Write leveling (Byte 0): 28 => 28
1865 12:26:44.824711 Write leveling (Byte 1): 33 => 33
1866 12:26:44.828597 DramcWriteLeveling(PI) end<-----
1867 12:26:44.828687
1868 12:26:44.828802 ==
1869 12:26:44.831893 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 12:26:44.835117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1871 12:26:44.835208 ==
1872 12:26:44.838335 [Gating] SW mode calibration
1873 12:26:44.844740 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1874 12:26:44.851436 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1875 12:26:44.854776 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1876 12:26:44.858081 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1877 12:26:44.864594 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 12:26:44.867828 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:26:44.871564 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 12:26:44.878140 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:26:44.881443 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:26:44.884683 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:26:44.891054 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:26:44.894418 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:26:44.898021 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:26:44.904466 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:26:44.908044 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:26:44.911157 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:26:44.917933 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:26:44.921403 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:26:44.924260 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1892 12:26:44.931249 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1893 12:26:44.934586 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:26:44.937825 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:26:44.944497 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:26:44.947975 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:26:44.951295 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:26:44.957563 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:26:44.961293 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:26:44.964448 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:26:44.971449 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 12:26:44.974220 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 12:26:44.977454 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 12:26:44.983968 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 12:26:44.987617 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 12:26:44.990872 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 12:26:44.997374 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1908 12:26:45.000821 0 10 4 | B1->B0 | 2f2f 3232 | 1 0 | (1 0) (0 1)
1909 12:26:45.004432 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 12:26:45.007795 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 12:26:45.014374 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 12:26:45.017528 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 12:26:45.021113 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 12:26:45.027444 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 12:26:45.030705 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 12:26:45.034441 0 11 4 | B1->B0 | 3534 3131 | 1 1 | (0 0) (0 0)
1917 12:26:45.041031 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1918 12:26:45.044219 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 12:26:45.047608 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 12:26:45.054494 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 12:26:45.057831 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 12:26:45.061210 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 12:26:45.067492 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1924 12:26:45.071185 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1925 12:26:45.074060 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 12:26:45.080849 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 12:26:45.084141 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 12:26:45.087478 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 12:26:45.093921 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 12:26:45.097584 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 12:26:45.100497 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 12:26:45.107573 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 12:26:45.110814 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 12:26:45.114014 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 12:26:45.120683 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 12:26:45.123763 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 12:26:45.127384 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 12:26:45.133917 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 12:26:45.137129 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 12:26:45.140334 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1941 12:26:45.143723 Total UI for P1: 0, mck2ui 16
1942 12:26:45.147132 best dqsien dly found for B1: ( 0, 14, 2)
1943 12:26:45.150438 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1944 12:26:45.153731 Total UI for P1: 0, mck2ui 16
1945 12:26:45.157412 best dqsien dly found for B0: ( 0, 14, 4)
1946 12:26:45.160260 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1947 12:26:45.167003 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1948 12:26:45.167087
1949 12:26:45.170280 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1950 12:26:45.173701 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1951 12:26:45.177071 [Gating] SW calibration Done
1952 12:26:45.177157 ==
1953 12:26:45.180386 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 12:26:45.183510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 12:26:45.183598 ==
1956 12:26:45.183668 RX Vref Scan: 0
1957 12:26:45.183733
1958 12:26:45.186826 RX Vref 0 -> 0, step: 1
1959 12:26:45.186901
1960 12:26:45.190271 RX Delay -130 -> 252, step: 16
1961 12:26:45.193875 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1962 12:26:45.196667 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1963 12:26:45.203665 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1964 12:26:45.206971 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1965 12:26:45.210207 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1966 12:26:45.213320 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1967 12:26:45.217028 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1968 12:26:45.223590 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1969 12:26:45.227035 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1970 12:26:45.230238 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1971 12:26:45.233487 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1972 12:26:45.236918 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1973 12:26:45.243474 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1974 12:26:45.246720 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1975 12:26:45.250051 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1976 12:26:45.253424 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1977 12:26:45.253537 ==
1978 12:26:45.256678 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 12:26:45.263236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 12:26:45.263328 ==
1981 12:26:45.263397 DQS Delay:
1982 12:26:45.266649 DQS0 = 0, DQS1 = 0
1983 12:26:45.266734 DQM Delay:
1984 12:26:45.266802 DQM0 = 88, DQM1 = 84
1985 12:26:45.269912 DQ Delay:
1986 12:26:45.273269 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1987 12:26:45.276402 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1988 12:26:45.279666 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1989 12:26:45.283111 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1990 12:26:45.283196
1991 12:26:45.283263
1992 12:26:45.283326 ==
1993 12:26:45.286320 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 12:26:45.289881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 12:26:45.289977 ==
1996 12:26:45.290046
1997 12:26:45.290108
1998 12:26:45.293105 TX Vref Scan disable
1999 12:26:45.293190 == TX Byte 0 ==
2000 12:26:45.299717 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2001 12:26:45.303102 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2002 12:26:45.306593 == TX Byte 1 ==
2003 12:26:45.309932 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
2004 12:26:45.313182 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
2005 12:26:45.313268 ==
2006 12:26:45.316368 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 12:26:45.319554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 12:26:45.319633 ==
2009 12:26:45.334307 TX Vref=22, minBit 8, minWin=27, winSum=451
2010 12:26:45.337644 TX Vref=24, minBit 13, minWin=27, winSum=456
2011 12:26:45.340903 TX Vref=26, minBit 1, minWin=28, winSum=458
2012 12:26:45.344498 TX Vref=28, minBit 8, minWin=28, winSum=459
2013 12:26:45.347820 TX Vref=30, minBit 8, minWin=28, winSum=465
2014 12:26:45.351194 TX Vref=32, minBit 8, minWin=27, winSum=459
2015 12:26:45.358030 [TxChooseVref] Worse bit 8, Min win 28, Win sum 465, Final Vref 30
2016 12:26:45.358128
2017 12:26:45.361176 Final TX Range 1 Vref 30
2018 12:26:45.361281
2019 12:26:45.361348 ==
2020 12:26:45.364560 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 12:26:45.367898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 12:26:45.367985 ==
2023 12:26:45.368052
2024 12:26:45.371106
2025 12:26:45.371190 TX Vref Scan disable
2026 12:26:45.374426 == TX Byte 0 ==
2027 12:26:45.377678 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2028 12:26:45.384517 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2029 12:26:45.384604 == TX Byte 1 ==
2030 12:26:45.387975 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
2031 12:26:45.394383 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
2032 12:26:45.394474
2033 12:26:45.394540 [DATLAT]
2034 12:26:45.394601 Freq=800, CH1 RK1
2035 12:26:45.394661
2036 12:26:45.397550 DATLAT Default: 0xa
2037 12:26:45.397639 0, 0xFFFF, sum = 0
2038 12:26:45.400915 1, 0xFFFF, sum = 0
2039 12:26:45.401001 2, 0xFFFF, sum = 0
2040 12:26:45.404278 3, 0xFFFF, sum = 0
2041 12:26:45.404363 4, 0xFFFF, sum = 0
2042 12:26:45.407538 5, 0xFFFF, sum = 0
2043 12:26:45.410807 6, 0xFFFF, sum = 0
2044 12:26:45.410893 7, 0xFFFF, sum = 0
2045 12:26:45.414269 8, 0xFFFF, sum = 0
2046 12:26:45.414354 9, 0x0, sum = 1
2047 12:26:45.414422 10, 0x0, sum = 2
2048 12:26:45.417475 11, 0x0, sum = 3
2049 12:26:45.417575 12, 0x0, sum = 4
2050 12:26:45.421004 best_step = 10
2051 12:26:45.421092
2052 12:26:45.421159 ==
2053 12:26:45.424301 Dram Type= 6, Freq= 0, CH_1, rank 1
2054 12:26:45.427791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2055 12:26:45.427874 ==
2056 12:26:45.431049 RX Vref Scan: 0
2057 12:26:45.431132
2058 12:26:45.431197 RX Vref 0 -> 0, step: 1
2059 12:26:45.431258
2060 12:26:45.434288 RX Delay -79 -> 252, step: 8
2061 12:26:45.441257 iDelay=209, Bit 0, Center 96 (1 ~ 192) 192
2062 12:26:45.444135 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2063 12:26:45.447934 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2064 12:26:45.451159 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2065 12:26:45.454450 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2066 12:26:45.460774 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2067 12:26:45.463998 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2068 12:26:45.467599 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2069 12:26:45.471008 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2070 12:26:45.474268 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2071 12:26:45.480916 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2072 12:26:45.484110 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2073 12:26:45.487214 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2074 12:26:45.490514 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2075 12:26:45.494283 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2076 12:26:45.500636 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2077 12:26:45.500751 ==
2078 12:26:45.504096 Dram Type= 6, Freq= 0, CH_1, rank 1
2079 12:26:45.507447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2080 12:26:45.507530 ==
2081 12:26:45.507596 DQS Delay:
2082 12:26:45.510735 DQS0 = 0, DQS1 = 0
2083 12:26:45.510817 DQM Delay:
2084 12:26:45.514210 DQM0 = 92, DQM1 = 84
2085 12:26:45.514293 DQ Delay:
2086 12:26:45.517550 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
2087 12:26:45.520428 DQ4 =96, DQ5 =108, DQ6 =96, DQ7 =88
2088 12:26:45.524106 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2089 12:26:45.527051 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
2090 12:26:45.527136
2091 12:26:45.527202
2092 12:26:45.534153 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2093 12:26:45.537586 CH1 RK1: MR19=606, MR18=3D13
2094 12:26:45.543813 CH1_RK1: MR19=0x606, MR18=0x3D13, DQSOSC=394, MR23=63, INC=95, DEC=63
2095 12:26:45.547112 [RxdqsGatingPostProcess] freq 800
2096 12:26:45.553817 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2097 12:26:45.557022 Pre-setting of DQS Precalculation
2098 12:26:45.560250 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2099 12:26:45.566850 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2100 12:26:45.573537 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2101 12:26:45.576676
2102 12:26:45.576760
2103 12:26:45.576863 [Calibration Summary] 1600 Mbps
2104 12:26:45.580091 CH 0, Rank 0
2105 12:26:45.580174 SW Impedance : PASS
2106 12:26:45.583282 DUTY Scan : NO K
2107 12:26:45.586860 ZQ Calibration : PASS
2108 12:26:45.586971 Jitter Meter : NO K
2109 12:26:45.590101 CBT Training : PASS
2110 12:26:45.593497 Write leveling : PASS
2111 12:26:45.593581 RX DQS gating : PASS
2112 12:26:45.596753 RX DQ/DQS(RDDQC) : PASS
2113 12:26:45.599986 TX DQ/DQS : PASS
2114 12:26:45.600070 RX DATLAT : PASS
2115 12:26:45.603465 RX DQ/DQS(Engine): PASS
2116 12:26:45.606767 TX OE : NO K
2117 12:26:45.606851 All Pass.
2118 12:26:45.606918
2119 12:26:45.606978 CH 0, Rank 1
2120 12:26:45.610009 SW Impedance : PASS
2121 12:26:45.613310 DUTY Scan : NO K
2122 12:26:45.613394 ZQ Calibration : PASS
2123 12:26:45.616494 Jitter Meter : NO K
2124 12:26:45.620160 CBT Training : PASS
2125 12:26:45.620243 Write leveling : PASS
2126 12:26:45.623548 RX DQS gating : PASS
2127 12:26:45.623633 RX DQ/DQS(RDDQC) : PASS
2128 12:26:45.626853 TX DQ/DQS : PASS
2129 12:26:45.630143 RX DATLAT : PASS
2130 12:26:45.630257 RX DQ/DQS(Engine): PASS
2131 12:26:45.633138 TX OE : NO K
2132 12:26:45.633253 All Pass.
2133 12:26:45.633347
2134 12:26:45.636975 CH 1, Rank 0
2135 12:26:45.637080 SW Impedance : PASS
2136 12:26:45.640238 DUTY Scan : NO K
2137 12:26:45.643506 ZQ Calibration : PASS
2138 12:26:45.643591 Jitter Meter : NO K
2139 12:26:45.646849 CBT Training : PASS
2140 12:26:45.650085 Write leveling : PASS
2141 12:26:45.650228 RX DQS gating : PASS
2142 12:26:45.653415 RX DQ/DQS(RDDQC) : PASS
2143 12:26:45.656661 TX DQ/DQS : PASS
2144 12:26:45.656779 RX DATLAT : PASS
2145 12:26:45.659995 RX DQ/DQS(Engine): PASS
2146 12:26:45.663330 TX OE : NO K
2147 12:26:45.663441 All Pass.
2148 12:26:45.663547
2149 12:26:45.663634 CH 1, Rank 1
2150 12:26:45.666713 SW Impedance : PASS
2151 12:26:45.669919 DUTY Scan : NO K
2152 12:26:45.670004 ZQ Calibration : PASS
2153 12:26:45.672972 Jitter Meter : NO K
2154 12:26:45.676555 CBT Training : PASS
2155 12:26:45.676661 Write leveling : PASS
2156 12:26:45.679708 RX DQS gating : PASS
2157 12:26:45.683198 RX DQ/DQS(RDDQC) : PASS
2158 12:26:45.683289 TX DQ/DQS : PASS
2159 12:26:45.686149 RX DATLAT : PASS
2160 12:26:45.686254 RX DQ/DQS(Engine): PASS
2161 12:26:45.689612 TX OE : NO K
2162 12:26:45.689688 All Pass.
2163 12:26:45.689751
2164 12:26:45.693178 DramC Write-DBI off
2165 12:26:45.696502 PER_BANK_REFRESH: Hybrid Mode
2166 12:26:45.696616 TX_TRACKING: ON
2167 12:26:45.699858 [GetDramInforAfterCalByMRR] Vendor 6.
2168 12:26:45.703036 [GetDramInforAfterCalByMRR] Revision 606.
2169 12:26:45.709438 [GetDramInforAfterCalByMRR] Revision 2 0.
2170 12:26:45.709527 MR0 0x3b3b
2171 12:26:45.709613 MR8 0x5151
2172 12:26:45.712707 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 12:26:45.712855
2174 12:26:45.716018 MR0 0x3b3b
2175 12:26:45.716104 MR8 0x5151
2176 12:26:45.719304 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2177 12:26:45.719409
2178 12:26:45.729654 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2179 12:26:45.732726 [FAST_K] Save calibration result to emmc
2180 12:26:45.735998 [FAST_K] Save calibration result to emmc
2181 12:26:45.739308 dram_init: config_dvfs: 1
2182 12:26:45.742699 dramc_set_vcore_voltage set vcore to 662500
2183 12:26:45.742787 Read voltage for 1200, 2
2184 12:26:45.745942 Vio18 = 0
2185 12:26:45.746030 Vcore = 662500
2186 12:26:45.746117 Vdram = 0
2187 12:26:45.749220 Vddq = 0
2188 12:26:45.749308 Vmddr = 0
2189 12:26:45.755927 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2190 12:26:45.759321 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2191 12:26:45.762617 MEM_TYPE=3, freq_sel=15
2192 12:26:45.765906 sv_algorithm_assistance_LP4_1600
2193 12:26:45.769168 ============ PULL DRAM RESETB DOWN ============
2194 12:26:45.772494 ========== PULL DRAM RESETB DOWN end =========
2195 12:26:45.779065 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2196 12:26:45.782557 ===================================
2197 12:26:45.782667 LPDDR4 DRAM CONFIGURATION
2198 12:26:45.785518 ===================================
2199 12:26:45.789250 EX_ROW_EN[0] = 0x0
2200 12:26:45.792622 EX_ROW_EN[1] = 0x0
2201 12:26:45.792739 LP4Y_EN = 0x0
2202 12:26:45.795750 WORK_FSP = 0x0
2203 12:26:45.795869 WL = 0x4
2204 12:26:45.798947 RL = 0x4
2205 12:26:45.799072 BL = 0x2
2206 12:26:45.802193 RPST = 0x0
2207 12:26:45.802317 RD_PRE = 0x0
2208 12:26:45.805478 WR_PRE = 0x1
2209 12:26:45.805592 WR_PST = 0x0
2210 12:26:45.809097 DBI_WR = 0x0
2211 12:26:45.809181 DBI_RD = 0x0
2212 12:26:45.812185 OTF = 0x1
2213 12:26:45.815453 ===================================
2214 12:26:45.818795 ===================================
2215 12:26:45.818899 ANA top config
2216 12:26:45.822092 ===================================
2217 12:26:45.825700 DLL_ASYNC_EN = 0
2218 12:26:45.828979 ALL_SLAVE_EN = 0
2219 12:26:45.829065 NEW_RANK_MODE = 1
2220 12:26:45.832272 DLL_IDLE_MODE = 1
2221 12:26:45.835538 LP45_APHY_COMB_EN = 1
2222 12:26:45.838795 TX_ODT_DIS = 1
2223 12:26:45.841926 NEW_8X_MODE = 1
2224 12:26:45.845349 ===================================
2225 12:26:45.848662 ===================================
2226 12:26:45.848753 data_rate = 2400
2227 12:26:45.851985 CKR = 1
2228 12:26:45.855308 DQ_P2S_RATIO = 8
2229 12:26:45.858649 ===================================
2230 12:26:45.861968 CA_P2S_RATIO = 8
2231 12:26:45.865172 DQ_CA_OPEN = 0
2232 12:26:45.868525 DQ_SEMI_OPEN = 0
2233 12:26:45.868605 CA_SEMI_OPEN = 0
2234 12:26:45.871928 CA_FULL_RATE = 0
2235 12:26:45.875157 DQ_CKDIV4_EN = 0
2236 12:26:45.878569 CA_CKDIV4_EN = 0
2237 12:26:45.881933 CA_PREDIV_EN = 0
2238 12:26:45.885091 PH8_DLY = 17
2239 12:26:45.885202 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2240 12:26:45.888699 DQ_AAMCK_DIV = 4
2241 12:26:45.891735 CA_AAMCK_DIV = 4
2242 12:26:45.895391 CA_ADMCK_DIV = 4
2243 12:26:45.898436 DQ_TRACK_CA_EN = 0
2244 12:26:45.901682 CA_PICK = 1200
2245 12:26:45.904886 CA_MCKIO = 1200
2246 12:26:45.904974 MCKIO_SEMI = 0
2247 12:26:45.908289 PLL_FREQ = 2366
2248 12:26:45.911490 DQ_UI_PI_RATIO = 32
2249 12:26:45.915000 CA_UI_PI_RATIO = 0
2250 12:26:45.918275 ===================================
2251 12:26:45.921678 ===================================
2252 12:26:45.924917 memory_type:LPDDR4
2253 12:26:45.925003 GP_NUM : 10
2254 12:26:45.928161 SRAM_EN : 1
2255 12:26:45.931841 MD32_EN : 0
2256 12:26:45.935190 ===================================
2257 12:26:45.935277 [ANA_INIT] >>>>>>>>>>>>>>
2258 12:26:45.938499 <<<<<< [CONFIGURE PHASE]: ANA_TX
2259 12:26:45.941846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2260 12:26:45.945024 ===================================
2261 12:26:45.948321 data_rate = 2400,PCW = 0X5b00
2262 12:26:45.951630 ===================================
2263 12:26:45.954883 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2264 12:26:45.961737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2265 12:26:45.964883 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2266 12:26:45.971349 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2267 12:26:45.974727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2268 12:26:45.978119 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2269 12:26:45.978199 [ANA_INIT] flow start
2270 12:26:45.981488 [ANA_INIT] PLL >>>>>>>>
2271 12:26:45.984681 [ANA_INIT] PLL <<<<<<<<
2272 12:26:45.987661 [ANA_INIT] MIDPI >>>>>>>>
2273 12:26:45.987750 [ANA_INIT] MIDPI <<<<<<<<
2274 12:26:45.991332 [ANA_INIT] DLL >>>>>>>>
2275 12:26:45.994481 [ANA_INIT] DLL <<<<<<<<
2276 12:26:45.994587 [ANA_INIT] flow end
2277 12:26:45.997884 ============ LP4 DIFF to SE enter ============
2278 12:26:46.004457 ============ LP4 DIFF to SE exit ============
2279 12:26:46.004539 [ANA_INIT] <<<<<<<<<<<<<
2280 12:26:46.007663 [Flow] Enable top DCM control >>>>>
2281 12:26:46.010992 [Flow] Enable top DCM control <<<<<
2282 12:26:46.014013 Enable DLL master slave shuffle
2283 12:26:46.020725 ==============================================================
2284 12:26:46.024068 Gating Mode config
2285 12:26:46.027489 ==============================================================
2286 12:26:46.030830 Config description:
2287 12:26:46.040645 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2288 12:26:46.047130 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2289 12:26:46.050482 SELPH_MODE 0: By rank 1: By Phase
2290 12:26:46.057390 ==============================================================
2291 12:26:46.060651 GAT_TRACK_EN = 1
2292 12:26:46.064008 RX_GATING_MODE = 2
2293 12:26:46.067269 RX_GATING_TRACK_MODE = 2
2294 12:26:46.067354 SELPH_MODE = 1
2295 12:26:46.070463 PICG_EARLY_EN = 1
2296 12:26:46.073877 VALID_LAT_VALUE = 1
2297 12:26:46.080502 ==============================================================
2298 12:26:46.083848 Enter into Gating configuration >>>>
2299 12:26:46.087277 Exit from Gating configuration <<<<
2300 12:26:46.090169 Enter into DVFS_PRE_config >>>>>
2301 12:26:46.100332 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2302 12:26:46.103676 Exit from DVFS_PRE_config <<<<<
2303 12:26:46.107273 Enter into PICG configuration >>>>
2304 12:26:46.110369 Exit from PICG configuration <<<<
2305 12:26:46.113611 [RX_INPUT] configuration >>>>>
2306 12:26:46.117169 [RX_INPUT] configuration <<<<<
2307 12:26:46.120248 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2308 12:26:46.126985 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2309 12:26:46.133508 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2310 12:26:46.140309 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2311 12:26:46.143459 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2312 12:26:46.150141 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2313 12:26:46.156601 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2314 12:26:46.159943 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2315 12:26:46.163322 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2316 12:26:46.166649 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2317 12:26:46.170061 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2318 12:26:46.176722 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2319 12:26:46.179992 ===================================
2320 12:26:46.183328 LPDDR4 DRAM CONFIGURATION
2321 12:26:46.186638 ===================================
2322 12:26:46.186717 EX_ROW_EN[0] = 0x0
2323 12:26:46.190064 EX_ROW_EN[1] = 0x0
2324 12:26:46.190138 LP4Y_EN = 0x0
2325 12:26:46.193464 WORK_FSP = 0x0
2326 12:26:46.193548 WL = 0x4
2327 12:26:46.196714 RL = 0x4
2328 12:26:46.196836 BL = 0x2
2329 12:26:46.199952 RPST = 0x0
2330 12:26:46.200062 RD_PRE = 0x0
2331 12:26:46.203627 WR_PRE = 0x1
2332 12:26:46.203711 WR_PST = 0x0
2333 12:26:46.206958 DBI_WR = 0x0
2334 12:26:46.207043 DBI_RD = 0x0
2335 12:26:46.210288 OTF = 0x1
2336 12:26:46.213068 ===================================
2337 12:26:46.216701 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2338 12:26:46.219847 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2339 12:26:46.226614 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2340 12:26:46.230071 ===================================
2341 12:26:46.230182 LPDDR4 DRAM CONFIGURATION
2342 12:26:46.233509 ===================================
2343 12:26:46.236554 EX_ROW_EN[0] = 0x10
2344 12:26:46.239750 EX_ROW_EN[1] = 0x0
2345 12:26:46.239880 LP4Y_EN = 0x0
2346 12:26:46.243241 WORK_FSP = 0x0
2347 12:26:46.243353 WL = 0x4
2348 12:26:46.246415 RL = 0x4
2349 12:26:46.246531 BL = 0x2
2350 12:26:46.249741 RPST = 0x0
2351 12:26:46.249857 RD_PRE = 0x0
2352 12:26:46.253160 WR_PRE = 0x1
2353 12:26:46.253271 WR_PST = 0x0
2354 12:26:46.256444 DBI_WR = 0x0
2355 12:26:46.256546 DBI_RD = 0x0
2356 12:26:46.259604 OTF = 0x1
2357 12:26:46.262885 ===================================
2358 12:26:46.269646 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2359 12:26:46.269731 ==
2360 12:26:46.272925 Dram Type= 6, Freq= 0, CH_0, rank 0
2361 12:26:46.276182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2362 12:26:46.276266 ==
2363 12:26:46.279905 [Duty_Offset_Calibration]
2364 12:26:46.279988 B0:2 B1:0 CA:1
2365 12:26:46.280054
2366 12:26:46.282760 [DutyScan_Calibration_Flow] k_type=0
2367 12:26:46.292714
2368 12:26:46.292853 ==CLK 0==
2369 12:26:46.296057 Final CLK duty delay cell = -4
2370 12:26:46.299378 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2371 12:26:46.302652 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2372 12:26:46.305918 [-4] AVG Duty = 4953%(X100)
2373 12:26:46.306000
2374 12:26:46.309293 CH0 CLK Duty spec in!! Max-Min= 156%
2375 12:26:46.312524 [DutyScan_Calibration_Flow] ====Done====
2376 12:26:46.312631
2377 12:26:46.315748 [DutyScan_Calibration_Flow] k_type=1
2378 12:26:46.331478
2379 12:26:46.331562 ==DQS 0 ==
2380 12:26:46.334944 Final DQS duty delay cell = 0
2381 12:26:46.338176 [0] MAX Duty = 5187%(X100), DQS PI = 30
2382 12:26:46.341525 [0] MIN Duty = 4938%(X100), DQS PI = 0
2383 12:26:46.341607 [0] AVG Duty = 5062%(X100)
2384 12:26:46.344609
2385 12:26:46.344716 ==DQS 1 ==
2386 12:26:46.348041 Final DQS duty delay cell = -4
2387 12:26:46.351611 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2388 12:26:46.355002 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2389 12:26:46.358313 [-4] AVG Duty = 5031%(X100)
2390 12:26:46.358395
2391 12:26:46.361461 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2392 12:26:46.361550
2393 12:26:46.364589 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2394 12:26:46.367861 [DutyScan_Calibration_Flow] ====Done====
2395 12:26:46.367944
2396 12:26:46.371167 [DutyScan_Calibration_Flow] k_type=3
2397 12:26:46.387504
2398 12:26:46.387588 ==DQM 0 ==
2399 12:26:46.390779 Final DQM duty delay cell = 0
2400 12:26:46.394026 [0] MAX Duty = 5062%(X100), DQS PI = 24
2401 12:26:46.397269 [0] MIN Duty = 4813%(X100), DQS PI = 2
2402 12:26:46.397352 [0] AVG Duty = 4937%(X100)
2403 12:26:46.400607
2404 12:26:46.400689 ==DQM 1 ==
2405 12:26:46.403862 Final DQM duty delay cell = -4
2406 12:26:46.407528 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2407 12:26:46.410428 [-4] MIN Duty = 4813%(X100), DQS PI = 14
2408 12:26:46.413917 [-4] AVG Duty = 4906%(X100)
2409 12:26:46.414001
2410 12:26:46.417098 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2411 12:26:46.417182
2412 12:26:46.420388 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2413 12:26:46.424167 [DutyScan_Calibration_Flow] ====Done====
2414 12:26:46.424251
2415 12:26:46.427012 [DutyScan_Calibration_Flow] k_type=2
2416 12:26:46.444481
2417 12:26:46.444569 ==DQ 0 ==
2418 12:26:46.447541 Final DQ duty delay cell = -4
2419 12:26:46.451016 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2420 12:26:46.454210 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2421 12:26:46.457693 [-4] AVG Duty = 4953%(X100)
2422 12:26:46.457779
2423 12:26:46.457845 ==DQ 1 ==
2424 12:26:46.461256 Final DQ duty delay cell = 4
2425 12:26:46.464358 [4] MAX Duty = 5093%(X100), DQS PI = 4
2426 12:26:46.467477 [4] MIN Duty = 5031%(X100), DQS PI = 0
2427 12:26:46.467561 [4] AVG Duty = 5062%(X100)
2428 12:26:46.471067
2429 12:26:46.474509 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2430 12:26:46.474594
2431 12:26:46.477669 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2432 12:26:46.480960 [DutyScan_Calibration_Flow] ====Done====
2433 12:26:46.481044 ==
2434 12:26:46.484326 Dram Type= 6, Freq= 0, CH_1, rank 0
2435 12:26:46.487685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2436 12:26:46.487769 ==
2437 12:26:46.490896 [Duty_Offset_Calibration]
2438 12:26:46.490980 B0:0 B1:-1 CA:2
2439 12:26:46.491047
2440 12:26:46.493795 [DutyScan_Calibration_Flow] k_type=0
2441 12:26:46.504402
2442 12:26:46.504486 ==CLK 0==
2443 12:26:46.507753 Final CLK duty delay cell = 0
2444 12:26:46.511164 [0] MAX Duty = 5156%(X100), DQS PI = 16
2445 12:26:46.514385 [0] MIN Duty = 4938%(X100), DQS PI = 44
2446 12:26:46.514469 [0] AVG Duty = 5047%(X100)
2447 12:26:46.517838
2448 12:26:46.521254 CH1 CLK Duty spec in!! Max-Min= 218%
2449 12:26:46.524122 [DutyScan_Calibration_Flow] ====Done====
2450 12:26:46.524206
2451 12:26:46.527565 [DutyScan_Calibration_Flow] k_type=1
2452 12:26:46.543654
2453 12:26:46.543740 ==DQS 0 ==
2454 12:26:46.547281 Final DQS duty delay cell = 0
2455 12:26:46.550413 [0] MAX Duty = 5093%(X100), DQS PI = 22
2456 12:26:46.553956 [0] MIN Duty = 4969%(X100), DQS PI = 0
2457 12:26:46.554042 [0] AVG Duty = 5031%(X100)
2458 12:26:46.556985
2459 12:26:46.557069 ==DQS 1 ==
2460 12:26:46.560545 Final DQS duty delay cell = 0
2461 12:26:46.563576 [0] MAX Duty = 5156%(X100), DQS PI = 0
2462 12:26:46.566997 [0] MIN Duty = 4875%(X100), DQS PI = 34
2463 12:26:46.567081 [0] AVG Duty = 5015%(X100)
2464 12:26:46.570428
2465 12:26:46.573540 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2466 12:26:46.573625
2467 12:26:46.577231 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2468 12:26:46.580442 [DutyScan_Calibration_Flow] ====Done====
2469 12:26:46.580526
2470 12:26:46.583760 [DutyScan_Calibration_Flow] k_type=3
2471 12:26:46.600278
2472 12:26:46.600364 ==DQM 0 ==
2473 12:26:46.603579 Final DQM duty delay cell = 4
2474 12:26:46.606894 [4] MAX Duty = 5093%(X100), DQS PI = 22
2475 12:26:46.610239 [4] MIN Duty = 4938%(X100), DQS PI = 48
2476 12:26:46.613570 [4] AVG Duty = 5015%(X100)
2477 12:26:46.613653
2478 12:26:46.613719 ==DQM 1 ==
2479 12:26:46.616639 Final DQM duty delay cell = -4
2480 12:26:46.619938 [-4] MAX Duty = 5031%(X100), DQS PI = 62
2481 12:26:46.623237 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2482 12:26:46.626520 [-4] AVG Duty = 4891%(X100)
2483 12:26:46.626622
2484 12:26:46.630287 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2485 12:26:46.630372
2486 12:26:46.633604 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2487 12:26:46.636843 [DutyScan_Calibration_Flow] ====Done====
2488 12:26:46.636942
2489 12:26:46.639923 [DutyScan_Calibration_Flow] k_type=2
2490 12:26:46.657292
2491 12:26:46.657411 ==DQ 0 ==
2492 12:26:46.660561 Final DQ duty delay cell = 0
2493 12:26:46.663677 [0] MAX Duty = 5062%(X100), DQS PI = 20
2494 12:26:46.667139 [0] MIN Duty = 4938%(X100), DQS PI = 44
2495 12:26:46.667225 [0] AVG Duty = 5000%(X100)
2496 12:26:46.670577
2497 12:26:46.670665 ==DQ 1 ==
2498 12:26:46.673811 Final DQ duty delay cell = 0
2499 12:26:46.676909 [0] MAX Duty = 5031%(X100), DQS PI = 2
2500 12:26:46.680469 [0] MIN Duty = 4813%(X100), DQS PI = 36
2501 12:26:46.680557 [0] AVG Duty = 4922%(X100)
2502 12:26:46.680626
2503 12:26:46.683644 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2504 12:26:46.686956
2505 12:26:46.690326 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2506 12:26:46.693629 [DutyScan_Calibration_Flow] ====Done====
2507 12:26:46.696999 nWR fixed to 30
2508 12:26:46.697085 [ModeRegInit_LP4] CH0 RK0
2509 12:26:46.700400 [ModeRegInit_LP4] CH0 RK1
2510 12:26:46.703716 [ModeRegInit_LP4] CH1 RK0
2511 12:26:46.706972 [ModeRegInit_LP4] CH1 RK1
2512 12:26:46.707057 match AC timing 7
2513 12:26:46.713202 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2514 12:26:46.716529 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2515 12:26:46.720039 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2516 12:26:46.726528 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2517 12:26:46.729840 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2518 12:26:46.729927 ==
2519 12:26:46.733175 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 12:26:46.736631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 12:26:46.736743 ==
2522 12:26:46.742743 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2523 12:26:46.749332 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2524 12:26:46.757294 [CA 0] Center 38 (7~69) winsize 63
2525 12:26:46.760507 [CA 1] Center 38 (7~69) winsize 63
2526 12:26:46.763613 [CA 2] Center 34 (4~65) winsize 62
2527 12:26:46.766755 [CA 3] Center 34 (4~65) winsize 62
2528 12:26:46.770365 [CA 4] Center 33 (3~64) winsize 62
2529 12:26:46.773476 [CA 5] Center 32 (3~62) winsize 60
2530 12:26:46.773581
2531 12:26:46.776840 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2532 12:26:46.776926
2533 12:26:46.780161 [CATrainingPosCal] consider 1 rank data
2534 12:26:46.783645 u2DelayCellTimex100 = 270/100 ps
2535 12:26:46.786712 CA0 delay=38 (7~69),Diff = 6 PI (28 cell)
2536 12:26:46.793602 CA1 delay=38 (7~69),Diff = 6 PI (28 cell)
2537 12:26:46.796776 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2538 12:26:46.800155 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2539 12:26:46.803513 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2540 12:26:46.806882 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2541 12:26:46.806968
2542 12:26:46.809888 CA PerBit enable=1, Macro0, CA PI delay=32
2543 12:26:46.809985
2544 12:26:46.813279 [CBTSetCACLKResult] CA Dly = 32
2545 12:26:46.813363 CS Dly: 6 (0~37)
2546 12:26:46.816605 ==
2547 12:26:46.819928 Dram Type= 6, Freq= 0, CH_0, rank 1
2548 12:26:46.823146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2549 12:26:46.823230 ==
2550 12:26:46.826276 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2551 12:26:46.833109 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2552 12:26:46.842435 [CA 0] Center 38 (8~69) winsize 62
2553 12:26:46.846154 [CA 1] Center 38 (7~69) winsize 63
2554 12:26:46.849425 [CA 2] Center 35 (5~66) winsize 62
2555 12:26:46.852676 [CA 3] Center 35 (5~66) winsize 62
2556 12:26:46.855963 [CA 4] Center 34 (4~65) winsize 62
2557 12:26:46.859127 [CA 5] Center 33 (3~64) winsize 62
2558 12:26:46.859212
2559 12:26:46.862506 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2560 12:26:46.862593
2561 12:26:46.865832 [CATrainingPosCal] consider 2 rank data
2562 12:26:46.869006 u2DelayCellTimex100 = 270/100 ps
2563 12:26:46.872533 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2564 12:26:46.878968 CA1 delay=38 (7~69),Diff = 6 PI (28 cell)
2565 12:26:46.882415 CA2 delay=35 (5~65),Diff = 3 PI (14 cell)
2566 12:26:46.885802 CA3 delay=35 (5~65),Diff = 3 PI (14 cell)
2567 12:26:46.889323 CA4 delay=34 (4~64),Diff = 2 PI (9 cell)
2568 12:26:46.892413 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2569 12:26:46.892511
2570 12:26:46.895442 CA PerBit enable=1, Macro0, CA PI delay=32
2571 12:26:46.895525
2572 12:26:46.898703 [CBTSetCACLKResult] CA Dly = 32
2573 12:26:46.902044 CS Dly: 7 (0~39)
2574 12:26:46.902128
2575 12:26:46.905758 ----->DramcWriteLeveling(PI) begin...
2576 12:26:46.905843 ==
2577 12:26:46.908590 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 12:26:46.912015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 12:26:46.912099 ==
2580 12:26:46.915328 Write leveling (Byte 0): 34 => 34
2581 12:26:46.918710 Write leveling (Byte 1): 29 => 29
2582 12:26:46.922091 DramcWriteLeveling(PI) end<-----
2583 12:26:46.922179
2584 12:26:46.922245 ==
2585 12:26:46.925395 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 12:26:46.928686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 12:26:46.928822 ==
2588 12:26:46.932055 [Gating] SW mode calibration
2589 12:26:46.938812 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2590 12:26:46.944931 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2591 12:26:46.948165 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2592 12:26:46.951701 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2593 12:26:46.958306 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 12:26:46.961481 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 12:26:46.964801 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 12:26:46.971486 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 12:26:46.974908 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2598 12:26:46.978303 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
2599 12:26:46.985003 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2600 12:26:46.988104 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 12:26:46.991598 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 12:26:46.998098 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 12:26:47.001629 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 12:26:47.004908 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 12:26:47.011065 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2606 12:26:47.014422 1 0 28 | B1->B0 | 2525 4646 | 1 0 | (0 0) (0 0)
2607 12:26:47.017756 1 1 0 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
2608 12:26:47.024326 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 12:26:47.027612 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 12:26:47.030929 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 12:26:47.037865 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 12:26:47.040693 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 12:26:47.043903 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 12:26:47.051126 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2615 12:26:47.054410 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2616 12:26:47.057634 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 12:26:47.064232 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 12:26:47.067550 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 12:26:47.070764 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 12:26:47.077455 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 12:26:47.080668 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 12:26:47.083854 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 12:26:47.090505 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 12:26:47.093984 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 12:26:47.097519 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 12:26:47.104151 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 12:26:47.107091 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 12:26:47.110625 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 12:26:47.117271 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2630 12:26:47.120530 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2631 12:26:47.123975 Total UI for P1: 0, mck2ui 16
2632 12:26:47.126837 best dqsien dly found for B0: ( 1, 3, 24)
2633 12:26:47.130214 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2634 12:26:47.133508 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 12:26:47.136718 Total UI for P1: 0, mck2ui 16
2636 12:26:47.140025 best dqsien dly found for B1: ( 1, 4, 0)
2637 12:26:47.146508 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2638 12:26:47.149861 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2639 12:26:47.149956
2640 12:26:47.153258 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2641 12:26:47.156488 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2642 12:26:47.160229 [Gating] SW calibration Done
2643 12:26:47.160317 ==
2644 12:26:47.163488 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 12:26:47.166725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 12:26:47.166816 ==
2647 12:26:47.170048 RX Vref Scan: 0
2648 12:26:47.170137
2649 12:26:47.170204 RX Vref 0 -> 0, step: 1
2650 12:26:47.170266
2651 12:26:47.173389 RX Delay -40 -> 252, step: 8
2652 12:26:47.176339 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2653 12:26:47.182985 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2654 12:26:47.186204 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2655 12:26:47.189861 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2656 12:26:47.193193 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2657 12:26:47.196560 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2658 12:26:47.203201 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2659 12:26:47.206301 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2660 12:26:47.209393 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2661 12:26:47.213146 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2662 12:26:47.215983 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2663 12:26:47.223037 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2664 12:26:47.225864 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2665 12:26:47.229173 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2666 12:26:47.232957 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2667 12:26:47.236103 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2668 12:26:47.238992 ==
2669 12:26:47.242643 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 12:26:47.245887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 12:26:47.245973 ==
2672 12:26:47.246040 DQS Delay:
2673 12:26:47.249215 DQS0 = 0, DQS1 = 0
2674 12:26:47.249304 DQM Delay:
2675 12:26:47.252448 DQM0 = 123, DQM1 = 110
2676 12:26:47.252564 DQ Delay:
2677 12:26:47.255811 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2678 12:26:47.259211 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2679 12:26:47.262552 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2680 12:26:47.265660 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2681 12:26:47.265811
2682 12:26:47.265910
2683 12:26:47.266009 ==
2684 12:26:47.268894 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 12:26:47.275466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 12:26:47.275589 ==
2687 12:26:47.275691
2688 12:26:47.275782
2689 12:26:47.275871 TX Vref Scan disable
2690 12:26:47.279197 == TX Byte 0 ==
2691 12:26:47.282517 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2692 12:26:47.285788 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2693 12:26:47.289078 == TX Byte 1 ==
2694 12:26:47.292734 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2695 12:26:47.299248 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2696 12:26:47.299358 ==
2697 12:26:47.302519 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 12:26:47.305789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 12:26:47.305865 ==
2700 12:26:47.317356 TX Vref=22, minBit 0, minWin=23, winSum=398
2701 12:26:47.320489 TX Vref=24, minBit 3, minWin=24, winSum=404
2702 12:26:47.323894 TX Vref=26, minBit 0, minWin=24, winSum=416
2703 12:26:47.327501 TX Vref=28, minBit 0, minWin=24, winSum=412
2704 12:26:47.330851 TX Vref=30, minBit 1, minWin=25, winSum=416
2705 12:26:47.334189 TX Vref=32, minBit 0, minWin=25, winSum=413
2706 12:26:47.340457 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 30
2707 12:26:47.340537
2708 12:26:47.343694 Final TX Range 1 Vref 30
2709 12:26:47.343823
2710 12:26:47.343906 ==
2711 12:26:47.347410 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 12:26:47.350674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 12:26:47.350751 ==
2714 12:26:47.350814
2715 12:26:47.353955
2716 12:26:47.354064 TX Vref Scan disable
2717 12:26:47.357411 == TX Byte 0 ==
2718 12:26:47.360687 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2719 12:26:47.364061 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2720 12:26:47.367435 == TX Byte 1 ==
2721 12:26:47.370466 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2722 12:26:47.373664 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2723 12:26:47.377093
2724 12:26:47.377181 [DATLAT]
2725 12:26:47.377288 Freq=1200, CH0 RK0
2726 12:26:47.377381
2727 12:26:47.380315 DATLAT Default: 0xd
2728 12:26:47.380387 0, 0xFFFF, sum = 0
2729 12:26:47.383564 1, 0xFFFF, sum = 0
2730 12:26:47.383683 2, 0xFFFF, sum = 0
2731 12:26:47.387080 3, 0xFFFF, sum = 0
2732 12:26:47.387183 4, 0xFFFF, sum = 0
2733 12:26:47.390793 5, 0xFFFF, sum = 0
2734 12:26:47.390898 6, 0xFFFF, sum = 0
2735 12:26:47.394094 7, 0xFFFF, sum = 0
2736 12:26:47.397242 8, 0xFFFF, sum = 0
2737 12:26:47.397349 9, 0xFFFF, sum = 0
2738 12:26:47.400434 10, 0xFFFF, sum = 0
2739 12:26:47.400542 11, 0xFFFF, sum = 0
2740 12:26:47.403964 12, 0x0, sum = 1
2741 12:26:47.404079 13, 0x0, sum = 2
2742 12:26:47.407298 14, 0x0, sum = 3
2743 12:26:47.407376 15, 0x0, sum = 4
2744 12:26:47.407479 best_step = 13
2745 12:26:47.407568
2746 12:26:47.410508 ==
2747 12:26:47.413880 Dram Type= 6, Freq= 0, CH_0, rank 0
2748 12:26:47.417094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2749 12:26:47.417178 ==
2750 12:26:47.417244 RX Vref Scan: 1
2751 12:26:47.417305
2752 12:26:47.420475 Set Vref Range= 32 -> 127
2753 12:26:47.420552
2754 12:26:47.423615 RX Vref 32 -> 127, step: 1
2755 12:26:47.423720
2756 12:26:47.427242 RX Delay -13 -> 252, step: 4
2757 12:26:47.427347
2758 12:26:47.430372 Set Vref, RX VrefLevel [Byte0]: 32
2759 12:26:47.433688 [Byte1]: 32
2760 12:26:47.433804
2761 12:26:47.437033 Set Vref, RX VrefLevel [Byte0]: 33
2762 12:26:47.440318 [Byte1]: 33
2763 12:26:47.440395
2764 12:26:47.443673 Set Vref, RX VrefLevel [Byte0]: 34
2765 12:26:47.446962 [Byte1]: 34
2766 12:26:47.451477
2767 12:26:47.451588 Set Vref, RX VrefLevel [Byte0]: 35
2768 12:26:47.454855 [Byte1]: 35
2769 12:26:47.459117
2770 12:26:47.459199 Set Vref, RX VrefLevel [Byte0]: 36
2771 12:26:47.462441 [Byte1]: 36
2772 12:26:47.467300
2773 12:26:47.467378 Set Vref, RX VrefLevel [Byte0]: 37
2774 12:26:47.470796 [Byte1]: 37
2775 12:26:47.475193
2776 12:26:47.475301 Set Vref, RX VrefLevel [Byte0]: 38
2777 12:26:47.478485 [Byte1]: 38
2778 12:26:47.482846
2779 12:26:47.482950 Set Vref, RX VrefLevel [Byte0]: 39
2780 12:26:47.486104 [Byte1]: 39
2781 12:26:47.490802
2782 12:26:47.490882 Set Vref, RX VrefLevel [Byte0]: 40
2783 12:26:47.494151 [Byte1]: 40
2784 12:26:47.498917
2785 12:26:47.498999 Set Vref, RX VrefLevel [Byte0]: 41
2786 12:26:47.502052 [Byte1]: 41
2787 12:26:47.506692
2788 12:26:47.506797 Set Vref, RX VrefLevel [Byte0]: 42
2789 12:26:47.509873 [Byte1]: 42
2790 12:26:47.514695
2791 12:26:47.514776 Set Vref, RX VrefLevel [Byte0]: 43
2792 12:26:47.517502 [Byte1]: 43
2793 12:26:47.522233
2794 12:26:47.522310 Set Vref, RX VrefLevel [Byte0]: 44
2795 12:26:47.525451 [Byte1]: 44
2796 12:26:47.530323
2797 12:26:47.530437 Set Vref, RX VrefLevel [Byte0]: 45
2798 12:26:47.533665 [Byte1]: 45
2799 12:26:47.538161
2800 12:26:47.538272 Set Vref, RX VrefLevel [Byte0]: 46
2801 12:26:47.541180 [Byte1]: 46
2802 12:26:47.545973
2803 12:26:47.546108 Set Vref, RX VrefLevel [Byte0]: 47
2804 12:26:47.549335 [Byte1]: 47
2805 12:26:47.554084
2806 12:26:47.554167 Set Vref, RX VrefLevel [Byte0]: 48
2807 12:26:47.557281 [Byte1]: 48
2808 12:26:47.561892
2809 12:26:47.561993 Set Vref, RX VrefLevel [Byte0]: 49
2810 12:26:47.565331 [Byte1]: 49
2811 12:26:47.569695
2812 12:26:47.569792 Set Vref, RX VrefLevel [Byte0]: 50
2813 12:26:47.572925 [Byte1]: 50
2814 12:26:47.577643
2815 12:26:47.577727 Set Vref, RX VrefLevel [Byte0]: 51
2816 12:26:47.580694 [Byte1]: 51
2817 12:26:47.585414
2818 12:26:47.585497 Set Vref, RX VrefLevel [Byte0]: 52
2819 12:26:47.588728 [Byte1]: 52
2820 12:26:47.593598
2821 12:26:47.593676 Set Vref, RX VrefLevel [Byte0]: 53
2822 12:26:47.596499 [Byte1]: 53
2823 12:26:47.601269
2824 12:26:47.601343 Set Vref, RX VrefLevel [Byte0]: 54
2825 12:26:47.604625 [Byte1]: 54
2826 12:26:47.609335
2827 12:26:47.609435 Set Vref, RX VrefLevel [Byte0]: 55
2828 12:26:47.612399 [Byte1]: 55
2829 12:26:47.616954
2830 12:26:47.617072 Set Vref, RX VrefLevel [Byte0]: 56
2831 12:26:47.620422 [Byte1]: 56
2832 12:26:47.625095
2833 12:26:47.625181 Set Vref, RX VrefLevel [Byte0]: 57
2834 12:26:47.628226 [Byte1]: 57
2835 12:26:47.632583
2836 12:26:47.632696 Set Vref, RX VrefLevel [Byte0]: 58
2837 12:26:47.639062 [Byte1]: 58
2838 12:26:47.639182
2839 12:26:47.642491 Set Vref, RX VrefLevel [Byte0]: 59
2840 12:26:47.645739 [Byte1]: 59
2841 12:26:47.645849
2842 12:26:47.649200 Set Vref, RX VrefLevel [Byte0]: 60
2843 12:26:47.652553 [Byte1]: 60
2844 12:26:47.656349
2845 12:26:47.656459 Set Vref, RX VrefLevel [Byte0]: 61
2846 12:26:47.659964 [Byte1]: 61
2847 12:26:47.664261
2848 12:26:47.664370 Set Vref, RX VrefLevel [Byte0]: 62
2849 12:26:47.667623 [Byte1]: 62
2850 12:26:47.672393
2851 12:26:47.672516 Set Vref, RX VrefLevel [Byte0]: 63
2852 12:26:47.675755 [Byte1]: 63
2853 12:26:47.680283
2854 12:26:47.680368 Set Vref, RX VrefLevel [Byte0]: 64
2855 12:26:47.683591 [Byte1]: 64
2856 12:26:47.687780
2857 12:26:47.687896 Set Vref, RX VrefLevel [Byte0]: 65
2858 12:26:47.691167 [Byte1]: 65
2859 12:26:47.695708
2860 12:26:47.695828 Set Vref, RX VrefLevel [Byte0]: 66
2861 12:26:47.699034 [Byte1]: 66
2862 12:26:47.703773
2863 12:26:47.703884 Set Vref, RX VrefLevel [Byte0]: 67
2864 12:26:47.707018 [Byte1]: 67
2865 12:26:47.711727
2866 12:26:47.711839 Set Vref, RX VrefLevel [Byte0]: 68
2867 12:26:47.714744 [Byte1]: 68
2868 12:26:47.719760
2869 12:26:47.719845 Final RX Vref Byte 0 = 59 to rank0
2870 12:26:47.723085 Final RX Vref Byte 1 = 48 to rank0
2871 12:26:47.726414 Final RX Vref Byte 0 = 59 to rank1
2872 12:26:47.729627 Final RX Vref Byte 1 = 48 to rank1==
2873 12:26:47.732718 Dram Type= 6, Freq= 0, CH_0, rank 0
2874 12:26:47.739290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2875 12:26:47.739408 ==
2876 12:26:47.739506 DQS Delay:
2877 12:26:47.739599 DQS0 = 0, DQS1 = 0
2878 12:26:47.742477 DQM Delay:
2879 12:26:47.742563 DQM0 = 123, DQM1 = 108
2880 12:26:47.746175 DQ Delay:
2881 12:26:47.749321 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2882 12:26:47.752538 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2883 12:26:47.756046 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =104
2884 12:26:47.759553 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =116
2885 12:26:47.759645
2886 12:26:47.759714
2887 12:26:47.769217 [DQSOSCAuto] RK0, (LSB)MR18= 0xa07, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2888 12:26:47.769325 CH0 RK0: MR19=404, MR18=A07
2889 12:26:47.775741 CH0_RK0: MR19=0x404, MR18=0xA07, DQSOSC=406, MR23=63, INC=39, DEC=26
2890 12:26:47.775835
2891 12:26:47.779438 ----->DramcWriteLeveling(PI) begin...
2892 12:26:47.779560 ==
2893 12:26:47.782769 Dram Type= 6, Freq= 0, CH_0, rank 1
2894 12:26:47.785925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2895 12:26:47.788981 ==
2896 12:26:47.789070 Write leveling (Byte 0): 34 => 34
2897 12:26:47.792347 Write leveling (Byte 1): 30 => 30
2898 12:26:47.795702 DramcWriteLeveling(PI) end<-----
2899 12:26:47.795822
2900 12:26:47.795898 ==
2901 12:26:47.799000 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 12:26:47.805758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 12:26:47.805877 ==
2904 12:26:47.808957 [Gating] SW mode calibration
2905 12:26:47.815619 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2906 12:26:47.819171 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2907 12:26:47.825668 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
2908 12:26:47.828888 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 12:26:47.832188 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 12:26:47.839169 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 12:26:47.842475 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 12:26:47.845626 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 12:26:47.848840 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2914 12:26:47.855729 0 15 28 | B1->B0 | 2f2f 2a2a | 1 1 | (1 0) (1 0)
2915 12:26:47.858933 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2916 12:26:47.862443 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 12:26:47.868679 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 12:26:47.872066 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 12:26:47.875458 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 12:26:47.882053 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 12:26:47.885334 1 0 24 | B1->B0 | 2525 2a29 | 0 1 | (0 0) (0 0)
2922 12:26:47.888551 1 0 28 | B1->B0 | 3939 4141 | 1 0 | (0 0) (0 0)
2923 12:26:47.895412 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 12:26:47.898762 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 12:26:47.902052 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 12:26:47.908632 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 12:26:47.912005 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 12:26:47.915273 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 12:26:47.921794 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 12:26:47.924918 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2931 12:26:47.928163 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2932 12:26:47.934870 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 12:26:47.938138 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 12:26:47.941734 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 12:26:47.948231 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 12:26:47.951493 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 12:26:47.954841 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 12:26:47.961623 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 12:26:47.964646 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 12:26:47.968084 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 12:26:47.974913 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 12:26:47.978165 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 12:26:47.981500 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 12:26:47.988488 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 12:26:47.991678 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 12:26:47.994793 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2947 12:26:47.998591 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 12:26:48.001922 Total UI for P1: 0, mck2ui 16
2949 12:26:48.004849 best dqsien dly found for B0: ( 1, 3, 28)
2950 12:26:48.008256 Total UI for P1: 0, mck2ui 16
2951 12:26:48.011619 best dqsien dly found for B1: ( 1, 3, 28)
2952 12:26:48.014929 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2953 12:26:48.021446 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2954 12:26:48.021531
2955 12:26:48.024820 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2956 12:26:48.028489 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2957 12:26:48.031641 [Gating] SW calibration Done
2958 12:26:48.031748 ==
2959 12:26:48.034888 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 12:26:48.038229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 12:26:48.038307 ==
2962 12:26:48.038371 RX Vref Scan: 0
2963 12:26:48.041522
2964 12:26:48.041606 RX Vref 0 -> 0, step: 1
2965 12:26:48.041672
2966 12:26:48.044598 RX Delay -40 -> 252, step: 8
2967 12:26:48.048041 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2968 12:26:48.051401 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2969 12:26:48.057914 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2970 12:26:48.061740 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2971 12:26:48.064836 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2972 12:26:48.068062 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2973 12:26:48.071015 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2974 12:26:48.077869 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2975 12:26:48.081495 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2976 12:26:48.084671 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2977 12:26:48.088036 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2978 12:26:48.091154 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2979 12:26:48.097861 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2980 12:26:48.101136 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2981 12:26:48.104375 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2982 12:26:48.107728 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2983 12:26:48.107841 ==
2984 12:26:48.111459 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 12:26:48.118162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 12:26:48.118251 ==
2987 12:26:48.118318 DQS Delay:
2988 12:26:48.121086 DQS0 = 0, DQS1 = 0
2989 12:26:48.121170 DQM Delay:
2990 12:26:48.121236 DQM0 = 120, DQM1 = 108
2991 12:26:48.124687 DQ Delay:
2992 12:26:48.128099 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2993 12:26:48.131273 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2994 12:26:48.134839 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2995 12:26:48.138143 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2996 12:26:48.138220
2997 12:26:48.138286
2998 12:26:48.138345 ==
2999 12:26:48.140839 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 12:26:48.144687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 12:26:48.144824 ==
3002 12:26:48.147928
3003 12:26:48.148035
3004 12:26:48.148100 TX Vref Scan disable
3005 12:26:48.151312 == TX Byte 0 ==
3006 12:26:48.154577 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3007 12:26:48.157923 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3008 12:26:48.161192 == TX Byte 1 ==
3009 12:26:48.164482 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3010 12:26:48.167868 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3011 12:26:48.167965 ==
3012 12:26:48.170925 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 12:26:48.177700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 12:26:48.177794 ==
3015 12:26:48.188514 TX Vref=22, minBit 2, minWin=23, winSum=399
3016 12:26:48.191848 TX Vref=24, minBit 0, minWin=24, winSum=411
3017 12:26:48.195132 TX Vref=26, minBit 2, minWin=24, winSum=416
3018 12:26:48.198499 TX Vref=28, minBit 0, minWin=25, winSum=419
3019 12:26:48.201743 TX Vref=30, minBit 1, minWin=24, winSum=416
3020 12:26:48.208435 TX Vref=32, minBit 1, minWin=24, winSum=417
3021 12:26:48.211683 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
3022 12:26:48.211772
3023 12:26:48.215052 Final TX Range 1 Vref 28
3024 12:26:48.215138
3025 12:26:48.215205 ==
3026 12:26:48.218357 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 12:26:48.221559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 12:26:48.224750 ==
3029 12:26:48.224846
3030 12:26:48.224913
3031 12:26:48.224976 TX Vref Scan disable
3032 12:26:48.228212 == TX Byte 0 ==
3033 12:26:48.231510 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3034 12:26:48.238335 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3035 12:26:48.238420 == TX Byte 1 ==
3036 12:26:48.241607 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3037 12:26:48.248308 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3038 12:26:48.248423
3039 12:26:48.248518 [DATLAT]
3040 12:26:48.248611 Freq=1200, CH0 RK1
3041 12:26:48.248712
3042 12:26:48.251506 DATLAT Default: 0xd
3043 12:26:48.251601 0, 0xFFFF, sum = 0
3044 12:26:48.254677 1, 0xFFFF, sum = 0
3045 12:26:48.258004 2, 0xFFFF, sum = 0
3046 12:26:48.258101 3, 0xFFFF, sum = 0
3047 12:26:48.261656 4, 0xFFFF, sum = 0
3048 12:26:48.261742 5, 0xFFFF, sum = 0
3049 12:26:48.264423 6, 0xFFFF, sum = 0
3050 12:26:48.264509 7, 0xFFFF, sum = 0
3051 12:26:48.268208 8, 0xFFFF, sum = 0
3052 12:26:48.268289 9, 0xFFFF, sum = 0
3053 12:26:48.271467 10, 0xFFFF, sum = 0
3054 12:26:48.271578 11, 0xFFFF, sum = 0
3055 12:26:48.274724 12, 0x0, sum = 1
3056 12:26:48.274847 13, 0x0, sum = 2
3057 12:26:48.277835 14, 0x0, sum = 3
3058 12:26:48.277951 15, 0x0, sum = 4
3059 12:26:48.281410 best_step = 13
3060 12:26:48.281501
3061 12:26:48.281572 ==
3062 12:26:48.284495 Dram Type= 6, Freq= 0, CH_0, rank 1
3063 12:26:48.288081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 12:26:48.288170 ==
3065 12:26:48.291153 RX Vref Scan: 0
3066 12:26:48.291239
3067 12:26:48.291307 RX Vref 0 -> 0, step: 1
3068 12:26:48.291372
3069 12:26:48.294748 RX Delay -21 -> 252, step: 4
3070 12:26:48.301006 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3071 12:26:48.304168 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3072 12:26:48.307443 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3073 12:26:48.311003 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3074 12:26:48.314351 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3075 12:26:48.320933 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3076 12:26:48.324304 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3077 12:26:48.327520 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3078 12:26:48.330935 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3079 12:26:48.333872 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3080 12:26:48.340744 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3081 12:26:48.343914 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3082 12:26:48.347405 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3083 12:26:48.350795 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3084 12:26:48.354009 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3085 12:26:48.360466 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3086 12:26:48.360561 ==
3087 12:26:48.363650 Dram Type= 6, Freq= 0, CH_0, rank 1
3088 12:26:48.367236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3089 12:26:48.367332 ==
3090 12:26:48.367402 DQS Delay:
3091 12:26:48.370674 DQS0 = 0, DQS1 = 0
3092 12:26:48.370767 DQM Delay:
3093 12:26:48.373956 DQM0 = 119, DQM1 = 107
3094 12:26:48.374073 DQ Delay:
3095 12:26:48.376872 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =116
3096 12:26:48.380572 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3097 12:26:48.383877 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =104
3098 12:26:48.387336 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3099 12:26:48.387444
3100 12:26:48.387539
3101 12:26:48.396783 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3102 12:26:48.400396 CH0 RK1: MR19=403, MR18=BF2
3103 12:26:48.403554 CH0_RK1: MR19=0x403, MR18=0xBF2, DQSOSC=405, MR23=63, INC=39, DEC=26
3104 12:26:48.406801 [RxdqsGatingPostProcess] freq 1200
3105 12:26:48.413564 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3106 12:26:48.416867 best DQS0 dly(2T, 0.5T) = (0, 11)
3107 12:26:48.420158 best DQS1 dly(2T, 0.5T) = (0, 12)
3108 12:26:48.423410 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3109 12:26:48.426697 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3110 12:26:48.430008 best DQS0 dly(2T, 0.5T) = (0, 11)
3111 12:26:48.433382 best DQS1 dly(2T, 0.5T) = (0, 11)
3112 12:26:48.436732 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3113 12:26:48.439977 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3114 12:26:48.443309 Pre-setting of DQS Precalculation
3115 12:26:48.446571 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3116 12:26:48.446653 ==
3117 12:26:48.449853 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 12:26:48.453216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 12:26:48.456495 ==
3120 12:26:48.460103 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3121 12:26:48.466460 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3122 12:26:48.474470 [CA 0] Center 37 (7~67) winsize 61
3123 12:26:48.477733 [CA 1] Center 37 (7~68) winsize 62
3124 12:26:48.480962 [CA 2] Center 34 (4~65) winsize 62
3125 12:26:48.484296 [CA 3] Center 33 (3~64) winsize 62
3126 12:26:48.487543 [CA 4] Center 33 (3~64) winsize 62
3127 12:26:48.491306 [CA 5] Center 33 (3~63) winsize 61
3128 12:26:48.491420
3129 12:26:48.494560 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3130 12:26:48.494647
3131 12:26:48.497709 [CATrainingPosCal] consider 1 rank data
3132 12:26:48.501131 u2DelayCellTimex100 = 270/100 ps
3133 12:26:48.504701 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3134 12:26:48.507936 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3135 12:26:48.514787 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3136 12:26:48.517884 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3137 12:26:48.521102 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3138 12:26:48.524270 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3139 12:26:48.524346
3140 12:26:48.527653 CA PerBit enable=1, Macro0, CA PI delay=33
3141 12:26:48.527747
3142 12:26:48.531033 [CBTSetCACLKResult] CA Dly = 33
3143 12:26:48.531108 CS Dly: 5 (0~36)
3144 12:26:48.534350 ==
3145 12:26:48.534442 Dram Type= 6, Freq= 0, CH_1, rank 1
3146 12:26:48.540976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3147 12:26:48.541054 ==
3148 12:26:48.544221 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3149 12:26:48.550745 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3150 12:26:48.560104 [CA 0] Center 38 (8~68) winsize 61
3151 12:26:48.563335 [CA 1] Center 37 (7~68) winsize 62
3152 12:26:48.566535 [CA 2] Center 35 (5~66) winsize 62
3153 12:26:48.569751 [CA 3] Center 34 (4~64) winsize 61
3154 12:26:48.573369 [CA 4] Center 34 (4~64) winsize 61
3155 12:26:48.576705 [CA 5] Center 33 (3~64) winsize 62
3156 12:26:48.576821
3157 12:26:48.580097 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3158 12:26:48.580198
3159 12:26:48.583528 [CATrainingPosCal] consider 2 rank data
3160 12:26:48.586806 u2DelayCellTimex100 = 270/100 ps
3161 12:26:48.590109 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3162 12:26:48.593455 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3163 12:26:48.600117 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3164 12:26:48.603270 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3165 12:26:48.606728 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3166 12:26:48.609788 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3167 12:26:48.609901
3168 12:26:48.613336 CA PerBit enable=1, Macro0, CA PI delay=33
3169 12:26:48.613420
3170 12:26:48.616407 [CBTSetCACLKResult] CA Dly = 33
3171 12:26:48.616492 CS Dly: 6 (0~38)
3172 12:26:48.616559
3173 12:26:48.623117 ----->DramcWriteLeveling(PI) begin...
3174 12:26:48.623202 ==
3175 12:26:48.626746 Dram Type= 6, Freq= 0, CH_1, rank 0
3176 12:26:48.629831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3177 12:26:48.629916 ==
3178 12:26:48.633111 Write leveling (Byte 0): 26 => 26
3179 12:26:48.636320 Write leveling (Byte 1): 28 => 28
3180 12:26:48.639609 DramcWriteLeveling(PI) end<-----
3181 12:26:48.639763
3182 12:26:48.639893 ==
3183 12:26:48.642875 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 12:26:48.646189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 12:26:48.646264 ==
3186 12:26:48.649542 [Gating] SW mode calibration
3187 12:26:48.656404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3188 12:26:48.663028 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3189 12:26:48.666259 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 12:26:48.669385 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 12:26:48.675998 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 12:26:48.679676 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 12:26:48.682567 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 12:26:48.689254 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3195 12:26:48.692617 0 15 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
3196 12:26:48.695847 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3197 12:26:48.702659 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 12:26:48.706113 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 12:26:48.709498 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 12:26:48.716081 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 12:26:48.719204 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 12:26:48.722752 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 12:26:48.725792 1 0 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3204 12:26:48.732335 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 12:26:48.735924 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 12:26:48.738999 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 12:26:48.745638 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 12:26:48.748914 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 12:26:48.752286 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 12:26:48.759126 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 12:26:48.762506 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3212 12:26:48.765826 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3213 12:26:48.772299 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 12:26:48.775570 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 12:26:48.778895 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 12:26:48.785484 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 12:26:48.788699 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 12:26:48.792135 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 12:26:48.798730 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 12:26:48.802122 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 12:26:48.805356 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 12:26:48.811869 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 12:26:48.815066 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 12:26:48.818791 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 12:26:48.825130 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 12:26:48.828595 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 12:26:48.832110 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3228 12:26:48.838674 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 12:26:48.838760 Total UI for P1: 0, mck2ui 16
3230 12:26:48.845290 best dqsien dly found for B0: ( 1, 3, 24)
3231 12:26:48.845377 Total UI for P1: 0, mck2ui 16
3232 12:26:48.848520 best dqsien dly found for B1: ( 1, 3, 24)
3233 12:26:48.855506 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3234 12:26:48.858369 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3235 12:26:48.858454
3236 12:26:48.861722 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3237 12:26:48.865409 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3238 12:26:48.868709 [Gating] SW calibration Done
3239 12:26:48.868835 ==
3240 12:26:48.871994 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 12:26:48.875235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 12:26:48.875320 ==
3243 12:26:48.878404 RX Vref Scan: 0
3244 12:26:48.878488
3245 12:26:48.878553 RX Vref 0 -> 0, step: 1
3246 12:26:48.878614
3247 12:26:48.881695 RX Delay -40 -> 252, step: 8
3248 12:26:48.884919 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3249 12:26:48.891919 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3250 12:26:48.895252 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3251 12:26:48.898081 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3252 12:26:48.901890 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3253 12:26:48.904681 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3254 12:26:48.911706 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3255 12:26:48.914841 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3256 12:26:48.918116 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3257 12:26:48.921530 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3258 12:26:48.925005 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3259 12:26:48.931476 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3260 12:26:48.934631 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3261 12:26:48.938091 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3262 12:26:48.941608 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3263 12:26:48.944642 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3264 12:26:48.948120 ==
3265 12:26:48.951382 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 12:26:48.954435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 12:26:48.954528 ==
3268 12:26:48.954608 DQS Delay:
3269 12:26:48.957911 DQS0 = 0, DQS1 = 0
3270 12:26:48.958002 DQM Delay:
3271 12:26:48.961332 DQM0 = 119, DQM1 = 113
3272 12:26:48.961453 DQ Delay:
3273 12:26:48.964515 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3274 12:26:48.967713 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3275 12:26:48.971205 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =107
3276 12:26:48.974411 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3277 12:26:48.974511
3278 12:26:48.974593
3279 12:26:48.974701 ==
3280 12:26:48.977849 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 12:26:48.984599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 12:26:48.984709 ==
3283 12:26:48.984821
3284 12:26:48.984919
3285 12:26:48.985000 TX Vref Scan disable
3286 12:26:48.988482 == TX Byte 0 ==
3287 12:26:48.991643 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3288 12:26:48.998293 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3289 12:26:48.998377 == TX Byte 1 ==
3290 12:26:49.001714 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3291 12:26:49.008346 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3292 12:26:49.008432 ==
3293 12:26:49.011678 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 12:26:49.014890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 12:26:49.014986 ==
3296 12:26:49.025958 TX Vref=22, minBit 8, minWin=24, winSum=400
3297 12:26:49.029237 TX Vref=24, minBit 3, minWin=24, winSum=403
3298 12:26:49.032477 TX Vref=26, minBit 10, minWin=24, winSum=408
3299 12:26:49.035829 TX Vref=28, minBit 8, minWin=25, winSum=416
3300 12:26:49.039263 TX Vref=30, minBit 10, minWin=25, winSum=419
3301 12:26:49.045694 TX Vref=32, minBit 9, minWin=25, winSum=420
3302 12:26:49.049110 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 32
3303 12:26:49.049198
3304 12:26:49.052442 Final TX Range 1 Vref 32
3305 12:26:49.052528
3306 12:26:49.052595 ==
3307 12:26:49.055842 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 12:26:49.059072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 12:26:49.059160 ==
3310 12:26:49.062337
3311 12:26:49.062422
3312 12:26:49.062490 TX Vref Scan disable
3313 12:26:49.065901 == TX Byte 0 ==
3314 12:26:49.069141 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3315 12:26:49.072177 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3316 12:26:49.075656 == TX Byte 1 ==
3317 12:26:49.078950 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3318 12:26:49.082690 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3319 12:26:49.085763
3320 12:26:49.085850 [DATLAT]
3321 12:26:49.085957 Freq=1200, CH1 RK0
3322 12:26:49.086060
3323 12:26:49.089006 DATLAT Default: 0xd
3324 12:26:49.089094 0, 0xFFFF, sum = 0
3325 12:26:49.092370 1, 0xFFFF, sum = 0
3326 12:26:49.092448 2, 0xFFFF, sum = 0
3327 12:26:49.095608 3, 0xFFFF, sum = 0
3328 12:26:49.098825 4, 0xFFFF, sum = 0
3329 12:26:49.098902 5, 0xFFFF, sum = 0
3330 12:26:49.102225 6, 0xFFFF, sum = 0
3331 12:26:49.102313 7, 0xFFFF, sum = 0
3332 12:26:49.105595 8, 0xFFFF, sum = 0
3333 12:26:49.105683 9, 0xFFFF, sum = 0
3334 12:26:49.108816 10, 0xFFFF, sum = 0
3335 12:26:49.108902 11, 0xFFFF, sum = 0
3336 12:26:49.112251 12, 0x0, sum = 1
3337 12:26:49.112338 13, 0x0, sum = 2
3338 12:26:49.115598 14, 0x0, sum = 3
3339 12:26:49.115683 15, 0x0, sum = 4
3340 12:26:49.115768 best_step = 13
3341 12:26:49.118826
3342 12:26:49.118910 ==
3343 12:26:49.122514 Dram Type= 6, Freq= 0, CH_1, rank 0
3344 12:26:49.125717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3345 12:26:49.125804 ==
3346 12:26:49.125869 RX Vref Scan: 1
3347 12:26:49.125930
3348 12:26:49.129044 Set Vref Range= 32 -> 127
3349 12:26:49.129152
3350 12:26:49.132474 RX Vref 32 -> 127, step: 1
3351 12:26:49.132563
3352 12:26:49.135574 RX Delay -5 -> 252, step: 4
3353 12:26:49.135686
3354 12:26:49.138881 Set Vref, RX VrefLevel [Byte0]: 32
3355 12:26:49.142247 [Byte1]: 32
3356 12:26:49.142349
3357 12:26:49.145650 Set Vref, RX VrefLevel [Byte0]: 33
3358 12:26:49.148933 [Byte1]: 33
3359 12:26:49.149045
3360 12:26:49.152000 Set Vref, RX VrefLevel [Byte0]: 34
3361 12:26:49.155369 [Byte1]: 34
3362 12:26:49.159700
3363 12:26:49.159809 Set Vref, RX VrefLevel [Byte0]: 35
3364 12:26:49.163153 [Byte1]: 35
3365 12:26:49.167602
3366 12:26:49.167714 Set Vref, RX VrefLevel [Byte0]: 36
3367 12:26:49.170823 [Byte1]: 36
3368 12:26:49.175631
3369 12:26:49.175738 Set Vref, RX VrefLevel [Byte0]: 37
3370 12:26:49.178937 [Byte1]: 37
3371 12:26:49.183251
3372 12:26:49.183331 Set Vref, RX VrefLevel [Byte0]: 38
3373 12:26:49.186861 [Byte1]: 38
3374 12:26:49.191402
3375 12:26:49.191507 Set Vref, RX VrefLevel [Byte0]: 39
3376 12:26:49.194773 [Byte1]: 39
3377 12:26:49.198996
3378 12:26:49.199069 Set Vref, RX VrefLevel [Byte0]: 40
3379 12:26:49.202276 [Byte1]: 40
3380 12:26:49.206950
3381 12:26:49.207059 Set Vref, RX VrefLevel [Byte0]: 41
3382 12:26:49.210305 [Byte1]: 41
3383 12:26:49.214639
3384 12:26:49.214748 Set Vref, RX VrefLevel [Byte0]: 42
3385 12:26:49.218418 [Byte1]: 42
3386 12:26:49.222611
3387 12:26:49.222696 Set Vref, RX VrefLevel [Byte0]: 43
3388 12:26:49.225883 [Byte1]: 43
3389 12:26:49.230600
3390 12:26:49.230684 Set Vref, RX VrefLevel [Byte0]: 44
3391 12:26:49.233833 [Byte1]: 44
3392 12:26:49.238650
3393 12:26:49.238732 Set Vref, RX VrefLevel [Byte0]: 45
3394 12:26:49.241634 [Byte1]: 45
3395 12:26:49.246277
3396 12:26:49.246359 Set Vref, RX VrefLevel [Byte0]: 46
3397 12:26:49.249607 [Byte1]: 46
3398 12:26:49.254041
3399 12:26:49.254123 Set Vref, RX VrefLevel [Byte0]: 47
3400 12:26:49.260616 [Byte1]: 47
3401 12:26:49.260700
3402 12:26:49.263927 Set Vref, RX VrefLevel [Byte0]: 48
3403 12:26:49.267189 [Byte1]: 48
3404 12:26:49.267271
3405 12:26:49.270407 Set Vref, RX VrefLevel [Byte0]: 49
3406 12:26:49.273658 [Byte1]: 49
3407 12:26:49.277682
3408 12:26:49.277764 Set Vref, RX VrefLevel [Byte0]: 50
3409 12:26:49.280883 [Byte1]: 50
3410 12:26:49.285669
3411 12:26:49.285751 Set Vref, RX VrefLevel [Byte0]: 51
3412 12:26:49.289012 [Byte1]: 51
3413 12:26:49.293091
3414 12:26:49.293200 Set Vref, RX VrefLevel [Byte0]: 52
3415 12:26:49.296689 [Byte1]: 52
3416 12:26:49.301425
3417 12:26:49.301507 Set Vref, RX VrefLevel [Byte0]: 53
3418 12:26:49.304646 [Byte1]: 53
3419 12:26:49.308891
3420 12:26:49.308973 Set Vref, RX VrefLevel [Byte0]: 54
3421 12:26:49.312209 [Byte1]: 54
3422 12:26:49.317022
3423 12:26:49.317104 Set Vref, RX VrefLevel [Byte0]: 55
3424 12:26:49.320257 [Byte1]: 55
3425 12:26:49.324503
3426 12:26:49.324586 Set Vref, RX VrefLevel [Byte0]: 56
3427 12:26:49.328207 [Byte1]: 56
3428 12:26:49.332391
3429 12:26:49.332467 Set Vref, RX VrefLevel [Byte0]: 57
3430 12:26:49.335783 [Byte1]: 57
3431 12:26:49.340402
3432 12:26:49.340485 Set Vref, RX VrefLevel [Byte0]: 58
3433 12:26:49.343666 [Byte1]: 58
3434 12:26:49.348492
3435 12:26:49.348575 Set Vref, RX VrefLevel [Byte0]: 59
3436 12:26:49.351734 [Byte1]: 59
3437 12:26:49.355917
3438 12:26:49.359132 Set Vref, RX VrefLevel [Byte0]: 60
3439 12:26:49.362701 [Byte1]: 60
3440 12:26:49.362784
3441 12:26:49.366065 Set Vref, RX VrefLevel [Byte0]: 61
3442 12:26:49.369429 [Byte1]: 61
3443 12:26:49.369512
3444 12:26:49.372660 Set Vref, RX VrefLevel [Byte0]: 62
3445 12:26:49.375898 [Byte1]: 62
3446 12:26:49.379604
3447 12:26:49.379686 Set Vref, RX VrefLevel [Byte0]: 63
3448 12:26:49.382832 [Byte1]: 63
3449 12:26:49.387637
3450 12:26:49.387720 Set Vref, RX VrefLevel [Byte0]: 64
3451 12:26:49.390697 [Byte1]: 64
3452 12:26:49.395207
3453 12:26:49.395290 Set Vref, RX VrefLevel [Byte0]: 65
3454 12:26:49.398639 [Byte1]: 65
3455 12:26:49.403432
3456 12:26:49.403508 Set Vref, RX VrefLevel [Byte0]: 66
3457 12:26:49.406734 [Byte1]: 66
3458 12:26:49.410874
3459 12:26:49.410949 Set Vref, RX VrefLevel [Byte0]: 67
3460 12:26:49.414277 [Byte1]: 67
3461 12:26:49.418960
3462 12:26:49.419032 Set Vref, RX VrefLevel [Byte0]: 68
3463 12:26:49.422436 [Byte1]: 68
3464 12:26:49.426674
3465 12:26:49.426757 Set Vref, RX VrefLevel [Byte0]: 69
3466 12:26:49.430131 [Byte1]: 69
3467 12:26:49.434685
3468 12:26:49.434767 Final RX Vref Byte 0 = 53 to rank0
3469 12:26:49.437890 Final RX Vref Byte 1 = 51 to rank0
3470 12:26:49.441281 Final RX Vref Byte 0 = 53 to rank1
3471 12:26:49.444488 Final RX Vref Byte 1 = 51 to rank1==
3472 12:26:49.447848 Dram Type= 6, Freq= 0, CH_1, rank 0
3473 12:26:49.454512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 12:26:49.454639 ==
3475 12:26:49.454712 DQS Delay:
3476 12:26:49.457740 DQS0 = 0, DQS1 = 0
3477 12:26:49.457853 DQM Delay:
3478 12:26:49.457972 DQM0 = 119, DQM1 = 112
3479 12:26:49.460939 DQ Delay:
3480 12:26:49.464073 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =120
3481 12:26:49.467710 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3482 12:26:49.471048 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =104
3483 12:26:49.474453 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118
3484 12:26:49.474538
3485 12:26:49.474643
3486 12:26:49.484290 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3487 12:26:49.484393 CH1 RK0: MR19=304, MR18=FE12
3488 12:26:49.491078 CH1_RK0: MR19=0x304, MR18=0xFE12, DQSOSC=403, MR23=63, INC=40, DEC=26
3489 12:26:49.491180
3490 12:26:49.494340 ----->DramcWriteLeveling(PI) begin...
3491 12:26:49.494437 ==
3492 12:26:49.497574 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 12:26:49.503953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 12:26:49.504039 ==
3495 12:26:49.507289 Write leveling (Byte 0): 25 => 25
3496 12:26:49.510583 Write leveling (Byte 1): 30 => 30
3497 12:26:49.510664 DramcWriteLeveling(PI) end<-----
3498 12:26:49.510736
3499 12:26:49.513866 ==
3500 12:26:49.517156 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 12:26:49.520932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 12:26:49.521029 ==
3503 12:26:49.524296 [Gating] SW mode calibration
3504 12:26:49.530953 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3505 12:26:49.534301 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3506 12:26:49.541004 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 12:26:49.543782 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 12:26:49.547532 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 12:26:49.553764 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 12:26:49.557018 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 12:26:49.560318 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 12:26:49.567357 0 15 24 | B1->B0 | 2a2a 3434 | 0 0 | (0 1) (1 0)
3513 12:26:49.570577 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3514 12:26:49.573767 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 12:26:49.580797 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 12:26:49.583927 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 12:26:49.587326 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 12:26:49.593907 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 12:26:49.597094 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 12:26:49.600582 1 0 24 | B1->B0 | 4141 2b2b | 0 1 | (0 0) (0 0)
3521 12:26:49.603902 1 0 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
3522 12:26:49.610481 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 12:26:49.613887 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 12:26:49.617024 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 12:26:49.623764 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 12:26:49.627134 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 12:26:49.630421 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 12:26:49.637105 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3529 12:26:49.640417 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3530 12:26:49.643545 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 12:26:49.650151 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 12:26:49.653469 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 12:26:49.656803 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 12:26:49.663507 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 12:26:49.666756 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 12:26:49.670082 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 12:26:49.676828 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 12:26:49.680124 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 12:26:49.682985 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 12:26:49.689861 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 12:26:49.693112 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 12:26:49.696374 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 12:26:49.702823 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 12:26:49.706082 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3545 12:26:49.709715 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3546 12:26:49.716148 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 12:26:49.719711 Total UI for P1: 0, mck2ui 16
3548 12:26:49.722650 best dqsien dly found for B0: ( 1, 3, 26)
3549 12:26:49.726159 Total UI for P1: 0, mck2ui 16
3550 12:26:49.729349 best dqsien dly found for B1: ( 1, 3, 26)
3551 12:26:49.732613 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3552 12:26:49.736026 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3553 12:26:49.736110
3554 12:26:49.739226 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3555 12:26:49.742512 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3556 12:26:49.745847 [Gating] SW calibration Done
3557 12:26:49.745931 ==
3558 12:26:49.749359 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 12:26:49.752568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 12:26:49.752679 ==
3561 12:26:49.755888 RX Vref Scan: 0
3562 12:26:49.755973
3563 12:26:49.759277 RX Vref 0 -> 0, step: 1
3564 12:26:49.759361
3565 12:26:49.759426 RX Delay -40 -> 252, step: 8
3566 12:26:49.765798 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3567 12:26:49.769006 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3568 12:26:49.772358 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3569 12:26:49.775795 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3570 12:26:49.778758 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3571 12:26:49.785243 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3572 12:26:49.788663 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3573 12:26:49.791875 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3574 12:26:49.795154 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3575 12:26:49.798489 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3576 12:26:49.805034 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3577 12:26:49.808348 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3578 12:26:49.811707 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3579 12:26:49.814960 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3580 12:26:49.821422 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3581 12:26:49.824790 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3582 12:26:49.824917 ==
3583 12:26:49.828193 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 12:26:49.831353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 12:26:49.831437 ==
3586 12:26:49.834916 DQS Delay:
3587 12:26:49.834999 DQS0 = 0, DQS1 = 0
3588 12:26:49.835085 DQM Delay:
3589 12:26:49.838098 DQM0 = 120, DQM1 = 113
3590 12:26:49.838183 DQ Delay:
3591 12:26:49.841357 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =123
3592 12:26:49.844751 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3593 12:26:49.848106 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3594 12:26:49.854558 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =123
3595 12:26:49.854644
3596 12:26:49.854713
3597 12:26:49.854816 ==
3598 12:26:49.857811 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 12:26:49.861200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 12:26:49.861285 ==
3601 12:26:49.861352
3602 12:26:49.861414
3603 12:26:49.864589 TX Vref Scan disable
3604 12:26:49.864675 == TX Byte 0 ==
3605 12:26:49.871109 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3606 12:26:49.874344 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3607 12:26:49.874449 == TX Byte 1 ==
3608 12:26:49.880985 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3609 12:26:49.884537 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3610 12:26:49.884641 ==
3611 12:26:49.887795 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 12:26:49.891024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 12:26:49.891115 ==
3614 12:26:49.904016 TX Vref=22, minBit 1, minWin=25, winSum=412
3615 12:26:49.907628 TX Vref=24, minBit 1, minWin=25, winSum=414
3616 12:26:49.910847 TX Vref=26, minBit 3, minWin=25, winSum=420
3617 12:26:49.914277 TX Vref=28, minBit 3, minWin=25, winSum=427
3618 12:26:49.917619 TX Vref=30, minBit 2, minWin=26, winSum=427
3619 12:26:49.924078 TX Vref=32, minBit 8, minWin=25, winSum=423
3620 12:26:49.927285 [TxChooseVref] Worse bit 2, Min win 26, Win sum 427, Final Vref 30
3621 12:26:49.927372
3622 12:26:49.930512 Final TX Range 1 Vref 30
3623 12:26:49.930617
3624 12:26:49.930699 ==
3625 12:26:49.933978 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 12:26:49.937239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 12:26:49.937363 ==
3628 12:26:49.940687
3629 12:26:49.940799
3630 12:26:49.940882 TX Vref Scan disable
3631 12:26:49.943920 == TX Byte 0 ==
3632 12:26:49.947211 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3633 12:26:49.953801 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3634 12:26:49.953894 == TX Byte 1 ==
3635 12:26:49.957037 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3636 12:26:49.963707 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3637 12:26:49.963795
3638 12:26:49.963866 [DATLAT]
3639 12:26:49.963933 Freq=1200, CH1 RK1
3640 12:26:49.964008
3641 12:26:49.966971 DATLAT Default: 0xd
3642 12:26:49.970234 0, 0xFFFF, sum = 0
3643 12:26:49.970320 1, 0xFFFF, sum = 0
3644 12:26:49.973595 2, 0xFFFF, sum = 0
3645 12:26:49.973682 3, 0xFFFF, sum = 0
3646 12:26:49.976849 4, 0xFFFF, sum = 0
3647 12:26:49.976967 5, 0xFFFF, sum = 0
3648 12:26:49.980136 6, 0xFFFF, sum = 0
3649 12:26:49.980249 7, 0xFFFF, sum = 0
3650 12:26:49.983570 8, 0xFFFF, sum = 0
3651 12:26:49.983673 9, 0xFFFF, sum = 0
3652 12:26:49.986711 10, 0xFFFF, sum = 0
3653 12:26:49.986813 11, 0xFFFF, sum = 0
3654 12:26:49.989939 12, 0x0, sum = 1
3655 12:26:49.990010 13, 0x0, sum = 2
3656 12:26:49.993242 14, 0x0, sum = 3
3657 12:26:49.993328 15, 0x0, sum = 4
3658 12:26:49.996609 best_step = 13
3659 12:26:49.996693
3660 12:26:49.996760 ==
3661 12:26:49.999716 Dram Type= 6, Freq= 0, CH_1, rank 1
3662 12:26:50.003537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3663 12:26:50.003646 ==
3664 12:26:50.006360 RX Vref Scan: 0
3665 12:26:50.006461
3666 12:26:50.006552 RX Vref 0 -> 0, step: 1
3667 12:26:50.006640
3668 12:26:50.009637 RX Delay -13 -> 252, step: 4
3669 12:26:50.016606 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3670 12:26:50.019859 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3671 12:26:50.023161 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3672 12:26:50.026448 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3673 12:26:50.029580 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3674 12:26:50.036400 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3675 12:26:50.039506 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3676 12:26:50.043103 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3677 12:26:50.046107 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3678 12:26:50.049722 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3679 12:26:50.056304 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3680 12:26:50.059425 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3681 12:26:50.062735 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3682 12:26:50.065973 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3683 12:26:50.069307 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3684 12:26:50.075881 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3685 12:26:50.075962 ==
3686 12:26:50.079170 Dram Type= 6, Freq= 0, CH_1, rank 1
3687 12:26:50.082454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3688 12:26:50.082557 ==
3689 12:26:50.082679 DQS Delay:
3690 12:26:50.086205 DQS0 = 0, DQS1 = 0
3691 12:26:50.086276 DQM Delay:
3692 12:26:50.089101 DQM0 = 119, DQM1 = 113
3693 12:26:50.089174 DQ Delay:
3694 12:26:50.092672 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3695 12:26:50.096052 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3696 12:26:50.099340 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3697 12:26:50.102663 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122
3698 12:26:50.105711
3699 12:26:50.105795
3700 12:26:50.112366 [DQSOSCAuto] RK1, (LSB)MR18= 0x9ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3701 12:26:50.115743 CH1 RK1: MR19=403, MR18=9ED
3702 12:26:50.122454 CH1_RK1: MR19=0x403, MR18=0x9ED, DQSOSC=406, MR23=63, INC=39, DEC=26
3703 12:26:50.125298 [RxdqsGatingPostProcess] freq 1200
3704 12:26:50.129116 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3705 12:26:50.131992 best DQS0 dly(2T, 0.5T) = (0, 11)
3706 12:26:50.135326 best DQS1 dly(2T, 0.5T) = (0, 11)
3707 12:26:50.138857 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3708 12:26:50.141925 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3709 12:26:50.145430 best DQS0 dly(2T, 0.5T) = (0, 11)
3710 12:26:50.148683 best DQS1 dly(2T, 0.5T) = (0, 11)
3711 12:26:50.152169 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3712 12:26:50.155225 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3713 12:26:50.158500 Pre-setting of DQS Precalculation
3714 12:26:50.162183 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3715 12:26:50.168655 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3716 12:26:50.178692 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3717 12:26:50.178781
3718 12:26:50.178846
3719 12:26:50.182026 [Calibration Summary] 2400 Mbps
3720 12:26:50.182110 CH 0, Rank 0
3721 12:26:50.185319 SW Impedance : PASS
3722 12:26:50.185403 DUTY Scan : NO K
3723 12:26:50.188218 ZQ Calibration : PASS
3724 12:26:50.191689 Jitter Meter : NO K
3725 12:26:50.191773 CBT Training : PASS
3726 12:26:50.195196 Write leveling : PASS
3727 12:26:50.198080 RX DQS gating : PASS
3728 12:26:50.198184 RX DQ/DQS(RDDQC) : PASS
3729 12:26:50.201581 TX DQ/DQS : PASS
3730 12:26:50.201692 RX DATLAT : PASS
3731 12:26:50.204937 RX DQ/DQS(Engine): PASS
3732 12:26:50.208111 TX OE : NO K
3733 12:26:50.208204 All Pass.
3734 12:26:50.208347
3735 12:26:50.211339 CH 0, Rank 1
3736 12:26:50.211423 SW Impedance : PASS
3737 12:26:50.214666 DUTY Scan : NO K
3738 12:26:50.214750 ZQ Calibration : PASS
3739 12:26:50.217948 Jitter Meter : NO K
3740 12:26:50.221216 CBT Training : PASS
3741 12:26:50.221300 Write leveling : PASS
3742 12:26:50.224532 RX DQS gating : PASS
3743 12:26:50.227886 RX DQ/DQS(RDDQC) : PASS
3744 12:26:50.227970 TX DQ/DQS : PASS
3745 12:26:50.231190 RX DATLAT : PASS
3746 12:26:50.234535 RX DQ/DQS(Engine): PASS
3747 12:26:50.234646 TX OE : NO K
3748 12:26:50.237843 All Pass.
3749 12:26:50.237918
3750 12:26:50.237982 CH 1, Rank 0
3751 12:26:50.241145 SW Impedance : PASS
3752 12:26:50.241255 DUTY Scan : NO K
3753 12:26:50.244393 ZQ Calibration : PASS
3754 12:26:50.247817 Jitter Meter : NO K
3755 12:26:50.247920 CBT Training : PASS
3756 12:26:50.251308 Write leveling : PASS
3757 12:26:50.254216 RX DQS gating : PASS
3758 12:26:50.254332 RX DQ/DQS(RDDQC) : PASS
3759 12:26:50.257830 TX DQ/DQS : PASS
3760 12:26:50.260894 RX DATLAT : PASS
3761 12:26:50.261004 RX DQ/DQS(Engine): PASS
3762 12:26:50.264513 TX OE : NO K
3763 12:26:50.264626 All Pass.
3764 12:26:50.264738
3765 12:26:50.267730 CH 1, Rank 1
3766 12:26:50.267841 SW Impedance : PASS
3767 12:26:50.271060 DUTY Scan : NO K
3768 12:26:50.274324 ZQ Calibration : PASS
3769 12:26:50.274413 Jitter Meter : NO K
3770 12:26:50.277609 CBT Training : PASS
3771 12:26:50.280711 Write leveling : PASS
3772 12:26:50.280847 RX DQS gating : PASS
3773 12:26:50.284048 RX DQ/DQS(RDDQC) : PASS
3774 12:26:50.284151 TX DQ/DQS : PASS
3775 12:26:50.287411 RX DATLAT : PASS
3776 12:26:50.290738 RX DQ/DQS(Engine): PASS
3777 12:26:50.290822 TX OE : NO K
3778 12:26:50.294155 All Pass.
3779 12:26:50.294241
3780 12:26:50.294308 DramC Write-DBI off
3781 12:26:50.297295 PER_BANK_REFRESH: Hybrid Mode
3782 12:26:50.300441 TX_TRACKING: ON
3783 12:26:50.307190 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3784 12:26:50.310499 [FAST_K] Save calibration result to emmc
3785 12:26:50.317015 dramc_set_vcore_voltage set vcore to 650000
3786 12:26:50.317118 Read voltage for 600, 5
3787 12:26:50.317215 Vio18 = 0
3788 12:26:50.320176 Vcore = 650000
3789 12:26:50.320276 Vdram = 0
3790 12:26:50.320356 Vddq = 0
3791 12:26:50.323775 Vmddr = 0
3792 12:26:50.327022 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3793 12:26:50.333525 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3794 12:26:50.333610 MEM_TYPE=3, freq_sel=19
3795 12:26:50.337021 sv_algorithm_assistance_LP4_1600
3796 12:26:50.343483 ============ PULL DRAM RESETB DOWN ============
3797 12:26:50.346783 ========== PULL DRAM RESETB DOWN end =========
3798 12:26:50.350175 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3799 12:26:50.353357 ===================================
3800 12:26:50.356631 LPDDR4 DRAM CONFIGURATION
3801 12:26:50.360114 ===================================
3802 12:26:50.363432 EX_ROW_EN[0] = 0x0
3803 12:26:50.363516 EX_ROW_EN[1] = 0x0
3804 12:26:50.366657 LP4Y_EN = 0x0
3805 12:26:50.366759 WORK_FSP = 0x0
3806 12:26:50.370086 WL = 0x2
3807 12:26:50.370197 RL = 0x2
3808 12:26:50.373130 BL = 0x2
3809 12:26:50.373214 RPST = 0x0
3810 12:26:50.376659 RD_PRE = 0x0
3811 12:26:50.376744 WR_PRE = 0x1
3812 12:26:50.379853 WR_PST = 0x0
3813 12:26:50.379938 DBI_WR = 0x0
3814 12:26:50.383091 DBI_RD = 0x0
3815 12:26:50.383190 OTF = 0x1
3816 12:26:50.386411 ===================================
3817 12:26:50.389761 ===================================
3818 12:26:50.393107 ANA top config
3819 12:26:50.396465 ===================================
3820 12:26:50.399748 DLL_ASYNC_EN = 0
3821 12:26:50.399832 ALL_SLAVE_EN = 1
3822 12:26:50.402957 NEW_RANK_MODE = 1
3823 12:26:50.406688 DLL_IDLE_MODE = 1
3824 12:26:50.409534 LP45_APHY_COMB_EN = 1
3825 12:26:50.412659 TX_ODT_DIS = 1
3826 12:26:50.412745 NEW_8X_MODE = 1
3827 12:26:50.416022 ===================================
3828 12:26:50.419332 ===================================
3829 12:26:50.422657 data_rate = 1200
3830 12:26:50.425939 CKR = 1
3831 12:26:50.429333 DQ_P2S_RATIO = 8
3832 12:26:50.432653 ===================================
3833 12:26:50.435791 CA_P2S_RATIO = 8
3834 12:26:50.439251 DQ_CA_OPEN = 0
3835 12:26:50.439429 DQ_SEMI_OPEN = 0
3836 12:26:50.442549 CA_SEMI_OPEN = 0
3837 12:26:50.445764 CA_FULL_RATE = 0
3838 12:26:50.449047 DQ_CKDIV4_EN = 1
3839 12:26:50.452415 CA_CKDIV4_EN = 1
3840 12:26:50.455621 CA_PREDIV_EN = 0
3841 12:26:50.455744 PH8_DLY = 0
3842 12:26:50.458799 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3843 12:26:50.462162 DQ_AAMCK_DIV = 4
3844 12:26:50.465718 CA_AAMCK_DIV = 4
3845 12:26:50.469035 CA_ADMCK_DIV = 4
3846 12:26:50.472056 DQ_TRACK_CA_EN = 0
3847 12:26:50.475625 CA_PICK = 600
3848 12:26:50.475716 CA_MCKIO = 600
3849 12:26:50.478643 MCKIO_SEMI = 0
3850 12:26:50.481941 PLL_FREQ = 2288
3851 12:26:50.485515 DQ_UI_PI_RATIO = 32
3852 12:26:50.488536 CA_UI_PI_RATIO = 0
3853 12:26:50.491711 ===================================
3854 12:26:50.495088 ===================================
3855 12:26:50.498458 memory_type:LPDDR4
3856 12:26:50.498560 GP_NUM : 10
3857 12:26:50.501691 SRAM_EN : 1
3858 12:26:50.501778 MD32_EN : 0
3859 12:26:50.505053 ===================================
3860 12:26:50.508261 [ANA_INIT] >>>>>>>>>>>>>>
3861 12:26:50.511486 <<<<<< [CONFIGURE PHASE]: ANA_TX
3862 12:26:50.514897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3863 12:26:50.518185 ===================================
3864 12:26:50.521258 data_rate = 1200,PCW = 0X5800
3865 12:26:50.524642 ===================================
3866 12:26:50.528033 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3867 12:26:50.534513 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3868 12:26:50.537849 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3869 12:26:50.544774 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3870 12:26:50.547656 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3871 12:26:50.551074 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3872 12:26:50.551191 [ANA_INIT] flow start
3873 12:26:50.554373 [ANA_INIT] PLL >>>>>>>>
3874 12:26:50.557807 [ANA_INIT] PLL <<<<<<<<
3875 12:26:50.560890 [ANA_INIT] MIDPI >>>>>>>>
3876 12:26:50.560980 [ANA_INIT] MIDPI <<<<<<<<
3877 12:26:50.564651 [ANA_INIT] DLL >>>>>>>>
3878 12:26:50.564775 [ANA_INIT] flow end
3879 12:26:50.571188 ============ LP4 DIFF to SE enter ============
3880 12:26:50.574580 ============ LP4 DIFF to SE exit ============
3881 12:26:50.577754 [ANA_INIT] <<<<<<<<<<<<<
3882 12:26:50.580910 [Flow] Enable top DCM control >>>>>
3883 12:26:50.584407 [Flow] Enable top DCM control <<<<<
3884 12:26:50.587468 Enable DLL master slave shuffle
3885 12:26:50.590876 ==============================================================
3886 12:26:50.594315 Gating Mode config
3887 12:26:50.597781 ==============================================================
3888 12:26:50.600649 Config description:
3889 12:26:50.610672 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3890 12:26:50.617595 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3891 12:26:50.620971 SELPH_MODE 0: By rank 1: By Phase
3892 12:26:50.627443 ==============================================================
3893 12:26:50.630684 GAT_TRACK_EN = 1
3894 12:26:50.633923 RX_GATING_MODE = 2
3895 12:26:50.637240 RX_GATING_TRACK_MODE = 2
3896 12:26:50.640500 SELPH_MODE = 1
3897 12:26:50.643821 PICG_EARLY_EN = 1
3898 12:26:50.647278 VALID_LAT_VALUE = 1
3899 12:26:50.650590 ==============================================================
3900 12:26:50.653882 Enter into Gating configuration >>>>
3901 12:26:50.657086 Exit from Gating configuration <<<<
3902 12:26:50.660313 Enter into DVFS_PRE_config >>>>>
3903 12:26:50.673361 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3904 12:26:50.673483 Exit from DVFS_PRE_config <<<<<
3905 12:26:50.676717 Enter into PICG configuration >>>>
3906 12:26:50.680018 Exit from PICG configuration <<<<
3907 12:26:50.683169 [RX_INPUT] configuration >>>>>
3908 12:26:50.686566 [RX_INPUT] configuration <<<<<
3909 12:26:50.693274 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3910 12:26:50.696881 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3911 12:26:50.703437 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3912 12:26:50.710155 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3913 12:26:50.716567 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3914 12:26:50.723165 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3915 12:26:50.726454 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3916 12:26:50.729644 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3917 12:26:50.733016 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3918 12:26:50.739493 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3919 12:26:50.743164 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3920 12:26:50.746478 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3921 12:26:50.749635 ===================================
3922 12:26:50.752987 LPDDR4 DRAM CONFIGURATION
3923 12:26:50.756293 ===================================
3924 12:26:50.759645 EX_ROW_EN[0] = 0x0
3925 12:26:50.759737 EX_ROW_EN[1] = 0x0
3926 12:26:50.763016 LP4Y_EN = 0x0
3927 12:26:50.763095 WORK_FSP = 0x0
3928 12:26:50.765908 WL = 0x2
3929 12:26:50.766000 RL = 0x2
3930 12:26:50.769428 BL = 0x2
3931 12:26:50.769520 RPST = 0x0
3932 12:26:50.772672 RD_PRE = 0x0
3933 12:26:50.772795 WR_PRE = 0x1
3934 12:26:50.775965 WR_PST = 0x0
3935 12:26:50.776055 DBI_WR = 0x0
3936 12:26:50.779144 DBI_RD = 0x0
3937 12:26:50.779239 OTF = 0x1
3938 12:26:50.782477 ===================================
3939 12:26:50.789052 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3940 12:26:50.792614 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3941 12:26:50.795614 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3942 12:26:50.798991 ===================================
3943 12:26:50.802069 LPDDR4 DRAM CONFIGURATION
3944 12:26:50.805691 ===================================
3945 12:26:50.808698 EX_ROW_EN[0] = 0x10
3946 12:26:50.808850 EX_ROW_EN[1] = 0x0
3947 12:26:50.812412 LP4Y_EN = 0x0
3948 12:26:50.812506 WORK_FSP = 0x0
3949 12:26:50.815624 WL = 0x2
3950 12:26:50.815718 RL = 0x2
3951 12:26:50.818977 BL = 0x2
3952 12:26:50.819059 RPST = 0x0
3953 12:26:50.822077 RD_PRE = 0x0
3954 12:26:50.822158 WR_PRE = 0x1
3955 12:26:50.825369 WR_PST = 0x0
3956 12:26:50.825446 DBI_WR = 0x0
3957 12:26:50.828656 DBI_RD = 0x0
3958 12:26:50.828756 OTF = 0x1
3959 12:26:50.831944 ===================================
3960 12:26:50.838234 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3961 12:26:50.843362 nWR fixed to 30
3962 12:26:50.846641 [ModeRegInit_LP4] CH0 RK0
3963 12:26:50.846738 [ModeRegInit_LP4] CH0 RK1
3964 12:26:50.849902 [ModeRegInit_LP4] CH1 RK0
3965 12:26:50.853260 [ModeRegInit_LP4] CH1 RK1
3966 12:26:50.853350 match AC timing 17
3967 12:26:50.859876 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3968 12:26:50.863276 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3969 12:26:50.866717 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3970 12:26:50.872996 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3971 12:26:50.876230 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3972 12:26:50.876371 ==
3973 12:26:50.879631 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 12:26:50.882803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 12:26:50.882898 ==
3976 12:26:50.889329 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3977 12:26:50.896086 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3978 12:26:50.899410 [CA 0] Center 36 (6~67) winsize 62
3979 12:26:50.902859 [CA 1] Center 36 (6~67) winsize 62
3980 12:26:50.905980 [CA 2] Center 34 (4~65) winsize 62
3981 12:26:50.908967 [CA 3] Center 34 (3~65) winsize 63
3982 12:26:50.912588 [CA 4] Center 33 (3~64) winsize 62
3983 12:26:50.915633 [CA 5] Center 33 (2~64) winsize 63
3984 12:26:50.915728
3985 12:26:50.918764 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3986 12:26:50.918852
3987 12:26:50.922454 [CATrainingPosCal] consider 1 rank data
3988 12:26:50.925628 u2DelayCellTimex100 = 270/100 ps
3989 12:26:50.929043 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3990 12:26:50.932289 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3991 12:26:50.938798 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3992 12:26:50.941742 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3993 12:26:50.944983 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3994 12:26:50.948662 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3995 12:26:50.948772
3996 12:26:50.951854 CA PerBit enable=1, Macro0, CA PI delay=33
3997 12:26:50.951945
3998 12:26:50.955288 [CBTSetCACLKResult] CA Dly = 33
3999 12:26:50.955382 CS Dly: 5 (0~36)
4000 12:26:50.958575 ==
4001 12:26:50.962022 Dram Type= 6, Freq= 0, CH_0, rank 1
4002 12:26:50.965335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4003 12:26:50.965423 ==
4004 12:26:50.968165 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4005 12:26:50.974799 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4006 12:26:50.978802 [CA 0] Center 36 (6~67) winsize 62
4007 12:26:50.982083 [CA 1] Center 36 (6~67) winsize 62
4008 12:26:50.985250 [CA 2] Center 35 (5~66) winsize 62
4009 12:26:50.988588 [CA 3] Center 34 (4~65) winsize 62
4010 12:26:50.991864 [CA 4] Center 34 (3~65) winsize 63
4011 12:26:50.995221 [CA 5] Center 34 (3~65) winsize 63
4012 12:26:50.995335
4013 12:26:50.998619 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4014 12:26:50.998724
4015 12:26:51.001877 [CATrainingPosCal] consider 2 rank data
4016 12:26:51.005176 u2DelayCellTimex100 = 270/100 ps
4017 12:26:51.011424 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4018 12:26:51.014894 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4019 12:26:51.018199 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4020 12:26:51.021729 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4021 12:26:51.024721 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4022 12:26:51.028241 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4023 12:26:51.028355
4024 12:26:51.031765 CA PerBit enable=1, Macro0, CA PI delay=33
4025 12:26:51.031879
4026 12:26:51.034546 [CBTSetCACLKResult] CA Dly = 33
4027 12:26:51.037864 CS Dly: 6 (0~38)
4028 12:26:51.037956
4029 12:26:51.041574 ----->DramcWriteLeveling(PI) begin...
4030 12:26:51.041668 ==
4031 12:26:51.044761 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 12:26:51.047759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 12:26:51.047874 ==
4034 12:26:51.051073 Write leveling (Byte 0): 32 => 32
4035 12:26:51.054787 Write leveling (Byte 1): 29 => 29
4036 12:26:51.057673 DramcWriteLeveling(PI) end<-----
4037 12:26:51.057817
4038 12:26:51.057992 ==
4039 12:26:51.060924 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 12:26:51.064333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 12:26:51.064439 ==
4042 12:26:51.067775 [Gating] SW mode calibration
4043 12:26:51.074319 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4044 12:26:51.080677 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4045 12:26:51.084004 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4046 12:26:51.090401 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 12:26:51.093777 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4048 12:26:51.097063 0 9 12 | B1->B0 | 3232 2a2a | 1 0 | (1 0) (0 1)
4049 12:26:51.103700 0 9 16 | B1->B0 | 2e2e 2424 | 0 0 | (1 1) (0 0)
4050 12:26:51.107011 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 12:26:51.110192 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 12:26:51.116734 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 12:26:51.120112 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 12:26:51.123756 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 12:26:51.130197 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 12:26:51.133233 0 10 12 | B1->B0 | 2929 4242 | 0 1 | (0 0) (0 0)
4057 12:26:51.136620 0 10 16 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
4058 12:26:51.143510 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 12:26:51.146685 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 12:26:51.149968 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 12:26:51.156682 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 12:26:51.159824 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 12:26:51.163167 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 12:26:51.169794 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 12:26:51.173155 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4066 12:26:51.176452 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 12:26:51.183045 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 12:26:51.186381 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 12:26:51.189674 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 12:26:51.196053 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 12:26:51.199398 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 12:26:51.202683 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 12:26:51.209459 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 12:26:51.212544 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 12:26:51.215799 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 12:26:51.222398 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 12:26:51.225829 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 12:26:51.229096 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 12:26:51.235597 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 12:26:51.239199 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4081 12:26:51.242633 Total UI for P1: 0, mck2ui 16
4082 12:26:51.245629 best dqsien dly found for B0: ( 0, 13, 10)
4083 12:26:51.249173 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4084 12:26:51.252244 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 12:26:51.255617 Total UI for P1: 0, mck2ui 16
4086 12:26:51.258891 best dqsien dly found for B1: ( 0, 13, 16)
4087 12:26:51.262534 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4088 12:26:51.269049 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4089 12:26:51.269150
4090 12:26:51.272353 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4091 12:26:51.275145 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4092 12:26:51.278580 [Gating] SW calibration Done
4093 12:26:51.278688 ==
4094 12:26:51.281920 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 12:26:51.285639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 12:26:51.285753 ==
4097 12:26:51.288721 RX Vref Scan: 0
4098 12:26:51.288832
4099 12:26:51.288896 RX Vref 0 -> 0, step: 1
4100 12:26:51.288956
4101 12:26:51.291876 RX Delay -230 -> 252, step: 16
4102 12:26:51.295649 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4103 12:26:51.302097 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4104 12:26:51.305006 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4105 12:26:51.308329 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4106 12:26:51.311684 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4107 12:26:51.318315 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4108 12:26:51.321696 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4109 12:26:51.324974 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4110 12:26:51.328112 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4111 12:26:51.331414 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4112 12:26:51.338071 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4113 12:26:51.341588 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4114 12:26:51.344707 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4115 12:26:51.351417 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4116 12:26:51.354513 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4117 12:26:51.358277 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4118 12:26:51.358420 ==
4119 12:26:51.361389 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 12:26:51.364710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 12:26:51.364864 ==
4122 12:26:51.367964 DQS Delay:
4123 12:26:51.368093 DQS0 = 0, DQS1 = 0
4124 12:26:51.371176 DQM Delay:
4125 12:26:51.371302 DQM0 = 52, DQM1 = 44
4126 12:26:51.371370 DQ Delay:
4127 12:26:51.374491 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4128 12:26:51.377846 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4129 12:26:51.381085 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4130 12:26:51.384360 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4131 12:26:51.384481
4132 12:26:51.387770
4133 12:26:51.387859 ==
4134 12:26:51.391130 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 12:26:51.394204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 12:26:51.394298 ==
4137 12:26:51.394365
4138 12:26:51.394426
4139 12:26:51.397484 TX Vref Scan disable
4140 12:26:51.397561 == TX Byte 0 ==
4141 12:26:51.403872 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4142 12:26:51.407252 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4143 12:26:51.407372 == TX Byte 1 ==
4144 12:26:51.414067 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4145 12:26:51.417384 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4146 12:26:51.417486 ==
4147 12:26:51.420667 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 12:26:51.423582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 12:26:51.423696 ==
4150 12:26:51.423764
4151 12:26:51.423834
4152 12:26:51.427316 TX Vref Scan disable
4153 12:26:51.430732 == TX Byte 0 ==
4154 12:26:51.433985 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4155 12:26:51.437334 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4156 12:26:51.440199 == TX Byte 1 ==
4157 12:26:51.443549 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4158 12:26:51.450158 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4159 12:26:51.450273
4160 12:26:51.450341 [DATLAT]
4161 12:26:51.450403 Freq=600, CH0 RK0
4162 12:26:51.450463
4163 12:26:51.453524 DATLAT Default: 0x9
4164 12:26:51.453648 0, 0xFFFF, sum = 0
4165 12:26:51.456992 1, 0xFFFF, sum = 0
4166 12:26:51.457089 2, 0xFFFF, sum = 0
4167 12:26:51.459986 3, 0xFFFF, sum = 0
4168 12:26:51.463396 4, 0xFFFF, sum = 0
4169 12:26:51.463494 5, 0xFFFF, sum = 0
4170 12:26:51.466641 6, 0xFFFF, sum = 0
4171 12:26:51.466734 7, 0xFFFF, sum = 0
4172 12:26:51.470079 8, 0x0, sum = 1
4173 12:26:51.470160 9, 0x0, sum = 2
4174 12:26:51.470225 10, 0x0, sum = 3
4175 12:26:51.473228 11, 0x0, sum = 4
4176 12:26:51.473319 best_step = 9
4177 12:26:51.473387
4178 12:26:51.473450 ==
4179 12:26:51.476446 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 12:26:51.483027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 12:26:51.483133 ==
4182 12:26:51.483201 RX Vref Scan: 1
4183 12:26:51.483263
4184 12:26:51.486577 RX Vref 0 -> 0, step: 1
4185 12:26:51.486684
4186 12:26:51.489780 RX Delay -163 -> 252, step: 8
4187 12:26:51.489890
4188 12:26:51.493176 Set Vref, RX VrefLevel [Byte0]: 59
4189 12:26:51.496350 [Byte1]: 48
4190 12:26:51.496448
4191 12:26:51.500040 Final RX Vref Byte 0 = 59 to rank0
4192 12:26:51.503325 Final RX Vref Byte 1 = 48 to rank0
4193 12:26:51.506547 Final RX Vref Byte 0 = 59 to rank1
4194 12:26:51.509779 Final RX Vref Byte 1 = 48 to rank1==
4195 12:26:51.513118 Dram Type= 6, Freq= 0, CH_0, rank 0
4196 12:26:51.516407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 12:26:51.516504 ==
4198 12:26:51.519707 DQS Delay:
4199 12:26:51.519797 DQS0 = 0, DQS1 = 0
4200 12:26:51.522887 DQM Delay:
4201 12:26:51.522975 DQM0 = 48, DQM1 = 39
4202 12:26:51.523042 DQ Delay:
4203 12:26:51.526197 DQ0 =44, DQ1 =52, DQ2 =44, DQ3 =44
4204 12:26:51.529459 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4205 12:26:51.532908 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4206 12:26:51.536243 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4207 12:26:51.536334
4208 12:26:51.536400
4209 12:26:51.545761 [DQSOSCAuto] RK0, (LSB)MR18= 0x5751, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4210 12:26:51.549080 CH0 RK0: MR19=808, MR18=5751
4211 12:26:51.555929 CH0_RK0: MR19=0x808, MR18=0x5751, DQSOSC=393, MR23=63, INC=169, DEC=113
4212 12:26:51.556048
4213 12:26:51.559152 ----->DramcWriteLeveling(PI) begin...
4214 12:26:51.559244 ==
4215 12:26:51.562566 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 12:26:51.565589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 12:26:51.565682 ==
4218 12:26:51.569101 Write leveling (Byte 0): 31 => 31
4219 12:26:51.572499 Write leveling (Byte 1): 32 => 32
4220 12:26:51.575843 DramcWriteLeveling(PI) end<-----
4221 12:26:51.575976
4222 12:26:51.576072 ==
4223 12:26:51.579014 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 12:26:51.582561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 12:26:51.582684 ==
4226 12:26:51.585389 [Gating] SW mode calibration
4227 12:26:51.592090 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4228 12:26:51.598796 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4229 12:26:51.601971 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4230 12:26:51.605252 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 12:26:51.612049 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4232 12:26:51.615367 0 9 12 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 0)
4233 12:26:51.618512 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (1 0)
4234 12:26:51.624802 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 12:26:51.628528 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 12:26:51.631812 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 12:26:51.638372 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 12:26:51.641715 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 12:26:51.645018 0 10 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (1 1)
4240 12:26:51.651181 0 10 12 | B1->B0 | 2727 3131 | 0 0 | (0 0) (0 0)
4241 12:26:51.654580 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4242 12:26:51.657790 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 12:26:51.664757 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 12:26:51.667900 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 12:26:51.674673 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 12:26:51.677783 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 12:26:51.681165 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 12:26:51.684661 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4249 12:26:51.690876 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 12:26:51.694137 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 12:26:51.697586 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 12:26:51.703987 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 12:26:51.707516 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 12:26:51.710881 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 12:26:51.717160 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 12:26:51.720511 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 12:26:51.723897 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 12:26:51.730475 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 12:26:51.733767 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 12:26:51.740442 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 12:26:51.743729 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 12:26:51.747077 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 12:26:51.753317 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 12:26:51.757099 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4265 12:26:51.760322 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 12:26:51.763403 Total UI for P1: 0, mck2ui 16
4267 12:26:51.766768 best dqsien dly found for B0: ( 0, 13, 12)
4268 12:26:51.770006 Total UI for P1: 0, mck2ui 16
4269 12:26:51.773371 best dqsien dly found for B1: ( 0, 13, 14)
4270 12:26:51.776539 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4271 12:26:51.780027 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4272 12:26:51.780147
4273 12:26:51.783523 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4274 12:26:51.790147 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4275 12:26:51.790287 [Gating] SW calibration Done
4276 12:26:51.790385 ==
4277 12:26:51.793426 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 12:26:51.799931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 12:26:51.800065 ==
4280 12:26:51.800158 RX Vref Scan: 0
4281 12:26:51.800247
4282 12:26:51.803180 RX Vref 0 -> 0, step: 1
4283 12:26:51.803332
4284 12:26:51.806627 RX Delay -230 -> 252, step: 16
4285 12:26:51.809823 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4286 12:26:51.813023 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4287 12:26:51.819683 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4288 12:26:51.822870 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4289 12:26:51.826150 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4290 12:26:51.829421 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4291 12:26:51.832753 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4292 12:26:51.839413 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4293 12:26:51.842679 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4294 12:26:51.846049 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4295 12:26:51.849295 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4296 12:26:51.856057 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4297 12:26:51.859393 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4298 12:26:51.862710 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4299 12:26:51.866242 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4300 12:26:51.872683 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4301 12:26:51.872877 ==
4302 12:26:51.875935 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 12:26:51.879234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 12:26:51.879349 ==
4305 12:26:51.879445 DQS Delay:
4306 12:26:51.882365 DQS0 = 0, DQS1 = 0
4307 12:26:51.882473 DQM Delay:
4308 12:26:51.885656 DQM0 = 47, DQM1 = 43
4309 12:26:51.885751 DQ Delay:
4310 12:26:51.889261 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4311 12:26:51.892418 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4312 12:26:51.895845 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4313 12:26:51.898957 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4314 12:26:51.899060
4315 12:26:51.899127
4316 12:26:51.899188 ==
4317 12:26:51.902153 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 12:26:51.905482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 12:26:51.908723 ==
4320 12:26:51.908875
4321 12:26:51.908962
4322 12:26:51.909064 TX Vref Scan disable
4323 12:26:51.912068 == TX Byte 0 ==
4324 12:26:51.915205 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4325 12:26:51.918605 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4326 12:26:51.922120 == TX Byte 1 ==
4327 12:26:51.925280 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4328 12:26:51.929002 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4329 12:26:51.931802 ==
4330 12:26:51.935052 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 12:26:51.938316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 12:26:51.938449 ==
4333 12:26:51.938562
4334 12:26:51.938656
4335 12:26:51.941648 TX Vref Scan disable
4336 12:26:51.941752 == TX Byte 0 ==
4337 12:26:51.948263 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4338 12:26:51.951668 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4339 12:26:51.954945 == TX Byte 1 ==
4340 12:26:51.958314 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4341 12:26:51.961674 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4342 12:26:51.961813
4343 12:26:51.961882 [DATLAT]
4344 12:26:51.964907 Freq=600, CH0 RK1
4345 12:26:51.965018
4346 12:26:51.965089 DATLAT Default: 0x9
4347 12:26:51.968184 0, 0xFFFF, sum = 0
4348 12:26:51.971401 1, 0xFFFF, sum = 0
4349 12:26:51.971529 2, 0xFFFF, sum = 0
4350 12:26:51.974675 3, 0xFFFF, sum = 0
4351 12:26:51.974779 4, 0xFFFF, sum = 0
4352 12:26:51.978197 5, 0xFFFF, sum = 0
4353 12:26:51.978302 6, 0xFFFF, sum = 0
4354 12:26:51.981361 7, 0xFFFF, sum = 0
4355 12:26:51.981451 8, 0x0, sum = 1
4356 12:26:51.984604 9, 0x0, sum = 2
4357 12:26:51.984732 10, 0x0, sum = 3
4358 12:26:51.984836 11, 0x0, sum = 4
4359 12:26:51.987913 best_step = 9
4360 12:26:51.987999
4361 12:26:51.988074 ==
4362 12:26:51.991115 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 12:26:51.994337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 12:26:51.994454 ==
4365 12:26:51.997876 RX Vref Scan: 0
4366 12:26:51.997967
4367 12:26:52.001401 RX Vref 0 -> 0, step: 1
4368 12:26:52.001491
4369 12:26:52.001571 RX Delay -163 -> 252, step: 8
4370 12:26:52.008584 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4371 12:26:52.012318 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4372 12:26:52.015465 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4373 12:26:52.018670 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4374 12:26:52.025326 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4375 12:26:52.028364 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4376 12:26:52.031975 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4377 12:26:52.035287 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4378 12:26:52.038682 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4379 12:26:52.044840 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4380 12:26:52.048150 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4381 12:26:52.051550 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4382 12:26:52.054872 iDelay=205, Bit 12, Center 44 (-99 ~ 188) 288
4383 12:26:52.061379 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4384 12:26:52.064733 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4385 12:26:52.068211 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4386 12:26:52.068322 ==
4387 12:26:52.071348 Dram Type= 6, Freq= 0, CH_0, rank 1
4388 12:26:52.074564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 12:26:52.074670 ==
4390 12:26:52.077898 DQS Delay:
4391 12:26:52.077983 DQS0 = 0, DQS1 = 0
4392 12:26:52.081595 DQM Delay:
4393 12:26:52.081690 DQM0 = 49, DQM1 = 40
4394 12:26:52.081775 DQ Delay:
4395 12:26:52.084740 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4396 12:26:52.088056 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4397 12:26:52.091293 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4398 12:26:52.094724 DQ12 =44, DQ13 =44, DQ14 =52, DQ15 =48
4399 12:26:52.094872
4400 12:26:52.094991
4401 12:26:52.104621 [DQSOSCAuto] RK1, (LSB)MR18= 0x612f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4402 12:26:52.107773 CH0 RK1: MR19=808, MR18=612F
4403 12:26:52.114684 CH0_RK1: MR19=0x808, MR18=0x612F, DQSOSC=391, MR23=63, INC=171, DEC=114
4404 12:26:52.118055 [RxdqsGatingPostProcess] freq 600
4405 12:26:52.120900 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4406 12:26:52.124342 Pre-setting of DQS Precalculation
4407 12:26:52.130853 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4408 12:26:52.131000 ==
4409 12:26:52.134475 Dram Type= 6, Freq= 0, CH_1, rank 0
4410 12:26:52.137665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 12:26:52.137782 ==
4412 12:26:52.141015 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4413 12:26:52.147555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4414 12:26:52.151353 [CA 0] Center 35 (5~66) winsize 62
4415 12:26:52.154648 [CA 1] Center 35 (5~66) winsize 62
4416 12:26:52.158021 [CA 2] Center 34 (3~65) winsize 63
4417 12:26:52.161281 [CA 3] Center 33 (3~64) winsize 62
4418 12:26:52.164631 [CA 4] Center 34 (3~65) winsize 63
4419 12:26:52.167979 [CA 5] Center 33 (3~64) winsize 62
4420 12:26:52.168093
4421 12:26:52.171274 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4422 12:26:52.171382
4423 12:26:52.174638 [CATrainingPosCal] consider 1 rank data
4424 12:26:52.177858 u2DelayCellTimex100 = 270/100 ps
4425 12:26:52.181181 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4426 12:26:52.188043 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4427 12:26:52.191311 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4428 12:26:52.194624 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4429 12:26:52.197882 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4430 12:26:52.201164 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4431 12:26:52.201283
4432 12:26:52.204467 CA PerBit enable=1, Macro0, CA PI delay=33
4433 12:26:52.204603
4434 12:26:52.207597 [CBTSetCACLKResult] CA Dly = 33
4435 12:26:52.210750 CS Dly: 5 (0~36)
4436 12:26:52.210912 ==
4437 12:26:52.213966 Dram Type= 6, Freq= 0, CH_1, rank 1
4438 12:26:52.217550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 12:26:52.217701 ==
4440 12:26:52.223891 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4441 12:26:52.227505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4442 12:26:52.231723 [CA 0] Center 35 (5~66) winsize 62
4443 12:26:52.235028 [CA 1] Center 35 (5~66) winsize 62
4444 12:26:52.238171 [CA 2] Center 34 (4~65) winsize 62
4445 12:26:52.241370 [CA 3] Center 34 (4~65) winsize 62
4446 12:26:52.244606 [CA 4] Center 34 (4~65) winsize 62
4447 12:26:52.248019 [CA 5] Center 33 (3~64) winsize 62
4448 12:26:52.248177
4449 12:26:52.251503 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4450 12:26:52.251654
4451 12:26:52.254710 [CATrainingPosCal] consider 2 rank data
4452 12:26:52.257894 u2DelayCellTimex100 = 270/100 ps
4453 12:26:52.261192 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4454 12:26:52.267905 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4455 12:26:52.271294 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4456 12:26:52.274580 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4457 12:26:52.277888 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4458 12:26:52.281158 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4459 12:26:52.281269
4460 12:26:52.284150 CA PerBit enable=1, Macro0, CA PI delay=33
4461 12:26:52.284248
4462 12:26:52.287531 [CBTSetCACLKResult] CA Dly = 33
4463 12:26:52.291101 CS Dly: 5 (0~37)
4464 12:26:52.291239
4465 12:26:52.294352 ----->DramcWriteLeveling(PI) begin...
4466 12:26:52.294483 ==
4467 12:26:52.297706 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 12:26:52.301121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 12:26:52.301244 ==
4470 12:26:52.304366 Write leveling (Byte 0): 28 => 28
4471 12:26:52.307230 Write leveling (Byte 1): 32 => 32
4472 12:26:52.310813 DramcWriteLeveling(PI) end<-----
4473 12:26:52.310965
4474 12:26:52.311073 ==
4475 12:26:52.313841 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 12:26:52.317439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 12:26:52.317595 ==
4478 12:26:52.320463 [Gating] SW mode calibration
4479 12:26:52.327565 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4480 12:26:52.333821 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4481 12:26:52.337064 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4482 12:26:52.340181 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4483 12:26:52.347035 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4484 12:26:52.350417 0 9 12 | B1->B0 | 2d2d 2e2e | 0 1 | (0 0) (1 1)
4485 12:26:52.353809 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4486 12:26:52.360455 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 12:26:52.363724 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 12:26:52.367091 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 12:26:52.373614 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 12:26:52.376960 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 12:26:52.380298 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4492 12:26:52.386697 0 10 12 | B1->B0 | 3a3a 3939 | 0 0 | (0 0) (0 0)
4493 12:26:52.389975 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 12:26:52.393360 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 12:26:52.400089 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 12:26:52.403406 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 12:26:52.406677 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 12:26:52.413285 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 12:26:52.416429 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4500 12:26:52.419938 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4501 12:26:52.426400 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 12:26:52.430114 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 12:26:52.433145 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 12:26:52.439925 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 12:26:52.442980 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 12:26:52.446400 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 12:26:52.452752 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 12:26:52.456180 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 12:26:52.459863 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 12:26:52.466024 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 12:26:52.469404 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 12:26:52.472680 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 12:26:52.479378 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 12:26:52.482709 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 12:26:52.485965 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4516 12:26:52.492881 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4517 12:26:52.496247 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 12:26:52.499569 Total UI for P1: 0, mck2ui 16
4519 12:26:52.502838 best dqsien dly found for B0: ( 0, 13, 10)
4520 12:26:52.506077 Total UI for P1: 0, mck2ui 16
4521 12:26:52.509372 best dqsien dly found for B1: ( 0, 13, 10)
4522 12:26:52.512678 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4523 12:26:52.515961 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4524 12:26:52.516081
4525 12:26:52.519303 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4526 12:26:52.522475 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4527 12:26:52.525601 [Gating] SW calibration Done
4528 12:26:52.525716 ==
4529 12:26:52.529046 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 12:26:52.532461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 12:26:52.535737 ==
4532 12:26:52.535857 RX Vref Scan: 0
4533 12:26:52.535952
4534 12:26:52.538801 RX Vref 0 -> 0, step: 1
4535 12:26:52.538891
4536 12:26:52.542504 RX Delay -230 -> 252, step: 16
4537 12:26:52.545647 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4538 12:26:52.549124 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4539 12:26:52.552162 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4540 12:26:52.558882 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4541 12:26:52.562140 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4542 12:26:52.565523 iDelay=218, Bit 5, Center 73 (-70 ~ 217) 288
4543 12:26:52.568930 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4544 12:26:52.571756 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4545 12:26:52.578380 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4546 12:26:52.581720 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4547 12:26:52.585037 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4548 12:26:52.588363 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4549 12:26:52.595151 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4550 12:26:52.598401 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4551 12:26:52.601618 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4552 12:26:52.604864 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4553 12:26:52.604955 ==
4554 12:26:52.608157 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 12:26:52.614751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 12:26:52.614872 ==
4557 12:26:52.614944 DQS Delay:
4558 12:26:52.618118 DQS0 = 0, DQS1 = 0
4559 12:26:52.618213 DQM Delay:
4560 12:26:52.618287 DQM0 = 54, DQM1 = 41
4561 12:26:52.621469 DQ Delay:
4562 12:26:52.624705 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4563 12:26:52.628352 DQ4 =49, DQ5 =73, DQ6 =65, DQ7 =49
4564 12:26:52.631399 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4565 12:26:52.634981 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4566 12:26:52.635081
4567 12:26:52.635149
4568 12:26:52.635212 ==
4569 12:26:52.638035 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 12:26:52.641580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 12:26:52.641698 ==
4572 12:26:52.641770
4573 12:26:52.641841
4574 12:26:52.644689 TX Vref Scan disable
4575 12:26:52.647951 == TX Byte 0 ==
4576 12:26:52.651642 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4577 12:26:52.654609 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4578 12:26:52.657869 == TX Byte 1 ==
4579 12:26:52.661634 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4580 12:26:52.664550 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4581 12:26:52.664660 ==
4582 12:26:52.667795 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 12:26:52.671032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 12:26:52.674318 ==
4585 12:26:52.674427
4586 12:26:52.674500
4587 12:26:52.674563 TX Vref Scan disable
4588 12:26:52.678520 == TX Byte 0 ==
4589 12:26:52.681724 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4590 12:26:52.688345 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4591 12:26:52.688458 == TX Byte 1 ==
4592 12:26:52.691693 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4593 12:26:52.698153 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4594 12:26:52.698272
4595 12:26:52.698340 [DATLAT]
4596 12:26:52.698402 Freq=600, CH1 RK0
4597 12:26:52.698472
4598 12:26:52.701894 DATLAT Default: 0x9
4599 12:26:52.701980 0, 0xFFFF, sum = 0
4600 12:26:52.704866 1, 0xFFFF, sum = 0
4601 12:26:52.704966 2, 0xFFFF, sum = 0
4602 12:26:52.708156 3, 0xFFFF, sum = 0
4603 12:26:52.711382 4, 0xFFFF, sum = 0
4604 12:26:52.711483 5, 0xFFFF, sum = 0
4605 12:26:52.714712 6, 0xFFFF, sum = 0
4606 12:26:52.714808 7, 0xFFFF, sum = 0
4607 12:26:52.718056 8, 0x0, sum = 1
4608 12:26:52.718149 9, 0x0, sum = 2
4609 12:26:52.718218 10, 0x0, sum = 3
4610 12:26:52.721356 11, 0x0, sum = 4
4611 12:26:52.721448 best_step = 9
4612 12:26:52.721518
4613 12:26:52.721581 ==
4614 12:26:52.724683 Dram Type= 6, Freq= 0, CH_1, rank 0
4615 12:26:52.731428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 12:26:52.731547 ==
4617 12:26:52.731621 RX Vref Scan: 1
4618 12:26:52.731684
4619 12:26:52.734715 RX Vref 0 -> 0, step: 1
4620 12:26:52.734806
4621 12:26:52.737740 RX Delay -179 -> 252, step: 8
4622 12:26:52.737832
4623 12:26:52.741238 Set Vref, RX VrefLevel [Byte0]: 53
4624 12:26:52.744772 [Byte1]: 51
4625 12:26:52.744873
4626 12:26:52.747975 Final RX Vref Byte 0 = 53 to rank0
4627 12:26:52.751047 Final RX Vref Byte 1 = 51 to rank0
4628 12:26:52.754214 Final RX Vref Byte 0 = 53 to rank1
4629 12:26:52.757832 Final RX Vref Byte 1 = 51 to rank1==
4630 12:26:52.760900 Dram Type= 6, Freq= 0, CH_1, rank 0
4631 12:26:52.764353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 12:26:52.767506 ==
4633 12:26:52.767641 DQS Delay:
4634 12:26:52.767742 DQS0 = 0, DQS1 = 0
4635 12:26:52.770774 DQM Delay:
4636 12:26:52.770881 DQM0 = 48, DQM1 = 41
4637 12:26:52.774040 DQ Delay:
4638 12:26:52.774167 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4639 12:26:52.777364 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4640 12:26:52.780616 DQ8 =32, DQ9 =28, DQ10 =44, DQ11 =32
4641 12:26:52.784047 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4642 12:26:52.787367
4643 12:26:52.787498
4644 12:26:52.793618 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4645 12:26:52.796977 CH1 RK0: MR19=808, MR18=4A71
4646 12:26:52.803441 CH1_RK0: MR19=0x808, MR18=0x4A71, DQSOSC=388, MR23=63, INC=174, DEC=116
4647 12:26:52.803593
4648 12:26:52.807151 ----->DramcWriteLeveling(PI) begin...
4649 12:26:52.807278 ==
4650 12:26:52.810566 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 12:26:52.813751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 12:26:52.813877 ==
4653 12:26:52.817011 Write leveling (Byte 0): 29 => 29
4654 12:26:52.820023 Write leveling (Byte 1): 29 => 29
4655 12:26:52.823332 DramcWriteLeveling(PI) end<-----
4656 12:26:52.823459
4657 12:26:52.823558 ==
4658 12:26:52.826768 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 12:26:52.830041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 12:26:52.830130 ==
4661 12:26:52.833361 [Gating] SW mode calibration
4662 12:26:52.839891 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4663 12:26:52.846610 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4664 12:26:52.849837 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4665 12:26:52.856430 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4666 12:26:52.859673 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 12:26:52.863336 0 9 12 | B1->B0 | 2626 3232 | 0 1 | (1 0) (0 1)
4668 12:26:52.869706 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 12:26:52.873197 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 12:26:52.876578 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 12:26:52.882780 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 12:26:52.886105 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 12:26:52.889378 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 12:26:52.895993 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4675 12:26:52.899448 0 10 12 | B1->B0 | 3838 2323 | 1 0 | (0 0) (0 0)
4676 12:26:52.902723 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 12:26:52.909449 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 12:26:52.912638 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 12:26:52.915932 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 12:26:52.922426 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 12:26:52.925747 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 12:26:52.929038 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 12:26:52.935624 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4684 12:26:52.938990 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 12:26:52.942235 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 12:26:52.945590 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 12:26:52.952099 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 12:26:52.955673 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 12:26:52.962246 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 12:26:52.965597 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 12:26:52.968806 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 12:26:52.972225 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 12:26:52.978755 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 12:26:52.982020 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 12:26:52.985441 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 12:26:52.991987 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 12:26:52.995246 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 12:26:52.998616 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4699 12:26:53.005187 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 12:26:53.008510 Total UI for P1: 0, mck2ui 16
4701 12:26:53.011824 best dqsien dly found for B0: ( 0, 13, 10)
4702 12:26:53.015032 Total UI for P1: 0, mck2ui 16
4703 12:26:53.018383 best dqsien dly found for B1: ( 0, 13, 8)
4704 12:26:53.021682 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4705 12:26:53.024989 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4706 12:26:53.025135
4707 12:26:53.028297 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4708 12:26:53.031783 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4709 12:26:53.035007 [Gating] SW calibration Done
4710 12:26:53.035130 ==
4711 12:26:53.038454 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 12:26:53.041678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 12:26:53.041788 ==
4714 12:26:53.044984 RX Vref Scan: 0
4715 12:26:53.045074
4716 12:26:53.045138 RX Vref 0 -> 0, step: 1
4717 12:26:53.048356
4718 12:26:53.048441 RX Delay -230 -> 252, step: 16
4719 12:26:53.054901 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4720 12:26:53.058333 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4721 12:26:53.061653 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4722 12:26:53.065014 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4723 12:26:53.071610 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4724 12:26:53.074881 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4725 12:26:53.077993 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4726 12:26:53.081725 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4727 12:26:53.084605 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4728 12:26:53.091298 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4729 12:26:53.094614 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4730 12:26:53.097884 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4731 12:26:53.101286 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4732 12:26:53.108014 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4733 12:26:53.111243 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4734 12:26:53.114451 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4735 12:26:53.114586 ==
4736 12:26:53.117576 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 12:26:53.120757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 12:26:53.124055 ==
4739 12:26:53.124161 DQS Delay:
4740 12:26:53.124228 DQS0 = 0, DQS1 = 0
4741 12:26:53.127697 DQM Delay:
4742 12:26:53.127788 DQM0 = 52, DQM1 = 46
4743 12:26:53.130993 DQ Delay:
4744 12:26:53.131101 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4745 12:26:53.134309 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4746 12:26:53.137601 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4747 12:26:53.140842 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4748 12:26:53.144115
4749 12:26:53.144220
4750 12:26:53.144290 ==
4751 12:26:53.147521 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 12:26:53.150728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 12:26:53.150851 ==
4754 12:26:53.150966
4755 12:26:53.151066
4756 12:26:53.154057 TX Vref Scan disable
4757 12:26:53.154169 == TX Byte 0 ==
4758 12:26:53.160646 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4759 12:26:53.163922 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4760 12:26:53.164034 == TX Byte 1 ==
4761 12:26:53.170510 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4762 12:26:53.173542 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4763 12:26:53.173645 ==
4764 12:26:53.176967 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 12:26:53.180435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 12:26:53.180568 ==
4767 12:26:53.180666
4768 12:26:53.180757
4769 12:26:53.183567 TX Vref Scan disable
4770 12:26:53.186728 == TX Byte 0 ==
4771 12:26:53.190378 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4772 12:26:53.196643 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4773 12:26:53.196815 == TX Byte 1 ==
4774 12:26:53.200051 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4775 12:26:53.206682 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4776 12:26:53.206817
4777 12:26:53.206911 [DATLAT]
4778 12:26:53.206978 Freq=600, CH1 RK1
4779 12:26:53.207040
4780 12:26:53.209932 DATLAT Default: 0x9
4781 12:26:53.210025 0, 0xFFFF, sum = 0
4782 12:26:53.213256 1, 0xFFFF, sum = 0
4783 12:26:53.216528 2, 0xFFFF, sum = 0
4784 12:26:53.216664 3, 0xFFFF, sum = 0
4785 12:26:53.219700 4, 0xFFFF, sum = 0
4786 12:26:53.219835 5, 0xFFFF, sum = 0
4787 12:26:53.223370 6, 0xFFFF, sum = 0
4788 12:26:53.223512 7, 0xFFFF, sum = 0
4789 12:26:53.226715 8, 0x0, sum = 1
4790 12:26:53.226861 9, 0x0, sum = 2
4791 12:26:53.229931 10, 0x0, sum = 3
4792 12:26:53.230069 11, 0x0, sum = 4
4793 12:26:53.230170 best_step = 9
4794 12:26:53.230263
4795 12:26:53.233215 ==
4796 12:26:53.233320 Dram Type= 6, Freq= 0, CH_1, rank 1
4797 12:26:53.239763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4798 12:26:53.239925 ==
4799 12:26:53.240036 RX Vref Scan: 0
4800 12:26:53.240136
4801 12:26:53.242694 RX Vref 0 -> 0, step: 1
4802 12:26:53.242816
4803 12:26:53.246154 RX Delay -163 -> 252, step: 8
4804 12:26:53.252759 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4805 12:26:53.256218 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4806 12:26:53.259441 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4807 12:26:53.262766 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4808 12:26:53.266131 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4809 12:26:53.272827 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4810 12:26:53.276145 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4811 12:26:53.279319 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4812 12:26:53.282633 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4813 12:26:53.286051 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4814 12:26:53.292548 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4815 12:26:53.295664 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4816 12:26:53.299065 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4817 12:26:53.302089 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4818 12:26:53.309098 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4819 12:26:53.312510 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4820 12:26:53.312649 ==
4821 12:26:53.315638 Dram Type= 6, Freq= 0, CH_1, rank 1
4822 12:26:53.318551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4823 12:26:53.318672 ==
4824 12:26:53.321948 DQS Delay:
4825 12:26:53.322060 DQS0 = 0, DQS1 = 0
4826 12:26:53.322155 DQM Delay:
4827 12:26:53.325643 DQM0 = 48, DQM1 = 45
4828 12:26:53.325735 DQ Delay:
4829 12:26:53.328751 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4830 12:26:53.332116 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4831 12:26:53.335326 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4832 12:26:53.338626 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =56
4833 12:26:53.338739
4834 12:26:53.338810
4835 12:26:53.348506 [DQSOSCAuto] RK1, (LSB)MR18= 0x561d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4836 12:26:53.348664 CH1 RK1: MR19=808, MR18=561D
4837 12:26:53.355161 CH1_RK1: MR19=0x808, MR18=0x561D, DQSOSC=393, MR23=63, INC=169, DEC=113
4838 12:26:53.358411 [RxdqsGatingPostProcess] freq 600
4839 12:26:53.364978 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4840 12:26:53.368225 Pre-setting of DQS Precalculation
4841 12:26:53.371582 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4842 12:26:53.381562 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4843 12:26:53.387918 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4844 12:26:53.388074
4845 12:26:53.388172
4846 12:26:53.391499 [Calibration Summary] 1200 Mbps
4847 12:26:53.391609 CH 0, Rank 0
4848 12:26:53.394758 SW Impedance : PASS
4849 12:26:53.394883 DUTY Scan : NO K
4850 12:26:53.398157 ZQ Calibration : PASS
4851 12:26:53.401313 Jitter Meter : NO K
4852 12:26:53.401439 CBT Training : PASS
4853 12:26:53.404346 Write leveling : PASS
4854 12:26:53.407963 RX DQS gating : PASS
4855 12:26:53.408077 RX DQ/DQS(RDDQC) : PASS
4856 12:26:53.411467 TX DQ/DQS : PASS
4857 12:26:53.414748 RX DATLAT : PASS
4858 12:26:53.414839 RX DQ/DQS(Engine): PASS
4859 12:26:53.418106 TX OE : NO K
4860 12:26:53.418194 All Pass.
4861 12:26:53.418261
4862 12:26:53.421376 CH 0, Rank 1
4863 12:26:53.421464 SW Impedance : PASS
4864 12:26:53.424544 DUTY Scan : NO K
4865 12:26:53.424656 ZQ Calibration : PASS
4866 12:26:53.427698 Jitter Meter : NO K
4867 12:26:53.431267 CBT Training : PASS
4868 12:26:53.431393 Write leveling : PASS
4869 12:26:53.434524 RX DQS gating : PASS
4870 12:26:53.437766 RX DQ/DQS(RDDQC) : PASS
4871 12:26:53.437879 TX DQ/DQS : PASS
4872 12:26:53.441011 RX DATLAT : PASS
4873 12:26:53.444234 RX DQ/DQS(Engine): PASS
4874 12:26:53.444337 TX OE : NO K
4875 12:26:53.447586 All Pass.
4876 12:26:53.447693
4877 12:26:53.447767 CH 1, Rank 0
4878 12:26:53.450897 SW Impedance : PASS
4879 12:26:53.450985 DUTY Scan : NO K
4880 12:26:53.454197 ZQ Calibration : PASS
4881 12:26:53.457329 Jitter Meter : NO K
4882 12:26:53.457443 CBT Training : PASS
4883 12:26:53.460675 Write leveling : PASS
4884 12:26:53.464132 RX DQS gating : PASS
4885 12:26:53.464229 RX DQ/DQS(RDDQC) : PASS
4886 12:26:53.467381 TX DQ/DQS : PASS
4887 12:26:53.470611 RX DATLAT : PASS
4888 12:26:53.470735 RX DQ/DQS(Engine): PASS
4889 12:26:53.473974 TX OE : NO K
4890 12:26:53.474092 All Pass.
4891 12:26:53.474188
4892 12:26:53.477215 CH 1, Rank 1
4893 12:26:53.477305 SW Impedance : PASS
4894 12:26:53.480643 DUTY Scan : NO K
4895 12:26:53.483939 ZQ Calibration : PASS
4896 12:26:53.484040 Jitter Meter : NO K
4897 12:26:53.487122 CBT Training : PASS
4898 12:26:53.490392 Write leveling : PASS
4899 12:26:53.490482 RX DQS gating : PASS
4900 12:26:53.493683 RX DQ/DQS(RDDQC) : PASS
4901 12:26:53.496976 TX DQ/DQS : PASS
4902 12:26:53.497064 RX DATLAT : PASS
4903 12:26:53.500178 RX DQ/DQS(Engine): PASS
4904 12:26:53.500300 TX OE : NO K
4905 12:26:53.503386 All Pass.
4906 12:26:53.503493
4907 12:26:53.503590 DramC Write-DBI off
4908 12:26:53.506878 PER_BANK_REFRESH: Hybrid Mode
4909 12:26:53.509942 TX_TRACKING: ON
4910 12:26:53.516923 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4911 12:26:53.519695 [FAST_K] Save calibration result to emmc
4912 12:26:53.526728 dramc_set_vcore_voltage set vcore to 662500
4913 12:26:53.526858 Read voltage for 933, 3
4914 12:26:53.529577 Vio18 = 0
4915 12:26:53.529667 Vcore = 662500
4916 12:26:53.529733 Vdram = 0
4917 12:26:53.532834 Vddq = 0
4918 12:26:53.532924 Vmddr = 0
4919 12:26:53.536464 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4920 12:26:53.542892 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4921 12:26:53.546344 MEM_TYPE=3, freq_sel=17
4922 12:26:53.549648 sv_algorithm_assistance_LP4_1600
4923 12:26:53.553053 ============ PULL DRAM RESETB DOWN ============
4924 12:26:53.556391 ========== PULL DRAM RESETB DOWN end =========
4925 12:26:53.559658 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4926 12:26:53.562973 ===================================
4927 12:26:53.565884 LPDDR4 DRAM CONFIGURATION
4928 12:26:53.569225 ===================================
4929 12:26:53.572460 EX_ROW_EN[0] = 0x0
4930 12:26:53.572576 EX_ROW_EN[1] = 0x0
4931 12:26:53.575812 LP4Y_EN = 0x0
4932 12:26:53.575902 WORK_FSP = 0x0
4933 12:26:53.579141 WL = 0x3
4934 12:26:53.579233 RL = 0x3
4935 12:26:53.582768 BL = 0x2
4936 12:26:53.582874 RPST = 0x0
4937 12:26:53.585552 RD_PRE = 0x0
4938 12:26:53.588888 WR_PRE = 0x1
4939 12:26:53.588976 WR_PST = 0x0
4940 12:26:53.592101 DBI_WR = 0x0
4941 12:26:53.592189 DBI_RD = 0x0
4942 12:26:53.595463 OTF = 0x1
4943 12:26:53.599025 ===================================
4944 12:26:53.602334 ===================================
4945 12:26:53.602429 ANA top config
4946 12:26:53.605837 ===================================
4947 12:26:53.608690 DLL_ASYNC_EN = 0
4948 12:26:53.611858 ALL_SLAVE_EN = 1
4949 12:26:53.611953 NEW_RANK_MODE = 1
4950 12:26:53.615255 DLL_IDLE_MODE = 1
4951 12:26:53.618404 LP45_APHY_COMB_EN = 1
4952 12:26:53.621761 TX_ODT_DIS = 1
4953 12:26:53.625387 NEW_8X_MODE = 1
4954 12:26:53.628560 ===================================
4955 12:26:53.631730 ===================================
4956 12:26:53.631850 data_rate = 1866
4957 12:26:53.635124 CKR = 1
4958 12:26:53.638776 DQ_P2S_RATIO = 8
4959 12:26:53.642053 ===================================
4960 12:26:53.645311 CA_P2S_RATIO = 8
4961 12:26:53.648378 DQ_CA_OPEN = 0
4962 12:26:53.651595 DQ_SEMI_OPEN = 0
4963 12:26:53.651716 CA_SEMI_OPEN = 0
4964 12:26:53.655042 CA_FULL_RATE = 0
4965 12:26:53.658379 DQ_CKDIV4_EN = 1
4966 12:26:53.661596 CA_CKDIV4_EN = 1
4967 12:26:53.664829 CA_PREDIV_EN = 0
4968 12:26:53.668188 PH8_DLY = 0
4969 12:26:53.668310 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4970 12:26:53.671576 DQ_AAMCK_DIV = 4
4971 12:26:53.674945 CA_AAMCK_DIV = 4
4972 12:26:53.678203 CA_ADMCK_DIV = 4
4973 12:26:53.681585 DQ_TRACK_CA_EN = 0
4974 12:26:53.684774 CA_PICK = 933
4975 12:26:53.688158 CA_MCKIO = 933
4976 12:26:53.688276 MCKIO_SEMI = 0
4977 12:26:53.691304 PLL_FREQ = 3732
4978 12:26:53.694544 DQ_UI_PI_RATIO = 32
4979 12:26:53.697850 CA_UI_PI_RATIO = 0
4980 12:26:53.701029 ===================================
4981 12:26:53.704644 ===================================
4982 12:26:53.708035 memory_type:LPDDR4
4983 12:26:53.708157 GP_NUM : 10
4984 12:26:53.710946 SRAM_EN : 1
4985 12:26:53.714265 MD32_EN : 0
4986 12:26:53.717852 ===================================
4987 12:26:53.717975 [ANA_INIT] >>>>>>>>>>>>>>
4988 12:26:53.721086 <<<<<< [CONFIGURE PHASE]: ANA_TX
4989 12:26:53.724597 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4990 12:26:53.727496 ===================================
4991 12:26:53.731032 data_rate = 1866,PCW = 0X8f00
4992 12:26:53.734193 ===================================
4993 12:26:53.737663 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4994 12:26:53.744423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4995 12:26:53.747358 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4996 12:26:53.754387 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4997 12:26:53.757645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4998 12:26:53.760728 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4999 12:26:53.760853 [ANA_INIT] flow start
5000 12:26:53.764138 [ANA_INIT] PLL >>>>>>>>
5001 12:26:53.767452 [ANA_INIT] PLL <<<<<<<<
5002 12:26:53.770817 [ANA_INIT] MIDPI >>>>>>>>
5003 12:26:53.770900 [ANA_INIT] MIDPI <<<<<<<<
5004 12:26:53.774050 [ANA_INIT] DLL >>>>>>>>
5005 12:26:53.777430 [ANA_INIT] flow end
5006 12:26:53.780729 ============ LP4 DIFF to SE enter ============
5007 12:26:53.784044 ============ LP4 DIFF to SE exit ============
5008 12:26:53.787298 [ANA_INIT] <<<<<<<<<<<<<
5009 12:26:53.790509 [Flow] Enable top DCM control >>>>>
5010 12:26:53.793857 [Flow] Enable top DCM control <<<<<
5011 12:26:53.797109 Enable DLL master slave shuffle
5012 12:26:53.800355 ==============================================================
5013 12:26:53.803639 Gating Mode config
5014 12:26:53.810132 ==============================================================
5015 12:26:53.810246 Config description:
5016 12:26:53.819984 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5017 12:26:53.826881 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5018 12:26:53.830060 SELPH_MODE 0: By rank 1: By Phase
5019 12:26:53.836925 ==============================================================
5020 12:26:53.840083 GAT_TRACK_EN = 1
5021 12:26:53.843121 RX_GATING_MODE = 2
5022 12:26:53.846622 RX_GATING_TRACK_MODE = 2
5023 12:26:53.850062 SELPH_MODE = 1
5024 12:26:53.853398 PICG_EARLY_EN = 1
5025 12:26:53.856490 VALID_LAT_VALUE = 1
5026 12:26:53.859899 ==============================================================
5027 12:26:53.863317 Enter into Gating configuration >>>>
5028 12:26:53.866556 Exit from Gating configuration <<<<
5029 12:26:53.869458 Enter into DVFS_PRE_config >>>>>
5030 12:26:53.882922 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5031 12:26:53.886258 Exit from DVFS_PRE_config <<<<<
5032 12:26:53.886360 Enter into PICG configuration >>>>
5033 12:26:53.889641 Exit from PICG configuration <<<<
5034 12:26:53.892878 [RX_INPUT] configuration >>>>>
5035 12:26:53.896163 [RX_INPUT] configuration <<<<<
5036 12:26:53.902825 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5037 12:26:53.906123 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5038 12:26:53.912713 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5039 12:26:53.919334 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5040 12:26:53.925758 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5041 12:26:53.932406 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5042 12:26:53.935560 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5043 12:26:53.938887 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5044 12:26:53.945360 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5045 12:26:53.948611 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5046 12:26:53.952338 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5047 12:26:53.955518 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5048 12:26:53.958661 ===================================
5049 12:26:53.961912 LPDDR4 DRAM CONFIGURATION
5050 12:26:53.965128 ===================================
5051 12:26:53.968534 EX_ROW_EN[0] = 0x0
5052 12:26:53.968628 EX_ROW_EN[1] = 0x0
5053 12:26:53.971864 LP4Y_EN = 0x0
5054 12:26:53.971951 WORK_FSP = 0x0
5055 12:26:53.975226 WL = 0x3
5056 12:26:53.975329 RL = 0x3
5057 12:26:53.978473 BL = 0x2
5058 12:26:53.978561 RPST = 0x0
5059 12:26:53.981795 RD_PRE = 0x0
5060 12:26:53.985151 WR_PRE = 0x1
5061 12:26:53.985241 WR_PST = 0x0
5062 12:26:53.988416 DBI_WR = 0x0
5063 12:26:53.988501 DBI_RD = 0x0
5064 12:26:53.991739 OTF = 0x1
5065 12:26:53.995066 ===================================
5066 12:26:53.998281 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5067 12:26:54.001446 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5068 12:26:54.004989 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5069 12:26:54.008312 ===================================
5070 12:26:54.011567 LPDDR4 DRAM CONFIGURATION
5071 12:26:54.014662 ===================================
5072 12:26:54.018084 EX_ROW_EN[0] = 0x10
5073 12:26:54.018177 EX_ROW_EN[1] = 0x0
5074 12:26:54.021346 LP4Y_EN = 0x0
5075 12:26:54.021435 WORK_FSP = 0x0
5076 12:26:54.024629 WL = 0x3
5077 12:26:54.024715 RL = 0x3
5078 12:26:54.027899 BL = 0x2
5079 12:26:54.027986 RPST = 0x0
5080 12:26:54.031136 RD_PRE = 0x0
5081 12:26:54.034465 WR_PRE = 0x1
5082 12:26:54.034555 WR_PST = 0x0
5083 12:26:54.037714 DBI_WR = 0x0
5084 12:26:54.037801 DBI_RD = 0x0
5085 12:26:54.041300 OTF = 0x1
5086 12:26:54.044588 ===================================
5087 12:26:54.047742 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5088 12:26:54.053198 nWR fixed to 30
5089 12:26:54.056620 [ModeRegInit_LP4] CH0 RK0
5090 12:26:54.056730 [ModeRegInit_LP4] CH0 RK1
5091 12:26:54.059665 [ModeRegInit_LP4] CH1 RK0
5092 12:26:54.063187 [ModeRegInit_LP4] CH1 RK1
5093 12:26:54.063315 match AC timing 9
5094 12:26:54.069648 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5095 12:26:54.072905 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5096 12:26:54.076352 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5097 12:26:54.082983 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5098 12:26:54.086384 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5099 12:26:54.086478 ==
5100 12:26:54.089773 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 12:26:54.093056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 12:26:54.093145 ==
5103 12:26:54.099202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5104 12:26:54.105747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5105 12:26:54.109406 [CA 0] Center 37 (7~68) winsize 62
5106 12:26:54.112710 [CA 1] Center 38 (8~68) winsize 61
5107 12:26:54.116024 [CA 2] Center 35 (5~66) winsize 62
5108 12:26:54.119185 [CA 3] Center 34 (4~65) winsize 62
5109 12:26:54.122489 [CA 4] Center 34 (4~64) winsize 61
5110 12:26:54.125822 [CA 5] Center 33 (3~64) winsize 62
5111 12:26:54.125916
5112 12:26:54.128990 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5113 12:26:54.129078
5114 12:26:54.132336 [CATrainingPosCal] consider 1 rank data
5115 12:26:54.135474 u2DelayCellTimex100 = 270/100 ps
5116 12:26:54.138742 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5117 12:26:54.142281 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5118 12:26:54.145689 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5119 12:26:54.149080 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5120 12:26:54.155496 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5121 12:26:54.158810 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5122 12:26:54.158938
5123 12:26:54.162213 CA PerBit enable=1, Macro0, CA PI delay=33
5124 12:26:54.162305
5125 12:26:54.165614 [CBTSetCACLKResult] CA Dly = 33
5126 12:26:54.165741 CS Dly: 7 (0~38)
5127 12:26:54.165854 ==
5128 12:26:54.168726 Dram Type= 6, Freq= 0, CH_0, rank 1
5129 12:26:54.175404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 12:26:54.175510 ==
5131 12:26:54.178748 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5132 12:26:54.185319 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5133 12:26:54.188514 [CA 0] Center 38 (7~69) winsize 63
5134 12:26:54.191773 [CA 1] Center 38 (8~68) winsize 61
5135 12:26:54.195085 [CA 2] Center 36 (6~66) winsize 61
5136 12:26:54.198501 [CA 3] Center 35 (5~66) winsize 62
5137 12:26:54.201920 [CA 4] Center 34 (4~65) winsize 62
5138 12:26:54.205200 [CA 5] Center 34 (4~64) winsize 61
5139 12:26:54.205319
5140 12:26:54.208114 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5141 12:26:54.208203
5142 12:26:54.211583 [CATrainingPosCal] consider 2 rank data
5143 12:26:54.214890 u2DelayCellTimex100 = 270/100 ps
5144 12:26:54.218218 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5145 12:26:54.224531 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5146 12:26:54.227792 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5147 12:26:54.231217 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5148 12:26:54.234563 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5149 12:26:54.237761 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5150 12:26:54.237873
5151 12:26:54.241194 CA PerBit enable=1, Macro0, CA PI delay=34
5152 12:26:54.241278
5153 12:26:54.244469 [CBTSetCACLKResult] CA Dly = 34
5154 12:26:54.247637 CS Dly: 7 (0~39)
5155 12:26:54.247762
5156 12:26:54.251112 ----->DramcWriteLeveling(PI) begin...
5157 12:26:54.251222 ==
5158 12:26:54.254476 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 12:26:54.257792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 12:26:54.257923 ==
5161 12:26:54.260918 Write leveling (Byte 0): 32 => 32
5162 12:26:54.264625 Write leveling (Byte 1): 31 => 31
5163 12:26:54.267702 DramcWriteLeveling(PI) end<-----
5164 12:26:54.267783
5165 12:26:54.267848 ==
5166 12:26:54.271100 Dram Type= 6, Freq= 0, CH_0, rank 0
5167 12:26:54.274222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5168 12:26:54.274311 ==
5169 12:26:54.277783 [Gating] SW mode calibration
5170 12:26:54.284196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5171 12:26:54.290931 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5172 12:26:54.294208 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5173 12:26:54.297405 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 12:26:54.304031 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 12:26:54.307319 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 12:26:54.310599 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 12:26:54.317419 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5178 12:26:54.320248 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5179 12:26:54.323810 0 14 28 | B1->B0 | 2f2f 2424 | 0 0 | (1 0) (0 0)
5180 12:26:54.330249 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)
5181 12:26:54.333671 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 12:26:54.337047 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 12:26:54.343827 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 12:26:54.347182 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 12:26:54.350432 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 12:26:54.357058 0 15 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
5187 12:26:54.360296 0 15 28 | B1->B0 | 2a2a 4545 | 0 0 | (0 0) (0 0)
5188 12:26:54.363673 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 12:26:54.370081 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 12:26:54.373601 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 12:26:54.376544 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 12:26:54.383304 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 12:26:54.386550 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 12:26:54.389880 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5195 12:26:54.396649 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5196 12:26:54.399987 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5197 12:26:54.402911 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 12:26:54.410069 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 12:26:54.413327 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 12:26:54.416680 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 12:26:54.422907 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 12:26:54.426368 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 12:26:54.429666 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 12:26:54.436622 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 12:26:54.439874 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 12:26:54.443238 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 12:26:54.449519 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 12:26:54.452777 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 12:26:54.456128 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 12:26:54.462679 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 12:26:54.466055 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5212 12:26:54.469381 Total UI for P1: 0, mck2ui 16
5213 12:26:54.472579 best dqsien dly found for B0: ( 1, 2, 26)
5214 12:26:54.476170 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5215 12:26:54.479234 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 12:26:54.482597 Total UI for P1: 0, mck2ui 16
5217 12:26:54.485686 best dqsien dly found for B1: ( 1, 3, 0)
5218 12:26:54.492332 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5219 12:26:54.495635 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5220 12:26:54.495723
5221 12:26:54.498882 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5222 12:26:54.502207 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5223 12:26:54.505507 [Gating] SW calibration Done
5224 12:26:54.505599 ==
5225 12:26:54.508713 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 12:26:54.512129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 12:26:54.512219 ==
5228 12:26:54.515371 RX Vref Scan: 0
5229 12:26:54.515457
5230 12:26:54.515523 RX Vref 0 -> 0, step: 1
5231 12:26:54.515584
5232 12:26:54.518702 RX Delay -80 -> 252, step: 8
5233 12:26:54.522238 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5234 12:26:54.528696 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5235 12:26:54.531893 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5236 12:26:54.535475 iDelay=208, Bit 3, Center 107 (24 ~ 191) 168
5237 12:26:54.538495 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5238 12:26:54.541664 iDelay=208, Bit 5, Center 99 (16 ~ 183) 168
5239 12:26:54.548314 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5240 12:26:54.551864 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5241 12:26:54.555182 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5242 12:26:54.558405 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5243 12:26:54.561762 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5244 12:26:54.565204 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5245 12:26:54.571544 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5246 12:26:54.574828 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5247 12:26:54.578523 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5248 12:26:54.581634 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5249 12:26:54.581735 ==
5250 12:26:54.584679 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 12:26:54.591177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 12:26:54.591296 ==
5253 12:26:54.591367 DQS Delay:
5254 12:26:54.594821 DQS0 = 0, DQS1 = 0
5255 12:26:54.594937 DQM Delay:
5256 12:26:54.595017 DQM0 = 108, DQM1 = 91
5257 12:26:54.597824 DQ Delay:
5258 12:26:54.601088 DQ0 =107, DQ1 =111, DQ2 =103, DQ3 =107
5259 12:26:54.604271 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5260 12:26:54.607717 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5261 12:26:54.610957 DQ12 =91, DQ13 =91, DQ14 =103, DQ15 =103
5262 12:26:54.611048
5263 12:26:54.611152
5264 12:26:54.611214 ==
5265 12:26:54.614271 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 12:26:54.617610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 12:26:54.617700 ==
5268 12:26:54.617767
5269 12:26:54.620914
5270 12:26:54.621014 TX Vref Scan disable
5271 12:26:54.624126 == TX Byte 0 ==
5272 12:26:54.627780 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5273 12:26:54.631020 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5274 12:26:54.634276 == TX Byte 1 ==
5275 12:26:54.637613 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5276 12:26:54.641031 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5277 12:26:54.641123 ==
5278 12:26:54.643839 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 12:26:54.650542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 12:26:54.650655 ==
5281 12:26:54.650723
5282 12:26:54.650784
5283 12:26:54.650843 TX Vref Scan disable
5284 12:26:54.655115 == TX Byte 0 ==
5285 12:26:54.658171 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5286 12:26:54.665221 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5287 12:26:54.665341 == TX Byte 1 ==
5288 12:26:54.668124 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5289 12:26:54.674792 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5290 12:26:54.674896
5291 12:26:54.674973 [DATLAT]
5292 12:26:54.675037 Freq=933, CH0 RK0
5293 12:26:54.675098
5294 12:26:54.678029 DATLAT Default: 0xd
5295 12:26:54.681309 0, 0xFFFF, sum = 0
5296 12:26:54.681398 1, 0xFFFF, sum = 0
5297 12:26:54.684514 2, 0xFFFF, sum = 0
5298 12:26:54.684628 3, 0xFFFF, sum = 0
5299 12:26:54.688071 4, 0xFFFF, sum = 0
5300 12:26:54.688177 5, 0xFFFF, sum = 0
5301 12:26:54.691230 6, 0xFFFF, sum = 0
5302 12:26:54.691345 7, 0xFFFF, sum = 0
5303 12:26:54.694401 8, 0xFFFF, sum = 0
5304 12:26:54.694489 9, 0xFFFF, sum = 0
5305 12:26:54.697786 10, 0x0, sum = 1
5306 12:26:54.697902 11, 0x0, sum = 2
5307 12:26:54.701319 12, 0x0, sum = 3
5308 12:26:54.701480 13, 0x0, sum = 4
5309 12:26:54.701580 best_step = 11
5310 12:26:54.704675
5311 12:26:54.704810 ==
5312 12:26:54.707824 Dram Type= 6, Freq= 0, CH_0, rank 0
5313 12:26:54.711148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 12:26:54.711299 ==
5315 12:26:54.711405 RX Vref Scan: 1
5316 12:26:54.711496
5317 12:26:54.714435 RX Vref 0 -> 0, step: 1
5318 12:26:54.714549
5319 12:26:54.717924 RX Delay -53 -> 252, step: 4
5320 12:26:54.718019
5321 12:26:54.721198 Set Vref, RX VrefLevel [Byte0]: 59
5322 12:26:54.724472 [Byte1]: 48
5323 12:26:54.724554
5324 12:26:54.727641 Final RX Vref Byte 0 = 59 to rank0
5325 12:26:54.731135 Final RX Vref Byte 1 = 48 to rank0
5326 12:26:54.734353 Final RX Vref Byte 0 = 59 to rank1
5327 12:26:54.737694 Final RX Vref Byte 1 = 48 to rank1==
5328 12:26:54.740963 Dram Type= 6, Freq= 0, CH_0, rank 0
5329 12:26:54.744582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 12:26:54.747376 ==
5331 12:26:54.747486 DQS Delay:
5332 12:26:54.747580 DQS0 = 0, DQS1 = 0
5333 12:26:54.750785 DQM Delay:
5334 12:26:54.750871 DQM0 = 107, DQM1 = 92
5335 12:26:54.754039 DQ Delay:
5336 12:26:54.757259 DQ0 =108, DQ1 =108, DQ2 =104, DQ3 =106
5337 12:26:54.761063 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =112
5338 12:26:54.764299 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =90
5339 12:26:54.767612 DQ12 =94, DQ13 =96, DQ14 =102, DQ15 =100
5340 12:26:54.767740
5341 12:26:54.767844
5342 12:26:54.774229 [DQSOSCAuto] RK0, (LSB)MR18= 0x201c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5343 12:26:54.777397 CH0 RK0: MR19=505, MR18=201C
5344 12:26:54.784070 CH0_RK0: MR19=0x505, MR18=0x201C, DQSOSC=411, MR23=63, INC=64, DEC=42
5345 12:26:54.784202
5346 12:26:54.787394 ----->DramcWriteLeveling(PI) begin...
5347 12:26:54.787499 ==
5348 12:26:54.790707 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 12:26:54.793656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 12:26:54.793790 ==
5351 12:26:54.797264 Write leveling (Byte 0): 32 => 32
5352 12:26:54.800636 Write leveling (Byte 1): 30 => 30
5353 12:26:54.803465 DramcWriteLeveling(PI) end<-----
5354 12:26:54.803584
5355 12:26:54.803681 ==
5356 12:26:54.806994 Dram Type= 6, Freq= 0, CH_0, rank 1
5357 12:26:54.813553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 12:26:54.813705 ==
5359 12:26:54.813846 [Gating] SW mode calibration
5360 12:26:54.823574 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5361 12:26:54.826893 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5362 12:26:54.830277 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 12:26:54.836597 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 12:26:54.839978 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 12:26:54.843345 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 12:26:54.850181 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 12:26:54.853505 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 12:26:54.859617 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5369 12:26:54.863342 0 14 28 | B1->B0 | 2c2c 2727 | 1 0 | (0 1) (1 0)
5370 12:26:54.866608 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 12:26:54.869781 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 12:26:54.876474 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 12:26:54.879776 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 12:26:54.882981 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 12:26:54.889654 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 12:26:54.892931 0 15 24 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (0 0)
5377 12:26:54.895829 0 15 28 | B1->B0 | 4040 4444 | 1 0 | (0 0) (0 0)
5378 12:26:54.902790 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 12:26:54.906248 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 12:26:54.909296 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 12:26:54.915747 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 12:26:54.919367 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 12:26:54.922681 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 12:26:54.928799 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5385 12:26:54.932674 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5386 12:26:54.935913 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 12:26:54.942145 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 12:26:54.945544 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 12:26:54.948701 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 12:26:54.955236 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 12:26:54.958534 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 12:26:54.965159 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 12:26:54.968380 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 12:26:54.972105 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 12:26:54.978638 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 12:26:54.981469 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 12:26:54.984721 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 12:26:54.991420 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 12:26:54.994878 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 12:26:54.998219 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 12:26:55.004779 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5402 12:26:55.008070 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 12:26:55.011623 Total UI for P1: 0, mck2ui 16
5404 12:26:55.014660 best dqsien dly found for B0: ( 1, 2, 28)
5405 12:26:55.018171 Total UI for P1: 0, mck2ui 16
5406 12:26:55.021142 best dqsien dly found for B1: ( 1, 2, 28)
5407 12:26:55.024743 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5408 12:26:55.028101 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5409 12:26:55.028207
5410 12:26:55.031457 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5411 12:26:55.034670 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5412 12:26:55.037972 [Gating] SW calibration Done
5413 12:26:55.038063 ==
5414 12:26:55.041394 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 12:26:55.044486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 12:26:55.044602 ==
5417 12:26:55.047754 RX Vref Scan: 0
5418 12:26:55.047868
5419 12:26:55.051098 RX Vref 0 -> 0, step: 1
5420 12:26:55.051225
5421 12:26:55.051347 RX Delay -80 -> 252, step: 8
5422 12:26:55.057569 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5423 12:26:55.061246 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5424 12:26:55.064200 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5425 12:26:55.067442 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5426 12:26:55.070678 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5427 12:26:55.077727 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5428 12:26:55.080902 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5429 12:26:55.084064 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5430 12:26:55.087441 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5431 12:26:55.090818 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5432 12:26:55.093984 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5433 12:26:55.100514 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5434 12:26:55.103816 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5435 12:26:55.107121 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5436 12:26:55.110497 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5437 12:26:55.113897 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5438 12:26:55.114022 ==
5439 12:26:55.117333 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 12:26:55.123669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 12:26:55.123806 ==
5442 12:26:55.123904 DQS Delay:
5443 12:26:55.127042 DQS0 = 0, DQS1 = 0
5444 12:26:55.127123 DQM Delay:
5445 12:26:55.130017 DQM0 = 105, DQM1 = 90
5446 12:26:55.130104 DQ Delay:
5447 12:26:55.133340 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5448 12:26:55.136461 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5449 12:26:55.139878 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5450 12:26:55.143163 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5451 12:26:55.143245
5452 12:26:55.143310
5453 12:26:55.143369 ==
5454 12:26:55.146568 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 12:26:55.150146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 12:26:55.150302 ==
5457 12:26:55.150400
5458 12:26:55.153417
5459 12:26:55.153564 TX Vref Scan disable
5460 12:26:55.156740 == TX Byte 0 ==
5461 12:26:55.159568 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5462 12:26:55.163452 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5463 12:26:55.166237 == TX Byte 1 ==
5464 12:26:55.169770 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5465 12:26:55.173132 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5466 12:26:55.173220 ==
5467 12:26:55.176406 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 12:26:55.182975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 12:26:55.183082 ==
5470 12:26:55.183150
5471 12:26:55.183212
5472 12:26:55.183271 TX Vref Scan disable
5473 12:26:55.187143 == TX Byte 0 ==
5474 12:26:55.190497 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5475 12:26:55.197160 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5476 12:26:55.197262 == TX Byte 1 ==
5477 12:26:55.200455 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5478 12:26:55.207016 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5479 12:26:55.207119
5480 12:26:55.207186 [DATLAT]
5481 12:26:55.207250 Freq=933, CH0 RK1
5482 12:26:55.207311
5483 12:26:55.210429 DATLAT Default: 0xb
5484 12:26:55.213726 0, 0xFFFF, sum = 0
5485 12:26:55.213815 1, 0xFFFF, sum = 0
5486 12:26:55.217040 2, 0xFFFF, sum = 0
5487 12:26:55.217160 3, 0xFFFF, sum = 0
5488 12:26:55.220116 4, 0xFFFF, sum = 0
5489 12:26:55.220208 5, 0xFFFF, sum = 0
5490 12:26:55.223339 6, 0xFFFF, sum = 0
5491 12:26:55.223427 7, 0xFFFF, sum = 0
5492 12:26:55.226916 8, 0xFFFF, sum = 0
5493 12:26:55.227005 9, 0xFFFF, sum = 0
5494 12:26:55.230055 10, 0x0, sum = 1
5495 12:26:55.230144 11, 0x0, sum = 2
5496 12:26:55.233071 12, 0x0, sum = 3
5497 12:26:55.233174 13, 0x0, sum = 4
5498 12:26:55.236680 best_step = 11
5499 12:26:55.236801
5500 12:26:55.236871 ==
5501 12:26:55.239835 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 12:26:55.243428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 12:26:55.243513 ==
5504 12:26:55.243580 RX Vref Scan: 0
5505 12:26:55.243641
5506 12:26:55.246743 RX Vref 0 -> 0, step: 1
5507 12:26:55.246824
5508 12:26:55.250072 RX Delay -53 -> 252, step: 4
5509 12:26:55.256578 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5510 12:26:55.259836 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5511 12:26:55.263068 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5512 12:26:55.266697 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5513 12:26:55.270019 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5514 12:26:55.276535 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5515 12:26:55.279788 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5516 12:26:55.283030 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5517 12:26:55.286195 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5518 12:26:55.289502 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5519 12:26:55.292754 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5520 12:26:55.299798 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5521 12:26:55.302741 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5522 12:26:55.305935 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5523 12:26:55.309342 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5524 12:26:55.312646 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5525 12:26:55.315899 ==
5526 12:26:55.319247 Dram Type= 6, Freq= 0, CH_0, rank 1
5527 12:26:55.322856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 12:26:55.322951 ==
5529 12:26:55.323019 DQS Delay:
5530 12:26:55.325833 DQS0 = 0, DQS1 = 0
5531 12:26:55.325919 DQM Delay:
5532 12:26:55.329064 DQM0 = 104, DQM1 = 92
5533 12:26:55.329148 DQ Delay:
5534 12:26:55.332695 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5535 12:26:55.335884 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5536 12:26:55.339071 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =92
5537 12:26:55.342677 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5538 12:26:55.342776
5539 12:26:55.342844
5540 12:26:55.352499 [DQSOSCAuto] RK1, (LSB)MR18= 0x2708, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5541 12:26:55.352618 CH0 RK1: MR19=505, MR18=2708
5542 12:26:55.358897 CH0_RK1: MR19=0x505, MR18=0x2708, DQSOSC=409, MR23=63, INC=64, DEC=43
5543 12:26:55.362261 [RxdqsGatingPostProcess] freq 933
5544 12:26:55.369044 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5545 12:26:55.372251 best DQS0 dly(2T, 0.5T) = (0, 10)
5546 12:26:55.375600 best DQS1 dly(2T, 0.5T) = (0, 11)
5547 12:26:55.378914 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5548 12:26:55.382334 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5549 12:26:55.385393 best DQS0 dly(2T, 0.5T) = (0, 10)
5550 12:26:55.385484 best DQS1 dly(2T, 0.5T) = (0, 10)
5551 12:26:55.388657 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5552 12:26:55.392040 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5553 12:26:55.395255 Pre-setting of DQS Precalculation
5554 12:26:55.401862 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5555 12:26:55.401984 ==
5556 12:26:55.405215 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 12:26:55.408537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 12:26:55.408651 ==
5559 12:26:55.415181 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5560 12:26:55.421484 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5561 12:26:55.424890 [CA 0] Center 37 (7~68) winsize 62
5562 12:26:55.428428 [CA 1] Center 37 (7~68) winsize 62
5563 12:26:55.431651 [CA 2] Center 35 (5~66) winsize 62
5564 12:26:55.435003 [CA 3] Center 34 (4~65) winsize 62
5565 12:26:55.438114 [CA 4] Center 35 (5~65) winsize 61
5566 12:26:55.441555 [CA 5] Center 34 (4~64) winsize 61
5567 12:26:55.441644
5568 12:26:55.444684 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5569 12:26:55.444816
5570 12:26:55.448266 [CATrainingPosCal] consider 1 rank data
5571 12:26:55.451373 u2DelayCellTimex100 = 270/100 ps
5572 12:26:55.454543 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5573 12:26:55.458135 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5574 12:26:55.461468 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5575 12:26:55.464712 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5576 12:26:55.467980 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5577 12:26:55.471190 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5578 12:26:55.471275
5579 12:26:55.478132 CA PerBit enable=1, Macro0, CA PI delay=34
5580 12:26:55.478245
5581 12:26:55.481002 [CBTSetCACLKResult] CA Dly = 34
5582 12:26:55.481089 CS Dly: 6 (0~37)
5583 12:26:55.481158 ==
5584 12:26:55.484272 Dram Type= 6, Freq= 0, CH_1, rank 1
5585 12:26:55.488004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 12:26:55.488095 ==
5587 12:26:55.494380 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5588 12:26:55.501065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5589 12:26:55.504418 [CA 0] Center 37 (7~68) winsize 62
5590 12:26:55.507613 [CA 1] Center 38 (7~69) winsize 63
5591 12:26:55.510892 [CA 2] Center 36 (6~66) winsize 61
5592 12:26:55.514146 [CA 3] Center 35 (6~65) winsize 60
5593 12:26:55.517431 [CA 4] Center 35 (5~65) winsize 61
5594 12:26:55.520701 [CA 5] Center 35 (5~65) winsize 61
5595 12:26:55.520850
5596 12:26:55.524094 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5597 12:26:55.524182
5598 12:26:55.527395 [CATrainingPosCal] consider 2 rank data
5599 12:26:55.530685 u2DelayCellTimex100 = 270/100 ps
5600 12:26:55.533877 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5601 12:26:55.537113 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5602 12:26:55.540376 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5603 12:26:55.547161 CA3 delay=35 (6~65),Diff = 1 PI (6 cell)
5604 12:26:55.550708 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5605 12:26:55.553714 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5606 12:26:55.553807
5607 12:26:55.556870 CA PerBit enable=1, Macro0, CA PI delay=34
5608 12:26:55.556975
5609 12:26:55.560301 [CBTSetCACLKResult] CA Dly = 34
5610 12:26:55.560394 CS Dly: 7 (0~39)
5611 12:26:55.560502
5612 12:26:55.563385 ----->DramcWriteLeveling(PI) begin...
5613 12:26:55.563503 ==
5614 12:26:55.567090 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 12:26:55.573630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 12:26:55.573739 ==
5617 12:26:55.576961 Write leveling (Byte 0): 26 => 26
5618 12:26:55.579979 Write leveling (Byte 1): 28 => 28
5619 12:26:55.583210 DramcWriteLeveling(PI) end<-----
5620 12:26:55.583291
5621 12:26:55.583354 ==
5622 12:26:55.586603 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 12:26:55.589804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 12:26:55.589919 ==
5625 12:26:55.593062 [Gating] SW mode calibration
5626 12:26:55.599646 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5627 12:26:55.606349 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5628 12:26:55.609623 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 12:26:55.612903 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 12:26:55.616267 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 12:26:55.622975 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 12:26:55.626431 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 12:26:55.629838 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 12:26:55.635956 0 14 24 | B1->B0 | 3030 2f2f | 0 0 | (1 0) (0 0)
5635 12:26:55.639350 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 12:26:55.642641 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 12:26:55.649167 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 12:26:55.652554 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 12:26:55.656103 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 12:26:55.662760 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 12:26:55.665805 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 12:26:55.669381 0 15 24 | B1->B0 | 2929 2e2e | 0 0 | (0 0) (0 0)
5643 12:26:55.675771 0 15 28 | B1->B0 | 4141 4545 | 0 0 | (1 1) (0 0)
5644 12:26:55.679088 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 12:26:55.682201 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 12:26:55.688782 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 12:26:55.692180 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 12:26:55.695445 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 12:26:55.702376 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5650 12:26:55.705685 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5651 12:26:55.708877 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5652 12:26:55.715662 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 12:26:55.718490 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 12:26:55.722104 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 12:26:55.728687 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 12:26:55.731963 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 12:26:55.734783 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 12:26:55.741824 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 12:26:55.744871 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 12:26:55.748220 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 12:26:55.754882 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 12:26:55.758118 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 12:26:55.761541 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 12:26:55.768099 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 12:26:55.771157 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 12:26:55.774750 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5667 12:26:55.781268 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 12:26:55.784233 Total UI for P1: 0, mck2ui 16
5669 12:26:55.787594 best dqsien dly found for B0: ( 1, 2, 24)
5670 12:26:55.790924 Total UI for P1: 0, mck2ui 16
5671 12:26:55.794257 best dqsien dly found for B1: ( 1, 2, 26)
5672 12:26:55.797630 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5673 12:26:55.800895 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5674 12:26:55.801025
5675 12:26:55.804482 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5676 12:26:55.807348 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5677 12:26:55.811000 [Gating] SW calibration Done
5678 12:26:55.811128 ==
5679 12:26:55.814350 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 12:26:55.817667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 12:26:55.817785 ==
5682 12:26:55.821003 RX Vref Scan: 0
5683 12:26:55.821120
5684 12:26:55.824254 RX Vref 0 -> 0, step: 1
5685 12:26:55.824374
5686 12:26:55.824480 RX Delay -80 -> 252, step: 8
5687 12:26:55.830732 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5688 12:26:55.833998 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5689 12:26:55.836874 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5690 12:26:55.840207 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5691 12:26:55.843457 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5692 12:26:55.850206 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5693 12:26:55.853500 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5694 12:26:55.856878 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5695 12:26:55.860091 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5696 12:26:55.863440 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5697 12:26:55.866751 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5698 12:26:55.873369 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5699 12:26:55.876387 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5700 12:26:55.879904 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5701 12:26:55.883464 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5702 12:26:55.886584 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5703 12:26:55.886721 ==
5704 12:26:55.889950 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 12:26:55.896317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 12:26:55.896460 ==
5707 12:26:55.896564 DQS Delay:
5708 12:26:55.899591 DQS0 = 0, DQS1 = 0
5709 12:26:55.899704 DQM Delay:
5710 12:26:55.903022 DQM0 = 102, DQM1 = 94
5711 12:26:55.903135 DQ Delay:
5712 12:26:55.906208 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5713 12:26:55.909526 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5714 12:26:55.912742 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5715 12:26:55.916448 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =99
5716 12:26:55.916571
5717 12:26:55.916671
5718 12:26:55.916792 ==
5719 12:26:55.919710 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 12:26:55.923097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 12:26:55.923215 ==
5722 12:26:55.923324
5723 12:26:55.926415
5724 12:26:55.926498 TX Vref Scan disable
5725 12:26:55.929735 == TX Byte 0 ==
5726 12:26:55.932556 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5727 12:26:55.935926 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5728 12:26:55.939199 == TX Byte 1 ==
5729 12:26:55.942596 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5730 12:26:55.945969 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5731 12:26:55.946082 ==
5732 12:26:55.949132 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 12:26:55.955812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 12:26:55.955945 ==
5735 12:26:55.956050
5736 12:26:55.956150
5737 12:26:55.956242 TX Vref Scan disable
5738 12:26:55.960118 == TX Byte 0 ==
5739 12:26:55.963388 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5740 12:26:55.970064 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5741 12:26:55.970227 == TX Byte 1 ==
5742 12:26:55.973397 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5743 12:26:55.980025 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5744 12:26:55.980173
5745 12:26:55.980286 [DATLAT]
5746 12:26:55.980388 Freq=933, CH1 RK0
5747 12:26:55.980488
5748 12:26:55.983217 DATLAT Default: 0xd
5749 12:26:55.983333 0, 0xFFFF, sum = 0
5750 12:26:55.986438 1, 0xFFFF, sum = 0
5751 12:26:55.989994 2, 0xFFFF, sum = 0
5752 12:26:55.990118 3, 0xFFFF, sum = 0
5753 12:26:55.993065 4, 0xFFFF, sum = 0
5754 12:26:55.993185 5, 0xFFFF, sum = 0
5755 12:26:55.996481 6, 0xFFFF, sum = 0
5756 12:26:55.996596 7, 0xFFFF, sum = 0
5757 12:26:55.999834 8, 0xFFFF, sum = 0
5758 12:26:55.999958 9, 0xFFFF, sum = 0
5759 12:26:56.002903 10, 0x0, sum = 1
5760 12:26:56.003019 11, 0x0, sum = 2
5761 12:26:56.006619 12, 0x0, sum = 3
5762 12:26:56.006736 13, 0x0, sum = 4
5763 12:26:56.006854 best_step = 11
5764 12:26:56.009728
5765 12:26:56.009848 ==
5766 12:26:56.013103 Dram Type= 6, Freq= 0, CH_1, rank 0
5767 12:26:56.016345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 12:26:56.016462 ==
5769 12:26:56.016561 RX Vref Scan: 1
5770 12:26:56.016675
5771 12:26:56.019581 RX Vref 0 -> 0, step: 1
5772 12:26:56.019695
5773 12:26:56.022575 RX Delay -53 -> 252, step: 4
5774 12:26:56.022686
5775 12:26:56.026400 Set Vref, RX VrefLevel [Byte0]: 53
5776 12:26:56.029213 [Byte1]: 51
5777 12:26:56.029334
5778 12:26:56.032582 Final RX Vref Byte 0 = 53 to rank0
5779 12:26:56.035921 Final RX Vref Byte 1 = 51 to rank0
5780 12:26:56.039191 Final RX Vref Byte 0 = 53 to rank1
5781 12:26:56.042578 Final RX Vref Byte 1 = 51 to rank1==
5782 12:26:56.045873 Dram Type= 6, Freq= 0, CH_1, rank 0
5783 12:26:56.052607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 12:26:56.052737 ==
5785 12:26:56.052830 DQS Delay:
5786 12:26:56.052912 DQS0 = 0, DQS1 = 0
5787 12:26:56.056055 DQM Delay:
5788 12:26:56.056156 DQM0 = 105, DQM1 = 97
5789 12:26:56.058983 DQ Delay:
5790 12:26:56.062251 DQ0 =110, DQ1 =98, DQ2 =96, DQ3 =104
5791 12:26:56.065542 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5792 12:26:56.068848 DQ8 =86, DQ9 =86, DQ10 =102, DQ11 =90
5793 12:26:56.072236 DQ12 =104, DQ13 =102, DQ14 =104, DQ15 =104
5794 12:26:56.072369
5795 12:26:56.072472
5796 12:26:56.078835 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c34, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5797 12:26:56.082291 CH1 RK0: MR19=505, MR18=1C34
5798 12:26:56.088841 CH1_RK0: MR19=0x505, MR18=0x1C34, DQSOSC=405, MR23=63, INC=66, DEC=44
5799 12:26:56.088968
5800 12:26:56.092345 ----->DramcWriteLeveling(PI) begin...
5801 12:26:56.092456 ==
5802 12:26:56.095301 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 12:26:56.099006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 12:26:56.102019 ==
5805 12:26:56.102113 Write leveling (Byte 0): 27 => 27
5806 12:26:56.105151 Write leveling (Byte 1): 27 => 27
5807 12:26:56.108622 DramcWriteLeveling(PI) end<-----
5808 12:26:56.108729
5809 12:26:56.108828 ==
5810 12:26:56.112116 Dram Type= 6, Freq= 0, CH_1, rank 1
5811 12:26:56.118428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 12:26:56.118531 ==
5813 12:26:56.121679 [Gating] SW mode calibration
5814 12:26:56.128676 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5815 12:26:56.131492 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5816 12:26:56.138126 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5817 12:26:56.141588 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 12:26:56.144771 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 12:26:56.151544 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 12:26:56.154858 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5821 12:26:56.158059 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 12:26:56.164871 0 14 24 | B1->B0 | 2f2f 3434 | 0 0 | (0 1) (0 1)
5823 12:26:56.167798 0 14 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5824 12:26:56.171568 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5825 12:26:56.177840 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 12:26:56.181168 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 12:26:56.184486 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 12:26:56.190877 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 12:26:56.194173 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 12:26:56.197343 0 15 24 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
5831 12:26:56.204305 0 15 28 | B1->B0 | 4444 3c3c | 0 1 | (0 0) (0 0)
5832 12:26:56.207435 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 12:26:56.210869 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 12:26:56.217370 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 12:26:56.220761 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 12:26:56.224115 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 12:26:56.230436 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 12:26:56.233725 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5839 12:26:56.237040 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5840 12:26:56.243447 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 12:26:56.246672 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 12:26:56.250079 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 12:26:56.256757 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 12:26:56.260089 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 12:26:56.263366 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 12:26:56.269867 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 12:26:56.273166 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 12:26:56.276597 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 12:26:56.283139 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 12:26:56.286472 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 12:26:56.289751 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 12:26:56.296140 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 12:26:56.299511 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 12:26:56.302858 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5855 12:26:56.309331 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5856 12:26:56.312792 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5857 12:26:56.315824 Total UI for P1: 0, mck2ui 16
5858 12:26:56.319358 best dqsien dly found for B0: ( 1, 2, 26)
5859 12:26:56.322760 Total UI for P1: 0, mck2ui 16
5860 12:26:56.325833 best dqsien dly found for B1: ( 1, 2, 26)
5861 12:26:56.329412 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5862 12:26:56.332677 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5863 12:26:56.332834
5864 12:26:56.336047 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5865 12:26:56.339280 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5866 12:26:56.342674 [Gating] SW calibration Done
5867 12:26:56.342792 ==
5868 12:26:56.345491 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 12:26:56.352180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 12:26:56.352306 ==
5871 12:26:56.352403 RX Vref Scan: 0
5872 12:26:56.352495
5873 12:26:56.355448 RX Vref 0 -> 0, step: 1
5874 12:26:56.355535
5875 12:26:56.359204 RX Delay -80 -> 252, step: 8
5876 12:26:56.361958 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5877 12:26:56.365265 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5878 12:26:56.368300 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5879 12:26:56.375360 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5880 12:26:56.378635 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5881 12:26:56.381924 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5882 12:26:56.385314 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5883 12:26:56.388581 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5884 12:26:56.391382 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5885 12:26:56.398420 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5886 12:26:56.401581 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5887 12:26:56.404810 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5888 12:26:56.408301 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5889 12:26:56.411426 iDelay=200, Bit 13, Center 103 (16 ~ 191) 176
5890 12:26:56.418283 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5891 12:26:56.421357 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5892 12:26:56.421455 ==
5893 12:26:56.424479 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 12:26:56.427929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 12:26:56.428025 ==
5896 12:26:56.430992 DQS Delay:
5897 12:26:56.431083 DQS0 = 0, DQS1 = 0
5898 12:26:56.434269 DQM Delay:
5899 12:26:56.434357 DQM0 = 103, DQM1 = 96
5900 12:26:56.434425 DQ Delay:
5901 12:26:56.437773 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5902 12:26:56.441128 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5903 12:26:56.444506 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5904 12:26:56.451006 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5905 12:26:56.451101
5906 12:26:56.451170
5907 12:26:56.451248 ==
5908 12:26:56.454273 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 12:26:56.457604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 12:26:56.457681 ==
5911 12:26:56.457746
5912 12:26:56.457807
5913 12:26:56.460899 TX Vref Scan disable
5914 12:26:56.460972 == TX Byte 0 ==
5915 12:26:56.467515 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5916 12:26:56.470828 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5917 12:26:56.470911 == TX Byte 1 ==
5918 12:26:56.477627 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5919 12:26:56.480508 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5920 12:26:56.480631 ==
5921 12:26:56.483817 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 12:26:56.487159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 12:26:56.487281 ==
5924 12:26:56.487373
5925 12:26:56.490543
5926 12:26:56.490614 TX Vref Scan disable
5927 12:26:56.493860 == TX Byte 0 ==
5928 12:26:56.497622 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5929 12:26:56.500699 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5930 12:26:56.503949 == TX Byte 1 ==
5931 12:26:56.507163 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5932 12:26:56.510538 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5933 12:26:56.513894
5934 12:26:56.513988 [DATLAT]
5935 12:26:56.514055 Freq=933, CH1 RK1
5936 12:26:56.514119
5937 12:26:56.517143 DATLAT Default: 0xb
5938 12:26:56.517240 0, 0xFFFF, sum = 0
5939 12:26:56.520565 1, 0xFFFF, sum = 0
5940 12:26:56.520673 2, 0xFFFF, sum = 0
5941 12:26:56.523790 3, 0xFFFF, sum = 0
5942 12:26:56.526983 4, 0xFFFF, sum = 0
5943 12:26:56.527086 5, 0xFFFF, sum = 0
5944 12:26:56.530108 6, 0xFFFF, sum = 0
5945 12:26:56.530225 7, 0xFFFF, sum = 0
5946 12:26:56.533728 8, 0xFFFF, sum = 0
5947 12:26:56.533836 9, 0xFFFF, sum = 0
5948 12:26:56.536949 10, 0x0, sum = 1
5949 12:26:56.537039 11, 0x0, sum = 2
5950 12:26:56.540263 12, 0x0, sum = 3
5951 12:26:56.540352 13, 0x0, sum = 4
5952 12:26:56.540421 best_step = 11
5953 12:26:56.540484
5954 12:26:56.543519 ==
5955 12:26:56.546834 Dram Type= 6, Freq= 0, CH_1, rank 1
5956 12:26:56.550178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5957 12:26:56.550257 ==
5958 12:26:56.550322 RX Vref Scan: 0
5959 12:26:56.550382
5960 12:26:56.553493 RX Vref 0 -> 0, step: 1
5961 12:26:56.553578
5962 12:26:56.556690 RX Delay -53 -> 252, step: 4
5963 12:26:56.563257 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5964 12:26:56.566572 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5965 12:26:56.569856 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5966 12:26:56.573098 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5967 12:26:56.576258 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5968 12:26:56.583142 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5969 12:26:56.585975 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5970 12:26:56.589357 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5971 12:26:56.592685 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5972 12:26:56.596111 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5973 12:26:56.599393 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5974 12:26:56.606031 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5975 12:26:56.609133 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5976 12:26:56.612421 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5977 12:26:56.615638 iDelay=199, Bit 14, Center 106 (19 ~ 194) 176
5978 12:26:56.622291 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5979 12:26:56.622416 ==
5980 12:26:56.625909 Dram Type= 6, Freq= 0, CH_1, rank 1
5981 12:26:56.628933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5982 12:26:56.629024 ==
5983 12:26:56.629091 DQS Delay:
5984 12:26:56.632551 DQS0 = 0, DQS1 = 0
5985 12:26:56.632652 DQM Delay:
5986 12:26:56.635677 DQM0 = 105, DQM1 = 98
5987 12:26:56.635766 DQ Delay:
5988 12:26:56.638696 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5989 12:26:56.642165 DQ4 =106, DQ5 =116, DQ6 =114, DQ7 =102
5990 12:26:56.645704 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92
5991 12:26:56.648728 DQ12 =108, DQ13 =104, DQ14 =106, DQ15 =108
5992 12:26:56.648855
5993 12:26:56.648923
5994 12:26:56.658647 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
5995 12:26:56.662014 CH1 RK1: MR19=504, MR18=20FD
5996 12:26:56.665286 CH1_RK1: MR19=0x504, MR18=0x20FD, DQSOSC=411, MR23=63, INC=64, DEC=42
5997 12:26:56.668515 [RxdqsGatingPostProcess] freq 933
5998 12:26:56.675056 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5999 12:26:56.678430 best DQS0 dly(2T, 0.5T) = (0, 10)
6000 12:26:56.681612 best DQS1 dly(2T, 0.5T) = (0, 10)
6001 12:26:56.684751 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6002 12:26:56.688246 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6003 12:26:56.691549 best DQS0 dly(2T, 0.5T) = (0, 10)
6004 12:26:56.694849 best DQS1 dly(2T, 0.5T) = (0, 10)
6005 12:26:56.698156 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6006 12:26:56.701559 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6007 12:26:56.704690 Pre-setting of DQS Precalculation
6008 12:26:56.708180 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6009 12:26:56.714956 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6010 12:26:56.721732 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6011 12:26:56.721846
6012 12:26:56.721914
6013 12:26:56.725050 [Calibration Summary] 1866 Mbps
6014 12:26:56.728358 CH 0, Rank 0
6015 12:26:56.728446 SW Impedance : PASS
6016 12:26:56.731675 DUTY Scan : NO K
6017 12:26:56.734712 ZQ Calibration : PASS
6018 12:26:56.734800 Jitter Meter : NO K
6019 12:26:56.738096 CBT Training : PASS
6020 12:26:56.741548 Write leveling : PASS
6021 12:26:56.741655 RX DQS gating : PASS
6022 12:26:56.744644 RX DQ/DQS(RDDQC) : PASS
6023 12:26:56.747690 TX DQ/DQS : PASS
6024 12:26:56.747779 RX DATLAT : PASS
6025 12:26:56.751185 RX DQ/DQS(Engine): PASS
6026 12:26:56.754622 TX OE : NO K
6027 12:26:56.754774 All Pass.
6028 12:26:56.754901
6029 12:26:56.755022 CH 0, Rank 1
6030 12:26:56.757794 SW Impedance : PASS
6031 12:26:56.761080 DUTY Scan : NO K
6032 12:26:56.761169 ZQ Calibration : PASS
6033 12:26:56.764321 Jitter Meter : NO K
6034 12:26:56.767496 CBT Training : PASS
6035 12:26:56.767652 Write leveling : PASS
6036 12:26:56.770779 RX DQS gating : PASS
6037 12:26:56.770892 RX DQ/DQS(RDDQC) : PASS
6038 12:26:56.774144 TX DQ/DQS : PASS
6039 12:26:56.777456 RX DATLAT : PASS
6040 12:26:56.777542 RX DQ/DQS(Engine): PASS
6041 12:26:56.780720 TX OE : NO K
6042 12:26:56.780851 All Pass.
6043 12:26:56.780920
6044 12:26:56.784112 CH 1, Rank 0
6045 12:26:56.784224 SW Impedance : PASS
6046 12:26:56.787826 DUTY Scan : NO K
6047 12:26:56.790963 ZQ Calibration : PASS
6048 12:26:56.791052 Jitter Meter : NO K
6049 12:26:56.794286 CBT Training : PASS
6050 12:26:56.797739 Write leveling : PASS
6051 12:26:56.797828 RX DQS gating : PASS
6052 12:26:56.800543 RX DQ/DQS(RDDQC) : PASS
6053 12:26:56.804362 TX DQ/DQS : PASS
6054 12:26:56.804483 RX DATLAT : PASS
6055 12:26:56.807598 RX DQ/DQS(Engine): PASS
6056 12:26:56.810846 TX OE : NO K
6057 12:26:56.810952 All Pass.
6058 12:26:56.811021
6059 12:26:56.811084 CH 1, Rank 1
6060 12:26:56.814114 SW Impedance : PASS
6061 12:26:56.817262 DUTY Scan : NO K
6062 12:26:56.817350 ZQ Calibration : PASS
6063 12:26:56.820896 Jitter Meter : NO K
6064 12:26:56.824257 CBT Training : PASS
6065 12:26:56.824374 Write leveling : PASS
6066 12:26:56.827135 RX DQS gating : PASS
6067 12:26:56.830544 RX DQ/DQS(RDDQC) : PASS
6068 12:26:56.830632 TX DQ/DQS : PASS
6069 12:26:56.833857 RX DATLAT : PASS
6070 12:26:56.833944 RX DQ/DQS(Engine): PASS
6071 12:26:56.837186 TX OE : NO K
6072 12:26:56.837274 All Pass.
6073 12:26:56.837350
6074 12:26:56.840350 DramC Write-DBI off
6075 12:26:56.843596 PER_BANK_REFRESH: Hybrid Mode
6076 12:26:56.843714 TX_TRACKING: ON
6077 12:26:56.853667 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6078 12:26:56.857120 [FAST_K] Save calibration result to emmc
6079 12:26:56.860260 dramc_set_vcore_voltage set vcore to 650000
6080 12:26:56.863945 Read voltage for 400, 6
6081 12:26:56.864046 Vio18 = 0
6082 12:26:56.866804 Vcore = 650000
6083 12:26:56.866890 Vdram = 0
6084 12:26:56.866961 Vddq = 0
6085 12:26:56.867024 Vmddr = 0
6086 12:26:56.873577 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6087 12:26:56.880140 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6088 12:26:56.880263 MEM_TYPE=3, freq_sel=20
6089 12:26:56.883360 sv_algorithm_assistance_LP4_800
6090 12:26:56.886760 ============ PULL DRAM RESETB DOWN ============
6091 12:26:56.893084 ========== PULL DRAM RESETB DOWN end =========
6092 12:26:56.896406 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6093 12:26:56.899772 ===================================
6094 12:26:56.903193 LPDDR4 DRAM CONFIGURATION
6095 12:26:56.906508 ===================================
6096 12:26:56.906613 EX_ROW_EN[0] = 0x0
6097 12:26:56.909714 EX_ROW_EN[1] = 0x0
6098 12:26:56.913033 LP4Y_EN = 0x0
6099 12:26:56.913115 WORK_FSP = 0x0
6100 12:26:56.915945 WL = 0x2
6101 12:26:56.916023 RL = 0x2
6102 12:26:56.919492 BL = 0x2
6103 12:26:56.919573 RPST = 0x0
6104 12:26:56.922689 RD_PRE = 0x0
6105 12:26:56.922771 WR_PRE = 0x1
6106 12:26:56.926098 WR_PST = 0x0
6107 12:26:56.926177 DBI_WR = 0x0
6108 12:26:56.929421 DBI_RD = 0x0
6109 12:26:56.929498 OTF = 0x1
6110 12:26:56.932661 ===================================
6111 12:26:56.936009 ===================================
6112 12:26:56.939356 ANA top config
6113 12:26:56.942583 ===================================
6114 12:26:56.942670 DLL_ASYNC_EN = 0
6115 12:26:56.945801 ALL_SLAVE_EN = 1
6116 12:26:56.949244 NEW_RANK_MODE = 1
6117 12:26:56.952468 DLL_IDLE_MODE = 1
6118 12:26:56.955837 LP45_APHY_COMB_EN = 1
6119 12:26:56.955930 TX_ODT_DIS = 1
6120 12:26:56.958953 NEW_8X_MODE = 1
6121 12:26:56.962227 ===================================
6122 12:26:56.965549 ===================================
6123 12:26:56.968687 data_rate = 800
6124 12:26:56.972376 CKR = 1
6125 12:26:56.975384 DQ_P2S_RATIO = 4
6126 12:26:56.978882 ===================================
6127 12:26:56.982254 CA_P2S_RATIO = 4
6128 12:26:56.982351 DQ_CA_OPEN = 0
6129 12:26:56.985584 DQ_SEMI_OPEN = 1
6130 12:26:56.988474 CA_SEMI_OPEN = 1
6131 12:26:56.991753 CA_FULL_RATE = 0
6132 12:26:56.995034 DQ_CKDIV4_EN = 0
6133 12:26:56.998680 CA_CKDIV4_EN = 1
6134 12:26:56.998797 CA_PREDIV_EN = 0
6135 12:26:57.001545 PH8_DLY = 0
6136 12:26:57.004915 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6137 12:26:57.008241 DQ_AAMCK_DIV = 0
6138 12:26:57.011551 CA_AAMCK_DIV = 0
6139 12:26:57.014875 CA_ADMCK_DIV = 4
6140 12:26:57.014995 DQ_TRACK_CA_EN = 0
6141 12:26:57.018166 CA_PICK = 800
6142 12:26:57.021493 CA_MCKIO = 400
6143 12:26:57.024693 MCKIO_SEMI = 400
6144 12:26:57.028347 PLL_FREQ = 3016
6145 12:26:57.031722 DQ_UI_PI_RATIO = 32
6146 12:26:57.034573 CA_UI_PI_RATIO = 32
6147 12:26:57.037908 ===================================
6148 12:26:57.041585 ===================================
6149 12:26:57.041708 memory_type:LPDDR4
6150 12:26:57.044473 GP_NUM : 10
6151 12:26:57.048053 SRAM_EN : 1
6152 12:26:57.048164 MD32_EN : 0
6153 12:26:57.051339 ===================================
6154 12:26:57.054636 [ANA_INIT] >>>>>>>>>>>>>>
6155 12:26:57.057822 <<<<<< [CONFIGURE PHASE]: ANA_TX
6156 12:26:57.061110 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6157 12:26:57.064312 ===================================
6158 12:26:57.067795 data_rate = 800,PCW = 0X7400
6159 12:26:57.070824 ===================================
6160 12:26:57.074223 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6161 12:26:57.077568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6162 12:26:57.091072 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6163 12:26:57.093861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6164 12:26:57.097635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6165 12:26:57.101062 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6166 12:26:57.104125 [ANA_INIT] flow start
6167 12:26:57.107475 [ANA_INIT] PLL >>>>>>>>
6168 12:26:57.107600 [ANA_INIT] PLL <<<<<<<<
6169 12:26:57.110752 [ANA_INIT] MIDPI >>>>>>>>
6170 12:26:57.114208 [ANA_INIT] MIDPI <<<<<<<<
6171 12:26:57.117441 [ANA_INIT] DLL >>>>>>>>
6172 12:26:57.117566 [ANA_INIT] flow end
6173 12:26:57.120785 ============ LP4 DIFF to SE enter ============
6174 12:26:57.127286 ============ LP4 DIFF to SE exit ============
6175 12:26:57.127424 [ANA_INIT] <<<<<<<<<<<<<
6176 12:26:57.130457 [Flow] Enable top DCM control >>>>>
6177 12:26:57.133713 [Flow] Enable top DCM control <<<<<
6178 12:26:57.137372 Enable DLL master slave shuffle
6179 12:26:57.143950 ==============================================================
6180 12:26:57.144065 Gating Mode config
6181 12:26:57.150534 ==============================================================
6182 12:26:57.153612 Config description:
6183 12:26:57.160747 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6184 12:26:57.170531 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6185 12:26:57.173550 SELPH_MODE 0: By rank 1: By Phase
6186 12:26:57.180282 ==============================================================
6187 12:26:57.183476 GAT_TRACK_EN = 0
6188 12:26:57.183578 RX_GATING_MODE = 2
6189 12:26:57.186893 RX_GATING_TRACK_MODE = 2
6190 12:26:57.190069 SELPH_MODE = 1
6191 12:26:57.193556 PICG_EARLY_EN = 1
6192 12:26:57.196629 VALID_LAT_VALUE = 1
6193 12:26:57.203632 ==============================================================
6194 12:26:57.206774 Enter into Gating configuration >>>>
6195 12:26:57.210117 Exit from Gating configuration <<<<
6196 12:26:57.213444 Enter into DVFS_PRE_config >>>>>
6197 12:26:57.223391 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6198 12:26:57.226671 Exit from DVFS_PRE_config <<<<<
6199 12:26:57.230015 Enter into PICG configuration >>>>
6200 12:26:57.233344 Exit from PICG configuration <<<<
6201 12:26:57.236537 [RX_INPUT] configuration >>>>>
6202 12:26:57.239801 [RX_INPUT] configuration <<<<<
6203 12:26:57.243193 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6204 12:26:57.249838 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6205 12:26:57.256304 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6206 12:26:57.262820 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6207 12:26:57.266409 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6208 12:26:57.273014 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6209 12:26:57.276241 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6210 12:26:57.283062 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6211 12:26:57.285885 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6212 12:26:57.289420 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6213 12:26:57.292724 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6214 12:26:57.299227 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6215 12:26:57.302704 ===================================
6216 12:26:57.305902 LPDDR4 DRAM CONFIGURATION
6217 12:26:57.309482 ===================================
6218 12:26:57.309574 EX_ROW_EN[0] = 0x0
6219 12:26:57.312744 EX_ROW_EN[1] = 0x0
6220 12:26:57.312858 LP4Y_EN = 0x0
6221 12:26:57.316097 WORK_FSP = 0x0
6222 12:26:57.316175 WL = 0x2
6223 12:26:57.319337 RL = 0x2
6224 12:26:57.319438 BL = 0x2
6225 12:26:57.322680 RPST = 0x0
6226 12:26:57.322754 RD_PRE = 0x0
6227 12:26:57.326020 WR_PRE = 0x1
6228 12:26:57.326094 WR_PST = 0x0
6229 12:26:57.328856 DBI_WR = 0x0
6230 12:26:57.328946 DBI_RD = 0x0
6231 12:26:57.332128 OTF = 0x1
6232 12:26:57.335494 ===================================
6233 12:26:57.339195 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6234 12:26:57.342515 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6235 12:26:57.348577 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6236 12:26:57.351883 ===================================
6237 12:26:57.355254 LPDDR4 DRAM CONFIGURATION
6238 12:26:57.358538 ===================================
6239 12:26:57.358666 EX_ROW_EN[0] = 0x10
6240 12:26:57.361721 EX_ROW_EN[1] = 0x0
6241 12:26:57.361832 LP4Y_EN = 0x0
6242 12:26:57.365070 WORK_FSP = 0x0
6243 12:26:57.365179 WL = 0x2
6244 12:26:57.368485 RL = 0x2
6245 12:26:57.368590 BL = 0x2
6246 12:26:57.372081 RPST = 0x0
6247 12:26:57.372197 RD_PRE = 0x0
6248 12:26:57.375392 WR_PRE = 0x1
6249 12:26:57.375496 WR_PST = 0x0
6250 12:26:57.378705 DBI_WR = 0x0
6251 12:26:57.378782 DBI_RD = 0x0
6252 12:26:57.381978 OTF = 0x1
6253 12:26:57.385175 ===================================
6254 12:26:57.391866 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6255 12:26:57.395185 nWR fixed to 30
6256 12:26:57.398328 [ModeRegInit_LP4] CH0 RK0
6257 12:26:57.398443 [ModeRegInit_LP4] CH0 RK1
6258 12:26:57.401567 [ModeRegInit_LP4] CH1 RK0
6259 12:26:57.405094 [ModeRegInit_LP4] CH1 RK1
6260 12:26:57.405187 match AC timing 19
6261 12:26:57.411472 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6262 12:26:57.415023 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6263 12:26:57.418418 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6264 12:26:57.424600 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6265 12:26:57.427876 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6266 12:26:57.427993 ==
6267 12:26:57.431627 Dram Type= 6, Freq= 0, CH_0, rank 0
6268 12:26:57.434581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 12:26:57.434689 ==
6270 12:26:57.441025 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6271 12:26:57.447723 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6272 12:26:57.451002 [CA 0] Center 36 (8~64) winsize 57
6273 12:26:57.454268 [CA 1] Center 36 (8~64) winsize 57
6274 12:26:57.457576 [CA 2] Center 36 (8~64) winsize 57
6275 12:26:57.461409 [CA 3] Center 36 (8~64) winsize 57
6276 12:26:57.464458 [CA 4] Center 36 (8~64) winsize 57
6277 12:26:57.467769 [CA 5] Center 36 (8~64) winsize 57
6278 12:26:57.467857
6279 12:26:57.471251 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6280 12:26:57.471332
6281 12:26:57.474309 [CATrainingPosCal] consider 1 rank data
6282 12:26:57.477682 u2DelayCellTimex100 = 270/100 ps
6283 12:26:57.481086 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 12:26:57.484434 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 12:26:57.487724 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 12:26:57.490950 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 12:26:57.494156 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 12:26:57.497567 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 12:26:57.497656
6290 12:26:57.500626 CA PerBit enable=1, Macro0, CA PI delay=36
6291 12:26:57.500789
6292 12:26:57.504145 [CBTSetCACLKResult] CA Dly = 36
6293 12:26:57.507269 CS Dly: 1 (0~32)
6294 12:26:57.507356 ==
6295 12:26:57.510760 Dram Type= 6, Freq= 0, CH_0, rank 1
6296 12:26:57.513864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 12:26:57.513954 ==
6298 12:26:57.520553 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6299 12:26:57.527378 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6300 12:26:57.530627 [CA 0] Center 36 (8~64) winsize 57
6301 12:26:57.533922 [CA 1] Center 36 (8~64) winsize 57
6302 12:26:57.536974 [CA 2] Center 36 (8~64) winsize 57
6303 12:26:57.537072 [CA 3] Center 36 (8~64) winsize 57
6304 12:26:57.540211 [CA 4] Center 36 (8~64) winsize 57
6305 12:26:57.543487 [CA 5] Center 36 (8~64) winsize 57
6306 12:26:57.543577
6307 12:26:57.547304 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6308 12:26:57.550187
6309 12:26:57.553576 [CATrainingPosCal] consider 2 rank data
6310 12:26:57.556692 u2DelayCellTimex100 = 270/100 ps
6311 12:26:57.560087 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 12:26:57.563456 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 12:26:57.566726 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 12:26:57.569849 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 12:26:57.573196 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 12:26:57.576556 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 12:26:57.576649
6318 12:26:57.579776 CA PerBit enable=1, Macro0, CA PI delay=36
6319 12:26:57.579873
6320 12:26:57.583086 [CBTSetCACLKResult] CA Dly = 36
6321 12:26:57.586351 CS Dly: 1 (0~32)
6322 12:26:57.586507
6323 12:26:57.589761 ----->DramcWriteLeveling(PI) begin...
6324 12:26:57.589854 ==
6325 12:26:57.592983 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 12:26:57.596214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 12:26:57.596298 ==
6328 12:26:57.599827 Write leveling (Byte 0): 40 => 8
6329 12:26:57.602925 Write leveling (Byte 1): 32 => 0
6330 12:26:57.606113 DramcWriteLeveling(PI) end<-----
6331 12:26:57.606208
6332 12:26:57.606276 ==
6333 12:26:57.609660 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 12:26:57.613101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 12:26:57.613206 ==
6336 12:26:57.616384 [Gating] SW mode calibration
6337 12:26:57.622787 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6338 12:26:57.629621 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6339 12:26:57.632906 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6340 12:26:57.639125 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6341 12:26:57.642541 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6342 12:26:57.645799 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6343 12:26:57.652629 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 12:26:57.655967 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 12:26:57.659210 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 12:26:57.665880 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6347 12:26:57.669164 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6348 12:26:57.672403 Total UI for P1: 0, mck2ui 16
6349 12:26:57.675614 best dqsien dly found for B0: ( 0, 14, 24)
6350 12:26:57.678956 Total UI for P1: 0, mck2ui 16
6351 12:26:57.682200 best dqsien dly found for B1: ( 0, 14, 24)
6352 12:26:57.685410 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6353 12:26:57.688775 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6354 12:26:57.688886
6355 12:26:57.692173 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6356 12:26:57.695489 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6357 12:26:57.698720 [Gating] SW calibration Done
6358 12:26:57.698823 ==
6359 12:26:57.702054 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 12:26:57.705335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 12:26:57.708570 ==
6362 12:26:57.708653 RX Vref Scan: 0
6363 12:26:57.708715
6364 12:26:57.711658 RX Vref 0 -> 0, step: 1
6365 12:26:57.711736
6366 12:26:57.715182 RX Delay -410 -> 252, step: 16
6367 12:26:57.718245 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6368 12:26:57.721649 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6369 12:26:57.724703 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6370 12:26:57.731609 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6371 12:26:57.734823 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6372 12:26:57.738117 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6373 12:26:57.741567 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6374 12:26:57.747640 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6375 12:26:57.751073 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6376 12:26:57.754326 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6377 12:26:57.760931 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6378 12:26:57.764243 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6379 12:26:57.767527 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6380 12:26:57.770838 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6381 12:26:57.777367 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6382 12:26:57.780994 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6383 12:26:57.781117 ==
6384 12:26:57.784388 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 12:26:57.787637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 12:26:57.787730 ==
6387 12:26:57.790791 DQS Delay:
6388 12:26:57.790876 DQS0 = 27, DQS1 = 43
6389 12:26:57.794162 DQM Delay:
6390 12:26:57.794247 DQM0 = 12, DQM1 = 12
6391 12:26:57.794312 DQ Delay:
6392 12:26:57.797546 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6393 12:26:57.800713 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6394 12:26:57.803691 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6395 12:26:57.807108 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6396 12:26:57.807196
6397 12:26:57.807260
6398 12:26:57.807319 ==
6399 12:26:57.810446 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 12:26:57.817307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 12:26:57.817410 ==
6402 12:26:57.817476
6403 12:26:57.817544
6404 12:26:57.817605 TX Vref Scan disable
6405 12:26:57.820398 == TX Byte 0 ==
6406 12:26:57.823594 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6407 12:26:57.826836 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6408 12:26:57.830521 == TX Byte 1 ==
6409 12:26:57.833344 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6410 12:26:57.836730 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6411 12:26:57.840364 ==
6412 12:26:57.843323 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 12:26:57.846587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 12:26:57.846675 ==
6415 12:26:57.846745
6416 12:26:57.846805
6417 12:26:57.849913 TX Vref Scan disable
6418 12:26:57.850017 == TX Byte 0 ==
6419 12:26:57.853178 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6420 12:26:57.860020 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6421 12:26:57.860122 == TX Byte 1 ==
6422 12:26:57.863418 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6423 12:26:57.869843 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6424 12:26:57.869961
6425 12:26:57.870027 [DATLAT]
6426 12:26:57.870087 Freq=400, CH0 RK0
6427 12:26:57.873217
6428 12:26:57.873300 DATLAT Default: 0xf
6429 12:26:57.876499 0, 0xFFFF, sum = 0
6430 12:26:57.876585 1, 0xFFFF, sum = 0
6431 12:26:57.879634 2, 0xFFFF, sum = 0
6432 12:26:57.879720 3, 0xFFFF, sum = 0
6433 12:26:57.882845 4, 0xFFFF, sum = 0
6434 12:26:57.882932 5, 0xFFFF, sum = 0
6435 12:26:57.886204 6, 0xFFFF, sum = 0
6436 12:26:57.886293 7, 0xFFFF, sum = 0
6437 12:26:57.889514 8, 0xFFFF, sum = 0
6438 12:26:57.889602 9, 0xFFFF, sum = 0
6439 12:26:57.892679 10, 0xFFFF, sum = 0
6440 12:26:57.892789 11, 0xFFFF, sum = 0
6441 12:26:57.896022 12, 0xFFFF, sum = 0
6442 12:26:57.896142 13, 0x0, sum = 1
6443 12:26:57.899336 14, 0x0, sum = 2
6444 12:26:57.899424 15, 0x0, sum = 3
6445 12:26:57.902635 16, 0x0, sum = 4
6446 12:26:57.902722 best_step = 14
6447 12:26:57.902789
6448 12:26:57.902850 ==
6449 12:26:57.905948 Dram Type= 6, Freq= 0, CH_0, rank 0
6450 12:26:57.912670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 12:26:57.912816 ==
6452 12:26:57.912887 RX Vref Scan: 1
6453 12:26:57.912950
6454 12:26:57.915981 RX Vref 0 -> 0, step: 1
6455 12:26:57.916067
6456 12:26:57.919225 RX Delay -327 -> 252, step: 8
6457 12:26:57.919314
6458 12:26:57.922321 Set Vref, RX VrefLevel [Byte0]: 59
6459 12:26:57.925955 [Byte1]: 48
6460 12:26:57.926046
6461 12:26:57.929113 Final RX Vref Byte 0 = 59 to rank0
6462 12:26:57.932718 Final RX Vref Byte 1 = 48 to rank0
6463 12:26:57.935911 Final RX Vref Byte 0 = 59 to rank1
6464 12:26:57.939074 Final RX Vref Byte 1 = 48 to rank1==
6465 12:26:57.942713 Dram Type= 6, Freq= 0, CH_0, rank 0
6466 12:26:57.945745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 12:26:57.949044 ==
6468 12:26:57.949170 DQS Delay:
6469 12:26:57.952296 DQS0 = 24, DQS1 = 48
6470 12:26:57.952386 DQM Delay:
6471 12:26:57.952453 DQM0 = 9, DQM1 = 16
6472 12:26:57.955620 DQ Delay:
6473 12:26:57.955709 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6474 12:26:57.958937 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6475 12:26:57.962122 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6476 12:26:57.965316 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6477 12:26:57.965406
6478 12:26:57.965474
6479 12:26:57.975468 [DQSOSCAuto] RK0, (LSB)MR18= 0xaea6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6480 12:26:57.978809 CH0 RK0: MR19=C0C, MR18=AEA6
6481 12:26:57.985262 CH0_RK0: MR19=0xC0C, MR18=0xAEA6, DQSOSC=388, MR23=63, INC=392, DEC=261
6482 12:26:57.985366 ==
6483 12:26:57.988683 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 12:26:57.991960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 12:26:57.992052 ==
6486 12:26:57.995158 [Gating] SW mode calibration
6487 12:26:58.001862 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6488 12:26:58.008395 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6489 12:26:58.011672 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6490 12:26:58.014502 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6491 12:26:58.021113 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6492 12:26:58.024452 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6493 12:26:58.027932 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 12:26:58.034202 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 12:26:58.037571 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 12:26:58.041101 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6497 12:26:58.047455 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6498 12:26:58.047550 Total UI for P1: 0, mck2ui 16
6499 12:26:58.054334 best dqsien dly found for B0: ( 0, 14, 24)
6500 12:26:58.054423 Total UI for P1: 0, mck2ui 16
6501 12:26:58.061029 best dqsien dly found for B1: ( 0, 14, 24)
6502 12:26:58.064175 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6503 12:26:58.067287 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6504 12:26:58.067375
6505 12:26:58.070601 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6506 12:26:58.074000 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6507 12:26:58.077306 [Gating] SW calibration Done
6508 12:26:58.077384 ==
6509 12:26:58.080528 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 12:26:58.083901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 12:26:58.083983 ==
6512 12:26:58.087157 RX Vref Scan: 0
6513 12:26:58.087235
6514 12:26:58.087297 RX Vref 0 -> 0, step: 1
6515 12:26:58.087357
6516 12:26:58.090802 RX Delay -410 -> 252, step: 16
6517 12:26:58.097501 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6518 12:26:58.100338 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6519 12:26:58.103681 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6520 12:26:58.106956 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6521 12:26:58.113550 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6522 12:26:58.116889 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6523 12:26:58.120075 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6524 12:26:58.123850 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6525 12:26:58.130102 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6526 12:26:58.133654 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6527 12:26:58.136645 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6528 12:26:58.143344 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6529 12:26:58.146520 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6530 12:26:58.149705 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6531 12:26:58.153197 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6532 12:26:58.159878 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6533 12:26:58.159964 ==
6534 12:26:58.163251 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 12:26:58.166114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 12:26:58.166193 ==
6537 12:26:58.166259 DQS Delay:
6538 12:26:58.169554 DQS0 = 19, DQS1 = 43
6539 12:26:58.169639 DQM Delay:
6540 12:26:58.173121 DQM0 = 2, DQM1 = 18
6541 12:26:58.173206 DQ Delay:
6542 12:26:58.176318 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6543 12:26:58.179798 DQ4 =0, DQ5 =0, DQ6 =8, DQ7 =8
6544 12:26:58.182665 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =24
6545 12:26:58.186399 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6546 12:26:58.186492
6547 12:26:58.186559
6548 12:26:58.186629 ==
6549 12:26:58.189628 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 12:26:58.192878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 12:26:58.192963 ==
6552 12:26:58.193030
6553 12:26:58.193093
6554 12:26:58.196087 TX Vref Scan disable
6555 12:26:58.199441 == TX Byte 0 ==
6556 12:26:58.202662 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6557 12:26:58.206039 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6558 12:26:58.206154 == TX Byte 1 ==
6559 12:26:58.212443 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6560 12:26:58.215710 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6561 12:26:58.215811 ==
6562 12:26:58.219035 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 12:26:58.222462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 12:26:58.222565 ==
6565 12:26:58.222656
6566 12:26:58.225869
6567 12:26:58.225966 TX Vref Scan disable
6568 12:26:58.229276 == TX Byte 0 ==
6569 12:26:58.232610 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6570 12:26:58.235802 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6571 12:26:58.239022 == TX Byte 1 ==
6572 12:26:58.242085 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6573 12:26:58.245630 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6574 12:26:58.245715
6575 12:26:58.245781 [DATLAT]
6576 12:26:58.248639 Freq=400, CH0 RK1
6577 12:26:58.248723
6578 12:26:58.248844 DATLAT Default: 0xe
6579 12:26:58.252307 0, 0xFFFF, sum = 0
6580 12:26:58.255403 1, 0xFFFF, sum = 0
6581 12:26:58.255488 2, 0xFFFF, sum = 0
6582 12:26:58.258419 3, 0xFFFF, sum = 0
6583 12:26:58.258569 4, 0xFFFF, sum = 0
6584 12:26:58.261951 5, 0xFFFF, sum = 0
6585 12:26:58.262056 6, 0xFFFF, sum = 0
6586 12:26:58.265030 7, 0xFFFF, sum = 0
6587 12:26:58.265116 8, 0xFFFF, sum = 0
6588 12:26:58.268415 9, 0xFFFF, sum = 0
6589 12:26:58.268517 10, 0xFFFF, sum = 0
6590 12:26:58.271765 11, 0xFFFF, sum = 0
6591 12:26:58.271852 12, 0xFFFF, sum = 0
6592 12:26:58.275251 13, 0x0, sum = 1
6593 12:26:58.275363 14, 0x0, sum = 2
6594 12:26:58.278464 15, 0x0, sum = 3
6595 12:26:58.278550 16, 0x0, sum = 4
6596 12:26:58.281812 best_step = 14
6597 12:26:58.281922
6598 12:26:58.282015 ==
6599 12:26:58.285133 Dram Type= 6, Freq= 0, CH_0, rank 1
6600 12:26:58.288425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 12:26:58.288566 ==
6602 12:26:58.291759 RX Vref Scan: 0
6603 12:26:58.291870
6604 12:26:58.291939 RX Vref 0 -> 0, step: 1
6605 12:26:58.292002
6606 12:26:58.295097 RX Delay -327 -> 252, step: 8
6607 12:26:58.302923 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6608 12:26:58.305780 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6609 12:26:58.309426 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6610 12:26:58.315834 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6611 12:26:58.319106 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6612 12:26:58.322433 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6613 12:26:58.325808 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6614 12:26:58.329171 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6615 12:26:58.335860 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6616 12:26:58.339150 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6617 12:26:58.342422 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6618 12:26:58.348733 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6619 12:26:58.351944 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6620 12:26:58.355504 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6621 12:26:58.359056 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6622 12:26:58.365466 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6623 12:26:58.365552 ==
6624 12:26:58.368650 Dram Type= 6, Freq= 0, CH_0, rank 1
6625 12:26:58.372201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6626 12:26:58.372297 ==
6627 12:26:58.372403 DQS Delay:
6628 12:26:58.375484 DQS0 = 28, DQS1 = 40
6629 12:26:58.375595 DQM Delay:
6630 12:26:58.378747 DQM0 = 10, DQM1 = 12
6631 12:26:58.378831 DQ Delay:
6632 12:26:58.381961 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6633 12:26:58.385273 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6634 12:26:58.388715 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =4
6635 12:26:58.391616 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6636 12:26:58.391700
6637 12:26:58.391765
6638 12:26:58.398212 [DQSOSCAuto] RK1, (LSB)MR18= 0xb46a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6639 12:26:58.401750 CH0 RK1: MR19=C0C, MR18=B46A
6640 12:26:58.408268 CH0_RK1: MR19=0xC0C, MR18=0xB46A, DQSOSC=387, MR23=63, INC=394, DEC=262
6641 12:26:58.411500 [RxdqsGatingPostProcess] freq 400
6642 12:26:58.417975 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6643 12:26:58.421397 best DQS0 dly(2T, 0.5T) = (0, 10)
6644 12:26:58.424680 best DQS1 dly(2T, 0.5T) = (0, 10)
6645 12:26:58.428112 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6646 12:26:58.431015 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6647 12:26:58.434418 best DQS0 dly(2T, 0.5T) = (0, 10)
6648 12:26:58.434501 best DQS1 dly(2T, 0.5T) = (0, 10)
6649 12:26:58.438200 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6650 12:26:58.440986 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6651 12:26:58.444229 Pre-setting of DQS Precalculation
6652 12:26:58.450733 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6653 12:26:58.450836 ==
6654 12:26:58.454368 Dram Type= 6, Freq= 0, CH_1, rank 0
6655 12:26:58.457509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 12:26:58.457651 ==
6657 12:26:58.464376 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6658 12:26:58.470938 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6659 12:26:58.473962 [CA 0] Center 36 (8~64) winsize 57
6660 12:26:58.477168 [CA 1] Center 36 (8~64) winsize 57
6661 12:26:58.480533 [CA 2] Center 36 (8~64) winsize 57
6662 12:26:58.483696 [CA 3] Center 36 (8~64) winsize 57
6663 12:26:58.483781 [CA 4] Center 36 (8~64) winsize 57
6664 12:26:58.487041 [CA 5] Center 36 (8~64) winsize 57
6665 12:26:58.487125
6666 12:26:58.493770 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6667 12:26:58.493856
6668 12:26:58.497119 [CATrainingPosCal] consider 1 rank data
6669 12:26:58.500476 u2DelayCellTimex100 = 270/100 ps
6670 12:26:58.503665 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 12:26:58.506775 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 12:26:58.510061 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 12:26:58.513389 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 12:26:58.516584 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 12:26:58.520093 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 12:26:58.520197
6677 12:26:58.523460 CA PerBit enable=1, Macro0, CA PI delay=36
6678 12:26:58.523565
6679 12:26:58.526751 [CBTSetCACLKResult] CA Dly = 36
6680 12:26:58.529999 CS Dly: 1 (0~32)
6681 12:26:58.530113 ==
6682 12:26:58.533337 Dram Type= 6, Freq= 0, CH_1, rank 1
6683 12:26:58.536625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 12:26:58.536739 ==
6685 12:26:58.543121 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6686 12:26:58.549865 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6687 12:26:58.553237 [CA 0] Center 36 (8~64) winsize 57
6688 12:26:58.553373 [CA 1] Center 36 (8~64) winsize 57
6689 12:26:58.556589 [CA 2] Center 36 (8~64) winsize 57
6690 12:26:58.559653 [CA 3] Center 36 (8~64) winsize 57
6691 12:26:58.563337 [CA 4] Center 36 (8~64) winsize 57
6692 12:26:58.566425 [CA 5] Center 36 (8~64) winsize 57
6693 12:26:58.566536
6694 12:26:58.569807 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6695 12:26:58.569919
6696 12:26:58.576561 [CATrainingPosCal] consider 2 rank data
6697 12:26:58.576688 u2DelayCellTimex100 = 270/100 ps
6698 12:26:58.582894 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 12:26:58.586017 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 12:26:58.589669 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 12:26:58.593064 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 12:26:58.596381 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 12:26:58.599706 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 12:26:58.599815
6705 12:26:58.602998 CA PerBit enable=1, Macro0, CA PI delay=36
6706 12:26:58.603108
6707 12:26:58.605921 [CBTSetCACLKResult] CA Dly = 36
6708 12:26:58.609589 CS Dly: 1 (0~32)
6709 12:26:58.609706
6710 12:26:58.612687 ----->DramcWriteLeveling(PI) begin...
6711 12:26:58.612805 ==
6712 12:26:58.615890 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 12:26:58.619238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 12:26:58.619340 ==
6715 12:26:58.622488 Write leveling (Byte 0): 40 => 8
6716 12:26:58.625750 Write leveling (Byte 1): 32 => 0
6717 12:26:58.629206 DramcWriteLeveling(PI) end<-----
6718 12:26:58.629314
6719 12:26:58.629409 ==
6720 12:26:58.632561 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 12:26:58.635932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 12:26:58.636017 ==
6723 12:26:58.639272 [Gating] SW mode calibration
6724 12:26:58.645806 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6725 12:26:58.652366 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6726 12:26:58.655639 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6727 12:26:58.659005 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6728 12:26:58.665475 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6729 12:26:58.668644 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6730 12:26:58.672229 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 12:26:58.678895 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 12:26:58.681736 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 12:26:58.685266 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6734 12:26:58.691817 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6735 12:26:58.695147 Total UI for P1: 0, mck2ui 16
6736 12:26:58.698440 best dqsien dly found for B0: ( 0, 14, 24)
6737 12:26:58.701787 Total UI for P1: 0, mck2ui 16
6738 12:26:58.705145 best dqsien dly found for B1: ( 0, 14, 24)
6739 12:26:58.708539 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6740 12:26:58.711807 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6741 12:26:58.711922
6742 12:26:58.714968 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6743 12:26:58.718542 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6744 12:26:58.721788 [Gating] SW calibration Done
6745 12:26:58.721873 ==
6746 12:26:58.725053 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 12:26:58.728218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 12:26:58.728305 ==
6749 12:26:58.731416 RX Vref Scan: 0
6750 12:26:58.731500
6751 12:26:58.734764 RX Vref 0 -> 0, step: 1
6752 12:26:58.734850
6753 12:26:58.734917 RX Delay -410 -> 252, step: 16
6754 12:26:58.741844 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6755 12:26:58.744637 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6756 12:26:58.748036 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6757 12:26:58.751353 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6758 12:26:58.757998 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6759 12:26:58.761368 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6760 12:26:58.764691 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6761 12:26:58.768099 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6762 12:26:58.774372 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6763 12:26:58.777980 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6764 12:26:58.781011 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6765 12:26:58.787841 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6766 12:26:58.791384 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6767 12:26:58.794567 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6768 12:26:58.798048 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6769 12:26:58.804624 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6770 12:26:58.804711 ==
6771 12:26:58.807891 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 12:26:58.811267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 12:26:58.811352 ==
6774 12:26:58.811417 DQS Delay:
6775 12:26:58.814619 DQS0 = 27, DQS1 = 43
6776 12:26:58.814702 DQM Delay:
6777 12:26:58.817826 DQM0 = 6, DQM1 = 18
6778 12:26:58.817909 DQ Delay:
6779 12:26:58.821449 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6780 12:26:58.824305 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6781 12:26:58.827631 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6782 12:26:58.830894 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6783 12:26:58.830984
6784 12:26:58.831050
6785 12:26:58.831110 ==
6786 12:26:58.834554 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 12:26:58.837461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 12:26:58.837545 ==
6789 12:26:58.837610
6790 12:26:58.837669
6791 12:26:58.840702 TX Vref Scan disable
6792 12:26:58.840810 == TX Byte 0 ==
6793 12:26:58.847340 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6794 12:26:58.850573 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6795 12:26:58.850715 == TX Byte 1 ==
6796 12:26:58.857608 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6797 12:26:58.860525 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6798 12:26:58.860608 ==
6799 12:26:58.863899 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 12:26:58.867636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 12:26:58.867723 ==
6802 12:26:58.867792
6803 12:26:58.870967
6804 12:26:58.871050 TX Vref Scan disable
6805 12:26:58.873876 == TX Byte 0 ==
6806 12:26:58.877043 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6807 12:26:58.880559 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6808 12:26:58.884056 == TX Byte 1 ==
6809 12:26:58.887134 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6810 12:26:58.890817 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6811 12:26:58.890903
6812 12:26:58.890970 [DATLAT]
6813 12:26:58.893844 Freq=400, CH1 RK0
6814 12:26:58.893928
6815 12:26:58.897239 DATLAT Default: 0xf
6816 12:26:58.897329 0, 0xFFFF, sum = 0
6817 12:26:58.900480 1, 0xFFFF, sum = 0
6818 12:26:58.900569 2, 0xFFFF, sum = 0
6819 12:26:58.903625 3, 0xFFFF, sum = 0
6820 12:26:58.903713 4, 0xFFFF, sum = 0
6821 12:26:58.907340 5, 0xFFFF, sum = 0
6822 12:26:58.907426 6, 0xFFFF, sum = 0
6823 12:26:58.910726 7, 0xFFFF, sum = 0
6824 12:26:58.910812 8, 0xFFFF, sum = 0
6825 12:26:58.913602 9, 0xFFFF, sum = 0
6826 12:26:58.913688 10, 0xFFFF, sum = 0
6827 12:26:58.916898 11, 0xFFFF, sum = 0
6828 12:26:58.916986 12, 0xFFFF, sum = 0
6829 12:26:58.920120 13, 0x0, sum = 1
6830 12:26:58.920208 14, 0x0, sum = 2
6831 12:26:58.923359 15, 0x0, sum = 3
6832 12:26:58.923435 16, 0x0, sum = 4
6833 12:26:58.926657 best_step = 14
6834 12:26:58.926741
6835 12:26:58.926807 ==
6836 12:26:58.930345 Dram Type= 6, Freq= 0, CH_1, rank 0
6837 12:26:58.933127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 12:26:58.933239 ==
6839 12:26:58.936768 RX Vref Scan: 1
6840 12:26:58.936900
6841 12:26:58.936968 RX Vref 0 -> 0, step: 1
6842 12:26:58.937031
6843 12:26:58.940093 RX Delay -327 -> 252, step: 8
6844 12:26:58.940161
6845 12:26:58.943467 Set Vref, RX VrefLevel [Byte0]: 53
6846 12:26:58.946753 [Byte1]: 51
6847 12:26:58.951308
6848 12:26:58.951411 Final RX Vref Byte 0 = 53 to rank0
6849 12:26:58.954548 Final RX Vref Byte 1 = 51 to rank0
6850 12:26:58.957832 Final RX Vref Byte 0 = 53 to rank1
6851 12:26:58.961157 Final RX Vref Byte 1 = 51 to rank1==
6852 12:26:58.964461 Dram Type= 6, Freq= 0, CH_1, rank 0
6853 12:26:58.971157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 12:26:58.971242 ==
6855 12:26:58.971311 DQS Delay:
6856 12:26:58.974566 DQS0 = 28, DQS1 = 40
6857 12:26:58.974642 DQM Delay:
6858 12:26:58.974706 DQM0 = 8, DQM1 = 13
6859 12:26:58.977768 DQ Delay:
6860 12:26:58.981112 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6861 12:26:58.981217 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =4
6862 12:26:58.984366 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6863 12:26:58.987546 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6864 12:26:58.990824
6865 12:26:58.990900
6866 12:26:58.997491 [DQSOSCAuto] RK0, (LSB)MR18= 0x8ec8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6867 12:26:59.000571 CH1 RK0: MR19=C0C, MR18=8EC8
6868 12:26:59.007179 CH1_RK0: MR19=0xC0C, MR18=0x8EC8, DQSOSC=385, MR23=63, INC=398, DEC=265
6869 12:26:59.007307 ==
6870 12:26:59.010420 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 12:26:59.014028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 12:26:59.014124 ==
6873 12:26:59.017437 [Gating] SW mode calibration
6874 12:26:59.023554 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6875 12:26:59.030344 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6876 12:26:59.033745 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6877 12:26:59.037189 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6878 12:26:59.043550 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6879 12:26:59.046389 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6880 12:26:59.049773 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 12:26:59.056716 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 12:26:59.060164 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 12:26:59.063109 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6884 12:26:59.069693 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6885 12:26:59.069781 Total UI for P1: 0, mck2ui 16
6886 12:26:59.076391 best dqsien dly found for B0: ( 0, 14, 24)
6887 12:26:59.076481 Total UI for P1: 0, mck2ui 16
6888 12:26:59.082921 best dqsien dly found for B1: ( 0, 14, 24)
6889 12:26:59.086171 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6890 12:26:59.089614 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6891 12:26:59.089700
6892 12:26:59.092724 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6893 12:26:59.096388 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6894 12:26:59.099417 [Gating] SW calibration Done
6895 12:26:59.099497 ==
6896 12:26:59.102923 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 12:26:59.106233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 12:26:59.106320 ==
6899 12:26:59.109435 RX Vref Scan: 0
6900 12:26:59.109522
6901 12:26:59.112642 RX Vref 0 -> 0, step: 1
6902 12:26:59.112728
6903 12:26:59.112854 RX Delay -410 -> 252, step: 16
6904 12:26:59.119280 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6905 12:26:59.122578 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6906 12:26:59.125763 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6907 12:26:59.132651 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6908 12:26:59.135681 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6909 12:26:59.138903 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6910 12:26:59.142344 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6911 12:26:59.149195 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6912 12:26:59.152038 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6913 12:26:59.155283 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6914 12:26:59.158716 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6915 12:26:59.165309 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6916 12:26:59.168544 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6917 12:26:59.172004 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6918 12:26:59.175171 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6919 12:26:59.182259 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6920 12:26:59.182349 ==
6921 12:26:59.185373 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 12:26:59.188694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 12:26:59.188815 ==
6924 12:26:59.188882 DQS Delay:
6925 12:26:59.192108 DQS0 = 35, DQS1 = 35
6926 12:26:59.192191 DQM Delay:
6927 12:26:59.195489 DQM0 = 16, DQM1 = 12
6928 12:26:59.195574 DQ Delay:
6929 12:26:59.198568 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6930 12:26:59.201664 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6931 12:26:59.205084 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6932 12:26:59.208199 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =24
6933 12:26:59.208285
6934 12:26:59.208350
6935 12:26:59.208411 ==
6936 12:26:59.211779 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 12:26:59.215060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 12:26:59.218354 ==
6939 12:26:59.218465
6940 12:26:59.218559
6941 12:26:59.218649 TX Vref Scan disable
6942 12:26:59.221721 == TX Byte 0 ==
6943 12:26:59.224699 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6944 12:26:59.227997 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6945 12:26:59.231264 == TX Byte 1 ==
6946 12:26:59.234613 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6947 12:26:59.237887 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6948 12:26:59.237972 ==
6949 12:26:59.241538 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 12:26:59.247710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 12:26:59.247798 ==
6952 12:26:59.247865
6953 12:26:59.247926
6954 12:26:59.247984 TX Vref Scan disable
6955 12:26:59.251366 == TX Byte 0 ==
6956 12:26:59.254682 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6957 12:26:59.257956 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6958 12:26:59.260937 == TX Byte 1 ==
6959 12:26:59.264286 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6960 12:26:59.267658 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6961 12:26:59.267743
6962 12:26:59.270953 [DATLAT]
6963 12:26:59.271041 Freq=400, CH1 RK1
6964 12:26:59.271109
6965 12:26:59.274232 DATLAT Default: 0xe
6966 12:26:59.274317 0, 0xFFFF, sum = 0
6967 12:26:59.277920 1, 0xFFFF, sum = 0
6968 12:26:59.278006 2, 0xFFFF, sum = 0
6969 12:26:59.281109 3, 0xFFFF, sum = 0
6970 12:26:59.281195 4, 0xFFFF, sum = 0
6971 12:26:59.284502 5, 0xFFFF, sum = 0
6972 12:26:59.284645 6, 0xFFFF, sum = 0
6973 12:26:59.287904 7, 0xFFFF, sum = 0
6974 12:26:59.287992 8, 0xFFFF, sum = 0
6975 12:26:59.290704 9, 0xFFFF, sum = 0
6976 12:26:59.290791 10, 0xFFFF, sum = 0
6977 12:26:59.294095 11, 0xFFFF, sum = 0
6978 12:26:59.297421 12, 0xFFFF, sum = 0
6979 12:26:59.297524 13, 0x0, sum = 1
6980 12:26:59.297623 14, 0x0, sum = 2
6981 12:26:59.300733 15, 0x0, sum = 3
6982 12:26:59.300851 16, 0x0, sum = 4
6983 12:26:59.304109 best_step = 14
6984 12:26:59.304192
6985 12:26:59.304258 ==
6986 12:26:59.307191 Dram Type= 6, Freq= 0, CH_1, rank 1
6987 12:26:59.310728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6988 12:26:59.310815 ==
6989 12:26:59.313748 RX Vref Scan: 0
6990 12:26:59.313860
6991 12:26:59.313956 RX Vref 0 -> 0, step: 1
6992 12:26:59.317003
6993 12:26:59.317088 RX Delay -311 -> 252, step: 8
6994 12:26:59.325772 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6995 12:26:59.328627 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6996 12:26:59.332311 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6997 12:26:59.338548 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6998 12:26:59.342181 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6999 12:26:59.345383 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
7000 12:26:59.348742 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
7001 12:26:59.352043 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7002 12:26:59.358609 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7003 12:26:59.362035 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7004 12:26:59.365329 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7005 12:26:59.372015 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7006 12:26:59.374903 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7007 12:26:59.378283 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7008 12:26:59.381637 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7009 12:26:59.388263 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7010 12:26:59.388378 ==
7011 12:26:59.391542 Dram Type= 6, Freq= 0, CH_1, rank 1
7012 12:26:59.394879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7013 12:26:59.394981 ==
7014 12:26:59.395076 DQS Delay:
7015 12:26:59.398280 DQS0 = 32, DQS1 = 36
7016 12:26:59.398396 DQM Delay:
7017 12:26:59.401678 DQM0 = 14, DQM1 = 12
7018 12:26:59.401782 DQ Delay:
7019 12:26:59.404577 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =16
7020 12:26:59.408001 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
7021 12:26:59.411233 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7022 12:26:59.414750 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =24
7023 12:26:59.414866
7024 12:26:59.414963
7025 12:26:59.424516 [DQSOSCAuto] RK1, (LSB)MR18= 0xac55, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7026 12:26:59.424618 CH1 RK1: MR19=C0C, MR18=AC55
7027 12:26:59.431296 CH1_RK1: MR19=0xC0C, MR18=0xAC55, DQSOSC=388, MR23=63, INC=392, DEC=261
7028 12:26:59.434216 [RxdqsGatingPostProcess] freq 400
7029 12:26:59.441145 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7030 12:26:59.444387 best DQS0 dly(2T, 0.5T) = (0, 10)
7031 12:26:59.447563 best DQS1 dly(2T, 0.5T) = (0, 10)
7032 12:26:59.450770 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7033 12:26:59.454058 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7034 12:26:59.457240 best DQS0 dly(2T, 0.5T) = (0, 10)
7035 12:26:59.457331 best DQS1 dly(2T, 0.5T) = (0, 10)
7036 12:26:59.460926 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7037 12:26:59.464237 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7038 12:26:59.467233 Pre-setting of DQS Precalculation
7039 12:26:59.473988 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7040 12:26:59.480601 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7041 12:26:59.487247 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7042 12:26:59.487366
7043 12:26:59.487461
7044 12:26:59.490708 [Calibration Summary] 800 Mbps
7045 12:26:59.494051 CH 0, Rank 0
7046 12:26:59.494136 SW Impedance : PASS
7047 12:26:59.497354 DUTY Scan : NO K
7048 12:26:59.497440 ZQ Calibration : PASS
7049 12:26:59.500679 Jitter Meter : NO K
7050 12:26:59.504022 CBT Training : PASS
7051 12:26:59.504108 Write leveling : PASS
7052 12:26:59.507241 RX DQS gating : PASS
7053 12:26:59.510653 RX DQ/DQS(RDDQC) : PASS
7054 12:26:59.510733 TX DQ/DQS : PASS
7055 12:26:59.513863 RX DATLAT : PASS
7056 12:26:59.517124 RX DQ/DQS(Engine): PASS
7057 12:26:59.517198 TX OE : NO K
7058 12:26:59.520623 All Pass.
7059 12:26:59.520727
7060 12:26:59.520847 CH 0, Rank 1
7061 12:26:59.523507 SW Impedance : PASS
7062 12:26:59.523615 DUTY Scan : NO K
7063 12:26:59.527307 ZQ Calibration : PASS
7064 12:26:59.530366 Jitter Meter : NO K
7065 12:26:59.530469 CBT Training : PASS
7066 12:26:59.533442 Write leveling : NO K
7067 12:26:59.537036 RX DQS gating : PASS
7068 12:26:59.537163 RX DQ/DQS(RDDQC) : PASS
7069 12:26:59.540106 TX DQ/DQS : PASS
7070 12:26:59.543864 RX DATLAT : PASS
7071 12:26:59.543947 RX DQ/DQS(Engine): PASS
7072 12:26:59.546726 TX OE : NO K
7073 12:26:59.546812 All Pass.
7074 12:26:59.546879
7075 12:26:59.550055 CH 1, Rank 0
7076 12:26:59.550141 SW Impedance : PASS
7077 12:26:59.553247 DUTY Scan : NO K
7078 12:26:59.553366 ZQ Calibration : PASS
7079 12:26:59.556554 Jitter Meter : NO K
7080 12:26:59.560319 CBT Training : PASS
7081 12:26:59.560422 Write leveling : PASS
7082 12:26:59.563430 RX DQS gating : PASS
7083 12:26:59.566776 RX DQ/DQS(RDDQC) : PASS
7084 12:26:59.566866 TX DQ/DQS : PASS
7085 12:26:59.570069 RX DATLAT : PASS
7086 12:26:59.573330 RX DQ/DQS(Engine): PASS
7087 12:26:59.573414 TX OE : NO K
7088 12:26:59.576695 All Pass.
7089 12:26:59.576787
7090 12:26:59.576867 CH 1, Rank 1
7091 12:26:59.579961 SW Impedance : PASS
7092 12:26:59.580044 DUTY Scan : NO K
7093 12:26:59.583173 ZQ Calibration : PASS
7094 12:26:59.586498 Jitter Meter : NO K
7095 12:26:59.586581 CBT Training : PASS
7096 12:26:59.589806 Write leveling : NO K
7097 12:26:59.593168 RX DQS gating : PASS
7098 12:26:59.593252 RX DQ/DQS(RDDQC) : PASS
7099 12:26:59.596458 TX DQ/DQS : PASS
7100 12:26:59.599763 RX DATLAT : PASS
7101 12:26:59.599846 RX DQ/DQS(Engine): PASS
7102 12:26:59.602953 TX OE : NO K
7103 12:26:59.603036 All Pass.
7104 12:26:59.603102
7105 12:26:59.606241 DramC Write-DBI off
7106 12:26:59.609556 PER_BANK_REFRESH: Hybrid Mode
7107 12:26:59.609666 TX_TRACKING: ON
7108 12:26:59.619627 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7109 12:26:59.622692 [FAST_K] Save calibration result to emmc
7110 12:26:59.625967 dramc_set_vcore_voltage set vcore to 725000
7111 12:26:59.629511 Read voltage for 1600, 0
7112 12:26:59.629599 Vio18 = 0
7113 12:26:59.629665 Vcore = 725000
7114 12:26:59.632658 Vdram = 0
7115 12:26:59.632742 Vddq = 0
7116 12:26:59.632845 Vmddr = 0
7117 12:26:59.639430 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7118 12:26:59.642615 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7119 12:26:59.645923 MEM_TYPE=3, freq_sel=13
7120 12:26:59.649295 sv_algorithm_assistance_LP4_3733
7121 12:26:59.652385 ============ PULL DRAM RESETB DOWN ============
7122 12:26:59.656002 ========== PULL DRAM RESETB DOWN end =========
7123 12:26:59.662675 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7124 12:26:59.665894 ===================================
7125 12:26:59.669147 LPDDR4 DRAM CONFIGURATION
7126 12:26:59.672445 ===================================
7127 12:26:59.672530 EX_ROW_EN[0] = 0x0
7128 12:26:59.675733 EX_ROW_EN[1] = 0x0
7129 12:26:59.675818 LP4Y_EN = 0x0
7130 12:26:59.678709 WORK_FSP = 0x1
7131 12:26:59.678793 WL = 0x5
7132 12:26:59.682072 RL = 0x5
7133 12:26:59.682156 BL = 0x2
7134 12:26:59.685423 RPST = 0x0
7135 12:26:59.685507 RD_PRE = 0x0
7136 12:26:59.688813 WR_PRE = 0x1
7137 12:26:59.688897 WR_PST = 0x1
7138 12:26:59.692000 DBI_WR = 0x0
7139 12:26:59.695339 DBI_RD = 0x0
7140 12:26:59.695442 OTF = 0x1
7141 12:26:59.698707 ===================================
7142 12:26:59.702007 ===================================
7143 12:26:59.702092 ANA top config
7144 12:26:59.705299 ===================================
7145 12:26:59.708654 DLL_ASYNC_EN = 0
7146 12:26:59.712015 ALL_SLAVE_EN = 0
7147 12:26:59.715300 NEW_RANK_MODE = 1
7148 12:26:59.718763 DLL_IDLE_MODE = 1
7149 12:26:59.718848 LP45_APHY_COMB_EN = 1
7150 12:26:59.722024 TX_ODT_DIS = 0
7151 12:26:59.725286 NEW_8X_MODE = 1
7152 12:26:59.728662 ===================================
7153 12:26:59.731693 ===================================
7154 12:26:59.735165 data_rate = 3200
7155 12:26:59.738400 CKR = 1
7156 12:26:59.738490 DQ_P2S_RATIO = 8
7157 12:26:59.741440 ===================================
7158 12:26:59.745018 CA_P2S_RATIO = 8
7159 12:26:59.748266 DQ_CA_OPEN = 0
7160 12:26:59.751458 DQ_SEMI_OPEN = 0
7161 12:26:59.754644 CA_SEMI_OPEN = 0
7162 12:26:59.758235 CA_FULL_RATE = 0
7163 12:26:59.758320 DQ_CKDIV4_EN = 0
7164 12:26:59.761259 CA_CKDIV4_EN = 0
7165 12:26:59.764529 CA_PREDIV_EN = 0
7166 12:26:59.768364 PH8_DLY = 12
7167 12:26:59.771507 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7168 12:26:59.774610 DQ_AAMCK_DIV = 4
7169 12:26:59.777795 CA_AAMCK_DIV = 4
7170 12:26:59.777929 CA_ADMCK_DIV = 4
7171 12:26:59.781062 DQ_TRACK_CA_EN = 0
7172 12:26:59.784464 CA_PICK = 1600
7173 12:26:59.787768 CA_MCKIO = 1600
7174 12:26:59.790937 MCKIO_SEMI = 0
7175 12:26:59.794380 PLL_FREQ = 3068
7176 12:26:59.797670 DQ_UI_PI_RATIO = 32
7177 12:26:59.797822 CA_UI_PI_RATIO = 0
7178 12:26:59.801039 ===================================
7179 12:26:59.804351 ===================================
7180 12:26:59.807612 memory_type:LPDDR4
7181 12:26:59.811054 GP_NUM : 10
7182 12:26:59.811212 SRAM_EN : 1
7183 12:26:59.814321 MD32_EN : 0
7184 12:26:59.817210 ===================================
7185 12:26:59.820529 [ANA_INIT] >>>>>>>>>>>>>>
7186 12:26:59.823797 <<<<<< [CONFIGURE PHASE]: ANA_TX
7187 12:26:59.827080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7188 12:26:59.830390 ===================================
7189 12:26:59.833690 data_rate = 3200,PCW = 0X7600
7190 12:26:59.837366 ===================================
7191 12:26:59.840788 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7192 12:26:59.843806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7193 12:26:59.850515 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7194 12:26:59.854146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7195 12:26:59.856993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7196 12:26:59.860346 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7197 12:26:59.863766 [ANA_INIT] flow start
7198 12:26:59.867096 [ANA_INIT] PLL >>>>>>>>
7199 12:26:59.867207 [ANA_INIT] PLL <<<<<<<<
7200 12:26:59.870265 [ANA_INIT] MIDPI >>>>>>>>
7201 12:26:59.873481 [ANA_INIT] MIDPI <<<<<<<<
7202 12:26:59.873592 [ANA_INIT] DLL >>>>>>>>
7203 12:26:59.876649 [ANA_INIT] DLL <<<<<<<<
7204 12:26:59.880203 [ANA_INIT] flow end
7205 12:26:59.883558 ============ LP4 DIFF to SE enter ============
7206 12:26:59.886873 ============ LP4 DIFF to SE exit ============
7207 12:26:59.890161 [ANA_INIT] <<<<<<<<<<<<<
7208 12:26:59.893471 [Flow] Enable top DCM control >>>>>
7209 12:26:59.896793 [Flow] Enable top DCM control <<<<<
7210 12:26:59.900163 Enable DLL master slave shuffle
7211 12:26:59.903355 ==============================================================
7212 12:26:59.906664 Gating Mode config
7213 12:26:59.913289 ==============================================================
7214 12:26:59.913405 Config description:
7215 12:26:59.923208 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7216 12:26:59.929996 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7217 12:26:59.936543 SELPH_MODE 0: By rank 1: By Phase
7218 12:26:59.939502 ==============================================================
7219 12:26:59.942700 GAT_TRACK_EN = 1
7220 12:26:59.945996 RX_GATING_MODE = 2
7221 12:26:59.949434 RX_GATING_TRACK_MODE = 2
7222 12:26:59.952936 SELPH_MODE = 1
7223 12:26:59.956064 PICG_EARLY_EN = 1
7224 12:26:59.959733 VALID_LAT_VALUE = 1
7225 12:26:59.962713 ==============================================================
7226 12:26:59.966284 Enter into Gating configuration >>>>
7227 12:26:59.969503 Exit from Gating configuration <<<<
7228 12:26:59.972653 Enter into DVFS_PRE_config >>>>>
7229 12:26:59.986172 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7230 12:26:59.989454 Exit from DVFS_PRE_config <<<<<
7231 12:26:59.992674 Enter into PICG configuration >>>>
7232 12:26:59.996038 Exit from PICG configuration <<<<
7233 12:26:59.996177 [RX_INPUT] configuration >>>>>
7234 12:26:59.999245 [RX_INPUT] configuration <<<<<
7235 12:27:00.005861 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7236 12:27:00.009096 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7237 12:27:00.015815 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7238 12:27:00.022446 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7239 12:27:00.028683 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7240 12:27:00.035312 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7241 12:27:00.038598 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7242 12:27:00.041898 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7243 12:27:00.048525 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7244 12:27:00.052100 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7245 12:27:00.055334 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7246 12:27:00.061875 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7247 12:27:00.065075 ===================================
7248 12:27:00.065190 LPDDR4 DRAM CONFIGURATION
7249 12:27:00.068268 ===================================
7250 12:27:00.071752 EX_ROW_EN[0] = 0x0
7251 12:27:00.071866 EX_ROW_EN[1] = 0x0
7252 12:27:00.074910 LP4Y_EN = 0x0
7253 12:27:00.075006 WORK_FSP = 0x1
7254 12:27:00.078169 WL = 0x5
7255 12:27:00.081700 RL = 0x5
7256 12:27:00.081821 BL = 0x2
7257 12:27:00.084714 RPST = 0x0
7258 12:27:00.084825 RD_PRE = 0x0
7259 12:27:00.087915 WR_PRE = 0x1
7260 12:27:00.088017 WR_PST = 0x1
7261 12:27:00.091554 DBI_WR = 0x0
7262 12:27:00.091686 DBI_RD = 0x0
7263 12:27:00.094763 OTF = 0x1
7264 12:27:00.097962 ===================================
7265 12:27:00.101360 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7266 12:27:00.104620 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7267 12:27:00.111290 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7268 12:27:00.114743 ===================================
7269 12:27:00.114862 LPDDR4 DRAM CONFIGURATION
7270 12:27:00.118014 ===================================
7271 12:27:00.121339 EX_ROW_EN[0] = 0x10
7272 12:27:00.121446 EX_ROW_EN[1] = 0x0
7273 12:27:00.124668 LP4Y_EN = 0x0
7274 12:27:00.127589 WORK_FSP = 0x1
7275 12:27:00.127682 WL = 0x5
7276 12:27:00.130959 RL = 0x5
7277 12:27:00.131049 BL = 0x2
7278 12:27:00.134215 RPST = 0x0
7279 12:27:00.134306 RD_PRE = 0x0
7280 12:27:00.137508 WR_PRE = 0x1
7281 12:27:00.137599 WR_PST = 0x1
7282 12:27:00.140712 DBI_WR = 0x0
7283 12:27:00.140831 DBI_RD = 0x0
7284 12:27:00.144196 OTF = 0x1
7285 12:27:00.147396 ===================================
7286 12:27:00.153937 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7287 12:27:00.154046 ==
7288 12:27:00.157224 Dram Type= 6, Freq= 0, CH_0, rank 0
7289 12:27:00.160477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7290 12:27:00.160593 ==
7291 12:27:00.163677 [Duty_Offset_Calibration]
7292 12:27:00.163766 B0:2 B1:0 CA:1
7293 12:27:00.163853
7294 12:27:00.167228 [DutyScan_Calibration_Flow] k_type=0
7295 12:27:00.176793
7296 12:27:00.176905 ==CLK 0==
7297 12:27:00.180331 Final CLK duty delay cell = -4
7298 12:27:00.183589 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7299 12:27:00.187075 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7300 12:27:00.190028 [-4] AVG Duty = 4922%(X100)
7301 12:27:00.190146
7302 12:27:00.193467 CH0 CLK Duty spec in!! Max-Min= 218%
7303 12:27:00.196506 [DutyScan_Calibration_Flow] ====Done====
7304 12:27:00.196596
7305 12:27:00.199869 [DutyScan_Calibration_Flow] k_type=1
7306 12:27:00.216327
7307 12:27:00.216468 ==DQS 0 ==
7308 12:27:00.219678 Final DQS duty delay cell = 0
7309 12:27:00.222971 [0] MAX Duty = 5249%(X100), DQS PI = 32
7310 12:27:00.226291 [0] MIN Duty = 4969%(X100), DQS PI = 0
7311 12:27:00.226382 [0] AVG Duty = 5109%(X100)
7312 12:27:00.229703
7313 12:27:00.229788 ==DQS 1 ==
7314 12:27:00.233118 Final DQS duty delay cell = -4
7315 12:27:00.236488 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7316 12:27:00.239878 [-4] MIN Duty = 4875%(X100), DQS PI = 6
7317 12:27:00.243206 [-4] AVG Duty = 5000%(X100)
7318 12:27:00.243293
7319 12:27:00.246471 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7320 12:27:00.246557
7321 12:27:00.249861 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7322 12:27:00.253099 [DutyScan_Calibration_Flow] ====Done====
7323 12:27:00.253186
7324 12:27:00.256393 [DutyScan_Calibration_Flow] k_type=3
7325 12:27:00.273047
7326 12:27:00.273202 ==DQM 0 ==
7327 12:27:00.276280 Final DQM duty delay cell = 0
7328 12:27:00.279477 [0] MAX Duty = 5124%(X100), DQS PI = 26
7329 12:27:00.282722 [0] MIN Duty = 4844%(X100), DQS PI = 2
7330 12:27:00.286198 [0] AVG Duty = 4984%(X100)
7331 12:27:00.286285
7332 12:27:00.286352 ==DQM 1 ==
7333 12:27:00.289528 Final DQM duty delay cell = -4
7334 12:27:00.292827 [-4] MAX Duty = 5031%(X100), DQS PI = 44
7335 12:27:00.295866 [-4] MIN Duty = 4751%(X100), DQS PI = 10
7336 12:27:00.299373 [-4] AVG Duty = 4891%(X100)
7337 12:27:00.299452
7338 12:27:00.302571 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7339 12:27:00.302656
7340 12:27:00.305999 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7341 12:27:00.309252 [DutyScan_Calibration_Flow] ====Done====
7342 12:27:00.309334
7343 12:27:00.312545 [DutyScan_Calibration_Flow] k_type=2
7344 12:27:00.330667
7345 12:27:00.330808 ==DQ 0 ==
7346 12:27:00.334001 Final DQ duty delay cell = 0
7347 12:27:00.336878 [0] MAX Duty = 5156%(X100), DQS PI = 36
7348 12:27:00.340197 [0] MIN Duty = 5000%(X100), DQS PI = 16
7349 12:27:00.340283 [0] AVG Duty = 5078%(X100)
7350 12:27:00.343659
7351 12:27:00.343743 ==DQ 1 ==
7352 12:27:00.346903 Final DQ duty delay cell = 0
7353 12:27:00.350275 [0] MAX Duty = 4969%(X100), DQS PI = 4
7354 12:27:00.353595 [0] MIN Duty = 4875%(X100), DQS PI = 12
7355 12:27:00.353671 [0] AVG Duty = 4922%(X100)
7356 12:27:00.356804
7357 12:27:00.360001 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7358 12:27:00.360122
7359 12:27:00.363734 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7360 12:27:00.366990 [DutyScan_Calibration_Flow] ====Done====
7361 12:27:00.367131 ==
7362 12:27:00.370309 Dram Type= 6, Freq= 0, CH_1, rank 0
7363 12:27:00.373604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7364 12:27:00.373709 ==
7365 12:27:00.376585 [Duty_Offset_Calibration]
7366 12:27:00.376711 B0:0 B1:-1 CA:2
7367 12:27:00.376820
7368 12:27:00.379785 [DutyScan_Calibration_Flow] k_type=0
7369 12:27:00.390666
7370 12:27:00.390769 ==CLK 0==
7371 12:27:00.394378 Final CLK duty delay cell = 0
7372 12:27:00.397474 [0] MAX Duty = 5156%(X100), DQS PI = 10
7373 12:27:00.400559 [0] MIN Duty = 4938%(X100), DQS PI = 46
7374 12:27:00.400665 [0] AVG Duty = 5047%(X100)
7375 12:27:00.404193
7376 12:27:00.404277 CH1 CLK Duty spec in!! Max-Min= 218%
7377 12:27:00.410806 [DutyScan_Calibration_Flow] ====Done====
7378 12:27:00.410914
7379 12:27:00.413978 [DutyScan_Calibration_Flow] k_type=1
7380 12:27:00.430266
7381 12:27:00.430370 ==DQS 0 ==
7382 12:27:00.433515 Final DQS duty delay cell = 0
7383 12:27:00.436885 [0] MAX Duty = 5124%(X100), DQS PI = 24
7384 12:27:00.440285 [0] MIN Duty = 5000%(X100), DQS PI = 0
7385 12:27:00.443551 [0] AVG Duty = 5062%(X100)
7386 12:27:00.443636
7387 12:27:00.443702 ==DQS 1 ==
7388 12:27:00.446752 Final DQS duty delay cell = 0
7389 12:27:00.450103 [0] MAX Duty = 5187%(X100), DQS PI = 0
7390 12:27:00.453429 [0] MIN Duty = 4844%(X100), DQS PI = 32
7391 12:27:00.456682 [0] AVG Duty = 5015%(X100)
7392 12:27:00.456804
7393 12:27:00.459962 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7394 12:27:00.460064
7395 12:27:00.463330 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7396 12:27:00.466578 [DutyScan_Calibration_Flow] ====Done====
7397 12:27:00.466697
7398 12:27:00.469739 [DutyScan_Calibration_Flow] k_type=3
7399 12:27:00.487832
7400 12:27:00.487992 ==DQM 0 ==
7401 12:27:00.491082 Final DQM duty delay cell = 4
7402 12:27:00.494457 [4] MAX Duty = 5125%(X100), DQS PI = 22
7403 12:27:00.497526 [4] MIN Duty = 4969%(X100), DQS PI = 44
7404 12:27:00.500976 [4] AVG Duty = 5047%(X100)
7405 12:27:00.501065
7406 12:27:00.501132 ==DQM 1 ==
7407 12:27:00.504273 Final DQM duty delay cell = 0
7408 12:27:00.507848 [0] MAX Duty = 5281%(X100), DQS PI = 58
7409 12:27:00.511005 [0] MIN Duty = 4907%(X100), DQS PI = 34
7410 12:27:00.514285 [0] AVG Duty = 5094%(X100)
7411 12:27:00.514397
7412 12:27:00.517604 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7413 12:27:00.517698
7414 12:27:00.521037 CH1 DQM 1 Duty spec in!! Max-Min= 374%
7415 12:27:00.524216 [DutyScan_Calibration_Flow] ====Done====
7416 12:27:00.524340
7417 12:27:00.527427 [DutyScan_Calibration_Flow] k_type=2
7418 12:27:00.545040
7419 12:27:00.545130 ==DQ 0 ==
7420 12:27:00.548201 Final DQ duty delay cell = 0
7421 12:27:00.551577 [0] MAX Duty = 5093%(X100), DQS PI = 18
7422 12:27:00.554533 [0] MIN Duty = 4969%(X100), DQS PI = 46
7423 12:27:00.557794 [0] AVG Duty = 5031%(X100)
7424 12:27:00.557905
7425 12:27:00.557998 ==DQ 1 ==
7426 12:27:00.561065 Final DQ duty delay cell = 0
7427 12:27:00.564418 [0] MAX Duty = 5062%(X100), DQS PI = 2
7428 12:27:00.567717 [0] MIN Duty = 4844%(X100), DQS PI = 32
7429 12:27:00.571235 [0] AVG Duty = 4953%(X100)
7430 12:27:00.571327
7431 12:27:00.574509 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7432 12:27:00.574591
7433 12:27:00.577865 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7434 12:27:00.581150 [DutyScan_Calibration_Flow] ====Done====
7435 12:27:00.584393 nWR fixed to 30
7436 12:27:00.587519 [ModeRegInit_LP4] CH0 RK0
7437 12:27:00.587643 [ModeRegInit_LP4] CH0 RK1
7438 12:27:00.590811 [ModeRegInit_LP4] CH1 RK0
7439 12:27:00.594211 [ModeRegInit_LP4] CH1 RK1
7440 12:27:00.594285 match AC timing 5
7441 12:27:00.600914 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7442 12:27:00.604082 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7443 12:27:00.607205 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7444 12:27:00.613825 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7445 12:27:00.617490 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7446 12:27:00.617580 [MiockJmeterHQA]
7447 12:27:00.617650
7448 12:27:00.620493 [DramcMiockJmeter] u1RxGatingPI = 0
7449 12:27:00.623932 0 : 4253, 4027
7450 12:27:00.624021 4 : 4252, 4027
7451 12:27:00.627335 8 : 4253, 4026
7452 12:27:00.627423 12 : 4252, 4027
7453 12:27:00.630737 16 : 4363, 4137
7454 12:27:00.630826 20 : 4252, 4027
7455 12:27:00.630899 24 : 4253, 4027
7456 12:27:00.633951 28 : 4252, 4027
7457 12:27:00.634039 32 : 4255, 4029
7458 12:27:00.636867 36 : 4253, 4027
7459 12:27:00.636954 40 : 4252, 4027
7460 12:27:00.640270 44 : 4366, 4140
7461 12:27:00.640357 48 : 4252, 4027
7462 12:27:00.643666 52 : 4255, 4030
7463 12:27:00.643753 56 : 4252, 4027
7464 12:27:00.643822 60 : 4363, 4140
7465 12:27:00.646993 64 : 4252, 4027
7466 12:27:00.647082 68 : 4361, 4138
7467 12:27:00.650191 72 : 4250, 4027
7468 12:27:00.650279 76 : 4250, 4027
7469 12:27:00.653536 80 : 4250, 4027
7470 12:27:00.653633 84 : 4252, 4029
7471 12:27:00.656795 88 : 4250, 3448
7472 12:27:00.656883 92 : 4250, 0
7473 12:27:00.656952 96 : 4252, 0
7474 12:27:00.660054 100 : 4361, 0
7475 12:27:00.660141 104 : 4363, 0
7476 12:27:00.660215 108 : 4250, 0
7477 12:27:00.663484 112 : 4250, 0
7478 12:27:00.663577 116 : 4250, 0
7479 12:27:00.666830 120 : 4252, 0
7480 12:27:00.666917 124 : 4252, 0
7481 12:27:00.666986 128 : 4250, 0
7482 12:27:00.670064 132 : 4252, 0
7483 12:27:00.670152 136 : 4249, 0
7484 12:27:00.673283 140 : 4250, 0
7485 12:27:00.673381 144 : 4252, 0
7486 12:27:00.673460 148 : 4250, 0
7487 12:27:00.676924 152 : 4361, 0
7488 12:27:00.677013 156 : 4250, 0
7489 12:27:00.680239 160 : 4250, 0
7490 12:27:00.680329 164 : 4250, 0
7491 12:27:00.680398 168 : 4250, 0
7492 12:27:00.683069 172 : 4252, 0
7493 12:27:00.683157 176 : 4250, 0
7494 12:27:00.686432 180 : 4250, 0
7495 12:27:00.686521 184 : 4253, 0
7496 12:27:00.686590 188 : 4249, 0
7497 12:27:00.689722 192 : 4250, 0
7498 12:27:00.689814 196 : 4252, 0
7499 12:27:00.689885 200 : 4360, 14
7500 12:27:00.692973 204 : 4249, 2640
7501 12:27:00.693070 208 : 4253, 4029
7502 12:27:00.696271 212 : 4360, 4138
7503 12:27:00.696358 216 : 4250, 4027
7504 12:27:00.700000 220 : 4250, 4027
7505 12:27:00.700089 224 : 4361, 4137
7506 12:27:00.702918 228 : 4361, 4137
7507 12:27:00.703005 232 : 4250, 4027
7508 12:27:00.706267 236 : 4363, 4140
7509 12:27:00.706354 240 : 4250, 4027
7510 12:27:00.709847 244 : 4250, 4027
7511 12:27:00.709935 248 : 4250, 4027
7512 12:27:00.713094 252 : 4252, 4029
7513 12:27:00.713182 256 : 4250, 4027
7514 12:27:00.716456 260 : 4250, 4027
7515 12:27:00.716571 264 : 4250, 4027
7516 12:27:00.716671 268 : 4252, 4029
7517 12:27:00.719483 272 : 4250, 4027
7518 12:27:00.719604 276 : 4361, 4137
7519 12:27:00.723069 280 : 4363, 4138
7520 12:27:00.723158 284 : 4250, 4027
7521 12:27:00.726317 288 : 4363, 4140
7522 12:27:00.726406 292 : 4250, 4027
7523 12:27:00.729802 296 : 4250, 4026
7524 12:27:00.729890 300 : 4250, 4027
7525 12:27:00.733045 304 : 4252, 4029
7526 12:27:00.733133 308 : 4250, 4027
7527 12:27:00.736066 312 : 4250, 3755
7528 12:27:00.736153 316 : 4360, 1722
7529 12:27:00.736223
7530 12:27:00.739614 MIOCK jitter meter ch=0
7531 12:27:00.739701
7532 12:27:00.743010 1T = (316-92) = 224 dly cells
7533 12:27:00.746302 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7534 12:27:00.746378 ==
7535 12:27:00.749592 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 12:27:00.756026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 12:27:00.756118 ==
7538 12:27:00.759347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7539 12:27:00.766124 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7540 12:27:00.769463 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7541 12:27:00.775539 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7542 12:27:00.783699 [CA 0] Center 42 (12~72) winsize 61
7543 12:27:00.786919 [CA 1] Center 42 (12~72) winsize 61
7544 12:27:00.790330 [CA 2] Center 37 (7~67) winsize 61
7545 12:27:00.793612 [CA 3] Center 37 (7~67) winsize 61
7546 12:27:00.797148 [CA 4] Center 36 (6~66) winsize 61
7547 12:27:00.800071 [CA 5] Center 35 (5~65) winsize 61
7548 12:27:00.800165
7549 12:27:00.803384 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7550 12:27:00.803471
7551 12:27:00.810120 [CATrainingPosCal] consider 1 rank data
7552 12:27:00.810207 u2DelayCellTimex100 = 290/100 ps
7553 12:27:00.816980 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7554 12:27:00.820305 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7555 12:27:00.823417 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7556 12:27:00.826914 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7557 12:27:00.830094 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7558 12:27:00.833197 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7559 12:27:00.833284
7560 12:27:00.836556 CA PerBit enable=1, Macro0, CA PI delay=35
7561 12:27:00.836642
7562 12:27:00.839878 [CBTSetCACLKResult] CA Dly = 35
7563 12:27:00.843307 CS Dly: 9 (0~40)
7564 12:27:00.846358 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7565 12:27:00.849773 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7566 12:27:00.849858 ==
7567 12:27:00.853111 Dram Type= 6, Freq= 0, CH_0, rank 1
7568 12:27:00.859820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 12:27:00.859906 ==
7570 12:27:00.863248 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7571 12:27:00.866592 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7572 12:27:00.873255 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7573 12:27:00.879704 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7574 12:27:00.887013 [CA 0] Center 43 (13~74) winsize 62
7575 12:27:00.890299 [CA 1] Center 43 (13~73) winsize 61
7576 12:27:00.893637 [CA 2] Center 38 (9~68) winsize 60
7577 12:27:00.896884 [CA 3] Center 38 (9~68) winsize 60
7578 12:27:00.900416 [CA 4] Center 37 (7~67) winsize 61
7579 12:27:00.903207 [CA 5] Center 36 (6~66) winsize 61
7580 12:27:00.903285
7581 12:27:00.906600 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7582 12:27:00.906685
7583 12:27:00.913318 [CATrainingPosCal] consider 2 rank data
7584 12:27:00.913406 u2DelayCellTimex100 = 290/100 ps
7585 12:27:00.920155 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7586 12:27:00.923328 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7587 12:27:00.926675 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7588 12:27:00.929917 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7589 12:27:00.933085 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7590 12:27:00.936694 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7591 12:27:00.936817
7592 12:27:00.939752 CA PerBit enable=1, Macro0, CA PI delay=35
7593 12:27:00.939869
7594 12:27:00.943309 [CBTSetCACLKResult] CA Dly = 35
7595 12:27:00.946546 CS Dly: 10 (0~43)
7596 12:27:00.949733 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7597 12:27:00.953085 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7598 12:27:00.953172
7599 12:27:00.956250 ----->DramcWriteLeveling(PI) begin...
7600 12:27:00.959561 ==
7601 12:27:00.959644 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 12:27:00.966330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 12:27:00.966414 ==
7604 12:27:00.969699 Write leveling (Byte 0): 36 => 36
7605 12:27:00.972604 Write leveling (Byte 1): 31 => 31
7606 12:27:00.975886 DramcWriteLeveling(PI) end<-----
7607 12:27:00.975968
7608 12:27:00.976033 ==
7609 12:27:00.979182 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 12:27:00.982914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 12:27:00.982996 ==
7612 12:27:00.986188 [Gating] SW mode calibration
7613 12:27:00.992488 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7614 12:27:00.998980 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7615 12:27:01.002274 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 12:27:01.005582 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 12:27:01.012262 1 4 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
7618 12:27:01.015525 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7619 12:27:01.019008 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7620 12:27:01.025825 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7621 12:27:01.029203 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7622 12:27:01.032462 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7623 12:27:01.038729 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 12:27:01.042310 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 12:27:01.045305 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
7626 12:27:01.048627 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7627 12:27:01.055430 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7628 12:27:01.058878 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
7629 12:27:01.062112 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 12:27:01.068617 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 12:27:01.071916 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 12:27:01.075290 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 12:27:01.081935 1 6 8 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7634 12:27:01.085298 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7635 12:27:01.088599 1 6 16 | B1->B0 | 2323 4646 | 1 0 | (0 0) (0 0)
7636 12:27:01.095030 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 12:27:01.098361 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 12:27:01.101759 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 12:27:01.108215 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 12:27:01.111421 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 12:27:01.114832 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7642 12:27:01.121487 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7643 12:27:01.124639 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7644 12:27:01.127921 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7645 12:27:01.134534 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 12:27:01.138315 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 12:27:01.141620 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 12:27:01.148146 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 12:27:01.151280 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 12:27:01.154449 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 12:27:01.161019 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 12:27:01.164715 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 12:27:01.167987 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 12:27:01.174606 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 12:27:01.177908 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 12:27:01.181230 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 12:27:01.187455 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7658 12:27:01.190719 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7659 12:27:01.194112 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7660 12:27:01.197361 Total UI for P1: 0, mck2ui 16
7661 12:27:01.200862 best dqsien dly found for B0: ( 1, 9, 10)
7662 12:27:01.207386 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7663 12:27:01.210609 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 12:27:01.213841 Total UI for P1: 0, mck2ui 16
7665 12:27:01.217057 best dqsien dly found for B1: ( 1, 9, 18)
7666 12:27:01.220396 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7667 12:27:01.223566 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7668 12:27:01.223683
7669 12:27:01.226877 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7670 12:27:01.230550 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7671 12:27:01.233921 [Gating] SW calibration Done
7672 12:27:01.234008 ==
7673 12:27:01.237145 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 12:27:01.243756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 12:27:01.243843 ==
7676 12:27:01.243910 RX Vref Scan: 0
7677 12:27:01.243972
7678 12:27:01.246998 RX Vref 0 -> 0, step: 1
7679 12:27:01.247083
7680 12:27:01.250371 RX Delay 0 -> 252, step: 8
7681 12:27:01.253605 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7682 12:27:01.256969 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7683 12:27:01.260076 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7684 12:27:01.263557 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7685 12:27:01.269764 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7686 12:27:01.273086 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7687 12:27:01.276424 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7688 12:27:01.279775 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7689 12:27:01.283383 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7690 12:27:01.290017 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7691 12:27:01.293327 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7692 12:27:01.296556 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7693 12:27:01.299729 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7694 12:27:01.302961 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7695 12:27:01.309904 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7696 12:27:01.313264 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7697 12:27:01.313348 ==
7698 12:27:01.316414 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 12:27:01.319760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 12:27:01.319843 ==
7701 12:27:01.323168 DQS Delay:
7702 12:27:01.323251 DQS0 = 0, DQS1 = 0
7703 12:27:01.323316 DQM Delay:
7704 12:27:01.326464 DQM0 = 138, DQM1 = 126
7705 12:27:01.326546 DQ Delay:
7706 12:27:01.329783 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7707 12:27:01.332739 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7708 12:27:01.339248 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7709 12:27:01.342682 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7710 12:27:01.342767
7711 12:27:01.342832
7712 12:27:01.342891 ==
7713 12:27:01.345837 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 12:27:01.349121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 12:27:01.349212 ==
7716 12:27:01.349280
7717 12:27:01.349341
7718 12:27:01.352496 TX Vref Scan disable
7719 12:27:01.355841 == TX Byte 0 ==
7720 12:27:01.359103 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7721 12:27:01.362241 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7722 12:27:01.365923 == TX Byte 1 ==
7723 12:27:01.368997 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7724 12:27:01.372376 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7725 12:27:01.372500 ==
7726 12:27:01.375604 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 12:27:01.381970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 12:27:01.382061 ==
7729 12:27:01.393841
7730 12:27:01.397180 TX Vref early break, caculate TX vref
7731 12:27:01.400527 TX Vref=16, minBit 4, minWin=22, winSum=378
7732 12:27:01.403797 TX Vref=18, minBit 7, minWin=22, winSum=384
7733 12:27:01.406949 TX Vref=20, minBit 6, minWin=23, winSum=393
7734 12:27:01.410371 TX Vref=22, minBit 4, minWin=24, winSum=408
7735 12:27:01.413630 TX Vref=24, minBit 4, minWin=25, winSum=420
7736 12:27:01.420141 TX Vref=26, minBit 0, minWin=26, winSum=428
7737 12:27:01.423477 TX Vref=28, minBit 2, minWin=25, winSum=426
7738 12:27:01.426800 TX Vref=30, minBit 0, minWin=25, winSum=419
7739 12:27:01.430147 TX Vref=32, minBit 0, minWin=25, winSum=411
7740 12:27:01.433512 TX Vref=34, minBit 1, minWin=24, winSum=401
7741 12:27:01.439602 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 26
7742 12:27:01.439690
7743 12:27:01.443005 Final TX Range 0 Vref 26
7744 12:27:01.443090
7745 12:27:01.443155 ==
7746 12:27:01.446262 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 12:27:01.449637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 12:27:01.449722 ==
7749 12:27:01.449787
7750 12:27:01.449846
7751 12:27:01.453146 TX Vref Scan disable
7752 12:27:01.459339 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7753 12:27:01.459423 == TX Byte 0 ==
7754 12:27:01.462770 u2DelayCellOfst[0]=16 cells (5 PI)
7755 12:27:01.465958 u2DelayCellOfst[1]=16 cells (5 PI)
7756 12:27:01.469770 u2DelayCellOfst[2]=13 cells (4 PI)
7757 12:27:01.472815 u2DelayCellOfst[3]=13 cells (4 PI)
7758 12:27:01.475917 u2DelayCellOfst[4]=10 cells (3 PI)
7759 12:27:01.479652 u2DelayCellOfst[5]=0 cells (0 PI)
7760 12:27:01.482724 u2DelayCellOfst[6]=20 cells (6 PI)
7761 12:27:01.485855 u2DelayCellOfst[7]=20 cells (6 PI)
7762 12:27:01.489555 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7763 12:27:01.492761 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7764 12:27:01.496079 == TX Byte 1 ==
7765 12:27:01.499322 u2DelayCellOfst[8]=0 cells (0 PI)
7766 12:27:01.502598 u2DelayCellOfst[9]=0 cells (0 PI)
7767 12:27:01.505796 u2DelayCellOfst[10]=6 cells (2 PI)
7768 12:27:01.509056 u2DelayCellOfst[11]=0 cells (0 PI)
7769 12:27:01.509140 u2DelayCellOfst[12]=13 cells (4 PI)
7770 12:27:01.512268 u2DelayCellOfst[13]=13 cells (4 PI)
7771 12:27:01.515640 u2DelayCellOfst[14]=16 cells (5 PI)
7772 12:27:01.518948 u2DelayCellOfst[15]=10 cells (3 PI)
7773 12:27:01.525355 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7774 12:27:01.528597 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7775 12:27:01.528684 DramC Write-DBI on
7776 12:27:01.531856 ==
7777 12:27:01.535601 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 12:27:01.538829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 12:27:01.538915 ==
7780 12:27:01.538981
7781 12:27:01.539040
7782 12:27:01.541971 TX Vref Scan disable
7783 12:27:01.542055 == TX Byte 0 ==
7784 12:27:01.548512 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7785 12:27:01.548599 == TX Byte 1 ==
7786 12:27:01.551685 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7787 12:27:01.555051 DramC Write-DBI off
7788 12:27:01.555137
7789 12:27:01.555203 [DATLAT]
7790 12:27:01.558274 Freq=1600, CH0 RK0
7791 12:27:01.558358
7792 12:27:01.558424 DATLAT Default: 0xf
7793 12:27:01.561654 0, 0xFFFF, sum = 0
7794 12:27:01.561739 1, 0xFFFF, sum = 0
7795 12:27:01.565036 2, 0xFFFF, sum = 0
7796 12:27:01.568302 3, 0xFFFF, sum = 0
7797 12:27:01.568387 4, 0xFFFF, sum = 0
7798 12:27:01.571655 5, 0xFFFF, sum = 0
7799 12:27:01.571740 6, 0xFFFF, sum = 0
7800 12:27:01.574706 7, 0xFFFF, sum = 0
7801 12:27:01.574791 8, 0xFFFF, sum = 0
7802 12:27:01.578229 9, 0xFFFF, sum = 0
7803 12:27:01.578315 10, 0xFFFF, sum = 0
7804 12:27:01.581334 11, 0xFFFF, sum = 0
7805 12:27:01.581419 12, 0xFFFF, sum = 0
7806 12:27:01.584404 13, 0xFFFF, sum = 0
7807 12:27:01.584489 14, 0x0, sum = 1
7808 12:27:01.587980 15, 0x0, sum = 2
7809 12:27:01.588065 16, 0x0, sum = 3
7810 12:27:01.591078 17, 0x0, sum = 4
7811 12:27:01.591164 best_step = 15
7812 12:27:01.591231
7813 12:27:01.591292 ==
7814 12:27:01.594340 Dram Type= 6, Freq= 0, CH_0, rank 0
7815 12:27:01.600989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7816 12:27:01.601075 ==
7817 12:27:01.601141 RX Vref Scan: 1
7818 12:27:01.601201
7819 12:27:01.604677 Set Vref Range= 24 -> 127
7820 12:27:01.604785
7821 12:27:01.607550 RX Vref 24 -> 127, step: 1
7822 12:27:01.607637
7823 12:27:01.607716 RX Delay 19 -> 252, step: 4
7824 12:27:01.611311
7825 12:27:01.611395 Set Vref, RX VrefLevel [Byte0]: 24
7826 12:27:01.614278 [Byte1]: 24
7827 12:27:01.618347
7828 12:27:01.618431 Set Vref, RX VrefLevel [Byte0]: 25
7829 12:27:01.621641 [Byte1]: 25
7830 12:27:01.625901
7831 12:27:01.626012 Set Vref, RX VrefLevel [Byte0]: 26
7832 12:27:01.629545 [Byte1]: 26
7833 12:27:01.633748
7834 12:27:01.633831 Set Vref, RX VrefLevel [Byte0]: 27
7835 12:27:01.637079 [Byte1]: 27
7836 12:27:01.641366
7837 12:27:01.641450 Set Vref, RX VrefLevel [Byte0]: 28
7838 12:27:01.644569 [Byte1]: 28
7839 12:27:01.648689
7840 12:27:01.648776 Set Vref, RX VrefLevel [Byte0]: 29
7841 12:27:01.651985 [Byte1]: 29
7842 12:27:01.656517
7843 12:27:01.656626 Set Vref, RX VrefLevel [Byte0]: 30
7844 12:27:01.659669 [Byte1]: 30
7845 12:27:01.663907
7846 12:27:01.664009 Set Vref, RX VrefLevel [Byte0]: 31
7847 12:27:01.667280 [Byte1]: 31
7848 12:27:01.671445
7849 12:27:01.671547 Set Vref, RX VrefLevel [Byte0]: 32
7850 12:27:01.674885 [Byte1]: 32
7851 12:27:01.679035
7852 12:27:01.679144 Set Vref, RX VrefLevel [Byte0]: 33
7853 12:27:01.682236 [Byte1]: 33
7854 12:27:01.686582
7855 12:27:01.686657 Set Vref, RX VrefLevel [Byte0]: 34
7856 12:27:01.689855 [Byte1]: 34
7857 12:27:01.694241
7858 12:27:01.694351 Set Vref, RX VrefLevel [Byte0]: 35
7859 12:27:01.697275 [Byte1]: 35
7860 12:27:01.701759
7861 12:27:01.701861 Set Vref, RX VrefLevel [Byte0]: 36
7862 12:27:01.705100 [Byte1]: 36
7863 12:27:01.709291
7864 12:27:01.709364 Set Vref, RX VrefLevel [Byte0]: 37
7865 12:27:01.712518 [Byte1]: 37
7866 12:27:01.716744
7867 12:27:01.719978 Set Vref, RX VrefLevel [Byte0]: 38
7868 12:27:01.723190 [Byte1]: 38
7869 12:27:01.723288
7870 12:27:01.726545 Set Vref, RX VrefLevel [Byte0]: 39
7871 12:27:01.729998 [Byte1]: 39
7872 12:27:01.730082
7873 12:27:01.733196 Set Vref, RX VrefLevel [Byte0]: 40
7874 12:27:01.736367 [Byte1]: 40
7875 12:27:01.736450
7876 12:27:01.740076 Set Vref, RX VrefLevel [Byte0]: 41
7877 12:27:01.742979 [Byte1]: 41
7878 12:27:01.747342
7879 12:27:01.747425 Set Vref, RX VrefLevel [Byte0]: 42
7880 12:27:01.750496 [Byte1]: 42
7881 12:27:01.754655
7882 12:27:01.754739 Set Vref, RX VrefLevel [Byte0]: 43
7883 12:27:01.757903 [Byte1]: 43
7884 12:27:01.762185
7885 12:27:01.762268 Set Vref, RX VrefLevel [Byte0]: 44
7886 12:27:01.765394 [Byte1]: 44
7887 12:27:01.770133
7888 12:27:01.770217 Set Vref, RX VrefLevel [Byte0]: 45
7889 12:27:01.773020 [Byte1]: 45
7890 12:27:01.777350
7891 12:27:01.777434 Set Vref, RX VrefLevel [Byte0]: 46
7892 12:27:01.781004 [Byte1]: 46
7893 12:27:01.785181
7894 12:27:01.785264 Set Vref, RX VrefLevel [Byte0]: 47
7895 12:27:01.788403 [Byte1]: 47
7896 12:27:01.792472
7897 12:27:01.792585 Set Vref, RX VrefLevel [Byte0]: 48
7898 12:27:01.796079 [Byte1]: 48
7899 12:27:01.800331
7900 12:27:01.800416 Set Vref, RX VrefLevel [Byte0]: 49
7901 12:27:01.803427 [Byte1]: 49
7902 12:27:01.807783
7903 12:27:01.807867 Set Vref, RX VrefLevel [Byte0]: 50
7904 12:27:01.811000 [Byte1]: 50
7905 12:27:01.815123
7906 12:27:01.818483 Set Vref, RX VrefLevel [Byte0]: 51
7907 12:27:01.821726 [Byte1]: 51
7908 12:27:01.821801
7909 12:27:01.824921 Set Vref, RX VrefLevel [Byte0]: 52
7910 12:27:01.828102 [Byte1]: 52
7911 12:27:01.828185
7912 12:27:01.831525 Set Vref, RX VrefLevel [Byte0]: 53
7913 12:27:01.834873 [Byte1]: 53
7914 12:27:01.837927
7915 12:27:01.838011 Set Vref, RX VrefLevel [Byte0]: 54
7916 12:27:01.841660 [Byte1]: 54
7917 12:27:01.845416
7918 12:27:01.845501 Set Vref, RX VrefLevel [Byte0]: 55
7919 12:27:01.848610 [Byte1]: 55
7920 12:27:01.853278
7921 12:27:01.853368 Set Vref, RX VrefLevel [Byte0]: 56
7922 12:27:01.856424 [Byte1]: 56
7923 12:27:01.860673
7924 12:27:01.860779 Set Vref, RX VrefLevel [Byte0]: 57
7925 12:27:01.863966 [Byte1]: 57
7926 12:27:01.868406
7927 12:27:01.868494 Set Vref, RX VrefLevel [Byte0]: 58
7928 12:27:01.871748 [Byte1]: 58
7929 12:27:01.876046
7930 12:27:01.876162 Set Vref, RX VrefLevel [Byte0]: 59
7931 12:27:01.879301 [Byte1]: 59
7932 12:27:01.883614
7933 12:27:01.883723 Set Vref, RX VrefLevel [Byte0]: 60
7934 12:27:01.886511 [Byte1]: 60
7935 12:27:01.891289
7936 12:27:01.891374 Set Vref, RX VrefLevel [Byte0]: 61
7937 12:27:01.894634 [Byte1]: 61
7938 12:27:01.898700
7939 12:27:01.898786 Set Vref, RX VrefLevel [Byte0]: 62
7940 12:27:01.902070 [Byte1]: 62
7941 12:27:01.906131
7942 12:27:01.906217 Set Vref, RX VrefLevel [Byte0]: 63
7943 12:27:01.909323 [Byte1]: 63
7944 12:27:01.913618
7945 12:27:01.913704 Set Vref, RX VrefLevel [Byte0]: 64
7946 12:27:01.916999 [Byte1]: 64
7947 12:27:01.921289
7948 12:27:01.921376 Set Vref, RX VrefLevel [Byte0]: 65
7949 12:27:01.924627 [Byte1]: 65
7950 12:27:01.928887
7951 12:27:01.928971 Set Vref, RX VrefLevel [Byte0]: 66
7952 12:27:01.932082 [Byte1]: 66
7953 12:27:01.936361
7954 12:27:01.936446 Set Vref, RX VrefLevel [Byte0]: 67
7955 12:27:01.939570 [Byte1]: 67
7956 12:27:01.944118
7957 12:27:01.944206 Set Vref, RX VrefLevel [Byte0]: 68
7958 12:27:01.947084 [Byte1]: 68
7959 12:27:01.951887
7960 12:27:01.951971 Set Vref, RX VrefLevel [Byte0]: 69
7961 12:27:01.954768 [Byte1]: 69
7962 12:27:01.959401
7963 12:27:01.959485 Set Vref, RX VrefLevel [Byte0]: 70
7964 12:27:01.962683 [Byte1]: 70
7965 12:27:01.966618
7966 12:27:01.966703 Set Vref, RX VrefLevel [Byte0]: 71
7967 12:27:01.969981 [Byte1]: 71
7968 12:27:01.974554
7969 12:27:01.974639 Set Vref, RX VrefLevel [Byte0]: 72
7970 12:27:01.977892 [Byte1]: 72
7971 12:27:01.981682
7972 12:27:01.981766 Set Vref, RX VrefLevel [Byte0]: 73
7973 12:27:01.985144 [Byte1]: 73
7974 12:27:01.989341
7975 12:27:01.989425 Set Vref, RX VrefLevel [Byte0]: 74
7976 12:27:01.992709 [Byte1]: 74
7977 12:27:01.996983
7978 12:27:01.997067 Set Vref, RX VrefLevel [Byte0]: 75
7979 12:27:02.000099 [Byte1]: 75
7980 12:27:02.004896
7981 12:27:02.004981 Set Vref, RX VrefLevel [Byte0]: 76
7982 12:27:02.008028 [Byte1]: 76
7983 12:27:02.012191
7984 12:27:02.012274 Set Vref, RX VrefLevel [Byte0]: 77
7985 12:27:02.015370 [Byte1]: 77
7986 12:27:02.019810
7987 12:27:02.019895 Set Vref, RX VrefLevel [Byte0]: 78
7988 12:27:02.023204 [Byte1]: 78
7989 12:27:02.027231
7990 12:27:02.027316 Final RX Vref Byte 0 = 60 to rank0
7991 12:27:02.030508 Final RX Vref Byte 1 = 62 to rank0
7992 12:27:02.034187 Final RX Vref Byte 0 = 60 to rank1
7993 12:27:02.037407 Final RX Vref Byte 1 = 62 to rank1==
7994 12:27:02.040631 Dram Type= 6, Freq= 0, CH_0, rank 0
7995 12:27:02.047170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7996 12:27:02.047256 ==
7997 12:27:02.047322 DQS Delay:
7998 12:27:02.050478 DQS0 = 0, DQS1 = 0
7999 12:27:02.050563 DQM Delay:
8000 12:27:02.050629 DQM0 = 135, DQM1 = 124
8001 12:27:02.053774 DQ Delay:
8002 12:27:02.057033 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
8003 12:27:02.060342 DQ4 =138, DQ5 =126, DQ6 =142, DQ7 =142
8004 12:27:02.063931 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8005 12:27:02.067301 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
8006 12:27:02.067386
8007 12:27:02.067452
8008 12:27:02.067511
8009 12:27:02.070198 [DramC_TX_OE_Calibration] TA2
8010 12:27:02.073564 Original DQ_B0 (3 6) =30, OEN = 27
8011 12:27:02.076774 Original DQ_B1 (3 6) =30, OEN = 27
8012 12:27:02.080111 24, 0x0, End_B0=24 End_B1=24
8013 12:27:02.083336 25, 0x0, End_B0=25 End_B1=25
8014 12:27:02.083422 26, 0x0, End_B0=26 End_B1=26
8015 12:27:02.086664 27, 0x0, End_B0=27 End_B1=27
8016 12:27:02.090064 28, 0x0, End_B0=28 End_B1=28
8017 12:27:02.093314 29, 0x0, End_B0=29 End_B1=29
8018 12:27:02.093402 30, 0x0, End_B0=30 End_B1=30
8019 12:27:02.096624 31, 0x4141, End_B0=30 End_B1=30
8020 12:27:02.099934 Byte0 end_step=30 best_step=27
8021 12:27:02.103073 Byte1 end_step=30 best_step=27
8022 12:27:02.106409 Byte0 TX OE(2T, 0.5T) = (3, 3)
8023 12:27:02.109659 Byte1 TX OE(2T, 0.5T) = (3, 3)
8024 12:27:02.109745
8025 12:27:02.109858
8026 12:27:02.116105 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
8027 12:27:02.119605 CH0 RK0: MR19=303, MR18=1D1B
8028 12:27:02.126135 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
8029 12:27:02.126227
8030 12:27:02.129745 ----->DramcWriteLeveling(PI) begin...
8031 12:27:02.129862 ==
8032 12:27:02.132920 Dram Type= 6, Freq= 0, CH_0, rank 1
8033 12:27:02.136181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8034 12:27:02.136296 ==
8035 12:27:02.139372 Write leveling (Byte 0): 36 => 36
8036 12:27:02.143092 Write leveling (Byte 1): 31 => 31
8037 12:27:02.145834 DramcWriteLeveling(PI) end<-----
8038 12:27:02.145949
8039 12:27:02.146100 ==
8040 12:27:02.149250 Dram Type= 6, Freq= 0, CH_0, rank 1
8041 12:27:02.152438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8042 12:27:02.155782 ==
8043 12:27:02.155880 [Gating] SW mode calibration
8044 12:27:02.165763 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8045 12:27:02.169236 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8046 12:27:02.172522 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 12:27:02.179217 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 12:27:02.182429 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
8049 12:27:02.185786 1 4 12 | B1->B0 | 2525 3232 | 1 1 | (1 1) (1 1)
8050 12:27:02.192437 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8051 12:27:02.195625 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8052 12:27:02.198905 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8053 12:27:02.205461 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 12:27:02.208608 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 12:27:02.211961 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 12:27:02.218645 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8057 12:27:02.221992 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
8058 12:27:02.225064 1 5 16 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
8059 12:27:02.232091 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 12:27:02.235072 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 12:27:02.238281 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 12:27:02.245128 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 12:27:02.248463 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 12:27:02.251771 1 6 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
8065 12:27:02.258202 1 6 12 | B1->B0 | 2c2c 4444 | 0 0 | (0 0) (0 0)
8066 12:27:02.261482 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 12:27:02.264748 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 12:27:02.271326 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 12:27:02.274869 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 12:27:02.278150 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 12:27:02.284390 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 12:27:02.287763 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8073 12:27:02.291109 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8074 12:27:02.297806 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8075 12:27:02.301166 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 12:27:02.304544 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 12:27:02.311064 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 12:27:02.313897 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 12:27:02.317196 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 12:27:02.324086 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 12:27:02.327400 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 12:27:02.330602 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 12:27:02.337409 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 12:27:02.340435 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 12:27:02.344122 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 12:27:02.350432 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 12:27:02.353677 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 12:27:02.356970 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8089 12:27:02.363606 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8090 12:27:02.366842 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8091 12:27:02.370220 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8092 12:27:02.373668 Total UI for P1: 0, mck2ui 16
8093 12:27:02.376737 best dqsien dly found for B0: ( 1, 9, 12)
8094 12:27:02.380462 Total UI for P1: 0, mck2ui 16
8095 12:27:02.383753 best dqsien dly found for B1: ( 1, 9, 14)
8096 12:27:02.386531 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8097 12:27:02.390188 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8098 12:27:02.390280
8099 12:27:02.396904 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8100 12:27:02.400269 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8101 12:27:02.403540 [Gating] SW calibration Done
8102 12:27:02.403631 ==
8103 12:27:02.406874 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 12:27:02.410118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 12:27:02.410206 ==
8106 12:27:02.410275 RX Vref Scan: 0
8107 12:27:02.410339
8108 12:27:02.413260 RX Vref 0 -> 0, step: 1
8109 12:27:02.413372
8110 12:27:02.416510 RX Delay 0 -> 252, step: 8
8111 12:27:02.419849 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8112 12:27:02.423352 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8113 12:27:02.429960 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8114 12:27:02.433186 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8115 12:27:02.436380 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8116 12:27:02.439762 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8117 12:27:02.443025 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8118 12:27:02.449522 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8119 12:27:02.453055 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8120 12:27:02.456448 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8121 12:27:02.459564 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8122 12:27:02.463369 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8123 12:27:02.469446 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8124 12:27:02.472677 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8125 12:27:02.476206 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8126 12:27:02.479409 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8127 12:27:02.479497 ==
8128 12:27:02.483019 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 12:27:02.489702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 12:27:02.489791 ==
8131 12:27:02.489859 DQS Delay:
8132 12:27:02.492602 DQS0 = 0, DQS1 = 0
8133 12:27:02.492688 DQM Delay:
8134 12:27:02.492757 DQM0 = 136, DQM1 = 126
8135 12:27:02.496329 DQ Delay:
8136 12:27:02.499204 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8137 12:27:02.502599 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8138 12:27:02.505927 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
8139 12:27:02.509267 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8140 12:27:02.509353
8141 12:27:02.509419
8142 12:27:02.509482 ==
8143 12:27:02.512609 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 12:27:02.515955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 12:27:02.519060 ==
8146 12:27:02.519146
8147 12:27:02.519213
8148 12:27:02.519275 TX Vref Scan disable
8149 12:27:02.522402 == TX Byte 0 ==
8150 12:27:02.526085 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8151 12:27:02.529366 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8152 12:27:02.532587 == TX Byte 1 ==
8153 12:27:02.535920 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8154 12:27:02.539182 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8155 12:27:02.542548 ==
8156 12:27:02.545851 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 12:27:02.548635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 12:27:02.548743 ==
8159 12:27:02.561607
8160 12:27:02.565020 TX Vref early break, caculate TX vref
8161 12:27:02.568514 TX Vref=16, minBit 1, minWin=23, winSum=389
8162 12:27:02.571697 TX Vref=18, minBit 0, minWin=24, winSum=399
8163 12:27:02.575119 TX Vref=20, minBit 0, minWin=24, winSum=407
8164 12:27:02.578412 TX Vref=22, minBit 8, minWin=24, winSum=420
8165 12:27:02.581658 TX Vref=24, minBit 0, minWin=26, winSum=426
8166 12:27:02.587998 TX Vref=26, minBit 0, minWin=25, winSum=426
8167 12:27:02.591421 TX Vref=28, minBit 2, minWin=25, winSum=430
8168 12:27:02.594689 TX Vref=30, minBit 0, minWin=25, winSum=418
8169 12:27:02.597994 TX Vref=32, minBit 1, minWin=24, winSum=409
8170 12:27:02.601333 TX Vref=34, minBit 2, minWin=23, winSum=402
8171 12:27:02.608066 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 24
8172 12:27:02.608178
8173 12:27:02.611502 Final TX Range 0 Vref 24
8174 12:27:02.611590
8175 12:27:02.611660 ==
8176 12:27:02.614415 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 12:27:02.617682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 12:27:02.617769 ==
8179 12:27:02.617837
8180 12:27:02.617899
8181 12:27:02.621070 TX Vref Scan disable
8182 12:27:02.627492 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8183 12:27:02.627579 == TX Byte 0 ==
8184 12:27:02.630837 u2DelayCellOfst[0]=10 cells (3 PI)
8185 12:27:02.634435 u2DelayCellOfst[1]=16 cells (5 PI)
8186 12:27:02.637624 u2DelayCellOfst[2]=10 cells (3 PI)
8187 12:27:02.640895 u2DelayCellOfst[3]=10 cells (3 PI)
8188 12:27:02.644171 u2DelayCellOfst[4]=6 cells (2 PI)
8189 12:27:02.647526 u2DelayCellOfst[5]=0 cells (0 PI)
8190 12:27:02.650806 u2DelayCellOfst[6]=16 cells (5 PI)
8191 12:27:02.654215 u2DelayCellOfst[7]=16 cells (5 PI)
8192 12:27:02.657456 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8193 12:27:02.660460 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8194 12:27:02.664010 == TX Byte 1 ==
8195 12:27:02.667195 u2DelayCellOfst[8]=0 cells (0 PI)
8196 12:27:02.670599 u2DelayCellOfst[9]=3 cells (1 PI)
8197 12:27:02.670684 u2DelayCellOfst[10]=6 cells (2 PI)
8198 12:27:02.674041 u2DelayCellOfst[11]=3 cells (1 PI)
8199 12:27:02.677438 u2DelayCellOfst[12]=13 cells (4 PI)
8200 12:27:02.680445 u2DelayCellOfst[13]=13 cells (4 PI)
8201 12:27:02.683616 u2DelayCellOfst[14]=16 cells (5 PI)
8202 12:27:02.687053 u2DelayCellOfst[15]=10 cells (3 PI)
8203 12:27:02.693539 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8204 12:27:02.696851 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8205 12:27:02.696965 DramC Write-DBI on
8206 12:27:02.697069 ==
8207 12:27:02.700184 Dram Type= 6, Freq= 0, CH_0, rank 1
8208 12:27:02.707187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8209 12:27:02.707305 ==
8210 12:27:02.707409
8211 12:27:02.707509
8212 12:27:02.707605 TX Vref Scan disable
8213 12:27:02.711071 == TX Byte 0 ==
8214 12:27:02.714516 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8215 12:27:02.717903 == TX Byte 1 ==
8216 12:27:02.720789 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8217 12:27:02.724529 DramC Write-DBI off
8218 12:27:02.724648
8219 12:27:02.724747 [DATLAT]
8220 12:27:02.724855 Freq=1600, CH0 RK1
8221 12:27:02.724953
8222 12:27:02.727609 DATLAT Default: 0xf
8223 12:27:02.731064 0, 0xFFFF, sum = 0
8224 12:27:02.731177 1, 0xFFFF, sum = 0
8225 12:27:02.734359 2, 0xFFFF, sum = 0
8226 12:27:02.734474 3, 0xFFFF, sum = 0
8227 12:27:02.737488 4, 0xFFFF, sum = 0
8228 12:27:02.737606 5, 0xFFFF, sum = 0
8229 12:27:02.740633 6, 0xFFFF, sum = 0
8230 12:27:02.740745 7, 0xFFFF, sum = 0
8231 12:27:02.744016 8, 0xFFFF, sum = 0
8232 12:27:02.744128 9, 0xFFFF, sum = 0
8233 12:27:02.747286 10, 0xFFFF, sum = 0
8234 12:27:02.747398 11, 0xFFFF, sum = 0
8235 12:27:02.750654 12, 0xFFFF, sum = 0
8236 12:27:02.750773 13, 0xFFFF, sum = 0
8237 12:27:02.753991 14, 0x0, sum = 1
8238 12:27:02.754109 15, 0x0, sum = 2
8239 12:27:02.757334 16, 0x0, sum = 3
8240 12:27:02.757449 17, 0x0, sum = 4
8241 12:27:02.760654 best_step = 15
8242 12:27:02.760776
8243 12:27:02.760881 ==
8244 12:27:02.763788 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 12:27:02.767104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 12:27:02.767226 ==
8247 12:27:02.770550 RX Vref Scan: 0
8248 12:27:02.770656
8249 12:27:02.770750 RX Vref 0 -> 0, step: 1
8250 12:27:02.770845
8251 12:27:02.773649 RX Delay 11 -> 252, step: 4
8252 12:27:02.780235 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8253 12:27:02.783578 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8254 12:27:02.786920 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8255 12:27:02.790023 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8256 12:27:02.793753 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8257 12:27:02.799872 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8258 12:27:02.803165 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8259 12:27:02.806865 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8260 12:27:02.810258 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8261 12:27:02.813602 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8262 12:27:02.819814 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8263 12:27:02.823129 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8264 12:27:02.826447 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8265 12:27:02.829794 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8266 12:27:02.832946 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8267 12:27:02.839797 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8268 12:27:02.839925 ==
8269 12:27:02.842891 Dram Type= 6, Freq= 0, CH_0, rank 1
8270 12:27:02.846475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8271 12:27:02.846581 ==
8272 12:27:02.846680 DQS Delay:
8273 12:27:02.849353 DQS0 = 0, DQS1 = 0
8274 12:27:02.849428 DQM Delay:
8275 12:27:02.852643 DQM0 = 133, DQM1 = 123
8276 12:27:02.852744 DQ Delay:
8277 12:27:02.856299 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8278 12:27:02.859631 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8279 12:27:02.862923 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8280 12:27:02.869482 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8281 12:27:02.869576
8282 12:27:02.869648
8283 12:27:02.869715
8284 12:27:02.869781 [DramC_TX_OE_Calibration] TA2
8285 12:27:02.872810 Original DQ_B0 (3 6) =30, OEN = 27
8286 12:27:02.876293 Original DQ_B1 (3 6) =30, OEN = 27
8287 12:27:02.879314 24, 0x0, End_B0=24 End_B1=24
8288 12:27:02.882462 25, 0x0, End_B0=25 End_B1=25
8289 12:27:02.886078 26, 0x0, End_B0=26 End_B1=26
8290 12:27:02.886169 27, 0x0, End_B0=27 End_B1=27
8291 12:27:02.889197 28, 0x0, End_B0=28 End_B1=28
8292 12:27:02.892471 29, 0x0, End_B0=29 End_B1=29
8293 12:27:02.895871 30, 0x0, End_B0=30 End_B1=30
8294 12:27:02.899069 31, 0x4141, End_B0=30 End_B1=30
8295 12:27:02.902873 Byte0 end_step=30 best_step=27
8296 12:27:02.902960 Byte1 end_step=30 best_step=27
8297 12:27:02.905695 Byte0 TX OE(2T, 0.5T) = (3, 3)
8298 12:27:02.909103 Byte1 TX OE(2T, 0.5T) = (3, 3)
8299 12:27:02.909190
8300 12:27:02.909257
8301 12:27:02.918892 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8302 12:27:02.918999 CH0 RK1: MR19=303, MR18=210F
8303 12:27:02.925556 CH0_RK1: MR19=0x303, MR18=0x210F, DQSOSC=393, MR23=63, INC=23, DEC=15
8304 12:27:02.928924 [RxdqsGatingPostProcess] freq 1600
8305 12:27:02.935694 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8306 12:27:02.938945 best DQS0 dly(2T, 0.5T) = (1, 1)
8307 12:27:02.942224 best DQS1 dly(2T, 0.5T) = (1, 1)
8308 12:27:02.945342 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8309 12:27:02.948989 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8310 12:27:02.949092 best DQS0 dly(2T, 0.5T) = (1, 1)
8311 12:27:02.952323 best DQS1 dly(2T, 0.5T) = (1, 1)
8312 12:27:02.955208 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8313 12:27:02.958459 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8314 12:27:02.962132 Pre-setting of DQS Precalculation
8315 12:27:02.968792 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8316 12:27:02.968873 ==
8317 12:27:02.971976 Dram Type= 6, Freq= 0, CH_1, rank 0
8318 12:27:02.975282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 12:27:02.975369 ==
8320 12:27:02.982006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8321 12:27:02.985264 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8322 12:27:02.988731 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8323 12:27:02.995053 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8324 12:27:03.004132 [CA 0] Center 40 (10~70) winsize 61
8325 12:27:03.007440 [CA 1] Center 41 (11~71) winsize 61
8326 12:27:03.010677 [CA 2] Center 36 (7~66) winsize 60
8327 12:27:03.013864 [CA 3] Center 36 (7~66) winsize 60
8328 12:27:03.017140 [CA 4] Center 36 (7~66) winsize 60
8329 12:27:03.020520 [CA 5] Center 36 (6~66) winsize 61
8330 12:27:03.020605
8331 12:27:03.023820 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8332 12:27:03.023895
8333 12:27:03.027308 [CATrainingPosCal] consider 1 rank data
8334 12:27:03.030434 u2DelayCellTimex100 = 290/100 ps
8335 12:27:03.037043 CA0 delay=40 (10~70),Diff = 4 PI (13 cell)
8336 12:27:03.040323 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8337 12:27:03.043729 CA2 delay=36 (7~66),Diff = 0 PI (0 cell)
8338 12:27:03.046924 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8339 12:27:03.050103 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8340 12:27:03.053737 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8341 12:27:03.053823
8342 12:27:03.056621 CA PerBit enable=1, Macro0, CA PI delay=36
8343 12:27:03.056732
8344 12:27:03.059932 [CBTSetCACLKResult] CA Dly = 36
8345 12:27:03.063254 CS Dly: 9 (0~40)
8346 12:27:03.066589 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8347 12:27:03.070222 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8348 12:27:03.070301 ==
8349 12:27:03.073414 Dram Type= 6, Freq= 0, CH_1, rank 1
8350 12:27:03.079898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 12:27:03.079989 ==
8352 12:27:03.083330 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8353 12:27:03.086645 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8354 12:27:03.093322 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8355 12:27:03.099549 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8356 12:27:03.107225 [CA 0] Center 42 (12~72) winsize 61
8357 12:27:03.110301 [CA 1] Center 42 (12~72) winsize 61
8358 12:27:03.113560 [CA 2] Center 37 (8~67) winsize 60
8359 12:27:03.116827 [CA 3] Center 37 (8~66) winsize 59
8360 12:27:03.120122 [CA 4] Center 37 (8~67) winsize 60
8361 12:27:03.123416 [CA 5] Center 36 (7~66) winsize 60
8362 12:27:03.123493
8363 12:27:03.126719 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8364 12:27:03.126803
8365 12:27:03.130051 [CATrainingPosCal] consider 2 rank data
8366 12:27:03.133710 u2DelayCellTimex100 = 290/100 ps
8367 12:27:03.139937 CA0 delay=41 (12~70),Diff = 5 PI (16 cell)
8368 12:27:03.143505 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8369 12:27:03.146809 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8370 12:27:03.149716 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8371 12:27:03.153052 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8372 12:27:03.156608 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8373 12:27:03.156688
8374 12:27:03.159917 CA PerBit enable=1, Macro0, CA PI delay=36
8375 12:27:03.160002
8376 12:27:03.163250 [CBTSetCACLKResult] CA Dly = 36
8377 12:27:03.166255 CS Dly: 10 (0~43)
8378 12:27:03.169455 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8379 12:27:03.172735 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8380 12:27:03.172833
8381 12:27:03.176408 ----->DramcWriteLeveling(PI) begin...
8382 12:27:03.176509 ==
8383 12:27:03.179680 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 12:27:03.186025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 12:27:03.186109 ==
8386 12:27:03.189440 Write leveling (Byte 0): 24 => 24
8387 12:27:03.192752 Write leveling (Byte 1): 27 => 27
8388 12:27:03.192856 DramcWriteLeveling(PI) end<-----
8389 12:27:03.195911
8390 12:27:03.195996 ==
8391 12:27:03.199212 Dram Type= 6, Freq= 0, CH_1, rank 0
8392 12:27:03.202436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8393 12:27:03.202511 ==
8394 12:27:03.206145 [Gating] SW mode calibration
8395 12:27:03.212421 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8396 12:27:03.215868 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8397 12:27:03.222301 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 12:27:03.225647 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 12:27:03.229041 1 4 8 | B1->B0 | 2929 3030 | 0 0 | (0 0) (0 0)
8400 12:27:03.235735 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 12:27:03.239116 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 12:27:03.242361 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 12:27:03.248652 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 12:27:03.252065 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 12:27:03.255475 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 12:27:03.262238 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8407 12:27:03.265585 1 5 8 | B1->B0 | 2b2b 2727 | 0 0 | (0 0) (1 0)
8408 12:27:03.268876 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8409 12:27:03.275323 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 12:27:03.278614 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 12:27:03.281807 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 12:27:03.288590 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 12:27:03.292019 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 12:27:03.295382 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8415 12:27:03.302000 1 6 8 | B1->B0 | 3c3b 4444 | 1 1 | (0 0) (0 0)
8416 12:27:03.305278 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 12:27:03.308335 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 12:27:03.314931 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 12:27:03.318428 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 12:27:03.321442 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 12:27:03.328375 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 12:27:03.331202 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8423 12:27:03.334522 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8424 12:27:03.341320 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8425 12:27:03.344669 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8426 12:27:03.347958 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 12:27:03.354844 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 12:27:03.358205 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 12:27:03.361427 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 12:27:03.367928 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 12:27:03.371294 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 12:27:03.374677 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 12:27:03.381300 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 12:27:03.384140 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 12:27:03.387901 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 12:27:03.394467 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 12:27:03.397816 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 12:27:03.401183 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8439 12:27:03.407717 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8440 12:27:03.410966 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8441 12:27:03.414104 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 12:27:03.417370 Total UI for P1: 0, mck2ui 16
8443 12:27:03.420816 best dqsien dly found for B0: ( 1, 9, 8)
8444 12:27:03.424423 Total UI for P1: 0, mck2ui 16
8445 12:27:03.427515 best dqsien dly found for B1: ( 1, 9, 10)
8446 12:27:03.430918 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8447 12:27:03.434208 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8448 12:27:03.434292
8449 12:27:03.440924 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8450 12:27:03.444188 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8451 12:27:03.444273 [Gating] SW calibration Done
8452 12:27:03.447434 ==
8453 12:27:03.450299 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 12:27:03.454080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 12:27:03.454166 ==
8456 12:27:03.454233 RX Vref Scan: 0
8457 12:27:03.454294
8458 12:27:03.457233 RX Vref 0 -> 0, step: 1
8459 12:27:03.457323
8460 12:27:03.460308 RX Delay 0 -> 252, step: 8
8461 12:27:03.463559 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8462 12:27:03.466849 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8463 12:27:03.470600 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8464 12:27:03.477232 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8465 12:27:03.480594 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8466 12:27:03.483538 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8467 12:27:03.486748 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8468 12:27:03.490087 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8469 12:27:03.496744 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8470 12:27:03.500145 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8471 12:27:03.503503 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8472 12:27:03.506865 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8473 12:27:03.510108 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8474 12:27:03.516665 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8475 12:27:03.519807 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8476 12:27:03.523060 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8477 12:27:03.523146 ==
8478 12:27:03.526649 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 12:27:03.529858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 12:27:03.533022 ==
8481 12:27:03.533107 DQS Delay:
8482 12:27:03.533174 DQS0 = 0, DQS1 = 0
8483 12:27:03.536648 DQM Delay:
8484 12:27:03.536732 DQM0 = 137, DQM1 = 130
8485 12:27:03.539691 DQ Delay:
8486 12:27:03.543042 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8487 12:27:03.546395 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8488 12:27:03.549779 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8489 12:27:03.553055 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8490 12:27:03.553168
8491 12:27:03.553263
8492 12:27:03.553340 ==
8493 12:27:03.556310 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 12:27:03.559550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 12:27:03.559678 ==
8496 12:27:03.562966
8497 12:27:03.563055
8498 12:27:03.563117 TX Vref Scan disable
8499 12:27:03.566212 == TX Byte 0 ==
8500 12:27:03.569640 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8501 12:27:03.572782 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8502 12:27:03.576060 == TX Byte 1 ==
8503 12:27:03.579318 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8504 12:27:03.582528 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8505 12:27:03.582611 ==
8506 12:27:03.585840 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 12:27:03.592478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 12:27:03.592560 ==
8509 12:27:03.602889
8510 12:27:03.606615 TX Vref early break, caculate TX vref
8511 12:27:03.609452 TX Vref=16, minBit 10, minWin=22, winSum=374
8512 12:27:03.612665 TX Vref=18, minBit 15, minWin=22, winSum=384
8513 12:27:03.616073 TX Vref=20, minBit 10, minWin=23, winSum=393
8514 12:27:03.619400 TX Vref=22, minBit 10, minWin=23, winSum=399
8515 12:27:03.626216 TX Vref=24, minBit 10, minWin=24, winSum=411
8516 12:27:03.629382 TX Vref=26, minBit 13, minWin=24, winSum=419
8517 12:27:03.632990 TX Vref=28, minBit 10, minWin=25, winSum=426
8518 12:27:03.635983 TX Vref=30, minBit 10, minWin=24, winSum=412
8519 12:27:03.639170 TX Vref=32, minBit 13, minWin=23, winSum=401
8520 12:27:03.646112 [TxChooseVref] Worse bit 10, Min win 25, Win sum 426, Final Vref 28
8521 12:27:03.646200
8522 12:27:03.649391 Final TX Range 0 Vref 28
8523 12:27:03.649475
8524 12:27:03.649541 ==
8525 12:27:03.652711 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 12:27:03.656017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 12:27:03.656104 ==
8528 12:27:03.656177
8529 12:27:03.656259
8530 12:27:03.659326 TX Vref Scan disable
8531 12:27:03.665900 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8532 12:27:03.666009 == TX Byte 0 ==
8533 12:27:03.668894 u2DelayCellOfst[0]=16 cells (5 PI)
8534 12:27:03.672231 u2DelayCellOfst[1]=10 cells (3 PI)
8535 12:27:03.675588 u2DelayCellOfst[2]=0 cells (0 PI)
8536 12:27:03.679025 u2DelayCellOfst[3]=3 cells (1 PI)
8537 12:27:03.682529 u2DelayCellOfst[4]=6 cells (2 PI)
8538 12:27:03.685241 u2DelayCellOfst[5]=16 cells (5 PI)
8539 12:27:03.688649 u2DelayCellOfst[6]=16 cells (5 PI)
8540 12:27:03.691996 u2DelayCellOfst[7]=6 cells (2 PI)
8541 12:27:03.695220 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8542 12:27:03.698540 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8543 12:27:03.701668 == TX Byte 1 ==
8544 12:27:03.705404 u2DelayCellOfst[8]=0 cells (0 PI)
8545 12:27:03.708655 u2DelayCellOfst[9]=3 cells (1 PI)
8546 12:27:03.711902 u2DelayCellOfst[10]=10 cells (3 PI)
8547 12:27:03.711980 u2DelayCellOfst[11]=3 cells (1 PI)
8548 12:27:03.715322 u2DelayCellOfst[12]=13 cells (4 PI)
8549 12:27:03.718240 u2DelayCellOfst[13]=16 cells (5 PI)
8550 12:27:03.721964 u2DelayCellOfst[14]=16 cells (5 PI)
8551 12:27:03.724862 u2DelayCellOfst[15]=16 cells (5 PI)
8552 12:27:03.731694 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8553 12:27:03.734804 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8554 12:27:03.734914 DramC Write-DBI on
8555 12:27:03.738379 ==
8556 12:27:03.738465 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 12:27:03.744942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 12:27:03.745038 ==
8559 12:27:03.745107
8560 12:27:03.745171
8561 12:27:03.748309 TX Vref Scan disable
8562 12:27:03.748399 == TX Byte 0 ==
8563 12:27:03.754694 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8564 12:27:03.754781 == TX Byte 1 ==
8565 12:27:03.757934 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8566 12:27:03.761133 DramC Write-DBI off
8567 12:27:03.761221
8568 12:27:03.761288 [DATLAT]
8569 12:27:03.764397 Freq=1600, CH1 RK0
8570 12:27:03.764483
8571 12:27:03.764550 DATLAT Default: 0xf
8572 12:27:03.767663 0, 0xFFFF, sum = 0
8573 12:27:03.767752 1, 0xFFFF, sum = 0
8574 12:27:03.771015 2, 0xFFFF, sum = 0
8575 12:27:03.771103 3, 0xFFFF, sum = 0
8576 12:27:03.774605 4, 0xFFFF, sum = 0
8577 12:27:03.774696 5, 0xFFFF, sum = 0
8578 12:27:03.777910 6, 0xFFFF, sum = 0
8579 12:27:03.781120 7, 0xFFFF, sum = 0
8580 12:27:03.781204 8, 0xFFFF, sum = 0
8581 12:27:03.784283 9, 0xFFFF, sum = 0
8582 12:27:03.784364 10, 0xFFFF, sum = 0
8583 12:27:03.787568 11, 0xFFFF, sum = 0
8584 12:27:03.787681 12, 0xFFFF, sum = 0
8585 12:27:03.790911 13, 0xFFFF, sum = 0
8586 12:27:03.791038 14, 0x0, sum = 1
8587 12:27:03.794315 15, 0x0, sum = 2
8588 12:27:03.794419 16, 0x0, sum = 3
8589 12:27:03.797668 17, 0x0, sum = 4
8590 12:27:03.797762 best_step = 15
8591 12:27:03.797844
8592 12:27:03.797938 ==
8593 12:27:03.801075 Dram Type= 6, Freq= 0, CH_1, rank 0
8594 12:27:03.804356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8595 12:27:03.807613 ==
8596 12:27:03.807740 RX Vref Scan: 1
8597 12:27:03.807845
8598 12:27:03.810924 Set Vref Range= 24 -> 127
8599 12:27:03.811053
8600 12:27:03.811160 RX Vref 24 -> 127, step: 1
8601 12:27:03.814029
8602 12:27:03.814115 RX Delay 19 -> 252, step: 4
8603 12:27:03.814211
8604 12:27:03.817384 Set Vref, RX VrefLevel [Byte0]: 24
8605 12:27:03.820705 [Byte1]: 24
8606 12:27:03.824240
8607 12:27:03.824348 Set Vref, RX VrefLevel [Byte0]: 25
8608 12:27:03.827739 [Byte1]: 25
8609 12:27:03.831768
8610 12:27:03.831855 Set Vref, RX VrefLevel [Byte0]: 26
8611 12:27:03.835099 [Byte1]: 26
8612 12:27:03.839894
8613 12:27:03.839980 Set Vref, RX VrefLevel [Byte0]: 27
8614 12:27:03.842651 [Byte1]: 27
8615 12:27:03.847159
8616 12:27:03.847244 Set Vref, RX VrefLevel [Byte0]: 28
8617 12:27:03.850378 [Byte1]: 28
8618 12:27:03.854629
8619 12:27:03.854714 Set Vref, RX VrefLevel [Byte0]: 29
8620 12:27:03.858212 [Byte1]: 29
8621 12:27:03.862174
8622 12:27:03.862259 Set Vref, RX VrefLevel [Byte0]: 30
8623 12:27:03.865556 [Byte1]: 30
8624 12:27:03.869826
8625 12:27:03.869911 Set Vref, RX VrefLevel [Byte0]: 31
8626 12:27:03.873346 [Byte1]: 31
8627 12:27:03.877366
8628 12:27:03.877450 Set Vref, RX VrefLevel [Byte0]: 32
8629 12:27:03.880759 [Byte1]: 32
8630 12:27:03.885058
8631 12:27:03.885143 Set Vref, RX VrefLevel [Byte0]: 33
8632 12:27:03.888331 [Byte1]: 33
8633 12:27:03.892656
8634 12:27:03.892774 Set Vref, RX VrefLevel [Byte0]: 34
8635 12:27:03.896127 [Byte1]: 34
8636 12:27:03.899970
8637 12:27:03.900065 Set Vref, RX VrefLevel [Byte0]: 35
8638 12:27:03.903461 [Byte1]: 35
8639 12:27:03.907703
8640 12:27:03.907786 Set Vref, RX VrefLevel [Byte0]: 36
8641 12:27:03.910902 [Byte1]: 36
8642 12:27:03.915077
8643 12:27:03.915161 Set Vref, RX VrefLevel [Byte0]: 37
8644 12:27:03.918553 [Byte1]: 37
8645 12:27:03.923016
8646 12:27:03.923099 Set Vref, RX VrefLevel [Byte0]: 38
8647 12:27:03.926332 [Byte1]: 38
8648 12:27:03.930633
8649 12:27:03.930716 Set Vref, RX VrefLevel [Byte0]: 39
8650 12:27:03.933567 [Byte1]: 39
8651 12:27:03.937979
8652 12:27:03.938063 Set Vref, RX VrefLevel [Byte0]: 40
8653 12:27:03.941261 [Byte1]: 40
8654 12:27:03.945515
8655 12:27:03.945601 Set Vref, RX VrefLevel [Byte0]: 41
8656 12:27:03.948705 [Byte1]: 41
8657 12:27:03.953061
8658 12:27:03.953171 Set Vref, RX VrefLevel [Byte0]: 42
8659 12:27:03.956315 [Byte1]: 42
8660 12:27:03.960645
8661 12:27:03.960756 Set Vref, RX VrefLevel [Byte0]: 43
8662 12:27:03.963769 [Byte1]: 43
8663 12:27:03.968165
8664 12:27:03.968274 Set Vref, RX VrefLevel [Byte0]: 44
8665 12:27:03.971502 [Byte1]: 44
8666 12:27:03.975853
8667 12:27:03.975935 Set Vref, RX VrefLevel [Byte0]: 45
8668 12:27:03.979043 [Byte1]: 45
8669 12:27:03.983252
8670 12:27:03.983336 Set Vref, RX VrefLevel [Byte0]: 46
8671 12:27:03.986572 [Byte1]: 46
8672 12:27:03.990803
8673 12:27:03.990919 Set Vref, RX VrefLevel [Byte0]: 47
8674 12:27:03.994189 [Byte1]: 47
8675 12:27:03.998725
8676 12:27:03.998808 Set Vref, RX VrefLevel [Byte0]: 48
8677 12:27:04.001678 [Byte1]: 48
8678 12:27:04.006195
8679 12:27:04.006278 Set Vref, RX VrefLevel [Byte0]: 49
8680 12:27:04.009597 [Byte1]: 49
8681 12:27:04.013828
8682 12:27:04.013911 Set Vref, RX VrefLevel [Byte0]: 50
8683 12:27:04.017046 [Byte1]: 50
8684 12:27:04.021574
8685 12:27:04.021658 Set Vref, RX VrefLevel [Byte0]: 51
8686 12:27:04.024393 [Byte1]: 51
8687 12:27:04.028752
8688 12:27:04.028873 Set Vref, RX VrefLevel [Byte0]: 52
8689 12:27:04.032343 [Byte1]: 52
8690 12:27:04.036621
8691 12:27:04.036731 Set Vref, RX VrefLevel [Byte0]: 53
8692 12:27:04.039619 [Byte1]: 53
8693 12:27:04.044069
8694 12:27:04.044152 Set Vref, RX VrefLevel [Byte0]: 54
8695 12:27:04.047278 [Byte1]: 54
8696 12:27:04.051507
8697 12:27:04.051590 Set Vref, RX VrefLevel [Byte0]: 55
8698 12:27:04.054806 [Byte1]: 55
8699 12:27:04.059130
8700 12:27:04.059214 Set Vref, RX VrefLevel [Byte0]: 56
8701 12:27:04.065452 [Byte1]: 56
8702 12:27:04.065536
8703 12:27:04.068999 Set Vref, RX VrefLevel [Byte0]: 57
8704 12:27:04.072190 [Byte1]: 57
8705 12:27:04.072324
8706 12:27:04.075517 Set Vref, RX VrefLevel [Byte0]: 58
8707 12:27:04.078570 [Byte1]: 58
8708 12:27:04.078649
8709 12:27:04.081979 Set Vref, RX VrefLevel [Byte0]: 59
8710 12:27:04.085074 [Byte1]: 59
8711 12:27:04.089409
8712 12:27:04.089495 Set Vref, RX VrefLevel [Byte0]: 60
8713 12:27:04.092699 [Byte1]: 60
8714 12:27:04.096949
8715 12:27:04.097033 Set Vref, RX VrefLevel [Byte0]: 61
8716 12:27:04.100393 [Byte1]: 61
8717 12:27:04.104411
8718 12:27:04.104494 Set Vref, RX VrefLevel [Byte0]: 62
8719 12:27:04.107795 [Byte1]: 62
8720 12:27:04.112302
8721 12:27:04.112388 Set Vref, RX VrefLevel [Byte0]: 63
8722 12:27:04.115493 [Byte1]: 63
8723 12:27:04.119728
8724 12:27:04.119802 Set Vref, RX VrefLevel [Byte0]: 64
8725 12:27:04.122695 [Byte1]: 64
8726 12:27:04.127147
8727 12:27:04.127218 Set Vref, RX VrefLevel [Byte0]: 65
8728 12:27:04.130643 [Byte1]: 65
8729 12:27:04.134609
8730 12:27:04.134693 Set Vref, RX VrefLevel [Byte0]: 66
8731 12:27:04.138122 [Byte1]: 66
8732 12:27:04.142593
8733 12:27:04.142676 Set Vref, RX VrefLevel [Byte0]: 67
8734 12:27:04.145521 [Byte1]: 67
8735 12:27:04.149748
8736 12:27:04.149832 Set Vref, RX VrefLevel [Byte0]: 68
8737 12:27:04.153115 [Byte1]: 68
8738 12:27:04.157778
8739 12:27:04.157861 Set Vref, RX VrefLevel [Byte0]: 69
8740 12:27:04.160628 [Byte1]: 69
8741 12:27:04.164904
8742 12:27:04.164988 Set Vref, RX VrefLevel [Byte0]: 70
8743 12:27:04.168222 [Byte1]: 70
8744 12:27:04.172433
8745 12:27:04.172533 Set Vref, RX VrefLevel [Byte0]: 71
8746 12:27:04.176018 [Byte1]: 71
8747 12:27:04.180016
8748 12:27:04.180110 Set Vref, RX VrefLevel [Byte0]: 72
8749 12:27:04.183512 [Byte1]: 72
8750 12:27:04.187780
8751 12:27:04.187864 Set Vref, RX VrefLevel [Byte0]: 73
8752 12:27:04.190955 [Byte1]: 73
8753 12:27:04.195260
8754 12:27:04.195354 Set Vref, RX VrefLevel [Byte0]: 74
8755 12:27:04.198693 [Byte1]: 74
8756 12:27:04.202909
8757 12:27:04.202993 Set Vref, RX VrefLevel [Byte0]: 75
8758 12:27:04.206328 [Byte1]: 75
8759 12:27:04.210738
8760 12:27:04.210822 Final RX Vref Byte 0 = 57 to rank0
8761 12:27:04.213728 Final RX Vref Byte 1 = 66 to rank0
8762 12:27:04.217597 Final RX Vref Byte 0 = 57 to rank1
8763 12:27:04.220485 Final RX Vref Byte 1 = 66 to rank1==
8764 12:27:04.223674 Dram Type= 6, Freq= 0, CH_1, rank 0
8765 12:27:04.230626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8766 12:27:04.230711 ==
8767 12:27:04.230778 DQS Delay:
8768 12:27:04.230843 DQS0 = 0, DQS1 = 0
8769 12:27:04.234045 DQM Delay:
8770 12:27:04.234132 DQM0 = 134, DQM1 = 129
8771 12:27:04.237454 DQ Delay:
8772 12:27:04.240331 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8773 12:27:04.243705 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
8774 12:27:04.247185 DQ8 =116, DQ9 =118, DQ10 =134, DQ11 =122
8775 12:27:04.250639 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8776 12:27:04.250724
8777 12:27:04.250790
8778 12:27:04.250851
8779 12:27:04.253567 [DramC_TX_OE_Calibration] TA2
8780 12:27:04.257070 Original DQ_B0 (3 6) =30, OEN = 27
8781 12:27:04.260406 Original DQ_B1 (3 6) =30, OEN = 27
8782 12:27:04.263469 24, 0x0, End_B0=24 End_B1=24
8783 12:27:04.263556 25, 0x0, End_B0=25 End_B1=25
8784 12:27:04.266761 26, 0x0, End_B0=26 End_B1=26
8785 12:27:04.270369 27, 0x0, End_B0=27 End_B1=27
8786 12:27:04.273449 28, 0x0, End_B0=28 End_B1=28
8787 12:27:04.276713 29, 0x0, End_B0=29 End_B1=29
8788 12:27:04.276837 30, 0x0, End_B0=30 End_B1=30
8789 12:27:04.280047 31, 0x4141, End_B0=30 End_B1=30
8790 12:27:04.283403 Byte0 end_step=30 best_step=27
8791 12:27:04.286807 Byte1 end_step=30 best_step=27
8792 12:27:04.290014 Byte0 TX OE(2T, 0.5T) = (3, 3)
8793 12:27:04.293200 Byte1 TX OE(2T, 0.5T) = (3, 3)
8794 12:27:04.293284
8795 12:27:04.293351
8796 12:27:04.299699 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8797 12:27:04.303514 CH1 RK0: MR19=303, MR18=1927
8798 12:27:04.309640 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8799 12:27:04.309725
8800 12:27:04.313078 ----->DramcWriteLeveling(PI) begin...
8801 12:27:04.313164 ==
8802 12:27:04.316530 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 12:27:04.319811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 12:27:04.319896 ==
8805 12:27:04.323209 Write leveling (Byte 0): 24 => 24
8806 12:27:04.326618 Write leveling (Byte 1): 29 => 29
8807 12:27:04.329775 DramcWriteLeveling(PI) end<-----
8808 12:27:04.329859
8809 12:27:04.329925 ==
8810 12:27:04.332689 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 12:27:04.336294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 12:27:04.336378 ==
8813 12:27:04.339683 [Gating] SW mode calibration
8814 12:27:04.346477 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8815 12:27:04.352769 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8816 12:27:04.356353 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 12:27:04.362673 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 12:27:04.365971 1 4 8 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
8819 12:27:04.369191 1 4 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
8820 12:27:04.375732 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 12:27:04.379021 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8822 12:27:04.382288 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 12:27:04.389139 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8824 12:27:04.392337 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 12:27:04.395817 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 12:27:04.402192 1 5 8 | B1->B0 | 2323 3434 | 0 1 | (1 0) (1 0)
8827 12:27:04.405404 1 5 12 | B1->B0 | 2323 2f2f | 0 1 | (1 0) (1 0)
8828 12:27:04.409106 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 12:27:04.415561 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 12:27:04.418880 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 12:27:04.422243 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 12:27:04.428786 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 12:27:04.431975 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8834 12:27:04.435420 1 6 8 | B1->B0 | 4444 2424 | 0 0 | (0 0) (0 0)
8835 12:27:04.441793 1 6 12 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
8836 12:27:04.445141 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 12:27:04.448636 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 12:27:04.455105 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 12:27:04.458576 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 12:27:04.461902 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 12:27:04.468271 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 12:27:04.471678 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8843 12:27:04.474812 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8844 12:27:04.481177 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 12:27:04.484757 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 12:27:04.487951 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 12:27:04.494422 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 12:27:04.498175 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 12:27:04.501136 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 12:27:04.507623 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 12:27:04.510943 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 12:27:04.514300 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 12:27:04.521107 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 12:27:04.524395 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 12:27:04.527698 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 12:27:04.534189 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 12:27:04.537317 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 12:27:04.540759 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8859 12:27:04.547248 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8860 12:27:04.550808 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8861 12:27:04.553756 Total UI for P1: 0, mck2ui 16
8862 12:27:04.557193 best dqsien dly found for B0: ( 1, 9, 10)
8863 12:27:04.560500 Total UI for P1: 0, mck2ui 16
8864 12:27:04.563982 best dqsien dly found for B1: ( 1, 9, 10)
8865 12:27:04.566969 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8866 12:27:04.570438 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8867 12:27:04.570523
8868 12:27:04.573837 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8869 12:27:04.577249 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8870 12:27:04.580347 [Gating] SW calibration Done
8871 12:27:04.580444 ==
8872 12:27:04.583808 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 12:27:04.590221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 12:27:04.590306 ==
8875 12:27:04.590372 RX Vref Scan: 0
8876 12:27:04.590434
8877 12:27:04.593532 RX Vref 0 -> 0, step: 1
8878 12:27:04.593614
8879 12:27:04.596670 RX Delay 0 -> 252, step: 8
8880 12:27:04.600105 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8881 12:27:04.603305 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8882 12:27:04.606616 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8883 12:27:04.610323 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8884 12:27:04.616555 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8885 12:27:04.619917 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8886 12:27:04.623349 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8887 12:27:04.626661 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8888 12:27:04.629664 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8889 12:27:04.636362 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8890 12:27:04.639729 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8891 12:27:04.643008 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8892 12:27:04.646347 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8893 12:27:04.649812 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8894 12:27:04.656074 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8895 12:27:04.659436 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8896 12:27:04.659520 ==
8897 12:27:04.662855 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 12:27:04.666215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 12:27:04.666298 ==
8900 12:27:04.669656 DQS Delay:
8901 12:27:04.669739 DQS0 = 0, DQS1 = 0
8902 12:27:04.672571 DQM Delay:
8903 12:27:04.672653 DQM0 = 136, DQM1 = 131
8904 12:27:04.672718 DQ Delay:
8905 12:27:04.675939 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8906 12:27:04.682732 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =135
8907 12:27:04.686079 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =123
8908 12:27:04.689328 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8909 12:27:04.689444
8910 12:27:04.689542
8911 12:27:04.689633 ==
8912 12:27:04.692392 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 12:27:04.695659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 12:27:04.695768 ==
8915 12:27:04.695863
8916 12:27:04.695953
8917 12:27:04.699442 TX Vref Scan disable
8918 12:27:04.702517 == TX Byte 0 ==
8919 12:27:04.705638 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8920 12:27:04.708735 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8921 12:27:04.712558 == TX Byte 1 ==
8922 12:27:04.715780 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8923 12:27:04.718886 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8924 12:27:04.718995 ==
8925 12:27:04.722561 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 12:27:04.725570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 12:27:04.728941 ==
8928 12:27:04.740548
8929 12:27:04.743393 TX Vref early break, caculate TX vref
8930 12:27:04.746655 TX Vref=16, minBit 9, minWin=22, winSum=379
8931 12:27:04.750020 TX Vref=18, minBit 9, minWin=21, winSum=384
8932 12:27:04.753411 TX Vref=20, minBit 9, minWin=23, winSum=398
8933 12:27:04.756794 TX Vref=22, minBit 9, minWin=23, winSum=406
8934 12:27:04.760234 TX Vref=24, minBit 9, minWin=24, winSum=412
8935 12:27:04.766489 TX Vref=26, minBit 12, minWin=24, winSum=417
8936 12:27:04.769972 TX Vref=28, minBit 10, minWin=24, winSum=413
8937 12:27:04.773379 TX Vref=30, minBit 8, minWin=24, winSum=407
8938 12:27:04.776695 TX Vref=32, minBit 10, minWin=23, winSum=397
8939 12:27:04.780028 TX Vref=34, minBit 10, minWin=22, winSum=392
8940 12:27:04.786462 [TxChooseVref] Worse bit 12, Min win 24, Win sum 417, Final Vref 26
8941 12:27:04.786547
8942 12:27:04.789743 Final TX Range 0 Vref 26
8943 12:27:04.789855
8944 12:27:04.789952 ==
8945 12:27:04.793115 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 12:27:04.796223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 12:27:04.796325 ==
8948 12:27:04.796417
8949 12:27:04.799732
8950 12:27:04.799834 TX Vref Scan disable
8951 12:27:04.806079 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8952 12:27:04.806163 == TX Byte 0 ==
8953 12:27:04.809304 u2DelayCellOfst[0]=13 cells (4 PI)
8954 12:27:04.812987 u2DelayCellOfst[1]=10 cells (3 PI)
8955 12:27:04.816043 u2DelayCellOfst[2]=0 cells (0 PI)
8956 12:27:04.819332 u2DelayCellOfst[3]=3 cells (1 PI)
8957 12:27:04.822895 u2DelayCellOfst[4]=6 cells (2 PI)
8958 12:27:04.826012 u2DelayCellOfst[5]=16 cells (5 PI)
8959 12:27:04.829575 u2DelayCellOfst[6]=16 cells (5 PI)
8960 12:27:04.832540 u2DelayCellOfst[7]=3 cells (1 PI)
8961 12:27:04.836041 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8962 12:27:04.839319 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8963 12:27:04.842250 == TX Byte 1 ==
8964 12:27:04.845621 u2DelayCellOfst[8]=0 cells (0 PI)
8965 12:27:04.849293 u2DelayCellOfst[9]=3 cells (1 PI)
8966 12:27:04.852287 u2DelayCellOfst[10]=6 cells (2 PI)
8967 12:27:04.855631 u2DelayCellOfst[11]=3 cells (1 PI)
8968 12:27:04.858659 u2DelayCellOfst[12]=10 cells (3 PI)
8969 12:27:04.858743 u2DelayCellOfst[13]=16 cells (5 PI)
8970 12:27:04.862078 u2DelayCellOfst[14]=16 cells (5 PI)
8971 12:27:04.865464 u2DelayCellOfst[15]=16 cells (5 PI)
8972 12:27:04.872232 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8973 12:27:04.875111 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8974 12:27:04.875195 DramC Write-DBI on
8975 12:27:04.878687 ==
8976 12:27:04.882077 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 12:27:04.885091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 12:27:04.885164 ==
8979 12:27:04.885227
8980 12:27:04.885289
8981 12:27:04.888420 TX Vref Scan disable
8982 12:27:04.888491 == TX Byte 0 ==
8983 12:27:04.894863 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8984 12:27:04.894943 == TX Byte 1 ==
8985 12:27:04.898185 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8986 12:27:04.901878 DramC Write-DBI off
8987 12:27:04.901957
8988 12:27:04.902021 [DATLAT]
8989 12:27:04.905114 Freq=1600, CH1 RK1
8990 12:27:04.905203
8991 12:27:04.905266 DATLAT Default: 0xf
8992 12:27:04.908214 0, 0xFFFF, sum = 0
8993 12:27:04.908287 1, 0xFFFF, sum = 0
8994 12:27:04.911776 2, 0xFFFF, sum = 0
8995 12:27:04.911854 3, 0xFFFF, sum = 0
8996 12:27:04.914884 4, 0xFFFF, sum = 0
8997 12:27:04.914984 5, 0xFFFF, sum = 0
8998 12:27:04.918388 6, 0xFFFF, sum = 0
8999 12:27:04.921493 7, 0xFFFF, sum = 0
9000 12:27:04.921572 8, 0xFFFF, sum = 0
9001 12:27:04.924718 9, 0xFFFF, sum = 0
9002 12:27:04.924850 10, 0xFFFF, sum = 0
9003 12:27:04.928276 11, 0xFFFF, sum = 0
9004 12:27:04.928356 12, 0xFFFF, sum = 0
9005 12:27:04.931514 13, 0xFFFF, sum = 0
9006 12:27:04.931590 14, 0x0, sum = 1
9007 12:27:04.934776 15, 0x0, sum = 2
9008 12:27:04.934866 16, 0x0, sum = 3
9009 12:27:04.937997 17, 0x0, sum = 4
9010 12:27:04.938075 best_step = 15
9011 12:27:04.938139
9012 12:27:04.938202 ==
9013 12:27:04.941367 Dram Type= 6, Freq= 0, CH_1, rank 1
9014 12:27:04.944809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9015 12:27:04.947877 ==
9016 12:27:04.947952 RX Vref Scan: 0
9017 12:27:04.948018
9018 12:27:04.951127 RX Vref 0 -> 0, step: 1
9019 12:27:04.951211
9020 12:27:04.951272 RX Delay 19 -> 252, step: 4
9021 12:27:04.958400 iDelay=191, Bit 0, Center 136 (91 ~ 182) 92
9022 12:27:04.961745 iDelay=191, Bit 1, Center 130 (83 ~ 178) 96
9023 12:27:04.965212 iDelay=191, Bit 2, Center 120 (71 ~ 170) 100
9024 12:27:04.968159 iDelay=191, Bit 3, Center 132 (83 ~ 182) 100
9025 12:27:04.971459 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
9026 12:27:04.978279 iDelay=191, Bit 5, Center 144 (99 ~ 190) 92
9027 12:27:04.981670 iDelay=191, Bit 6, Center 142 (95 ~ 190) 96
9028 12:27:04.985194 iDelay=191, Bit 7, Center 130 (83 ~ 178) 96
9029 12:27:04.988057 iDelay=191, Bit 8, Center 114 (67 ~ 162) 96
9030 12:27:04.991471 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
9031 12:27:04.997855 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
9032 12:27:05.001266 iDelay=191, Bit 11, Center 124 (71 ~ 178) 108
9033 12:27:05.004652 iDelay=191, Bit 12, Center 138 (87 ~ 190) 104
9034 12:27:05.007951 iDelay=191, Bit 13, Center 138 (87 ~ 190) 104
9035 12:27:05.011232 iDelay=191, Bit 14, Center 138 (91 ~ 186) 96
9036 12:27:05.017929 iDelay=191, Bit 15, Center 138 (87 ~ 190) 104
9037 12:27:05.018018 ==
9038 12:27:05.021029 Dram Type= 6, Freq= 0, CH_1, rank 1
9039 12:27:05.024333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9040 12:27:05.024440 ==
9041 12:27:05.024505 DQS Delay:
9042 12:27:05.027741 DQS0 = 0, DQS1 = 0
9043 12:27:05.027822 DQM Delay:
9044 12:27:05.031061 DQM0 = 133, DQM1 = 129
9045 12:27:05.031139 DQ Delay:
9046 12:27:05.034228 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9047 12:27:05.037416 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
9048 12:27:05.040670 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =124
9049 12:27:05.047492 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
9050 12:27:05.047622
9051 12:27:05.047688
9052 12:27:05.047783
9053 12:27:05.050475 [DramC_TX_OE_Calibration] TA2
9054 12:27:05.050558 Original DQ_B0 (3 6) =30, OEN = 27
9055 12:27:05.053857 Original DQ_B1 (3 6) =30, OEN = 27
9056 12:27:05.057049 24, 0x0, End_B0=24 End_B1=24
9057 12:27:05.060861 25, 0x0, End_B0=25 End_B1=25
9058 12:27:05.064246 26, 0x0, End_B0=26 End_B1=26
9059 12:27:05.067162 27, 0x0, End_B0=27 End_B1=27
9060 12:27:05.067253 28, 0x0, End_B0=28 End_B1=28
9061 12:27:05.070632 29, 0x0, End_B0=29 End_B1=29
9062 12:27:05.074075 30, 0x0, End_B0=30 End_B1=30
9063 12:27:05.077058 31, 0x4545, End_B0=30 End_B1=30
9064 12:27:05.080629 Byte0 end_step=30 best_step=27
9065 12:27:05.080703 Byte1 end_step=30 best_step=27
9066 12:27:05.084105 Byte0 TX OE(2T, 0.5T) = (3, 3)
9067 12:27:05.087073 Byte1 TX OE(2T, 0.5T) = (3, 3)
9068 12:27:05.087156
9069 12:27:05.087223
9070 12:27:05.097322 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
9071 12:27:05.097407 CH1 RK1: MR19=303, MR18=1B06
9072 12:27:05.103691 CH1_RK1: MR19=0x303, MR18=0x1B06, DQSOSC=396, MR23=63, INC=23, DEC=15
9073 12:27:05.107201 [RxdqsGatingPostProcess] freq 1600
9074 12:27:05.113745 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9075 12:27:05.117124 best DQS0 dly(2T, 0.5T) = (1, 1)
9076 12:27:05.120273 best DQS1 dly(2T, 0.5T) = (1, 1)
9077 12:27:05.123491 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9078 12:27:05.126739 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9079 12:27:05.130005 best DQS0 dly(2T, 0.5T) = (1, 1)
9080 12:27:05.130091 best DQS1 dly(2T, 0.5T) = (1, 1)
9081 12:27:05.133480 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9082 12:27:05.136733 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9083 12:27:05.140043 Pre-setting of DQS Precalculation
9084 12:27:05.146501 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9085 12:27:05.152982 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9086 12:27:05.159685 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9087 12:27:05.159803
9088 12:27:05.159886
9089 12:27:05.162920 [Calibration Summary] 3200 Mbps
9090 12:27:05.166403 CH 0, Rank 0
9091 12:27:05.166513 SW Impedance : PASS
9092 12:27:05.169754 DUTY Scan : NO K
9093 12:27:05.169864 ZQ Calibration : PASS
9094 12:27:05.172736 Jitter Meter : NO K
9095 12:27:05.176102 CBT Training : PASS
9096 12:27:05.176180 Write leveling : PASS
9097 12:27:05.179532 RX DQS gating : PASS
9098 12:27:05.182964 RX DQ/DQS(RDDQC) : PASS
9099 12:27:05.183039 TX DQ/DQS : PASS
9100 12:27:05.185940 RX DATLAT : PASS
9101 12:27:05.189412 RX DQ/DQS(Engine): PASS
9102 12:27:05.189489 TX OE : PASS
9103 12:27:05.192684 All Pass.
9104 12:27:05.192754
9105 12:27:05.192826 CH 0, Rank 1
9106 12:27:05.196255 SW Impedance : PASS
9107 12:27:05.196340 DUTY Scan : NO K
9108 12:27:05.199510 ZQ Calibration : PASS
9109 12:27:05.202489 Jitter Meter : NO K
9110 12:27:05.202566 CBT Training : PASS
9111 12:27:05.205937 Write leveling : PASS
9112 12:27:05.209300 RX DQS gating : PASS
9113 12:27:05.209384 RX DQ/DQS(RDDQC) : PASS
9114 12:27:05.212687 TX DQ/DQS : PASS
9115 12:27:05.215788 RX DATLAT : PASS
9116 12:27:05.215899 RX DQ/DQS(Engine): PASS
9117 12:27:05.219138 TX OE : PASS
9118 12:27:05.219222 All Pass.
9119 12:27:05.219288
9120 12:27:05.222606 CH 1, Rank 0
9121 12:27:05.222688 SW Impedance : PASS
9122 12:27:05.225894 DUTY Scan : NO K
9123 12:27:05.229032 ZQ Calibration : PASS
9124 12:27:05.229116 Jitter Meter : NO K
9125 12:27:05.232307 CBT Training : PASS
9126 12:27:05.235398 Write leveling : PASS
9127 12:27:05.235527 RX DQS gating : PASS
9128 12:27:05.238952 RX DQ/DQS(RDDQC) : PASS
9129 12:27:05.241777 TX DQ/DQS : PASS
9130 12:27:05.241861 RX DATLAT : PASS
9131 12:27:05.245464 RX DQ/DQS(Engine): PASS
9132 12:27:05.248529 TX OE : PASS
9133 12:27:05.248634 All Pass.
9134 12:27:05.248701
9135 12:27:05.248770 CH 1, Rank 1
9136 12:27:05.251764 SW Impedance : PASS
9137 12:27:05.255119 DUTY Scan : NO K
9138 12:27:05.255202 ZQ Calibration : PASS
9139 12:27:05.258596 Jitter Meter : NO K
9140 12:27:05.258679 CBT Training : PASS
9141 12:27:05.261659 Write leveling : PASS
9142 12:27:05.265253 RX DQS gating : PASS
9143 12:27:05.265386 RX DQ/DQS(RDDQC) : PASS
9144 12:27:05.268611 TX DQ/DQS : PASS
9145 12:27:05.271528 RX DATLAT : PASS
9146 12:27:05.271638 RX DQ/DQS(Engine): PASS
9147 12:27:05.274961 TX OE : PASS
9148 12:27:05.275061 All Pass.
9149 12:27:05.275151
9150 12:27:05.278262 DramC Write-DBI on
9151 12:27:05.281617 PER_BANK_REFRESH: Hybrid Mode
9152 12:27:05.281711 TX_TRACKING: ON
9153 12:27:05.291509 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9154 12:27:05.298106 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9155 12:27:05.304450 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9156 12:27:05.311274 [FAST_K] Save calibration result to emmc
9157 12:27:05.311374 sync common calibartion params.
9158 12:27:05.314666 sync cbt_mode0:1, 1:1
9159 12:27:05.317995 dram_init: ddr_geometry: 2
9160 12:27:05.318084 dram_init: ddr_geometry: 2
9161 12:27:05.321102 dram_init: ddr_geometry: 2
9162 12:27:05.324444 0:dram_rank_size:100000000
9163 12:27:05.327905 1:dram_rank_size:100000000
9164 12:27:05.331086 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9165 12:27:05.334386 DFS_SHUFFLE_HW_MODE: ON
9166 12:27:05.337901 dramc_set_vcore_voltage set vcore to 725000
9167 12:27:05.341135 Read voltage for 1600, 0
9168 12:27:05.341229 Vio18 = 0
9169 12:27:05.344374 Vcore = 725000
9170 12:27:05.344463 Vdram = 0
9171 12:27:05.344546 Vddq = 0
9172 12:27:05.344618 Vmddr = 0
9173 12:27:05.347626 switch to 3200 Mbps bootup
9174 12:27:05.350747 [DramcRunTimeConfig]
9175 12:27:05.350824 PHYPLL
9176 12:27:05.354392 DPM_CONTROL_AFTERK: ON
9177 12:27:05.354478 PER_BANK_REFRESH: ON
9178 12:27:05.357646 REFRESH_OVERHEAD_REDUCTION: ON
9179 12:27:05.360906 CMD_PICG_NEW_MODE: OFF
9180 12:27:05.360993 XRTWTW_NEW_MODE: ON
9181 12:27:05.364047 XRTRTR_NEW_MODE: ON
9182 12:27:05.364132 TX_TRACKING: ON
9183 12:27:05.367380 RDSEL_TRACKING: OFF
9184 12:27:05.370535 DQS Precalculation for DVFS: ON
9185 12:27:05.370651 RX_TRACKING: OFF
9186 12:27:05.374093 HW_GATING DBG: ON
9187 12:27:05.374194 ZQCS_ENABLE_LP4: ON
9188 12:27:05.377583 RX_PICG_NEW_MODE: ON
9189 12:27:05.377676 TX_PICG_NEW_MODE: ON
9190 12:27:05.380588 ENABLE_RX_DCM_DPHY: ON
9191 12:27:05.384045 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9192 12:27:05.387447 DUMMY_READ_FOR_TRACKING: OFF
9193 12:27:05.387600 !!! SPM_CONTROL_AFTERK: OFF
9194 12:27:05.390312 !!! SPM could not control APHY
9195 12:27:05.393705 IMPEDANCE_TRACKING: ON
9196 12:27:05.393875 TEMP_SENSOR: ON
9197 12:27:05.397114 HW_SAVE_FOR_SR: OFF
9198 12:27:05.400603 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9199 12:27:05.403544 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9200 12:27:05.403734 Read ODT Tracking: ON
9201 12:27:05.406931 Refresh Rate DeBounce: ON
9202 12:27:05.410353 DFS_NO_QUEUE_FLUSH: ON
9203 12:27:05.413710 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9204 12:27:05.413870 ENABLE_DFS_RUNTIME_MRW: OFF
9205 12:27:05.417150 DDR_RESERVE_NEW_MODE: ON
9206 12:27:05.420556 MR_CBT_SWITCH_FREQ: ON
9207 12:27:05.420734 =========================
9208 12:27:05.440611 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9209 12:27:05.443872 dram_init: ddr_geometry: 2
9210 12:27:05.462082 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9211 12:27:05.465563 dram_init: dram init end (result: 0)
9212 12:27:05.471967 DRAM-K: Full calibration passed in 24481 msecs
9213 12:27:05.475266 MRC: failed to locate region type 0.
9214 12:27:05.475353 DRAM rank0 size:0x100000000,
9215 12:27:05.478570 DRAM rank1 size=0x100000000
9216 12:27:05.488359 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9217 12:27:05.495228 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9218 12:27:05.501747 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9219 12:27:05.508502 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9220 12:27:05.511907 DRAM rank0 size:0x100000000,
9221 12:27:05.515248 DRAM rank1 size=0x100000000
9222 12:27:05.515333 CBMEM:
9223 12:27:05.518180 IMD: root @ 0xfffff000 254 entries.
9224 12:27:05.521614 IMD: root @ 0xffffec00 62 entries.
9225 12:27:05.525007 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9226 12:27:05.531467 WARNING: RO_VPD is uninitialized or empty.
9227 12:27:05.534798 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9228 12:27:05.541953 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9229 12:27:05.554949 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9230 12:27:05.566263 BS: romstage times (exec / console): total (unknown) / 23986 ms
9231 12:27:05.566354
9232 12:27:05.566423
9233 12:27:05.576101 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9234 12:27:05.579654 ARM64: Exception handlers installed.
9235 12:27:05.582802 ARM64: Testing exception
9236 12:27:05.586269 ARM64: Done test exception
9237 12:27:05.586374 Enumerating buses...
9238 12:27:05.589720 Show all devs... Before device enumeration.
9239 12:27:05.592530 Root Device: enabled 1
9240 12:27:05.595997 CPU_CLUSTER: 0: enabled 1
9241 12:27:05.596083 CPU: 00: enabled 1
9242 12:27:05.599349 Compare with tree...
9243 12:27:05.599434 Root Device: enabled 1
9244 12:27:05.602727 CPU_CLUSTER: 0: enabled 1
9245 12:27:05.606157 CPU: 00: enabled 1
9246 12:27:05.606242 Root Device scanning...
9247 12:27:05.609486 scan_static_bus for Root Device
9248 12:27:05.612741 CPU_CLUSTER: 0 enabled
9249 12:27:05.615747 scan_static_bus for Root Device done
9250 12:27:05.619184 scan_bus: bus Root Device finished in 8 msecs
9251 12:27:05.619322 done
9252 12:27:05.625548 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9253 12:27:05.629044 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9254 12:27:05.635488 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9255 12:27:05.638861 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9256 12:27:05.642261 Allocating resources...
9257 12:27:05.645630 Reading resources...
9258 12:27:05.648611 Root Device read_resources bus 0 link: 0
9259 12:27:05.652054 DRAM rank0 size:0x100000000,
9260 12:27:05.652166 DRAM rank1 size=0x100000000
9261 12:27:05.658535 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9262 12:27:05.658651 CPU: 00 missing read_resources
9263 12:27:05.664991 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9264 12:27:05.668627 Root Device read_resources bus 0 link: 0 done
9265 12:27:05.671859 Done reading resources.
9266 12:27:05.675020 Show resources in subtree (Root Device)...After reading.
9267 12:27:05.678665 Root Device child on link 0 CPU_CLUSTER: 0
9268 12:27:05.681715 CPU_CLUSTER: 0 child on link 0 CPU: 00
9269 12:27:05.691647 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9270 12:27:05.691734 CPU: 00
9271 12:27:05.695223 Root Device assign_resources, bus 0 link: 0
9272 12:27:05.698180 CPU_CLUSTER: 0 missing set_resources
9273 12:27:05.704594 Root Device assign_resources, bus 0 link: 0 done
9274 12:27:05.704678 Done setting resources.
9275 12:27:05.711550 Show resources in subtree (Root Device)...After assigning values.
9276 12:27:05.715041 Root Device child on link 0 CPU_CLUSTER: 0
9277 12:27:05.717940 CPU_CLUSTER: 0 child on link 0 CPU: 00
9278 12:27:05.728089 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9279 12:27:05.728199 CPU: 00
9280 12:27:05.731099 Done allocating resources.
9281 12:27:05.737790 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9282 12:27:05.737868 Enabling resources...
9283 12:27:05.740912 done.
9284 12:27:05.744288 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9285 12:27:05.747653 Initializing devices...
9286 12:27:05.747743 Root Device init
9287 12:27:05.751030 init hardware done!
9288 12:27:05.751103 0x00000018: ctrlr->caps
9289 12:27:05.754385 52.000 MHz: ctrlr->f_max
9290 12:27:05.757235 0.400 MHz: ctrlr->f_min
9291 12:27:05.757321 0x40ff8080: ctrlr->voltages
9292 12:27:05.760870 sclk: 390625
9293 12:27:05.760954 Bus Width = 1
9294 12:27:05.764172 sclk: 390625
9295 12:27:05.764257 Bus Width = 1
9296 12:27:05.767482 Early init status = 3
9297 12:27:05.770894 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9298 12:27:05.774150 in-header: 03 fc 00 00 01 00 00 00
9299 12:27:05.777293 in-data: 00
9300 12:27:05.780395 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9301 12:27:05.785032 in-header: 03 fd 00 00 00 00 00 00
9302 12:27:05.788463 in-data:
9303 12:27:05.791650 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9304 12:27:05.795291 in-header: 03 fc 00 00 01 00 00 00
9305 12:27:05.798333 in-data: 00
9306 12:27:05.801710 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9307 12:27:05.806695 in-header: 03 fd 00 00 00 00 00 00
9308 12:27:05.809624 in-data:
9309 12:27:05.813113 [SSUSB] Setting up USB HOST controller...
9310 12:27:05.816407 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9311 12:27:05.819753 [SSUSB] phy power-on done.
9312 12:27:05.823292 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9313 12:27:05.829609 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9314 12:27:05.833173 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9315 12:27:05.839356 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9316 12:27:05.846229 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9317 12:27:05.852969 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9318 12:27:05.859343 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9319 12:27:05.866073 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9320 12:27:05.869311 SPM: binary array size = 0x9dc
9321 12:27:05.872687 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9322 12:27:05.879245 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9323 12:27:05.886022 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9324 12:27:05.892288 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9325 12:27:05.895501 configure_display: Starting display init
9326 12:27:05.929601 anx7625_power_on_init: Init interface.
9327 12:27:05.933050 anx7625_disable_pd_protocol: Disabled PD feature.
9328 12:27:05.936448 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9329 12:27:05.963915 anx7625_start_dp_work: Secure OCM version=00
9330 12:27:05.967424 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9331 12:27:05.982229 sp_tx_get_edid_block: EDID Block = 1
9332 12:27:06.084752 Extracted contents:
9333 12:27:06.088103 header: 00 ff ff ff ff ff ff 00
9334 12:27:06.091390 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9335 12:27:06.094546 version: 01 04
9336 12:27:06.098013 basic params: 95 1f 11 78 0a
9337 12:27:06.101471 chroma info: 76 90 94 55 54 90 27 21 50 54
9338 12:27:06.104662 established: 00 00 00
9339 12:27:06.111104 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9340 12:27:06.114625 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9341 12:27:06.121223 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9342 12:27:06.127897 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9343 12:27:06.134599 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9344 12:27:06.137518 extensions: 00
9345 12:27:06.137604 checksum: fb
9346 12:27:06.137671
9347 12:27:06.140861 Manufacturer: IVO Model 57d Serial Number 0
9348 12:27:06.144135 Made week 0 of 2020
9349 12:27:06.147542 EDID version: 1.4
9350 12:27:06.147665 Digital display
9351 12:27:06.150925 6 bits per primary color channel
9352 12:27:06.151046 DisplayPort interface
9353 12:27:06.154307 Maximum image size: 31 cm x 17 cm
9354 12:27:06.157608 Gamma: 220%
9355 12:27:06.157713 Check DPMS levels
9356 12:27:06.160418 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9357 12:27:06.167260 First detailed timing is preferred timing
9358 12:27:06.167347 Established timings supported:
9359 12:27:06.170561 Standard timings supported:
9360 12:27:06.173973 Detailed timings
9361 12:27:06.177023 Hex of detail: 383680a07038204018303c0035ae10000019
9362 12:27:06.183619 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9363 12:27:06.187047 0780 0798 07c8 0820 hborder 0
9364 12:27:06.190488 0438 043b 0447 0458 vborder 0
9365 12:27:06.193432 -hsync -vsync
9366 12:27:06.193525 Did detailed timing
9367 12:27:06.200040 Hex of detail: 000000000000000000000000000000000000
9368 12:27:06.203604 Manufacturer-specified data, tag 0
9369 12:27:06.206842 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9370 12:27:06.210252 ASCII string: InfoVision
9371 12:27:06.213348 Hex of detail: 000000fe00523134304e574635205248200a
9372 12:27:06.216570 ASCII string: R140NWF5 RH
9373 12:27:06.216654 Checksum
9374 12:27:06.220257 Checksum: 0xfb (valid)
9375 12:27:06.223287 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9376 12:27:06.226552 DSI data_rate: 832800000 bps
9377 12:27:06.233289 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9378 12:27:06.236646 anx7625_parse_edid: pixelclock(138800).
9379 12:27:06.239605 hactive(1920), hsync(48), hfp(24), hbp(88)
9380 12:27:06.242963 vactive(1080), vsync(12), vfp(3), vbp(17)
9381 12:27:06.246480 anx7625_dsi_config: config dsi.
9382 12:27:06.252886 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9383 12:27:06.266827 anx7625_dsi_config: success to config DSI
9384 12:27:06.270214 anx7625_dp_start: MIPI phy setup OK.
9385 12:27:06.273565 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9386 12:27:06.277024 mtk_ddp_mode_set invalid vrefresh 60
9387 12:27:06.279926 main_disp_path_setup
9388 12:27:06.280008 ovl_layer_smi_id_en
9389 12:27:06.283668 ovl_layer_smi_id_en
9390 12:27:06.283750 ccorr_config
9391 12:27:06.283816 aal_config
9392 12:27:06.286630 gamma_config
9393 12:27:06.286712 postmask_config
9394 12:27:06.290016 dither_config
9395 12:27:06.293502 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9396 12:27:06.299809 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9397 12:27:06.303463 Root Device init finished in 551 msecs
9398 12:27:06.306528 CPU_CLUSTER: 0 init
9399 12:27:06.312723 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9400 12:27:06.319671 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9401 12:27:06.319772 APU_MBOX 0x190000b0 = 0x10001
9402 12:27:06.323043 APU_MBOX 0x190001b0 = 0x10001
9403 12:27:06.326156 APU_MBOX 0x190005b0 = 0x10001
9404 12:27:06.329671 APU_MBOX 0x190006b0 = 0x10001
9405 12:27:06.335961 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9406 12:27:06.345893 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9407 12:27:06.358326 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9408 12:27:06.364560 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9409 12:27:06.376463 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9410 12:27:06.385675 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9411 12:27:06.388944 CPU_CLUSTER: 0 init finished in 81 msecs
9412 12:27:06.391909 Devices initialized
9413 12:27:06.395455 Show all devs... After init.
9414 12:27:06.395586 Root Device: enabled 1
9415 12:27:06.398490 CPU_CLUSTER: 0: enabled 1
9416 12:27:06.401952 CPU: 00: enabled 1
9417 12:27:06.405382 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9418 12:27:06.408196 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9419 12:27:06.411580 ELOG: NV offset 0x57f000 size 0x1000
9420 12:27:06.418464 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9421 12:27:06.425183 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9422 12:27:06.428512 ELOG: Event(17) added with size 13 at 2023-06-06 12:27:03 UTC
9423 12:27:06.434991 out: cmd=0x121: 03 db 21 01 00 00 00 00
9424 12:27:06.438490 in-header: 03 45 00 00 2c 00 00 00
9425 12:27:06.448311 in-data: 1a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9426 12:27:06.454612 ELOG: Event(A1) added with size 10 at 2023-06-06 12:27:03 UTC
9427 12:27:06.461389 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9428 12:27:06.468106 ELOG: Event(A0) added with size 9 at 2023-06-06 12:27:03 UTC
9429 12:27:06.471265 elog_add_boot_reason: Logged dev mode boot
9430 12:27:06.477926 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9431 12:27:06.478038 Finalize devices...
9432 12:27:06.481507 Devices finalized
9433 12:27:06.484499 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9434 12:27:06.487914 Writing coreboot table at 0xffe64000
9435 12:27:06.491104 0. 000000000010a000-0000000000113fff: RAMSTAGE
9436 12:27:06.497772 1. 0000000040000000-00000000400fffff: RAM
9437 12:27:06.501086 2. 0000000040100000-000000004032afff: RAMSTAGE
9438 12:27:06.504401 3. 000000004032b000-00000000545fffff: RAM
9439 12:27:06.507755 4. 0000000054600000-000000005465ffff: BL31
9440 12:27:06.510862 5. 0000000054660000-00000000ffe63fff: RAM
9441 12:27:06.517499 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9442 12:27:06.520862 7. 0000000100000000-000000023fffffff: RAM
9443 12:27:06.524166 Passing 5 GPIOs to payload:
9444 12:27:06.527485 NAME | PORT | POLARITY | VALUE
9445 12:27:06.534127 EC in RW | 0x000000aa | low | undefined
9446 12:27:06.537500 EC interrupt | 0x00000005 | low | undefined
9447 12:27:06.540662 TPM interrupt | 0x000000ab | high | undefined
9448 12:27:06.547084 SD card detect | 0x00000011 | high | undefined
9449 12:27:06.550772 speaker enable | 0x00000093 | high | undefined
9450 12:27:06.553815 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9451 12:27:06.557027 in-header: 03 f9 00 00 02 00 00 00
9452 12:27:06.560400 in-data: 02 00
9453 12:27:06.563813 ADC[4]: Raw value=901770 ID=7
9454 12:27:06.563933 ADC[3]: Raw value=213179 ID=1
9455 12:27:06.567235 RAM Code: 0x71
9456 12:27:06.570498 ADC[6]: Raw value=74502 ID=0
9457 12:27:06.573832 ADC[5]: Raw value=212441 ID=1
9458 12:27:06.573942 SKU Code: 0x1
9459 12:27:06.580261 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9460 12:27:06.580371 coreboot table: 964 bytes.
9461 12:27:06.583576 IMD ROOT 0. 0xfffff000 0x00001000
9462 12:27:06.587134 IMD SMALL 1. 0xffffe000 0x00001000
9463 12:27:06.590056 RO MCACHE 2. 0xffffc000 0x00001104
9464 12:27:06.593627 CONSOLE 3. 0xfff7c000 0x00080000
9465 12:27:06.596926 FMAP 4. 0xfff7b000 0x00000452
9466 12:27:06.600215 TIME STAMP 5. 0xfff7a000 0x00000910
9467 12:27:06.603521 VBOOT WORK 6. 0xfff66000 0x00014000
9468 12:27:06.606865 RAMOOPS 7. 0xffe66000 0x00100000
9469 12:27:06.610289 COREBOOT 8. 0xffe64000 0x00002000
9470 12:27:06.613494 IMD small region:
9471 12:27:06.616835 IMD ROOT 0. 0xffffec00 0x00000400
9472 12:27:06.619775 VPD 1. 0xffffeba0 0x0000004c
9473 12:27:06.623550 MMC STATUS 2. 0xffffeb80 0x00000004
9474 12:27:06.626513 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9475 12:27:06.629827 Probing TPM: done!
9476 12:27:06.633773 Connected to device vid:did:rid of 1ae0:0028:00
9477 12:27:06.644259 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9478 12:27:06.647550 Initialized TPM device CR50 revision 0
9479 12:27:06.650788 Checking cr50 for pending updates
9480 12:27:06.655260 Reading cr50 TPM mode
9481 12:27:06.663703 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9482 12:27:06.670506 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9483 12:27:06.710570 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9484 12:27:06.714005 Checking segment from ROM address 0x40100000
9485 12:27:06.717309 Checking segment from ROM address 0x4010001c
9486 12:27:06.723871 Loading segment from ROM address 0x40100000
9487 12:27:06.723959 code (compression=0)
9488 12:27:06.733783 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9489 12:27:06.740573 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9490 12:27:06.740698 it's not compressed!
9491 12:27:06.746786 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9492 12:27:06.753331 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9493 12:27:06.770928 Loading segment from ROM address 0x4010001c
9494 12:27:06.771017 Entry Point 0x80000000
9495 12:27:06.773902 Loaded segments
9496 12:27:06.777358 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9497 12:27:06.783731 Jumping to boot code at 0x80000000(0xffe64000)
9498 12:27:06.790539 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9499 12:27:06.797337 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9500 12:27:06.804921 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9501 12:27:06.808689 Checking segment from ROM address 0x40100000
9502 12:27:06.811669 Checking segment from ROM address 0x4010001c
9503 12:27:06.818638 Loading segment from ROM address 0x40100000
9504 12:27:06.818724 code (compression=1)
9505 12:27:06.825150 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9506 12:27:06.834989 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9507 12:27:06.835076 using LZMA
9508 12:27:06.843523 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9509 12:27:06.850356 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9510 12:27:06.853723 Loading segment from ROM address 0x4010001c
9511 12:27:06.853810 Entry Point 0x54601000
9512 12:27:06.857196 Loaded segments
9513 12:27:06.860266 NOTICE: MT8192 bl31_setup
9514 12:27:06.867185 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9515 12:27:06.870705 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9516 12:27:06.873795 WARNING: region 0:
9517 12:27:06.877024 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 12:27:06.877103 WARNING: region 1:
9519 12:27:06.883760 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9520 12:27:06.886865 WARNING: region 2:
9521 12:27:06.890639 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9522 12:27:06.893566 WARNING: region 3:
9523 12:27:06.896881 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9524 12:27:06.900341 WARNING: region 4:
9525 12:27:06.907003 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9526 12:27:06.907086 WARNING: region 5:
9527 12:27:06.910223 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9528 12:27:06.913673 WARNING: region 6:
9529 12:27:06.916945 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9530 12:27:06.920496 WARNING: region 7:
9531 12:27:06.923783 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9532 12:27:06.930534 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9533 12:27:06.933428 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9534 12:27:06.936777 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9535 12:27:06.943437 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9536 12:27:06.946813 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9537 12:27:06.953608 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9538 12:27:06.956597 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9539 12:27:06.959980 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9540 12:27:06.966533 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9541 12:27:06.969943 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9542 12:27:06.973120 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9543 12:27:06.980166 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9544 12:27:06.983445 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9545 12:27:06.990012 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9546 12:27:06.993289 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9547 12:27:06.996659 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9548 12:27:07.002934 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9549 12:27:07.006299 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9550 12:27:07.012903 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9551 12:27:07.016202 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9552 12:27:07.019599 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9553 12:27:07.026032 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9554 12:27:07.029332 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9555 12:27:07.032552 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9556 12:27:07.039397 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9557 12:27:07.042848 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9558 12:27:07.049551 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9559 12:27:07.053040 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9560 12:27:07.059421 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9561 12:27:07.062820 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9562 12:27:07.066226 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9563 12:27:07.072569 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9564 12:27:07.075885 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9565 12:27:07.079309 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9566 12:27:07.082360 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9567 12:27:07.089438 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9568 12:27:07.092623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9569 12:27:07.095816 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9570 12:27:07.099176 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9571 12:27:07.105939 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9572 12:27:07.109398 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9573 12:27:07.112411 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9574 12:27:07.115775 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9575 12:27:07.122493 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9576 12:27:07.125824 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9577 12:27:07.129208 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9578 12:27:07.135529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9579 12:27:07.138887 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9580 12:27:07.142293 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9581 12:27:07.148939 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9582 12:27:07.152269 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9583 12:27:07.159017 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9584 12:27:07.161977 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9585 12:27:07.165375 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9586 12:27:07.172256 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9587 12:27:07.175471 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9588 12:27:07.181759 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9589 12:27:07.185476 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9590 12:27:07.191690 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9591 12:27:07.195211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9592 12:27:07.201688 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9593 12:27:07.205233 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9594 12:27:07.208623 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9595 12:27:07.215442 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9596 12:27:07.218704 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9597 12:27:07.225530 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9598 12:27:07.228371 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9599 12:27:07.235081 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9600 12:27:07.238422 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9601 12:27:07.241716 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9602 12:27:07.248108 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9603 12:27:07.251486 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9604 12:27:07.258118 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9605 12:27:07.261618 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9606 12:27:07.267947 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9607 12:27:07.271397 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9608 12:27:07.278059 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9609 12:27:07.281406 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9610 12:27:07.284463 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9611 12:27:07.291110 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9612 12:27:07.294706 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9613 12:27:07.301477 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9614 12:27:07.304317 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9615 12:27:07.311119 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9616 12:27:07.314599 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9617 12:27:07.318073 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9618 12:27:07.324303 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9619 12:27:07.327573 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9620 12:27:07.334362 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9621 12:27:07.337678 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9622 12:27:07.344391 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9623 12:27:07.347711 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9624 12:27:07.354511 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9625 12:27:07.357351 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9626 12:27:07.364148 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9627 12:27:07.367524 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9628 12:27:07.370901 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9629 12:27:07.373894 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9630 12:27:07.380612 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9631 12:27:07.383968 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9632 12:27:07.387229 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9633 12:27:07.393762 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9634 12:27:07.397424 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9635 12:27:07.403920 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9636 12:27:07.406915 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9637 12:27:07.410601 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9638 12:27:07.417093 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9639 12:27:07.420548 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9640 12:27:07.426931 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9641 12:27:07.430195 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9642 12:27:07.433638 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9643 12:27:07.440119 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9644 12:27:07.443581 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9645 12:27:07.450042 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9646 12:27:07.453468 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9647 12:27:07.456964 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9648 12:27:07.463596 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9649 12:27:07.466524 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9650 12:27:07.470039 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9651 12:27:07.476478 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9652 12:27:07.479826 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9653 12:27:07.483311 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9654 12:27:07.486599 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9655 12:27:07.490023 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9656 12:27:07.496564 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9657 12:27:07.499921 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9658 12:27:07.506397 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9659 12:27:07.509532 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9660 12:27:07.513099 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9661 12:27:07.519791 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9662 12:27:07.522962 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9663 12:27:07.529519 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9664 12:27:07.532780 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9665 12:27:07.536645 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9666 12:27:07.543168 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9667 12:27:07.546213 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9668 12:27:07.552740 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9669 12:27:07.556214 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9670 12:27:07.559696 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9671 12:27:07.566197 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9672 12:27:07.569538 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9673 12:27:07.575984 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9674 12:27:07.579389 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9675 12:27:07.582343 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9676 12:27:07.589119 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9677 12:27:07.592533 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9678 12:27:07.599265 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9679 12:27:07.602501 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9680 12:27:07.605662 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9681 12:27:07.612171 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9682 12:27:07.615869 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9683 12:27:07.622329 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9684 12:27:07.625639 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9685 12:27:07.629230 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9686 12:27:07.635492 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9687 12:27:07.639222 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9688 12:27:07.645602 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9689 12:27:07.648960 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9690 12:27:07.652441 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9691 12:27:07.658928 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9692 12:27:07.662313 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9693 12:27:07.665652 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9694 12:27:07.672325 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9695 12:27:07.675230 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9696 12:27:07.682029 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9697 12:27:07.685462 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9698 12:27:07.688730 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9699 12:27:07.695369 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9700 12:27:07.698638 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9701 12:27:07.704951 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9702 12:27:07.708252 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9703 12:27:07.715080 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9704 12:27:07.718294 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9705 12:27:07.721404 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9706 12:27:07.728245 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9707 12:27:07.731437 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9708 12:27:07.738081 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9709 12:27:07.741009 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9710 12:27:07.744294 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9711 12:27:07.751220 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9712 12:27:07.754639 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9713 12:27:07.758010 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9714 12:27:07.764157 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9715 12:27:07.767622 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9716 12:27:07.774052 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9717 12:27:07.777362 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9718 12:27:07.780841 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9719 12:27:07.787202 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9720 12:27:07.790630 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9721 12:27:07.797215 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9722 12:27:07.800564 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9723 12:27:07.806985 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9724 12:27:07.810358 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9725 12:27:07.813719 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9726 12:27:07.820502 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9727 12:27:07.823694 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9728 12:27:07.830337 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9729 12:27:07.833475 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9730 12:27:07.840116 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9731 12:27:07.843206 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9732 12:27:07.846825 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9733 12:27:07.853448 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9734 12:27:07.856381 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9735 12:27:07.863142 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9736 12:27:07.866441 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9737 12:27:07.872761 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9738 12:27:07.876178 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9739 12:27:07.879460 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9740 12:27:07.886318 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9741 12:27:07.889673 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9742 12:27:07.896483 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9743 12:27:07.899421 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9744 12:27:07.906224 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9745 12:27:07.909609 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9746 12:27:07.912509 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9747 12:27:07.919172 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9748 12:27:07.922536 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9749 12:27:07.929443 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9750 12:27:07.932595 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9751 12:27:07.939324 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9752 12:27:07.942445 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9753 12:27:07.945879 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9754 12:27:07.952183 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9755 12:27:07.955632 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9756 12:27:07.962315 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9757 12:27:07.965696 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9758 12:27:07.972287 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9759 12:27:07.975285 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9760 12:27:07.978720 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9761 12:27:07.985334 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9762 12:27:07.988696 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9763 12:27:07.992022 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9764 12:27:07.995507 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9765 12:27:07.998775 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9766 12:27:08.005212 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9767 12:27:08.008661 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9768 12:27:08.015171 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9769 12:27:08.018543 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9770 12:27:08.021776 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9771 12:27:08.028444 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9772 12:27:08.031693 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9773 12:27:08.038011 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9774 12:27:08.041291 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9775 12:27:08.044827 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9776 12:27:08.051626 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9777 12:27:08.054766 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9778 12:27:08.057964 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9779 12:27:08.064580 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9780 12:27:08.067877 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9781 12:27:08.071226 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9782 12:27:08.077891 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9783 12:27:08.080918 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9784 12:27:08.087452 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9785 12:27:08.090901 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9786 12:27:08.094416 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9787 12:27:08.100840 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9788 12:27:08.104271 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9789 12:27:08.110562 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9790 12:27:08.114116 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9791 12:27:08.117572 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9792 12:27:08.123774 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9793 12:27:08.127265 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9794 12:27:08.130227 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9795 12:27:08.136861 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9796 12:27:08.140208 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9797 12:27:08.143530 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9798 12:27:08.150041 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9799 12:27:08.153666 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9800 12:27:08.160268 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9801 12:27:08.163486 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9802 12:27:08.166852 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9803 12:27:08.169873 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9804 12:27:08.173437 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9805 12:27:08.179950 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9806 12:27:08.183364 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9807 12:27:08.186394 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9808 12:27:08.189753 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9809 12:27:08.196440 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9810 12:27:08.199884 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9811 12:27:08.203186 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9812 12:27:08.209503 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9813 12:27:08.212768 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9814 12:27:08.216172 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9815 12:27:08.222671 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9816 12:27:08.225997 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9817 12:27:08.232422 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9818 12:27:08.235811 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9819 12:27:08.242395 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9820 12:27:08.245766 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9821 12:27:08.249237 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9822 12:27:08.255558 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9823 12:27:08.259163 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9824 12:27:08.265497 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9825 12:27:08.269132 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9826 12:27:08.272205 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9827 12:27:08.279013 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9828 12:27:08.282469 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9829 12:27:08.289050 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9830 12:27:08.291961 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9831 12:27:08.295482 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9832 12:27:08.301837 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9833 12:27:08.305263 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9834 12:27:08.312194 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9835 12:27:08.315103 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9836 12:27:08.321929 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9837 12:27:08.325231 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9838 12:27:08.328234 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9839 12:27:08.334961 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9840 12:27:08.338357 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9841 12:27:08.344653 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9842 12:27:08.348032 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9843 12:27:08.354749 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9844 12:27:08.358056 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9845 12:27:08.361270 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9846 12:27:08.367825 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9847 12:27:08.371395 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9848 12:27:08.377674 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9849 12:27:08.380952 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9850 12:27:08.384155 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9851 12:27:08.391201 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9852 12:27:08.394292 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9853 12:27:08.401159 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9854 12:27:08.404017 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9855 12:27:08.407404 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9856 12:27:08.414171 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9857 12:27:08.417534 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9858 12:27:08.423816 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9859 12:27:08.427319 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9860 12:27:08.433648 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9861 12:27:08.437138 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9862 12:27:08.440633 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9863 12:27:08.447244 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9864 12:27:08.450231 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9865 12:27:08.457090 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9866 12:27:08.460528 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9867 12:27:08.463817 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9868 12:27:08.470253 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9869 12:27:08.473521 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9870 12:27:08.480215 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9871 12:27:08.483409 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9872 12:27:08.487043 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9873 12:27:08.493346 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9874 12:27:08.496472 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9875 12:27:08.503069 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9876 12:27:08.506669 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9877 12:27:08.513031 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9878 12:27:08.516504 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9879 12:27:08.519377 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9880 12:27:08.526224 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9881 12:27:08.529451 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9882 12:27:08.536232 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9883 12:27:08.539667 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9884 12:27:08.546112 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9885 12:27:08.549440 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9886 12:27:08.552938 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9887 12:27:08.559271 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9888 12:27:08.562714 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9889 12:27:08.568980 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9890 12:27:08.572428 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9891 12:27:08.578964 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9892 12:27:08.582468 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9893 12:27:08.585749 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9894 12:27:08.592216 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9895 12:27:08.595375 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9896 12:27:08.601863 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9897 12:27:08.605491 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9898 12:27:08.612010 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9899 12:27:08.615191 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9900 12:27:08.621954 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9901 12:27:08.624995 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9902 12:27:08.628352 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9903 12:27:08.635027 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9904 12:27:08.638517 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9905 12:27:08.645226 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9906 12:27:08.648608 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9907 12:27:08.655343 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9908 12:27:08.658226 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9909 12:27:08.661654 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9910 12:27:08.668214 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9911 12:27:08.671483 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9912 12:27:08.678225 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9913 12:27:08.681615 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9914 12:27:08.688239 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9915 12:27:08.691099 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9916 12:27:08.698082 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9917 12:27:08.701280 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9918 12:27:08.704426 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9919 12:27:08.711320 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9920 12:27:08.714427 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9921 12:27:08.720913 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9922 12:27:08.724509 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9923 12:27:08.730819 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9924 12:27:08.734127 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9925 12:27:08.741012 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9926 12:27:08.743958 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9927 12:27:08.750776 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9928 12:27:08.754262 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9929 12:27:08.757196 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9930 12:27:08.763957 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9931 12:27:08.767460 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9932 12:27:08.773738 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9933 12:27:08.777419 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9934 12:27:08.780297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9935 12:27:08.787314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9936 12:27:08.790287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9937 12:27:08.797074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9938 12:27:08.800388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9939 12:27:08.807034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9940 12:27:08.810266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9941 12:27:08.816556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9942 12:27:08.820103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9943 12:27:08.826669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9944 12:27:08.830138 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9945 12:27:08.836411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9946 12:27:08.839928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9947 12:27:08.846584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9948 12:27:08.849567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9949 12:27:08.856166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9950 12:27:08.859605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9951 12:27:08.866408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9952 12:27:08.869391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9953 12:27:08.876161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9954 12:27:08.879531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9955 12:27:08.885978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9956 12:27:08.889383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9957 12:27:08.896008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9958 12:27:08.899343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9959 12:27:08.905846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9960 12:27:08.908947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9961 12:27:08.915425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9962 12:27:08.919010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9963 12:27:08.925501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9964 12:27:08.928938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9965 12:27:08.935556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9966 12:27:08.938990 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9967 12:27:08.942313 INFO: [APUAPC] vio 0
9968 12:27:08.945473 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9969 12:27:08.952230 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9970 12:27:08.955291 INFO: [APUAPC] D0_APC_0: 0x400510
9971 12:27:08.958785 INFO: [APUAPC] D0_APC_1: 0x0
9972 12:27:08.958904 INFO: [APUAPC] D0_APC_2: 0x1540
9973 12:27:08.961898 INFO: [APUAPC] D0_APC_3: 0x0
9974 12:27:08.965034 INFO: [APUAPC] D1_APC_0: 0xffffffff
9975 12:27:08.968676 INFO: [APUAPC] D1_APC_1: 0xffffffff
9976 12:27:08.971665 INFO: [APUAPC] D1_APC_2: 0x3fffff
9977 12:27:08.975328 INFO: [APUAPC] D1_APC_3: 0x0
9978 12:27:08.978304 INFO: [APUAPC] D2_APC_0: 0xffffffff
9979 12:27:08.982030 INFO: [APUAPC] D2_APC_1: 0xffffffff
9980 12:27:08.985277 INFO: [APUAPC] D2_APC_2: 0x3fffff
9981 12:27:08.988309 INFO: [APUAPC] D2_APC_3: 0x0
9982 12:27:08.991744 INFO: [APUAPC] D3_APC_0: 0xffffffff
9983 12:27:08.995262 INFO: [APUAPC] D3_APC_1: 0xffffffff
9984 12:27:08.998337 INFO: [APUAPC] D3_APC_2: 0x3fffff
9985 12:27:09.001761 INFO: [APUAPC] D3_APC_3: 0x0
9986 12:27:09.005140 INFO: [APUAPC] D4_APC_0: 0xffffffff
9987 12:27:09.007981 INFO: [APUAPC] D4_APC_1: 0xffffffff
9988 12:27:09.011362 INFO: [APUAPC] D4_APC_2: 0x3fffff
9989 12:27:09.014763 INFO: [APUAPC] D4_APC_3: 0x0
9990 12:27:09.017929 INFO: [APUAPC] D5_APC_0: 0xffffffff
9991 12:27:09.021360 INFO: [APUAPC] D5_APC_1: 0xffffffff
9992 12:27:09.024552 INFO: [APUAPC] D5_APC_2: 0x3fffff
9993 12:27:09.027834 INFO: [APUAPC] D5_APC_3: 0x0
9994 12:27:09.031124 INFO: [APUAPC] D6_APC_0: 0xffffffff
9995 12:27:09.034364 INFO: [APUAPC] D6_APC_1: 0xffffffff
9996 12:27:09.037962 INFO: [APUAPC] D6_APC_2: 0x3fffff
9997 12:27:09.041237 INFO: [APUAPC] D6_APC_3: 0x0
9998 12:27:09.044333 INFO: [APUAPC] D7_APC_0: 0xffffffff
9999 12:27:09.047674 INFO: [APUAPC] D7_APC_1: 0xffffffff
10000 12:27:09.051106 INFO: [APUAPC] D7_APC_2: 0x3fffff
10001 12:27:09.054590 INFO: [APUAPC] D7_APC_3: 0x0
10002 12:27:09.057463 INFO: [APUAPC] D8_APC_0: 0xffffffff
10003 12:27:09.061064 INFO: [APUAPC] D8_APC_1: 0xffffffff
10004 12:27:09.064225 INFO: [APUAPC] D8_APC_2: 0x3fffff
10005 12:27:09.067200 INFO: [APUAPC] D8_APC_3: 0x0
10006 12:27:09.070618 INFO: [APUAPC] D9_APC_0: 0xffffffff
10007 12:27:09.074026 INFO: [APUAPC] D9_APC_1: 0xffffffff
10008 12:27:09.077474 INFO: [APUAPC] D9_APC_2: 0x3fffff
10009 12:27:09.080684 INFO: [APUAPC] D9_APC_3: 0x0
10010 12:27:09.084081 INFO: [APUAPC] D10_APC_0: 0xffffffff
10011 12:27:09.087367 INFO: [APUAPC] D10_APC_1: 0xffffffff
10012 12:27:09.090666 INFO: [APUAPC] D10_APC_2: 0x3fffff
10013 12:27:09.094123 INFO: [APUAPC] D10_APC_3: 0x0
10014 12:27:09.097459 INFO: [APUAPC] D11_APC_0: 0xffffffff
10015 12:27:09.100563 INFO: [APUAPC] D11_APC_1: 0xffffffff
10016 12:27:09.104122 INFO: [APUAPC] D11_APC_2: 0x3fffff
10017 12:27:09.107085 INFO: [APUAPC] D11_APC_3: 0x0
10018 12:27:09.110733 INFO: [APUAPC] D12_APC_0: 0xffffffff
10019 12:27:09.113720 INFO: [APUAPC] D12_APC_1: 0xffffffff
10020 12:27:09.117209 INFO: [APUAPC] D12_APC_2: 0x3fffff
10021 12:27:09.120579 INFO: [APUAPC] D12_APC_3: 0x0
10022 12:27:09.123553 INFO: [APUAPC] D13_APC_0: 0xffffffff
10023 12:27:09.126848 INFO: [APUAPC] D13_APC_1: 0xffffffff
10024 12:27:09.130518 INFO: [APUAPC] D13_APC_2: 0x3fffff
10025 12:27:09.133702 INFO: [APUAPC] D13_APC_3: 0x0
10026 12:27:09.136757 INFO: [APUAPC] D14_APC_0: 0xffffffff
10027 12:27:09.140137 INFO: [APUAPC] D14_APC_1: 0xffffffff
10028 12:27:09.143542 INFO: [APUAPC] D14_APC_2: 0x3fffff
10029 12:27:09.146905 INFO: [APUAPC] D14_APC_3: 0x0
10030 12:27:09.149953 INFO: [APUAPC] D15_APC_0: 0xffffffff
10031 12:27:09.153521 INFO: [APUAPC] D15_APC_1: 0xffffffff
10032 12:27:09.156542 INFO: [APUAPC] D15_APC_2: 0x3fffff
10033 12:27:09.160277 INFO: [APUAPC] D15_APC_3: 0x0
10034 12:27:09.163414 INFO: [APUAPC] APC_CON: 0x4
10035 12:27:09.166430 INFO: [NOCDAPC] D0_APC_0: 0x0
10036 12:27:09.170029 INFO: [NOCDAPC] D0_APC_1: 0x0
10037 12:27:09.172978 INFO: [NOCDAPC] D1_APC_0: 0x0
10038 12:27:09.173059 INFO: [NOCDAPC] D1_APC_1: 0xfff
10039 12:27:09.176418 INFO: [NOCDAPC] D2_APC_0: 0x0
10040 12:27:09.179727 INFO: [NOCDAPC] D2_APC_1: 0xfff
10041 12:27:09.183196 INFO: [NOCDAPC] D3_APC_0: 0x0
10042 12:27:09.186480 INFO: [NOCDAPC] D3_APC_1: 0xfff
10043 12:27:09.189986 INFO: [NOCDAPC] D4_APC_0: 0x0
10044 12:27:09.193233 INFO: [NOCDAPC] D4_APC_1: 0xfff
10045 12:27:09.196185 INFO: [NOCDAPC] D5_APC_0: 0x0
10046 12:27:09.199578 INFO: [NOCDAPC] D5_APC_1: 0xfff
10047 12:27:09.203043 INFO: [NOCDAPC] D6_APC_0: 0x0
10048 12:27:09.206316 INFO: [NOCDAPC] D6_APC_1: 0xfff
10049 12:27:09.206390 INFO: [NOCDAPC] D7_APC_0: 0x0
10050 12:27:09.209762 INFO: [NOCDAPC] D7_APC_1: 0xfff
10051 12:27:09.213092 INFO: [NOCDAPC] D8_APC_0: 0x0
10052 12:27:09.216394 INFO: [NOCDAPC] D8_APC_1: 0xfff
10053 12:27:09.219334 INFO: [NOCDAPC] D9_APC_0: 0x0
10054 12:27:09.222578 INFO: [NOCDAPC] D9_APC_1: 0xfff
10055 12:27:09.225985 INFO: [NOCDAPC] D10_APC_0: 0x0
10056 12:27:09.229237 INFO: [NOCDAPC] D10_APC_1: 0xfff
10057 12:27:09.232526 INFO: [NOCDAPC] D11_APC_0: 0x0
10058 12:27:09.236258 INFO: [NOCDAPC] D11_APC_1: 0xfff
10059 12:27:09.239526 INFO: [NOCDAPC] D12_APC_0: 0x0
10060 12:27:09.242840 INFO: [NOCDAPC] D12_APC_1: 0xfff
10061 12:27:09.245996 INFO: [NOCDAPC] D13_APC_0: 0x0
10062 12:27:09.249058 INFO: [NOCDAPC] D13_APC_1: 0xfff
10063 12:27:09.252397 INFO: [NOCDAPC] D14_APC_0: 0x0
10064 12:27:09.252512 INFO: [NOCDAPC] D14_APC_1: 0xfff
10065 12:27:09.255572 INFO: [NOCDAPC] D15_APC_0: 0x0
10066 12:27:09.259016 INFO: [NOCDAPC] D15_APC_1: 0xfff
10067 12:27:09.262462 INFO: [NOCDAPC] APC_CON: 0x4
10068 12:27:09.265816 INFO: [APUAPC] set_apusys_apc done
10069 12:27:09.268661 INFO: [DEVAPC] devapc_init done
10070 12:27:09.272062 INFO: GICv3 without legacy support detected.
10071 12:27:09.278703 INFO: ARM GICv3 driver initialized in EL3
10072 12:27:09.282179 INFO: Maximum SPI INTID supported: 639
10073 12:27:09.285608 INFO: BL31: Initializing runtime services
10074 12:27:09.291942 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10075 12:27:09.295232 INFO: SPM: enable CPC mode
10076 12:27:09.298459 INFO: mcdi ready for mcusys-off-idle and system suspend
10077 12:27:09.305381 INFO: BL31: Preparing for EL3 exit to normal world
10078 12:27:09.308487 INFO: Entry point address = 0x80000000
10079 12:27:09.308560 INFO: SPSR = 0x8
10080 12:27:09.315417
10081 12:27:09.315542
10082 12:27:09.315648
10083 12:27:09.318357 Starting depthcharge on Spherion...
10084 12:27:09.318495
10085 12:27:09.318610 Wipe memory regions:
10086 12:27:09.318713
10087 12:27:09.319543 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10088 12:27:09.319690 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10089 12:27:09.319806 Setting prompt string to ['asurada:']
10090 12:27:09.320018 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10091 12:27:09.321881 [0x00000040000000, 0x00000054600000)
10092 12:27:09.444100
10093 12:27:09.444291 [0x00000054660000, 0x00000080000000)
10094 12:27:09.705231
10095 12:27:09.705780 [0x000000821a7280, 0x000000ffe64000)
10096 12:27:10.450211
10097 12:27:10.450677 [0x00000100000000, 0x00000240000000)
10098 12:27:12.339691
10099 12:27:12.342978 Initializing XHCI USB controller at 0x11200000.
10100 12:27:13.381440
10101 12:27:13.384282 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10102 12:27:13.384921
10103 12:27:13.385448
10104 12:27:13.385967
10105 12:27:13.386996 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10107 12:27:13.488497 asurada: tftpboot 192.168.201.1 10605755/tftp-deploy-d9nntriy/kernel/image.itb 10605755/tftp-deploy-d9nntriy/kernel/cmdline
10108 12:27:13.489116 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10109 12:27:13.489648 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10110 12:27:13.494216 tftpboot 192.168.201.1 10605755/tftp-deploy-d9nntriy/kernel/image.itp-deploy-d9nntriy/kernel/cmdline
10111 12:27:13.494691
10112 12:27:13.495083 Waiting for link
10113 12:27:13.654149
10114 12:27:13.654306 R8152: Initializing
10115 12:27:13.654402
10116 12:27:13.657579 Version 9 (ocp_data = 6010)
10117 12:27:13.657680
10118 12:27:13.660666 R8152: Done initializing
10119 12:27:13.660753
10120 12:27:13.660845 Adding net device
10121 12:27:15.529044
10122 12:27:15.529178 done.
10123 12:27:15.529260
10124 12:27:15.529325 MAC: 00:e0:4c:72:2d:d6
10125 12:27:15.529386
10126 12:27:15.531975 Sending DHCP discover... done.
10127 12:27:15.532056
10128 12:27:15.535856 Waiting for reply... done.
10129 12:27:15.535969
10130 12:27:15.538578 Sending DHCP request... done.
10131 12:27:15.538664
10132 12:27:15.543082 Waiting for reply... done.
10133 12:27:15.543173
10134 12:27:15.543270 My ip is 192.168.201.21
10135 12:27:15.543361
10136 12:27:15.546467 The DHCP server ip is 192.168.201.1
10137 12:27:15.546581
10138 12:27:15.553079 TFTP server IP predefined by user: 192.168.201.1
10139 12:27:15.553198
10140 12:27:15.559740 Bootfile predefined by user: 10605755/tftp-deploy-d9nntriy/kernel/image.itb
10141 12:27:15.559844
10142 12:27:15.562696 Sending tftp read request... done.
10143 12:27:15.562809
10144 12:27:15.562906 Waiting for the transfer...
10145 12:27:15.563000
10146 12:27:15.819172 00000000 ################################################################
10147 12:27:15.819313
10148 12:27:16.073663 00080000 ################################################################
10149 12:27:16.073836
10150 12:27:16.339943 00100000 ################################################################
10151 12:27:16.340075
10152 12:27:16.598924 00180000 ################################################################
10153 12:27:16.599074
10154 12:27:16.852896 00200000 ################################################################
10155 12:27:16.853036
10156 12:27:17.101037 00280000 ################################################################
10157 12:27:17.101182
10158 12:27:17.354047 00300000 ################################################################
10159 12:27:17.354218
10160 12:27:17.600232 00380000 ################################################################
10161 12:27:17.600400
10162 12:27:17.849701 00400000 ################################################################
10163 12:27:17.849872
10164 12:27:18.099293 00480000 ################################################################
10165 12:27:18.099459
10166 12:27:18.349526 00500000 ################################################################
10167 12:27:18.349695
10168 12:27:18.591265 00580000 ################################################################
10169 12:27:18.591403
10170 12:27:18.833118 00600000 ################################################################
10171 12:27:18.833282
10172 12:27:19.078652 00680000 ################################################################
10173 12:27:19.078789
10174 12:27:19.325555 00700000 ################################################################
10175 12:27:19.325693
10176 12:27:19.579817 00780000 ################################################################
10177 12:27:19.579982
10178 12:27:19.829192 00800000 ################################################################
10179 12:27:19.829333
10180 12:27:20.077539 00880000 ################################################################
10181 12:27:20.077722
10182 12:27:20.329277 00900000 ################################################################
10183 12:27:20.329423
10184 12:27:20.591149 00980000 ################################################################
10185 12:27:20.591291
10186 12:27:20.853884 00a00000 ################################################################
10187 12:27:20.854051
10188 12:27:21.100681 00a80000 ################################################################
10189 12:27:21.100860
10190 12:27:21.359420 00b00000 ################################################################
10191 12:27:21.359559
10192 12:27:21.622768 00b80000 ################################################################
10193 12:27:21.622920
10194 12:27:21.873805 00c00000 ################################################################
10195 12:27:21.873976
10196 12:27:22.135399 00c80000 ################################################################
10197 12:27:22.135568
10198 12:27:22.385665 00d00000 ################################################################
10199 12:27:22.385846
10200 12:27:22.634453 00d80000 ################################################################
10201 12:27:22.634635
10202 12:27:22.885105 00e00000 ################################################################
10203 12:27:22.885278
10204 12:27:23.133375 00e80000 ################################################################
10205 12:27:23.133551
10206 12:27:23.379590 00f00000 ################################################################
10207 12:27:23.379768
10208 12:27:23.624486 00f80000 ################################################################
10209 12:27:23.624663
10210 12:27:23.871640 01000000 ################################################################
10211 12:27:23.871793
10212 12:27:24.116440 01080000 ################################################################
10213 12:27:24.116618
10214 12:27:24.361121 01100000 ################################################################
10215 12:27:24.361302
10216 12:27:24.600509 01180000 ################################################################
10217 12:27:24.600684
10218 12:27:24.841332 01200000 ################################################################
10219 12:27:24.841517
10220 12:27:25.086876 01280000 ################################################################
10221 12:27:25.087035
10222 12:27:25.333597 01300000 ################################################################
10223 12:27:25.333752
10224 12:27:25.580888 01380000 ################################################################
10225 12:27:25.581058
10226 12:27:25.824550 01400000 ################################################################
10227 12:27:25.824715
10228 12:27:26.083433 01480000 ################################################################
10229 12:27:26.083576
10230 12:27:26.346217 01500000 ################################################################
10231 12:27:26.346391
10232 12:27:26.601645 01580000 ################################################################
10233 12:27:26.601827
10234 12:27:26.848122 01600000 ################################################################
10235 12:27:26.848287
10236 12:27:27.097488 01680000 ################################################################
10237 12:27:27.097665
10238 12:27:27.356730 01700000 ################################################################
10239 12:27:27.356919
10240 12:27:27.604557 01780000 ################################################################
10241 12:27:27.604730
10242 12:27:27.853164 01800000 ################################################################
10243 12:27:27.853319
10244 12:27:28.114579 01880000 ################################################################
10245 12:27:28.114763
10246 12:27:28.356064 01900000 ################################################################
10247 12:27:28.356239
10248 12:27:28.613725 01980000 ################################################################
10249 12:27:28.613869
10250 12:27:28.879430 01a00000 ################################################################
10251 12:27:28.879565
10252 12:27:29.128443 01a80000 ################################################################
10253 12:27:29.128617
10254 12:27:29.330576 01b00000 ##################################################### done.
10255 12:27:29.330735
10256 12:27:29.333763 The bootfile was 28741254 bytes long.
10257 12:27:29.333872
10258 12:27:29.337312 Sending tftp read request... done.
10259 12:27:29.337397
10260 12:27:29.340412 Waiting for the transfer...
10261 12:27:29.340514
10262 12:27:29.340608 00000000 # done.
10263 12:27:29.340722
10264 12:27:29.350587 Command line loaded dynamically from TFTP file: 10605755/tftp-deploy-d9nntriy/kernel/cmdline
10265 12:27:29.350672
10266 12:27:29.370284 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605755/extract-nfsrootfs-o4xbtzwu,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10267 12:27:29.370392
10268 12:27:29.370479 Loading FIT.
10269 12:27:29.370597
10270 12:27:29.373391 Image ramdisk-1 has 18605545 bytes.
10271 12:27:29.373482
10272 12:27:29.376659 Image fdt-1 has 46924 bytes.
10273 12:27:29.376783
10274 12:27:29.380344 Image kernel-1 has 10086749 bytes.
10275 12:27:29.380432
10276 12:27:29.390076 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10277 12:27:29.390166
10278 12:27:29.406740 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10279 12:27:29.406832
10280 12:27:29.409733 Choosing best match conf-1 for compat google,spherion-rev2.
10281 12:27:29.413487
10282 12:27:29.417074 Connected to device vid:did:rid of 1ae0:0028:00
10283 12:27:29.426869
10284 12:27:29.430230 tpm_get_response: command 0x17b, return code 0x0
10285 12:27:29.430345
10286 12:27:29.433628 ec_init: CrosEC protocol v3 supported (256, 248)
10287 12:27:29.438540
10288 12:27:29.442084 tpm_cleanup: add release locality here.
10289 12:27:29.442171
10290 12:27:29.442239 Shutting down all USB controllers.
10291 12:27:29.445060
10292 12:27:29.445175 Removing current net device
10293 12:27:29.445264
10294 12:27:29.451598 Exiting depthcharge with code 4 at timestamp: 49415066
10295 12:27:29.451684
10296 12:27:29.455045 LZMA decompressing kernel-1 to 0x821a6718
10297 12:27:29.455162
10298 12:27:29.458245 LZMA decompressing kernel-1 to 0x40000000
10299 12:27:30.725166
10300 12:27:30.725316 jumping to kernel
10301 12:27:30.725748 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
10302 12:27:30.725861 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10303 12:27:30.726007 Setting prompt string to ['Linux version [0-9]']
10304 12:27:30.726127 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10305 12:27:30.726210 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10306 12:27:30.808069
10307 12:27:30.811134 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10308 12:27:30.814637 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10309 12:27:30.814799 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10310 12:27:30.814947 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10311 12:27:30.815059 Using line separator: #'\n'#
10312 12:27:30.815171 No login prompt set.
10313 12:27:30.815268 Parsing kernel messages
10314 12:27:30.815381 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10315 12:27:30.815585 [login-action] Waiting for messages, (timeout 00:04:04)
10316 12:27:30.834106 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614976-arm64-gcc-10-defconfig-arm64-chromebook-lgg5p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023
10317 12:27:30.837687 [ 0.000000] random: crng init done
10318 12:27:30.844133 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10319 12:27:30.847123 [ 0.000000] efi: UEFI not found.
10320 12:27:30.854180 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10321 12:27:30.860319 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10322 12:27:30.870237 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10323 12:27:30.880426 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10324 12:27:30.887147 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10325 12:27:30.893623 [ 0.000000] printk: bootconsole [mtk8250] enabled
10326 12:27:30.900381 [ 0.000000] NUMA: No NUMA configuration found
10327 12:27:30.906966 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10328 12:27:30.910342 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10329 12:27:30.913341 [ 0.000000] Zone ranges:
10330 12:27:30.920259 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10331 12:27:30.923390 [ 0.000000] DMA32 empty
10332 12:27:30.930173 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10333 12:27:30.933260 [ 0.000000] Movable zone start for each node
10334 12:27:30.936323 [ 0.000000] Early memory node ranges
10335 12:27:30.943105 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10336 12:27:30.950036 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10337 12:27:30.956468 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10338 12:27:30.963026 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10339 12:27:30.966318 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10340 12:27:30.976010 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10341 12:27:31.031998 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10342 12:27:31.038233 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10343 12:27:31.044682 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10344 12:27:31.048132 [ 0.000000] psci: probing for conduit method from DT.
10345 12:27:31.054875 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10346 12:27:31.058355 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10347 12:27:31.064445 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10348 12:27:31.068027 [ 0.000000] psci: SMC Calling Convention v1.2
10349 12:27:31.074430 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10350 12:27:31.077983 [ 0.000000] Detected VIPT I-cache on CPU0
10351 12:27:31.084616 [ 0.000000] CPU features: detected: GIC system register CPU interface
10352 12:27:31.091312 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10353 12:27:31.097694 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10354 12:27:31.104068 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10355 12:27:31.114185 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10356 12:27:31.120850 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10357 12:27:31.123835 [ 0.000000] alternatives: applying boot alternatives
10358 12:27:31.130809 [ 0.000000] Fallback order for Node 0: 0
10359 12:27:31.137436 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10360 12:27:31.140683 [ 0.000000] Policy zone: Normal
10361 12:27:31.160429 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605755/extract-nfsrootfs-o4xbtzwu,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10362 12:27:31.170171 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10363 12:27:31.182113 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10364 12:27:31.191922 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10365 12:27:31.198574 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10366 12:27:31.202229 <6>[ 0.000000] software IO TLB: area num 8.
10367 12:27:31.258383 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10368 12:27:31.407652 <6>[ 0.000000] Memory: 7954776K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397992K reserved, 32768K cma-reserved)
10369 12:27:31.414428 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10370 12:27:31.420988 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10371 12:27:31.424508 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10372 12:27:31.430667 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10373 12:27:31.437647 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10374 12:27:31.440483 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10375 12:27:31.450588 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10376 12:27:31.457462 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10377 12:27:31.463971 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10378 12:27:31.470447 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10379 12:27:31.473832 <6>[ 0.000000] GICv3: 608 SPIs implemented
10380 12:27:31.477331 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10381 12:27:31.483642 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10382 12:27:31.487213 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10383 12:27:31.493473 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10384 12:27:31.506600 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10385 12:27:31.519780 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10386 12:27:31.526354 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10387 12:27:31.533592 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10388 12:27:31.546973 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10389 12:27:31.553754 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10390 12:27:31.560264 <6>[ 0.009173] Console: colour dummy device 80x25
10391 12:27:31.570149 <6>[ 0.013900] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10392 12:27:31.576604 <6>[ 0.024342] pid_max: default: 32768 minimum: 301
10393 12:27:31.580250 <6>[ 0.029216] LSM: Security Framework initializing
10394 12:27:31.586670 <6>[ 0.034120] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10395 12:27:31.596577 <6>[ 0.041934] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10396 12:27:31.606585 <6>[ 0.051313] cblist_init_generic: Setting adjustable number of callback queues.
10397 12:27:31.609758 <6>[ 0.058764] cblist_init_generic: Setting shift to 3 and lim to 1.
10398 12:27:31.616413 <6>[ 0.065104] cblist_init_generic: Setting shift to 3 and lim to 1.
10399 12:27:31.622762 <6>[ 0.071550] rcu: Hierarchical SRCU implementation.
10400 12:27:31.629371 <6>[ 0.076564] rcu: Max phase no-delay instances is 1000.
10401 12:27:31.636188 <6>[ 0.083614] EFI services will not be available.
10402 12:27:31.639174 <6>[ 0.088585] smp: Bringing up secondary CPUs ...
10403 12:27:31.647318 <6>[ 0.093668] Detected VIPT I-cache on CPU1
10404 12:27:31.653824 <6>[ 0.093740] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10405 12:27:31.660583 <6>[ 0.093771] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10406 12:27:31.663515 <6>[ 0.094101] Detected VIPT I-cache on CPU2
10407 12:27:31.673427 <6>[ 0.094149] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10408 12:27:31.679973 <6>[ 0.094163] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10409 12:27:31.683417 <6>[ 0.094422] Detected VIPT I-cache on CPU3
10410 12:27:31.689977 <6>[ 0.094471] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10411 12:27:31.696799 <6>[ 0.094484] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10412 12:27:31.700194 <6>[ 0.094792] CPU features: detected: Spectre-v4
10413 12:27:31.706378 <6>[ 0.094798] CPU features: detected: Spectre-BHB
10414 12:27:31.710084 <6>[ 0.094805] Detected PIPT I-cache on CPU4
10415 12:27:31.716375 <6>[ 0.094860] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10416 12:27:31.723109 <6>[ 0.094876] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10417 12:27:31.729410 <6>[ 0.095171] Detected PIPT I-cache on CPU5
10418 12:27:31.736326 <6>[ 0.095235] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10419 12:27:31.742495 <6>[ 0.095252] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10420 12:27:31.746022 <6>[ 0.095534] Detected PIPT I-cache on CPU6
10421 12:27:31.752708 <6>[ 0.095600] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10422 12:27:31.762488 <6>[ 0.095616] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10423 12:27:31.765856 <6>[ 0.095910] Detected PIPT I-cache on CPU7
10424 12:27:31.772363 <6>[ 0.095976] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10425 12:27:31.778909 <6>[ 0.095991] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10426 12:27:31.782267 <6>[ 0.096038] smp: Brought up 1 node, 8 CPUs
10427 12:27:31.788850 <6>[ 0.237300] SMP: Total of 8 processors activated.
10428 12:27:31.795370 <6>[ 0.242252] CPU features: detected: 32-bit EL0 Support
10429 12:27:31.801886 <6>[ 0.247648] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10430 12:27:31.808359 <6>[ 0.256449] CPU features: detected: Common not Private translations
10431 12:27:31.815285 <6>[ 0.262965] CPU features: detected: CRC32 instructions
10432 12:27:31.821789 <6>[ 0.268316] CPU features: detected: RCpc load-acquire (LDAPR)
10433 12:27:31.824982 <6>[ 0.274313] CPU features: detected: LSE atomic instructions
10434 12:27:31.831422 <6>[ 0.280130] CPU features: detected: Privileged Access Never
10435 12:27:31.838318 <6>[ 0.285910] CPU features: detected: RAS Extension Support
10436 12:27:31.845007 <6>[ 0.291519] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10437 12:27:31.847979 <6>[ 0.298738] CPU: All CPU(s) started at EL2
10438 12:27:31.854997 <6>[ 0.303081] alternatives: applying system-wide alternatives
10439 12:27:31.865002 <6>[ 0.313788] devtmpfs: initialized
10440 12:27:31.880300 <6>[ 0.322588] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10441 12:27:31.886583 <6>[ 0.332555] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10442 12:27:31.893230 <6>[ 0.340575] pinctrl core: initialized pinctrl subsystem
10443 12:27:31.896762 <6>[ 0.347261] DMI not present or invalid.
10444 12:27:31.903005 <6>[ 0.351669] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10445 12:27:31.912947 <6>[ 0.358535] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10446 12:27:31.919571 <6>[ 0.366116] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10447 12:27:31.929911 <6>[ 0.374327] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10448 12:27:31.932836 <6>[ 0.382573] audit: initializing netlink subsys (disabled)
10449 12:27:31.943100 <5>[ 0.388269] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10450 12:27:31.949237 <6>[ 0.388982] thermal_sys: Registered thermal governor 'step_wise'
10451 12:27:31.956255 <6>[ 0.396235] thermal_sys: Registered thermal governor 'power_allocator'
10452 12:27:31.959241 <6>[ 0.402491] cpuidle: using governor menu
10453 12:27:31.966163 <6>[ 0.413452] NET: Registered PF_QIPCRTR protocol family
10454 12:27:31.972270 <6>[ 0.418943] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10455 12:27:31.979384 <6>[ 0.426047] ASID allocator initialised with 32768 entries
10456 12:27:31.982466 <6>[ 0.432618] Serial: AMBA PL011 UART driver
10457 12:27:31.992622 <4>[ 0.441288] Trying to register duplicate clock ID: 134
10458 12:27:32.046189 <6>[ 0.498467] KASLR enabled
10459 12:27:32.060524 <6>[ 0.506214] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10460 12:27:32.067007 <6>[ 0.513231] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10461 12:27:32.073897 <6>[ 0.519722] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10462 12:27:32.080272 <6>[ 0.526726] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10463 12:27:32.086801 <6>[ 0.533215] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10464 12:27:32.093597 <6>[ 0.540220] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10465 12:27:32.100223 <6>[ 0.546706] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10466 12:27:32.106634 <6>[ 0.553710] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10467 12:27:32.110223 <6>[ 0.561232] ACPI: Interpreter disabled.
10468 12:27:32.118548 <6>[ 0.567625] iommu: Default domain type: Translated
10469 12:27:32.125153 <6>[ 0.572735] iommu: DMA domain TLB invalidation policy: strict mode
10470 12:27:32.128750 <5>[ 0.579388] SCSI subsystem initialized
10471 12:27:32.135433 <6>[ 0.583554] usbcore: registered new interface driver usbfs
10472 12:27:32.141873 <6>[ 0.589290] usbcore: registered new interface driver hub
10473 12:27:32.145252 <6>[ 0.594845] usbcore: registered new device driver usb
10474 12:27:32.152163 <6>[ 0.600926] pps_core: LinuxPPS API ver. 1 registered
10475 12:27:32.161599 <6>[ 0.606121] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10476 12:27:32.164926 <6>[ 0.615465] PTP clock support registered
10477 12:27:32.168223 <6>[ 0.619705] EDAC MC: Ver: 3.0.0
10478 12:27:32.175992 <6>[ 0.624853] FPGA manager framework
10479 12:27:32.182351 <6>[ 0.628531] Advanced Linux Sound Architecture Driver Initialized.
10480 12:27:32.185753 <6>[ 0.635307] vgaarb: loaded
10481 12:27:32.192399 <6>[ 0.638488] clocksource: Switched to clocksource arch_sys_counter
10482 12:27:32.195727 <5>[ 0.644925] VFS: Disk quotas dquot_6.6.0
10483 12:27:32.202114 <6>[ 0.649110] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10484 12:27:32.205551 <6>[ 0.656296] pnp: PnP ACPI: disabled
10485 12:27:32.213968 <6>[ 0.663024] NET: Registered PF_INET protocol family
10486 12:27:32.223731 <6>[ 0.668617] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10487 12:27:32.235499 <6>[ 0.680938] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10488 12:27:32.245491 <6>[ 0.689754] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10489 12:27:32.251626 <6>[ 0.697722] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10490 12:27:32.261703 <6>[ 0.706422] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10491 12:27:32.268066 <6>[ 0.716171] TCP: Hash tables configured (established 65536 bind 65536)
10492 12:27:32.274729 <6>[ 0.723025] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10493 12:27:32.284624 <6>[ 0.730224] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10494 12:27:32.291542 <6>[ 0.737925] NET: Registered PF_UNIX/PF_LOCAL protocol family
10495 12:27:32.297987 <6>[ 0.744074] RPC: Registered named UNIX socket transport module.
10496 12:27:32.301365 <6>[ 0.750228] RPC: Registered udp transport module.
10497 12:27:32.307638 <6>[ 0.755160] RPC: Registered tcp transport module.
10498 12:27:32.314281 <6>[ 0.760092] RPC: Registered tcp NFSv4.1 backchannel transport module.
10499 12:27:32.317794 <6>[ 0.766762] PCI: CLS 0 bytes, default 64
10500 12:27:32.320723 <6>[ 0.771082] Unpacking initramfs...
10501 12:27:32.330978 <6>[ 0.775168] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10502 12:27:32.337639 <6>[ 0.783846] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10503 12:27:32.344022 <6>[ 0.792672] kvm [1]: IPA Size Limit: 40 bits
10504 12:27:32.347661 <6>[ 0.797197] kvm [1]: GICv3: no GICV resource entry
10505 12:27:32.354122 <6>[ 0.802216] kvm [1]: disabling GICv2 emulation
10506 12:27:32.360604 <6>[ 0.806909] kvm [1]: GIC system register CPU interface enabled
10507 12:27:32.363813 <6>[ 0.813068] kvm [1]: vgic interrupt IRQ18
10508 12:27:32.370550 <6>[ 0.817438] kvm [1]: VHE mode initialized successfully
10509 12:27:32.373470 <5>[ 0.823840] Initialise system trusted keyrings
10510 12:27:32.380253 <6>[ 0.828638] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10511 12:27:32.389944 <6>[ 0.838646] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10512 12:27:32.396520 <5>[ 0.845008] NFS: Registering the id_resolver key type
10513 12:27:32.399473 <5>[ 0.850307] Key type id_resolver registered
10514 12:27:32.406065 <5>[ 0.854720] Key type id_legacy registered
10515 12:27:32.412824 <6>[ 0.858998] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10516 12:27:32.419291 <6>[ 0.865916] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10517 12:27:32.425707 <6>[ 0.873617] 9p: Installing v9fs 9p2000 file system support
10518 12:27:32.462777 <5>[ 0.911800] Key type asymmetric registered
10519 12:27:32.466410 <5>[ 0.916131] Asymmetric key parser 'x509' registered
10520 12:27:32.476233 <6>[ 0.921275] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10521 12:27:32.479494 <6>[ 0.928891] io scheduler mq-deadline registered
10522 12:27:32.482760 <6>[ 0.933650] io scheduler kyber registered
10523 12:27:32.501621 <6>[ 0.950384] EINJ: ACPI disabled.
10524 12:27:32.533512 <4>[ 0.975655] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10525 12:27:32.543350 <4>[ 0.986303] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10526 12:27:32.558054 <6>[ 1.007057] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10527 12:27:32.566238 <6>[ 1.015018] printk: console [ttyS0] disabled
10528 12:27:32.594652 <6>[ 1.039665] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10529 12:27:32.600882 <6>[ 1.049136] printk: console [ttyS0] enabled
10530 12:27:32.604305 <6>[ 1.049136] printk: console [ttyS0] enabled
10531 12:27:32.610995 <6>[ 1.058030] printk: bootconsole [mtk8250] disabled
10532 12:27:32.614552 <6>[ 1.058030] printk: bootconsole [mtk8250] disabled
10533 12:27:32.620976 <6>[ 1.069274] SuperH (H)SCI(F) driver initialized
10534 12:27:32.624056 <6>[ 1.074542] msm_serial: driver initialized
10535 12:27:32.638079 <6>[ 1.083482] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10536 12:27:32.648301 <6>[ 1.092030] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10537 12:27:32.654935 <6>[ 1.100572] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10538 12:27:32.664413 <6>[ 1.109201] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10539 12:27:32.674471 <6>[ 1.117912] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10540 12:27:32.681100 <6>[ 1.126636] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10541 12:27:32.691067 <6>[ 1.135178] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10542 12:27:32.697768 <6>[ 1.143983] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10543 12:27:32.707546 <6>[ 1.152525] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10544 12:27:32.719436 <6>[ 1.168176] loop: module loaded
10545 12:27:32.726338 <6>[ 1.174232] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10546 12:27:32.748442 <4>[ 1.197621] mtk-pmic-keys: Failed to locate of_node [id: -1]
10547 12:27:32.755525 <6>[ 1.204509] megasas: 07.719.03.00-rc1
10548 12:27:32.764908 <6>[ 1.214016] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10549 12:27:32.773297 <6>[ 1.221867] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10550 12:27:32.789655 <6>[ 1.238598] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10551 12:27:32.850440 <6>[ 1.292700] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10552 12:27:33.145100 <6>[ 1.593733] Freeing initrd memory: 18164K
10553 12:27:33.156615 <6>[ 1.605375] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10554 12:27:33.167864 <6>[ 1.616318] tun: Universal TUN/TAP device driver, 1.6
10555 12:27:33.170978 <6>[ 1.622363] thunder_xcv, ver 1.0
10556 12:27:33.174572 <6>[ 1.625867] thunder_bgx, ver 1.0
10557 12:27:33.177621 <6>[ 1.629362] nicpf, ver 1.0
10558 12:27:33.187890 <6>[ 1.633365] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10559 12:27:33.191105 <6>[ 1.640840] hns3: Copyright (c) 2017 Huawei Corporation.
10560 12:27:33.197935 <6>[ 1.646427] hclge is initializing
10561 12:27:33.201392 <6>[ 1.650010] e1000: Intel(R) PRO/1000 Network Driver
10562 12:27:33.207670 <6>[ 1.655139] e1000: Copyright (c) 1999-2006 Intel Corporation.
10563 12:27:33.211074 <6>[ 1.661152] e1000e: Intel(R) PRO/1000 Network Driver
10564 12:27:33.217957 <6>[ 1.666367] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10565 12:27:33.224080 <6>[ 1.672556] igb: Intel(R) Gigabit Ethernet Network Driver
10566 12:27:33.230869 <6>[ 1.678206] igb: Copyright (c) 2007-2014 Intel Corporation.
10567 12:27:33.237808 <6>[ 1.684042] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10568 12:27:33.244230 <6>[ 1.690560] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10569 12:27:33.247632 <6>[ 1.697016] sky2: driver version 1.30
10570 12:27:33.253857 <6>[ 1.701988] VFIO - User Level meta-driver version: 0.3
10571 12:27:33.261490 <6>[ 1.710185] usbcore: registered new interface driver usb-storage
10572 12:27:33.268015 <6>[ 1.716630] usbcore: registered new device driver onboard-usb-hub
10573 12:27:33.277050 <6>[ 1.725719] mt6397-rtc mt6359-rtc: registered as rtc0
10574 12:27:33.286618 <6>[ 1.731185] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:27:30 UTC (1686054450)
10575 12:27:33.290003 <6>[ 1.740740] i2c_dev: i2c /dev entries driver
10576 12:27:33.306898 <6>[ 1.752353] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10577 12:27:33.314110 <6>[ 1.762565] sdhci: Secure Digital Host Controller Interface driver
10578 12:27:33.320841 <6>[ 1.769002] sdhci: Copyright(c) Pierre Ossman
10579 12:27:33.327279 <6>[ 1.774388] Synopsys Designware Multimedia Card Interface Driver
10580 12:27:33.330642 <6>[ 1.780994] mmc0: CQHCI version 5.10
10581 12:27:33.337036 <6>[ 1.781533] sdhci-pltfm: SDHCI platform and OF driver helper
10582 12:27:33.344012 <6>[ 1.792844] ledtrig-cpu: registered to indicate activity on CPUs
10583 12:27:33.355249 <6>[ 1.800167] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10584 12:27:33.358081 <6>[ 1.807557] usbcore: registered new interface driver usbhid
10585 12:27:33.365076 <6>[ 1.813390] usbhid: USB HID core driver
10586 12:27:33.371521 <6>[ 1.817632] spi_master spi0: will run message pump with realtime priority
10587 12:27:33.415109 <6>[ 1.857167] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10588 12:27:33.433538 <6>[ 1.872151] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10589 12:27:33.437184 <6>[ 1.885741] mmc0: Command Queue Engine enabled
10590 12:27:33.444028 <6>[ 1.887713] cros-ec-spi spi0.0: Chrome EC device registered
10591 12:27:33.450513 <6>[ 1.890488] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10592 12:27:33.453907 <6>[ 1.903556] mmcblk0: mmc0:0001 DA4128 116 GiB
10593 12:27:33.464881 <6>[ 1.913466] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10594 12:27:33.474815 <6>[ 1.913669] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10595 12:27:33.481216 <6>[ 1.920911] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10596 12:27:33.484838 <6>[ 1.930808] NET: Registered PF_PACKET protocol family
10597 12:27:33.491505 <6>[ 1.934645] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10598 12:27:33.494528 <6>[ 1.939337] 9pnet: Installing 9P2000 support
10599 12:27:33.501316 <6>[ 1.945065] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10600 12:27:33.507795 <5>[ 1.949015] Key type dns_resolver registered
10601 12:27:33.511231 <6>[ 1.960565] registered taskstats version 1
10602 12:27:33.517721 <5>[ 1.964966] Loading compiled-in X.509 certificates
10603 12:27:33.550754 <4>[ 1.992922] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10604 12:27:33.560408 <4>[ 2.003638] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10605 12:27:33.570952 <3>[ 2.016669] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10606 12:27:33.583774 <6>[ 2.032492] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10607 12:27:33.590903 <6>[ 2.039246] xhci-mtk 11200000.usb: xHCI Host Controller
10608 12:27:33.597392 <6>[ 2.044748] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10609 12:27:33.607131 <6>[ 2.052602] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10610 12:27:33.613814 <6>[ 2.062023] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10611 12:27:33.620468 <6>[ 2.068256] xhci-mtk 11200000.usb: xHCI Host Controller
10612 12:27:33.627216 <6>[ 2.073754] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10613 12:27:33.633419 <6>[ 2.081414] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10614 12:27:33.640848 <6>[ 2.089305] hub 1-0:1.0: USB hub found
10615 12:27:33.643910 <6>[ 2.093338] hub 1-0:1.0: 1 port detected
10616 12:27:33.653565 <6>[ 2.097682] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10617 12:27:33.656978 <6>[ 2.106504] hub 2-0:1.0: USB hub found
10618 12:27:33.659915 <6>[ 2.110531] hub 2-0:1.0: 1 port detected
10619 12:27:33.668507 <6>[ 2.117638] mtk-msdc 11f70000.mmc: Got CD GPIO
10620 12:27:33.685141 <6>[ 2.130628] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10621 12:27:33.692099 <6>[ 2.138672] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10622 12:27:33.702222 <4>[ 2.146642] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10623 12:27:33.711823 <6>[ 2.156300] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10624 12:27:33.718411 <6>[ 2.164382] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10625 12:27:33.724875 <6>[ 2.172422] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10626 12:27:33.734759 <6>[ 2.180337] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10627 12:27:33.741694 <6>[ 2.188158] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10628 12:27:33.751016 <6>[ 2.195979] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10629 12:27:33.761441 <6>[ 2.206701] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10630 12:27:33.771267 <6>[ 2.215066] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10631 12:27:33.777970 <6>[ 2.223409] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10632 12:27:33.787762 <6>[ 2.231752] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10633 12:27:33.794450 <6>[ 2.240095] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10634 12:27:33.804690 <6>[ 2.248443] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10635 12:27:33.811337 <6>[ 2.256787] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10636 12:27:33.820907 <6>[ 2.265129] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10637 12:27:33.828036 <6>[ 2.273473] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10638 12:27:33.837456 <6>[ 2.281816] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10639 12:27:33.843691 <6>[ 2.290158] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10640 12:27:33.854172 <6>[ 2.298501] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10641 12:27:33.860529 <6>[ 2.306844] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10642 12:27:33.870376 <6>[ 2.315189] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10643 12:27:33.876924 <6>[ 2.323536] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10644 12:27:33.883354 <6>[ 2.332490] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10645 12:27:33.891100 <6>[ 2.339998] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10646 12:27:33.898294 <6>[ 2.347070] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10647 12:27:33.908353 <6>[ 2.354221] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10648 12:27:33.914878 <6>[ 2.361541] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10649 12:27:33.924698 <6>[ 2.368456] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10650 12:27:33.931571 <6>[ 2.377596] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10651 12:27:33.941583 <6>[ 2.386733] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10652 12:27:33.951121 <6>[ 2.396036] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10653 12:27:33.961192 <6>[ 2.405511] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10654 12:27:33.971215 <6>[ 2.414985] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10655 12:27:33.981222 <6>[ 2.424113] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10656 12:27:33.987616 <6>[ 2.433587] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10657 12:27:33.997539 <6>[ 2.442714] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10658 12:27:34.007407 <6>[ 2.452015] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10659 12:27:34.017241 <6>[ 2.462181] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10660 12:27:34.028133 <6>[ 2.473662] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10661 12:27:34.034570 <6>[ 2.483549] Trying to probe devices needed for running init ...
10662 12:27:34.072699 <6>[ 2.518761] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10663 12:27:34.227446 <6>[ 2.676329] hub 1-1:1.0: USB hub found
10664 12:27:34.230244 <6>[ 2.680828] hub 1-1:1.0: 4 ports detected
10665 12:27:34.353132 <6>[ 2.798976] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10666 12:27:34.377833 <6>[ 2.827185] hub 2-1:1.0: USB hub found
10667 12:27:34.381210 <6>[ 2.831580] hub 2-1:1.0: 3 ports detected
10668 12:27:34.552707 <6>[ 2.998763] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10669 12:27:34.685913 <6>[ 3.134902] hub 1-1.4:1.0: USB hub found
10670 12:27:34.689499 <6>[ 3.139564] hub 1-1.4:1.0: 2 ports detected
10671 12:27:34.765332 <6>[ 3.211008] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10672 12:27:34.985352 <6>[ 3.430761] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10673 12:27:35.176861 <6>[ 3.622760] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10674 12:27:46.309627 <6>[ 14.763371] ALSA device list:
10675 12:27:46.315805 <6>[ 14.766620] No soundcards found.
10676 12:27:46.328346 <6>[ 14.779032] Freeing unused kernel memory: 8384K
10677 12:27:46.331441 <6>[ 14.783967] Run /init as init process
10678 12:27:46.341988 Loading, please wait...
10679 12:27:46.370067 Starting systemd-udevd version 252.6-1
10680 12:27:46.790532 <6>[ 15.237698] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10681 12:27:46.802209 <6>[ 15.252739] remoteproc remoteproc0: scp is available
10682 12:27:46.812327 <4>[ 15.258330] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10683 12:27:46.818799 <6>[ 15.268364] remoteproc remoteproc0: powering up scp
10684 12:27:46.828546 <4>[ 15.273560] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10685 12:27:46.835150 <3>[ 15.283533] remoteproc remoteproc0: request_firmware failed: -2
10686 12:27:46.841946 <6>[ 15.284959] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10687 12:27:46.848394 <6>[ 15.288941] usbcore: registered new interface driver r8152
10688 12:27:46.854852 <3>[ 15.297417] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 12:27:46.865000 <6>[ 15.303139] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10690 12:27:46.868015 <6>[ 15.307682] mc: Linux media interface: v0.10
10691 12:27:46.878055 <3>[ 15.314854] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 12:27:46.884664 <4>[ 15.320199] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10693 12:27:46.894474 <6>[ 15.320497] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10694 12:27:46.901044 <3>[ 15.324580] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 12:27:46.910936 <6>[ 15.325905] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10696 12:27:46.917791 <3>[ 15.332069] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 12:27:46.927664 <3>[ 15.332089] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 12:27:46.934076 <3>[ 15.332097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 12:27:46.940650 <3>[ 15.332105] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 12:27:46.950517 <3>[ 15.332112] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 12:27:46.957545 <3>[ 15.332163] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 12:27:46.966987 <3>[ 15.332209] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 12:27:46.973655 <3>[ 15.332215] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 12:27:46.983904 <3>[ 15.332222] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 12:27:46.990623 <3>[ 15.332278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 12:27:47.000172 <3>[ 15.332285] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 12:27:47.007175 <3>[ 15.332291] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 12:27:47.013582 <3>[ 15.332298] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 12:27:47.023425 <3>[ 15.332304] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 12:27:47.030234 <3>[ 15.332469] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 12:27:47.039788 <4>[ 15.333010] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10712 12:27:47.046383 <6>[ 15.439934] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10713 12:27:47.053296 <3>[ 15.446318] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10714 12:27:47.059862 <6>[ 15.448674] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10715 12:27:47.069904 <6>[ 15.455648] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10716 12:27:47.076391 <6>[ 15.456392] pci_bus 0000:00: root bus resource [bus 00-ff]
10717 12:27:47.082814 <6>[ 15.456402] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10718 12:27:47.092725 <6>[ 15.456408] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10719 12:27:47.099301 <6>[ 15.456451] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10720 12:27:47.106028 <6>[ 15.456469] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10721 12:27:47.109510 <6>[ 15.456558] pci 0000:00:00.0: supports D1 D2
10722 12:27:47.115995 <6>[ 15.456562] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10723 12:27:47.125951 <6>[ 15.458552] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10724 12:27:47.132323 <6>[ 15.458697] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10725 12:27:47.139224 <6>[ 15.458727] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10726 12:27:47.145689 <6>[ 15.458747] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10727 12:27:47.155536 <6>[ 15.458766] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10728 12:27:47.159090 <6>[ 15.458879] pci 0000:01:00.0: supports D1 D2
10729 12:27:47.165638 <6>[ 15.458883] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10730 12:27:47.175530 <4>[ 15.473757] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10731 12:27:47.181998 <6>[ 15.474626] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10732 12:27:47.188368 <6>[ 15.474667] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10733 12:27:47.198433 <6>[ 15.474675] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10734 12:27:47.205019 <6>[ 15.474688] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10735 12:27:47.212025 <6>[ 15.474704] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10736 12:27:47.222124 <6>[ 15.474720] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10737 12:27:47.225289 <6>[ 15.474734] pci 0000:00:00.0: PCI bridge to [bus 01]
10738 12:27:47.235189 <6>[ 15.474742] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10739 12:27:47.242153 <6>[ 15.474899] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10740 12:27:47.248756 <6>[ 15.475737] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10741 12:27:47.252131 <6>[ 15.476386] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10742 12:27:47.262643 <6>[ 15.479916] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10743 12:27:47.269164 <4>[ 15.487026] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10744 12:27:47.275340 <3>[ 15.572768] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10745 12:27:47.285370 <4>[ 15.586432] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10746 12:27:47.288822 <4>[ 15.586432] Fallback method does not support PEC.
10747 12:27:47.295735 <6>[ 15.634674] r8152 2-1.3:1.0 eth0: v1.12.13
10748 12:27:47.302661 <3>[ 15.690322] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10749 12:27:47.309400 <3>[ 15.711732] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10750 12:27:47.315812 <3>[ 15.717988] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10751 12:27:47.325841 <3>[ 15.749694] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10752 12:27:47.335577 <6>[ 15.750202] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10753 12:27:47.351889 <6>[ 15.802005] usbcore: registered new interface driver cdc_ether
10754 12:27:47.358254 <6>[ 15.806611] videodev: Linux video capture interface: v2.00
10755 12:27:47.365651 <6>[ 15.815788] Bluetooth: Core ver 2.22
10756 12:27:47.372065 <6>[ 15.815810] usbcore: registered new interface driver r8153_ecm
10757 12:27:47.378620 <5>[ 15.817084] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10758 12:27:47.385181 <6>[ 15.819886] NET: Registered PF_BLUETOOTH protocol family
10759 12:27:47.392230 <5>[ 15.831823] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10760 12:27:47.398614 <6>[ 15.833761] Bluetooth: HCI device and connection manager initialized
10761 12:27:47.405424 <6>[ 15.835915] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10762 12:27:47.408348 <6>[ 15.858853] Bluetooth: HCI socket layer initialized
10763 12:27:47.415211 <6>[ 15.860149] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10764 12:27:47.421750 <6>[ 15.864009] Bluetooth: L2CAP socket layer initialized
10765 12:27:47.434694 <6>[ 15.872873] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10766 12:27:47.438087 <6>[ 15.876369] Bluetooth: SCO socket layer initialized
10767 12:27:47.444476 <6>[ 15.889088] usbcore: registered new interface driver uvcvideo
10768 12:27:47.451380 <6>[ 15.895315] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10769 12:27:47.459908 <6>[ 15.910273] usbcore: registered new interface driver btusb
10770 12:27:47.472861 <4>[ 15.916696] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10771 12:27:47.479325 <3>[ 15.927250] Bluetooth: hci0: Failed to load firmware file (-2)
10772 12:27:47.482669 <3>[ 15.933341] Bluetooth: hci0: Failed to set up firmware (-2)
10773 12:27:47.493065 <4>[ 15.935072] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10774 12:27:47.502658 <4>[ 15.939175] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10775 12:27:47.509091 <6>[ 15.958764] cfg80211: failed to load regulatory.db
10776 12:27:47.545039 <6>[ 15.991935] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10777 12:27:47.551200 <6>[ 15.999441] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10778 12:27:47.575637 <6>[ 16.026232] mt7921e 0000:01:00.0: ASIC revision: 79610010
10779 12:27:47.682277 <4>[ 16.126605] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 12:27:47.685682 Begin: Loading essential drivers ... done.
10781 12:27:47.692534 Begin: Running /scripts/init-premount ... done.
10782 12:27:47.698961 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10783 12:27:47.705852 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10784 12:27:47.711956 Device /sys/class/net/enx00e04c722dd6 found
10785 12:27:47.712067 done.
10786 12:27:47.724036 Begin: Waiting up to 180 secs for any network device to become available ... done.
10787 12:27:47.783162 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10788 12:27:47.805063 <4>[ 16.249308] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10789 12:27:47.924240 <4>[ 16.368339] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10790 12:27:48.040003 <4>[ 16.484147] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10791 12:27:48.156385 <4>[ 16.600084] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10792 12:27:48.272355 <4>[ 16.716063] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 12:27:48.388248 <4>[ 16.832016] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10794 12:27:48.503842 <4>[ 16.947997] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 12:27:48.619940 <4>[ 17.063932] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 12:27:48.735896 <4>[ 17.179881] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10797 12:27:48.843812 <3>[ 17.293921] mt7921e 0000:01:00.0: hardware init failed
10798 12:27:48.850315 <6>[ 17.294776] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10799 12:27:49.780356 IP-Config: no response after 2 secs - giving up
10800 12:27:49.835270 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10801 12:27:49.838579 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10802 12:27:49.844841 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10803 12:27:49.855032 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10804 12:27:49.861639 host : mt8192-asurada-spherion-r0-cbg-1
10805 12:27:49.867969 domain : lava-rack
10806 12:27:49.871392 rootserver: 192.168.201.1 rootpath:
10807 12:27:49.872014 filename :
10808 12:27:49.923669 done.
10809 12:27:49.930849 Begin: Running /scripts/nfs-bottom ... done.
10810 12:27:49.951969 Begin: Running /scripts/init-bottom ... done.
10811 12:27:51.203766 <6>[ 19.655078] NET: Registered PF_INET6 protocol family
10812 12:27:51.210917 <6>[ 19.661798] Segment Routing with IPv6
10813 12:27:51.213900 <6>[ 19.665766] In-situ OAM (IOAM) with IPv6
10814 12:27:51.382520 <30>[ 19.806805] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10815 12:27:51.388943 <30>[ 19.839211] systemd[1]: Detected architecture arm64.
10816 12:27:51.396520
10817 12:27:51.399475 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10818 12:27:51.399888
10819 12:27:51.424982 <30>[ 19.876011] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10820 12:27:52.003293 <30>[ 20.451303] systemd[1]: Queued start job for default target graphical.target.
10821 12:27:52.033088 <30>[ 20.480828] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10822 12:27:52.039363 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10823 12:27:52.059595 <30>[ 20.507550] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10824 12:27:52.066112 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10825 12:27:52.088670 <30>[ 20.536231] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10826 12:27:52.098575 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10827 12:27:52.116428 <30>[ 20.563944] systemd[1]: Created slice user.slice - User and Session Slice.
10828 12:27:52.122805 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10829 12:27:52.142479 <30>[ 20.587002] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10830 12:27:52.149424 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10831 12:27:52.170758 <30>[ 20.614925] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10832 12:27:52.176665 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10833 12:27:52.205525 <30>[ 20.643206] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10834 12:27:52.215009 <30>[ 20.663041] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10835 12:27:52.221835 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10836 12:27:52.239351 <30>[ 20.687014] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10837 12:27:52.249034 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10838 12:27:52.263715 <30>[ 20.715172] systemd[1]: Reached target paths.target - Path Units.
10839 12:27:52.270816 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10840 12:27:52.291405 <30>[ 20.739084] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10841 12:27:52.297858 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10842 12:27:52.311869 <30>[ 20.762816] systemd[1]: Reached target slices.target - Slice Units.
10843 12:27:52.321934 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10844 12:27:52.336360 <30>[ 20.787113] systemd[1]: Reached target swap.target - Swaps.
10845 12:27:52.342910 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10846 12:27:52.363361 <30>[ 20.810867] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10847 12:27:52.373161 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10848 12:27:52.391917 <30>[ 20.839431] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10849 12:27:52.401551 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10850 12:27:52.420914 <30>[ 20.868666] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10851 12:27:52.430966 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10852 12:27:52.447894 <30>[ 20.895824] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10853 12:27:52.457969 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10854 12:27:52.475576 <30>[ 20.923147] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10855 12:27:52.482115 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10856 12:27:52.500455 <30>[ 20.947877] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10857 12:27:52.510388 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10858 12:27:52.529842 <30>[ 20.977456] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10859 12:27:52.539705 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10860 12:27:52.556299 <30>[ 21.003618] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10861 12:27:52.565909 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10862 12:27:52.603414 <30>[ 21.051075] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10863 12:27:52.609961 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10864 12:27:52.629932 <30>[ 21.077430] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10865 12:27:52.636377 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10866 12:27:52.657998 <30>[ 21.105643] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10867 12:27:52.664586 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10868 12:27:52.690121 <30>[ 21.131109] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10869 12:27:52.702500 <30>[ 21.150257] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10870 12:27:52.712615 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10871 12:27:52.734644 <30>[ 21.182009] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10872 12:27:52.741036 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10873 12:27:52.762056 <30>[ 21.209873] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10874 12:27:52.768696 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10875 12:27:52.790671 <30>[ 21.238322] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10876 12:27:52.797212 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10877 12:27:52.807076 <6>[ 21.253188] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10878 12:27:52.807511
10879 12:27:52.818190 <30>[ 21.265955] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10880 12:27:52.824810 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10881 12:27:52.863849 <30>[ 21.311300] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10882 12:27:52.870121 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10883 12:27:52.894664 <30>[ 21.342182] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10884 12:27:52.901200 Startin<6>[ 21.351135] fuse: init (API version 7.37)
10885 12:27:52.904167 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10886 12:27:52.928353 <30>[ 21.376121] systemd[1]: Starting systemd-journald.service - Journal Service...
10887 12:27:52.934839 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10888 12:27:52.958446 <30>[ 21.406095] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10889 12:27:52.965116 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10890 12:27:52.990657 <30>[ 21.435175] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10891 12:27:52.997483 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10892 12:27:53.047454 <30>[ 21.495414] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10893 12:27:53.056991 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10894 12:27:53.078336 <30>[ 21.526217] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10895 12:27:53.085122 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10896 12:27:53.095052 <3>[ 21.543162] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 12:27:53.107934 <30>[ 21.555939] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10898 12:27:53.114635 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10899 12:27:53.125323 <3>[ 21.573238] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 12:27:53.135333 <30>[ 21.583081] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10901 12:27:53.141538 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10902 12:27:53.159624 <30>[ 21.607075] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10903 12:27:53.166167 <3>[ 21.610214] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 12:27:53.176246 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10905 12:27:53.195440 <30>[ 21.643608] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10906 12:27:53.205583 <3>[ 21.644541] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 12:27:53.211839 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10908 12:27:53.232140 <30>[ 21.679941] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10909 12:27:53.238900 <3>[ 21.686008] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 12:27:53.248646 <30>[ 21.687787] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10911 12:27:53.255372 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10912 12:27:53.269750 <3>[ 21.717792] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 12:27:53.280256 <30>[ 21.728157] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10914 12:27:53.286972 <30>[ 21.735908] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10915 12:27:53.300490 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 21.748015] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 12:27:53.303521 m_mod.s…e[0m - Load Kernel Module dm_mod.
10917 12:27:53.320708 <30>[ 21.771890] systemd[1]: modprobe@drm.service: Deactivated successfully.
10918 12:27:53.330992 <30>[ 21.779303] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10919 12:27:53.338000 <3>[ 21.780616] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 12:27:53.348228 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10921 12:27:53.367768 <30>[ 21.815853] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10922 12:27:53.374678 <3>[ 21.816871] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 12:27:53.384568 <30>[ 21.824117] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10924 12:27:53.394480 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10925 12:27:53.405294 <3>[ 21.853184] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 12:27:53.415072 <30>[ 21.863331] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10927 12:27:53.421916 <30>[ 21.870899] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10928 12:27:53.432348 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10929 12:27:53.448068 <30>[ 21.895750] systemd[1]: modprobe@loop.service: Deactivated successfully.
10930 12:27:53.455082 <30>[ 21.903349] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10931 12:27:53.461845 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10932 12:27:53.479112 <30>[ 21.927311] systemd[1]: Started systemd-journald.service - Journal Service.
10933 12:27:53.485869 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10934 12:27:53.505076 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10935 12:27:53.523679 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10936 12:27:53.544080 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10937 12:27:53.564078 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10938 12:27:53.611297 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10939 12:27:53.629941 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10940 12:27:53.649918 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10941 12:27:53.668297 <4>[ 22.109483] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10942 12:27:53.678022 <3>[ 22.125167] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10943 12:27:53.684348 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10944 12:27:53.708632 <46>[ 22.156922] systemd-journald[300]: Received client request to flush runtime journal.
10945 12:27:53.722570 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10946 12:27:53.962962 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10947 12:27:54.281633 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10948 12:27:54.299039 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10949 12:27:54.315075 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10950 12:27:54.330735 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10951 12:27:54.809406 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10952 12:27:55.092184 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10953 12:27:55.115663 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10954 12:27:55.159292 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10955 12:27:55.220664 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10956 12:27:55.242628 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10957 12:27:55.262473 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10958 12:27:55.299063 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
10959 12:27:55.317453 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10960 12:27:55.338176 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10961 12:27:55.360523 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
10962 12:27:55.374844 See 'systemctl status systemd-binfmt.service' for details.
10963 12:27:55.533342 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10964 12:27:55.609878 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10965 12:27:55.630602 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10966 12:27:55.689885 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10967 12:27:55.784553 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10968 12:27:55.808943 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10969 12:27:55.971858 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10970 12:27:56.032532 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10971 12:27:56.085118 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10972 12:27:56.138284 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10973 12:27:56.168258 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10974 12:27:56.179539 <6>[ 24.631404] remoteproc remoteproc0: powering up scp
10975 12:27:56.195570 [[0;32m OK [<4>[ 24.641734] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10976 12:27:56.205378 0m] Reached target [0;1;39mnetwork.target[0m -<3>[ 24.653875] remoteproc remoteproc0: request_firmware failed: -2
10977 12:27:56.205477 Network.
10978 12:27:56.215252 <3>[ 24.662450] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10979 12:27:56.232715 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10980 12:27:56.251278 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10981 12:27:56.271842 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10982 12:27:56.290599 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10983 12:27:56.306603 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10984 12:27:56.327462 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10985 12:27:56.348851 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10986 12:27:56.366448 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10987 12:27:56.384689 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10988 12:27:56.404781 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10989 12:27:56.422463 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10990 12:27:56.439990 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10991 12:27:56.458471 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10992 12:27:56.474663 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10993 12:27:56.490903 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10994 12:27:56.531417 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10995 12:27:56.615675 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10996 12:27:56.687986 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10997 12:27:56.716888 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10998 12:27:56.745359 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10999 12:27:56.873482 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11000 12:27:56.916325 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11001 12:27:56.970924 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11002 12:27:56.994689 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11003 12:27:57.010944 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11004 12:27:57.034396 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11005 12:27:57.057389 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11006 12:27:57.077742 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11007 12:27:57.100994 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11008 12:27:57.118363 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11009 12:27:57.167830 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11010 12:27:57.186764 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11011 12:27:57.238188 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11012 12:27:57.331411 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11013 12:27:57.391526
11014 12:27:57.392024
11015 12:27:57.395011 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11016 12:27:57.395433
11017 12:27:57.398447 debian-bookworm-arm64 login: root (automatic login)
11018 12:27:57.398868
11019 12:27:57.399221
11020 12:27:57.647527 Linux debian-bookworm-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023 aarch64
11021 12:27:57.648201
11022 12:27:57.654131 The programs included with the Debian GNU/Linux system are free software;
11023 12:27:57.660153 the exact distribution terms for each program are described in the
11024 12:27:57.663530 individual files in /usr/share/doc/*/copyright.
11025 12:27:57.663652
11026 12:27:57.669951 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11027 12:27:57.673284 permitted by applicable law.
11028 12:27:58.538273 Matched prompt #10: / #
11030 12:27:58.538610 Setting prompt string to ['/ #']
11031 12:27:58.538709 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11033 12:27:58.539033 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11034 12:27:58.539148 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11035 12:27:58.539224 Setting prompt string to ['/ #']
11036 12:27:58.539289 Forcing a shell prompt, looking for ['/ #']
11038 12:27:58.589493 / #
11039 12:27:58.589655 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11040 12:27:58.589753 Waiting using forced prompt support (timeout 00:02:30)
11041 12:27:58.594665
11042 12:27:58.594931 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11043 12:27:58.595064 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
11045 12:27:58.695458 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605755/extract-nfsrootfs-o4xbtzwu'
11046 12:27:58.700409 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605755/extract-nfsrootfs-o4xbtzwu'
11048 12:27:58.800912 / # export NFS_SERVER_IP='192.168.201.1'
11049 12:27:58.805903 export NFS_SERVER_IP='192.168.201.1'
11050 12:27:58.806190 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11051 12:27:58.806294 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11052 12:27:58.806385 end: 2 depthcharge-action (duration 00:01:24) [common]
11053 12:27:58.806484 start: 3 lava-test-retry (timeout 00:07:48) [common]
11054 12:27:58.806576 start: 3.1 lava-test-shell (timeout 00:07:48) [common]
11055 12:27:58.806651 Using namespace: common
11057 12:27:58.906957 / # #
11058 12:27:58.907132 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11059 12:27:58.912077 #
11060 12:27:58.912347 Using /lava-10605755
11062 12:27:59.012706 / # export SHELL=/bin/bash
11063 12:27:59.017679 export SHELL=/bin/bash
11065 12:27:59.118418 / # . /lava-10605755/environment
11066 12:27:59.124594 . /lava-10605755/environment
11068 12:27:59.230112 / # /lava-10605755/bin/lava-test-runner /lava-10605755/0
11069 12:27:59.230640 Test shell timeout: 10s (minimum of the action and connection timeout)
11070 12:27:59.236249 /lava-10605755/bin/lava-test-runner /lava-10605755/0
11071 12:27:59.477263 + export TESTRUN_ID=0_timesync-off
11072 12:27:59.480398 + TESTRUN_ID=0_timesync-off
11073 12:27:59.483653 + cd /lava-10605755/0/tests/0_timesync-off
11074 12:27:59.486974 ++ cat uuid
11075 12:27:59.490662 + UUID=10605755_1.6.2.3.1
11076 12:27:59.491140 + set +x
11077 12:27:59.493996 Received signal: <STARTRUN> 0_timesync-off 10605755_1.6.2.3.1
11078 12:27:59.494481 Starting test lava.0_timesync-off (10605755_1.6.2.3.1)
11079 12:27:59.494959 Skipping test definition patterns.
11080 12:27:59.497038 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10605755_1.6.2.3.1>
11081 12:27:59.497516 + systemctl stop systemd-timesyncd
11082 12:27:59.538230 + set +x
11083 12:27:59.541795 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10605755_1.6.2.3.1>
11084 12:27:59.542050 Received signal: <ENDRUN> 0_timesync-off 10605755_1.6.2.3.1
11085 12:27:59.542133 Ending use of test pattern.
11086 12:27:59.542197 Ending test lava.0_timesync-off (10605755_1.6.2.3.1), duration 0.05
11088 12:27:59.583188 + export TESTRUN_ID=1_kselftest-alsa
11089 12:27:59.586501 + TESTRUN_ID=1_kselftest-alsa
11090 12:27:59.589937 + cd /lava-10605755/0/tests/1_kselftest-alsa
11091 12:27:59.593165 ++ cat uuid
11092 12:27:59.596468 + UUID=10605755_1.6.2.3.5
11093 12:27:59.596552 + set +x
11094 12:27:59.599840 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 10605755_1.6.2.3.5>
11095 12:27:59.600095 Received signal: <STARTRUN> 1_kselftest-alsa 10605755_1.6.2.3.5
11096 12:27:59.600186 Starting test lava.1_kselftest-alsa (10605755_1.6.2.3.5)
11097 12:27:59.600278 Skipping test definition patterns.
11098 12:27:59.603345 + cd ./automated/linux/kselftest/
11099 12:27:59.629566 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11100 12:27:59.653211 INFO: install_deps skipped
11101 12:28:00.151430 --2023-06-06 12:27:57-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11102 12:28:00.157947 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11103 12:28:00.294572 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11104 12:28:00.440667 HTTP request sent, awaiting response... 200 OK
11105 12:28:00.444060 Length: 2699740 (2.6M) [application/octet-stream]
11106 12:28:00.447115 Saving to: 'kselftest.tar.xz'
11107 12:28:00.447592
11108 12:28:00.448068
11109 12:28:00.733040 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11110 12:28:01.025347 kselftest.tar.xz 1%[ ] 47.81K 164KB/s
11111 12:28:01.512257 kselftest.tar.xz 8%[> ] 217.50K 372KB/s
11112 12:28:01.815040 kselftest.tar.xz 30%[=====> ] 814.23K 759KB/s
11113 12:28:01.821818 kselftest.tar.xz 92%[=================> ] 2.37M 1.73MB/s
11114 12:28:01.828450 kselftest.tar.xz 100%[===================>] 2.57M 1.87MB/s in 1.4s
11115 12:28:01.828628
11116 12:28:02.055995 2023-06-06 12:27:59 (1.87 MB/s) - 'kselftest.tar.xz' saved [2699740/2699740]
11117 12:28:02.056152
11118 12:28:06.441395 skiplist:
11119 12:28:06.444610 ========================================
11120 12:28:06.447965 ========================================
11121 12:28:06.481332 alsa:mixer-test
11122 12:28:06.496976 ============== Tests to run ===============
11123 12:28:06.497067 alsa:mixer-test
11124 12:28:06.499927 ===========End Tests to run ===============
11125 12:28:06.578551 <12>[ 35.031714] kselftest: Running tests in alsa
11126 12:28:06.586234 TAP version 13
11127 12:28:06.597479 1..1
11128 12:28:06.609959 # selftests: alsa: mixer-test
11129 12:28:07.013147 # TAP version 13
11130 12:28:07.013318 # 1..0
11131 12:28:07.019614 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11132 12:28:07.022975 ok 1 selftests: alsa: mixer-test
11133 12:28:07.636945 alsa_mixer-test pass
11134 12:28:07.668101 + ../../utils/send-to-lava.sh ./output/result.txt
11135 12:28:07.715655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11136 12:28:07.715793 + set +x
11137 12:28:07.716053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11139 12:28:07.722272 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 10605755_1.6.2.3.5>
11140 12:28:07.722527 Received signal: <ENDRUN> 1_kselftest-alsa 10605755_1.6.2.3.5
11141 12:28:07.722602 Ending use of test pattern.
11142 12:28:07.722667 Ending test lava.1_kselftest-alsa (10605755_1.6.2.3.5), duration 8.12
11144 12:28:07.725486 <LAVA_TEST_RUNNER EXIT>
11145 12:28:07.725740 ok: lava_test_shell seems to have completed
11146 12:28:07.725837 alsa_mixer-test: pass
11147 12:28:07.725927 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11148 12:28:07.726013 end: 3 lava-test-retry (duration 00:00:09) [common]
11149 12:28:07.726103 start: 4 finalize (timeout 00:07:39) [common]
11150 12:28:07.726191 start: 4.1 power-off (timeout 00:00:30) [common]
11151 12:28:07.726402 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11152 12:28:07.801253 >> Command sent successfully.
11153 12:28:07.803894 Returned 0 in 0 seconds
11154 12:28:07.904279 end: 4.1 power-off (duration 00:00:00) [common]
11156 12:28:07.904809 start: 4.2 read-feedback (timeout 00:07:39) [common]
11157 12:28:07.905099 Listened to connection for namespace 'common' for up to 1s
11158 12:28:08.906071 Finalising connection for namespace 'common'
11159 12:28:08.906273 Disconnecting from shell: Finalise
11160 12:28:08.906380 / #
11161 12:28:09.006700 end: 4.2 read-feedback (duration 00:00:01) [common]
11162 12:28:09.006881 end: 4 finalize (duration 00:00:01) [common]
11163 12:28:09.007022 Cleaning after the job
11164 12:28:09.007138 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/ramdisk
11165 12:28:09.009594 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/kernel
11166 12:28:09.019521 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/dtb
11167 12:28:09.019754 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/nfsrootfs
11168 12:28:09.098706 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605755/tftp-deploy-d9nntriy/modules
11169 12:28:09.104261 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605755
11170 12:28:09.644049 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605755
11171 12:28:09.644248 Job finished correctly