Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 43
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 12:31:42.177663 lava-dispatcher, installed at version: 2023.05.1
2 12:31:42.177884 start: 0 validate
3 12:31:42.178030 Start time: 2023-06-06 12:31:42.178020+00:00 (UTC)
4 12:31:42.178167 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:31:42.178300 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 12:31:42.473869 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:31:42.474069 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:31:42.760943 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:31:42.761133 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:31:43.054170 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:31:43.054339 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:31:43.347387 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:31:43.347552 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:31:43.639311 validate duration: 1.46
16 12:31:43.639586 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:31:43.639699 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:31:43.639792 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:31:43.639923 Not decompressing ramdisk as can be used compressed.
20 12:31:43.640008 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 12:31:43.640074 saving as /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/ramdisk/initrd.cpio.gz
22 12:31:43.640150 total size: 4665601 (4MB)
23 12:31:43.641310 progress 0% (0MB)
24 12:31:43.642794 progress 5% (0MB)
25 12:31:43.644097 progress 10% (0MB)
26 12:31:43.645332 progress 15% (0MB)
27 12:31:43.646562 progress 20% (0MB)
28 12:31:43.647815 progress 25% (1MB)
29 12:31:43.649048 progress 30% (1MB)
30 12:31:43.650305 progress 35% (1MB)
31 12:31:43.651586 progress 40% (1MB)
32 12:31:43.653018 progress 45% (2MB)
33 12:31:43.654301 progress 50% (2MB)
34 12:31:43.655560 progress 55% (2MB)
35 12:31:43.656828 progress 60% (2MB)
36 12:31:43.658074 progress 65% (2MB)
37 12:31:43.659325 progress 70% (3MB)
38 12:31:43.660604 progress 75% (3MB)
39 12:31:43.661855 progress 80% (3MB)
40 12:31:43.663278 progress 85% (3MB)
41 12:31:43.664535 progress 90% (4MB)
42 12:31:43.665801 progress 95% (4MB)
43 12:31:43.667070 progress 100% (4MB)
44 12:31:43.667227 4MB downloaded in 0.03s (164.35MB/s)
45 12:31:43.667402 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:31:43.667650 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:31:43.667738 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:31:43.667836 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:31:43.667968 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:31:43.668041 saving as /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/kernel/Image
52 12:31:43.668104 total size: 45746688 (43MB)
53 12:31:43.668165 No compression specified
54 12:31:43.669396 progress 0% (0MB)
55 12:31:43.681165 progress 5% (2MB)
56 12:31:43.692933 progress 10% (4MB)
57 12:31:43.704616 progress 15% (6MB)
58 12:31:43.716352 progress 20% (8MB)
59 12:31:43.728185 progress 25% (10MB)
60 12:31:43.739739 progress 30% (13MB)
61 12:31:43.751531 progress 35% (15MB)
62 12:31:43.763214 progress 40% (17MB)
63 12:31:43.774979 progress 45% (19MB)
64 12:31:43.786682 progress 50% (21MB)
65 12:31:43.798160 progress 55% (24MB)
66 12:31:43.810081 progress 60% (26MB)
67 12:31:43.821751 progress 65% (28MB)
68 12:31:43.834145 progress 70% (30MB)
69 12:31:43.846420 progress 75% (32MB)
70 12:31:43.858702 progress 80% (34MB)
71 12:31:43.870341 progress 85% (37MB)
72 12:31:43.882106 progress 90% (39MB)
73 12:31:43.893611 progress 95% (41MB)
74 12:31:43.905126 progress 100% (43MB)
75 12:31:43.905273 43MB downloaded in 0.24s (183.95MB/s)
76 12:31:43.905423 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:31:43.905660 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:31:43.905750 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:31:43.905842 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:31:43.905979 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:31:43.906050 saving as /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/dtb/mt8192-asurada-spherion-r0.dtb
83 12:31:43.906114 total size: 46924 (0MB)
84 12:31:43.906175 No compression specified
85 12:31:43.907244 progress 69% (0MB)
86 12:31:43.907524 progress 100% (0MB)
87 12:31:43.907680 0MB downloaded in 0.00s (28.62MB/s)
88 12:31:43.907801 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:31:43.908028 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:31:43.908114 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:31:43.908197 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:31:43.908315 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 12:31:43.908384 saving as /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/nfsrootfs/full.rootfs.tar
95 12:31:43.908445 total size: 200770336 (191MB)
96 12:31:43.908506 Using unxz to decompress xz
97 12:31:43.912098 progress 0% (0MB)
98 12:31:44.443147 progress 5% (9MB)
99 12:31:44.957714 progress 10% (19MB)
100 12:31:45.534383 progress 15% (28MB)
101 12:31:45.909280 progress 20% (38MB)
102 12:31:46.242509 progress 25% (47MB)
103 12:31:46.843649 progress 30% (57MB)
104 12:31:47.396365 progress 35% (67MB)
105 12:31:47.988261 progress 40% (76MB)
106 12:31:48.551605 progress 45% (86MB)
107 12:31:49.169803 progress 50% (95MB)
108 12:31:49.849619 progress 55% (105MB)
109 12:31:50.560965 progress 60% (114MB)
110 12:31:50.682946 progress 65% (124MB)
111 12:31:50.826017 progress 70% (134MB)
112 12:31:50.922944 progress 75% (143MB)
113 12:31:50.999342 progress 80% (153MB)
114 12:31:51.071382 progress 85% (162MB)
115 12:31:51.172545 progress 90% (172MB)
116 12:31:51.472940 progress 95% (181MB)
117 12:31:52.071755 progress 100% (191MB)
118 12:31:52.076582 191MB downloaded in 8.17s (23.44MB/s)
119 12:31:52.076921 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:31:52.077334 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:31:52.077463 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:31:52.077586 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:31:52.077779 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:31:52.077881 saving as /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/modules/modules.tar
126 12:31:52.077978 total size: 8539116 (8MB)
127 12:31:52.078074 Using unxz to decompress xz
128 12:31:52.082161 progress 0% (0MB)
129 12:31:52.103421 progress 5% (0MB)
130 12:31:52.128684 progress 10% (0MB)
131 12:31:52.152513 progress 15% (1MB)
132 12:31:52.180769 progress 20% (1MB)
133 12:31:52.205984 progress 25% (2MB)
134 12:31:52.231153 progress 30% (2MB)
135 12:31:52.257338 progress 35% (2MB)
136 12:31:52.282095 progress 40% (3MB)
137 12:31:52.305974 progress 45% (3MB)
138 12:31:52.331148 progress 50% (4MB)
139 12:31:52.355153 progress 55% (4MB)
140 12:31:52.380166 progress 60% (4MB)
141 12:31:52.405507 progress 65% (5MB)
142 12:31:52.430869 progress 70% (5MB)
143 12:31:52.457402 progress 75% (6MB)
144 12:31:52.487905 progress 80% (6MB)
145 12:31:52.510363 progress 85% (6MB)
146 12:31:52.534644 progress 90% (7MB)
147 12:31:52.559719 progress 95% (7MB)
148 12:31:52.584342 progress 100% (8MB)
149 12:31:52.589722 8MB downloaded in 0.51s (15.91MB/s)
150 12:31:52.590061 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:31:52.590490 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:31:52.590621 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:31:52.590753 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:31:56.838449 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10605810/extract-nfsrootfs-mg6xi24_
156 12:31:56.838692 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 12:31:56.838831 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 12:31:56.839044 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf
159 12:31:56.839219 makedir: /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin
160 12:31:56.839376 makedir: /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/tests
161 12:31:56.839530 makedir: /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/results
162 12:31:56.839696 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-add-keys
163 12:31:56.839893 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-add-sources
164 12:31:56.840063 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-background-process-start
165 12:31:56.840201 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-background-process-stop
166 12:31:56.840334 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-common-functions
167 12:31:56.840464 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-echo-ipv4
168 12:31:56.840588 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-install-packages
169 12:31:56.840716 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-installed-packages
170 12:31:56.840845 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-os-build
171 12:31:56.841003 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-probe-channel
172 12:31:56.841162 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-probe-ip
173 12:31:56.841318 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-target-ip
174 12:31:56.841477 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-target-mac
175 12:31:56.841635 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-target-storage
176 12:31:56.841804 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-test-case
177 12:31:56.841962 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-test-event
178 12:31:56.842123 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-test-feedback
179 12:31:56.842279 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-test-raise
180 12:31:56.842437 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-test-reference
181 12:31:56.842594 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-test-runner
182 12:31:56.842749 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-test-set
183 12:31:56.842907 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-test-shell
184 12:31:56.843064 Updating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-add-keys (debian)
185 12:31:56.847510 Updating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-add-sources (debian)
186 12:31:56.847716 Updating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-install-packages (debian)
187 12:31:56.847901 Updating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-installed-packages (debian)
188 12:31:56.852289 Updating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/bin/lava-os-build (debian)
189 12:31:56.852470 Creating /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/environment
190 12:31:56.852609 LAVA metadata
191 12:31:56.852713 - LAVA_JOB_ID=10605810
192 12:31:56.852815 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:31:56.852955 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 12:31:56.853052 skipped lava-vland-overlay
195 12:31:56.853160 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:31:56.853273 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 12:31:56.853364 skipped lava-multinode-overlay
198 12:31:56.853470 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:31:56.853600 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 12:31:56.853707 Loading test definitions
201 12:31:56.853844 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 12:31:56.853948 Using /lava-10605810 at stage 0
203 12:31:56.854342 uuid=10605810_1.6.2.3.1 testdef=None
204 12:31:56.854464 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:31:56.854582 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 12:31:56.855200 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:31:56.855517 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 12:31:56.865092 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:31:56.865510 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 12:31:56.872808 runner path: /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/0/tests/0_timesync-off test_uuid 10605810_1.6.2.3.1
213 12:31:56.873020 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:31:56.873410 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 12:31:56.873525 Using /lava-10605810 at stage 0
217 12:31:56.873680 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:31:56.873801 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/0/tests/1_kselftest-arm64'
219 12:32:06.100342 Running '/usr/bin/git checkout kernelci.org
220 12:32:06.181970 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 12:32:06.182992 uuid=10605810_1.6.2.3.5 testdef=None
222 12:32:06.183193 end: 1.6.2.3.5 git-repo-action (duration 00:00:09) [common]
224 12:32:06.183516 start: 1.6.2.3.6 test-overlay (timeout 00:09:37) [common]
225 12:32:06.184526 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:32:06.184918 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:37) [common]
228 12:32:06.186547 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:32:06.186812 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:37) [common]
231 12:32:06.188324 runner path: /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/0/tests/1_kselftest-arm64 test_uuid 10605810_1.6.2.3.5
232 12:32:06.188449 BOARD='mt8192-asurada-spherion-r0'
233 12:32:06.188556 BRANCH='cip'
234 12:32:06.188649 SKIPFILE='/dev/null'
235 12:32:06.188743 SKIP_INSTALL='True'
236 12:32:06.188840 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:32:06.188930 TST_CASENAME=''
238 12:32:06.189035 TST_CMDFILES='arm64'
239 12:32:06.189236 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:32:06.189603 Creating lava-test-runner.conf files
242 12:32:06.189699 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605810/lava-overlay-zcvpkgpf/lava-10605810/0 for stage 0
243 12:32:06.189823 - 0_timesync-off
244 12:32:06.189926 - 1_kselftest-arm64
245 12:32:06.190054 end: 1.6.2.3 test-definition (duration 00:00:09) [common]
246 12:32:06.190181 start: 1.6.2.4 compress-overlay (timeout 00:09:37) [common]
247 12:32:14.102165 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 12:32:14.102382 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:30) [common]
249 12:32:14.102517 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:32:14.102660 end: 1.6.2 lava-overlay (duration 00:00:17) [common]
251 12:32:14.102810 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:30) [common]
252 12:32:14.227834 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:32:14.228205 start: 1.6.4 extract-modules (timeout 00:09:29) [common]
254 12:32:14.228327 extracting modules file /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605810/extract-nfsrootfs-mg6xi24_
255 12:32:14.490625 extracting modules file /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605810/extract-overlay-ramdisk-5h54t0f6/ramdisk
256 12:32:14.804433 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 12:32:14.804656 start: 1.6.5 apply-overlay-tftp (timeout 00:09:29) [common]
258 12:32:14.804751 [common] Applying overlay to NFS
259 12:32:14.804823 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605810/compress-overlay-9ho_4apz/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605810/extract-nfsrootfs-mg6xi24_
260 12:32:15.973455 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:32:15.973688 start: 1.6.6 configure-preseed-file (timeout 00:09:28) [common]
262 12:32:15.973825 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:32:15.973958 start: 1.6.7 compress-ramdisk (timeout 00:09:28) [common]
264 12:32:15.974086 Building ramdisk /var/lib/lava/dispatcher/tmp/10605810/extract-overlay-ramdisk-5h54t0f6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605810/extract-overlay-ramdisk-5h54t0f6/ramdisk
265 12:32:16.266262 >> 117807 blocks
266 12:32:18.345696 rename /var/lib/lava/dispatcher/tmp/10605810/extract-overlay-ramdisk-5h54t0f6/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/ramdisk/ramdisk.cpio.gz
267 12:32:18.346137 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:32:18.346286 start: 1.6.8 prepare-kernel (timeout 00:09:25) [common]
269 12:32:18.346402 start: 1.6.8.1 prepare-fit (timeout 00:09:25) [common]
270 12:32:18.346514 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/kernel/Image'
271 12:32:31.247630 Returned 0 in 12 seconds
272 12:32:31.348230 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/kernel/image.itb
273 12:32:31.675990 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:32:31.676388 output: Created: Tue Jun 6 13:32:31 2023
275 12:32:31.676473 output: Image 0 (kernel-1)
276 12:32:31.676542 output: Description:
277 12:32:31.676627 output: Created: Tue Jun 6 13:32:31 2023
278 12:32:31.676723 output: Type: Kernel Image
279 12:32:31.676817 output: Compression: lzma compressed
280 12:32:31.676910 output: Data Size: 10086749 Bytes = 9850.34 KiB = 9.62 MiB
281 12:32:31.677004 output: Architecture: AArch64
282 12:32:31.677093 output: OS: Linux
283 12:32:31.677183 output: Load Address: 0x00000000
284 12:32:31.677273 output: Entry Point: 0x00000000
285 12:32:31.677363 output: Hash algo: crc32
286 12:32:31.677450 output: Hash value: a26c3f91
287 12:32:31.677537 output: Image 1 (fdt-1)
288 12:32:31.677622 output: Description: mt8192-asurada-spherion-r0
289 12:32:31.677708 output: Created: Tue Jun 6 13:32:31 2023
290 12:32:31.677795 output: Type: Flat Device Tree
291 12:32:31.677880 output: Compression: uncompressed
292 12:32:31.677965 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 12:32:31.678053 output: Architecture: AArch64
294 12:32:31.678139 output: Hash algo: crc32
295 12:32:31.678224 output: Hash value: 1df858fa
296 12:32:31.678311 output: Image 2 (ramdisk-1)
297 12:32:31.678397 output: Description: unavailable
298 12:32:31.678481 output: Created: Tue Jun 6 13:32:31 2023
299 12:32:31.678568 output: Type: RAMDisk Image
300 12:32:31.678654 output: Compression: Unknown Compression
301 12:32:31.678739 output: Data Size: 17636691 Bytes = 17223.33 KiB = 16.82 MiB
302 12:32:31.678826 output: Architecture: AArch64
303 12:32:31.678911 output: OS: Linux
304 12:32:31.678997 output: Load Address: unavailable
305 12:32:31.679088 output: Entry Point: unavailable
306 12:32:31.679174 output: Hash algo: crc32
307 12:32:31.679268 output: Hash value: bb9ef8d6
308 12:32:31.679361 output: Default Configuration: 'conf-1'
309 12:32:31.679421 output: Configuration 0 (conf-1)
310 12:32:31.679480 output: Description: mt8192-asurada-spherion-r0
311 12:32:31.679537 output: Kernel: kernel-1
312 12:32:31.679592 output: Init Ramdisk: ramdisk-1
313 12:32:31.679648 output: FDT: fdt-1
314 12:32:31.679703 output: Loadables: kernel-1
315 12:32:31.679762 output:
316 12:32:31.679961 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 12:32:31.680065 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 12:32:31.680175 end: 1.6 prepare-tftp-overlay (duration 00:00:39) [common]
319 12:32:31.680277 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:12) [common]
320 12:32:31.680359 No LXC device requested
321 12:32:31.680444 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:32:31.680533 start: 1.8 deploy-device-env (timeout 00:09:12) [common]
323 12:32:31.680614 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:32:31.680700 Checking files for TFTP limit of 4294967296 bytes.
325 12:32:31.681358 end: 1 tftp-deploy (duration 00:00:48) [common]
326 12:32:31.681503 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:32:31.681630 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:32:31.681809 substitutions:
329 12:32:31.681910 - {DTB}: 10605810/tftp-deploy-chfj_5iw/dtb/mt8192-asurada-spherion-r0.dtb
330 12:32:31.682009 - {INITRD}: 10605810/tftp-deploy-chfj_5iw/ramdisk/ramdisk.cpio.gz
331 12:32:31.682103 - {KERNEL}: 10605810/tftp-deploy-chfj_5iw/kernel/Image
332 12:32:31.682195 - {LAVA_MAC}: None
333 12:32:31.682285 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10605810/extract-nfsrootfs-mg6xi24_
334 12:32:31.682382 - {NFS_SERVER_IP}: 192.168.201.1
335 12:32:31.682480 - {PRESEED_CONFIG}: None
336 12:32:31.682574 - {PRESEED_LOCAL}: None
337 12:32:31.682668 - {RAMDISK}: 10605810/tftp-deploy-chfj_5iw/ramdisk/ramdisk.cpio.gz
338 12:32:31.682732 - {ROOT_PART}: None
339 12:32:31.682792 - {ROOT}: None
340 12:32:31.682855 - {SERVER_IP}: 192.168.201.1
341 12:32:31.682913 - {TEE}: None
342 12:32:31.682971 Parsed boot commands:
343 12:32:31.683027 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:32:31.683258 Parsed boot commands: tftpboot 192.168.201.1 10605810/tftp-deploy-chfj_5iw/kernel/image.itb 10605810/tftp-deploy-chfj_5iw/kernel/cmdline
345 12:32:31.683388 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:32:31.683482 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:32:31.683582 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:32:31.683675 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:32:31.683749 Not connected, no need to disconnect.
350 12:32:31.683834 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:32:31.683922 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:32:31.683994 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
353 12:32:31.687505 Setting prompt string to ['lava-test: # ']
354 12:32:31.687871 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:32:31.687985 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:32:31.688094 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:32:31.688189 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:32:31.688394 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 12:32:36.822983 >> Command sent successfully.
360 12:32:36.825355 Returned 0 in 5 seconds
361 12:32:36.925757 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:32:36.926195 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:32:36.926352 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:32:36.926485 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:32:36.926588 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:32:36.926698 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:32:36.927082 [Enter `^Ec?' for help]
369 12:32:37.101006
370 12:32:37.101156
371 12:32:37.101246 F0: 102B 0000
372 12:32:37.101336
373 12:32:37.101432 F3: 1001 0000 [0200]
374 12:32:37.101529
375 12:32:37.104245 F3: 1001 0000
376 12:32:37.104328
377 12:32:37.104398 F7: 102D 0000
378 12:32:37.104462
379 12:32:37.104535 F1: 0000 0000
380 12:32:37.107343
381 12:32:37.107434 V0: 0000 0000 [0001]
382 12:32:37.107503
383 12:32:37.107579 00: 0007 8000
384 12:32:37.111142
385 12:32:37.111251 01: 0000 0000
386 12:32:37.111360
387 12:32:37.111430 BP: 0C00 0209 [0000]
388 12:32:37.111493
389 12:32:37.114859 G0: 1182 0000
390 12:32:37.114961
391 12:32:37.115055 EC: 0000 0021 [4000]
392 12:32:37.115146
393 12:32:37.118049 S7: 0000 0000 [0000]
394 12:32:37.118154
395 12:32:37.118251 CC: 0000 0000 [0001]
396 12:32:37.118342
397 12:32:37.121448 T0: 0000 0040 [010F]
398 12:32:37.121557
399 12:32:37.121652 Jump to BL
400 12:32:37.121751
401 12:32:37.147260
402 12:32:37.147413
403 12:32:37.147491
404 12:32:37.154957 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:32:37.158230 ARM64: Exception handlers installed.
406 12:32:37.161999 ARM64: Testing exception
407 12:32:37.165941 ARM64: Done test exception
408 12:32:37.172733 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:32:37.183825 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:32:37.189933 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:32:37.199903 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:32:37.207067 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:32:37.213247 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:32:37.223908 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:32:37.230676 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:32:37.250472 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:32:37.253125 WDT: Last reset was cold boot
418 12:32:37.257005 SPI1(PAD0) initialized at 2873684 Hz
419 12:32:37.260211 SPI5(PAD0) initialized at 992727 Hz
420 12:32:37.263314 VBOOT: Loading verstage.
421 12:32:37.269915 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:32:37.273733 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:32:37.277113 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:32:37.280369 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:32:37.287444 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:32:37.294044 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:32:37.305133 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
428 12:32:37.305249
429 12:32:37.305370
430 12:32:37.315129 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:32:37.318179 ARM64: Exception handlers installed.
432 12:32:37.321467 ARM64: Testing exception
433 12:32:37.321591 ARM64: Done test exception
434 12:32:37.328625 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:32:37.331976 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:32:37.347447 Probing TPM: . done!
437 12:32:37.347549 TPM ready after 0 ms
438 12:32:37.353930 Connected to device vid:did:rid of 1ae0:0028:00
439 12:32:37.360492 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 12:32:37.418863 Initialized TPM device CR50 revision 0
441 12:32:37.431212 tlcl_send_startup: Startup return code is 0
442 12:32:37.431359 TPM: setup succeeded
443 12:32:37.442924 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:32:37.451633 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:32:37.463829 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:32:37.473242 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:32:37.476538 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:32:37.480620 in-header: 03 07 00 00 08 00 00 00
449 12:32:37.483843 in-data: aa e4 47 04 13 02 00 00
450 12:32:37.487376 Chrome EC: UHEPI supported
451 12:32:37.494725 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:32:37.498507 in-header: 03 ad 00 00 08 00 00 00
453 12:32:37.502024 in-data: 00 20 20 08 00 00 00 00
454 12:32:37.502134 Phase 1
455 12:32:37.505399 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:32:37.513173 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:32:37.516522 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:32:37.520670 Recovery requested (1009000e)
459 12:32:37.529961 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:32:37.536502 tlcl_extend: response is 0
461 12:32:37.545921 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:32:37.552052 tlcl_extend: response is 0
463 12:32:37.559356 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:32:37.579030 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
465 12:32:37.586062 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:32:37.586158
467 12:32:37.586227
468 12:32:37.596679 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:32:37.600648 ARM64: Exception handlers installed.
470 12:32:37.600740 ARM64: Testing exception
471 12:32:37.603982 ARM64: Done test exception
472 12:32:37.624707 pmic_efuse_setting: Set efuses in 11 msecs
473 12:32:37.627924 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:32:37.634995 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:32:37.638366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:32:37.644845 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:32:37.648638 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:32:37.652530 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:32:37.659796 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:32:37.663321 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:32:37.666783 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:32:37.670667 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:32:37.678129 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:32:37.681955 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:32:37.685309 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:32:37.689245 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:32:37.696607 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:32:37.704039 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:32:37.708016 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:32:37.715113 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:32:37.718480 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:32:37.725834 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:32:37.729764 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:32:37.736721 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:32:37.740596 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:32:37.747821 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:32:37.751675 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:32:37.759385 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:32:37.762631 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:32:37.770564 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:32:37.773716 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:32:37.777736 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:32:37.784840 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:32:37.787921 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:32:37.795648 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:32:37.798930 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:32:37.803152 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:32:37.810443 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:32:37.813689 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:32:37.817704 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:32:37.825076 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:32:37.829087 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:32:37.832393 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:32:37.836243 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:32:37.840149 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:32:37.847190 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:32:37.850991 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:32:37.854887 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:32:37.858211 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:32:37.861933 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:32:37.865970 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:32:37.873278 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:32:37.876543 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:32:37.880501 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:32:37.887954 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:32:37.895071 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:32:37.898839 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:32:37.909711 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:32:37.917125 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:32:37.920972 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:32:37.928218 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:32:37.931496 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:32:37.938758 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x5
534 12:32:37.942849 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:32:37.946293 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 12:32:37.953191 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:32:37.961624 [RTC]rtc_get_frequency_meter,154: input=15, output=790
538 12:32:37.971248 [RTC]rtc_get_frequency_meter,154: input=23, output=978
539 12:32:37.981051 [RTC]rtc_get_frequency_meter,154: input=19, output=885
540 12:32:37.990632 [RTC]rtc_get_frequency_meter,154: input=17, output=838
541 12:32:37.999667 [RTC]rtc_get_frequency_meter,154: input=16, output=814
542 12:32:38.009341 [RTC]rtc_get_frequency_meter,154: input=15, output=790
543 12:32:38.019987 [RTC]rtc_get_frequency_meter,154: input=16, output=813
544 12:32:38.023210 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 12:32:38.026510 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 12:32:38.030563 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 12:32:38.037853 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 12:32:38.041578 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 12:32:38.044951 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 12:32:38.048928 ADC[4]: Raw value=902066 ID=7
551 12:32:38.052132 ADC[3]: Raw value=213336 ID=1
552 12:32:38.052251 RAM Code: 0x71
553 12:32:38.055844 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 12:32:38.063503 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 12:32:38.071198 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 12:32:38.077814 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 12:32:38.081803 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 12:32:38.085241 in-header: 03 07 00 00 08 00 00 00
559 12:32:38.085339 in-data: aa e4 47 04 13 02 00 00
560 12:32:38.089222 Chrome EC: UHEPI supported
561 12:32:38.095729 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 12:32:38.099553 in-header: 03 ed 00 00 08 00 00 00
563 12:32:38.103458 in-data: 80 20 60 08 00 00 00 00
564 12:32:38.107159 MRC: failed to locate region type 0.
565 12:32:38.114358 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 12:32:38.118278 DRAM-K: Running full calibration
567 12:32:38.121619 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 12:32:38.124855 header.status = 0x0
569 12:32:38.128958 header.version = 0x6 (expected: 0x6)
570 12:32:38.132314 header.size = 0xd00 (expected: 0xd00)
571 12:32:38.132431 header.flags = 0x0
572 12:32:38.139516 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 12:32:38.157205 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
574 12:32:38.164816 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 12:32:38.168771 dram_init: ddr_geometry: 2
576 12:32:38.168922 [EMI] MDL number = 2
577 12:32:38.172733 [EMI] Get MDL freq = 0
578 12:32:38.172873 dram_init: ddr_type: 0
579 12:32:38.175974 is_discrete_lpddr4: 1
580 12:32:38.179749 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 12:32:38.179887
582 12:32:38.180007
583 12:32:38.180105 [Bian_co] ETT version 0.0.0.1
584 12:32:38.187053 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 12:32:38.187218
586 12:32:38.190874 dramc_set_vcore_voltage set vcore to 650000
587 12:32:38.190994 Read voltage for 800, 4
588 12:32:38.194265 Vio18 = 0
589 12:32:38.194374 Vcore = 650000
590 12:32:38.194472 Vdram = 0
591 12:32:38.197578 Vddq = 0
592 12:32:38.197685 Vmddr = 0
593 12:32:38.197780 dram_init: config_dvfs: 1
594 12:32:38.204318 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 12:32:38.211412 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 12:32:38.214498 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 12:32:38.217686 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 12:32:38.221138 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 12:32:38.224427 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 12:32:38.227702 MEM_TYPE=3, freq_sel=18
601 12:32:38.230991 sv_algorithm_assistance_LP4_1600
602 12:32:38.234290 ============ PULL DRAM RESETB DOWN ============
603 12:32:38.237552 ========== PULL DRAM RESETB DOWN end =========
604 12:32:38.244166 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 12:32:38.247510 ===================================
606 12:32:38.247600 LPDDR4 DRAM CONFIGURATION
607 12:32:38.250934 ===================================
608 12:32:38.254834 EX_ROW_EN[0] = 0x0
609 12:32:38.254922 EX_ROW_EN[1] = 0x0
610 12:32:38.257650 LP4Y_EN = 0x0
611 12:32:38.260870 WORK_FSP = 0x0
612 12:32:38.260958 WL = 0x2
613 12:32:38.264730 RL = 0x2
614 12:32:38.264818 BL = 0x2
615 12:32:38.267795 RPST = 0x0
616 12:32:38.267883 RD_PRE = 0x0
617 12:32:38.271081 WR_PRE = 0x1
618 12:32:38.271196 WR_PST = 0x0
619 12:32:38.274394 DBI_WR = 0x0
620 12:32:38.274482 DBI_RD = 0x0
621 12:32:38.278011 OTF = 0x1
622 12:32:38.281275 ===================================
623 12:32:38.284490 ===================================
624 12:32:38.284578 ANA top config
625 12:32:38.287821 ===================================
626 12:32:38.291635 DLL_ASYNC_EN = 0
627 12:32:38.294968 ALL_SLAVE_EN = 1
628 12:32:38.295056 NEW_RANK_MODE = 1
629 12:32:38.297693 DLL_IDLE_MODE = 1
630 12:32:38.300989 LP45_APHY_COMB_EN = 1
631 12:32:38.304860 TX_ODT_DIS = 1
632 12:32:38.304976 NEW_8X_MODE = 1
633 12:32:38.308018 ===================================
634 12:32:38.311400 ===================================
635 12:32:38.314664 data_rate = 1600
636 12:32:38.318261 CKR = 1
637 12:32:38.321635 DQ_P2S_RATIO = 8
638 12:32:38.324980 ===================================
639 12:32:38.328235 CA_P2S_RATIO = 8
640 12:32:38.331723 DQ_CA_OPEN = 0
641 12:32:38.331828 DQ_SEMI_OPEN = 0
642 12:32:38.334984 CA_SEMI_OPEN = 0
643 12:32:38.338348 CA_FULL_RATE = 0
644 12:32:38.341558 DQ_CKDIV4_EN = 1
645 12:32:38.344732 CA_CKDIV4_EN = 1
646 12:32:38.347881 CA_PREDIV_EN = 0
647 12:32:38.347958 PH8_DLY = 0
648 12:32:38.351326 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 12:32:38.354605 DQ_AAMCK_DIV = 4
650 12:32:38.357918 CA_AAMCK_DIV = 4
651 12:32:38.361077 CA_ADMCK_DIV = 4
652 12:32:38.364443 DQ_TRACK_CA_EN = 0
653 12:32:38.364532 CA_PICK = 800
654 12:32:38.368370 CA_MCKIO = 800
655 12:32:38.371521 MCKIO_SEMI = 0
656 12:32:38.374786 PLL_FREQ = 3068
657 12:32:38.378574 DQ_UI_PI_RATIO = 32
658 12:32:38.381934 CA_UI_PI_RATIO = 0
659 12:32:38.382057 ===================================
660 12:32:38.385754 ===================================
661 12:32:38.389513 memory_type:LPDDR4
662 12:32:38.392896 GP_NUM : 10
663 12:32:38.393008 SRAM_EN : 1
664 12:32:38.396777 MD32_EN : 0
665 12:32:38.400212 ===================================
666 12:32:38.400308 [ANA_INIT] >>>>>>>>>>>>>>
667 12:32:38.403532 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 12:32:38.407513 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 12:32:38.410634 ===================================
670 12:32:38.413793 data_rate = 1600,PCW = 0X7600
671 12:32:38.417041 ===================================
672 12:32:38.420970 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 12:32:38.424333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 12:32:38.430677 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 12:32:38.433980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 12:32:38.437402 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 12:32:38.441170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 12:32:38.444442 [ANA_INIT] flow start
679 12:32:38.447609 [ANA_INIT] PLL >>>>>>>>
680 12:32:38.447718 [ANA_INIT] PLL <<<<<<<<
681 12:32:38.450909 [ANA_INIT] MIDPI >>>>>>>>
682 12:32:38.454342 [ANA_INIT] MIDPI <<<<<<<<
683 12:32:38.457439 [ANA_INIT] DLL >>>>>>>>
684 12:32:38.457546 [ANA_INIT] flow end
685 12:32:38.461467 ============ LP4 DIFF to SE enter ============
686 12:32:38.468067 ============ LP4 DIFF to SE exit ============
687 12:32:38.468161 [ANA_INIT] <<<<<<<<<<<<<
688 12:32:38.471279 [Flow] Enable top DCM control >>>>>
689 12:32:38.474495 [Flow] Enable top DCM control <<<<<
690 12:32:38.477715 Enable DLL master slave shuffle
691 12:32:38.484660 ==============================================================
692 12:32:38.484782 Gating Mode config
693 12:32:38.490845 ==============================================================
694 12:32:38.494738 Config description:
695 12:32:38.500888 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 12:32:38.508020 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 12:32:38.514445 SELPH_MODE 0: By rank 1: By Phase
698 12:32:38.521010 ==============================================================
699 12:32:38.521128 GAT_TRACK_EN = 1
700 12:32:38.524340 RX_GATING_MODE = 2
701 12:32:38.527425 RX_GATING_TRACK_MODE = 2
702 12:32:38.531299 SELPH_MODE = 1
703 12:32:38.534670 PICG_EARLY_EN = 1
704 12:32:38.538004 VALID_LAT_VALUE = 1
705 12:32:38.544362 ==============================================================
706 12:32:38.547601 Enter into Gating configuration >>>>
707 12:32:38.550750 Exit from Gating configuration <<<<
708 12:32:38.554792 Enter into DVFS_PRE_config >>>>>
709 12:32:38.564467 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 12:32:38.567838 Exit from DVFS_PRE_config <<<<<
711 12:32:38.570917 Enter into PICG configuration >>>>
712 12:32:38.574164 Exit from PICG configuration <<<<
713 12:32:38.577604 [RX_INPUT] configuration >>>>>
714 12:32:38.577718 [RX_INPUT] configuration <<<<<
715 12:32:38.584547 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 12:32:38.591572 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 12:32:38.594740 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 12:32:38.601570 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 12:32:38.608152 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 12:32:38.614816 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 12:32:38.618018 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 12:32:38.621425 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 12:32:38.624699 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 12:32:38.631590 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 12:32:38.634820 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 12:32:38.638213 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:32:38.641449 ===================================
728 12:32:38.644694 LPDDR4 DRAM CONFIGURATION
729 12:32:38.648507 ===================================
730 12:32:38.651694 EX_ROW_EN[0] = 0x0
731 12:32:38.651822 EX_ROW_EN[1] = 0x0
732 12:32:38.654960 LP4Y_EN = 0x0
733 12:32:38.655049 WORK_FSP = 0x0
734 12:32:38.658346 WL = 0x2
735 12:32:38.658434 RL = 0x2
736 12:32:38.661730 BL = 0x2
737 12:32:38.661818 RPST = 0x0
738 12:32:38.665077 RD_PRE = 0x0
739 12:32:38.665164 WR_PRE = 0x1
740 12:32:38.668344 WR_PST = 0x0
741 12:32:38.668432 DBI_WR = 0x0
742 12:32:38.671566 DBI_RD = 0x0
743 12:32:38.671654 OTF = 0x1
744 12:32:38.674840 ===================================
745 12:32:38.678023 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 12:32:38.684711 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 12:32:38.688506 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 12:32:38.691782 ===================================
749 12:32:38.694842 LPDDR4 DRAM CONFIGURATION
750 12:32:38.697940 ===================================
751 12:32:38.698054 EX_ROW_EN[0] = 0x10
752 12:32:38.701769 EX_ROW_EN[1] = 0x0
753 12:32:38.704973 LP4Y_EN = 0x0
754 12:32:38.705085 WORK_FSP = 0x0
755 12:32:38.707921 WL = 0x2
756 12:32:38.708027 RL = 0x2
757 12:32:38.711256 BL = 0x2
758 12:32:38.711371 RPST = 0x0
759 12:32:38.715077 RD_PRE = 0x0
760 12:32:38.715182 WR_PRE = 0x1
761 12:32:38.718422 WR_PST = 0x0
762 12:32:38.718531 DBI_WR = 0x0
763 12:32:38.721696 DBI_RD = 0x0
764 12:32:38.721803 OTF = 0x1
765 12:32:38.724946 ===================================
766 12:32:38.731625 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 12:32:38.735338 nWR fixed to 40
768 12:32:38.739266 [ModeRegInit_LP4] CH0 RK0
769 12:32:38.739390 [ModeRegInit_LP4] CH0 RK1
770 12:32:38.741957 [ModeRegInit_LP4] CH1 RK0
771 12:32:38.745280 [ModeRegInit_LP4] CH1 RK1
772 12:32:38.745390 match AC timing 13
773 12:32:38.752459 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 12:32:38.755651 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 12:32:38.758952 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 12:32:38.765370 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 12:32:38.768665 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 12:32:38.772062 [EMI DOE] emi_dcm 0
779 12:32:38.775149 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 12:32:38.775267 ==
781 12:32:38.778587 Dram Type= 6, Freq= 0, CH_0, rank 0
782 12:32:38.781871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 12:32:38.781991 ==
784 12:32:38.788501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 12:32:38.795102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 12:32:38.803297 [CA 0] Center 37 (7~68) winsize 62
787 12:32:38.806308 [CA 1] Center 37 (6~68) winsize 63
788 12:32:38.809893 [CA 2] Center 35 (5~66) winsize 62
789 12:32:38.812900 [CA 3] Center 34 (4~65) winsize 62
790 12:32:38.816638 [CA 4] Center 34 (3~65) winsize 63
791 12:32:38.819939 [CA 5] Center 33 (3~64) winsize 62
792 12:32:38.820052
793 12:32:38.823173 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 12:32:38.823283
795 12:32:38.826405 [CATrainingPosCal] consider 1 rank data
796 12:32:38.829719 u2DelayCellTimex100 = 270/100 ps
797 12:32:38.833007 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 12:32:38.836308 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 12:32:38.843336 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 12:32:38.846570 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 12:32:38.849831 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 12:32:38.853087 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 12:32:38.853199
804 12:32:38.856236 CA PerBit enable=1, Macro0, CA PI delay=33
805 12:32:38.856346
806 12:32:38.859539 [CBTSetCACLKResult] CA Dly = 33
807 12:32:38.859619 CS Dly: 5 (0~36)
808 12:32:38.859721 ==
809 12:32:38.862851 Dram Type= 6, Freq= 0, CH_0, rank 1
810 12:32:38.869448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 12:32:38.869565 ==
812 12:32:38.872822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 12:32:38.879366 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 12:32:38.889222 [CA 0] Center 37 (7~68) winsize 62
815 12:32:38.892557 [CA 1] Center 37 (6~68) winsize 63
816 12:32:38.895813 [CA 2] Center 35 (4~66) winsize 63
817 12:32:38.899203 [CA 3] Center 35 (4~66) winsize 63
818 12:32:38.902506 [CA 4] Center 34 (4~65) winsize 62
819 12:32:38.905825 [CA 5] Center 33 (3~64) winsize 62
820 12:32:38.905933
821 12:32:38.909192 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 12:32:38.909299
823 12:32:38.912830 [CATrainingPosCal] consider 2 rank data
824 12:32:38.915879 u2DelayCellTimex100 = 270/100 ps
825 12:32:38.919725 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 12:32:38.922934 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
827 12:32:38.929566 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 12:32:38.932609 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 12:32:38.936479 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
830 12:32:38.939782 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 12:32:38.939879
832 12:32:38.942861 CA PerBit enable=1, Macro0, CA PI delay=33
833 12:32:38.942976
834 12:32:38.945991 [CBTSetCACLKResult] CA Dly = 33
835 12:32:38.946075 CS Dly: 6 (0~38)
836 12:32:38.946143
837 12:32:38.949172 ----->DramcWriteLeveling(PI) begin...
838 12:32:38.952473 ==
839 12:32:38.956413 Dram Type= 6, Freq= 0, CH_0, rank 0
840 12:32:38.960278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 12:32:38.960382 ==
842 12:32:38.963613 Write leveling (Byte 0): 30 => 30
843 12:32:38.963709 Write leveling (Byte 1): 30 => 30
844 12:32:38.967559 DramcWriteLeveling(PI) end<-----
845 12:32:38.967652
846 12:32:38.967723 ==
847 12:32:38.970925 Dram Type= 6, Freq= 0, CH_0, rank 0
848 12:32:38.974249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 12:32:38.974367 ==
850 12:32:38.978114 [Gating] SW mode calibration
851 12:32:38.984766 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 12:32:38.992001 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 12:32:38.995363 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 12:32:38.998645 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 12:32:39.005380 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
856 12:32:39.008638 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:32:39.012460 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:32:39.019084 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:32:39.022298 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:32:39.025591 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:32:39.028646 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:32:39.035327 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:32:39.039030 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:32:39.042128 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:32:39.049281 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:32:39.052544 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:32:39.055760 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:32:39.062088 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:32:39.065582 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:32:39.068832 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 12:32:39.075389 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 12:32:39.078582 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
873 12:32:39.082476 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:32:39.088992 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:32:39.092346 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:32:39.095782 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:32:39.102227 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:32:39.105564 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:32:39.108850 0 9 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
880 12:32:39.115487 0 9 12 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (1 1)
881 12:32:39.118623 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:32:39.121836 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:32:39.125834 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 12:32:39.132335 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 12:32:39.135346 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 12:32:39.138740 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 12:32:39.145429 0 10 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
888 12:32:39.149002 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
889 12:32:39.152109 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:32:39.158972 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:32:39.162380 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 12:32:39.165816 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 12:32:39.172443 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 12:32:39.175714 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 12:32:39.179112 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
896 12:32:39.185819 0 11 12 | B1->B0 | 3939 4242 | 0 1 | (0 0) (0 0)
897 12:32:39.188960 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:32:39.192270 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:32:39.195557 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 12:32:39.202192 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 12:32:39.205583 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 12:32:39.208868 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 12:32:39.216039 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 12:32:39.219272 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:32:39.222770 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:32:39.229126 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:32:39.232438 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:32:39.235712 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:32:39.242500 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:32:39.245892 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:32:39.249184 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:32:39.256191 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:32:39.259242 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:32:39.262420 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:32:39.266201 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 12:32:39.272531 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 12:32:39.275809 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 12:32:39.279718 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 12:32:39.286261 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 12:32:39.289467 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 12:32:39.292677 Total UI for P1: 0, mck2ui 16
922 12:32:39.295874 best dqsien dly found for B0: ( 0, 14, 8)
923 12:32:39.299885 Total UI for P1: 0, mck2ui 16
924 12:32:39.303157 best dqsien dly found for B1: ( 0, 14, 10)
925 12:32:39.306024 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 12:32:39.309328 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 12:32:39.309415
928 12:32:39.312759 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 12:32:39.316595 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 12:32:39.319969 [Gating] SW calibration Done
931 12:32:39.320082 ==
932 12:32:39.323193 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:32:39.326539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:32:39.326650 ==
935 12:32:39.329854 RX Vref Scan: 0
936 12:32:39.329936
937 12:32:39.333038 RX Vref 0 -> 0, step: 1
938 12:32:39.333146
939 12:32:39.333257 RX Delay -130 -> 252, step: 16
940 12:32:39.339562 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 12:32:39.342775 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 12:32:39.346680 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 12:32:39.349910 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 12:32:39.353313 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 12:32:39.359919 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 12:32:39.363138 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 12:32:39.366197 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
948 12:32:39.369354 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 12:32:39.373007 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 12:32:39.379827 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 12:32:39.382941 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 12:32:39.386107 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 12:32:39.389445 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
954 12:32:39.396615 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 12:32:39.399841 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 12:32:39.399924 ==
957 12:32:39.403150 Dram Type= 6, Freq= 0, CH_0, rank 0
958 12:32:39.406568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 12:32:39.406660 ==
960 12:32:39.406734 DQS Delay:
961 12:32:39.409863 DQS0 = 0, DQS1 = 0
962 12:32:39.409942 DQM Delay:
963 12:32:39.413033 DQM0 = 85, DQM1 = 77
964 12:32:39.413115 DQ Delay:
965 12:32:39.416439 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 12:32:39.419731 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =85
967 12:32:39.423115 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
968 12:32:39.426397 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
969 12:32:39.426504
970 12:32:39.426603
971 12:32:39.426698 ==
972 12:32:39.429503 Dram Type= 6, Freq= 0, CH_0, rank 0
973 12:32:39.432920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 12:32:39.436217 ==
975 12:32:39.436303
976 12:32:39.436371
977 12:32:39.436435 TX Vref Scan disable
978 12:32:39.439430 == TX Byte 0 ==
979 12:32:39.442809 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
980 12:32:39.446719 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
981 12:32:39.449836 == TX Byte 1 ==
982 12:32:39.453001 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
983 12:32:39.456442 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
984 12:32:39.456530 ==
985 12:32:39.459566 Dram Type= 6, Freq= 0, CH_0, rank 0
986 12:32:39.466119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 12:32:39.466205 ==
988 12:32:39.478076 TX Vref=22, minBit 5, minWin=27, winSum=441
989 12:32:39.481332 TX Vref=24, minBit 3, minWin=27, winSum=442
990 12:32:39.484975 TX Vref=26, minBit 5, minWin=27, winSum=446
991 12:32:39.488429 TX Vref=28, minBit 12, minWin=27, winSum=451
992 12:32:39.491480 TX Vref=30, minBit 12, minWin=27, winSum=453
993 12:32:39.498705 TX Vref=32, minBit 2, minWin=28, winSum=455
994 12:32:39.501947 [TxChooseVref] Worse bit 2, Min win 28, Win sum 455, Final Vref 32
995 12:32:39.502054
996 12:32:39.505114 Final TX Range 1 Vref 32
997 12:32:39.505225
998 12:32:39.505325 ==
999 12:32:39.508567 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 12:32:39.511726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 12:32:39.511837 ==
1002 12:32:39.511934
1003 12:32:39.515125
1004 12:32:39.515233 TX Vref Scan disable
1005 12:32:39.518456 == TX Byte 0 ==
1006 12:32:39.522127 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1007 12:32:39.525538 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1008 12:32:39.528717 == TX Byte 1 ==
1009 12:32:39.531931 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1010 12:32:39.535225 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1011 12:32:39.535333
1012 12:32:39.538599 [DATLAT]
1013 12:32:39.538713 Freq=800, CH0 RK0
1014 12:32:39.538813
1015 12:32:39.541632 DATLAT Default: 0xa
1016 12:32:39.541742 0, 0xFFFF, sum = 0
1017 12:32:39.544956 1, 0xFFFF, sum = 0
1018 12:32:39.545096 2, 0xFFFF, sum = 0
1019 12:32:39.548847 3, 0xFFFF, sum = 0
1020 12:32:39.548972 4, 0xFFFF, sum = 0
1021 12:32:39.552029 5, 0xFFFF, sum = 0
1022 12:32:39.552144 6, 0xFFFF, sum = 0
1023 12:32:39.555227 7, 0xFFFF, sum = 0
1024 12:32:39.555339 8, 0xFFFF, sum = 0
1025 12:32:39.558589 9, 0x0, sum = 1
1026 12:32:39.558698 10, 0x0, sum = 2
1027 12:32:39.561810 11, 0x0, sum = 3
1028 12:32:39.561920 12, 0x0, sum = 4
1029 12:32:39.565024 best_step = 10
1030 12:32:39.565133
1031 12:32:39.565231 ==
1032 12:32:39.568970 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 12:32:39.571585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 12:32:39.571691 ==
1035 12:32:39.575420 RX Vref Scan: 1
1036 12:32:39.575532
1037 12:32:39.575628 Set Vref Range= 32 -> 127
1038 12:32:39.575726
1039 12:32:39.578521 RX Vref 32 -> 127, step: 1
1040 12:32:39.578627
1041 12:32:39.582060 RX Delay -95 -> 252, step: 8
1042 12:32:39.582166
1043 12:32:39.585128 Set Vref, RX VrefLevel [Byte0]: 32
1044 12:32:39.588428 [Byte1]: 32
1045 12:32:39.588552
1046 12:32:39.592825 Set Vref, RX VrefLevel [Byte0]: 33
1047 12:32:39.596137 [Byte1]: 33
1048 12:32:39.596249
1049 12:32:39.599409 Set Vref, RX VrefLevel [Byte0]: 34
1050 12:32:39.602803 [Byte1]: 34
1051 12:32:39.606133
1052 12:32:39.606264 Set Vref, RX VrefLevel [Byte0]: 35
1053 12:32:39.609483 [Byte1]: 35
1054 12:32:39.613999
1055 12:32:39.614114 Set Vref, RX VrefLevel [Byte0]: 36
1056 12:32:39.617374 [Byte1]: 36
1057 12:32:39.622003
1058 12:32:39.622117 Set Vref, RX VrefLevel [Byte0]: 37
1059 12:32:39.625199 [Byte1]: 37
1060 12:32:39.629340
1061 12:32:39.629456 Set Vref, RX VrefLevel [Byte0]: 38
1062 12:32:39.632523 [Byte1]: 38
1063 12:32:39.637359
1064 12:32:39.637481 Set Vref, RX VrefLevel [Byte0]: 39
1065 12:32:39.640761 [Byte1]: 39
1066 12:32:39.644646
1067 12:32:39.644732 Set Vref, RX VrefLevel [Byte0]: 40
1068 12:32:39.647859 [Byte1]: 40
1069 12:32:39.652411
1070 12:32:39.652497 Set Vref, RX VrefLevel [Byte0]: 41
1071 12:32:39.655691 [Byte1]: 41
1072 12:32:39.659526
1073 12:32:39.659610 Set Vref, RX VrefLevel [Byte0]: 42
1074 12:32:39.662668 [Byte1]: 42
1075 12:32:39.667219
1076 12:32:39.667331 Set Vref, RX VrefLevel [Byte0]: 43
1077 12:32:39.670234 [Byte1]: 43
1078 12:32:39.675034
1079 12:32:39.675119 Set Vref, RX VrefLevel [Byte0]: 44
1080 12:32:39.678125 [Byte1]: 44
1081 12:32:39.682532
1082 12:32:39.682618 Set Vref, RX VrefLevel [Byte0]: 45
1083 12:32:39.685833 [Byte1]: 45
1084 12:32:39.689571
1085 12:32:39.689657 Set Vref, RX VrefLevel [Byte0]: 46
1086 12:32:39.693514 [Byte1]: 46
1087 12:32:39.697820
1088 12:32:39.697906 Set Vref, RX VrefLevel [Byte0]: 47
1089 12:32:39.701031 [Byte1]: 47
1090 12:32:39.705132
1091 12:32:39.705218 Set Vref, RX VrefLevel [Byte0]: 48
1092 12:32:39.708471 [Byte1]: 48
1093 12:32:39.712919
1094 12:32:39.713004 Set Vref, RX VrefLevel [Byte0]: 49
1095 12:32:39.716227 [Byte1]: 49
1096 12:32:39.720099
1097 12:32:39.720184 Set Vref, RX VrefLevel [Byte0]: 50
1098 12:32:39.723362 [Byte1]: 50
1099 12:32:39.727967
1100 12:32:39.728071 Set Vref, RX VrefLevel [Byte0]: 51
1101 12:32:39.731224 [Byte1]: 51
1102 12:32:39.735751
1103 12:32:39.735863 Set Vref, RX VrefLevel [Byte0]: 52
1104 12:32:39.738470 [Byte1]: 52
1105 12:32:39.743037
1106 12:32:39.743152 Set Vref, RX VrefLevel [Byte0]: 53
1107 12:32:39.746466 [Byte1]: 53
1108 12:32:39.750279
1109 12:32:39.750389 Set Vref, RX VrefLevel [Byte0]: 54
1110 12:32:39.754251 [Byte1]: 54
1111 12:32:39.758153
1112 12:32:39.758256 Set Vref, RX VrefLevel [Byte0]: 55
1113 12:32:39.761403 [Byte1]: 55
1114 12:32:39.766029
1115 12:32:39.766114 Set Vref, RX VrefLevel [Byte0]: 56
1116 12:32:39.769260 [Byte1]: 56
1117 12:32:39.773808
1118 12:32:39.773894 Set Vref, RX VrefLevel [Byte0]: 57
1119 12:32:39.776379 [Byte1]: 57
1120 12:32:39.780971
1121 12:32:39.781055 Set Vref, RX VrefLevel [Byte0]: 58
1122 12:32:39.784053 [Byte1]: 58
1123 12:32:39.788557
1124 12:32:39.788646 Set Vref, RX VrefLevel [Byte0]: 59
1125 12:32:39.791844 [Byte1]: 59
1126 12:32:39.796228
1127 12:32:39.796313 Set Vref, RX VrefLevel [Byte0]: 60
1128 12:32:39.799353 [Byte1]: 60
1129 12:32:39.803665
1130 12:32:39.803778 Set Vref, RX VrefLevel [Byte0]: 61
1131 12:32:39.806969 [Byte1]: 61
1132 12:32:39.811624
1133 12:32:39.811732 Set Vref, RX VrefLevel [Byte0]: 62
1134 12:32:39.814911 [Byte1]: 62
1135 12:32:39.818984
1136 12:32:39.819098 Set Vref, RX VrefLevel [Byte0]: 63
1137 12:32:39.825669 [Byte1]: 63
1138 12:32:39.825786
1139 12:32:39.828879 Set Vref, RX VrefLevel [Byte0]: 64
1140 12:32:39.832299 [Byte1]: 64
1141 12:32:39.832388
1142 12:32:39.835721 Set Vref, RX VrefLevel [Byte0]: 65
1143 12:32:39.839000 [Byte1]: 65
1144 12:32:39.839085
1145 12:32:39.842287 Set Vref, RX VrefLevel [Byte0]: 66
1146 12:32:39.845760 [Byte1]: 66
1147 12:32:39.849071
1148 12:32:39.849189 Set Vref, RX VrefLevel [Byte0]: 67
1149 12:32:39.852943 [Byte1]: 67
1150 12:32:39.856689
1151 12:32:39.856804 Set Vref, RX VrefLevel [Byte0]: 68
1152 12:32:39.860127 [Byte1]: 68
1153 12:32:39.864605
1154 12:32:39.864717 Set Vref, RX VrefLevel [Byte0]: 69
1155 12:32:39.867919 [Byte1]: 69
1156 12:32:39.872446
1157 12:32:39.872555 Set Vref, RX VrefLevel [Byte0]: 70
1158 12:32:39.875711 [Byte1]: 70
1159 12:32:39.879579
1160 12:32:39.879664 Set Vref, RX VrefLevel [Byte0]: 71
1161 12:32:39.882874 [Byte1]: 71
1162 12:32:39.887081
1163 12:32:39.887167 Set Vref, RX VrefLevel [Byte0]: 72
1164 12:32:39.890408 [Byte1]: 72
1165 12:32:39.894840
1166 12:32:39.894924 Set Vref, RX VrefLevel [Byte0]: 73
1167 12:32:39.898116 [Byte1]: 73
1168 12:32:39.902525
1169 12:32:39.902660 Set Vref, RX VrefLevel [Byte0]: 74
1170 12:32:39.905662 [Byte1]: 74
1171 12:32:39.910126
1172 12:32:39.910249 Set Vref, RX VrefLevel [Byte0]: 75
1173 12:32:39.913358 [Byte1]: 75
1174 12:32:39.917996
1175 12:32:39.918100 Set Vref, RX VrefLevel [Byte0]: 76
1176 12:32:39.921344 [Byte1]: 76
1177 12:32:39.925378
1178 12:32:39.925508 Final RX Vref Byte 0 = 62 to rank0
1179 12:32:39.928562 Final RX Vref Byte 1 = 59 to rank0
1180 12:32:39.931902 Final RX Vref Byte 0 = 62 to rank1
1181 12:32:39.935202 Final RX Vref Byte 1 = 59 to rank1==
1182 12:32:39.938563 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 12:32:39.945186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 12:32:39.945272 ==
1185 12:32:39.945338 DQS Delay:
1186 12:32:39.945398 DQS0 = 0, DQS1 = 0
1187 12:32:39.948392 DQM Delay:
1188 12:32:39.948474 DQM0 = 88, DQM1 = 79
1189 12:32:39.952646 DQ Delay:
1190 12:32:39.955083 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1191 12:32:39.958608 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1192 12:32:39.961816 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1193 12:32:39.964975 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1194 12:32:39.965082
1195 12:32:39.965175
1196 12:32:39.971621 [DQSOSCAuto] RK0, (LSB)MR18= 0x280f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 399 ps
1197 12:32:39.974854 CH0 RK0: MR19=606, MR18=280F
1198 12:32:39.981636 CH0_RK0: MR19=0x606, MR18=0x280F, DQSOSC=399, MR23=63, INC=92, DEC=61
1199 12:32:39.981756
1200 12:32:39.985409 ----->DramcWriteLeveling(PI) begin...
1201 12:32:39.985514 ==
1202 12:32:39.988412 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 12:32:39.991676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 12:32:39.991781 ==
1205 12:32:39.994885 Write leveling (Byte 0): 30 => 30
1206 12:32:39.998820 Write leveling (Byte 1): 28 => 28
1207 12:32:40.001803 DramcWriteLeveling(PI) end<-----
1208 12:32:40.001912
1209 12:32:40.002014 ==
1210 12:32:40.005001 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 12:32:40.008780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 12:32:40.008900 ==
1213 12:32:40.012055 [Gating] SW mode calibration
1214 12:32:40.018591 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 12:32:40.025080 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 12:32:40.028252 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 12:32:40.031620 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1218 12:32:40.079411 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1219 12:32:40.079562 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:32:40.079861 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:32:40.079960 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:32:40.080051 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:32:40.080591 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:32:40.080692 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:32:40.080960 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:32:40.081104 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:32:40.081233 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:32:40.123165 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:32:40.123309 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:32:40.123610 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:32:40.123709 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:32:40.123806 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1233 12:32:40.123900 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1234 12:32:40.123990 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1235 12:32:40.124082 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:32:40.124186 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:32:40.124276 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:32:40.167544 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:32:40.167712 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 12:32:40.167984 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 12:32:40.168083 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:32:40.168154 0 9 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
1243 12:32:40.168222 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1244 12:32:40.168288 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 12:32:40.168350 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 12:32:40.168423 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 12:32:40.168484 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 12:32:40.168546 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 12:32:40.174811 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
1250 12:32:40.178027 0 10 8 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (1 1)
1251 12:32:40.181404 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 12:32:40.188018 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 12:32:40.191853 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 12:32:40.195117 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 12:32:40.198228 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 12:32:40.205579 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 12:32:40.208754 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1258 12:32:40.212687 0 11 8 | B1->B0 | 2b2b 4242 | 1 0 | (0 0) (0 0)
1259 12:32:40.216542 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1260 12:32:40.223489 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 12:32:40.226808 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 12:32:40.230165 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 12:32:40.233928 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 12:32:40.240627 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 12:32:40.243923 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 12:32:40.247194 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1267 12:32:40.253749 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1268 12:32:40.257010 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 12:32:40.260379 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 12:32:40.266811 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 12:32:40.270791 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 12:32:40.274046 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 12:32:40.280686 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 12:32:40.283991 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 12:32:40.287240 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 12:32:40.293826 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 12:32:40.297124 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 12:32:40.300303 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 12:32:40.306941 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 12:32:40.310106 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 12:32:40.313857 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1282 12:32:40.317052 Total UI for P1: 0, mck2ui 16
1283 12:32:40.320236 best dqsien dly found for B0: ( 0, 14, 2)
1284 12:32:40.323322 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1285 12:32:40.330379 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 12:32:40.333624 Total UI for P1: 0, mck2ui 16
1287 12:32:40.336905 best dqsien dly found for B1: ( 0, 14, 8)
1288 12:32:40.340244 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1289 12:32:40.343486 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1290 12:32:40.343584
1291 12:32:40.346716 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1292 12:32:40.350063 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1293 12:32:40.353904 [Gating] SW calibration Done
1294 12:32:40.353987 ==
1295 12:32:40.356693 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 12:32:40.360584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 12:32:40.360670 ==
1298 12:32:40.363807 RX Vref Scan: 0
1299 12:32:40.363892
1300 12:32:40.363958 RX Vref 0 -> 0, step: 1
1301 12:32:40.364021
1302 12:32:40.367059 RX Delay -130 -> 252, step: 16
1303 12:32:40.370445 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1304 12:32:40.376937 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1305 12:32:40.380144 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1306 12:32:40.383510 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1307 12:32:40.386905 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1308 12:32:40.390212 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1309 12:32:40.397366 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1310 12:32:40.400558 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1311 12:32:40.403809 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1312 12:32:40.407099 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1313 12:32:40.410350 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1314 12:32:40.416917 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1315 12:32:40.420142 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1316 12:32:40.423360 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1317 12:32:40.427294 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1318 12:32:40.430313 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1319 12:32:40.434055 ==
1320 12:32:40.436800 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 12:32:40.440758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 12:32:40.440846 ==
1323 12:32:40.440914 DQS Delay:
1324 12:32:40.443945 DQS0 = 0, DQS1 = 0
1325 12:32:40.444031 DQM Delay:
1326 12:32:40.447195 DQM0 = 87, DQM1 = 79
1327 12:32:40.447310 DQ Delay:
1328 12:32:40.450482 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1329 12:32:40.453840 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
1330 12:32:40.457140 DQ8 =69, DQ9 =77, DQ10 =77, DQ11 =77
1331 12:32:40.460483 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1332 12:32:40.460590
1333 12:32:40.460693
1334 12:32:40.460791 ==
1335 12:32:40.463736 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 12:32:40.466891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 12:32:40.467005 ==
1338 12:32:40.467105
1339 12:32:40.467198
1340 12:32:40.470248 TX Vref Scan disable
1341 12:32:40.473442 == TX Byte 0 ==
1342 12:32:40.476873 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1343 12:32:40.480179 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1344 12:32:40.483515 == TX Byte 1 ==
1345 12:32:40.486808 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1346 12:32:40.490237 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1347 12:32:40.490356 ==
1348 12:32:40.493615 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 12:32:40.496852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 12:32:40.500012 ==
1351 12:32:40.511905 TX Vref=22, minBit 2, minWin=27, winSum=443
1352 12:32:40.515073 TX Vref=24, minBit 3, minWin=27, winSum=449
1353 12:32:40.518399 TX Vref=26, minBit 3, minWin=27, winSum=447
1354 12:32:40.522109 TX Vref=28, minBit 12, minWin=27, winSum=451
1355 12:32:40.525407 TX Vref=30, minBit 0, minWin=28, winSum=455
1356 12:32:40.531781 TX Vref=32, minBit 3, minWin=28, winSum=457
1357 12:32:40.535005 [TxChooseVref] Worse bit 3, Min win 28, Win sum 457, Final Vref 32
1358 12:32:40.535114
1359 12:32:40.538199 Final TX Range 1 Vref 32
1360 12:32:40.538316
1361 12:32:40.538426 ==
1362 12:32:40.541684 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 12:32:40.544909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 12:32:40.545017 ==
1365 12:32:40.548221
1366 12:32:40.548298
1367 12:32:40.548362 TX Vref Scan disable
1368 12:32:40.552060 == TX Byte 0 ==
1369 12:32:40.555509 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1370 12:32:40.562050 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1371 12:32:40.562154 == TX Byte 1 ==
1372 12:32:40.565447 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1373 12:32:40.571513 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1374 12:32:40.571629
1375 12:32:40.571703 [DATLAT]
1376 12:32:40.571765 Freq=800, CH0 RK1
1377 12:32:40.571824
1378 12:32:40.575267 DATLAT Default: 0xa
1379 12:32:40.575358 0, 0xFFFF, sum = 0
1380 12:32:40.578559 1, 0xFFFF, sum = 0
1381 12:32:40.581800 2, 0xFFFF, sum = 0
1382 12:32:40.581884 3, 0xFFFF, sum = 0
1383 12:32:40.585111 4, 0xFFFF, sum = 0
1384 12:32:40.585195 5, 0xFFFF, sum = 0
1385 12:32:40.588501 6, 0xFFFF, sum = 0
1386 12:32:40.588585 7, 0xFFFF, sum = 0
1387 12:32:40.591699 8, 0xFFFF, sum = 0
1388 12:32:40.591797 9, 0x0, sum = 1
1389 12:32:40.595155 10, 0x0, sum = 2
1390 12:32:40.595237 11, 0x0, sum = 3
1391 12:32:40.595302 12, 0x0, sum = 4
1392 12:32:40.598300 best_step = 10
1393 12:32:40.598381
1394 12:32:40.598444 ==
1395 12:32:40.601451 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 12:32:40.604805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 12:32:40.604887 ==
1398 12:32:40.608511 RX Vref Scan: 0
1399 12:32:40.608623
1400 12:32:40.608686 RX Vref 0 -> 0, step: 1
1401 12:32:40.611828
1402 12:32:40.611936 RX Delay -95 -> 252, step: 8
1403 12:32:40.618309 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1404 12:32:40.621685 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1405 12:32:40.625469 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1406 12:32:40.628558 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1407 12:32:40.632077 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1408 12:32:40.638502 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1409 12:32:40.641616 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1410 12:32:40.645462 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1411 12:32:40.648843 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1412 12:32:40.652175 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1413 12:32:40.658268 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1414 12:32:40.661636 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1415 12:32:40.665760 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1416 12:32:40.668817 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1417 12:32:40.672271 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1418 12:32:40.678563 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1419 12:32:40.678645 ==
1420 12:32:40.682233 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 12:32:40.685576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 12:32:40.685658 ==
1423 12:32:40.685723 DQS Delay:
1424 12:32:40.688768 DQS0 = 0, DQS1 = 0
1425 12:32:40.688849 DQM Delay:
1426 12:32:40.692119 DQM0 = 87, DQM1 = 78
1427 12:32:40.692200 DQ Delay:
1428 12:32:40.695427 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1429 12:32:40.698733 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1430 12:32:40.701973 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1431 12:32:40.705703 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1432 12:32:40.705784
1433 12:32:40.705848
1434 12:32:40.712121 [DQSOSCAuto] RK1, (LSB)MR18= 0x321b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1435 12:32:40.715395 CH0 RK1: MR19=606, MR18=321B
1436 12:32:40.722337 CH0_RK1: MR19=0x606, MR18=0x321B, DQSOSC=397, MR23=63, INC=93, DEC=62
1437 12:32:40.725743 [RxdqsGatingPostProcess] freq 800
1438 12:32:40.732303 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 12:32:40.732385 Pre-setting of DQS Precalculation
1440 12:32:40.738659 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 12:32:40.738784 ==
1442 12:32:40.741819 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 12:32:40.745551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 12:32:40.745634 ==
1445 12:32:40.751944 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 12:32:40.758528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 12:32:40.766492 [CA 0] Center 36 (6~66) winsize 61
1448 12:32:40.769769 [CA 1] Center 36 (6~66) winsize 61
1449 12:32:40.773663 [CA 2] Center 34 (4~64) winsize 61
1450 12:32:40.776868 [CA 3] Center 33 (3~64) winsize 62
1451 12:32:40.780266 [CA 4] Center 34 (4~65) winsize 62
1452 12:32:40.783568 [CA 5] Center 33 (3~64) winsize 62
1453 12:32:40.783706
1454 12:32:40.786935 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1455 12:32:40.787066
1456 12:32:40.790211 [CATrainingPosCal] consider 1 rank data
1457 12:32:40.793398 u2DelayCellTimex100 = 270/100 ps
1458 12:32:40.796580 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1459 12:32:40.799970 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1460 12:32:40.806391 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1461 12:32:40.810262 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1462 12:32:40.813589 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1463 12:32:40.816909 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1464 12:32:40.817013
1465 12:32:40.820127 CA PerBit enable=1, Macro0, CA PI delay=33
1466 12:32:40.820240
1467 12:32:40.823318 [CBTSetCACLKResult] CA Dly = 33
1468 12:32:40.823426 CS Dly: 5 (0~36)
1469 12:32:40.823489 ==
1470 12:32:40.826519 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 12:32:40.833690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 12:32:40.833819 ==
1473 12:32:40.836864 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 12:32:40.843615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 12:32:40.852670 [CA 0] Center 36 (6~67) winsize 62
1476 12:32:40.856168 [CA 1] Center 36 (6~66) winsize 61
1477 12:32:40.859495 [CA 2] Center 34 (4~65) winsize 62
1478 12:32:40.862899 [CA 3] Center 33 (3~64) winsize 62
1479 12:32:40.866182 [CA 4] Center 34 (4~65) winsize 62
1480 12:32:40.869517 [CA 5] Center 33 (3~64) winsize 62
1481 12:32:40.869619
1482 12:32:40.872873 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1483 12:32:40.872960
1484 12:32:40.876680 [CATrainingPosCal] consider 2 rank data
1485 12:32:40.880631 u2DelayCellTimex100 = 270/100 ps
1486 12:32:40.884548 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1487 12:32:40.887720 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1488 12:32:40.891485 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1489 12:32:40.894978 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1490 12:32:40.898851 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1491 12:32:40.902972 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1492 12:32:40.903077
1493 12:32:40.906426 CA PerBit enable=1, Macro0, CA PI delay=33
1494 12:32:40.906512
1495 12:32:40.910152 [CBTSetCACLKResult] CA Dly = 33
1496 12:32:40.910238 CS Dly: 5 (0~37)
1497 12:32:40.910323
1498 12:32:40.913460 ----->DramcWriteLeveling(PI) begin...
1499 12:32:40.913546 ==
1500 12:32:40.916790 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 12:32:40.923490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 12:32:40.923577 ==
1503 12:32:40.926649 Write leveling (Byte 0): 27 => 27
1504 12:32:40.926736 Write leveling (Byte 1): 28 => 28
1505 12:32:40.929828 DramcWriteLeveling(PI) end<-----
1506 12:32:40.929913
1507 12:32:40.933649 ==
1508 12:32:40.933735 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 12:32:40.939616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 12:32:40.939706 ==
1511 12:32:40.943695 [Gating] SW mode calibration
1512 12:32:40.949869 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 12:32:40.953272 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 12:32:40.960155 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 12:32:40.963320 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 1)
1516 12:32:40.966655 0 6 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1517 12:32:40.973367 0 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1518 12:32:40.976586 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:32:40.980020 0 6 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1520 12:32:40.986805 0 6 24 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1521 12:32:40.989979 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:32:40.993259 0 7 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1523 12:32:40.999898 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:32:41.003100 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1525 12:32:41.006481 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1526 12:32:41.009805 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1527 12:32:41.016275 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1528 12:32:41.019519 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1529 12:32:41.023388 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1530 12:32:41.030056 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1531 12:32:41.033305 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:32:41.036832 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1533 12:32:41.043133 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:32:41.046384 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:32:41.049632 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:32:41.056617 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:32:41.060030 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 12:32:41.063149 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 12:32:41.069674 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:32:41.072809 0 9 8 | B1->B0 | 2525 2626 | 1 0 | (1 1) (0 0)
1541 12:32:41.076180 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 12:32:41.082760 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 12:32:41.086693 0 9 20 | B1->B0 | 3534 3434 | 1 1 | (1 1) (1 1)
1544 12:32:41.089441 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1545 12:32:41.096689 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 12:32:41.100132 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 12:32:41.102735 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
1548 12:32:41.106574 0 10 8 | B1->B0 | 2e2e 3030 | 0 1 | (1 0) (1 0)
1549 12:32:41.113204 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 12:32:41.116398 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1551 12:32:41.119799 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 12:32:41.126167 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 12:32:41.129455 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 12:32:41.133508 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 12:32:41.140160 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 12:32:41.143314 0 11 8 | B1->B0 | 3737 2f2f | 0 1 | (0 0) (0 0)
1557 12:32:41.146282 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 12:32:41.152969 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 12:32:41.156902 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 12:32:41.159567 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 12:32:41.166210 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 12:32:41.170047 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 12:32:41.173213 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 12:32:41.179907 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1565 12:32:41.183179 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 12:32:41.186453 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 12:32:41.189669 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:32:41.196346 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 12:32:41.199599 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 12:32:41.202977 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:32:41.209678 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 12:32:41.212917 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:32:41.216241 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 12:32:41.223263 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 12:32:41.226701 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 12:32:41.229677 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 12:32:41.236580 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 12:32:41.239933 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 12:32:41.243031 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 12:32:41.249453 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1581 12:32:41.252643 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 12:32:41.256563 Total UI for P1: 0, mck2ui 16
1583 12:32:41.259781 best dqsien dly found for B0: ( 0, 14, 8)
1584 12:32:41.262991 Total UI for P1: 0, mck2ui 16
1585 12:32:41.266824 best dqsien dly found for B1: ( 0, 14, 8)
1586 12:32:41.269928 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1587 12:32:41.273211 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1588 12:32:41.273322
1589 12:32:41.276341 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1590 12:32:41.279729 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1591 12:32:41.282936 [Gating] SW calibration Done
1592 12:32:41.283036 ==
1593 12:32:41.286294 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 12:32:41.290183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 12:32:41.290267 ==
1596 12:32:41.293421 RX Vref Scan: 0
1597 12:32:41.293550
1598 12:32:41.296652 RX Vref 0 -> 0, step: 1
1599 12:32:41.296759
1600 12:32:41.296853 RX Delay -130 -> 252, step: 16
1601 12:32:41.302673 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1602 12:32:41.306569 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1603 12:32:41.309827 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1604 12:32:41.313142 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1605 12:32:41.316481 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1606 12:32:41.322945 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1607 12:32:41.326335 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1608 12:32:41.329479 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1609 12:32:41.332770 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1610 12:32:41.336629 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1611 12:32:41.342986 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1612 12:32:41.346191 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1613 12:32:41.349606 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1614 12:32:41.352893 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1615 12:32:41.356530 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1616 12:32:41.362977 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1617 12:32:41.363079 ==
1618 12:32:41.366283 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 12:32:41.369859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 12:32:41.369972 ==
1621 12:32:41.370067 DQS Delay:
1622 12:32:41.372885 DQS0 = 0, DQS1 = 0
1623 12:32:41.372987 DQM Delay:
1624 12:32:41.376150 DQM0 = 84, DQM1 = 77
1625 12:32:41.376250 DQ Delay:
1626 12:32:41.379926 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1627 12:32:41.383043 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1628 12:32:41.386202 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1629 12:32:41.389756 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1630 12:32:41.389839
1631 12:32:41.389908
1632 12:32:41.389970 ==
1633 12:32:41.392936 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 12:32:41.396200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 12:32:41.396311 ==
1636 12:32:41.399535
1637 12:32:41.399619
1638 12:32:41.399691 TX Vref Scan disable
1639 12:32:41.402749 == TX Byte 0 ==
1640 12:32:41.406122 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1641 12:32:41.409303 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1642 12:32:41.412582 == TX Byte 1 ==
1643 12:32:41.415935 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1644 12:32:41.419750 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1645 12:32:41.419827 ==
1646 12:32:41.422968 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 12:32:41.429688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 12:32:41.429770 ==
1649 12:32:41.441618 TX Vref=22, minBit 0, minWin=27, winSum=437
1650 12:32:41.444881 TX Vref=24, minBit 4, minWin=27, winSum=444
1651 12:32:41.447985 TX Vref=26, minBit 3, minWin=27, winSum=446
1652 12:32:41.451194 TX Vref=28, minBit 0, minWin=28, winSum=452
1653 12:32:41.455261 TX Vref=30, minBit 1, minWin=28, winSum=453
1654 12:32:41.458504 TX Vref=32, minBit 0, minWin=27, winSum=451
1655 12:32:41.464981 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 30
1656 12:32:41.465095
1657 12:32:41.468909 Final TX Range 1 Vref 30
1658 12:32:41.468994
1659 12:32:41.469062 ==
1660 12:32:41.472106 Dram Type= 6, Freq= 0, CH_1, rank 0
1661 12:32:41.475196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1662 12:32:41.475308 ==
1663 12:32:41.475416
1664 12:32:41.475508
1665 12:32:41.478523 TX Vref Scan disable
1666 12:32:41.482523 == TX Byte 0 ==
1667 12:32:41.485567 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1668 12:32:41.488771 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1669 12:32:41.492160 == TX Byte 1 ==
1670 12:32:41.495280 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1671 12:32:41.498667 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1672 12:32:41.498769
1673 12:32:41.501886 [DATLAT]
1674 12:32:41.502011 Freq=800, CH1 RK0
1675 12:32:41.502136
1676 12:32:41.505194 DATLAT Default: 0xa
1677 12:32:41.505304 0, 0xFFFF, sum = 0
1678 12:32:41.509116 1, 0xFFFF, sum = 0
1679 12:32:41.509221 2, 0xFFFF, sum = 0
1680 12:32:41.511929 3, 0xFFFF, sum = 0
1681 12:32:41.512003 4, 0xFFFF, sum = 0
1682 12:32:41.515225 5, 0xFFFF, sum = 0
1683 12:32:41.515341 6, 0xFFFF, sum = 0
1684 12:32:41.519128 7, 0xFFFF, sum = 0
1685 12:32:41.519202 8, 0xFFFF, sum = 0
1686 12:32:41.522144 9, 0x0, sum = 1
1687 12:32:41.522244 10, 0x0, sum = 2
1688 12:32:41.525411 11, 0x0, sum = 3
1689 12:32:41.525511 12, 0x0, sum = 4
1690 12:32:41.528820 best_step = 10
1691 12:32:41.528922
1692 12:32:41.529018 ==
1693 12:32:41.532111 Dram Type= 6, Freq= 0, CH_1, rank 0
1694 12:32:41.535470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1695 12:32:41.535557 ==
1696 12:32:41.535649 RX Vref Scan: 1
1697 12:32:41.535711
1698 12:32:41.538671 Set Vref Range= 32 -> 127
1699 12:32:41.538768
1700 12:32:41.541943 RX Vref 32 -> 127, step: 1
1701 12:32:41.542022
1702 12:32:41.545753 RX Delay -95 -> 252, step: 8
1703 12:32:41.545861
1704 12:32:41.549023 Set Vref, RX VrefLevel [Byte0]: 32
1705 12:32:41.552220 [Byte1]: 32
1706 12:32:41.552307
1707 12:32:41.555313 Set Vref, RX VrefLevel [Byte0]: 33
1708 12:32:41.558557 [Byte1]: 33
1709 12:32:41.558640
1710 12:32:41.562397 Set Vref, RX VrefLevel [Byte0]: 34
1711 12:32:41.565579 [Byte1]: 34
1712 12:32:41.569192
1713 12:32:41.569271 Set Vref, RX VrefLevel [Byte0]: 35
1714 12:32:41.572346 [Byte1]: 35
1715 12:32:41.576841
1716 12:32:41.576924 Set Vref, RX VrefLevel [Byte0]: 36
1717 12:32:41.580090 [Byte1]: 36
1718 12:32:41.584670
1719 12:32:41.584754 Set Vref, RX VrefLevel [Byte0]: 37
1720 12:32:41.587818 [Byte1]: 37
1721 12:32:41.592169
1722 12:32:41.592248 Set Vref, RX VrefLevel [Byte0]: 38
1723 12:32:41.595557 [Byte1]: 38
1724 12:32:41.599314
1725 12:32:41.599481 Set Vref, RX VrefLevel [Byte0]: 39
1726 12:32:41.602719 [Byte1]: 39
1727 12:32:41.607353
1728 12:32:41.607446 Set Vref, RX VrefLevel [Byte0]: 40
1729 12:32:41.610673 [Byte1]: 40
1730 12:32:41.614535
1731 12:32:41.614610 Set Vref, RX VrefLevel [Byte0]: 41
1732 12:32:41.617865 [Byte1]: 41
1733 12:32:41.622550
1734 12:32:41.622668 Set Vref, RX VrefLevel [Byte0]: 42
1735 12:32:41.625833 [Byte1]: 42
1736 12:32:41.629678
1737 12:32:41.629808 Set Vref, RX VrefLevel [Byte0]: 43
1738 12:32:41.633097 [Byte1]: 43
1739 12:32:41.637233
1740 12:32:41.637346 Set Vref, RX VrefLevel [Byte0]: 44
1741 12:32:41.640713 [Byte1]: 44
1742 12:32:41.645294
1743 12:32:41.645462 Set Vref, RX VrefLevel [Byte0]: 45
1744 12:32:41.648656 [Byte1]: 45
1745 12:32:41.652468
1746 12:32:41.652575 Set Vref, RX VrefLevel [Byte0]: 46
1747 12:32:41.655789 [Byte1]: 46
1748 12:32:41.660287
1749 12:32:41.660369 Set Vref, RX VrefLevel [Byte0]: 47
1750 12:32:41.663542 [Byte1]: 47
1751 12:32:41.668105
1752 12:32:41.668311 Set Vref, RX VrefLevel [Byte0]: 48
1753 12:32:41.671375 [Byte1]: 48
1754 12:32:41.675257
1755 12:32:41.675361 Set Vref, RX VrefLevel [Byte0]: 49
1756 12:32:41.678986 [Byte1]: 49
1757 12:32:41.683460
1758 12:32:41.683542 Set Vref, RX VrefLevel [Byte0]: 50
1759 12:32:41.686529 [Byte1]: 50
1760 12:32:41.690948
1761 12:32:41.691056 Set Vref, RX VrefLevel [Byte0]: 51
1762 12:32:41.694010 [Byte1]: 51
1763 12:32:41.698474
1764 12:32:41.698573 Set Vref, RX VrefLevel [Byte0]: 52
1765 12:32:41.701701 [Byte1]: 52
1766 12:32:41.705682
1767 12:32:41.705764 Set Vref, RX VrefLevel [Byte0]: 53
1768 12:32:41.709039 [Byte1]: 53
1769 12:32:41.713622
1770 12:32:41.713748 Set Vref, RX VrefLevel [Byte0]: 54
1771 12:32:41.717020 [Byte1]: 54
1772 12:32:41.721002
1773 12:32:41.721088 Set Vref, RX VrefLevel [Byte0]: 55
1774 12:32:41.724410 [Byte1]: 55
1775 12:32:41.728996
1776 12:32:41.729078 Set Vref, RX VrefLevel [Byte0]: 56
1777 12:32:41.735569 [Byte1]: 56
1778 12:32:41.735651
1779 12:32:41.738217 Set Vref, RX VrefLevel [Byte0]: 57
1780 12:32:41.741544 [Byte1]: 57
1781 12:32:41.741626
1782 12:32:41.745450 Set Vref, RX VrefLevel [Byte0]: 58
1783 12:32:41.748515 [Byte1]: 58
1784 12:32:41.748649
1785 12:32:41.752024 Set Vref, RX VrefLevel [Byte0]: 59
1786 12:32:41.754970 [Byte1]: 59
1787 12:32:41.758924
1788 12:32:41.759010 Set Vref, RX VrefLevel [Byte0]: 60
1789 12:32:41.762077 [Byte1]: 60
1790 12:32:41.766851
1791 12:32:41.766934 Set Vref, RX VrefLevel [Byte0]: 61
1792 12:32:41.770005 [Byte1]: 61
1793 12:32:41.773998
1794 12:32:41.774081 Set Vref, RX VrefLevel [Byte0]: 62
1795 12:32:41.777851 [Byte1]: 62
1796 12:32:41.781871
1797 12:32:41.781954 Set Vref, RX VrefLevel [Byte0]: 63
1798 12:32:41.784944 [Byte1]: 63
1799 12:32:41.789264
1800 12:32:41.789344 Set Vref, RX VrefLevel [Byte0]: 64
1801 12:32:41.793008 [Byte1]: 64
1802 12:32:41.797069
1803 12:32:41.797153 Set Vref, RX VrefLevel [Byte0]: 65
1804 12:32:41.800308 [Byte1]: 65
1805 12:32:41.804683
1806 12:32:41.804757 Set Vref, RX VrefLevel [Byte0]: 66
1807 12:32:41.807741 [Byte1]: 66
1808 12:32:41.812274
1809 12:32:41.812358 Set Vref, RX VrefLevel [Byte0]: 67
1810 12:32:41.815553 [Byte1]: 67
1811 12:32:41.819602
1812 12:32:41.819678 Set Vref, RX VrefLevel [Byte0]: 68
1813 12:32:41.822848 [Byte1]: 68
1814 12:32:41.827500
1815 12:32:41.827574 Set Vref, RX VrefLevel [Byte0]: 69
1816 12:32:41.830818 [Byte1]: 69
1817 12:32:41.834843
1818 12:32:41.834923 Set Vref, RX VrefLevel [Byte0]: 70
1819 12:32:41.838029 [Byte1]: 70
1820 12:32:41.842683
1821 12:32:41.842791 Set Vref, RX VrefLevel [Byte0]: 71
1822 12:32:41.846035 [Byte1]: 71
1823 12:32:41.850015
1824 12:32:41.850110 Set Vref, RX VrefLevel [Byte0]: 72
1825 12:32:41.853856 [Byte1]: 72
1826 12:32:41.857992
1827 12:32:41.858068 Set Vref, RX VrefLevel [Byte0]: 73
1828 12:32:41.861196 [Byte1]: 73
1829 12:32:41.865632
1830 12:32:41.865741 Set Vref, RX VrefLevel [Byte0]: 74
1831 12:32:41.868830 [Byte1]: 74
1832 12:32:41.873218
1833 12:32:41.873306 Set Vref, RX VrefLevel [Byte0]: 75
1834 12:32:41.876562 [Byte1]: 75
1835 12:32:41.880533
1836 12:32:41.880666 Set Vref, RX VrefLevel [Byte0]: 76
1837 12:32:41.883983 [Byte1]: 76
1838 12:32:41.888558
1839 12:32:41.888661 Set Vref, RX VrefLevel [Byte0]: 77
1840 12:32:41.891218 [Byte1]: 77
1841 12:32:41.895744
1842 12:32:41.895824 Set Vref, RX VrefLevel [Byte0]: 78
1843 12:32:41.899552 [Byte1]: 78
1844 12:32:41.903170
1845 12:32:41.903276 Set Vref, RX VrefLevel [Byte0]: 79
1846 12:32:41.906989 [Byte1]: 79
1847 12:32:41.911217
1848 12:32:41.911328 Set Vref, RX VrefLevel [Byte0]: 80
1849 12:32:41.914336 [Byte1]: 80
1850 12:32:41.919018
1851 12:32:41.919124 Final RX Vref Byte 0 = 62 to rank0
1852 12:32:41.921701 Final RX Vref Byte 1 = 60 to rank0
1853 12:32:41.924913 Final RX Vref Byte 0 = 62 to rank1
1854 12:32:41.928858 Final RX Vref Byte 1 = 60 to rank1==
1855 12:32:41.932150 Dram Type= 6, Freq= 0, CH_1, rank 0
1856 12:32:41.938650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 12:32:41.938756 ==
1858 12:32:41.938854 DQS Delay:
1859 12:32:41.938949 DQS0 = 0, DQS1 = 0
1860 12:32:41.941878 DQM Delay:
1861 12:32:41.941991 DQM0 = 84, DQM1 = 73
1862 12:32:41.945191 DQ Delay:
1863 12:32:41.948579 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =84
1864 12:32:41.948664 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =80
1865 12:32:41.951834 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =72
1866 12:32:41.958277 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76
1867 12:32:41.958383
1868 12:32:41.958478
1869 12:32:41.965501 [DQSOSCAuto] RK0, (LSB)MR18= 0x24f9, (MSB)MR19= 0x605, tDQSOscB0 = 412 ps tDQSOscB1 = 400 ps
1870 12:32:41.968124 CH1 RK0: MR19=605, MR18=24F9
1871 12:32:41.975130 CH1_RK0: MR19=0x605, MR18=0x24F9, DQSOSC=400, MR23=63, INC=92, DEC=61
1872 12:32:41.975274
1873 12:32:41.978553 ----->DramcWriteLeveling(PI) begin...
1874 12:32:41.978669 ==
1875 12:32:41.981811 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 12:32:41.985093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 12:32:41.985200 ==
1878 12:32:41.988458 Write leveling (Byte 0): 26 => 26
1879 12:32:41.991571 Write leveling (Byte 1): 30 => 30
1880 12:32:41.994875 DramcWriteLeveling(PI) end<-----
1881 12:32:41.994988
1882 12:32:41.995084 ==
1883 12:32:41.998143 Dram Type= 6, Freq= 0, CH_1, rank 1
1884 12:32:42.001697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1885 12:32:42.001813 ==
1886 12:32:42.005188 [Gating] SW mode calibration
1887 12:32:42.011470 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1888 12:32:42.018090 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1889 12:32:42.021761 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1890 12:32:42.025090 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1891 12:32:42.031535 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:32:42.035109 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:32:42.038263 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:32:42.044726 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:32:42.048125 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:32:42.051386 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:32:42.058202 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:32:42.062023 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:32:42.065241 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:32:42.071769 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1901 12:32:42.075094 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1902 12:32:42.078010 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1903 12:32:42.085288 0 7 24 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1904 12:32:42.087992 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 12:32:42.091885 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1906 12:32:42.095151 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 1)
1907 12:32:42.101951 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1908 12:32:42.105160 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1909 12:32:42.108583 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 12:32:42.114783 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 12:32:42.118259 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 12:32:42.121429 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 12:32:42.128212 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 12:32:42.131542 0 9 4 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
1915 12:32:42.134809 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1916 12:32:42.141520 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1917 12:32:42.144720 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 12:32:42.148699 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1919 12:32:42.155247 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 12:32:42.158066 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1921 12:32:42.161315 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1922 12:32:42.168480 0 10 4 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (0 0)
1923 12:32:42.171785 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1924 12:32:42.175069 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1925 12:32:42.181473 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1926 12:32:42.184637 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 12:32:42.187966 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 12:32:42.194704 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 12:32:42.197901 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1930 12:32:42.201126 0 11 4 | B1->B0 | 2c2c 3838 | 1 0 | (0 0) (1 1)
1931 12:32:42.205071 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1932 12:32:42.211735 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 12:32:42.214940 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 12:32:42.218241 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 12:32:42.224613 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 12:32:42.228374 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 12:32:42.231465 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 12:32:42.238490 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1939 12:32:42.241699 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1940 12:32:42.245117 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 12:32:42.251632 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 12:32:42.254947 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 12:32:42.258290 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 12:32:42.264780 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 12:32:42.267886 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 12:32:42.271285 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 12:32:42.277890 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 12:32:42.281246 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 12:32:42.284547 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 12:32:42.291677 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 12:32:42.295009 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 12:32:42.298239 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 12:32:42.304973 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 12:32:42.308373 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1955 12:32:42.311631 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1956 12:32:42.314930 Total UI for P1: 0, mck2ui 16
1957 12:32:42.318119 best dqsien dly found for B0: ( 0, 14, 4)
1958 12:32:42.321392 Total UI for P1: 0, mck2ui 16
1959 12:32:42.324725 best dqsien dly found for B1: ( 0, 14, 4)
1960 12:32:42.328464 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1961 12:32:42.331718 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1962 12:32:42.331858
1963 12:32:42.334840 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1964 12:32:42.337858 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1965 12:32:42.341179 [Gating] SW calibration Done
1966 12:32:42.341309 ==
1967 12:32:42.344507 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 12:32:42.351060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 12:32:42.351216 ==
1970 12:32:42.351320 RX Vref Scan: 0
1971 12:32:42.351407
1972 12:32:42.354956 RX Vref 0 -> 0, step: 1
1973 12:32:42.355066
1974 12:32:42.358242 RX Delay -130 -> 252, step: 16
1975 12:32:42.361656 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1976 12:32:42.364815 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1977 12:32:42.368203 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1978 12:32:42.371386 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1979 12:32:42.377955 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1980 12:32:42.381346 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1981 12:32:42.384553 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1982 12:32:42.387870 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1983 12:32:42.391169 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1984 12:32:42.397801 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1985 12:32:42.401684 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1986 12:32:42.404898 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1987 12:32:42.408209 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1988 12:32:42.411636 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1989 12:32:42.418192 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1990 12:32:42.421090 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1991 12:32:42.421238 ==
1992 12:32:42.424559 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 12:32:42.427725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 12:32:42.427840 ==
1995 12:32:42.431069 DQS Delay:
1996 12:32:42.431201 DQS0 = 0, DQS1 = 0
1997 12:32:42.431306 DQM Delay:
1998 12:32:42.434888 DQM0 = 80, DQM1 = 77
1999 12:32:42.435013 DQ Delay:
2000 12:32:42.437929 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
2001 12:32:42.441231 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =69
2002 12:32:42.444238 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
2003 12:32:42.447678 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2004 12:32:42.447821
2005 12:32:42.447926
2006 12:32:42.448019 ==
2007 12:32:42.450978 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 12:32:42.457639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 12:32:42.457792 ==
2010 12:32:42.457893
2011 12:32:42.457984
2012 12:32:42.458073 TX Vref Scan disable
2013 12:32:42.460966 == TX Byte 0 ==
2014 12:32:42.464230 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2015 12:32:42.470912 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2016 12:32:42.471073 == TX Byte 1 ==
2017 12:32:42.474289 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2018 12:32:42.480958 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2019 12:32:42.481141 ==
2020 12:32:42.484842 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 12:32:42.487586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 12:32:42.487689 ==
2023 12:32:42.500404 TX Vref=22, minBit 1, minWin=27, winSum=442
2024 12:32:42.503644 TX Vref=24, minBit 0, minWin=27, winSum=446
2025 12:32:42.507617 TX Vref=26, minBit 0, minWin=27, winSum=448
2026 12:32:42.510984 TX Vref=28, minBit 0, minWin=28, winSum=454
2027 12:32:42.514046 TX Vref=30, minBit 12, minWin=27, winSum=451
2028 12:32:42.520734 TX Vref=32, minBit 0, minWin=28, winSum=455
2029 12:32:42.524184 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 32
2030 12:32:42.524321
2031 12:32:42.527583 Final TX Range 1 Vref 32
2032 12:32:42.527685
2033 12:32:42.527760 ==
2034 12:32:42.530959 Dram Type= 6, Freq= 0, CH_1, rank 1
2035 12:32:42.534219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2036 12:32:42.534329 ==
2037 12:32:42.534403
2038 12:32:42.536879
2039 12:32:42.536963 TX Vref Scan disable
2040 12:32:42.540826 == TX Byte 0 ==
2041 12:32:42.544116 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2042 12:32:42.550570 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2043 12:32:42.550727 == TX Byte 1 ==
2044 12:32:42.553666 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2045 12:32:42.560530 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2046 12:32:42.560665
2047 12:32:42.560737 [DATLAT]
2048 12:32:42.560801 Freq=800, CH1 RK1
2049 12:32:42.560862
2050 12:32:42.563924 DATLAT Default: 0xa
2051 12:32:42.564033 0, 0xFFFF, sum = 0
2052 12:32:42.567333 1, 0xFFFF, sum = 0
2053 12:32:42.567467 2, 0xFFFF, sum = 0
2054 12:32:42.570630 3, 0xFFFF, sum = 0
2055 12:32:42.570755 4, 0xFFFF, sum = 0
2056 12:32:42.573888 5, 0xFFFF, sum = 0
2057 12:32:42.577202 6, 0xFFFF, sum = 0
2058 12:32:42.577338 7, 0xFFFF, sum = 0
2059 12:32:42.580684 8, 0xFFFF, sum = 0
2060 12:32:42.580810 9, 0x0, sum = 1
2061 12:32:42.580921 10, 0x0, sum = 2
2062 12:32:42.583908 11, 0x0, sum = 3
2063 12:32:42.584036 12, 0x0, sum = 4
2064 12:32:42.587284 best_step = 10
2065 12:32:42.587444
2066 12:32:42.587554 ==
2067 12:32:42.590560 Dram Type= 6, Freq= 0, CH_1, rank 1
2068 12:32:42.593714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2069 12:32:42.593844 ==
2070 12:32:42.597137 RX Vref Scan: 0
2071 12:32:42.597266
2072 12:32:42.597374 RX Vref 0 -> 0, step: 1
2073 12:32:42.597472
2074 12:32:42.600289 RX Delay -95 -> 252, step: 8
2075 12:32:42.606982 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2076 12:32:42.610951 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2077 12:32:42.613661 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2078 12:32:42.617581 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2079 12:32:42.620909 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2080 12:32:42.626951 iDelay=209, Bit 5, Center 92 (-15 ~ 200) 216
2081 12:32:42.630228 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2082 12:32:42.633545 iDelay=209, Bit 7, Center 80 (-31 ~ 192) 224
2083 12:32:42.637390 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2084 12:32:42.640695 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2085 12:32:42.647097 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2086 12:32:42.650423 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2087 12:32:42.653614 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2088 12:32:42.656958 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2089 12:32:42.663625 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2090 12:32:42.666892 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2091 12:32:42.667041 ==
2092 12:32:42.670182 Dram Type= 6, Freq= 0, CH_1, rank 1
2093 12:32:42.673379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2094 12:32:42.673511 ==
2095 12:32:42.673614 DQS Delay:
2096 12:32:42.676762 DQS0 = 0, DQS1 = 0
2097 12:32:42.676878 DQM Delay:
2098 12:32:42.680039 DQM0 = 81, DQM1 = 75
2099 12:32:42.680158 DQ Delay:
2100 12:32:42.683395 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2101 12:32:42.686710 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =80
2102 12:32:42.689891 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2103 12:32:42.693255 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2104 12:32:42.693376
2105 12:32:42.693473
2106 12:32:42.703798 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
2107 12:32:42.703960 CH1 RK1: MR19=606, MR18=1B26
2108 12:32:42.710226 CH1_RK1: MR19=0x606, MR18=0x1B26, DQSOSC=400, MR23=63, INC=92, DEC=61
2109 12:32:42.713483 [RxdqsGatingPostProcess] freq 800
2110 12:32:42.720074 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2111 12:32:42.723331 Pre-setting of DQS Precalculation
2112 12:32:42.726705 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2113 12:32:42.733283 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2114 12:32:42.743279 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2115 12:32:42.743457
2116 12:32:42.743555
2117 12:32:42.746439 [Calibration Summary] 1600 Mbps
2118 12:32:42.746562 CH 0, Rank 0
2119 12:32:42.750288 SW Impedance : PASS
2120 12:32:42.750387 DUTY Scan : NO K
2121 12:32:42.753533 ZQ Calibration : PASS
2122 12:32:42.753661 Jitter Meter : NO K
2123 12:32:42.756815 CBT Training : PASS
2124 12:32:42.760054 Write leveling : PASS
2125 12:32:42.760170 RX DQS gating : PASS
2126 12:32:42.763179 RX DQ/DQS(RDDQC) : PASS
2127 12:32:42.766527 TX DQ/DQS : PASS
2128 12:32:42.766634 RX DATLAT : PASS
2129 12:32:42.769676 RX DQ/DQS(Engine): PASS
2130 12:32:42.773063 TX OE : NO K
2131 12:32:42.773201 All Pass.
2132 12:32:42.773318
2133 12:32:42.773437 CH 0, Rank 1
2134 12:32:42.776345 SW Impedance : PASS
2135 12:32:42.780334 DUTY Scan : NO K
2136 12:32:42.780498 ZQ Calibration : PASS
2137 12:32:42.783628 Jitter Meter : NO K
2138 12:32:42.787026 CBT Training : PASS
2139 12:32:42.787167 Write leveling : PASS
2140 12:32:42.789823 RX DQS gating : PASS
2141 12:32:42.789945 RX DQ/DQS(RDDQC) : PASS
2142 12:32:42.793234 TX DQ/DQS : PASS
2143 12:32:42.796557 RX DATLAT : PASS
2144 12:32:42.796709 RX DQ/DQS(Engine): PASS
2145 12:32:42.799940 TX OE : NO K
2146 12:32:42.800064 All Pass.
2147 12:32:42.800197
2148 12:32:42.803282 CH 1, Rank 0
2149 12:32:42.803431 SW Impedance : PASS
2150 12:32:42.806558 DUTY Scan : NO K
2151 12:32:42.809956 ZQ Calibration : PASS
2152 12:32:42.810079 Jitter Meter : NO K
2153 12:32:42.813081 CBT Training : PASS
2154 12:32:42.816416 Write leveling : PASS
2155 12:32:42.816519 RX DQS gating : PASS
2156 12:32:42.819704 RX DQ/DQS(RDDQC) : PASS
2157 12:32:42.823484 TX DQ/DQS : PASS
2158 12:32:42.823589 RX DATLAT : PASS
2159 12:32:42.826920 RX DQ/DQS(Engine): PASS
2160 12:32:42.830167 TX OE : NO K
2161 12:32:42.830281 All Pass.
2162 12:32:42.830392
2163 12:32:42.830485 CH 1, Rank 1
2164 12:32:42.833363 SW Impedance : PASS
2165 12:32:42.836476 DUTY Scan : NO K
2166 12:32:42.836611 ZQ Calibration : PASS
2167 12:32:42.840358 Jitter Meter : NO K
2168 12:32:42.840444 CBT Training : PASS
2169 12:32:42.843773 Write leveling : PASS
2170 12:32:42.846956 RX DQS gating : PASS
2171 12:32:42.847076 RX DQ/DQS(RDDQC) : PASS
2172 12:32:42.850102 TX DQ/DQS : PASS
2173 12:32:42.853263 RX DATLAT : PASS
2174 12:32:42.853404 RX DQ/DQS(Engine): PASS
2175 12:32:42.856503 TX OE : NO K
2176 12:32:42.856618 All Pass.
2177 12:32:42.856689
2178 12:32:42.859854 DramC Write-DBI off
2179 12:32:42.863617 PER_BANK_REFRESH: Hybrid Mode
2180 12:32:42.863754 TX_TRACKING: ON
2181 12:32:42.866927 [GetDramInforAfterCalByMRR] Vendor 6.
2182 12:32:42.870202 [GetDramInforAfterCalByMRR] Revision 606.
2183 12:32:42.873322 [GetDramInforAfterCalByMRR] Revision 2 0.
2184 12:32:42.876599 MR0 0x3b3b
2185 12:32:42.876730 MR8 0x5151
2186 12:32:42.879974 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2187 12:32:42.880094
2188 12:32:42.880190 MR0 0x3b3b
2189 12:32:42.883260 MR8 0x5151
2190 12:32:42.886489 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2191 12:32:42.886622
2192 12:32:42.896720 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2193 12:32:42.900132 [FAST_K] Save calibration result to emmc
2194 12:32:42.903364 [FAST_K] Save calibration result to emmc
2195 12:32:42.903516 dram_init: config_dvfs: 1
2196 12:32:42.910075 dramc_set_vcore_voltage set vcore to 662500
2197 12:32:42.910219 Read voltage for 1200, 2
2198 12:32:42.913258 Vio18 = 0
2199 12:32:42.913379 Vcore = 662500
2200 12:32:42.913484 Vdram = 0
2201 12:32:42.916451 Vddq = 0
2202 12:32:42.916572 Vmddr = 0
2203 12:32:42.919716 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2204 12:32:42.926468 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2205 12:32:42.929606 MEM_TYPE=3, freq_sel=15
2206 12:32:42.929754 sv_algorithm_assistance_LP4_1600
2207 12:32:42.936308 ============ PULL DRAM RESETB DOWN ============
2208 12:32:42.939556 ========== PULL DRAM RESETB DOWN end =========
2209 12:32:42.942938 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2210 12:32:42.946404 ===================================
2211 12:32:42.949727 LPDDR4 DRAM CONFIGURATION
2212 12:32:42.953160 ===================================
2213 12:32:42.956454 EX_ROW_EN[0] = 0x0
2214 12:32:42.956580 EX_ROW_EN[1] = 0x0
2215 12:32:42.959670 LP4Y_EN = 0x0
2216 12:32:42.959778 WORK_FSP = 0x0
2217 12:32:42.962997 WL = 0x4
2218 12:32:42.963124 RL = 0x4
2219 12:32:42.966150 BL = 0x2
2220 12:32:42.966272 RPST = 0x0
2221 12:32:42.969842 RD_PRE = 0x0
2222 12:32:42.969940 WR_PRE = 0x1
2223 12:32:42.973245 WR_PST = 0x0
2224 12:32:42.973339 DBI_WR = 0x0
2225 12:32:42.976586 DBI_RD = 0x0
2226 12:32:42.976706 OTF = 0x1
2227 12:32:42.979946 ===================================
2228 12:32:42.983183 ===================================
2229 12:32:42.986659 ANA top config
2230 12:32:42.990053 ===================================
2231 12:32:42.993458 DLL_ASYNC_EN = 0
2232 12:32:42.993551 ALL_SLAVE_EN = 0
2233 12:32:42.996726 NEW_RANK_MODE = 1
2234 12:32:42.999914 DLL_IDLE_MODE = 1
2235 12:32:43.003423 LP45_APHY_COMB_EN = 1
2236 12:32:43.003527 TX_ODT_DIS = 1
2237 12:32:43.006147 NEW_8X_MODE = 1
2238 12:32:43.009622 ===================================
2239 12:32:43.013461 ===================================
2240 12:32:43.016674 data_rate = 2400
2241 12:32:43.019872 CKR = 1
2242 12:32:43.023058 DQ_P2S_RATIO = 8
2243 12:32:43.026283 ===================================
2244 12:32:43.029576 CA_P2S_RATIO = 8
2245 12:32:43.029681 DQ_CA_OPEN = 0
2246 12:32:43.032906 DQ_SEMI_OPEN = 0
2247 12:32:43.036341 CA_SEMI_OPEN = 0
2248 12:32:43.039599 CA_FULL_RATE = 0
2249 12:32:43.042939 DQ_CKDIV4_EN = 0
2250 12:32:43.046321 CA_CKDIV4_EN = 0
2251 12:32:43.046466 CA_PREDIV_EN = 0
2252 12:32:43.049759 PH8_DLY = 17
2253 12:32:43.053178 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2254 12:32:43.056499 DQ_AAMCK_DIV = 4
2255 12:32:43.059763 CA_AAMCK_DIV = 4
2256 12:32:43.063182 CA_ADMCK_DIV = 4
2257 12:32:43.063285 DQ_TRACK_CA_EN = 0
2258 12:32:43.066532 CA_PICK = 1200
2259 12:32:43.069725 CA_MCKIO = 1200
2260 12:32:43.072815 MCKIO_SEMI = 0
2261 12:32:43.076193 PLL_FREQ = 2366
2262 12:32:43.079472 DQ_UI_PI_RATIO = 32
2263 12:32:43.082916 CA_UI_PI_RATIO = 0
2264 12:32:43.086416 ===================================
2265 12:32:43.089679 ===================================
2266 12:32:43.089786 memory_type:LPDDR4
2267 12:32:43.093029 GP_NUM : 10
2268 12:32:43.096489 SRAM_EN : 1
2269 12:32:43.096649 MD32_EN : 0
2270 12:32:43.099768 ===================================
2271 12:32:43.103095 [ANA_INIT] >>>>>>>>>>>>>>
2272 12:32:43.106477 <<<<<< [CONFIGURE PHASE]: ANA_TX
2273 12:32:43.109887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2274 12:32:43.113100 ===================================
2275 12:32:43.116432 data_rate = 2400,PCW = 0X5b00
2276 12:32:43.119799 ===================================
2277 12:32:43.123056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2278 12:32:43.126220 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2279 12:32:43.132843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2280 12:32:43.136320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2281 12:32:43.139625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2282 12:32:43.142862 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2283 12:32:43.146481 [ANA_INIT] flow start
2284 12:32:43.149961 [ANA_INIT] PLL >>>>>>>>
2285 12:32:43.150088 [ANA_INIT] PLL <<<<<<<<
2286 12:32:43.152591 [ANA_INIT] MIDPI >>>>>>>>
2287 12:32:43.156131 [ANA_INIT] MIDPI <<<<<<<<
2288 12:32:43.156301 [ANA_INIT] DLL >>>>>>>>
2289 12:32:43.159423 [ANA_INIT] DLL <<<<<<<<
2290 12:32:43.162818 [ANA_INIT] flow end
2291 12:32:43.166166 ============ LP4 DIFF to SE enter ============
2292 12:32:43.169443 ============ LP4 DIFF to SE exit ============
2293 12:32:43.172683 [ANA_INIT] <<<<<<<<<<<<<
2294 12:32:43.175988 [Flow] Enable top DCM control >>>>>
2295 12:32:43.179823 [Flow] Enable top DCM control <<<<<
2296 12:32:43.182906 Enable DLL master slave shuffle
2297 12:32:43.186223 ==============================================================
2298 12:32:43.189437 Gating Mode config
2299 12:32:43.196339 ==============================================================
2300 12:32:43.196493 Config description:
2301 12:32:43.205889 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2302 12:32:43.212541 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2303 12:32:43.215989 SELPH_MODE 0: By rank 1: By Phase
2304 12:32:43.222762 ==============================================================
2305 12:32:43.225962 GAT_TRACK_EN = 1
2306 12:32:43.229272 RX_GATING_MODE = 2
2307 12:32:43.233117 RX_GATING_TRACK_MODE = 2
2308 12:32:43.236256 SELPH_MODE = 1
2309 12:32:43.239619 PICG_EARLY_EN = 1
2310 12:32:43.242988 VALID_LAT_VALUE = 1
2311 12:32:43.246277 ==============================================================
2312 12:32:43.249638 Enter into Gating configuration >>>>
2313 12:32:43.252888 Exit from Gating configuration <<<<
2314 12:32:43.256238 Enter into DVFS_PRE_config >>>>>
2315 12:32:43.266252 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2316 12:32:43.269719 Exit from DVFS_PRE_config <<<<<
2317 12:32:43.272877 Enter into PICG configuration >>>>
2318 12:32:43.276016 Exit from PICG configuration <<<<
2319 12:32:43.279241 [RX_INPUT] configuration >>>>>
2320 12:32:43.282542 [RX_INPUT] configuration <<<<<
2321 12:32:43.289657 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2322 12:32:43.292965 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2323 12:32:43.299737 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2324 12:32:43.306115 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2325 12:32:43.312880 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2326 12:32:43.319510 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2327 12:32:43.322750 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2328 12:32:43.326188 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2329 12:32:43.329542 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2330 12:32:43.336148 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2331 12:32:43.339365 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2332 12:32:43.342639 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 12:32:43.345954 ===================================
2334 12:32:43.349460 LPDDR4 DRAM CONFIGURATION
2335 12:32:43.352859 ===================================
2336 12:32:43.353004 EX_ROW_EN[0] = 0x0
2337 12:32:43.356303 EX_ROW_EN[1] = 0x0
2338 12:32:43.356430 LP4Y_EN = 0x0
2339 12:32:43.358937 WORK_FSP = 0x0
2340 12:32:43.362977 WL = 0x4
2341 12:32:43.363126 RL = 0x4
2342 12:32:43.366113 BL = 0x2
2343 12:32:43.366234 RPST = 0x0
2344 12:32:43.369684 RD_PRE = 0x0
2345 12:32:43.369811 WR_PRE = 0x1
2346 12:32:43.372457 WR_PST = 0x0
2347 12:32:43.372569 DBI_WR = 0x0
2348 12:32:43.375614 DBI_RD = 0x0
2349 12:32:43.375736 OTF = 0x1
2350 12:32:43.379485 ===================================
2351 12:32:43.382895 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2352 12:32:43.389253 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2353 12:32:43.392485 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2354 12:32:43.395710 ===================================
2355 12:32:43.399090 LPDDR4 DRAM CONFIGURATION
2356 12:32:43.402424 ===================================
2357 12:32:43.402541 EX_ROW_EN[0] = 0x10
2358 12:32:43.405771 EX_ROW_EN[1] = 0x0
2359 12:32:43.405865 LP4Y_EN = 0x0
2360 12:32:43.409202 WORK_FSP = 0x0
2361 12:32:43.409323 WL = 0x4
2362 12:32:43.412459 RL = 0x4
2363 12:32:43.412579 BL = 0x2
2364 12:32:43.415907 RPST = 0x0
2365 12:32:43.416002 RD_PRE = 0x0
2366 12:32:43.419109 WR_PRE = 0x1
2367 12:32:43.419219 WR_PST = 0x0
2368 12:32:43.422348 DBI_WR = 0x0
2369 12:32:43.422441 DBI_RD = 0x0
2370 12:32:43.425686 OTF = 0x1
2371 12:32:43.428961 ===================================
2372 12:32:43.435739 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2373 12:32:43.435873 ==
2374 12:32:43.439013 Dram Type= 6, Freq= 0, CH_0, rank 0
2375 12:32:43.442543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2376 12:32:43.442649 ==
2377 12:32:43.445576 [Duty_Offset_Calibration]
2378 12:32:43.445708 B0:2 B1:-1 CA:1
2379 12:32:43.449326
2380 12:32:43.449457 [DutyScan_Calibration_Flow] k_type=0
2381 12:32:43.458972
2382 12:32:43.459132 ==CLK 0==
2383 12:32:43.462210 Final CLK duty delay cell = -4
2384 12:32:43.465565 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2385 12:32:43.468882 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2386 12:32:43.472188 [-4] AVG Duty = 4953%(X100)
2387 12:32:43.472325
2388 12:32:43.475843 CH0 CLK Duty spec in!! Max-Min= 156%
2389 12:32:43.479005 [DutyScan_Calibration_Flow] ====Done====
2390 12:32:43.479131
2391 12:32:43.482130 [DutyScan_Calibration_Flow] k_type=1
2392 12:32:43.498193
2393 12:32:43.498358 ==DQS 0 ==
2394 12:32:43.501683 Final DQS duty delay cell = 0
2395 12:32:43.504965 [0] MAX Duty = 5125%(X100), DQS PI = 48
2396 12:32:43.508350 [0] MIN Duty = 5000%(X100), DQS PI = 14
2397 12:32:43.511686 [0] AVG Duty = 5062%(X100)
2398 12:32:43.511790
2399 12:32:43.511860 ==DQS 1 ==
2400 12:32:43.514972 Final DQS duty delay cell = -4
2401 12:32:43.517783 [-4] MAX Duty = 5093%(X100), DQS PI = 4
2402 12:32:43.521649 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2403 12:32:43.525098 [-4] AVG Duty = 5046%(X100)
2404 12:32:43.525199
2405 12:32:43.527765 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2406 12:32:43.527872
2407 12:32:43.531191 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2408 12:32:43.534671 [DutyScan_Calibration_Flow] ====Done====
2409 12:32:43.534799
2410 12:32:43.537853 [DutyScan_Calibration_Flow] k_type=3
2411 12:32:43.554951
2412 12:32:43.555113 ==DQM 0 ==
2413 12:32:43.558411 Final DQM duty delay cell = 0
2414 12:32:43.561229 [0] MAX Duty = 5000%(X100), DQS PI = 54
2415 12:32:43.564611 [0] MIN Duty = 4907%(X100), DQS PI = 2
2416 12:32:43.564739 [0] AVG Duty = 4953%(X100)
2417 12:32:43.567849
2418 12:32:43.567987 ==DQM 1 ==
2419 12:32:43.571212 Final DQM duty delay cell = 0
2420 12:32:43.574639 [0] MAX Duty = 5124%(X100), DQS PI = 32
2421 12:32:43.578063 [0] MIN Duty = 4969%(X100), DQS PI = 10
2422 12:32:43.581644 [0] AVG Duty = 5046%(X100)
2423 12:32:43.581770
2424 12:32:43.584917 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2425 12:32:43.585038
2426 12:32:43.588170 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2427 12:32:43.591344 [DutyScan_Calibration_Flow] ====Done====
2428 12:32:43.591456
2429 12:32:43.594742 [DutyScan_Calibration_Flow] k_type=2
2430 12:32:43.610480
2431 12:32:43.610650 ==DQ 0 ==
2432 12:32:43.613969 Final DQ duty delay cell = -4
2433 12:32:43.617366 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2434 12:32:43.620656 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2435 12:32:43.623874 [-4] AVG Duty = 4969%(X100)
2436 12:32:43.624005
2437 12:32:43.624105 ==DQ 1 ==
2438 12:32:43.627194 Final DQ duty delay cell = 0
2439 12:32:43.630545 [0] MAX Duty = 5031%(X100), DQS PI = 18
2440 12:32:43.633890 [0] MIN Duty = 4907%(X100), DQS PI = 46
2441 12:32:43.637344 [0] AVG Duty = 4969%(X100)
2442 12:32:43.637454
2443 12:32:43.640617 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2444 12:32:43.640710
2445 12:32:43.643888 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2446 12:32:43.647321 [DutyScan_Calibration_Flow] ====Done====
2447 12:32:43.647461 ==
2448 12:32:43.650754 Dram Type= 6, Freq= 0, CH_1, rank 0
2449 12:32:43.654086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2450 12:32:43.654227 ==
2451 12:32:43.657373 [Duty_Offset_Calibration]
2452 12:32:43.657480 B0:1 B1:1 CA:2
2453 12:32:43.657565
2454 12:32:43.660528 [DutyScan_Calibration_Flow] k_type=0
2455 12:32:43.671024
2456 12:32:43.671156 ==CLK 0==
2457 12:32:43.674228 Final CLK duty delay cell = 0
2458 12:32:43.677578 [0] MAX Duty = 5156%(X100), DQS PI = 24
2459 12:32:43.680846 [0] MIN Duty = 4969%(X100), DQS PI = 40
2460 12:32:43.680938 [0] AVG Duty = 5062%(X100)
2461 12:32:43.683960
2462 12:32:43.687225 CH1 CLK Duty spec in!! Max-Min= 187%
2463 12:32:43.690450 [DutyScan_Calibration_Flow] ====Done====
2464 12:32:43.690575
2465 12:32:43.694245 [DutyScan_Calibration_Flow] k_type=1
2466 12:32:43.710537
2467 12:32:43.710678 ==DQS 0 ==
2468 12:32:43.713766 Final DQS duty delay cell = 0
2469 12:32:43.716927 [0] MAX Duty = 5031%(X100), DQS PI = 18
2470 12:32:43.720360 [0] MIN Duty = 4813%(X100), DQS PI = 50
2471 12:32:43.720504 [0] AVG Duty = 4922%(X100)
2472 12:32:43.723639
2473 12:32:43.723732 ==DQS 1 ==
2474 12:32:43.727023 Final DQS duty delay cell = 0
2475 12:32:43.730327 [0] MAX Duty = 5062%(X100), DQS PI = 36
2476 12:32:43.733727 [0] MIN Duty = 4907%(X100), DQS PI = 16
2477 12:32:43.733855 [0] AVG Duty = 4984%(X100)
2478 12:32:43.737153
2479 12:32:43.740783 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2480 12:32:43.740935
2481 12:32:43.743322 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2482 12:32:43.747071 [DutyScan_Calibration_Flow] ====Done====
2483 12:32:43.747224
2484 12:32:43.750440 [DutyScan_Calibration_Flow] k_type=3
2485 12:32:43.766454
2486 12:32:43.766622 ==DQM 0 ==
2487 12:32:43.770437 Final DQM duty delay cell = 0
2488 12:32:43.773567 [0] MAX Duty = 5093%(X100), DQS PI = 18
2489 12:32:43.776847 [0] MIN Duty = 4907%(X100), DQS PI = 48
2490 12:32:43.780086 [0] AVG Duty = 5000%(X100)
2491 12:32:43.780210
2492 12:32:43.780306 ==DQM 1 ==
2493 12:32:43.783453 Final DQM duty delay cell = 0
2494 12:32:43.786636 [0] MAX Duty = 5156%(X100), DQS PI = 62
2495 12:32:43.789988 [0] MIN Duty = 4938%(X100), DQS PI = 22
2496 12:32:43.793399 [0] AVG Duty = 5047%(X100)
2497 12:32:43.793540
2498 12:32:43.796592 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2499 12:32:43.796694
2500 12:32:43.799931 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2501 12:32:43.803187 [DutyScan_Calibration_Flow] ====Done====
2502 12:32:43.803311
2503 12:32:43.806383 [DutyScan_Calibration_Flow] k_type=2
2504 12:32:43.823085
2505 12:32:43.823256 ==DQ 0 ==
2506 12:32:43.826417 Final DQ duty delay cell = 0
2507 12:32:43.830342 [0] MAX Duty = 5125%(X100), DQS PI = 18
2508 12:32:43.833166 [0] MIN Duty = 4938%(X100), DQS PI = 50
2509 12:32:43.833304 [0] AVG Duty = 5031%(X100)
2510 12:32:43.836636
2511 12:32:43.836756 ==DQ 1 ==
2512 12:32:43.840024 Final DQ duty delay cell = 0
2513 12:32:43.843460 [0] MAX Duty = 5093%(X100), DQS PI = 8
2514 12:32:43.846733 [0] MIN Duty = 5031%(X100), DQS PI = 2
2515 12:32:43.846868 [0] AVG Duty = 5062%(X100)
2516 12:32:43.846985
2517 12:32:43.850215 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2518 12:32:43.850315
2519 12:32:43.853580 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2520 12:32:43.860054 [DutyScan_Calibration_Flow] ====Done====
2521 12:32:43.863526 nWR fixed to 30
2522 12:32:43.863693 [ModeRegInit_LP4] CH0 RK0
2523 12:32:43.866670 [ModeRegInit_LP4] CH0 RK1
2524 12:32:43.869892 [ModeRegInit_LP4] CH1 RK0
2525 12:32:43.870019 [ModeRegInit_LP4] CH1 RK1
2526 12:32:43.873405 match AC timing 7
2527 12:32:43.876559 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2528 12:32:43.880112 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2529 12:32:43.886747 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2530 12:32:43.890123 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2531 12:32:43.896149 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2532 12:32:43.896329 ==
2533 12:32:43.900088 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 12:32:43.903267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 12:32:43.903409 ==
2536 12:32:43.909595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2537 12:32:43.912971 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2538 12:32:43.922954 [CA 0] Center 40 (10~71) winsize 62
2539 12:32:43.926240 [CA 1] Center 39 (9~70) winsize 62
2540 12:32:43.929689 [CA 2] Center 36 (6~67) winsize 62
2541 12:32:43.932992 [CA 3] Center 35 (5~66) winsize 62
2542 12:32:43.936248 [CA 4] Center 35 (5~65) winsize 61
2543 12:32:43.939597 [CA 5] Center 34 (4~65) winsize 62
2544 12:32:43.939710
2545 12:32:43.943030 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2546 12:32:43.943120
2547 12:32:43.946371 [CATrainingPosCal] consider 1 rank data
2548 12:32:43.949674 u2DelayCellTimex100 = 270/100 ps
2549 12:32:43.952988 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2550 12:32:43.959980 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2551 12:32:43.963278 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2552 12:32:43.966504 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2553 12:32:43.969864 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2554 12:32:43.973091 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2555 12:32:43.973199
2556 12:32:43.976277 CA PerBit enable=1, Macro0, CA PI delay=34
2557 12:32:43.976375
2558 12:32:43.979615 [CBTSetCACLKResult] CA Dly = 34
2559 12:32:43.979710 CS Dly: 7 (0~38)
2560 12:32:43.982892 ==
2561 12:32:43.986350 Dram Type= 6, Freq= 0, CH_0, rank 1
2562 12:32:43.989655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 12:32:43.989761 ==
2564 12:32:43.992921 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2565 12:32:43.999586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2566 12:32:44.009440 [CA 0] Center 39 (9~70) winsize 62
2567 12:32:44.012500 [CA 1] Center 39 (9~70) winsize 62
2568 12:32:44.015805 [CA 2] Center 36 (6~67) winsize 62
2569 12:32:44.018865 [CA 3] Center 36 (5~67) winsize 63
2570 12:32:44.022611 [CA 4] Center 34 (4~65) winsize 62
2571 12:32:44.025940 [CA 5] Center 34 (4~64) winsize 61
2572 12:32:44.026082
2573 12:32:44.029340 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2574 12:32:44.029452
2575 12:32:44.032570 [CATrainingPosCal] consider 2 rank data
2576 12:32:44.036028 u2DelayCellTimex100 = 270/100 ps
2577 12:32:44.039183 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2578 12:32:44.042453 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2579 12:32:44.049105 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2580 12:32:44.052487 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2581 12:32:44.055732 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2582 12:32:44.058896 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2583 12:32:44.059020
2584 12:32:44.062405 CA PerBit enable=1, Macro0, CA PI delay=34
2585 12:32:44.062502
2586 12:32:44.065765 [CBTSetCACLKResult] CA Dly = 34
2587 12:32:44.065861 CS Dly: 8 (0~41)
2588 12:32:44.065936
2589 12:32:44.068957 ----->DramcWriteLeveling(PI) begin...
2590 12:32:44.072292 ==
2591 12:32:44.072393 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 12:32:44.079390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 12:32:44.079549 ==
2594 12:32:44.082694 Write leveling (Byte 0): 28 => 28
2595 12:32:44.086042 Write leveling (Byte 1): 27 => 27
2596 12:32:44.086162 DramcWriteLeveling(PI) end<-----
2597 12:32:44.089362
2598 12:32:44.089478 ==
2599 12:32:44.092501 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 12:32:44.095901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 12:32:44.096004 ==
2602 12:32:44.099113 [Gating] SW mode calibration
2603 12:32:44.106298 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2604 12:32:44.108887 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2605 12:32:44.115823 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 12:32:44.119178 0 15 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2607 12:32:44.122261 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 12:32:44.129201 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 12:32:44.132725 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 12:32:44.136019 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2611 12:32:44.142753 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2612 12:32:44.145890 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2613 12:32:44.149178 1 0 0 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
2614 12:32:44.155919 1 0 4 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2615 12:32:44.159232 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 12:32:44.162603 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 12:32:44.169107 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 12:32:44.172586 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 12:32:44.175782 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2620 12:32:44.182506 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2621 12:32:44.185805 1 1 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2622 12:32:44.189090 1 1 4 | B1->B0 | 3938 4646 | 1 0 | (0 0) (0 0)
2623 12:32:44.195629 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 12:32:44.198975 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 12:32:44.202237 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 12:32:44.205746 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 12:32:44.212508 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 12:32:44.215753 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 12:32:44.218907 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2630 12:32:44.225859 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 12:32:44.229082 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 12:32:44.232299 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 12:32:44.239107 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 12:32:44.242231 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 12:32:44.245642 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 12:32:44.252138 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 12:32:44.255552 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 12:32:44.258702 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 12:32:44.265947 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 12:32:44.269155 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 12:32:44.272482 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 12:32:44.279090 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 12:32:44.282638 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 12:32:44.285898 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 12:32:44.292246 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2646 12:32:44.295630 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2647 12:32:44.298855 Total UI for P1: 0, mck2ui 16
2648 12:32:44.302129 best dqsien dly found for B0: ( 1, 4, 0)
2649 12:32:44.305591 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2650 12:32:44.308860 Total UI for P1: 0, mck2ui 16
2651 12:32:44.312087 best dqsien dly found for B1: ( 1, 4, 2)
2652 12:32:44.315689 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2653 12:32:44.319232 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2654 12:32:44.319378
2655 12:32:44.321785 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2656 12:32:44.325438 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2657 12:32:44.328632 [Gating] SW calibration Done
2658 12:32:44.328762 ==
2659 12:32:44.331966 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 12:32:44.338953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 12:32:44.339079 ==
2662 12:32:44.339166 RX Vref Scan: 0
2663 12:32:44.339231
2664 12:32:44.342231 RX Vref 0 -> 0, step: 1
2665 12:32:44.342355
2666 12:32:44.345531 RX Delay -40 -> 252, step: 8
2667 12:32:44.348838 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2668 12:32:44.352259 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2669 12:32:44.355587 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2670 12:32:44.358938 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2671 12:32:44.365371 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2672 12:32:44.368538 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2673 12:32:44.371798 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2674 12:32:44.375206 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2675 12:32:44.378484 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2676 12:32:44.385077 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2677 12:32:44.388981 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2678 12:32:44.391969 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2679 12:32:44.395374 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2680 12:32:44.398782 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2681 12:32:44.405363 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2682 12:32:44.408587 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2683 12:32:44.408694 ==
2684 12:32:44.411916 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 12:32:44.415419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 12:32:44.415523 ==
2687 12:32:44.415594 DQS Delay:
2688 12:32:44.418539 DQS0 = 0, DQS1 = 0
2689 12:32:44.418633 DQM Delay:
2690 12:32:44.421911 DQM0 = 116, DQM1 = 107
2691 12:32:44.422011 DQ Delay:
2692 12:32:44.425703 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2693 12:32:44.428946 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2694 12:32:44.432171 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2695 12:32:44.435396 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =111
2696 12:32:44.438498
2697 12:32:44.438625
2698 12:32:44.438722 ==
2699 12:32:44.441804 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 12:32:44.445140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 12:32:44.445283 ==
2702 12:32:44.445395
2703 12:32:44.445499
2704 12:32:44.448448 TX Vref Scan disable
2705 12:32:44.448591 == TX Byte 0 ==
2706 12:32:44.455112 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2707 12:32:44.458283 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2708 12:32:44.458403 == TX Byte 1 ==
2709 12:32:44.465618 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2710 12:32:44.468770 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2711 12:32:44.468881 ==
2712 12:32:44.472017 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 12:32:44.475145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2714 12:32:44.475266 ==
2715 12:32:44.487807 TX Vref=22, minBit 4, minWin=25, winSum=422
2716 12:32:44.491048 TX Vref=24, minBit 4, minWin=25, winSum=424
2717 12:32:44.494485 TX Vref=26, minBit 5, minWin=25, winSum=432
2718 12:32:44.497600 TX Vref=28, minBit 1, minWin=26, winSum=432
2719 12:32:44.500907 TX Vref=30, minBit 1, minWin=26, winSum=439
2720 12:32:44.504192 TX Vref=32, minBit 4, minWin=26, winSum=437
2721 12:32:44.511425 [TxChooseVref] Worse bit 1, Min win 26, Win sum 439, Final Vref 30
2722 12:32:44.511555
2723 12:32:44.514148 Final TX Range 1 Vref 30
2724 12:32:44.514240
2725 12:32:44.514327 ==
2726 12:32:44.517970 Dram Type= 6, Freq= 0, CH_0, rank 0
2727 12:32:44.521222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2728 12:32:44.521318 ==
2729 12:32:44.521408
2730 12:32:44.521490
2731 12:32:44.524515 TX Vref Scan disable
2732 12:32:44.527704 == TX Byte 0 ==
2733 12:32:44.531504 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2734 12:32:44.534816 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2735 12:32:44.537863 == TX Byte 1 ==
2736 12:32:44.541162 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2737 12:32:44.544271 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2738 12:32:44.544370
2739 12:32:44.548006 [DATLAT]
2740 12:32:44.548111 Freq=1200, CH0 RK0
2741 12:32:44.548201
2742 12:32:44.551203 DATLAT Default: 0xd
2743 12:32:44.551320 0, 0xFFFF, sum = 0
2744 12:32:44.554415 1, 0xFFFF, sum = 0
2745 12:32:44.554537 2, 0xFFFF, sum = 0
2746 12:32:44.557664 3, 0xFFFF, sum = 0
2747 12:32:44.557756 4, 0xFFFF, sum = 0
2748 12:32:44.560911 5, 0xFFFF, sum = 0
2749 12:32:44.561005 6, 0xFFFF, sum = 0
2750 12:32:44.564789 7, 0xFFFF, sum = 0
2751 12:32:44.564889 8, 0xFFFF, sum = 0
2752 12:32:44.568042 9, 0xFFFF, sum = 0
2753 12:32:44.568136 10, 0xFFFF, sum = 0
2754 12:32:44.571216 11, 0xFFFF, sum = 0
2755 12:32:44.571335 12, 0x0, sum = 1
2756 12:32:44.574452 13, 0x0, sum = 2
2757 12:32:44.574545 14, 0x0, sum = 3
2758 12:32:44.577759 15, 0x0, sum = 4
2759 12:32:44.577856 best_step = 13
2760 12:32:44.577946
2761 12:32:44.578030 ==
2762 12:32:44.580982 Dram Type= 6, Freq= 0, CH_0, rank 0
2763 12:32:44.587610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2764 12:32:44.587740 ==
2765 12:32:44.587816 RX Vref Scan: 1
2766 12:32:44.587884
2767 12:32:44.590818 Set Vref Range= 32 -> 127
2768 12:32:44.590938
2769 12:32:44.594773 RX Vref 32 -> 127, step: 1
2770 12:32:44.594890
2771 12:32:44.598108 RX Delay -21 -> 252, step: 4
2772 12:32:44.598190
2773 12:32:44.601151 Set Vref, RX VrefLevel [Byte0]: 32
2774 12:32:44.601235 [Byte1]: 32
2775 12:32:44.605829
2776 12:32:44.605918 Set Vref, RX VrefLevel [Byte0]: 33
2777 12:32:44.609119 [Byte1]: 33
2778 12:32:44.613722
2779 12:32:44.613846 Set Vref, RX VrefLevel [Byte0]: 34
2780 12:32:44.616940 [Byte1]: 34
2781 12:32:44.621556
2782 12:32:44.624814 Set Vref, RX VrefLevel [Byte0]: 35
2783 12:32:44.624907 [Byte1]: 35
2784 12:32:44.629501
2785 12:32:44.629601 Set Vref, RX VrefLevel [Byte0]: 36
2786 12:32:44.632774 [Byte1]: 36
2787 12:32:44.637259
2788 12:32:44.637394 Set Vref, RX VrefLevel [Byte0]: 37
2789 12:32:44.641163 [Byte1]: 37
2790 12:32:44.645546
2791 12:32:44.645653 Set Vref, RX VrefLevel [Byte0]: 38
2792 12:32:44.648859 [Byte1]: 38
2793 12:32:44.653165
2794 12:32:44.653272 Set Vref, RX VrefLevel [Byte0]: 39
2795 12:32:44.656477 [Byte1]: 39
2796 12:32:44.661126
2797 12:32:44.661229 Set Vref, RX VrefLevel [Byte0]: 40
2798 12:32:44.664354 [Byte1]: 40
2799 12:32:44.669467
2800 12:32:44.669581 Set Vref, RX VrefLevel [Byte0]: 41
2801 12:32:44.672797 [Byte1]: 41
2802 12:32:44.676855
2803 12:32:44.676984 Set Vref, RX VrefLevel [Byte0]: 42
2804 12:32:44.680181 [Byte1]: 42
2805 12:32:44.685452
2806 12:32:44.685588 Set Vref, RX VrefLevel [Byte0]: 43
2807 12:32:44.688755 [Byte1]: 43
2808 12:32:44.693245
2809 12:32:44.693374 Set Vref, RX VrefLevel [Byte0]: 44
2810 12:32:44.696337 [Byte1]: 44
2811 12:32:44.701055
2812 12:32:44.701203 Set Vref, RX VrefLevel [Byte0]: 45
2813 12:32:44.704355 [Byte1]: 45
2814 12:32:44.708895
2815 12:32:44.709026 Set Vref, RX VrefLevel [Byte0]: 46
2816 12:32:44.712176 [Byte1]: 46
2817 12:32:44.716727
2818 12:32:44.716862 Set Vref, RX VrefLevel [Byte0]: 47
2819 12:32:44.719959 [Byte1]: 47
2820 12:32:44.724657
2821 12:32:44.724784 Set Vref, RX VrefLevel [Byte0]: 48
2822 12:32:44.727924 [Byte1]: 48
2823 12:32:44.732445
2824 12:32:44.732584 Set Vref, RX VrefLevel [Byte0]: 49
2825 12:32:44.735663 [Byte1]: 49
2826 12:32:44.740259
2827 12:32:44.740400 Set Vref, RX VrefLevel [Byte0]: 50
2828 12:32:44.744040 [Byte1]: 50
2829 12:32:44.748555
2830 12:32:44.748711 Set Vref, RX VrefLevel [Byte0]: 51
2831 12:32:44.751814 [Byte1]: 51
2832 12:32:44.756383
2833 12:32:44.756531 Set Vref, RX VrefLevel [Byte0]: 52
2834 12:32:44.759587 [Byte1]: 52
2835 12:32:44.764384
2836 12:32:44.764535 Set Vref, RX VrefLevel [Byte0]: 53
2837 12:32:44.767686 [Byte1]: 53
2838 12:32:44.772056
2839 12:32:44.772199 Set Vref, RX VrefLevel [Byte0]: 54
2840 12:32:44.775735 [Byte1]: 54
2841 12:32:44.780150
2842 12:32:44.780291 Set Vref, RX VrefLevel [Byte0]: 55
2843 12:32:44.783385 [Byte1]: 55
2844 12:32:44.788058
2845 12:32:44.788207 Set Vref, RX VrefLevel [Byte0]: 56
2846 12:32:44.791390 [Byte1]: 56
2847 12:32:44.796019
2848 12:32:44.796139 Set Vref, RX VrefLevel [Byte0]: 57
2849 12:32:44.799057 [Byte1]: 57
2850 12:32:44.803896
2851 12:32:44.804015 Set Vref, RX VrefLevel [Byte0]: 58
2852 12:32:44.807189 [Byte1]: 58
2853 12:32:44.811615
2854 12:32:44.811785 Set Vref, RX VrefLevel [Byte0]: 59
2855 12:32:44.815039 [Byte1]: 59
2856 12:32:44.819609
2857 12:32:44.819720 Set Vref, RX VrefLevel [Byte0]: 60
2858 12:32:44.822858 [Byte1]: 60
2859 12:32:44.827503
2860 12:32:44.827628 Set Vref, RX VrefLevel [Byte0]: 61
2861 12:32:44.830892 [Byte1]: 61
2862 12:32:44.835315
2863 12:32:44.835471 Set Vref, RX VrefLevel [Byte0]: 62
2864 12:32:44.838761 [Byte1]: 62
2865 12:32:44.843572
2866 12:32:44.843700 Set Vref, RX VrefLevel [Byte0]: 63
2867 12:32:44.846865 [Byte1]: 63
2868 12:32:44.851748
2869 12:32:44.851876 Set Vref, RX VrefLevel [Byte0]: 64
2870 12:32:44.854885 [Byte1]: 64
2871 12:32:44.859183
2872 12:32:44.859330 Set Vref, RX VrefLevel [Byte0]: 65
2873 12:32:44.863089 [Byte1]: 65
2874 12:32:44.867776
2875 12:32:44.867917 Set Vref, RX VrefLevel [Byte0]: 66
2876 12:32:44.870836 [Byte1]: 66
2877 12:32:44.875519
2878 12:32:44.875638 Set Vref, RX VrefLevel [Byte0]: 67
2879 12:32:44.878786 [Byte1]: 67
2880 12:32:44.883264
2881 12:32:44.883419 Set Vref, RX VrefLevel [Byte0]: 68
2882 12:32:44.886642 [Byte1]: 68
2883 12:32:44.891097
2884 12:32:44.891205 Final RX Vref Byte 0 = 53 to rank0
2885 12:32:44.894507 Final RX Vref Byte 1 = 51 to rank0
2886 12:32:44.897705 Final RX Vref Byte 0 = 53 to rank1
2887 12:32:44.901638 Final RX Vref Byte 1 = 51 to rank1==
2888 12:32:44.904835 Dram Type= 6, Freq= 0, CH_0, rank 0
2889 12:32:44.911400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 12:32:44.911538 ==
2891 12:32:44.911614 DQS Delay:
2892 12:32:44.911679 DQS0 = 0, DQS1 = 0
2893 12:32:44.914554 DQM Delay:
2894 12:32:44.914629 DQM0 = 115, DQM1 = 104
2895 12:32:44.917848 DQ Delay:
2896 12:32:44.921111 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =116
2897 12:32:44.924555 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2898 12:32:44.927789 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2899 12:32:44.931115 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
2900 12:32:44.931264
2901 12:32:44.931379
2902 12:32:44.937860 [DQSOSCAuto] RK0, (LSB)MR18= 0xffee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2903 12:32:44.941139 CH0 RK0: MR19=303, MR18=FFEE
2904 12:32:44.947849 CH0_RK0: MR19=0x303, MR18=0xFFEE, DQSOSC=410, MR23=63, INC=39, DEC=26
2905 12:32:44.948020
2906 12:32:44.950873 ----->DramcWriteLeveling(PI) begin...
2907 12:32:44.951005 ==
2908 12:32:44.954026 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 12:32:44.957834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 12:32:44.961118 ==
2911 12:32:44.961253 Write leveling (Byte 0): 31 => 31
2912 12:32:44.964211 Write leveling (Byte 1): 31 => 31
2913 12:32:44.967483 DramcWriteLeveling(PI) end<-----
2914 12:32:44.967583
2915 12:32:44.967660 ==
2916 12:32:44.971676 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 12:32:44.978121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 12:32:44.978283 ==
2919 12:32:44.978387 [Gating] SW mode calibration
2920 12:32:44.987960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2921 12:32:44.991295 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2922 12:32:44.994502 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2923 12:32:45.001072 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2924 12:32:45.004980 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 12:32:45.008375 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 12:32:45.014344 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 12:32:45.018219 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 12:32:45.020925 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2929 12:32:45.027987 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2930 12:32:45.031209 1 0 0 | B1->B0 | 2e2e 2929 | 0 0 | (0 0) (0 0)
2931 12:32:45.034568 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2932 12:32:45.041130 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 12:32:45.044456 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 12:32:45.048260 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 12:32:45.054760 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 12:32:45.057945 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
2937 12:32:45.061085 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2938 12:32:45.064279 1 1 0 | B1->B0 | 3030 3c3c | 0 1 | (0 0) (0 0)
2939 12:32:45.071199 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 12:32:45.075004 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 12:32:45.078121 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 12:32:45.084659 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 12:32:45.087920 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 12:32:45.091214 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 12:32:45.097901 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2946 12:32:45.101086 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2947 12:32:45.105021 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2948 12:32:45.111741 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 12:32:45.114321 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 12:32:45.118231 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 12:32:45.124760 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 12:32:45.128116 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 12:32:45.131225 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 12:32:45.137651 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 12:32:45.140873 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 12:32:45.144310 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 12:32:45.150900 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 12:32:45.154215 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 12:32:45.158217 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 12:32:45.161392 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2961 12:32:45.167727 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2962 12:32:45.170940 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2963 12:32:45.174947 Total UI for P1: 0, mck2ui 16
2964 12:32:45.177826 best dqsien dly found for B0: ( 1, 3, 26)
2965 12:32:45.181139 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 12:32:45.184496 Total UI for P1: 0, mck2ui 16
2967 12:32:45.187685 best dqsien dly found for B1: ( 1, 4, 0)
2968 12:32:45.191032 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2969 12:32:45.194780 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2970 12:32:45.194917
2971 12:32:45.201442 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2972 12:32:45.204721 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2973 12:32:45.204882 [Gating] SW calibration Done
2974 12:32:45.208003 ==
2975 12:32:45.211283 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 12:32:45.214674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 12:32:45.214797 ==
2978 12:32:45.214870 RX Vref Scan: 0
2979 12:32:45.214934
2980 12:32:45.217787 RX Vref 0 -> 0, step: 1
2981 12:32:45.217884
2982 12:32:45.221125 RX Delay -40 -> 252, step: 8
2983 12:32:45.224449 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2984 12:32:45.228236 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2985 12:32:45.231546 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2986 12:32:45.238144 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2987 12:32:45.241433 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2988 12:32:45.244861 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2989 12:32:45.248029 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2990 12:32:45.251333 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2991 12:32:45.257966 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2992 12:32:45.261179 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2993 12:32:45.264448 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2994 12:32:45.268361 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2995 12:32:45.271616 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2996 12:32:45.278082 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2997 12:32:45.281270 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2998 12:32:45.284582 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2999 12:32:45.284693 ==
3000 12:32:45.288391 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 12:32:45.291532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 12:32:45.291666 ==
3003 12:32:45.294805 DQS Delay:
3004 12:32:45.294929 DQS0 = 0, DQS1 = 0
3005 12:32:45.298060 DQM Delay:
3006 12:32:45.298180 DQM0 = 115, DQM1 = 106
3007 12:32:45.298278 DQ Delay:
3008 12:32:45.301473 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
3009 12:32:45.304658 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
3010 12:32:45.308004 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3011 12:32:45.314480 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3012 12:32:45.314638
3013 12:32:45.314742
3014 12:32:45.314834 ==
3015 12:32:45.318094 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 12:32:45.321489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 12:32:45.321614 ==
3018 12:32:45.321712
3019 12:32:45.321805
3020 12:32:45.324791 TX Vref Scan disable
3021 12:32:45.324907 == TX Byte 0 ==
3022 12:32:45.331284 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3023 12:32:45.334398 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3024 12:32:45.334528 == TX Byte 1 ==
3025 12:32:45.341091 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3026 12:32:45.344307 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3027 12:32:45.344448 ==
3028 12:32:45.348137 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 12:32:45.351463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 12:32:45.351615 ==
3031 12:32:45.363827 TX Vref=22, minBit 15, minWin=25, winSum=421
3032 12:32:45.367030 TX Vref=24, minBit 12, minWin=25, winSum=423
3033 12:32:45.370932 TX Vref=26, minBit 5, minWin=26, winSum=431
3034 12:32:45.374073 TX Vref=28, minBit 7, minWin=26, winSum=434
3035 12:32:45.377319 TX Vref=30, minBit 12, minWin=26, winSum=436
3036 12:32:45.384328 TX Vref=32, minBit 3, minWin=26, winSum=433
3037 12:32:45.387339 [TxChooseVref] Worse bit 12, Min win 26, Win sum 436, Final Vref 30
3038 12:32:45.387464
3039 12:32:45.390684 Final TX Range 1 Vref 30
3040 12:32:45.390800
3041 12:32:45.390896 ==
3042 12:32:45.393994 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 12:32:45.397312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 12:32:45.400497 ==
3045 12:32:45.400595
3046 12:32:45.400663
3047 12:32:45.400725 TX Vref Scan disable
3048 12:32:45.403663 == TX Byte 0 ==
3049 12:32:45.407703 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3050 12:32:45.413938 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3051 12:32:45.414103 == TX Byte 1 ==
3052 12:32:45.417248 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3053 12:32:45.424010 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3054 12:32:45.424174
3055 12:32:45.424282 [DATLAT]
3056 12:32:45.424384 Freq=1200, CH0 RK1
3057 12:32:45.424490
3058 12:32:45.427365 DATLAT Default: 0xd
3059 12:32:45.427491 0, 0xFFFF, sum = 0
3060 12:32:45.430745 1, 0xFFFF, sum = 0
3061 12:32:45.430889 2, 0xFFFF, sum = 0
3062 12:32:45.434096 3, 0xFFFF, sum = 0
3063 12:32:45.437226 4, 0xFFFF, sum = 0
3064 12:32:45.437377 5, 0xFFFF, sum = 0
3065 12:32:45.441191 6, 0xFFFF, sum = 0
3066 12:32:45.441333 7, 0xFFFF, sum = 0
3067 12:32:45.444202 8, 0xFFFF, sum = 0
3068 12:32:45.444328 9, 0xFFFF, sum = 0
3069 12:32:45.447431 10, 0xFFFF, sum = 0
3070 12:32:45.447536 11, 0xFFFF, sum = 0
3071 12:32:45.450895 12, 0x0, sum = 1
3072 12:32:45.451016 13, 0x0, sum = 2
3073 12:32:45.454231 14, 0x0, sum = 3
3074 12:32:45.454333 15, 0x0, sum = 4
3075 12:32:45.454404 best_step = 13
3076 12:32:45.457593
3077 12:32:45.457686 ==
3078 12:32:45.460920 Dram Type= 6, Freq= 0, CH_0, rank 1
3079 12:32:45.464171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3080 12:32:45.464279 ==
3081 12:32:45.464350 RX Vref Scan: 0
3082 12:32:45.464411
3083 12:32:45.467615 RX Vref 0 -> 0, step: 1
3084 12:32:45.467714
3085 12:32:45.470742 RX Delay -21 -> 252, step: 4
3086 12:32:45.474078 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3087 12:32:45.480895 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3088 12:32:45.484164 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3089 12:32:45.487148 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3090 12:32:45.490458 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3091 12:32:45.493614 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3092 12:32:45.500805 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3093 12:32:45.503656 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3094 12:32:45.507397 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3095 12:32:45.510623 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3096 12:32:45.513997 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3097 12:32:45.517441 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3098 12:32:45.524086 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3099 12:32:45.527295 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3100 12:32:45.530764 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3101 12:32:45.533949 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3102 12:32:45.534060 ==
3103 12:32:45.537141 Dram Type= 6, Freq= 0, CH_0, rank 1
3104 12:32:45.543846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 12:32:45.543975 ==
3106 12:32:45.544068 DQS Delay:
3107 12:32:45.547589 DQS0 = 0, DQS1 = 0
3108 12:32:45.547721 DQM Delay:
3109 12:32:45.550618 DQM0 = 114, DQM1 = 105
3110 12:32:45.550722 DQ Delay:
3111 12:32:45.553823 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3112 12:32:45.557174 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3113 12:32:45.560588 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3114 12:32:45.563885 DQ12 =110, DQ13 =112, DQ14 =118, DQ15 =114
3115 12:32:45.563995
3116 12:32:45.564067
3117 12:32:45.573625 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
3118 12:32:45.573776 CH0 RK1: MR19=403, MR18=3F4
3119 12:32:45.580179 CH0_RK1: MR19=0x403, MR18=0x3F4, DQSOSC=408, MR23=63, INC=39, DEC=26
3120 12:32:45.583993 [RxdqsGatingPostProcess] freq 1200
3121 12:32:45.590274 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3122 12:32:45.593599 best DQS0 dly(2T, 0.5T) = (0, 12)
3123 12:32:45.597230 best DQS1 dly(2T, 0.5T) = (0, 12)
3124 12:32:45.597344 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3125 12:32:45.600420 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3126 12:32:45.603479 best DQS0 dly(2T, 0.5T) = (0, 11)
3127 12:32:45.607454 best DQS1 dly(2T, 0.5T) = (0, 12)
3128 12:32:45.610129 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3129 12:32:45.613975 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3130 12:32:45.617249 Pre-setting of DQS Precalculation
3131 12:32:45.623820 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3132 12:32:45.623951 ==
3133 12:32:45.627093 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 12:32:45.630562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 12:32:45.630692 ==
3136 12:32:45.637106 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3137 12:32:45.640332 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3138 12:32:45.650020 [CA 0] Center 38 (8~68) winsize 61
3139 12:32:45.653222 [CA 1] Center 38 (8~68) winsize 61
3140 12:32:45.656510 [CA 2] Center 34 (4~65) winsize 62
3141 12:32:45.659744 [CA 3] Center 34 (4~65) winsize 62
3142 12:32:45.662980 [CA 4] Center 34 (4~65) winsize 62
3143 12:32:45.666237 [CA 5] Center 34 (4~64) winsize 61
3144 12:32:45.666371
3145 12:32:45.670166 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3146 12:32:45.670299
3147 12:32:45.672947 [CATrainingPosCal] consider 1 rank data
3148 12:32:45.676929 u2DelayCellTimex100 = 270/100 ps
3149 12:32:45.680268 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3150 12:32:45.683670 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3151 12:32:45.686803 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
3152 12:32:45.693217 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3153 12:32:45.696987 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3154 12:32:45.700012 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3155 12:32:45.700121
3156 12:32:45.703128 CA PerBit enable=1, Macro0, CA PI delay=34
3157 12:32:45.703235
3158 12:32:45.706843 [CBTSetCACLKResult] CA Dly = 34
3159 12:32:45.706981 CS Dly: 6 (0~37)
3160 12:32:45.707069 ==
3161 12:32:45.709965 Dram Type= 6, Freq= 0, CH_1, rank 1
3162 12:32:45.716671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 12:32:45.716809 ==
3164 12:32:45.719840 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3165 12:32:45.726360 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3166 12:32:45.735235 [CA 0] Center 38 (8~68) winsize 61
3167 12:32:45.738600 [CA 1] Center 38 (8~68) winsize 61
3168 12:32:45.741806 [CA 2] Center 34 (4~65) winsize 62
3169 12:32:45.745107 [CA 3] Center 34 (4~65) winsize 62
3170 12:32:45.749047 [CA 4] Center 34 (4~65) winsize 62
3171 12:32:45.752172 [CA 5] Center 33 (3~63) winsize 61
3172 12:32:45.752396
3173 12:32:45.755268 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3174 12:32:45.755431
3175 12:32:45.759090 [CATrainingPosCal] consider 2 rank data
3176 12:32:45.762365 u2DelayCellTimex100 = 270/100 ps
3177 12:32:45.765592 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3178 12:32:45.768745 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3179 12:32:45.775454 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3180 12:32:45.778688 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3181 12:32:45.781991 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3182 12:32:45.785301 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3183 12:32:45.785438
3184 12:32:45.788526 CA PerBit enable=1, Macro0, CA PI delay=33
3185 12:32:45.788621
3186 12:32:45.791755 [CBTSetCACLKResult] CA Dly = 33
3187 12:32:45.791880 CS Dly: 7 (0~40)
3188 12:32:45.791966
3189 12:32:45.795462 ----->DramcWriteLeveling(PI) begin...
3190 12:32:45.798810 ==
3191 12:32:45.798939 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 12:32:45.805723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 12:32:45.805854 ==
3194 12:32:45.808734 Write leveling (Byte 0): 26 => 26
3195 12:32:45.811970 Write leveling (Byte 1): 29 => 29
3196 12:32:45.815961 DramcWriteLeveling(PI) end<-----
3197 12:32:45.816089
3198 12:32:45.816159 ==
3199 12:32:45.819221 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 12:32:45.822125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 12:32:45.822220 ==
3202 12:32:45.825894 [Gating] SW mode calibration
3203 12:32:45.832236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3204 12:32:45.835497 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3205 12:32:45.842198 0 15 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3206 12:32:45.845660 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3207 12:32:45.848773 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 12:32:45.855337 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 12:32:45.859001 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3210 12:32:45.862105 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 12:32:45.869153 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 12:32:45.872436 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
3213 12:32:45.875590 1 0 0 | B1->B0 | 2424 2d2d | 0 0 | (1 0) (1 0)
3214 12:32:45.882169 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3215 12:32:45.885389 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3216 12:32:45.888825 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 12:32:45.895300 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 12:32:45.899118 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 12:32:45.902242 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 12:32:45.909054 1 0 28 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
3221 12:32:45.912281 1 1 0 | B1->B0 | 4545 3232 | 0 1 | (0 0) (0 0)
3222 12:32:45.915427 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 12:32:45.919252 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 12:32:45.925870 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 12:32:45.929094 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 12:32:45.932140 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 12:32:45.938882 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 12:32:45.942096 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 12:32:45.945418 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3230 12:32:45.952064 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 12:32:45.955918 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 12:32:45.959203 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 12:32:45.965760 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 12:32:45.968834 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 12:32:45.972118 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 12:32:45.978820 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 12:32:45.982060 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 12:32:45.985385 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 12:32:45.991841 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 12:32:45.995782 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 12:32:45.998469 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 12:32:46.005605 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 12:32:46.008737 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 12:32:46.011924 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3245 12:32:46.018961 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3246 12:32:46.022220 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3247 12:32:46.025555 Total UI for P1: 0, mck2ui 16
3248 12:32:46.028803 best dqsien dly found for B0: ( 1, 3, 30)
3249 12:32:46.032115 Total UI for P1: 0, mck2ui 16
3250 12:32:46.035561 best dqsien dly found for B1: ( 1, 4, 0)
3251 12:32:46.038816 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3252 12:32:46.042183 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3253 12:32:46.042353
3254 12:32:46.045282 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3255 12:32:46.048692 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3256 12:32:46.051952 [Gating] SW calibration Done
3257 12:32:46.052066 ==
3258 12:32:46.055047 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 12:32:46.059038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 12:32:46.059159 ==
3261 12:32:46.062186 RX Vref Scan: 0
3262 12:32:46.062278
3263 12:32:46.062349 RX Vref 0 -> 0, step: 1
3264 12:32:46.062413
3265 12:32:46.065484 RX Delay -40 -> 252, step: 8
3266 12:32:46.071837 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3267 12:32:46.075629 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3268 12:32:46.078943 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3269 12:32:46.081690 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3270 12:32:46.085472 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3271 12:32:46.088717 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3272 12:32:46.095330 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3273 12:32:46.098622 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3274 12:32:46.101975 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3275 12:32:46.105181 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3276 12:32:46.108470 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3277 12:32:46.115461 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3278 12:32:46.118684 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3279 12:32:46.121869 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3280 12:32:46.124899 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3281 12:32:46.128803 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3282 12:32:46.131510 ==
3283 12:32:46.134803 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 12:32:46.138619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 12:32:46.138725 ==
3286 12:32:46.138796 DQS Delay:
3287 12:32:46.141979 DQS0 = 0, DQS1 = 0
3288 12:32:46.142068 DQM Delay:
3289 12:32:46.145378 DQM0 = 115, DQM1 = 109
3290 12:32:46.145477 DQ Delay:
3291 12:32:46.148730 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3292 12:32:46.152134 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =111
3293 12:32:46.155239 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3294 12:32:46.158769 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115
3295 12:32:46.158931
3296 12:32:46.159038
3297 12:32:46.159135 ==
3298 12:32:46.161997 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 12:32:46.168412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 12:32:46.168563 ==
3301 12:32:46.168635
3302 12:32:46.168698
3303 12:32:46.168775 TX Vref Scan disable
3304 12:32:46.171903 == TX Byte 0 ==
3305 12:32:46.175062 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3306 12:32:46.181521 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3307 12:32:46.181679 == TX Byte 1 ==
3308 12:32:46.185305 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3309 12:32:46.191937 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3310 12:32:46.192064 ==
3311 12:32:46.195097 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 12:32:46.198285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 12:32:46.198422 ==
3314 12:32:46.209442 TX Vref=22, minBit 1, minWin=24, winSum=408
3315 12:32:46.213387 TX Vref=24, minBit 3, minWin=25, winSum=418
3316 12:32:46.216492 TX Vref=26, minBit 1, minWin=25, winSum=422
3317 12:32:46.219760 TX Vref=28, minBit 0, minWin=26, winSum=426
3318 12:32:46.222985 TX Vref=30, minBit 1, minWin=26, winSum=431
3319 12:32:46.226846 TX Vref=32, minBit 1, minWin=26, winSum=431
3320 12:32:46.233385 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3321 12:32:46.233538
3322 12:32:46.236707 Final TX Range 1 Vref 30
3323 12:32:46.236796
3324 12:32:46.236886 ==
3325 12:32:46.239882 Dram Type= 6, Freq= 0, CH_1, rank 0
3326 12:32:46.243225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3327 12:32:46.243361 ==
3328 12:32:46.243440
3329 12:32:46.243504
3330 12:32:46.246488 TX Vref Scan disable
3331 12:32:46.249837 == TX Byte 0 ==
3332 12:32:46.253104 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3333 12:32:46.256562 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3334 12:32:46.259725 == TX Byte 1 ==
3335 12:32:46.262889 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3336 12:32:46.266814 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3337 12:32:46.266936
3338 12:32:46.270129 [DATLAT]
3339 12:32:46.270225 Freq=1200, CH1 RK0
3340 12:32:46.270296
3341 12:32:46.273341 DATLAT Default: 0xd
3342 12:32:46.273427 0, 0xFFFF, sum = 0
3343 12:32:46.276643 1, 0xFFFF, sum = 0
3344 12:32:46.276733 2, 0xFFFF, sum = 0
3345 12:32:46.279940 3, 0xFFFF, sum = 0
3346 12:32:46.280039 4, 0xFFFF, sum = 0
3347 12:32:46.283222 5, 0xFFFF, sum = 0
3348 12:32:46.283341 6, 0xFFFF, sum = 0
3349 12:32:46.286417 7, 0xFFFF, sum = 0
3350 12:32:46.286537 8, 0xFFFF, sum = 0
3351 12:32:46.289738 9, 0xFFFF, sum = 0
3352 12:32:46.293066 10, 0xFFFF, sum = 0
3353 12:32:46.293213 11, 0xFFFF, sum = 0
3354 12:32:46.296254 12, 0x0, sum = 1
3355 12:32:46.296371 13, 0x0, sum = 2
3356 12:32:46.296467 14, 0x0, sum = 3
3357 12:32:46.299697 15, 0x0, sum = 4
3358 12:32:46.299806 best_step = 13
3359 12:32:46.299899
3360 12:32:46.299987 ==
3361 12:32:46.302994 Dram Type= 6, Freq= 0, CH_1, rank 0
3362 12:32:46.310141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3363 12:32:46.310280 ==
3364 12:32:46.310378 RX Vref Scan: 1
3365 12:32:46.310467
3366 12:32:46.312890 Set Vref Range= 32 -> 127
3367 12:32:46.312993
3368 12:32:46.316698 RX Vref 32 -> 127, step: 1
3369 12:32:46.316807
3370 12:32:46.320123 RX Delay -21 -> 252, step: 4
3371 12:32:46.320227
3372 12:32:46.323246 Set Vref, RX VrefLevel [Byte0]: 32
3373 12:32:46.326432 [Byte1]: 32
3374 12:32:46.326545
3375 12:32:46.329741 Set Vref, RX VrefLevel [Byte0]: 33
3376 12:32:46.333494 [Byte1]: 33
3377 12:32:46.333608
3378 12:32:46.336733 Set Vref, RX VrefLevel [Byte0]: 34
3379 12:32:46.339939 [Byte1]: 34
3380 12:32:46.343983
3381 12:32:46.344099 Set Vref, RX VrefLevel [Byte0]: 35
3382 12:32:46.347353 [Byte1]: 35
3383 12:32:46.351853
3384 12:32:46.351980 Set Vref, RX VrefLevel [Byte0]: 36
3385 12:32:46.355268 [Byte1]: 36
3386 12:32:46.359721
3387 12:32:46.359843 Set Vref, RX VrefLevel [Byte0]: 37
3388 12:32:46.363008 [Byte1]: 37
3389 12:32:46.367520
3390 12:32:46.367648 Set Vref, RX VrefLevel [Byte0]: 38
3391 12:32:46.370635 [Byte1]: 38
3392 12:32:46.375825
3393 12:32:46.375934 Set Vref, RX VrefLevel [Byte0]: 39
3394 12:32:46.379066 [Byte1]: 39
3395 12:32:46.383521
3396 12:32:46.383624 Set Vref, RX VrefLevel [Byte0]: 40
3397 12:32:46.386924 [Byte1]: 40
3398 12:32:46.391379
3399 12:32:46.391490 Set Vref, RX VrefLevel [Byte0]: 41
3400 12:32:46.394683 [Byte1]: 41
3401 12:32:46.399426
3402 12:32:46.399560 Set Vref, RX VrefLevel [Byte0]: 42
3403 12:32:46.402533 [Byte1]: 42
3404 12:32:46.407157
3405 12:32:46.407306 Set Vref, RX VrefLevel [Byte0]: 43
3406 12:32:46.410383 [Byte1]: 43
3407 12:32:46.415026
3408 12:32:46.415151 Set Vref, RX VrefLevel [Byte0]: 44
3409 12:32:46.418366 [Byte1]: 44
3410 12:32:46.422776
3411 12:32:46.422913 Set Vref, RX VrefLevel [Byte0]: 45
3412 12:32:46.426097 [Byte1]: 45
3413 12:32:46.431078
3414 12:32:46.431202 Set Vref, RX VrefLevel [Byte0]: 46
3415 12:32:46.434125 [Byte1]: 46
3416 12:32:46.438672
3417 12:32:46.438798 Set Vref, RX VrefLevel [Byte0]: 47
3418 12:32:46.441966 [Byte1]: 47
3419 12:32:46.446457
3420 12:32:46.446569 Set Vref, RX VrefLevel [Byte0]: 48
3421 12:32:46.450278 [Byte1]: 48
3422 12:32:46.454761
3423 12:32:46.454880 Set Vref, RX VrefLevel [Byte0]: 49
3424 12:32:46.458096 [Byte1]: 49
3425 12:32:46.462604
3426 12:32:46.462714 Set Vref, RX VrefLevel [Byte0]: 50
3427 12:32:46.465986 [Byte1]: 50
3428 12:32:46.470429
3429 12:32:46.470549 Set Vref, RX VrefLevel [Byte0]: 51
3430 12:32:46.473780 [Byte1]: 51
3431 12:32:46.478621
3432 12:32:46.478742 Set Vref, RX VrefLevel [Byte0]: 52
3433 12:32:46.481956 [Byte1]: 52
3434 12:32:46.486498
3435 12:32:46.486620 Set Vref, RX VrefLevel [Byte0]: 53
3436 12:32:46.489840 [Byte1]: 53
3437 12:32:46.494468
3438 12:32:46.494592 Set Vref, RX VrefLevel [Byte0]: 54
3439 12:32:46.497721 [Byte1]: 54
3440 12:32:46.502234
3441 12:32:46.502352 Set Vref, RX VrefLevel [Byte0]: 55
3442 12:32:46.505837 [Byte1]: 55
3443 12:32:46.510399
3444 12:32:46.510513 Set Vref, RX VrefLevel [Byte0]: 56
3445 12:32:46.513659 [Byte1]: 56
3446 12:32:46.518251
3447 12:32:46.518368 Set Vref, RX VrefLevel [Byte0]: 57
3448 12:32:46.521556 [Byte1]: 57
3449 12:32:46.525799
3450 12:32:46.525910 Set Vref, RX VrefLevel [Byte0]: 58
3451 12:32:46.529075 [Byte1]: 58
3452 12:32:46.533679
3453 12:32:46.533795 Set Vref, RX VrefLevel [Byte0]: 59
3454 12:32:46.537090 [Byte1]: 59
3455 12:32:46.541640
3456 12:32:46.541763 Set Vref, RX VrefLevel [Byte0]: 60
3457 12:32:46.544903 [Byte1]: 60
3458 12:32:46.549594
3459 12:32:46.549721 Set Vref, RX VrefLevel [Byte0]: 61
3460 12:32:46.553110 [Byte1]: 61
3461 12:32:46.557729
3462 12:32:46.557860 Set Vref, RX VrefLevel [Byte0]: 62
3463 12:32:46.561129 [Byte1]: 62
3464 12:32:46.565757
3465 12:32:46.565879 Set Vref, RX VrefLevel [Byte0]: 63
3466 12:32:46.569080 [Byte1]: 63
3467 12:32:46.573775
3468 12:32:46.573892 Set Vref, RX VrefLevel [Byte0]: 64
3469 12:32:46.576544 [Byte1]: 64
3470 12:32:46.581318
3471 12:32:46.581444 Set Vref, RX VrefLevel [Byte0]: 65
3472 12:32:46.584748 [Byte1]: 65
3473 12:32:46.589220
3474 12:32:46.589335 Set Vref, RX VrefLevel [Byte0]: 66
3475 12:32:46.592509 [Byte1]: 66
3476 12:32:46.597126
3477 12:32:46.597230 Set Vref, RX VrefLevel [Byte0]: 67
3478 12:32:46.600332 [Byte1]: 67
3479 12:32:46.604904
3480 12:32:46.605042 Set Vref, RX VrefLevel [Byte0]: 68
3481 12:32:46.608826 [Byte1]: 68
3482 12:32:46.612961
3483 12:32:46.616116 Set Vref, RX VrefLevel [Byte0]: 69
3484 12:32:46.616246 [Byte1]: 69
3485 12:32:46.620914
3486 12:32:46.621033 Set Vref, RX VrefLevel [Byte0]: 70
3487 12:32:46.624394 [Byte1]: 70
3488 12:32:46.628901
3489 12:32:46.629010 Set Vref, RX VrefLevel [Byte0]: 71
3490 12:32:46.632274 [Byte1]: 71
3491 12:32:46.636562
3492 12:32:46.636670 Set Vref, RX VrefLevel [Byte0]: 72
3493 12:32:46.640458 [Byte1]: 72
3494 12:32:46.644844
3495 12:32:46.644951 Final RX Vref Byte 0 = 53 to rank0
3496 12:32:46.647905 Final RX Vref Byte 1 = 51 to rank0
3497 12:32:46.651121 Final RX Vref Byte 0 = 53 to rank1
3498 12:32:46.654441 Final RX Vref Byte 1 = 51 to rank1==
3499 12:32:46.658506 Dram Type= 6, Freq= 0, CH_1, rank 0
3500 12:32:46.665007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 12:32:46.665151 ==
3502 12:32:46.665254 DQS Delay:
3503 12:32:46.665355 DQS0 = 0, DQS1 = 0
3504 12:32:46.668228 DQM Delay:
3505 12:32:46.668368 DQM0 = 115, DQM1 = 109
3506 12:32:46.671644 DQ Delay:
3507 12:32:46.674900 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =114
3508 12:32:46.678281 DQ4 =114, DQ5 =124, DQ6 =126, DQ7 =114
3509 12:32:46.681458 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3510 12:32:46.684700 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3511 12:32:46.684822
3512 12:32:46.684918
3513 12:32:46.691993 [DQSOSCAuto] RK0, (LSB)MR18= 0xfee3, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3514 12:32:46.694579 CH1 RK0: MR19=303, MR18=FEE3
3515 12:32:46.701899 CH1_RK0: MR19=0x303, MR18=0xFEE3, DQSOSC=410, MR23=63, INC=39, DEC=26
3516 12:32:46.702044
3517 12:32:46.705081 ----->DramcWriteLeveling(PI) begin...
3518 12:32:46.705208 ==
3519 12:32:46.708202 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 12:32:46.711627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 12:32:46.711788 ==
3522 12:32:46.714923 Write leveling (Byte 0): 28 => 28
3523 12:32:46.718312 Write leveling (Byte 1): 29 => 29
3524 12:32:46.721605 DramcWriteLeveling(PI) end<-----
3525 12:32:46.721751
3526 12:32:46.721855 ==
3527 12:32:46.725007 Dram Type= 6, Freq= 0, CH_1, rank 1
3528 12:32:46.731845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3529 12:32:46.732013 ==
3530 12:32:46.732114 [Gating] SW mode calibration
3531 12:32:46.741580 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3532 12:32:46.745034 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3533 12:32:46.748121 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3534 12:32:46.755108 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3535 12:32:46.758568 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3536 12:32:46.761989 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3537 12:32:46.767895 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3538 12:32:46.771193 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3539 12:32:46.774526 0 15 24 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
3540 12:32:46.781232 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3541 12:32:46.784513 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3542 12:32:46.787938 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3543 12:32:46.794589 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3544 12:32:46.797974 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3545 12:32:46.801347 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3546 12:32:46.807979 1 0 20 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
3547 12:32:46.811222 1 0 24 | B1->B0 | 2525 3838 | 0 0 | (0 0) (1 1)
3548 12:32:46.814567 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
3549 12:32:46.821385 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3550 12:32:46.824647 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3551 12:32:46.828048 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 12:32:46.834589 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3553 12:32:46.837828 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 12:32:46.841247 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3555 12:32:46.847535 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3556 12:32:46.851166 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3557 12:32:46.854386 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 12:32:46.860940 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 12:32:46.864310 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 12:32:46.867774 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 12:32:46.874315 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 12:32:46.877804 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 12:32:46.880476 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 12:32:46.887251 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 12:32:46.890523 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 12:32:46.893742 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 12:32:46.900697 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 12:32:46.903913 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 12:32:46.907295 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 12:32:46.910652 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3571 12:32:46.916834 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3572 12:32:46.920933 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3573 12:32:46.923816 Total UI for P1: 0, mck2ui 16
3574 12:32:46.927202 best dqsien dly found for B0: ( 1, 3, 22)
3575 12:32:46.930525 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3576 12:32:46.933839 Total UI for P1: 0, mck2ui 16
3577 12:32:46.937148 best dqsien dly found for B1: ( 1, 3, 28)
3578 12:32:46.940374 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3579 12:32:46.943878 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3580 12:32:46.944013
3581 12:32:46.950241 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3582 12:32:46.954204 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3583 12:32:46.957280 [Gating] SW calibration Done
3584 12:32:46.957415 ==
3585 12:32:46.960486 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 12:32:46.963683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 12:32:46.963817 ==
3588 12:32:46.963913 RX Vref Scan: 0
3589 12:32:46.964004
3590 12:32:46.966798 RX Vref 0 -> 0, step: 1
3591 12:32:46.966904
3592 12:32:46.970178 RX Delay -40 -> 252, step: 8
3593 12:32:46.973400 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3594 12:32:46.976725 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3595 12:32:46.983883 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3596 12:32:46.987128 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3597 12:32:46.990507 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3598 12:32:46.993846 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3599 12:32:46.997285 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3600 12:32:47.003918 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3601 12:32:47.007122 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3602 12:32:47.010381 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3603 12:32:47.013831 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3604 12:32:47.016945 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3605 12:32:47.023587 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3606 12:32:47.026736 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3607 12:32:47.030047 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3608 12:32:47.033475 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3609 12:32:47.033598 ==
3610 12:32:47.036794 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 12:32:47.043560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 12:32:47.043705 ==
3613 12:32:47.043789 DQS Delay:
3614 12:32:47.046187 DQS0 = 0, DQS1 = 0
3615 12:32:47.046330 DQM Delay:
3616 12:32:47.046433 DQM0 = 114, DQM1 = 110
3617 12:32:47.049657 DQ Delay:
3618 12:32:47.052931 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3619 12:32:47.056312 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3620 12:32:47.059567 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3621 12:32:47.063501 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3622 12:32:47.063661
3623 12:32:47.063764
3624 12:32:47.063864 ==
3625 12:32:47.066097 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 12:32:47.069970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 12:32:47.073371 ==
3628 12:32:47.073505
3629 12:32:47.073603
3630 12:32:47.073695 TX Vref Scan disable
3631 12:32:47.076614 == TX Byte 0 ==
3632 12:32:47.079868 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3633 12:32:47.082988 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3634 12:32:47.086214 == TX Byte 1 ==
3635 12:32:47.089465 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3636 12:32:47.093417 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3637 12:32:47.093552 ==
3638 12:32:47.096689 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 12:32:47.102668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 12:32:47.102799 ==
3641 12:32:47.113397 TX Vref=22, minBit 2, minWin=25, winSum=421
3642 12:32:47.116734 TX Vref=24, minBit 0, minWin=25, winSum=425
3643 12:32:47.119945 TX Vref=26, minBit 2, minWin=26, winSum=431
3644 12:32:47.123890 TX Vref=28, minBit 2, minWin=26, winSum=434
3645 12:32:47.126995 TX Vref=30, minBit 2, minWin=26, winSum=434
3646 12:32:47.133410 TX Vref=32, minBit 2, minWin=26, winSum=433
3647 12:32:47.137191 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 28
3648 12:32:47.137330
3649 12:32:47.140596 Final TX Range 1 Vref 28
3650 12:32:47.140726
3651 12:32:47.140825 ==
3652 12:32:47.143743 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 12:32:47.146703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 12:32:47.146868 ==
3655 12:32:47.150077
3656 12:32:47.150218
3657 12:32:47.150327 TX Vref Scan disable
3658 12:32:47.153328 == TX Byte 0 ==
3659 12:32:47.156712 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3660 12:32:47.159895 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3661 12:32:47.163739 == TX Byte 1 ==
3662 12:32:47.166812 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3663 12:32:47.170122 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3664 12:32:47.173136
3665 12:32:47.173253 [DATLAT]
3666 12:32:47.173358 Freq=1200, CH1 RK1
3667 12:32:47.173460
3668 12:32:47.177033 DATLAT Default: 0xd
3669 12:32:47.177155 0, 0xFFFF, sum = 0
3670 12:32:47.179754 1, 0xFFFF, sum = 0
3671 12:32:47.179876 2, 0xFFFF, sum = 0
3672 12:32:47.183567 3, 0xFFFF, sum = 0
3673 12:32:47.183690 4, 0xFFFF, sum = 0
3674 12:32:47.186785 5, 0xFFFF, sum = 0
3675 12:32:47.190136 6, 0xFFFF, sum = 0
3676 12:32:47.190272 7, 0xFFFF, sum = 0
3677 12:32:47.193439 8, 0xFFFF, sum = 0
3678 12:32:47.193554 9, 0xFFFF, sum = 0
3679 12:32:47.196905 10, 0xFFFF, sum = 0
3680 12:32:47.197021 11, 0xFFFF, sum = 0
3681 12:32:47.199458 12, 0x0, sum = 1
3682 12:32:47.199569 13, 0x0, sum = 2
3683 12:32:47.202834 14, 0x0, sum = 3
3684 12:32:47.202947 15, 0x0, sum = 4
3685 12:32:47.203042 best_step = 13
3686 12:32:47.206813
3687 12:32:47.206926 ==
3688 12:32:47.209529 Dram Type= 6, Freq= 0, CH_1, rank 1
3689 12:32:47.212717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3690 12:32:47.212834 ==
3691 12:32:47.212935 RX Vref Scan: 0
3692 12:32:47.213029
3693 12:32:47.216727 RX Vref 0 -> 0, step: 1
3694 12:32:47.216845
3695 12:32:47.219368 RX Delay -21 -> 252, step: 4
3696 12:32:47.223325 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3697 12:32:47.229838 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3698 12:32:47.232942 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3699 12:32:47.236103 iDelay=191, Bit 3, Center 110 (43 ~ 178) 136
3700 12:32:47.239562 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3701 12:32:47.242636 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3702 12:32:47.249154 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3703 12:32:47.253148 iDelay=191, Bit 7, Center 110 (43 ~ 178) 136
3704 12:32:47.256150 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3705 12:32:47.259524 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3706 12:32:47.262880 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3707 12:32:47.269155 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3708 12:32:47.272327 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3709 12:32:47.276097 iDelay=191, Bit 13, Center 116 (51 ~ 182) 132
3710 12:32:47.279237 iDelay=191, Bit 14, Center 116 (51 ~ 182) 132
3711 12:32:47.285723 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3712 12:32:47.285896 ==
3713 12:32:47.288886 Dram Type= 6, Freq= 0, CH_1, rank 1
3714 12:32:47.292828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3715 12:32:47.292971 ==
3716 12:32:47.293073 DQS Delay:
3717 12:32:47.296092 DQS0 = 0, DQS1 = 0
3718 12:32:47.296196 DQM Delay:
3719 12:32:47.299301 DQM0 = 112, DQM1 = 108
3720 12:32:47.299431 DQ Delay:
3721 12:32:47.302559 DQ0 =112, DQ1 =108, DQ2 =104, DQ3 =110
3722 12:32:47.305781 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =110
3723 12:32:47.309119 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =100
3724 12:32:47.312535 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3725 12:32:47.312665
3726 12:32:47.312757
3727 12:32:47.322477 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5fc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 414 ps
3728 12:32:47.325746 CH1 RK1: MR19=303, MR18=F5FC
3729 12:32:47.328998 CH1_RK1: MR19=0x303, MR18=0xF5FC, DQSOSC=411, MR23=63, INC=38, DEC=25
3730 12:32:47.332136 [RxdqsGatingPostProcess] freq 1200
3731 12:32:47.339204 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3732 12:32:47.342405 best DQS0 dly(2T, 0.5T) = (0, 11)
3733 12:32:47.345652 best DQS1 dly(2T, 0.5T) = (0, 12)
3734 12:32:47.349002 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3735 12:32:47.352398 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3736 12:32:47.355708 best DQS0 dly(2T, 0.5T) = (0, 11)
3737 12:32:47.359008 best DQS1 dly(2T, 0.5T) = (0, 11)
3738 12:32:47.362446 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3739 12:32:47.365777 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3740 12:32:47.368935 Pre-setting of DQS Precalculation
3741 12:32:47.372259 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3742 12:32:47.378693 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3743 12:32:47.385545 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3744 12:32:47.385723
3745 12:32:47.388823
3746 12:32:47.388940 [Calibration Summary] 2400 Mbps
3747 12:32:47.392293 CH 0, Rank 0
3748 12:32:47.392424 SW Impedance : PASS
3749 12:32:47.395636 DUTY Scan : NO K
3750 12:32:47.398929 ZQ Calibration : PASS
3751 12:32:47.399062 Jitter Meter : NO K
3752 12:32:47.402234 CBT Training : PASS
3753 12:32:47.404935 Write leveling : PASS
3754 12:32:47.405085 RX DQS gating : PASS
3755 12:32:47.408290 RX DQ/DQS(RDDQC) : PASS
3756 12:32:47.412192 TX DQ/DQS : PASS
3757 12:32:47.412324 RX DATLAT : PASS
3758 12:32:47.415469 RX DQ/DQS(Engine): PASS
3759 12:32:47.418205 TX OE : NO K
3760 12:32:47.418327 All Pass.
3761 12:32:47.418423
3762 12:32:47.418511 CH 0, Rank 1
3763 12:32:47.422127 SW Impedance : PASS
3764 12:32:47.425404 DUTY Scan : NO K
3765 12:32:47.425525 ZQ Calibration : PASS
3766 12:32:47.428205 Jitter Meter : NO K
3767 12:32:47.428325 CBT Training : PASS
3768 12:32:47.431979 Write leveling : PASS
3769 12:32:47.435300 RX DQS gating : PASS
3770 12:32:47.435430 RX DQ/DQS(RDDQC) : PASS
3771 12:32:47.438498 TX DQ/DQS : PASS
3772 12:32:47.441840 RX DATLAT : PASS
3773 12:32:47.441966 RX DQ/DQS(Engine): PASS
3774 12:32:47.444945 TX OE : NO K
3775 12:32:47.445064 All Pass.
3776 12:32:47.445161
3777 12:32:47.448097 CH 1, Rank 0
3778 12:32:47.448189 SW Impedance : PASS
3779 12:32:47.451625 DUTY Scan : NO K
3780 12:32:47.454949 ZQ Calibration : PASS
3781 12:32:47.455103 Jitter Meter : NO K
3782 12:32:47.458294 CBT Training : PASS
3783 12:32:47.461606 Write leveling : PASS
3784 12:32:47.461709 RX DQS gating : PASS
3785 12:32:47.465052 RX DQ/DQS(RDDQC) : PASS
3786 12:32:47.468438 TX DQ/DQS : PASS
3787 12:32:47.468582 RX DATLAT : PASS
3788 12:32:47.471693 RX DQ/DQS(Engine): PASS
3789 12:32:47.474980 TX OE : NO K
3790 12:32:47.475129 All Pass.
3791 12:32:47.475231
3792 12:32:47.475327 CH 1, Rank 1
3793 12:32:47.478371 SW Impedance : PASS
3794 12:32:47.481534 DUTY Scan : NO K
3795 12:32:47.481657 ZQ Calibration : PASS
3796 12:32:47.484789 Jitter Meter : NO K
3797 12:32:47.484882 CBT Training : PASS
3798 12:32:47.488058 Write leveling : PASS
3799 12:32:47.491370 RX DQS gating : PASS
3800 12:32:47.491508 RX DQ/DQS(RDDQC) : PASS
3801 12:32:47.494559 TX DQ/DQS : PASS
3802 12:32:47.497881 RX DATLAT : PASS
3803 12:32:47.498040 RX DQ/DQS(Engine): PASS
3804 12:32:47.501391 TX OE : NO K
3805 12:32:47.501527 All Pass.
3806 12:32:47.501627
3807 12:32:47.504738 DramC Write-DBI off
3808 12:32:47.507943 PER_BANK_REFRESH: Hybrid Mode
3809 12:32:47.508076 TX_TRACKING: ON
3810 12:32:47.518113 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3811 12:32:47.522007 [FAST_K] Save calibration result to emmc
3812 12:32:47.524637 dramc_set_vcore_voltage set vcore to 650000
3813 12:32:47.527839 Read voltage for 600, 5
3814 12:32:47.527962 Vio18 = 0
3815 12:32:47.528068 Vcore = 650000
3816 12:32:47.531298 Vdram = 0
3817 12:32:47.531445 Vddq = 0
3818 12:32:47.531588 Vmddr = 0
3819 12:32:47.538106 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3820 12:32:47.541364 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3821 12:32:47.544593 MEM_TYPE=3, freq_sel=19
3822 12:32:47.547949 sv_algorithm_assistance_LP4_1600
3823 12:32:47.551543 ============ PULL DRAM RESETB DOWN ============
3824 12:32:47.554755 ========== PULL DRAM RESETB DOWN end =========
3825 12:32:47.561435 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3826 12:32:47.564757 ===================================
3827 12:32:47.567581 LPDDR4 DRAM CONFIGURATION
3828 12:32:47.570896 ===================================
3829 12:32:47.571048 EX_ROW_EN[0] = 0x0
3830 12:32:47.574250 EX_ROW_EN[1] = 0x0
3831 12:32:47.574380 LP4Y_EN = 0x0
3832 12:32:47.577404 WORK_FSP = 0x0
3833 12:32:47.577518 WL = 0x2
3834 12:32:47.581429 RL = 0x2
3835 12:32:47.581561 BL = 0x2
3836 12:32:47.584694 RPST = 0x0
3837 12:32:47.584791 RD_PRE = 0x0
3838 12:32:47.587919 WR_PRE = 0x1
3839 12:32:47.588018 WR_PST = 0x0
3840 12:32:47.591001 DBI_WR = 0x0
3841 12:32:47.591123 DBI_RD = 0x0
3842 12:32:47.594161 OTF = 0x1
3843 12:32:47.597428 ===================================
3844 12:32:47.600826 ===================================
3845 12:32:47.600931 ANA top config
3846 12:32:47.604167 ===================================
3847 12:32:47.607559 DLL_ASYNC_EN = 0
3848 12:32:47.610666 ALL_SLAVE_EN = 1
3849 12:32:47.614113 NEW_RANK_MODE = 1
3850 12:32:47.614217 DLL_IDLE_MODE = 1
3851 12:32:47.617563 LP45_APHY_COMB_EN = 1
3852 12:32:47.622771 TX_ODT_DIS = 1
3853 12:32:47.624009 NEW_8X_MODE = 1
3854 12:32:47.627453 ===================================
3855 12:32:47.630720 ===================================
3856 12:32:47.634077 data_rate = 1200
3857 12:32:47.637441 CKR = 1
3858 12:32:47.637549 DQ_P2S_RATIO = 8
3859 12:32:47.640806 ===================================
3860 12:32:47.644220 CA_P2S_RATIO = 8
3861 12:32:47.646905 DQ_CA_OPEN = 0
3862 12:32:47.650234 DQ_SEMI_OPEN = 0
3863 12:32:47.654010 CA_SEMI_OPEN = 0
3864 12:32:47.657450 CA_FULL_RATE = 0
3865 12:32:47.657588 DQ_CKDIV4_EN = 1
3866 12:32:47.660686 CA_CKDIV4_EN = 1
3867 12:32:47.663900 CA_PREDIV_EN = 0
3868 12:32:47.667264 PH8_DLY = 0
3869 12:32:47.670555 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3870 12:32:47.673953 DQ_AAMCK_DIV = 4
3871 12:32:47.674056 CA_AAMCK_DIV = 4
3872 12:32:47.677150 CA_ADMCK_DIV = 4
3873 12:32:47.680504 DQ_TRACK_CA_EN = 0
3874 12:32:47.683765 CA_PICK = 600
3875 12:32:47.686879 CA_MCKIO = 600
3876 12:32:47.690081 MCKIO_SEMI = 0
3877 12:32:47.693273 PLL_FREQ = 2288
3878 12:32:47.693379 DQ_UI_PI_RATIO = 32
3879 12:32:47.696521 CA_UI_PI_RATIO = 0
3880 12:32:47.700376 ===================================
3881 12:32:47.703466 ===================================
3882 12:32:47.706748 memory_type:LPDDR4
3883 12:32:47.710083 GP_NUM : 10
3884 12:32:47.710212 SRAM_EN : 1
3885 12:32:47.713238 MD32_EN : 0
3886 12:32:47.716412 ===================================
3887 12:32:47.719858 [ANA_INIT] >>>>>>>>>>>>>>
3888 12:32:47.719955 <<<<<< [CONFIGURE PHASE]: ANA_TX
3889 12:32:47.726510 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3890 12:32:47.729868 ===================================
3891 12:32:47.729993 data_rate = 1200,PCW = 0X5800
3892 12:32:47.733169 ===================================
3893 12:32:47.736496 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3894 12:32:47.743170 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3895 12:32:47.749504 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3896 12:32:47.752789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3897 12:32:47.756146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3898 12:32:47.759333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3899 12:32:47.763129 [ANA_INIT] flow start
3900 12:32:47.763272 [ANA_INIT] PLL >>>>>>>>
3901 12:32:47.766336 [ANA_INIT] PLL <<<<<<<<
3902 12:32:47.769637 [ANA_INIT] MIDPI >>>>>>>>
3903 12:32:47.773117 [ANA_INIT] MIDPI <<<<<<<<
3904 12:32:47.773221 [ANA_INIT] DLL >>>>>>>>
3905 12:32:47.776364 [ANA_INIT] flow end
3906 12:32:47.779689 ============ LP4 DIFF to SE enter ============
3907 12:32:47.783085 ============ LP4 DIFF to SE exit ============
3908 12:32:47.786430 [ANA_INIT] <<<<<<<<<<<<<
3909 12:32:47.789504 [Flow] Enable top DCM control >>>>>
3910 12:32:47.792836 [Flow] Enable top DCM control <<<<<
3911 12:32:47.796082 Enable DLL master slave shuffle
3912 12:32:47.803090 ==============================================================
3913 12:32:47.803251 Gating Mode config
3914 12:32:47.809564 ==============================================================
3915 12:32:47.809727 Config description:
3916 12:32:47.819038 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3917 12:32:47.825842 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3918 12:32:47.832709 SELPH_MODE 0: By rank 1: By Phase
3919 12:32:47.836084 ==============================================================
3920 12:32:47.839505 GAT_TRACK_EN = 1
3921 12:32:47.842763 RX_GATING_MODE = 2
3922 12:32:47.845664 RX_GATING_TRACK_MODE = 2
3923 12:32:47.849545 SELPH_MODE = 1
3924 12:32:47.852382 PICG_EARLY_EN = 1
3925 12:32:47.855734 VALID_LAT_VALUE = 1
3926 12:32:47.859619 ==============================================================
3927 12:32:47.862322 Enter into Gating configuration >>>>
3928 12:32:47.866170 Exit from Gating configuration <<<<
3929 12:32:47.868943 Enter into DVFS_PRE_config >>>>>
3930 12:32:47.882728 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3931 12:32:47.885540 Exit from DVFS_PRE_config <<<<<
3932 12:32:47.888860 Enter into PICG configuration >>>>
3933 12:32:47.892127 Exit from PICG configuration <<<<
3934 12:32:47.892237 [RX_INPUT] configuration >>>>>
3935 12:32:47.895493 [RX_INPUT] configuration <<<<<
3936 12:32:47.902009 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3937 12:32:47.905847 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3938 12:32:47.912134 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3939 12:32:47.918976 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3940 12:32:47.925585 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3941 12:32:47.932310 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3942 12:32:47.935684 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3943 12:32:47.938941 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3944 12:32:47.945045 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3945 12:32:47.948360 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3946 12:32:47.951671 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3947 12:32:47.954929 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3948 12:32:47.958379 ===================================
3949 12:32:47.961642 LPDDR4 DRAM CONFIGURATION
3950 12:32:47.965140 ===================================
3951 12:32:47.968473 EX_ROW_EN[0] = 0x0
3952 12:32:47.968559 EX_ROW_EN[1] = 0x0
3953 12:32:47.971658 LP4Y_EN = 0x0
3954 12:32:47.971743 WORK_FSP = 0x0
3955 12:32:47.974873 WL = 0x2
3956 12:32:47.974958 RL = 0x2
3957 12:32:47.978138 BL = 0x2
3958 12:32:47.978223 RPST = 0x0
3959 12:32:47.981451 RD_PRE = 0x0
3960 12:32:47.981537 WR_PRE = 0x1
3961 12:32:47.985114 WR_PST = 0x0
3962 12:32:47.988637 DBI_WR = 0x0
3963 12:32:47.988722 DBI_RD = 0x0
3964 12:32:47.991831 OTF = 0x1
3965 12:32:47.995234 ===================================
3966 12:32:47.998379 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3967 12:32:48.001572 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3968 12:32:48.004766 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3969 12:32:48.008004 ===================================
3970 12:32:48.011753 LPDDR4 DRAM CONFIGURATION
3971 12:32:48.014417 ===================================
3972 12:32:48.018212 EX_ROW_EN[0] = 0x10
3973 12:32:48.018332 EX_ROW_EN[1] = 0x0
3974 12:32:48.021421 LP4Y_EN = 0x0
3975 12:32:48.021533 WORK_FSP = 0x0
3976 12:32:48.024722 WL = 0x2
3977 12:32:48.024807 RL = 0x2
3978 12:32:48.027913 BL = 0x2
3979 12:32:48.027999 RPST = 0x0
3980 12:32:48.031202 RD_PRE = 0x0
3981 12:32:48.031313 WR_PRE = 0x1
3982 12:32:48.034579 WR_PST = 0x0
3983 12:32:48.034664 DBI_WR = 0x0
3984 12:32:48.037886 DBI_RD = 0x0
3985 12:32:48.041091 OTF = 0x1
3986 12:32:48.044498 ===================================
3987 12:32:48.047574 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3988 12:32:48.053031 nWR fixed to 30
3989 12:32:48.056157 [ModeRegInit_LP4] CH0 RK0
3990 12:32:48.056276 [ModeRegInit_LP4] CH0 RK1
3991 12:32:48.059595 [ModeRegInit_LP4] CH1 RK0
3992 12:32:48.062942 [ModeRegInit_LP4] CH1 RK1
3993 12:32:48.063055 match AC timing 17
3994 12:32:48.069506 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3995 12:32:48.072769 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3996 12:32:48.076094 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3997 12:32:48.082560 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3998 12:32:48.085816 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3999 12:32:48.085922 ==
4000 12:32:48.089248 Dram Type= 6, Freq= 0, CH_0, rank 0
4001 12:32:48.092530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4002 12:32:48.092633 ==
4003 12:32:48.099098 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4004 12:32:48.105881 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4005 12:32:48.109010 [CA 0] Center 36 (6~66) winsize 61
4006 12:32:48.112923 [CA 1] Center 36 (6~66) winsize 61
4007 12:32:48.115933 [CA 2] Center 34 (4~65) winsize 62
4008 12:32:48.119072 [CA 3] Center 34 (4~65) winsize 62
4009 12:32:48.122134 [CA 4] Center 33 (3~64) winsize 62
4010 12:32:48.125989 [CA 5] Center 33 (3~64) winsize 62
4011 12:32:48.126096
4012 12:32:48.129288 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4013 12:32:48.129501
4014 12:32:48.132579 [CATrainingPosCal] consider 1 rank data
4015 12:32:48.135952 u2DelayCellTimex100 = 270/100 ps
4016 12:32:48.139193 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4017 12:32:48.142617 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4018 12:32:48.145916 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4019 12:32:48.149416 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4020 12:32:48.152507 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4021 12:32:48.159112 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4022 12:32:48.159202
4023 12:32:48.162397 CA PerBit enable=1, Macro0, CA PI delay=33
4024 12:32:48.162482
4025 12:32:48.165621 [CBTSetCACLKResult] CA Dly = 33
4026 12:32:48.165707 CS Dly: 4 (0~35)
4027 12:32:48.165773 ==
4028 12:32:48.168892 Dram Type= 6, Freq= 0, CH_0, rank 1
4029 12:32:48.172288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4030 12:32:48.175673 ==
4031 12:32:48.178841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4032 12:32:48.185268 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4033 12:32:48.189264 [CA 0] Center 36 (6~66) winsize 61
4034 12:32:48.191911 [CA 1] Center 35 (5~66) winsize 62
4035 12:32:48.195229 [CA 2] Center 34 (4~65) winsize 62
4036 12:32:48.198541 [CA 3] Center 34 (4~65) winsize 62
4037 12:32:48.202432 [CA 4] Center 33 (3~64) winsize 62
4038 12:32:48.205523 [CA 5] Center 33 (3~64) winsize 62
4039 12:32:48.205606
4040 12:32:48.208849 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4041 12:32:48.208931
4042 12:32:48.212130 [CATrainingPosCal] consider 2 rank data
4043 12:32:48.215158 u2DelayCellTimex100 = 270/100 ps
4044 12:32:48.218432 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4045 12:32:48.222146 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4046 12:32:48.225228 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4047 12:32:48.232059 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4048 12:32:48.235249 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4049 12:32:48.238428 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4050 12:32:48.238511
4051 12:32:48.241929 CA PerBit enable=1, Macro0, CA PI delay=33
4052 12:32:48.242027
4053 12:32:48.245227 [CBTSetCACLKResult] CA Dly = 33
4054 12:32:48.245309 CS Dly: 4 (0~36)
4055 12:32:48.245375
4056 12:32:48.248346 ----->DramcWriteLeveling(PI) begin...
4057 12:32:48.248430 ==
4058 12:32:48.251710 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 12:32:48.258315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 12:32:48.258402 ==
4061 12:32:48.261606 Write leveling (Byte 0): 32 => 32
4062 12:32:48.265001 Write leveling (Byte 1): 28 => 28
4063 12:32:48.265085 DramcWriteLeveling(PI) end<-----
4064 12:32:48.268304
4065 12:32:48.268393 ==
4066 12:32:48.272088 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 12:32:48.275304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 12:32:48.275421 ==
4069 12:32:48.278610 [Gating] SW mode calibration
4070 12:32:48.284892 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4071 12:32:48.288403 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4072 12:32:48.295388 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4073 12:32:48.298125 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4074 12:32:48.301999 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4075 12:32:48.308578 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4076 12:32:48.311953 0 9 16 | B1->B0 | 3232 2a2a | 1 0 | (1 0) (1 1)
4077 12:32:48.315145 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4078 12:32:48.321481 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4079 12:32:48.324860 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4080 12:32:48.328643 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4081 12:32:48.334861 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4082 12:32:48.338142 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4083 12:32:48.341992 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4084 12:32:48.348724 0 10 16 | B1->B0 | 3131 3a3a | 1 0 | (0 0) (0 0)
4085 12:32:48.351979 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 12:32:48.355257 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4087 12:32:48.358514 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4088 12:32:48.365154 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4089 12:32:48.368465 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4090 12:32:48.371635 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 12:32:48.378314 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 12:32:48.381686 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4093 12:32:48.385275 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 12:32:48.391555 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 12:32:48.394897 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 12:32:48.398197 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 12:32:48.404989 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 12:32:48.408167 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 12:32:48.411454 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 12:32:48.417810 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 12:32:48.421246 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 12:32:48.424981 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 12:32:48.431227 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 12:32:48.435095 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 12:32:48.438661 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 12:32:48.444912 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 12:32:48.448227 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 12:32:48.451568 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4109 12:32:48.454756 Total UI for P1: 0, mck2ui 16
4110 12:32:48.458079 best dqsien dly found for B0: ( 0, 13, 14)
4111 12:32:48.464709 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4112 12:32:48.467985 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4113 12:32:48.471271 Total UI for P1: 0, mck2ui 16
4114 12:32:48.474659 best dqsien dly found for B1: ( 0, 13, 18)
4115 12:32:48.478040 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4116 12:32:48.481355 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4117 12:32:48.481458
4118 12:32:48.484543 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4119 12:32:48.488046 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4120 12:32:48.491256 [Gating] SW calibration Done
4121 12:32:48.491377 ==
4122 12:32:48.494316 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 12:32:48.497707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 12:32:48.497790 ==
4125 12:32:48.501589 RX Vref Scan: 0
4126 12:32:48.501672
4127 12:32:48.505056 RX Vref 0 -> 0, step: 1
4128 12:32:48.505139
4129 12:32:48.507654 RX Delay -230 -> 252, step: 16
4130 12:32:48.511615 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4131 12:32:48.514980 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4132 12:32:48.518188 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4133 12:32:48.521389 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4134 12:32:48.527751 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4135 12:32:48.531568 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4136 12:32:48.534825 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4137 12:32:48.538002 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4138 12:32:48.544847 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4139 12:32:48.547927 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4140 12:32:48.551261 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4141 12:32:48.554598 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4142 12:32:48.561054 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4143 12:32:48.564401 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4144 12:32:48.567764 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4145 12:32:48.571021 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4146 12:32:48.571104 ==
4147 12:32:48.574309 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 12:32:48.580970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 12:32:48.581054 ==
4150 12:32:48.581120 DQS Delay:
4151 12:32:48.584264 DQS0 = 0, DQS1 = 0
4152 12:32:48.584346 DQM Delay:
4153 12:32:48.584413 DQM0 = 40, DQM1 = 33
4154 12:32:48.587636 DQ Delay:
4155 12:32:48.590880 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4156 12:32:48.594199 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4157 12:32:48.597306 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4158 12:32:48.600634 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4159 12:32:48.600719
4160 12:32:48.600784
4161 12:32:48.600843 ==
4162 12:32:48.603997 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 12:32:48.607206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 12:32:48.607314 ==
4165 12:32:48.607433
4166 12:32:48.607496
4167 12:32:48.610677 TX Vref Scan disable
4168 12:32:48.610760 == TX Byte 0 ==
4169 12:32:48.617254 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4170 12:32:48.620578 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4171 12:32:48.620662 == TX Byte 1 ==
4172 12:32:48.627605 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4173 12:32:48.630801 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4174 12:32:48.630884 ==
4175 12:32:48.633978 Dram Type= 6, Freq= 0, CH_0, rank 0
4176 12:32:48.637176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 12:32:48.637261 ==
4178 12:32:48.637326
4179 12:32:48.637387
4180 12:32:48.640930 TX Vref Scan disable
4181 12:32:48.644223 == TX Byte 0 ==
4182 12:32:48.647831 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4183 12:32:48.650993 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4184 12:32:48.654196 == TX Byte 1 ==
4185 12:32:48.657597 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4186 12:32:48.660864 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4187 12:32:48.664067
4188 12:32:48.664149 [DATLAT]
4189 12:32:48.664215 Freq=600, CH0 RK0
4190 12:32:48.664277
4191 12:32:48.667384 DATLAT Default: 0x9
4192 12:32:48.667482 0, 0xFFFF, sum = 0
4193 12:32:48.670646 1, 0xFFFF, sum = 0
4194 12:32:48.670730 2, 0xFFFF, sum = 0
4195 12:32:48.673950 3, 0xFFFF, sum = 0
4196 12:32:48.674034 4, 0xFFFF, sum = 0
4197 12:32:48.677819 5, 0xFFFF, sum = 0
4198 12:32:48.677903 6, 0xFFFF, sum = 0
4199 12:32:48.680990 7, 0xFFFF, sum = 0
4200 12:32:48.681074 8, 0x0, sum = 1
4201 12:32:48.684440 9, 0x0, sum = 2
4202 12:32:48.684524 10, 0x0, sum = 3
4203 12:32:48.687828 11, 0x0, sum = 4
4204 12:32:48.687912 best_step = 9
4205 12:32:48.687977
4206 12:32:48.688038 ==
4207 12:32:48.691084 Dram Type= 6, Freq= 0, CH_0, rank 0
4208 12:32:48.697627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 12:32:48.697711 ==
4210 12:32:48.697777 RX Vref Scan: 1
4211 12:32:48.697838
4212 12:32:48.700823 RX Vref 0 -> 0, step: 1
4213 12:32:48.700906
4214 12:32:48.703994 RX Delay -195 -> 252, step: 8
4215 12:32:48.704077
4216 12:32:48.707870 Set Vref, RX VrefLevel [Byte0]: 53
4217 12:32:48.710398 [Byte1]: 51
4218 12:32:48.710481
4219 12:32:48.713780 Final RX Vref Byte 0 = 53 to rank0
4220 12:32:48.717529 Final RX Vref Byte 1 = 51 to rank0
4221 12:32:48.720835 Final RX Vref Byte 0 = 53 to rank1
4222 12:32:48.723993 Final RX Vref Byte 1 = 51 to rank1==
4223 12:32:48.727312 Dram Type= 6, Freq= 0, CH_0, rank 0
4224 12:32:48.730735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 12:32:48.730862 ==
4226 12:32:48.733816 DQS Delay:
4227 12:32:48.733914 DQS0 = 0, DQS1 = 0
4228 12:32:48.734029 DQM Delay:
4229 12:32:48.737613 DQM0 = 42, DQM1 = 33
4230 12:32:48.737757 DQ Delay:
4231 12:32:48.740900 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4232 12:32:48.743932 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4233 12:32:48.747174 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4234 12:32:48.750407 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4235 12:32:48.750484
4236 12:32:48.750548
4237 12:32:48.760599 [DQSOSCAuto] RK0, (LSB)MR18= 0x411f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4238 12:32:48.763920 CH0 RK0: MR19=808, MR18=411F
4239 12:32:48.767237 CH0_RK0: MR19=0x808, MR18=0x411F, DQSOSC=397, MR23=63, INC=166, DEC=110
4240 12:32:48.767315
4241 12:32:48.770678 ----->DramcWriteLeveling(PI) begin...
4242 12:32:48.773902 ==
4243 12:32:48.777110 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 12:32:48.780324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 12:32:48.780409 ==
4246 12:32:48.783697 Write leveling (Byte 0): 33 => 33
4247 12:32:48.786859 Write leveling (Byte 1): 30 => 30
4248 12:32:48.790101 DramcWriteLeveling(PI) end<-----
4249 12:32:48.790185
4250 12:32:48.790260 ==
4251 12:32:48.793914 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 12:32:48.797333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 12:32:48.797418 ==
4254 12:32:48.800427 [Gating] SW mode calibration
4255 12:32:48.806776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4256 12:32:48.813335 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4257 12:32:48.816707 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4258 12:32:48.820648 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4259 12:32:48.826629 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4260 12:32:48.829964 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4261 12:32:48.834034 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
4262 12:32:48.837238 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4263 12:32:48.843726 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4264 12:32:48.846833 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4265 12:32:48.849968 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4266 12:32:48.856993 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4267 12:32:48.860154 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 12:32:48.863666 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4269 12:32:48.870084 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4270 12:32:48.873285 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 12:32:48.876563 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4272 12:32:48.883094 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 12:32:48.886425 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 12:32:48.889736 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 12:32:48.896353 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 12:32:48.899788 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4277 12:32:48.902908 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4278 12:32:48.910041 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4279 12:32:48.913293 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 12:32:48.916714 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 12:32:48.923093 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 12:32:48.926526 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 12:32:48.929610 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 12:32:48.936729 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 12:32:48.940049 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 12:32:48.943293 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 12:32:48.949863 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 12:32:48.953104 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 12:32:48.956131 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 12:32:48.962740 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 12:32:48.966454 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 12:32:48.969727 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4293 12:32:48.976334 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4294 12:32:48.976444 Total UI for P1: 0, mck2ui 16
4295 12:32:48.979650 best dqsien dly found for B0: ( 0, 13, 12)
4296 12:32:48.986218 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4297 12:32:48.989413 Total UI for P1: 0, mck2ui 16
4298 12:32:48.992701 best dqsien dly found for B1: ( 0, 13, 14)
4299 12:32:48.996129 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4300 12:32:48.999266 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4301 12:32:48.999432
4302 12:32:49.002801 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4303 12:32:49.006110 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4304 12:32:49.009465 [Gating] SW calibration Done
4305 12:32:49.009548 ==
4306 12:32:49.012623 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 12:32:49.016454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 12:32:49.016540 ==
4309 12:32:49.019070 RX Vref Scan: 0
4310 12:32:49.019179
4311 12:32:49.022496 RX Vref 0 -> 0, step: 1
4312 12:32:49.022579
4313 12:32:49.022644 RX Delay -230 -> 252, step: 16
4314 12:32:49.029648 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4315 12:32:49.032958 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4316 12:32:49.036278 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4317 12:32:49.039544 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4318 12:32:49.045963 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4319 12:32:49.049167 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4320 12:32:49.052988 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4321 12:32:49.056244 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4322 12:32:49.059514 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4323 12:32:49.065843 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4324 12:32:49.069591 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4325 12:32:49.073078 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4326 12:32:49.076059 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4327 12:32:49.082539 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4328 12:32:49.085922 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4329 12:32:49.089191 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4330 12:32:49.089298 ==
4331 12:32:49.092652 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 12:32:49.095961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 12:32:49.099191 ==
4334 12:32:49.099297 DQS Delay:
4335 12:32:49.099438 DQS0 = 0, DQS1 = 0
4336 12:32:49.102513 DQM Delay:
4337 12:32:49.102588 DQM0 = 41, DQM1 = 31
4338 12:32:49.105846 DQ Delay:
4339 12:32:49.109214 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4340 12:32:49.109298 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4341 12:32:49.112593 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4342 12:32:49.116173 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4343 12:32:49.119262
4344 12:32:49.119345
4345 12:32:49.119455 ==
4346 12:32:49.122452 Dram Type= 6, Freq= 0, CH_0, rank 1
4347 12:32:49.125739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 12:32:49.125851 ==
4349 12:32:49.125945
4350 12:32:49.126034
4351 12:32:49.128972 TX Vref Scan disable
4352 12:32:49.129058 == TX Byte 0 ==
4353 12:32:49.135813 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4354 12:32:49.139048 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4355 12:32:49.139215 == TX Byte 1 ==
4356 12:32:49.145962 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4357 12:32:49.149357 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4358 12:32:49.149437 ==
4359 12:32:49.152456 Dram Type= 6, Freq= 0, CH_0, rank 1
4360 12:32:49.155729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 12:32:49.155819 ==
4362 12:32:49.155885
4363 12:32:49.155945
4364 12:32:49.158937 TX Vref Scan disable
4365 12:32:49.162865 == TX Byte 0 ==
4366 12:32:49.165910 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4367 12:32:49.169159 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4368 12:32:49.172390 == TX Byte 1 ==
4369 12:32:49.175666 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4370 12:32:49.178948 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4371 12:32:49.179055
4372 12:32:49.182772 [DATLAT]
4373 12:32:49.182879 Freq=600, CH0 RK1
4374 12:32:49.182971
4375 12:32:49.186080 DATLAT Default: 0x9
4376 12:32:49.186161 0, 0xFFFF, sum = 0
4377 12:32:49.189220 1, 0xFFFF, sum = 0
4378 12:32:49.189303 2, 0xFFFF, sum = 0
4379 12:32:49.192528 3, 0xFFFF, sum = 0
4380 12:32:49.192611 4, 0xFFFF, sum = 0
4381 12:32:49.195916 5, 0xFFFF, sum = 0
4382 12:32:49.195999 6, 0xFFFF, sum = 0
4383 12:32:49.199232 7, 0xFFFF, sum = 0
4384 12:32:49.199341 8, 0x0, sum = 1
4385 12:32:49.202566 9, 0x0, sum = 2
4386 12:32:49.202649 10, 0x0, sum = 3
4387 12:32:49.205908 11, 0x0, sum = 4
4388 12:32:49.205990 best_step = 9
4389 12:32:49.206054
4390 12:32:49.206113 ==
4391 12:32:49.209157 Dram Type= 6, Freq= 0, CH_0, rank 1
4392 12:32:49.215854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 12:32:49.215936 ==
4394 12:32:49.215999 RX Vref Scan: 0
4395 12:32:49.216058
4396 12:32:49.219201 RX Vref 0 -> 0, step: 1
4397 12:32:49.219307
4398 12:32:49.222377 RX Delay -195 -> 252, step: 8
4399 12:32:49.225573 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4400 12:32:49.231992 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4401 12:32:49.235343 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4402 12:32:49.238658 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4403 12:32:49.242527 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4404 12:32:49.245928 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4405 12:32:49.252197 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4406 12:32:49.255491 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4407 12:32:49.258717 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4408 12:32:49.261975 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4409 12:32:49.265873 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4410 12:32:49.272106 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4411 12:32:49.275935 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4412 12:32:49.279057 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4413 12:32:49.285393 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4414 12:32:49.288503 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4415 12:32:49.288605 ==
4416 12:32:49.291839 Dram Type= 6, Freq= 0, CH_0, rank 1
4417 12:32:49.295120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 12:32:49.295263 ==
4419 12:32:49.295370 DQS Delay:
4420 12:32:49.298576 DQS0 = 0, DQS1 = 0
4421 12:32:49.298668 DQM Delay:
4422 12:32:49.301918 DQM0 = 39, DQM1 = 33
4423 12:32:49.302008 DQ Delay:
4424 12:32:49.305111 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4425 12:32:49.308474 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =44
4426 12:32:49.311700 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4427 12:32:49.315028 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4428 12:32:49.315115
4429 12:32:49.315181
4430 12:32:49.324952 [DQSOSCAuto] RK1, (LSB)MR18= 0x4e30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4431 12:32:49.325065 CH0 RK1: MR19=808, MR18=4E30
4432 12:32:49.331388 CH0_RK1: MR19=0x808, MR18=0x4E30, DQSOSC=395, MR23=63, INC=168, DEC=112
4433 12:32:49.334845 [RxdqsGatingPostProcess] freq 600
4434 12:32:49.341345 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4435 12:32:49.344717 Pre-setting of DQS Precalculation
4436 12:32:49.348722 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4437 12:32:49.348841 ==
4438 12:32:49.352058 Dram Type= 6, Freq= 0, CH_1, rank 0
4439 12:32:49.355327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 12:32:49.358514 ==
4441 12:32:49.361865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4442 12:32:49.368109 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4443 12:32:49.371934 [CA 0] Center 35 (4~66) winsize 63
4444 12:32:49.375175 [CA 1] Center 35 (5~66) winsize 62
4445 12:32:49.378239 [CA 2] Center 33 (3~64) winsize 62
4446 12:32:49.381472 [CA 3] Center 33 (3~64) winsize 62
4447 12:32:49.384689 [CA 4] Center 34 (3~65) winsize 63
4448 12:32:49.388456 [CA 5] Center 33 (2~64) winsize 63
4449 12:32:49.388539
4450 12:32:49.391653 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4451 12:32:49.391738
4452 12:32:49.395077 [CATrainingPosCal] consider 1 rank data
4453 12:32:49.398397 u2DelayCellTimex100 = 270/100 ps
4454 12:32:49.401692 CA0 delay=35 (4~66),Diff = 2 PI (19 cell)
4455 12:32:49.404974 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4456 12:32:49.408257 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4457 12:32:49.411568 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4458 12:32:49.418822 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4459 12:32:49.421972 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4460 12:32:49.422055
4461 12:32:49.425381 CA PerBit enable=1, Macro0, CA PI delay=33
4462 12:32:49.425465
4463 12:32:49.428655 [CBTSetCACLKResult] CA Dly = 33
4464 12:32:49.428739 CS Dly: 5 (0~36)
4465 12:32:49.428804 ==
4466 12:32:49.431877 Dram Type= 6, Freq= 0, CH_1, rank 1
4467 12:32:49.438231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 12:32:49.438338 ==
4469 12:32:49.441512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4470 12:32:49.448148 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4471 12:32:49.451490 [CA 0] Center 35 (5~66) winsize 62
4472 12:32:49.454709 [CA 1] Center 35 (5~66) winsize 62
4473 12:32:49.457907 [CA 2] Center 34 (3~65) winsize 63
4474 12:32:49.461874 [CA 3] Center 33 (3~64) winsize 62
4475 12:32:49.464564 [CA 4] Center 34 (3~65) winsize 63
4476 12:32:49.468585 [CA 5] Center 33 (2~64) winsize 63
4477 12:32:49.468670
4478 12:32:49.471668 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4479 12:32:49.471758
4480 12:32:49.474801 [CATrainingPosCal] consider 2 rank data
4481 12:32:49.478259 u2DelayCellTimex100 = 270/100 ps
4482 12:32:49.481493 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4483 12:32:49.484657 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4484 12:32:49.491662 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4485 12:32:49.494806 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4486 12:32:49.498064 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4487 12:32:49.501314 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4488 12:32:49.501397
4489 12:32:49.504672 CA PerBit enable=1, Macro0, CA PI delay=33
4490 12:32:49.504756
4491 12:32:49.507884 [CBTSetCACLKResult] CA Dly = 33
4492 12:32:49.507967 CS Dly: 5 (0~36)
4493 12:32:49.508033
4494 12:32:49.511185 ----->DramcWriteLeveling(PI) begin...
4495 12:32:49.514491 ==
4496 12:32:49.514577 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 12:32:49.521186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 12:32:49.521270 ==
4499 12:32:49.524417 Write leveling (Byte 0): 29 => 29
4500 12:32:49.527706 Write leveling (Byte 1): 29 => 29
4501 12:32:49.530997 DramcWriteLeveling(PI) end<-----
4502 12:32:49.531080
4503 12:32:49.531145 ==
4504 12:32:49.534285 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 12:32:49.537750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 12:32:49.537834 ==
4507 12:32:49.540894 [Gating] SW mode calibration
4508 12:32:49.547863 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4509 12:32:49.551293 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4510 12:32:49.557943 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4511 12:32:49.561269 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4512 12:32:49.564638 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4513 12:32:49.571140 0 9 12 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 0)
4514 12:32:49.574297 0 9 16 | B1->B0 | 2b2b 2929 | 0 0 | (0 0) (0 0)
4515 12:32:49.577445 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4516 12:32:49.584381 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4517 12:32:49.587511 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4518 12:32:49.590670 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4519 12:32:49.597571 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4520 12:32:49.600830 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 12:32:49.604151 0 10 12 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (0 0)
4522 12:32:49.610632 0 10 16 | B1->B0 | 3d3d 4343 | 0 0 | (0 0) (0 0)
4523 12:32:49.613944 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 12:32:49.617271 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4525 12:32:49.623917 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 12:32:49.627003 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 12:32:49.630461 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 12:32:49.637101 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 12:32:49.640311 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 12:32:49.643387 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4531 12:32:49.650412 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 12:32:49.653791 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 12:32:49.657007 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 12:32:49.663544 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 12:32:49.666931 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 12:32:49.670035 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 12:32:49.676451 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 12:32:49.680250 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 12:32:49.683522 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 12:32:49.689841 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 12:32:49.693025 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 12:32:49.696855 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 12:32:49.703189 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 12:32:49.706602 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 12:32:49.709991 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4546 12:32:49.716728 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4547 12:32:49.716814 Total UI for P1: 0, mck2ui 16
4548 12:32:49.723286 best dqsien dly found for B0: ( 0, 13, 14)
4549 12:32:49.723410 Total UI for P1: 0, mck2ui 16
4550 12:32:49.726498 best dqsien dly found for B1: ( 0, 13, 12)
4551 12:32:49.733077 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4552 12:32:49.736356 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4553 12:32:49.736440
4554 12:32:49.739593 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4555 12:32:49.742901 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4556 12:32:49.746139 [Gating] SW calibration Done
4557 12:32:49.746247 ==
4558 12:32:49.749490 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 12:32:49.753160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 12:32:49.753244 ==
4561 12:32:49.756316 RX Vref Scan: 0
4562 12:32:49.756416
4563 12:32:49.756491 RX Vref 0 -> 0, step: 1
4564 12:32:49.756595
4565 12:32:49.759622 RX Delay -230 -> 252, step: 16
4566 12:32:49.766266 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4567 12:32:49.769514 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4568 12:32:49.772900 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4569 12:32:49.776268 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4570 12:32:49.779608 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4571 12:32:49.785935 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4572 12:32:49.789727 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4573 12:32:49.793164 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4574 12:32:49.796389 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4575 12:32:49.802610 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4576 12:32:49.805911 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4577 12:32:49.809079 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4578 12:32:49.812404 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4579 12:32:49.819031 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4580 12:32:49.822391 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4581 12:32:49.825644 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4582 12:32:49.825727 ==
4583 12:32:49.828905 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 12:32:49.832905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 12:32:49.832989 ==
4586 12:32:49.835543 DQS Delay:
4587 12:32:49.835625 DQS0 = 0, DQS1 = 0
4588 12:32:49.838833 DQM Delay:
4589 12:32:49.838915 DQM0 = 42, DQM1 = 34
4590 12:32:49.838981 DQ Delay:
4591 12:32:49.842192 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =41
4592 12:32:49.845548 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =33
4593 12:32:49.848762 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4594 12:32:49.852071 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4595 12:32:49.852154
4596 12:32:49.852220
4597 12:32:49.855905 ==
4598 12:32:49.858862 Dram Type= 6, Freq= 0, CH_1, rank 0
4599 12:32:49.862125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 12:32:49.862209 ==
4601 12:32:49.862275
4602 12:32:49.862337
4603 12:32:49.865397 TX Vref Scan disable
4604 12:32:49.865480 == TX Byte 0 ==
4605 12:32:49.869257 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4606 12:32:49.875213 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4607 12:32:49.875296 == TX Byte 1 ==
4608 12:32:49.881967 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4609 12:32:49.885779 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4610 12:32:49.885862 ==
4611 12:32:49.888936 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 12:32:49.891909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 12:32:49.891994 ==
4614 12:32:49.892060
4615 12:32:49.892121
4616 12:32:49.895312 TX Vref Scan disable
4617 12:32:49.898667 == TX Byte 0 ==
4618 12:32:49.901905 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4619 12:32:49.905133 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4620 12:32:49.908877 == TX Byte 1 ==
4621 12:32:49.912009 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4622 12:32:49.915817 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4623 12:32:49.915900
4624 12:32:49.919008 [DATLAT]
4625 12:32:49.919121 Freq=600, CH1 RK0
4626 12:32:49.919216
4627 12:32:49.922366 DATLAT Default: 0x9
4628 12:32:49.922475 0, 0xFFFF, sum = 0
4629 12:32:49.925625 1, 0xFFFF, sum = 0
4630 12:32:49.925710 2, 0xFFFF, sum = 0
4631 12:32:49.928898 3, 0xFFFF, sum = 0
4632 12:32:49.928983 4, 0xFFFF, sum = 0
4633 12:32:49.932158 5, 0xFFFF, sum = 0
4634 12:32:49.932244 6, 0xFFFF, sum = 0
4635 12:32:49.935474 7, 0xFFFF, sum = 0
4636 12:32:49.935585 8, 0x0, sum = 1
4637 12:32:49.938791 9, 0x0, sum = 2
4638 12:32:49.938876 10, 0x0, sum = 3
4639 12:32:49.942045 11, 0x0, sum = 4
4640 12:32:49.942158 best_step = 9
4641 12:32:49.942251
4642 12:32:49.942340 ==
4643 12:32:49.945323 Dram Type= 6, Freq= 0, CH_1, rank 0
4644 12:32:49.948601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 12:32:49.951744 ==
4646 12:32:49.951828 RX Vref Scan: 1
4647 12:32:49.951894
4648 12:32:49.954974 RX Vref 0 -> 0, step: 1
4649 12:32:49.955058
4650 12:32:49.958372 RX Delay -195 -> 252, step: 8
4651 12:32:49.958456
4652 12:32:49.961551 Set Vref, RX VrefLevel [Byte0]: 53
4653 12:32:49.965374 [Byte1]: 51
4654 12:32:49.965458
4655 12:32:49.968637 Final RX Vref Byte 0 = 53 to rank0
4656 12:32:49.971860 Final RX Vref Byte 1 = 51 to rank0
4657 12:32:49.975020 Final RX Vref Byte 0 = 53 to rank1
4658 12:32:49.978408 Final RX Vref Byte 1 = 51 to rank1==
4659 12:32:49.981734 Dram Type= 6, Freq= 0, CH_1, rank 0
4660 12:32:49.984987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 12:32:49.985088 ==
4662 12:32:49.988134 DQS Delay:
4663 12:32:49.988244 DQS0 = 0, DQS1 = 0
4664 12:32:49.988349 DQM Delay:
4665 12:32:49.991307 DQM0 = 40, DQM1 = 31
4666 12:32:49.991448 DQ Delay:
4667 12:32:49.994614 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4668 12:32:49.997826 DQ4 =40, DQ5 =52, DQ6 =52, DQ7 =36
4669 12:32:50.001774 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4670 12:32:50.004446 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4671 12:32:50.004560
4672 12:32:50.004664
4673 12:32:50.014705 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e04, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
4674 12:32:50.014817 CH1 RK0: MR19=808, MR18=3E04
4675 12:32:50.021561 CH1_RK0: MR19=0x808, MR18=0x3E04, DQSOSC=398, MR23=63, INC=165, DEC=110
4676 12:32:50.021676
4677 12:32:50.024926 ----->DramcWriteLeveling(PI) begin...
4678 12:32:50.025034 ==
4679 12:32:50.028363 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 12:32:50.034585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 12:32:50.034666 ==
4682 12:32:50.037926 Write leveling (Byte 0): 30 => 30
4683 12:32:50.041303 Write leveling (Byte 1): 33 => 33
4684 12:32:50.041412 DramcWriteLeveling(PI) end<-----
4685 12:32:50.044559
4686 12:32:50.044667 ==
4687 12:32:50.047897 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 12:32:50.051247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 12:32:50.051382 ==
4690 12:32:50.054636 [Gating] SW mode calibration
4691 12:32:50.061158 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4692 12:32:50.064924 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4693 12:32:50.071129 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4694 12:32:50.074949 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4695 12:32:50.078427 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4696 12:32:50.084979 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 1) (1 0)
4697 12:32:50.087698 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4698 12:32:50.091060 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4699 12:32:50.097897 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4700 12:32:50.100981 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4701 12:32:50.104180 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4702 12:32:50.111296 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4703 12:32:50.114583 0 10 8 | B1->B0 | 2423 2828 | 1 0 | (0 0) (0 0)
4704 12:32:50.117649 0 10 12 | B1->B0 | 2f2f 3c3c | 1 0 | (0 0) (0 0)
4705 12:32:50.124931 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4706 12:32:50.127748 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4707 12:32:50.131102 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 12:32:50.137653 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 12:32:50.140794 0 11 0 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
4710 12:32:50.144181 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 12:32:50.151022 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4712 12:32:50.154149 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4713 12:32:50.157316 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 12:32:50.163984 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 12:32:50.167381 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 12:32:50.171152 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 12:32:50.177725 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 12:32:50.181021 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 12:32:50.184382 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 12:32:50.187648 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 12:32:50.194127 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 12:32:50.197471 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 12:32:50.200640 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 12:32:50.207611 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 12:32:50.210840 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 12:32:50.214188 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 12:32:50.220603 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 12:32:50.223830 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4729 12:32:50.227689 Total UI for P1: 0, mck2ui 16
4730 12:32:50.230695 best dqsien dly found for B0: ( 0, 13, 10)
4731 12:32:50.233983 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4732 12:32:50.237248 Total UI for P1: 0, mck2ui 16
4733 12:32:50.240737 best dqsien dly found for B1: ( 0, 13, 14)
4734 12:32:50.244032 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4735 12:32:50.247235 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4736 12:32:50.247367
4737 12:32:50.253950 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4738 12:32:50.257265 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4739 12:32:50.260392 [Gating] SW calibration Done
4740 12:32:50.260476 ==
4741 12:32:50.263705 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 12:32:50.266986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 12:32:50.267070 ==
4744 12:32:50.267137 RX Vref Scan: 0
4745 12:32:50.267209
4746 12:32:50.270393 RX Vref 0 -> 0, step: 1
4747 12:32:50.270484
4748 12:32:50.273617 RX Delay -230 -> 252, step: 16
4749 12:32:50.277505 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4750 12:32:50.280293 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4751 12:32:50.287334 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4752 12:32:50.290709 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4753 12:32:50.293963 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4754 12:32:50.297289 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4755 12:32:50.303810 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4756 12:32:50.307019 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4757 12:32:50.310761 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4758 12:32:50.313839 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4759 12:32:50.317522 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4760 12:32:50.324171 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4761 12:32:50.327224 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4762 12:32:50.330496 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4763 12:32:50.333587 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4764 12:32:50.340251 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4765 12:32:50.340358 ==
4766 12:32:50.344119 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 12:32:50.346826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 12:32:50.346939 ==
4769 12:32:50.347037 DQS Delay:
4770 12:32:50.350620 DQS0 = 0, DQS1 = 0
4771 12:32:50.350724 DQM Delay:
4772 12:32:50.353352 DQM0 = 37, DQM1 = 34
4773 12:32:50.353461 DQ Delay:
4774 12:32:50.357314 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4775 12:32:50.360547 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4776 12:32:50.363918 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4777 12:32:50.367157 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4778 12:32:50.367260
4779 12:32:50.367361
4780 12:32:50.367459 ==
4781 12:32:50.369838 Dram Type= 6, Freq= 0, CH_1, rank 1
4782 12:32:50.373787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4783 12:32:50.377003 ==
4784 12:32:50.377093
4785 12:32:50.377186
4786 12:32:50.377278 TX Vref Scan disable
4787 12:32:50.380149 == TX Byte 0 ==
4788 12:32:50.383296 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4789 12:32:50.386499 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4790 12:32:50.389966 == TX Byte 1 ==
4791 12:32:50.393230 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4792 12:32:50.396518 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4793 12:32:50.399915 ==
4794 12:32:50.399997 Dram Type= 6, Freq= 0, CH_1, rank 1
4795 12:32:50.406825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4796 12:32:50.406907 ==
4797 12:32:50.406971
4798 12:32:50.407031
4799 12:32:50.409969 TX Vref Scan disable
4800 12:32:50.410050 == TX Byte 0 ==
4801 12:32:50.416511 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4802 12:32:50.420265 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4803 12:32:50.420347 == TX Byte 1 ==
4804 12:32:50.426598 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4805 12:32:50.429756 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4806 12:32:50.429838
4807 12:32:50.429903 [DATLAT]
4808 12:32:50.433603 Freq=600, CH1 RK1
4809 12:32:50.433686
4810 12:32:50.433750 DATLAT Default: 0x9
4811 12:32:50.436381 0, 0xFFFF, sum = 0
4812 12:32:50.436465 1, 0xFFFF, sum = 0
4813 12:32:50.440329 2, 0xFFFF, sum = 0
4814 12:32:50.440438 3, 0xFFFF, sum = 0
4815 12:32:50.442947 4, 0xFFFF, sum = 0
4816 12:32:50.446248 5, 0xFFFF, sum = 0
4817 12:32:50.446358 6, 0xFFFF, sum = 0
4818 12:32:50.449689 7, 0xFFFF, sum = 0
4819 12:32:50.449772 8, 0x0, sum = 1
4820 12:32:50.449838 9, 0x0, sum = 2
4821 12:32:50.453016 10, 0x0, sum = 3
4822 12:32:50.453099 11, 0x0, sum = 4
4823 12:32:50.456251 best_step = 9
4824 12:32:50.456332
4825 12:32:50.456396 ==
4826 12:32:50.460050 Dram Type= 6, Freq= 0, CH_1, rank 1
4827 12:32:50.463260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4828 12:32:50.463389 ==
4829 12:32:50.466660 RX Vref Scan: 0
4830 12:32:50.466742
4831 12:32:50.466806 RX Vref 0 -> 0, step: 1
4832 12:32:50.466865
4833 12:32:50.470078 RX Delay -195 -> 252, step: 8
4834 12:32:50.476712 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4835 12:32:50.480048 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4836 12:32:50.483894 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4837 12:32:50.487060 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4838 12:32:50.493626 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4839 12:32:50.497054 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4840 12:32:50.500311 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4841 12:32:50.503139 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4842 12:32:50.510137 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4843 12:32:50.513277 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4844 12:32:50.516606 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4845 12:32:50.519906 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4846 12:32:50.523723 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4847 12:32:50.529947 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4848 12:32:50.533195 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4849 12:32:50.536291 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4850 12:32:50.536375 ==
4851 12:32:50.539971 Dram Type= 6, Freq= 0, CH_1, rank 1
4852 12:32:50.546445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4853 12:32:50.546554 ==
4854 12:32:50.546625 DQS Delay:
4855 12:32:50.549683 DQS0 = 0, DQS1 = 0
4856 12:32:50.549765 DQM Delay:
4857 12:32:50.549860 DQM0 = 36, DQM1 = 33
4858 12:32:50.553086 DQ Delay:
4859 12:32:50.556217 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4860 12:32:50.559593 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4861 12:32:50.562938 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4862 12:32:50.565989 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4863 12:32:50.566125
4864 12:32:50.566308
4865 12:32:50.572699 [DQSOSCAuto] RK1, (LSB)MR18= 0x3543, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 399 ps
4866 12:32:50.575920 CH1 RK1: MR19=808, MR18=3543
4867 12:32:50.582452 CH1_RK1: MR19=0x808, MR18=0x3543, DQSOSC=397, MR23=63, INC=166, DEC=110
4868 12:32:50.586406 [RxdqsGatingPostProcess] freq 600
4869 12:32:50.589499 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4870 12:32:50.592661 Pre-setting of DQS Precalculation
4871 12:32:50.599146 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4872 12:32:50.605799 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4873 12:32:50.612214 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4874 12:32:50.612324
4875 12:32:50.612419
4876 12:32:50.616150 [Calibration Summary] 1200 Mbps
4877 12:32:50.616259 CH 0, Rank 0
4878 12:32:50.619328 SW Impedance : PASS
4879 12:32:50.622684 DUTY Scan : NO K
4880 12:32:50.622766 ZQ Calibration : PASS
4881 12:32:50.625875 Jitter Meter : NO K
4882 12:32:50.628985 CBT Training : PASS
4883 12:32:50.629067 Write leveling : PASS
4884 12:32:50.632805 RX DQS gating : PASS
4885 12:32:50.636298 RX DQ/DQS(RDDQC) : PASS
4886 12:32:50.636382 TX DQ/DQS : PASS
4887 12:32:50.639386 RX DATLAT : PASS
4888 12:32:50.642468 RX DQ/DQS(Engine): PASS
4889 12:32:50.642583 TX OE : NO K
4890 12:32:50.642687 All Pass.
4891 12:32:50.645668
4892 12:32:50.645751 CH 0, Rank 1
4893 12:32:50.649469 SW Impedance : PASS
4894 12:32:50.649567 DUTY Scan : NO K
4895 12:32:50.652883 ZQ Calibration : PASS
4896 12:32:50.652966 Jitter Meter : NO K
4897 12:32:50.655368 CBT Training : PASS
4898 12:32:50.658802 Write leveling : PASS
4899 12:32:50.658887 RX DQS gating : PASS
4900 12:32:50.662703 RX DQ/DQS(RDDQC) : PASS
4901 12:32:50.665950 TX DQ/DQS : PASS
4902 12:32:50.666033 RX DATLAT : PASS
4903 12:32:50.669259 RX DQ/DQS(Engine): PASS
4904 12:32:50.672456 TX OE : NO K
4905 12:32:50.672539 All Pass.
4906 12:32:50.672604
4907 12:32:50.672663 CH 1, Rank 0
4908 12:32:50.675841 SW Impedance : PASS
4909 12:32:50.679229 DUTY Scan : NO K
4910 12:32:50.679311 ZQ Calibration : PASS
4911 12:32:50.682402 Jitter Meter : NO K
4912 12:32:50.685772 CBT Training : PASS
4913 12:32:50.685855 Write leveling : PASS
4914 12:32:50.689070 RX DQS gating : PASS
4915 12:32:50.692304 RX DQ/DQS(RDDQC) : PASS
4916 12:32:50.692386 TX DQ/DQS : PASS
4917 12:32:50.695407 RX DATLAT : PASS
4918 12:32:50.695489 RX DQ/DQS(Engine): PASS
4919 12:32:50.699083 TX OE : NO K
4920 12:32:50.699204 All Pass.
4921 12:32:50.699268
4922 12:32:50.702382 CH 1, Rank 1
4923 12:32:50.702464 SW Impedance : PASS
4924 12:32:50.705607 DUTY Scan : NO K
4925 12:32:50.708869 ZQ Calibration : PASS
4926 12:32:50.708951 Jitter Meter : NO K
4927 12:32:50.712117 CBT Training : PASS
4928 12:32:50.715360 Write leveling : PASS
4929 12:32:50.715473 RX DQS gating : PASS
4930 12:32:50.719252 RX DQ/DQS(RDDQC) : PASS
4931 12:32:50.722543 TX DQ/DQS : PASS
4932 12:32:50.722626 RX DATLAT : PASS
4933 12:32:50.725851 RX DQ/DQS(Engine): PASS
4934 12:32:50.728911 TX OE : NO K
4935 12:32:50.728994 All Pass.
4936 12:32:50.729059
4937 12:32:50.732270 DramC Write-DBI off
4938 12:32:50.732352 PER_BANK_REFRESH: Hybrid Mode
4939 12:32:50.735276 TX_TRACKING: ON
4940 12:32:50.742376 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4941 12:32:50.745510 [FAST_K] Save calibration result to emmc
4942 12:32:50.751877 dramc_set_vcore_voltage set vcore to 662500
4943 12:32:50.751961 Read voltage for 933, 3
4944 12:32:50.755217 Vio18 = 0
4945 12:32:50.755325 Vcore = 662500
4946 12:32:50.755461 Vdram = 0
4947 12:32:50.759055 Vddq = 0
4948 12:32:50.759163 Vmddr = 0
4949 12:32:50.762369 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4950 12:32:50.768981 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4951 12:32:50.772248 MEM_TYPE=3, freq_sel=17
4952 12:32:50.775540 sv_algorithm_assistance_LP4_1600
4953 12:32:50.778895 ============ PULL DRAM RESETB DOWN ============
4954 12:32:50.782121 ========== PULL DRAM RESETB DOWN end =========
4955 12:32:50.785394 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4956 12:32:50.788840 ===================================
4957 12:32:50.792078 LPDDR4 DRAM CONFIGURATION
4958 12:32:50.795416 ===================================
4959 12:32:50.798528 EX_ROW_EN[0] = 0x0
4960 12:32:50.798610 EX_ROW_EN[1] = 0x0
4961 12:32:50.801678 LP4Y_EN = 0x0
4962 12:32:50.801761 WORK_FSP = 0x0
4963 12:32:50.805517 WL = 0x3
4964 12:32:50.805599 RL = 0x3
4965 12:32:50.808997 BL = 0x2
4966 12:32:50.809079 RPST = 0x0
4967 12:32:50.812165 RD_PRE = 0x0
4968 12:32:50.812248 WR_PRE = 0x1
4969 12:32:50.815497 WR_PST = 0x0
4970 12:32:50.818237 DBI_WR = 0x0
4971 12:32:50.818320 DBI_RD = 0x0
4972 12:32:50.821920 OTF = 0x1
4973 12:32:50.825279 ===================================
4974 12:32:50.828848 ===================================
4975 12:32:50.828931 ANA top config
4976 12:32:50.831645 ===================================
4977 12:32:50.835085 DLL_ASYNC_EN = 0
4978 12:32:50.835156 ALL_SLAVE_EN = 1
4979 12:32:50.838440 NEW_RANK_MODE = 1
4980 12:32:50.841550 DLL_IDLE_MODE = 1
4981 12:32:50.845265 LP45_APHY_COMB_EN = 1
4982 12:32:50.848534 TX_ODT_DIS = 1
4983 12:32:50.848618 NEW_8X_MODE = 1
4984 12:32:50.851622 ===================================
4985 12:32:50.854852 ===================================
4986 12:32:50.858028 data_rate = 1866
4987 12:32:50.861409 CKR = 1
4988 12:32:50.864801 DQ_P2S_RATIO = 8
4989 12:32:50.868010 ===================================
4990 12:32:50.871228 CA_P2S_RATIO = 8
4991 12:32:50.874520 DQ_CA_OPEN = 0
4992 12:32:50.874603 DQ_SEMI_OPEN = 0
4993 12:32:50.877844 CA_SEMI_OPEN = 0
4994 12:32:50.881263 CA_FULL_RATE = 0
4995 12:32:50.884588 DQ_CKDIV4_EN = 1
4996 12:32:50.887901 CA_CKDIV4_EN = 1
4997 12:32:50.891123 CA_PREDIV_EN = 0
4998 12:32:50.891206 PH8_DLY = 0
4999 12:32:50.894422 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5000 12:32:50.897803 DQ_AAMCK_DIV = 4
5001 12:32:50.901220 CA_AAMCK_DIV = 4
5002 12:32:50.904577 CA_ADMCK_DIV = 4
5003 12:32:50.907725 DQ_TRACK_CA_EN = 0
5004 12:32:50.907810 CA_PICK = 933
5005 12:32:50.910876 CA_MCKIO = 933
5006 12:32:50.914870 MCKIO_SEMI = 0
5007 12:32:50.918106 PLL_FREQ = 3732
5008 12:32:50.921460 DQ_UI_PI_RATIO = 32
5009 12:32:50.924719 CA_UI_PI_RATIO = 0
5010 12:32:50.927854 ===================================
5011 12:32:50.931241 ===================================
5012 12:32:50.931325 memory_type:LPDDR4
5013 12:32:50.934624 GP_NUM : 10
5014 12:32:50.937813 SRAM_EN : 1
5015 12:32:50.937896 MD32_EN : 0
5016 12:32:50.941372 ===================================
5017 12:32:50.944647 [ANA_INIT] >>>>>>>>>>>>>>
5018 12:32:50.947789 <<<<<< [CONFIGURE PHASE]: ANA_TX
5019 12:32:50.950911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5020 12:32:50.954809 ===================================
5021 12:32:50.957889 data_rate = 1866,PCW = 0X8f00
5022 12:32:50.961090 ===================================
5023 12:32:50.964130 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5024 12:32:50.967328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5025 12:32:50.974565 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5026 12:32:50.977932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5027 12:32:50.984390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5028 12:32:50.987695 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5029 12:32:50.987815 [ANA_INIT] flow start
5030 12:32:50.991074 [ANA_INIT] PLL >>>>>>>>
5031 12:32:50.994451 [ANA_INIT] PLL <<<<<<<<
5032 12:32:50.994539 [ANA_INIT] MIDPI >>>>>>>>
5033 12:32:50.997658 [ANA_INIT] MIDPI <<<<<<<<
5034 12:32:51.000802 [ANA_INIT] DLL >>>>>>>>
5035 12:32:51.000885 [ANA_INIT] flow end
5036 12:32:51.004235 ============ LP4 DIFF to SE enter ============
5037 12:32:51.010722 ============ LP4 DIFF to SE exit ============
5038 12:32:51.010807 [ANA_INIT] <<<<<<<<<<<<<
5039 12:32:51.013888 [Flow] Enable top DCM control >>>>>
5040 12:32:51.017241 [Flow] Enable top DCM control <<<<<
5041 12:32:51.021041 Enable DLL master slave shuffle
5042 12:32:51.027637 ==============================================================
5043 12:32:51.027722 Gating Mode config
5044 12:32:51.034104 ==============================================================
5045 12:32:51.037531 Config description:
5046 12:32:51.047260 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5047 12:32:51.054122 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5048 12:32:51.057415 SELPH_MODE 0: By rank 1: By Phase
5049 12:32:51.064223 ==============================================================
5050 12:32:51.067463 GAT_TRACK_EN = 1
5051 12:32:51.070664 RX_GATING_MODE = 2
5052 12:32:51.070747 RX_GATING_TRACK_MODE = 2
5053 12:32:51.073922 SELPH_MODE = 1
5054 12:32:51.077331 PICG_EARLY_EN = 1
5055 12:32:51.080525 VALID_LAT_VALUE = 1
5056 12:32:51.087216 ==============================================================
5057 12:32:51.090489 Enter into Gating configuration >>>>
5058 12:32:51.093668 Exit from Gating configuration <<<<
5059 12:32:51.096964 Enter into DVFS_PRE_config >>>>>
5060 12:32:51.106955 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5061 12:32:51.110124 Exit from DVFS_PRE_config <<<<<
5062 12:32:51.114116 Enter into PICG configuration >>>>
5063 12:32:51.116725 Exit from PICG configuration <<<<
5064 12:32:51.120553 [RX_INPUT] configuration >>>>>
5065 12:32:51.123698 [RX_INPUT] configuration <<<<<
5066 12:32:51.127026 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5067 12:32:51.133668 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5068 12:32:51.140311 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5069 12:32:51.146791 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5070 12:32:51.150079 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5071 12:32:51.156523 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5072 12:32:51.160386 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5073 12:32:51.166881 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5074 12:32:51.170054 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5075 12:32:51.173258 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5076 12:32:51.177105 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5077 12:32:51.183731 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5078 12:32:51.187056 ===================================
5079 12:32:51.187160 LPDDR4 DRAM CONFIGURATION
5080 12:32:51.190331 ===================================
5081 12:32:51.193624 EX_ROW_EN[0] = 0x0
5082 12:32:51.196877 EX_ROW_EN[1] = 0x0
5083 12:32:51.196960 LP4Y_EN = 0x0
5084 12:32:51.200182 WORK_FSP = 0x0
5085 12:32:51.200259 WL = 0x3
5086 12:32:51.203444 RL = 0x3
5087 12:32:51.203519 BL = 0x2
5088 12:32:51.206694 RPST = 0x0
5089 12:32:51.206785 RD_PRE = 0x0
5090 12:32:51.209858 WR_PRE = 0x1
5091 12:32:51.209959 WR_PST = 0x0
5092 12:32:51.213407 DBI_WR = 0x0
5093 12:32:51.213482 DBI_RD = 0x0
5094 12:32:51.216557 OTF = 0x1
5095 12:32:51.219959 ===================================
5096 12:32:51.223718 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5097 12:32:51.226784 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5098 12:32:51.233289 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5099 12:32:51.236644 ===================================
5100 12:32:51.236728 LPDDR4 DRAM CONFIGURATION
5101 12:32:51.239987 ===================================
5102 12:32:51.243106 EX_ROW_EN[0] = 0x10
5103 12:32:51.246311 EX_ROW_EN[1] = 0x0
5104 12:32:51.246394 LP4Y_EN = 0x0
5105 12:32:51.249814 WORK_FSP = 0x0
5106 12:32:51.249896 WL = 0x3
5107 12:32:51.253614 RL = 0x3
5108 12:32:51.253697 BL = 0x2
5109 12:32:51.256593 RPST = 0x0
5110 12:32:51.256709 RD_PRE = 0x0
5111 12:32:51.259858 WR_PRE = 0x1
5112 12:32:51.259945 WR_PST = 0x0
5113 12:32:51.263716 DBI_WR = 0x0
5114 12:32:51.263802 DBI_RD = 0x0
5115 12:32:51.266298 OTF = 0x1
5116 12:32:51.270205 ===================================
5117 12:32:51.276540 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5118 12:32:51.279717 nWR fixed to 30
5119 12:32:51.279805 [ModeRegInit_LP4] CH0 RK0
5120 12:32:51.283162 [ModeRegInit_LP4] CH0 RK1
5121 12:32:51.286425 [ModeRegInit_LP4] CH1 RK0
5122 12:32:51.286511 [ModeRegInit_LP4] CH1 RK1
5123 12:32:51.289684 match AC timing 9
5124 12:32:51.292888 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5125 12:32:51.296242 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5126 12:32:51.303601 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5127 12:32:51.306743 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5128 12:32:51.313418 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5129 12:32:51.313504 ==
5130 12:32:51.316690 Dram Type= 6, Freq= 0, CH_0, rank 0
5131 12:32:51.319935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 12:32:51.320020 ==
5133 12:32:51.326582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5134 12:32:51.332993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5135 12:32:51.336409 [CA 0] Center 38 (7~69) winsize 63
5136 12:32:51.339650 [CA 1] Center 37 (7~68) winsize 62
5137 12:32:51.342665 [CA 2] Center 35 (5~66) winsize 62
5138 12:32:51.346155 [CA 3] Center 34 (4~65) winsize 62
5139 12:32:51.349373 [CA 4] Center 34 (4~65) winsize 62
5140 12:32:51.349462 [CA 5] Center 34 (4~64) winsize 61
5141 12:32:51.352631
5142 12:32:51.355881 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5143 12:32:51.355967
5144 12:32:51.359661 [CATrainingPosCal] consider 1 rank data
5145 12:32:51.362900 u2DelayCellTimex100 = 270/100 ps
5146 12:32:51.366135 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5147 12:32:51.369310 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5148 12:32:51.372709 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5149 12:32:51.375930 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5150 12:32:51.379209 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5151 12:32:51.382723 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5152 12:32:51.382809
5153 12:32:51.385817 CA PerBit enable=1, Macro0, CA PI delay=34
5154 12:32:51.389058
5155 12:32:51.389143 [CBTSetCACLKResult] CA Dly = 34
5156 12:32:51.392490 CS Dly: 6 (0~37)
5157 12:32:51.392575 ==
5158 12:32:51.395781 Dram Type= 6, Freq= 0, CH_0, rank 1
5159 12:32:51.399138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 12:32:51.399221 ==
5161 12:32:51.405798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5162 12:32:51.412272 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5163 12:32:51.415520 [CA 0] Center 38 (8~69) winsize 62
5164 12:32:51.418849 [CA 1] Center 38 (8~69) winsize 62
5165 12:32:51.422099 [CA 2] Center 35 (5~66) winsize 62
5166 12:32:51.426039 [CA 3] Center 34 (4~65) winsize 62
5167 12:32:51.429362 [CA 4] Center 34 (3~65) winsize 63
5168 12:32:51.432431 [CA 5] Center 33 (3~64) winsize 62
5169 12:32:51.432515
5170 12:32:51.435770 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5171 12:32:51.435853
5172 12:32:51.439234 [CATrainingPosCal] consider 2 rank data
5173 12:32:51.441986 u2DelayCellTimex100 = 270/100 ps
5174 12:32:51.445793 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5175 12:32:51.449122 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5176 12:32:51.452495 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5177 12:32:51.455088 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5178 12:32:51.458474 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5179 12:32:51.462267 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5180 12:32:51.462351
5181 12:32:51.468515 CA PerBit enable=1, Macro0, CA PI delay=34
5182 12:32:51.468599
5183 12:32:51.468664 [CBTSetCACLKResult] CA Dly = 34
5184 12:32:51.472337 CS Dly: 7 (0~39)
5185 12:32:51.472420
5186 12:32:51.475486 ----->DramcWriteLeveling(PI) begin...
5187 12:32:51.475573 ==
5188 12:32:51.478893 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 12:32:51.482056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 12:32:51.482140 ==
5191 12:32:51.485201 Write leveling (Byte 0): 32 => 32
5192 12:32:51.489029 Write leveling (Byte 1): 27 => 27
5193 12:32:51.491698 DramcWriteLeveling(PI) end<-----
5194 12:32:51.491781
5195 12:32:51.491847 ==
5196 12:32:51.495013 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 12:32:51.502130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 12:32:51.502217 ==
5199 12:32:51.502283 [Gating] SW mode calibration
5200 12:32:51.511626 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5201 12:32:51.515270 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5202 12:32:51.518689 0 14 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5203 12:32:51.525242 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5204 12:32:51.528558 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5205 12:32:51.531642 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5206 12:32:51.538095 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5207 12:32:51.541307 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5208 12:32:51.544607 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5209 12:32:51.551755 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5210 12:32:51.555056 0 15 0 | B1->B0 | 3030 2d2d | 1 0 | (1 0) (0 0)
5211 12:32:51.558389 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5212 12:32:51.564826 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5213 12:32:51.567994 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5214 12:32:51.571226 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5215 12:32:51.578286 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5216 12:32:51.581468 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5217 12:32:51.584813 0 15 28 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
5218 12:32:51.591123 1 0 0 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
5219 12:32:51.594910 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5220 12:32:51.598035 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5221 12:32:51.604545 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5222 12:32:51.607771 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 12:32:51.611165 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 12:32:51.617788 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 12:32:51.621052 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5226 12:32:51.624307 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5227 12:32:51.630869 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5228 12:32:51.634158 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 12:32:51.637443 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 12:32:51.644653 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 12:32:51.647827 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 12:32:51.651095 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 12:32:51.657601 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 12:32:51.660999 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 12:32:51.664300 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 12:32:51.670674 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 12:32:51.673905 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 12:32:51.677204 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 12:32:51.684221 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 12:32:51.687548 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 12:32:51.690738 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5242 12:32:51.693984 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5243 12:32:51.700912 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5244 12:32:51.704201 Total UI for P1: 0, mck2ui 16
5245 12:32:51.707551 best dqsien dly found for B0: ( 1, 2, 30)
5246 12:32:51.710760 Total UI for P1: 0, mck2ui 16
5247 12:32:51.713929 best dqsien dly found for B1: ( 1, 2, 30)
5248 12:32:51.717217 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5249 12:32:51.720607 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5250 12:32:51.720716
5251 12:32:51.723874 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5252 12:32:51.727261 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5253 12:32:51.730614 [Gating] SW calibration Done
5254 12:32:51.730725 ==
5255 12:32:51.733924 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 12:32:51.737241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 12:32:51.737317 ==
5258 12:32:51.740516 RX Vref Scan: 0
5259 12:32:51.740591
5260 12:32:51.743706 RX Vref 0 -> 0, step: 1
5261 12:32:51.743808
5262 12:32:51.743901 RX Delay -80 -> 252, step: 8
5263 12:32:51.750158 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5264 12:32:51.753379 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5265 12:32:51.757160 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5266 12:32:51.759948 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5267 12:32:51.763226 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5268 12:32:51.767072 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5269 12:32:51.773705 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5270 12:32:51.776850 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5271 12:32:51.780146 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5272 12:32:51.783450 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5273 12:32:51.786482 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5274 12:32:51.793493 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5275 12:32:51.796990 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5276 12:32:51.800122 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5277 12:32:51.803142 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5278 12:32:51.807130 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5279 12:32:51.807236 ==
5280 12:32:51.809775 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 12:32:51.817040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 12:32:51.817151 ==
5283 12:32:51.817247 DQS Delay:
5284 12:32:51.817344 DQS0 = 0, DQS1 = 0
5285 12:32:51.820299 DQM Delay:
5286 12:32:51.820383 DQM0 = 99, DQM1 = 87
5287 12:32:51.823514 DQ Delay:
5288 12:32:51.826933 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5289 12:32:51.830144 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5290 12:32:51.833268 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5291 12:32:51.836740 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5292 12:32:51.836851
5293 12:32:51.836946
5294 12:32:51.837038 ==
5295 12:32:51.840050 Dram Type= 6, Freq= 0, CH_0, rank 0
5296 12:32:51.843346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 12:32:51.843530 ==
5298 12:32:51.843635
5299 12:32:51.843728
5300 12:32:51.846672 TX Vref Scan disable
5301 12:32:51.846781 == TX Byte 0 ==
5302 12:32:51.853112 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5303 12:32:51.856379 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5304 12:32:51.860112 == TX Byte 1 ==
5305 12:32:51.863445 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5306 12:32:51.866168 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5307 12:32:51.866250 ==
5308 12:32:51.870081 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 12:32:51.873278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 12:32:51.873361 ==
5311 12:32:51.876679
5312 12:32:51.876760
5313 12:32:51.876824 TX Vref Scan disable
5314 12:32:51.879867 == TX Byte 0 ==
5315 12:32:51.883037 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5316 12:32:51.889885 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5317 12:32:51.889968 == TX Byte 1 ==
5318 12:32:51.893003 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5319 12:32:51.899463 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5320 12:32:51.899545
5321 12:32:51.899609 [DATLAT]
5322 12:32:51.899669 Freq=933, CH0 RK0
5323 12:32:51.899728
5324 12:32:51.903352 DATLAT Default: 0xd
5325 12:32:51.903487 0, 0xFFFF, sum = 0
5326 12:32:51.906448 1, 0xFFFF, sum = 0
5327 12:32:51.909722 2, 0xFFFF, sum = 0
5328 12:32:51.909805 3, 0xFFFF, sum = 0
5329 12:32:51.912991 4, 0xFFFF, sum = 0
5330 12:32:51.913074 5, 0xFFFF, sum = 0
5331 12:32:51.916175 6, 0xFFFF, sum = 0
5332 12:32:51.916259 7, 0xFFFF, sum = 0
5333 12:32:51.919500 8, 0xFFFF, sum = 0
5334 12:32:51.919583 9, 0xFFFF, sum = 0
5335 12:32:51.922697 10, 0x0, sum = 1
5336 12:32:51.922780 11, 0x0, sum = 2
5337 12:32:51.926604 12, 0x0, sum = 3
5338 12:32:51.926686 13, 0x0, sum = 4
5339 12:32:51.926753 best_step = 11
5340 12:32:51.926812
5341 12:32:51.929807 ==
5342 12:32:51.933169 Dram Type= 6, Freq= 0, CH_0, rank 0
5343 12:32:51.936382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 12:32:51.936465 ==
5345 12:32:51.936529 RX Vref Scan: 1
5346 12:32:51.936589
5347 12:32:51.939716 RX Vref 0 -> 0, step: 1
5348 12:32:51.939798
5349 12:32:51.943048 RX Delay -61 -> 252, step: 4
5350 12:32:51.943131
5351 12:32:51.946289 Set Vref, RX VrefLevel [Byte0]: 53
5352 12:32:51.949585 [Byte1]: 51
5353 12:32:51.949668
5354 12:32:51.952870 Final RX Vref Byte 0 = 53 to rank0
5355 12:32:51.956137 Final RX Vref Byte 1 = 51 to rank0
5356 12:32:51.959844 Final RX Vref Byte 0 = 53 to rank1
5357 12:32:51.963155 Final RX Vref Byte 1 = 51 to rank1==
5358 12:32:51.966271 Dram Type= 6, Freq= 0, CH_0, rank 0
5359 12:32:51.969587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 12:32:51.972864 ==
5361 12:32:51.972973 DQS Delay:
5362 12:32:51.973072 DQS0 = 0, DQS1 = 0
5363 12:32:51.976181 DQM Delay:
5364 12:32:51.976282 DQM0 = 97, DQM1 = 88
5365 12:32:51.979310 DQ Delay:
5366 12:32:51.979451 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5367 12:32:51.982561 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =102
5368 12:32:51.985890 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =80
5369 12:32:51.992803 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =96
5370 12:32:51.992906
5371 12:32:51.992997
5372 12:32:51.999175 [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5373 12:32:52.002917 CH0 RK0: MR19=504, MR18=14FF
5374 12:32:52.009421 CH0_RK0: MR19=0x504, MR18=0x14FF, DQSOSC=415, MR23=63, INC=62, DEC=41
5375 12:32:52.009529
5376 12:32:52.012582 ----->DramcWriteLeveling(PI) begin...
5377 12:32:52.012665 ==
5378 12:32:52.015780 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 12:32:52.019065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 12:32:52.019148 ==
5381 12:32:52.022337 Write leveling (Byte 0): 31 => 31
5382 12:32:52.025586 Write leveling (Byte 1): 30 => 30
5383 12:32:52.028898 DramcWriteLeveling(PI) end<-----
5384 12:32:52.028967
5385 12:32:52.029028 ==
5386 12:32:52.032160 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 12:32:52.035520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 12:32:52.035592 ==
5389 12:32:52.038834 [Gating] SW mode calibration
5390 12:32:52.045941 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5391 12:32:52.052520 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5392 12:32:52.055653 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5393 12:32:52.059035 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5394 12:32:52.065621 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5395 12:32:52.068855 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5396 12:32:52.072137 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5397 12:32:52.078595 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5398 12:32:52.081836 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5399 12:32:52.085233 0 14 28 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (0 0)
5400 12:32:52.092134 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5401 12:32:52.095363 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5402 12:32:52.098638 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5403 12:32:52.105483 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5404 12:32:52.108796 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5405 12:32:52.111987 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5406 12:32:52.118342 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 12:32:52.121685 0 15 28 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)
5408 12:32:52.124778 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5409 12:32:52.131462 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 12:32:52.135344 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 12:32:52.138032 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 12:32:52.144758 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 12:32:52.148698 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 12:32:52.151361 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5415 12:32:52.157981 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5416 12:32:52.161998 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5417 12:32:52.164651 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 12:32:52.171662 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 12:32:52.174877 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 12:32:52.178060 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 12:32:52.184584 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 12:32:52.187788 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 12:32:52.191098 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 12:32:52.197972 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 12:32:52.201204 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 12:32:52.204574 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 12:32:52.211624 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 12:32:52.214221 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 12:32:52.217522 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 12:32:52.224316 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5431 12:32:52.227725 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5432 12:32:52.230975 Total UI for P1: 0, mck2ui 16
5433 12:32:52.234231 best dqsien dly found for B0: ( 1, 2, 24)
5434 12:32:52.237670 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5435 12:32:52.240855 Total UI for P1: 0, mck2ui 16
5436 12:32:52.244208 best dqsien dly found for B1: ( 1, 2, 28)
5437 12:32:52.247341 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5438 12:32:52.250659 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5439 12:32:52.250742
5440 12:32:52.257178 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5441 12:32:52.260483 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5442 12:32:52.260612 [Gating] SW calibration Done
5443 12:32:52.264554 ==
5444 12:32:52.264637 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 12:32:52.270976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 12:32:52.271085 ==
5447 12:32:52.271196 RX Vref Scan: 0
5448 12:32:52.271286
5449 12:32:52.274113 RX Vref 0 -> 0, step: 1
5450 12:32:52.274195
5451 12:32:52.277445 RX Delay -80 -> 252, step: 8
5452 12:32:52.280625 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5453 12:32:52.284442 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5454 12:32:52.287825 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5455 12:32:52.291096 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5456 12:32:52.297715 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5457 12:32:52.300908 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5458 12:32:52.303907 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5459 12:32:52.307166 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5460 12:32:52.310931 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5461 12:32:52.314089 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5462 12:32:52.320593 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5463 12:32:52.323674 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5464 12:32:52.327432 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5465 12:32:52.330618 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5466 12:32:52.333810 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5467 12:32:52.340346 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5468 12:32:52.340429 ==
5469 12:32:52.343658 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 12:32:52.346922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 12:32:52.347005 ==
5472 12:32:52.347070 DQS Delay:
5473 12:32:52.350226 DQS0 = 0, DQS1 = 0
5474 12:32:52.350308 DQM Delay:
5475 12:32:52.353659 DQM0 = 97, DQM1 = 88
5476 12:32:52.353741 DQ Delay:
5477 12:32:52.356882 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5478 12:32:52.360116 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5479 12:32:52.364022 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =75
5480 12:32:52.366714 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5481 12:32:52.366797
5482 12:32:52.366862
5483 12:32:52.366921 ==
5484 12:32:52.370198 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 12:32:52.373458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 12:32:52.373541 ==
5487 12:32:52.376686
5488 12:32:52.376768
5489 12:32:52.376833 TX Vref Scan disable
5490 12:32:52.380433 == TX Byte 0 ==
5491 12:32:52.383663 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5492 12:32:52.387070 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5493 12:32:52.390515 == TX Byte 1 ==
5494 12:32:52.393670 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5495 12:32:52.397054 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5496 12:32:52.397137 ==
5497 12:32:52.400227 Dram Type= 6, Freq= 0, CH_0, rank 1
5498 12:32:52.406715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 12:32:52.406798 ==
5500 12:32:52.406863
5501 12:32:52.406923
5502 12:32:52.406980 TX Vref Scan disable
5503 12:32:52.411079 == TX Byte 0 ==
5504 12:32:52.414502 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5505 12:32:52.420925 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5506 12:32:52.421045 == TX Byte 1 ==
5507 12:32:52.424213 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5508 12:32:52.430727 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5509 12:32:52.430811
5510 12:32:52.430877 [DATLAT]
5511 12:32:52.430937 Freq=933, CH0 RK1
5512 12:32:52.430996
5513 12:32:52.433911 DATLAT Default: 0xb
5514 12:32:52.437042 0, 0xFFFF, sum = 0
5515 12:32:52.437127 1, 0xFFFF, sum = 0
5516 12:32:52.440444 2, 0xFFFF, sum = 0
5517 12:32:52.440528 3, 0xFFFF, sum = 0
5518 12:32:52.443645 4, 0xFFFF, sum = 0
5519 12:32:52.443730 5, 0xFFFF, sum = 0
5520 12:32:52.446962 6, 0xFFFF, sum = 0
5521 12:32:52.447047 7, 0xFFFF, sum = 0
5522 12:32:52.450916 8, 0xFFFF, sum = 0
5523 12:32:52.451026 9, 0xFFFF, sum = 0
5524 12:32:52.454372 10, 0x0, sum = 1
5525 12:32:52.454456 11, 0x0, sum = 2
5526 12:32:52.457669 12, 0x0, sum = 3
5527 12:32:52.457754 13, 0x0, sum = 4
5528 12:32:52.457820 best_step = 11
5529 12:32:52.457880
5530 12:32:52.460909 ==
5531 12:32:52.464264 Dram Type= 6, Freq= 0, CH_0, rank 1
5532 12:32:52.466978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 12:32:52.467061 ==
5534 12:32:52.467127 RX Vref Scan: 0
5535 12:32:52.467187
5536 12:32:52.470269 RX Vref 0 -> 0, step: 1
5537 12:32:52.470352
5538 12:32:52.473656 RX Delay -61 -> 252, step: 4
5539 12:32:52.476999 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5540 12:32:52.483908 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5541 12:32:52.487210 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5542 12:32:52.490477 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5543 12:32:52.493766 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5544 12:32:52.497097 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5545 12:32:52.500598 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5546 12:32:52.507075 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5547 12:32:52.510148 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5548 12:32:52.513308 iDelay=199, Bit 9, Center 76 (-13 ~ 166) 180
5549 12:32:52.516597 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5550 12:32:52.523032 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5551 12:32:52.526442 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5552 12:32:52.529728 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5553 12:32:52.533025 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5554 12:32:52.536742 iDelay=199, Bit 15, Center 98 (11 ~ 186) 176
5555 12:32:52.536821 ==
5556 12:32:52.539810 Dram Type= 6, Freq= 0, CH_0, rank 1
5557 12:32:52.546149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 12:32:52.546229 ==
5559 12:32:52.546324 DQS Delay:
5560 12:32:52.549575 DQS0 = 0, DQS1 = 0
5561 12:32:52.549649 DQM Delay:
5562 12:32:52.549711 DQM0 = 95, DQM1 = 87
5563 12:32:52.552745 DQ Delay:
5564 12:32:52.556015 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5565 12:32:52.559189 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5566 12:32:52.563172 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =80
5567 12:32:52.566486 DQ12 =90, DQ13 =92, DQ14 =98, DQ15 =98
5568 12:32:52.566591
5569 12:32:52.566686
5570 12:32:52.573045 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
5571 12:32:52.576264 CH0 RK1: MR19=505, MR18=1C09
5572 12:32:52.582954 CH0_RK1: MR19=0x505, MR18=0x1C09, DQSOSC=412, MR23=63, INC=63, DEC=42
5573 12:32:52.586313 [RxdqsGatingPostProcess] freq 933
5574 12:32:52.589553 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5575 12:32:52.592547 best DQS0 dly(2T, 0.5T) = (0, 10)
5576 12:32:52.595859 best DQS1 dly(2T, 0.5T) = (0, 10)
5577 12:32:52.599837 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5578 12:32:52.603143 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5579 12:32:52.606237 best DQS0 dly(2T, 0.5T) = (0, 10)
5580 12:32:52.609577 best DQS1 dly(2T, 0.5T) = (0, 10)
5581 12:32:52.612784 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5582 12:32:52.615991 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5583 12:32:52.619448 Pre-setting of DQS Precalculation
5584 12:32:52.622688 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5585 12:32:52.625866 ==
5586 12:32:52.628954 Dram Type= 6, Freq= 0, CH_1, rank 0
5587 12:32:52.632886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5588 12:32:52.632969 ==
5589 12:32:52.635525 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5590 12:32:52.642596 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5591 12:32:52.645876 [CA 0] Center 36 (6~67) winsize 62
5592 12:32:52.649669 [CA 1] Center 36 (6~67) winsize 62
5593 12:32:52.652230 [CA 2] Center 34 (4~64) winsize 61
5594 12:32:52.655981 [CA 3] Center 34 (4~64) winsize 61
5595 12:32:52.659430 [CA 4] Center 34 (4~64) winsize 61
5596 12:32:52.662771 [CA 5] Center 33 (3~64) winsize 62
5597 12:32:52.662853
5598 12:32:52.665902 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5599 12:32:52.666009
5600 12:32:52.669053 [CATrainingPosCal] consider 1 rank data
5601 12:32:52.672424 u2DelayCellTimex100 = 270/100 ps
5602 12:32:52.675769 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5603 12:32:52.679670 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5604 12:32:52.686261 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5605 12:32:52.688857 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5606 12:32:52.692252 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5607 12:32:52.695939 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5608 12:32:52.696021
5609 12:32:52.699257 CA PerBit enable=1, Macro0, CA PI delay=33
5610 12:32:52.699384
5611 12:32:52.702539 [CBTSetCACLKResult] CA Dly = 33
5612 12:32:52.702636 CS Dly: 4 (0~35)
5613 12:32:52.705960 ==
5614 12:32:52.706043 Dram Type= 6, Freq= 0, CH_1, rank 1
5615 12:32:52.712625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 12:32:52.712707 ==
5617 12:32:52.715784 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5618 12:32:52.722408 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5619 12:32:52.726079 [CA 0] Center 36 (6~67) winsize 62
5620 12:32:52.729333 [CA 1] Center 36 (6~67) winsize 62
5621 12:32:52.732600 [CA 2] Center 33 (3~64) winsize 62
5622 12:32:52.735913 [CA 3] Center 33 (3~64) winsize 62
5623 12:32:52.739111 [CA 4] Center 33 (3~64) winsize 62
5624 12:32:52.742434 [CA 5] Center 33 (3~63) winsize 61
5625 12:32:52.742517
5626 12:32:52.745578 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5627 12:32:52.745660
5628 12:32:52.748883 [CATrainingPosCal] consider 2 rank data
5629 12:32:52.752683 u2DelayCellTimex100 = 270/100 ps
5630 12:32:52.755780 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5631 12:32:52.762279 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5632 12:32:52.765686 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5633 12:32:52.768929 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5634 12:32:52.772085 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5635 12:32:52.775572 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5636 12:32:52.775655
5637 12:32:52.778783 CA PerBit enable=1, Macro0, CA PI delay=33
5638 12:32:52.778865
5639 12:32:52.782185 [CBTSetCACLKResult] CA Dly = 33
5640 12:32:52.785340 CS Dly: 5 (0~38)
5641 12:32:52.785425
5642 12:32:52.788753 ----->DramcWriteLeveling(PI) begin...
5643 12:32:52.788838 ==
5644 12:32:52.792070 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 12:32:52.795362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 12:32:52.795458 ==
5647 12:32:52.798562 Write leveling (Byte 0): 28 => 28
5648 12:32:52.801761 Write leveling (Byte 1): 29 => 29
5649 12:32:52.805038 DramcWriteLeveling(PI) end<-----
5650 12:32:52.805120
5651 12:32:52.805186 ==
5652 12:32:52.808970 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 12:32:52.811661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 12:32:52.811797 ==
5655 12:32:52.815039 [Gating] SW mode calibration
5656 12:32:52.822175 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5657 12:32:52.828396 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5658 12:32:52.831606 0 14 0 | B1->B0 | 3131 3030 | 0 1 | (0 0) (1 1)
5659 12:32:52.835286 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5660 12:32:52.841712 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5661 12:32:52.845131 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5662 12:32:52.848339 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5663 12:32:52.854837 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5664 12:32:52.858515 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 12:32:52.861930 0 14 28 | B1->B0 | 3131 3131 | 0 0 | (0 1) (0 1)
5666 12:32:52.868550 0 15 0 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
5667 12:32:52.871257 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5668 12:32:52.874573 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5669 12:32:52.881146 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5670 12:32:52.884467 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5671 12:32:52.888357 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 12:32:52.894970 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 12:32:52.898261 0 15 28 | B1->B0 | 2d2d 2727 | 0 0 | (0 0) (0 0)
5674 12:32:52.901476 1 0 0 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
5675 12:32:52.907910 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 12:32:52.911105 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5677 12:32:52.914505 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 12:32:52.921237 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 12:32:52.924556 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 12:32:52.927921 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 12:32:52.934146 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5682 12:32:52.937420 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 12:32:52.941100 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 12:32:52.947749 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 12:32:52.951001 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 12:32:52.954274 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 12:32:52.960670 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 12:32:52.963789 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 12:32:52.967127 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 12:32:52.974396 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 12:32:52.977108 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 12:32:52.980409 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 12:32:52.986801 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 12:32:52.990722 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 12:32:52.993454 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 12:32:53.000748 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 12:32:53.003970 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5698 12:32:53.007212 Total UI for P1: 0, mck2ui 16
5699 12:32:53.010499 best dqsien dly found for B0: ( 1, 2, 26)
5700 12:32:53.013532 Total UI for P1: 0, mck2ui 16
5701 12:32:53.016963 best dqsien dly found for B1: ( 1, 2, 26)
5702 12:32:53.020309 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5703 12:32:53.023576 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5704 12:32:53.023659
5705 12:32:53.026940 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5706 12:32:53.030286 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5707 12:32:53.033700 [Gating] SW calibration Done
5708 12:32:53.033836 ==
5709 12:32:53.036968 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 12:32:53.040248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 12:32:53.040332 ==
5712 12:32:53.043371 RX Vref Scan: 0
5713 12:32:53.043496
5714 12:32:53.046397 RX Vref 0 -> 0, step: 1
5715 12:32:53.046480
5716 12:32:53.046546 RX Delay -80 -> 252, step: 8
5717 12:32:53.053711 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5718 12:32:53.056360 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5719 12:32:53.060330 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5720 12:32:53.063444 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5721 12:32:53.066561 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5722 12:32:53.069697 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5723 12:32:53.076400 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5724 12:32:53.079744 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5725 12:32:53.083489 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5726 12:32:53.086231 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5727 12:32:53.090172 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5728 12:32:53.096706 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5729 12:32:53.100031 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5730 12:32:53.103307 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5731 12:32:53.106668 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5732 12:32:53.109863 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5733 12:32:53.109947 ==
5734 12:32:53.112652 Dram Type= 6, Freq= 0, CH_1, rank 0
5735 12:32:53.119667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 12:32:53.119751 ==
5737 12:32:53.119827 DQS Delay:
5738 12:32:53.122844 DQS0 = 0, DQS1 = 0
5739 12:32:53.122927 DQM Delay:
5740 12:32:53.122992 DQM0 = 95, DQM1 = 89
5741 12:32:53.126178 DQ Delay:
5742 12:32:53.129487 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5743 12:32:53.132464 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5744 12:32:53.136486 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5745 12:32:53.139767 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5746 12:32:53.139850
5747 12:32:53.139914
5748 12:32:53.139972 ==
5749 12:32:53.142869 Dram Type= 6, Freq= 0, CH_1, rank 0
5750 12:32:53.146100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 12:32:53.146183 ==
5752 12:32:53.146247
5753 12:32:53.146306
5754 12:32:53.149275 TX Vref Scan disable
5755 12:32:53.152528 == TX Byte 0 ==
5756 12:32:53.156405 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5757 12:32:53.159131 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5758 12:32:53.162420 == TX Byte 1 ==
5759 12:32:53.165796 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5760 12:32:53.169479 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5761 12:32:53.169564 ==
5762 12:32:53.172675 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 12:32:53.175956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 12:32:53.176039 ==
5765 12:32:53.179144
5766 12:32:53.179251
5767 12:32:53.179379 TX Vref Scan disable
5768 12:32:53.182426 == TX Byte 0 ==
5769 12:32:53.185804 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5770 12:32:53.192285 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5771 12:32:53.192368 == TX Byte 1 ==
5772 12:32:53.195570 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5773 12:32:53.202371 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5774 12:32:53.202453
5775 12:32:53.202529 [DATLAT]
5776 12:32:53.202591 Freq=933, CH1 RK0
5777 12:32:53.202649
5778 12:32:53.205458 DATLAT Default: 0xd
5779 12:32:53.205540 0, 0xFFFF, sum = 0
5780 12:32:53.208701 1, 0xFFFF, sum = 0
5781 12:32:53.212025 2, 0xFFFF, sum = 0
5782 12:32:53.212108 3, 0xFFFF, sum = 0
5783 12:32:53.215938 4, 0xFFFF, sum = 0
5784 12:32:53.216021 5, 0xFFFF, sum = 0
5785 12:32:53.219154 6, 0xFFFF, sum = 0
5786 12:32:53.219237 7, 0xFFFF, sum = 0
5787 12:32:53.222566 8, 0xFFFF, sum = 0
5788 12:32:53.222665 9, 0xFFFF, sum = 0
5789 12:32:53.225673 10, 0x0, sum = 1
5790 12:32:53.225756 11, 0x0, sum = 2
5791 12:32:53.229054 12, 0x0, sum = 3
5792 12:32:53.229137 13, 0x0, sum = 4
5793 12:32:53.229203 best_step = 11
5794 12:32:53.229264
5795 12:32:53.232216 ==
5796 12:32:53.235427 Dram Type= 6, Freq= 0, CH_1, rank 0
5797 12:32:53.238646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 12:32:53.238731 ==
5799 12:32:53.238796 RX Vref Scan: 1
5800 12:32:53.238856
5801 12:32:53.242007 RX Vref 0 -> 0, step: 1
5802 12:32:53.242089
5803 12:32:53.245198 RX Delay -61 -> 252, step: 4
5804 12:32:53.245289
5805 12:32:53.249118 Set Vref, RX VrefLevel [Byte0]: 53
5806 12:32:53.252248 [Byte1]: 51
5807 12:32:53.252330
5808 12:32:53.255451 Final RX Vref Byte 0 = 53 to rank0
5809 12:32:53.258641 Final RX Vref Byte 1 = 51 to rank0
5810 12:32:53.261774 Final RX Vref Byte 0 = 53 to rank1
5811 12:32:53.265141 Final RX Vref Byte 1 = 51 to rank1==
5812 12:32:53.268509 Dram Type= 6, Freq= 0, CH_1, rank 0
5813 12:32:53.271840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 12:32:53.275682 ==
5815 12:32:53.275769 DQS Delay:
5816 12:32:53.275853 DQS0 = 0, DQS1 = 0
5817 12:32:53.278801 DQM Delay:
5818 12:32:53.278905 DQM0 = 98, DQM1 = 90
5819 12:32:53.282244 DQ Delay:
5820 12:32:53.282354 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =98
5821 12:32:53.285477 DQ4 =98, DQ5 =108, DQ6 =108, DQ7 =92
5822 12:32:53.288809 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =88
5823 12:32:53.292004 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =94
5824 12:32:53.295257
5825 12:32:53.295339
5826 12:32:53.301861 [DQSOSCAuto] RK0, (LSB)MR18= 0x13f0, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5827 12:32:53.305302 CH1 RK0: MR19=504, MR18=13F0
5828 12:32:53.311799 CH1_RK0: MR19=0x504, MR18=0x13F0, DQSOSC=415, MR23=63, INC=62, DEC=41
5829 12:32:53.311886
5830 12:32:53.315186 ----->DramcWriteLeveling(PI) begin...
5831 12:32:53.315288 ==
5832 12:32:53.318349 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 12:32:53.321819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 12:32:53.321922 ==
5835 12:32:53.324961 Write leveling (Byte 0): 26 => 26
5836 12:32:53.328668 Write leveling (Byte 1): 28 => 28
5837 12:32:53.331991 DramcWriteLeveling(PI) end<-----
5838 12:32:53.332066
5839 12:32:53.332129 ==
5840 12:32:53.335184 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 12:32:53.338583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 12:32:53.338671 ==
5843 12:32:53.341721 [Gating] SW mode calibration
5844 12:32:53.348254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5845 12:32:53.354778 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5846 12:32:53.358479 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5847 12:32:53.361523 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5848 12:32:53.367876 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5849 12:32:53.371784 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5850 12:32:53.375017 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5851 12:32:53.381671 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5852 12:32:53.384898 0 14 24 | B1->B0 | 3030 2e2e | 0 0 | (0 1) (0 0)
5853 12:32:53.388292 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5854 12:32:53.394822 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5855 12:32:53.398218 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5856 12:32:53.401485 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5857 12:32:53.408145 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5858 12:32:53.411272 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5859 12:32:53.414678 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5860 12:32:53.421390 0 15 24 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
5861 12:32:53.424554 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5862 12:32:53.427955 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 12:32:53.434440 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 12:32:53.438298 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5865 12:32:53.441581 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5866 12:32:53.447893 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 12:32:53.451199 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 12:32:53.454483 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5869 12:32:53.460859 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5870 12:32:53.464631 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 12:32:53.467875 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 12:32:53.474847 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 12:32:53.477571 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 12:32:53.480890 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 12:32:53.488159 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 12:32:53.491307 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 12:32:53.494555 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 12:32:53.497713 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 12:32:53.504229 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 12:32:53.507505 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 12:32:53.510803 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 12:32:53.517410 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 12:32:53.520863 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5884 12:32:53.524112 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5885 12:32:53.530870 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5886 12:32:53.534155 Total UI for P1: 0, mck2ui 16
5887 12:32:53.537435 best dqsien dly found for B0: ( 1, 2, 22)
5888 12:32:53.540615 Total UI for P1: 0, mck2ui 16
5889 12:32:53.544029 best dqsien dly found for B1: ( 1, 2, 26)
5890 12:32:53.547867 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5891 12:32:53.551041 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5892 12:32:53.551142
5893 12:32:53.554442 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5894 12:32:53.557705 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5895 12:32:53.560816 [Gating] SW calibration Done
5896 12:32:53.560900 ==
5897 12:32:53.563936 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 12:32:53.567196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 12:32:53.567281 ==
5900 12:32:53.570930 RX Vref Scan: 0
5901 12:32:53.571014
5902 12:32:53.571080 RX Vref 0 -> 0, step: 1
5903 12:32:53.571141
5904 12:32:53.574130 RX Delay -80 -> 252, step: 8
5905 12:32:53.577404 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5906 12:32:53.583945 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5907 12:32:53.587803 iDelay=200, Bit 2, Center 83 (-16 ~ 183) 200
5908 12:32:53.591030 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5909 12:32:53.594094 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5910 12:32:53.597267 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5911 12:32:53.600532 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5912 12:32:53.607102 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5913 12:32:53.610405 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5914 12:32:53.613828 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5915 12:32:53.617070 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5916 12:32:53.620392 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5917 12:32:53.627305 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5918 12:32:53.630783 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5919 12:32:53.633910 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5920 12:32:53.637357 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5921 12:32:53.637441 ==
5922 12:32:53.640621 Dram Type= 6, Freq= 0, CH_1, rank 1
5923 12:32:53.643830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5924 12:32:53.647034 ==
5925 12:32:53.647160 DQS Delay:
5926 12:32:53.647226 DQS0 = 0, DQS1 = 0
5927 12:32:53.650126 DQM Delay:
5928 12:32:53.650210 DQM0 = 94, DQM1 = 88
5929 12:32:53.653348 DQ Delay:
5930 12:32:53.653448 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =95
5931 12:32:53.656684 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5932 12:32:53.660032 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5933 12:32:53.666536 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5934 12:32:53.666621
5935 12:32:53.666687
5936 12:32:53.666751 ==
5937 12:32:53.669776 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 12:32:53.673625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 12:32:53.673710 ==
5940 12:32:53.673777
5941 12:32:53.673836
5942 12:32:53.676523 TX Vref Scan disable
5943 12:32:53.676608 == TX Byte 0 ==
5944 12:32:53.683237 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5945 12:32:53.686463 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5946 12:32:53.686549 == TX Byte 1 ==
5947 12:32:53.693181 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5948 12:32:53.696828 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5949 12:32:53.696937 ==
5950 12:32:53.699917 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 12:32:53.703307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 12:32:53.703410 ==
5953 12:32:53.703479
5954 12:32:53.703541
5955 12:32:53.706554 TX Vref Scan disable
5956 12:32:53.709883 == TX Byte 0 ==
5957 12:32:53.713189 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5958 12:32:53.716282 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5959 12:32:53.719561 == TX Byte 1 ==
5960 12:32:53.722888 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5961 12:32:53.726934 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5962 12:32:53.727084
5963 12:32:53.730175 [DATLAT]
5964 12:32:53.730308 Freq=933, CH1 RK1
5965 12:32:53.730427
5966 12:32:53.732855 DATLAT Default: 0xb
5967 12:32:53.732940 0, 0xFFFF, sum = 0
5968 12:32:53.736131 1, 0xFFFF, sum = 0
5969 12:32:53.736228 2, 0xFFFF, sum = 0
5970 12:32:53.740109 3, 0xFFFF, sum = 0
5971 12:32:53.740196 4, 0xFFFF, sum = 0
5972 12:32:53.743205 5, 0xFFFF, sum = 0
5973 12:32:53.743294 6, 0xFFFF, sum = 0
5974 12:32:53.746561 7, 0xFFFF, sum = 0
5975 12:32:53.746650 8, 0xFFFF, sum = 0
5976 12:32:53.749648 9, 0xFFFF, sum = 0
5977 12:32:53.749735 10, 0x0, sum = 1
5978 12:32:53.752882 11, 0x0, sum = 2
5979 12:32:53.752968 12, 0x0, sum = 3
5980 12:32:53.756633 13, 0x0, sum = 4
5981 12:32:53.756733 best_step = 11
5982 12:32:53.756801
5983 12:32:53.756864 ==
5984 12:32:53.759975 Dram Type= 6, Freq= 0, CH_1, rank 1
5985 12:32:53.766655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5986 12:32:53.766755 ==
5987 12:32:53.766823 RX Vref Scan: 0
5988 12:32:53.766885
5989 12:32:53.769791 RX Vref 0 -> 0, step: 1
5990 12:32:53.769876
5991 12:32:53.772936 RX Delay -61 -> 252, step: 4
5992 12:32:53.776170 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5993 12:32:53.779337 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5994 12:32:53.786619 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5995 12:32:53.789838 iDelay=199, Bit 3, Center 90 (-1 ~ 182) 184
5996 12:32:53.793109 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5997 12:32:53.796449 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5998 12:32:53.799609 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5999 12:32:53.802890 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
6000 12:32:53.809261 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
6001 12:32:53.812571 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
6002 12:32:53.815841 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
6003 12:32:53.819687 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
6004 12:32:53.822402 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
6005 12:32:53.828970 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
6006 12:32:53.832321 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
6007 12:32:53.835652 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
6008 12:32:53.835745 ==
6009 12:32:53.839392 Dram Type= 6, Freq= 0, CH_1, rank 1
6010 12:32:53.842710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6011 12:32:53.842796 ==
6012 12:32:53.846088 DQS Delay:
6013 12:32:53.846189 DQS0 = 0, DQS1 = 0
6014 12:32:53.848769 DQM Delay:
6015 12:32:53.848854 DQM0 = 94, DQM1 = 90
6016 12:32:53.848919 DQ Delay:
6017 12:32:53.852520 DQ0 =96, DQ1 =90, DQ2 =84, DQ3 =90
6018 12:32:53.855805 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =90
6019 12:32:53.858841 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
6020 12:32:53.862162 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
6021 12:32:53.862247
6022 12:32:53.862313
6023 12:32:53.872540 [DQSOSCAuto] RK1, (LSB)MR18= 0xd16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
6024 12:32:53.875702 CH1 RK1: MR19=505, MR18=D16
6025 12:32:53.878948 CH1_RK1: MR19=0x505, MR18=0xD16, DQSOSC=414, MR23=63, INC=63, DEC=42
6026 12:32:53.882684 [RxdqsGatingPostProcess] freq 933
6027 12:32:53.889049 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6028 12:32:53.892423 best DQS0 dly(2T, 0.5T) = (0, 10)
6029 12:32:53.895738 best DQS1 dly(2T, 0.5T) = (0, 10)
6030 12:32:53.899047 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6031 12:32:53.902220 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6032 12:32:53.905403 best DQS0 dly(2T, 0.5T) = (0, 10)
6033 12:32:53.909221 best DQS1 dly(2T, 0.5T) = (0, 10)
6034 12:32:53.912594 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6035 12:32:53.915184 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6036 12:32:53.919128 Pre-setting of DQS Precalculation
6037 12:32:53.922392 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6038 12:32:53.928946 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6039 12:32:53.935645 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6040 12:32:53.935733
6041 12:32:53.935801
6042 12:32:53.938420 [Calibration Summary] 1866 Mbps
6043 12:32:53.942146 CH 0, Rank 0
6044 12:32:53.942230 SW Impedance : PASS
6045 12:32:53.945413 DUTY Scan : NO K
6046 12:32:53.948708 ZQ Calibration : PASS
6047 12:32:53.948796 Jitter Meter : NO K
6048 12:32:53.952033 CBT Training : PASS
6049 12:32:53.955256 Write leveling : PASS
6050 12:32:53.955410 RX DQS gating : PASS
6051 12:32:53.958315 RX DQ/DQS(RDDQC) : PASS
6052 12:32:53.962229 TX DQ/DQS : PASS
6053 12:32:53.962338 RX DATLAT : PASS
6054 12:32:53.965188 RX DQ/DQS(Engine): PASS
6055 12:32:53.965298 TX OE : NO K
6056 12:32:53.968497 All Pass.
6057 12:32:53.968577
6058 12:32:53.968660 CH 0, Rank 1
6059 12:32:53.971860 SW Impedance : PASS
6060 12:32:53.971940 DUTY Scan : NO K
6061 12:32:53.975201 ZQ Calibration : PASS
6062 12:32:53.978568 Jitter Meter : NO K
6063 12:32:53.978658 CBT Training : PASS
6064 12:32:53.981702 Write leveling : PASS
6065 12:32:53.985418 RX DQS gating : PASS
6066 12:32:53.985501 RX DQ/DQS(RDDQC) : PASS
6067 12:32:53.988682 TX DQ/DQS : PASS
6068 12:32:53.991940 RX DATLAT : PASS
6069 12:32:53.992027 RX DQ/DQS(Engine): PASS
6070 12:32:53.995135 TX OE : NO K
6071 12:32:53.995249 All Pass.
6072 12:32:53.995467
6073 12:32:53.998448 CH 1, Rank 0
6074 12:32:53.998531 SW Impedance : PASS
6075 12:32:54.001767 DUTY Scan : NO K
6076 12:32:54.005112 ZQ Calibration : PASS
6077 12:32:54.005185 Jitter Meter : NO K
6078 12:32:54.008176 CBT Training : PASS
6079 12:32:54.011932 Write leveling : PASS
6080 12:32:54.012009 RX DQS gating : PASS
6081 12:32:54.015006 RX DQ/DQS(RDDQC) : PASS
6082 12:32:54.018437 TX DQ/DQS : PASS
6083 12:32:54.018515 RX DATLAT : PASS
6084 12:32:54.021582 RX DQ/DQS(Engine): PASS
6085 12:32:54.021666 TX OE : NO K
6086 12:32:54.024875 All Pass.
6087 12:32:54.024958
6088 12:32:54.025023 CH 1, Rank 1
6089 12:32:54.028090 SW Impedance : PASS
6090 12:32:54.028173 DUTY Scan : NO K
6091 12:32:54.031287 ZQ Calibration : PASS
6092 12:32:54.034718 Jitter Meter : NO K
6093 12:32:54.034811 CBT Training : PASS
6094 12:32:54.038031 Write leveling : PASS
6095 12:32:54.041246 RX DQS gating : PASS
6096 12:32:54.041330 RX DQ/DQS(RDDQC) : PASS
6097 12:32:54.045032 TX DQ/DQS : PASS
6098 12:32:54.048419 RX DATLAT : PASS
6099 12:32:54.048491 RX DQ/DQS(Engine): PASS
6100 12:32:54.051782 TX OE : NO K
6101 12:32:54.051866 All Pass.
6102 12:32:54.051931
6103 12:32:54.054944 DramC Write-DBI off
6104 12:32:54.058340 PER_BANK_REFRESH: Hybrid Mode
6105 12:32:54.058424 TX_TRACKING: ON
6106 12:32:54.067864 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6107 12:32:54.071641 [FAST_K] Save calibration result to emmc
6108 12:32:54.074956 dramc_set_vcore_voltage set vcore to 650000
6109 12:32:54.078234 Read voltage for 400, 6
6110 12:32:54.078332 Vio18 = 0
6111 12:32:54.078399 Vcore = 650000
6112 12:32:54.081540 Vdram = 0
6113 12:32:54.081623 Vddq = 0
6114 12:32:54.081699 Vmddr = 0
6115 12:32:54.087872 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6116 12:32:54.091076 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6117 12:32:54.094799 MEM_TYPE=3, freq_sel=20
6118 12:32:54.098064 sv_algorithm_assistance_LP4_800
6119 12:32:54.101188 ============ PULL DRAM RESETB DOWN ============
6120 12:32:54.104473 ========== PULL DRAM RESETB DOWN end =========
6121 12:32:54.111139 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6122 12:32:54.114346 ===================================
6123 12:32:54.114432 LPDDR4 DRAM CONFIGURATION
6124 12:32:54.117654 ===================================
6125 12:32:54.121356 EX_ROW_EN[0] = 0x0
6126 12:32:54.124608 EX_ROW_EN[1] = 0x0
6127 12:32:54.124726 LP4Y_EN = 0x0
6128 12:32:54.127905 WORK_FSP = 0x0
6129 12:32:54.128045 WL = 0x2
6130 12:32:54.131324 RL = 0x2
6131 12:32:54.131439 BL = 0x2
6132 12:32:54.134792 RPST = 0x0
6133 12:32:54.134884 RD_PRE = 0x0
6134 12:32:54.138050 WR_PRE = 0x1
6135 12:32:54.138165 WR_PST = 0x0
6136 12:32:54.141316 DBI_WR = 0x0
6137 12:32:54.141400 DBI_RD = 0x0
6138 12:32:54.144553 OTF = 0x1
6139 12:32:54.147938 ===================================
6140 12:32:54.151239 ===================================
6141 12:32:54.151356 ANA top config
6142 12:32:54.154554 ===================================
6143 12:32:54.157852 DLL_ASYNC_EN = 0
6144 12:32:54.161020 ALL_SLAVE_EN = 1
6145 12:32:54.164421 NEW_RANK_MODE = 1
6146 12:32:54.164536 DLL_IDLE_MODE = 1
6147 12:32:54.167578 LP45_APHY_COMB_EN = 1
6148 12:32:54.170806 TX_ODT_DIS = 1
6149 12:32:54.174141 NEW_8X_MODE = 1
6150 12:32:54.177461 ===================================
6151 12:32:54.180890 ===================================
6152 12:32:54.184290 data_rate = 800
6153 12:32:54.184428 CKR = 1
6154 12:32:54.187335 DQ_P2S_RATIO = 4
6155 12:32:54.190670 ===================================
6156 12:32:54.194454 CA_P2S_RATIO = 4
6157 12:32:54.197554 DQ_CA_OPEN = 0
6158 12:32:54.200886 DQ_SEMI_OPEN = 1
6159 12:32:54.204110 CA_SEMI_OPEN = 1
6160 12:32:54.204230 CA_FULL_RATE = 0
6161 12:32:54.207299 DQ_CKDIV4_EN = 0
6162 12:32:54.210653 CA_CKDIV4_EN = 1
6163 12:32:54.213989 CA_PREDIV_EN = 0
6164 12:32:54.217232 PH8_DLY = 0
6165 12:32:54.221012 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6166 12:32:54.221126 DQ_AAMCK_DIV = 0
6167 12:32:54.224214 CA_AAMCK_DIV = 0
6168 12:32:54.227529 CA_ADMCK_DIV = 4
6169 12:32:54.230681 DQ_TRACK_CA_EN = 0
6170 12:32:54.234012 CA_PICK = 800
6171 12:32:54.237724 CA_MCKIO = 400
6172 12:32:54.237852 MCKIO_SEMI = 400
6173 12:32:54.241119 PLL_FREQ = 3016
6174 12:32:54.243880 DQ_UI_PI_RATIO = 32
6175 12:32:54.247679 CA_UI_PI_RATIO = 32
6176 12:32:54.251038 ===================================
6177 12:32:54.254410 ===================================
6178 12:32:54.257659 memory_type:LPDDR4
6179 12:32:54.257771 GP_NUM : 10
6180 12:32:54.260912 SRAM_EN : 1
6181 12:32:54.264158 MD32_EN : 0
6182 12:32:54.267327 ===================================
6183 12:32:54.267506 [ANA_INIT] >>>>>>>>>>>>>>
6184 12:32:54.270498 <<<<<< [CONFIGURE PHASE]: ANA_TX
6185 12:32:54.273742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6186 12:32:54.277446 ===================================
6187 12:32:54.280746 data_rate = 800,PCW = 0X7400
6188 12:32:54.283982 ===================================
6189 12:32:54.287298 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6190 12:32:54.293611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6191 12:32:54.303915 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6192 12:32:54.310343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6193 12:32:54.313769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6194 12:32:54.317047 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6195 12:32:54.317180 [ANA_INIT] flow start
6196 12:32:54.320155 [ANA_INIT] PLL >>>>>>>>
6197 12:32:54.323967 [ANA_INIT] PLL <<<<<<<<
6198 12:32:54.324105 [ANA_INIT] MIDPI >>>>>>>>
6199 12:32:54.326990 [ANA_INIT] MIDPI <<<<<<<<
6200 12:32:54.330138 [ANA_INIT] DLL >>>>>>>>
6201 12:32:54.330281 [ANA_INIT] flow end
6202 12:32:54.336715 ============ LP4 DIFF to SE enter ============
6203 12:32:54.340505 ============ LP4 DIFF to SE exit ============
6204 12:32:54.343175 [ANA_INIT] <<<<<<<<<<<<<
6205 12:32:54.346437 [Flow] Enable top DCM control >>>>>
6206 12:32:54.350476 [Flow] Enable top DCM control <<<<<
6207 12:32:54.350581 Enable DLL master slave shuffle
6208 12:32:54.357053 ==============================================================
6209 12:32:54.360254 Gating Mode config
6210 12:32:54.363514 ==============================================================
6211 12:32:54.366795 Config description:
6212 12:32:54.376662 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6213 12:32:54.383122 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6214 12:32:54.386522 SELPH_MODE 0: By rank 1: By Phase
6215 12:32:54.393143 ==============================================================
6216 12:32:54.396445 GAT_TRACK_EN = 0
6217 12:32:54.399720 RX_GATING_MODE = 2
6218 12:32:54.402865 RX_GATING_TRACK_MODE = 2
6219 12:32:54.406060 SELPH_MODE = 1
6220 12:32:54.409162 PICG_EARLY_EN = 1
6221 12:32:54.409268 VALID_LAT_VALUE = 1
6222 12:32:54.415807 ==============================================================
6223 12:32:54.419792 Enter into Gating configuration >>>>
6224 12:32:54.422859 Exit from Gating configuration <<<<
6225 12:32:54.426097 Enter into DVFS_PRE_config >>>>>
6226 12:32:54.436344 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6227 12:32:54.439361 Exit from DVFS_PRE_config <<<<<
6228 12:32:54.442680 Enter into PICG configuration >>>>
6229 12:32:54.445898 Exit from PICG configuration <<<<
6230 12:32:54.449322 [RX_INPUT] configuration >>>>>
6231 12:32:54.452685 [RX_INPUT] configuration <<<<<
6232 12:32:54.455973 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6233 12:32:54.463026 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6234 12:32:54.469554 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6235 12:32:54.475965 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6236 12:32:54.482519 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6237 12:32:54.485694 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6238 12:32:54.493018 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6239 12:32:54.496114 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6240 12:32:54.499482 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6241 12:32:54.502664 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6242 12:32:54.508947 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6243 12:32:54.512263 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6244 12:32:54.515848 ===================================
6245 12:32:54.518994 LPDDR4 DRAM CONFIGURATION
6246 12:32:54.522394 ===================================
6247 12:32:54.522512 EX_ROW_EN[0] = 0x0
6248 12:32:54.525739 EX_ROW_EN[1] = 0x0
6249 12:32:54.525894 LP4Y_EN = 0x0
6250 12:32:54.528982 WORK_FSP = 0x0
6251 12:32:54.529130 WL = 0x2
6252 12:32:54.532609 RL = 0x2
6253 12:32:54.532712 BL = 0x2
6254 12:32:54.535696 RPST = 0x0
6255 12:32:54.538865 RD_PRE = 0x0
6256 12:32:54.538962 WR_PRE = 0x1
6257 12:32:54.542754 WR_PST = 0x0
6258 12:32:54.542854 DBI_WR = 0x0
6259 12:32:54.545999 DBI_RD = 0x0
6260 12:32:54.546098 OTF = 0x1
6261 12:32:54.549283 ===================================
6262 12:32:54.552588 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6263 12:32:54.555850 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6264 12:32:54.562364 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6265 12:32:54.565804 ===================================
6266 12:32:54.568929 LPDDR4 DRAM CONFIGURATION
6267 12:32:54.572263 ===================================
6268 12:32:54.572368 EX_ROW_EN[0] = 0x10
6269 12:32:54.575544 EX_ROW_EN[1] = 0x0
6270 12:32:54.575632 LP4Y_EN = 0x0
6271 12:32:54.578763 WORK_FSP = 0x0
6272 12:32:54.578850 WL = 0x2
6273 12:32:54.582741 RL = 0x2
6274 12:32:54.582841 BL = 0x2
6275 12:32:54.585365 RPST = 0x0
6276 12:32:54.585457 RD_PRE = 0x0
6277 12:32:54.589179 WR_PRE = 0x1
6278 12:32:54.589280 WR_PST = 0x0
6279 12:32:54.592320 DBI_WR = 0x0
6280 12:32:54.592437 DBI_RD = 0x0
6281 12:32:54.595571 OTF = 0x1
6282 12:32:54.598828 ===================================
6283 12:32:54.605559 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6284 12:32:54.608781 nWR fixed to 30
6285 12:32:54.611909 [ModeRegInit_LP4] CH0 RK0
6286 12:32:54.612046 [ModeRegInit_LP4] CH0 RK1
6287 12:32:54.615709 [ModeRegInit_LP4] CH1 RK0
6288 12:32:54.618944 [ModeRegInit_LP4] CH1 RK1
6289 12:32:54.619047 match AC timing 19
6290 12:32:54.625489 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6291 12:32:54.628790 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6292 12:32:54.631998 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6293 12:32:54.638450 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6294 12:32:54.642185 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6295 12:32:54.642315 ==
6296 12:32:54.645313 Dram Type= 6, Freq= 0, CH_0, rank 0
6297 12:32:54.648575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 12:32:54.648673 ==
6299 12:32:54.655569 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6300 12:32:54.662088 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6301 12:32:54.665505 [CA 0] Center 36 (8~64) winsize 57
6302 12:32:54.668865 [CA 1] Center 36 (8~64) winsize 57
6303 12:32:54.672222 [CA 2] Center 36 (8~64) winsize 57
6304 12:32:54.672310 [CA 3] Center 36 (8~64) winsize 57
6305 12:32:54.675542 [CA 4] Center 36 (8~64) winsize 57
6306 12:32:54.678884 [CA 5] Center 36 (8~64) winsize 57
6307 12:32:54.678981
6308 12:32:54.685137 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6309 12:32:54.685252
6310 12:32:54.688414 [CATrainingPosCal] consider 1 rank data
6311 12:32:54.691687 u2DelayCellTimex100 = 270/100 ps
6312 12:32:54.694940 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 12:32:54.698296 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 12:32:54.701501 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 12:32:54.705526 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 12:32:54.708700 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 12:32:54.712027 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 12:32:54.712152
6319 12:32:54.715127 CA PerBit enable=1, Macro0, CA PI delay=36
6320 12:32:54.715236
6321 12:32:54.718394 [CBTSetCACLKResult] CA Dly = 36
6322 12:32:54.721608 CS Dly: 1 (0~32)
6323 12:32:54.721734 ==
6324 12:32:54.725443 Dram Type= 6, Freq= 0, CH_0, rank 1
6325 12:32:54.728676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 12:32:54.728768 ==
6327 12:32:54.735000 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6328 12:32:54.738432 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6329 12:32:54.741839 [CA 0] Center 36 (8~64) winsize 57
6330 12:32:54.744985 [CA 1] Center 36 (8~64) winsize 57
6331 12:32:54.748001 [CA 2] Center 36 (8~64) winsize 57
6332 12:32:54.751851 [CA 3] Center 36 (8~64) winsize 57
6333 12:32:54.754962 [CA 4] Center 36 (8~64) winsize 57
6334 12:32:54.758029 [CA 5] Center 36 (8~64) winsize 57
6335 12:32:54.758155
6336 12:32:54.761414 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6337 12:32:54.761526
6338 12:32:54.764668 [CATrainingPosCal] consider 2 rank data
6339 12:32:54.767993 u2DelayCellTimex100 = 270/100 ps
6340 12:32:54.771304 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 12:32:54.774456 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 12:32:54.781189 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6343 12:32:54.785004 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6344 12:32:54.788200 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6345 12:32:54.791550 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 12:32:54.791659
6347 12:32:54.794876 CA PerBit enable=1, Macro0, CA PI delay=36
6348 12:32:54.794998
6349 12:32:54.798102 [CBTSetCACLKResult] CA Dly = 36
6350 12:32:54.798224 CS Dly: 1 (0~32)
6351 12:32:54.798321
6352 12:32:54.801326 ----->DramcWriteLeveling(PI) begin...
6353 12:32:54.801431 ==
6354 12:32:54.804632 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 12:32:54.811126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 12:32:54.811284 ==
6357 12:32:54.814402 Write leveling (Byte 0): 40 => 8
6358 12:32:54.818347 Write leveling (Byte 1): 32 => 0
6359 12:32:54.818450 DramcWriteLeveling(PI) end<-----
6360 12:32:54.821478
6361 12:32:54.821569 ==
6362 12:32:54.824744 Dram Type= 6, Freq= 0, CH_0, rank 0
6363 12:32:54.827996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6364 12:32:54.828141 ==
6365 12:32:54.831181 [Gating] SW mode calibration
6366 12:32:54.837894 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6367 12:32:54.841161 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6368 12:32:54.847554 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6369 12:32:54.851379 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6370 12:32:54.854485 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6371 12:32:54.860683 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6372 12:32:54.864155 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6373 12:32:54.867438 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6374 12:32:54.873893 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6375 12:32:54.877160 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6376 12:32:54.880373 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6377 12:32:54.883814 Total UI for P1: 0, mck2ui 16
6378 12:32:54.887651 best dqsien dly found for B0: ( 0, 14, 24)
6379 12:32:54.890827 Total UI for P1: 0, mck2ui 16
6380 12:32:54.894016 best dqsien dly found for B1: ( 0, 14, 24)
6381 12:32:54.897358 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6382 12:32:54.903727 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6383 12:32:54.903863
6384 12:32:54.906919 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6385 12:32:54.910333 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6386 12:32:54.913572 [Gating] SW calibration Done
6387 12:32:54.913694 ==
6388 12:32:54.916796 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 12:32:54.920206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 12:32:54.920319 ==
6391 12:32:54.923798 RX Vref Scan: 0
6392 12:32:54.923899
6393 12:32:54.923965 RX Vref 0 -> 0, step: 1
6394 12:32:54.924027
6395 12:32:54.926951 RX Delay -410 -> 252, step: 16
6396 12:32:54.930802 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6397 12:32:54.937244 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6398 12:32:54.940440 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6399 12:32:54.943869 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6400 12:32:54.947255 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6401 12:32:54.953707 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6402 12:32:54.956850 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6403 12:32:54.960188 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6404 12:32:54.963751 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6405 12:32:54.970452 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6406 12:32:54.973833 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6407 12:32:54.976940 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6408 12:32:54.980317 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6409 12:32:54.986777 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6410 12:32:54.990650 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6411 12:32:54.993351 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6412 12:32:54.993478 ==
6413 12:32:54.996721 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 12:32:55.003243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 12:32:55.003401 ==
6416 12:32:55.003480 DQS Delay:
6417 12:32:55.007218 DQS0 = 35, DQS1 = 51
6418 12:32:55.007334 DQM Delay:
6419 12:32:55.007424 DQM0 = 5, DQM1 = 10
6420 12:32:55.010100 DQ Delay:
6421 12:32:55.013544 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6422 12:32:55.013667 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6423 12:32:55.016726 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6424 12:32:55.019967 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6425 12:32:55.020096
6426 12:32:55.020195
6427 12:32:55.023379 ==
6428 12:32:55.026493 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 12:32:55.029688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 12:32:55.029810 ==
6431 12:32:55.029906
6432 12:32:55.029995
6433 12:32:55.032992 TX Vref Scan disable
6434 12:32:55.033101 == TX Byte 0 ==
6435 12:32:55.036798 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6436 12:32:55.043073 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6437 12:32:55.043247 == TX Byte 1 ==
6438 12:32:55.046426 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6439 12:32:55.053100 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6440 12:32:55.053239 ==
6441 12:32:55.056347 Dram Type= 6, Freq= 0, CH_0, rank 0
6442 12:32:55.059526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 12:32:55.059682 ==
6444 12:32:55.059807
6445 12:32:55.059914
6446 12:32:55.062717 TX Vref Scan disable
6447 12:32:55.062867 == TX Byte 0 ==
6448 12:32:55.069761 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6449 12:32:55.073070 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6450 12:32:55.073183 == TX Byte 1 ==
6451 12:32:55.079484 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6452 12:32:55.082870 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6453 12:32:55.082976
6454 12:32:55.083045 [DATLAT]
6455 12:32:55.086007 Freq=400, CH0 RK0
6456 12:32:55.086093
6457 12:32:55.086160 DATLAT Default: 0xf
6458 12:32:55.089270 0, 0xFFFF, sum = 0
6459 12:32:55.089360 1, 0xFFFF, sum = 0
6460 12:32:55.093066 2, 0xFFFF, sum = 0
6461 12:32:55.093156 3, 0xFFFF, sum = 0
6462 12:32:55.096602 4, 0xFFFF, sum = 0
6463 12:32:55.096695 5, 0xFFFF, sum = 0
6464 12:32:55.099894 6, 0xFFFF, sum = 0
6465 12:32:55.099982 7, 0xFFFF, sum = 0
6466 12:32:55.103162 8, 0xFFFF, sum = 0
6467 12:32:55.103247 9, 0xFFFF, sum = 0
6468 12:32:55.106479 10, 0xFFFF, sum = 0
6469 12:32:55.106564 11, 0xFFFF, sum = 0
6470 12:32:55.109734 12, 0xFFFF, sum = 0
6471 12:32:55.109821 13, 0x0, sum = 1
6472 12:32:55.112980 14, 0x0, sum = 2
6473 12:32:55.113075 15, 0x0, sum = 3
6474 12:32:55.116304 16, 0x0, sum = 4
6475 12:32:55.116390 best_step = 14
6476 12:32:55.116456
6477 12:32:55.116516 ==
6478 12:32:55.119539 Dram Type= 6, Freq= 0, CH_0, rank 0
6479 12:32:55.126015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 12:32:55.126120 ==
6481 12:32:55.126193 RX Vref Scan: 1
6482 12:32:55.126257
6483 12:32:55.129532 RX Vref 0 -> 0, step: 1
6484 12:32:55.129644
6485 12:32:55.133247 RX Delay -343 -> 252, step: 8
6486 12:32:55.133350
6487 12:32:55.136421 Set Vref, RX VrefLevel [Byte0]: 53
6488 12:32:55.139672 [Byte1]: 51
6489 12:32:55.139786
6490 12:32:55.142834 Final RX Vref Byte 0 = 53 to rank0
6491 12:32:55.145829 Final RX Vref Byte 1 = 51 to rank0
6492 12:32:55.149839 Final RX Vref Byte 0 = 53 to rank1
6493 12:32:55.153039 Final RX Vref Byte 1 = 51 to rank1==
6494 12:32:55.156293 Dram Type= 6, Freq= 0, CH_0, rank 0
6495 12:32:55.159565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 12:32:55.162877 ==
6497 12:32:55.162962 DQS Delay:
6498 12:32:55.163028 DQS0 = 44, DQS1 = 60
6499 12:32:55.166148 DQM Delay:
6500 12:32:55.166265 DQM0 = 11, DQM1 = 13
6501 12:32:55.169187 DQ Delay:
6502 12:32:55.169274 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6503 12:32:55.172946 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6504 12:32:55.176388 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6505 12:32:55.179616 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6506 12:32:55.179705
6507 12:32:55.179775
6508 12:32:55.189503 [DQSOSCAuto] RK0, (LSB)MR18= 0x7e4b, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
6509 12:32:55.192622 CH0 RK0: MR19=C0C, MR18=7E4B
6510 12:32:55.199174 CH0_RK0: MR19=0xC0C, MR18=0x7E4B, DQSOSC=393, MR23=63, INC=382, DEC=254
6511 12:32:55.199302 ==
6512 12:32:55.202474 Dram Type= 6, Freq= 0, CH_0, rank 1
6513 12:32:55.205770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 12:32:55.205857 ==
6515 12:32:55.209263 [Gating] SW mode calibration
6516 12:32:55.215769 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6517 12:32:55.219012 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6518 12:32:55.225554 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6519 12:32:55.228834 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6520 12:32:55.232268 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6521 12:32:55.239256 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6522 12:32:55.242387 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6523 12:32:55.245472 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6524 12:32:55.252253 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6525 12:32:55.256033 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6526 12:32:55.259381 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6527 12:32:55.262629 Total UI for P1: 0, mck2ui 16
6528 12:32:55.265923 best dqsien dly found for B0: ( 0, 14, 24)
6529 12:32:55.269405 Total UI for P1: 0, mck2ui 16
6530 12:32:55.272511 best dqsien dly found for B1: ( 0, 14, 24)
6531 12:32:55.275485 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6532 12:32:55.278713 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6533 12:32:55.282630
6534 12:32:55.285934 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6535 12:32:55.289057 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6536 12:32:55.292335 [Gating] SW calibration Done
6537 12:32:55.292516 ==
6538 12:32:55.295667 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 12:32:55.298831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 12:32:55.298989 ==
6541 12:32:55.299117 RX Vref Scan: 0
6542 12:32:55.299252
6543 12:32:55.302155 RX Vref 0 -> 0, step: 1
6544 12:32:55.302300
6545 12:32:55.305499 RX Delay -410 -> 252, step: 16
6546 12:32:55.308815 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6547 12:32:55.315512 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6548 12:32:55.318799 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6549 12:32:55.321999 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6550 12:32:55.325388 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6551 12:32:55.331924 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6552 12:32:55.335213 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6553 12:32:55.338454 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6554 12:32:55.341831 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6555 12:32:55.348883 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6556 12:32:55.351977 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6557 12:32:55.355045 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6558 12:32:55.358798 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6559 12:32:55.365109 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6560 12:32:55.368727 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6561 12:32:55.371899 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6562 12:32:55.372058 ==
6563 12:32:55.375165 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 12:32:55.378452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 12:32:55.381696 ==
6566 12:32:55.381852 DQS Delay:
6567 12:32:55.381987 DQS0 = 43, DQS1 = 51
6568 12:32:55.384968 DQM Delay:
6569 12:32:55.385110 DQM0 = 11, DQM1 = 10
6570 12:32:55.388174 DQ Delay:
6571 12:32:55.388329 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6572 12:32:55.392140 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6573 12:32:55.394800 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6574 12:32:55.398129 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6575 12:32:55.398270
6576 12:32:55.398398
6577 12:32:55.401416 ==
6578 12:32:55.401564 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 12:32:55.408643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 12:32:55.408848 ==
6581 12:32:55.408992
6582 12:32:55.409122
6583 12:32:55.411271 TX Vref Scan disable
6584 12:32:55.411455 == TX Byte 0 ==
6585 12:32:55.415272 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6586 12:32:55.418594 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6587 12:32:55.421822 == TX Byte 1 ==
6588 12:32:55.425258 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6589 12:32:55.428450 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6590 12:32:55.431603 ==
6591 12:32:55.434854 Dram Type= 6, Freq= 0, CH_0, rank 1
6592 12:32:55.440261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 12:32:55.440511 ==
6594 12:32:55.440652
6595 12:32:55.440767
6596 12:32:55.441401 TX Vref Scan disable
6597 12:32:55.441525 == TX Byte 0 ==
6598 12:32:55.444894 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6599 12:32:55.451616 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6600 12:32:55.451791 == TX Byte 1 ==
6601 12:32:55.454679 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6602 12:32:55.461491 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6603 12:32:55.461665
6604 12:32:55.461751 [DATLAT]
6605 12:32:55.461815 Freq=400, CH0 RK1
6606 12:32:55.461876
6607 12:32:55.464558 DATLAT Default: 0xe
6608 12:32:55.464672 0, 0xFFFF, sum = 0
6609 12:32:55.467693 1, 0xFFFF, sum = 0
6610 12:32:55.471402 2, 0xFFFF, sum = 0
6611 12:32:55.471546 3, 0xFFFF, sum = 0
6612 12:32:55.474587 4, 0xFFFF, sum = 0
6613 12:32:55.474708 5, 0xFFFF, sum = 0
6614 12:32:55.477774 6, 0xFFFF, sum = 0
6615 12:32:55.477911 7, 0xFFFF, sum = 0
6616 12:32:55.481163 8, 0xFFFF, sum = 0
6617 12:32:55.481272 9, 0xFFFF, sum = 0
6618 12:32:55.484485 10, 0xFFFF, sum = 0
6619 12:32:55.484605 11, 0xFFFF, sum = 0
6620 12:32:55.488190 12, 0xFFFF, sum = 0
6621 12:32:55.488297 13, 0x0, sum = 1
6622 12:32:55.491248 14, 0x0, sum = 2
6623 12:32:55.491360 15, 0x0, sum = 3
6624 12:32:55.494565 16, 0x0, sum = 4
6625 12:32:55.494690 best_step = 14
6626 12:32:55.494789
6627 12:32:55.494882 ==
6628 12:32:55.497845 Dram Type= 6, Freq= 0, CH_0, rank 1
6629 12:32:55.501122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 12:32:55.501214 ==
6631 12:32:55.504491 RX Vref Scan: 0
6632 12:32:55.504580
6633 12:32:55.507800 RX Vref 0 -> 0, step: 1
6634 12:32:55.507930
6635 12:32:55.508031 RX Delay -343 -> 252, step: 8
6636 12:32:55.516448 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6637 12:32:55.520324 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6638 12:32:55.523612 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6639 12:32:55.526977 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6640 12:32:55.533325 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6641 12:32:55.536618 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6642 12:32:55.539927 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6643 12:32:55.543277 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6644 12:32:55.549904 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6645 12:32:55.553272 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6646 12:32:55.556430 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6647 12:32:55.563507 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6648 12:32:55.566587 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6649 12:32:55.569673 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6650 12:32:55.572793 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6651 12:32:55.579627 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6652 12:32:55.579716 ==
6653 12:32:55.582829 Dram Type= 6, Freq= 0, CH_0, rank 1
6654 12:32:55.586166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 12:32:55.586251 ==
6656 12:32:55.586318 DQS Delay:
6657 12:32:55.589410 DQS0 = 48, DQS1 = 60
6658 12:32:55.589495 DQM Delay:
6659 12:32:55.593054 DQM0 = 13, DQM1 = 14
6660 12:32:55.593145 DQ Delay:
6661 12:32:55.596404 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6662 12:32:55.599482 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6663 12:32:55.602813 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =4
6664 12:32:55.606136 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6665 12:32:55.606224
6666 12:32:55.606293
6667 12:32:55.612749 [DQSOSCAuto] RK1, (LSB)MR18= 0x986a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6668 12:32:55.616158 CH0 RK1: MR19=C0C, MR18=986A
6669 12:32:55.622700 CH0_RK1: MR19=0xC0C, MR18=0x986A, DQSOSC=390, MR23=63, INC=388, DEC=258
6670 12:32:55.626027 [RxdqsGatingPostProcess] freq 400
6671 12:32:55.632606 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6672 12:32:55.635940 best DQS0 dly(2T, 0.5T) = (0, 10)
6673 12:32:55.636030 best DQS1 dly(2T, 0.5T) = (0, 10)
6674 12:32:55.639803 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6675 12:32:55.643080 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6676 12:32:55.645787 best DQS0 dly(2T, 0.5T) = (0, 10)
6677 12:32:55.649676 best DQS1 dly(2T, 0.5T) = (0, 10)
6678 12:32:55.652930 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6679 12:32:55.656406 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6680 12:32:55.659564 Pre-setting of DQS Precalculation
6681 12:32:55.666151 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6682 12:32:55.666241 ==
6683 12:32:55.669350 Dram Type= 6, Freq= 0, CH_1, rank 0
6684 12:32:55.672589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 12:32:55.672699 ==
6686 12:32:55.679328 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6687 12:32:55.682441 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6688 12:32:55.686174 [CA 0] Center 36 (8~64) winsize 57
6689 12:32:55.689153 [CA 1] Center 36 (8~64) winsize 57
6690 12:32:55.692657 [CA 2] Center 36 (8~64) winsize 57
6691 12:32:55.695765 [CA 3] Center 36 (8~64) winsize 57
6692 12:32:55.698876 [CA 4] Center 36 (8~64) winsize 57
6693 12:32:55.702791 [CA 5] Center 36 (8~64) winsize 57
6694 12:32:55.702887
6695 12:32:55.706235 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6696 12:32:55.706364
6697 12:32:55.708898 [CATrainingPosCal] consider 1 rank data
6698 12:32:55.712022 u2DelayCellTimex100 = 270/100 ps
6699 12:32:55.716027 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 12:32:55.719290 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 12:32:55.725920 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 12:32:55.729163 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 12:32:55.732425 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 12:32:55.735743 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 12:32:55.735855
6706 12:32:55.739074 CA PerBit enable=1, Macro0, CA PI delay=36
6707 12:32:55.739174
6708 12:32:55.742412 [CBTSetCACLKResult] CA Dly = 36
6709 12:32:55.742501 CS Dly: 1 (0~32)
6710 12:32:55.742606 ==
6711 12:32:55.745750 Dram Type= 6, Freq= 0, CH_1, rank 1
6712 12:32:55.751832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 12:32:55.751920 ==
6714 12:32:55.755655 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6715 12:32:55.762234 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6716 12:32:55.765505 [CA 0] Center 36 (8~64) winsize 57
6717 12:32:55.768775 [CA 1] Center 36 (8~64) winsize 57
6718 12:32:55.772291 [CA 2] Center 36 (8~64) winsize 57
6719 12:32:55.775562 [CA 3] Center 36 (8~64) winsize 57
6720 12:32:55.778768 [CA 4] Center 36 (8~64) winsize 57
6721 12:32:55.781932 [CA 5] Center 36 (8~64) winsize 57
6722 12:32:55.782042
6723 12:32:55.785319 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6724 12:32:55.785405
6725 12:32:55.788313 [CATrainingPosCal] consider 2 rank data
6726 12:32:55.791591 u2DelayCellTimex100 = 270/100 ps
6727 12:32:55.795261 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 12:32:55.798153 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 12:32:55.801593 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 12:32:55.804682 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 12:32:55.811718 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 12:32:55.814928 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 12:32:55.815020
6734 12:32:55.818115 CA PerBit enable=1, Macro0, CA PI delay=36
6735 12:32:55.818227
6736 12:32:55.821509 [CBTSetCACLKResult] CA Dly = 36
6737 12:32:55.821596 CS Dly: 1 (0~32)
6738 12:32:55.821664
6739 12:32:55.824591 ----->DramcWriteLeveling(PI) begin...
6740 12:32:55.824702 ==
6741 12:32:55.827938 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 12:32:55.834835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 12:32:55.834928 ==
6744 12:32:55.838201 Write leveling (Byte 0): 40 => 8
6745 12:32:55.841538 Write leveling (Byte 1): 40 => 8
6746 12:32:55.841629 DramcWriteLeveling(PI) end<-----
6747 12:32:55.841698
6748 12:32:55.844805 ==
6749 12:32:55.847993 Dram Type= 6, Freq= 0, CH_1, rank 0
6750 12:32:55.851143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6751 12:32:55.851256 ==
6752 12:32:55.854469 [Gating] SW mode calibration
6753 12:32:55.860969 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6754 12:32:55.864248 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6755 12:32:55.870870 0 11 0 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
6756 12:32:55.874231 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6757 12:32:55.877428 0 12 0 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
6758 12:32:55.884209 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6759 12:32:55.887479 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6760 12:32:55.890764 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6761 12:32:55.897511 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6762 12:32:55.900746 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6763 12:32:55.904329 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6764 12:32:55.907640 Total UI for P1: 0, mck2ui 16
6765 12:32:55.910669 best dqsien dly found for B0: ( 0, 14, 24)
6766 12:32:55.914085 Total UI for P1: 0, mck2ui 16
6767 12:32:55.917637 best dqsien dly found for B1: ( 0, 14, 24)
6768 12:32:55.920939 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6769 12:32:55.924236 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6770 12:32:55.924380
6771 12:32:55.930880 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6772 12:32:55.934128 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6773 12:32:55.937515 [Gating] SW calibration Done
6774 12:32:55.937783 ==
6775 12:32:55.940945 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 12:32:55.944174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 12:32:55.944584 ==
6778 12:32:55.944948 RX Vref Scan: 0
6779 12:32:55.945319
6780 12:32:55.947259 RX Vref 0 -> 0, step: 1
6781 12:32:55.947738
6782 12:32:55.950593 RX Delay -410 -> 252, step: 16
6783 12:32:55.953852 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6784 12:32:55.960512 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6785 12:32:55.963730 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6786 12:32:55.966914 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6787 12:32:55.970883 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6788 12:32:55.977294 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6789 12:32:55.980538 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6790 12:32:55.983909 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6791 12:32:55.987205 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6792 12:32:55.994003 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6793 12:32:55.997192 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6794 12:32:56.000360 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6795 12:32:56.004039 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6796 12:32:56.010158 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6797 12:32:56.013896 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6798 12:32:56.017252 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6799 12:32:56.017591 ==
6800 12:32:56.020333 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 12:32:56.023495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 12:32:56.026690 ==
6803 12:32:56.027095 DQS Delay:
6804 12:32:56.027499 DQS0 = 51, DQS1 = 59
6805 12:32:56.029959 DQM Delay:
6806 12:32:56.030373 DQM0 = 19, DQM1 = 17
6807 12:32:56.033407 DQ Delay:
6808 12:32:56.037305 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6809 12:32:56.037642 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6810 12:32:56.040007 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6811 12:32:56.043867 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6812 12:32:56.044234
6813 12:32:56.047014
6814 12:32:56.047477 ==
6815 12:32:56.050325 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 12:32:56.053784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 12:32:56.054239 ==
6818 12:32:56.054649
6819 12:32:56.055040
6820 12:32:56.056936 TX Vref Scan disable
6821 12:32:56.057304 == TX Byte 0 ==
6822 12:32:56.060213 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6823 12:32:56.066898 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6824 12:32:56.067336 == TX Byte 1 ==
6825 12:32:56.070110 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6826 12:32:56.076654 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6827 12:32:56.077094 ==
6828 12:32:56.080143 Dram Type= 6, Freq= 0, CH_1, rank 0
6829 12:32:56.083198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 12:32:56.083589 ==
6831 12:32:56.083925
6832 12:32:56.084242
6833 12:32:56.086672 TX Vref Scan disable
6834 12:32:56.087070 == TX Byte 0 ==
6835 12:32:56.090007 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6836 12:32:56.096596 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6837 12:32:56.096942 == TX Byte 1 ==
6838 12:32:56.099975 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6839 12:32:56.106419 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6840 12:32:56.106877
6841 12:32:56.107287 [DATLAT]
6842 12:32:56.107674 Freq=400, CH1 RK0
6843 12:32:56.110152
6844 12:32:56.110526 DATLAT Default: 0xf
6845 12:32:56.113390 0, 0xFFFF, sum = 0
6846 12:32:56.113740 1, 0xFFFF, sum = 0
6847 12:32:56.116360 2, 0xFFFF, sum = 0
6848 12:32:56.116726 3, 0xFFFF, sum = 0
6849 12:32:56.120177 4, 0xFFFF, sum = 0
6850 12:32:56.120628 5, 0xFFFF, sum = 0
6851 12:32:56.123064 6, 0xFFFF, sum = 0
6852 12:32:56.123442 7, 0xFFFF, sum = 0
6853 12:32:56.126188 8, 0xFFFF, sum = 0
6854 12:32:56.126532 9, 0xFFFF, sum = 0
6855 12:32:56.130028 10, 0xFFFF, sum = 0
6856 12:32:56.130369 11, 0xFFFF, sum = 0
6857 12:32:56.133081 12, 0xFFFF, sum = 0
6858 12:32:56.133421 13, 0x0, sum = 1
6859 12:32:56.136221 14, 0x0, sum = 2
6860 12:32:56.136561 15, 0x0, sum = 3
6861 12:32:56.139641 16, 0x0, sum = 4
6862 12:32:56.140002 best_step = 14
6863 12:32:56.140268
6864 12:32:56.140515 ==
6865 12:32:56.142870 Dram Type= 6, Freq= 0, CH_1, rank 0
6866 12:32:56.149472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 12:32:56.149830 ==
6868 12:32:56.150098 RX Vref Scan: 1
6869 12:32:56.150367
6870 12:32:56.152752 RX Vref 0 -> 0, step: 1
6871 12:32:56.153091
6872 12:32:56.156133 RX Delay -359 -> 252, step: 8
6873 12:32:56.156470
6874 12:32:56.160025 Set Vref, RX VrefLevel [Byte0]: 53
6875 12:32:56.163100 [Byte1]: 51
6876 12:32:56.163468
6877 12:32:56.166466 Final RX Vref Byte 0 = 53 to rank0
6878 12:32:56.169634 Final RX Vref Byte 1 = 51 to rank0
6879 12:32:56.172968 Final RX Vref Byte 0 = 53 to rank1
6880 12:32:56.176256 Final RX Vref Byte 1 = 51 to rank1==
6881 12:32:56.179567 Dram Type= 6, Freq= 0, CH_1, rank 0
6882 12:32:56.182934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 12:32:56.186004 ==
6884 12:32:56.186440 DQS Delay:
6885 12:32:56.186814 DQS0 = 48, DQS1 = 60
6886 12:32:56.189323 DQM Delay:
6887 12:32:56.189750 DQM0 = 13, DQM1 = 12
6888 12:32:56.192664 DQ Delay:
6889 12:32:56.193061 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6890 12:32:56.196117 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6891 12:32:56.199285 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6892 12:32:56.202568 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6893 12:32:56.202962
6894 12:32:56.203325
6895 12:32:56.212627 [DQSOSCAuto] RK0, (LSB)MR18= 0x8c33, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6896 12:32:56.215751 CH1 RK0: MR19=C0C, MR18=8C33
6897 12:32:56.222676 CH1_RK0: MR19=0xC0C, MR18=0x8C33, DQSOSC=392, MR23=63, INC=384, DEC=256
6898 12:32:56.223117 ==
6899 12:32:56.225736 Dram Type= 6, Freq= 0, CH_1, rank 1
6900 12:32:56.229268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 12:32:56.229685 ==
6902 12:32:56.232377 [Gating] SW mode calibration
6903 12:32:56.239634 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6904 12:32:56.242758 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6905 12:32:56.249068 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6906 12:32:56.252586 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6907 12:32:56.255882 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6908 12:32:56.262572 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6909 12:32:56.265773 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6910 12:32:56.268766 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6911 12:32:56.275771 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6912 12:32:56.279159 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6913 12:32:56.282463 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6914 12:32:56.285786 Total UI for P1: 0, mck2ui 16
6915 12:32:56.288999 best dqsien dly found for B0: ( 0, 14, 24)
6916 12:32:56.292211 Total UI for P1: 0, mck2ui 16
6917 12:32:56.295451 best dqsien dly found for B1: ( 0, 14, 24)
6918 12:32:56.298797 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6919 12:32:56.302132 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6920 12:32:56.306045
6921 12:32:56.308635 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6922 12:32:56.312014 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6923 12:32:56.315302 [Gating] SW calibration Done
6924 12:32:56.315686 ==
6925 12:32:56.319312 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 12:32:56.322533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 12:32:56.322899 ==
6928 12:32:56.323187 RX Vref Scan: 0
6929 12:32:56.325676
6930 12:32:56.326038 RX Vref 0 -> 0, step: 1
6931 12:32:56.326330
6932 12:32:56.328847 RX Delay -410 -> 252, step: 16
6933 12:32:56.332320 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6934 12:32:56.338306 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6935 12:32:56.341624 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6936 12:32:56.345385 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6937 12:32:56.348442 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6938 12:32:56.355090 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6939 12:32:56.358750 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6940 12:32:56.361852 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6941 12:32:56.365384 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6942 12:32:56.371779 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6943 12:32:56.375829 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6944 12:32:56.378975 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6945 12:32:56.382244 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6946 12:32:56.388202 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6947 12:32:56.392091 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6948 12:32:56.394811 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6949 12:32:56.395186 ==
6950 12:32:56.398654 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 12:32:56.405243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 12:32:56.405622 ==
6953 12:32:56.405997 DQS Delay:
6954 12:32:56.408579 DQS0 = 51, DQS1 = 59
6955 12:32:56.408949 DQM Delay:
6956 12:32:56.409323 DQM0 = 16, DQM1 = 19
6957 12:32:56.411871 DQ Delay:
6958 12:32:56.415402 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6959 12:32:56.418439 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6960 12:32:56.421848 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6961 12:32:56.425041 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6962 12:32:56.425417
6963 12:32:56.425788
6964 12:32:56.426139 ==
6965 12:32:56.428346 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 12:32:56.431553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 12:32:56.431917 ==
6968 12:32:56.432203
6969 12:32:56.432473
6970 12:32:56.434694 TX Vref Scan disable
6971 12:32:56.435058 == TX Byte 0 ==
6972 12:32:56.441515 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6973 12:32:56.444636 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6974 12:32:56.445027 == TX Byte 1 ==
6975 12:32:56.447882 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6976 12:32:56.454707 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6977 12:32:56.455072 ==
6978 12:32:56.458013 Dram Type= 6, Freq= 0, CH_1, rank 1
6979 12:32:56.461238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6980 12:32:56.461626 ==
6981 12:32:56.461918
6982 12:32:56.462187
6983 12:32:56.464451 TX Vref Scan disable
6984 12:32:56.464815 == TX Byte 0 ==
6985 12:32:56.470907 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6986 12:32:56.474289 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6987 12:32:56.474654 == TX Byte 1 ==
6988 12:32:56.481287 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6989 12:32:56.484656 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6990 12:32:56.485022
6991 12:32:56.485310 [DATLAT]
6992 12:32:56.487835 Freq=400, CH1 RK1
6993 12:32:56.488201
6994 12:32:56.488489 DATLAT Default: 0xe
6995 12:32:56.491161 0, 0xFFFF, sum = 0
6996 12:32:56.491566 1, 0xFFFF, sum = 0
6997 12:32:56.494505 2, 0xFFFF, sum = 0
6998 12:32:56.494872 3, 0xFFFF, sum = 0
6999 12:32:56.497634 4, 0xFFFF, sum = 0
7000 12:32:56.498176 5, 0xFFFF, sum = 0
7001 12:32:56.501082 6, 0xFFFF, sum = 0
7002 12:32:56.501672 7, 0xFFFF, sum = 0
7003 12:32:56.504224 8, 0xFFFF, sum = 0
7004 12:32:56.504788 9, 0xFFFF, sum = 0
7005 12:32:56.507525 10, 0xFFFF, sum = 0
7006 12:32:56.508065 11, 0xFFFF, sum = 0
7007 12:32:56.511613 12, 0xFFFF, sum = 0
7008 12:32:56.512237 13, 0x0, sum = 1
7009 12:32:56.514703 14, 0x0, sum = 2
7010 12:32:56.515266 15, 0x0, sum = 3
7011 12:32:56.517512 16, 0x0, sum = 4
7012 12:32:56.517967 best_step = 14
7013 12:32:56.518452
7014 12:32:56.518849 ==
7015 12:32:56.520671 Dram Type= 6, Freq= 0, CH_1, rank 1
7016 12:32:56.527337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7017 12:32:56.527657 ==
7018 12:32:56.527914 RX Vref Scan: 0
7019 12:32:56.528116
7020 12:32:56.531205 RX Vref 0 -> 0, step: 1
7021 12:32:56.531448
7022 12:32:56.534400 RX Delay -359 -> 252, step: 8
7023 12:32:56.540629 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7024 12:32:56.543618 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7025 12:32:56.547541 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7026 12:32:56.550677 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
7027 12:32:56.557089 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7028 12:32:56.560834 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7029 12:32:56.564047 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7030 12:32:56.567317 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7031 12:32:56.573974 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7032 12:32:56.577303 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7033 12:32:56.580621 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7034 12:32:56.586898 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7035 12:32:56.590257 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
7036 12:32:56.593574 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7037 12:32:56.596892 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7038 12:32:56.603861 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7039 12:32:56.603948 ==
7040 12:32:56.607062 Dram Type= 6, Freq= 0, CH_1, rank 1
7041 12:32:56.610299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7042 12:32:56.610387 ==
7043 12:32:56.610465 DQS Delay:
7044 12:32:56.613586 DQS0 = 52, DQS1 = 56
7045 12:32:56.613664 DQM Delay:
7046 12:32:56.616776 DQM0 = 13, DQM1 = 9
7047 12:32:56.616861 DQ Delay:
7048 12:32:56.620155 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7049 12:32:56.623494 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7050 12:32:56.626798 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7051 12:32:56.630136 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
7052 12:32:56.630263
7053 12:32:56.630367
7054 12:32:56.636624 [DQSOSCAuto] RK1, (LSB)MR18= 0x7288, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
7055 12:32:56.639743 CH1 RK1: MR19=C0C, MR18=7288
7056 12:32:56.646770 CH1_RK1: MR19=0xC0C, MR18=0x7288, DQSOSC=392, MR23=63, INC=384, DEC=256
7057 12:32:56.650080 [RxdqsGatingPostProcess] freq 400
7058 12:32:56.656410 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7059 12:32:56.659687 best DQS0 dly(2T, 0.5T) = (0, 10)
7060 12:32:56.659803 best DQS1 dly(2T, 0.5T) = (0, 10)
7061 12:32:56.662900 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7062 12:32:56.666787 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7063 12:32:56.669980 best DQS0 dly(2T, 0.5T) = (0, 10)
7064 12:32:56.673522 best DQS1 dly(2T, 0.5T) = (0, 10)
7065 12:32:56.676820 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7066 12:32:56.680110 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7067 12:32:56.683480 Pre-setting of DQS Precalculation
7068 12:32:56.689961 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7069 12:32:56.696629 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7070 12:32:56.703234 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7071 12:32:56.703366
7072 12:32:56.703437
7073 12:32:56.706464 [Calibration Summary] 800 Mbps
7074 12:32:56.706545 CH 0, Rank 0
7075 12:32:56.709695 SW Impedance : PASS
7076 12:32:56.712907 DUTY Scan : NO K
7077 12:32:56.713016 ZQ Calibration : PASS
7078 12:32:56.716302 Jitter Meter : NO K
7079 12:32:56.716384 CBT Training : PASS
7080 12:32:56.719410 Write leveling : PASS
7081 12:32:56.722794 RX DQS gating : PASS
7082 12:32:56.722901 RX DQ/DQS(RDDQC) : PASS
7083 12:32:56.726206 TX DQ/DQS : PASS
7084 12:32:56.729593 RX DATLAT : PASS
7085 12:32:56.729716 RX DQ/DQS(Engine): PASS
7086 12:32:56.732865 TX OE : NO K
7087 12:32:56.732976 All Pass.
7088 12:32:56.733080
7089 12:32:56.736228 CH 0, Rank 1
7090 12:32:56.736338 SW Impedance : PASS
7091 12:32:56.739470 DUTY Scan : NO K
7092 12:32:56.743275 ZQ Calibration : PASS
7093 12:32:56.743407 Jitter Meter : NO K
7094 12:32:56.746291 CBT Training : PASS
7095 12:32:56.749569 Write leveling : NO K
7096 12:32:56.749678 RX DQS gating : PASS
7097 12:32:56.752767 RX DQ/DQS(RDDQC) : PASS
7098 12:32:56.755944 TX DQ/DQS : PASS
7099 12:32:56.756092 RX DATLAT : PASS
7100 12:32:56.759754 RX DQ/DQS(Engine): PASS
7101 12:32:56.762778 TX OE : NO K
7102 12:32:56.762921 All Pass.
7103 12:32:56.763059
7104 12:32:56.763192 CH 1, Rank 0
7105 12:32:56.766068 SW Impedance : PASS
7106 12:32:56.766190 DUTY Scan : NO K
7107 12:32:56.769767 ZQ Calibration : PASS
7108 12:32:56.773131 Jitter Meter : NO K
7109 12:32:56.773265 CBT Training : PASS
7110 12:32:56.776478 Write leveling : PASS
7111 12:32:56.779729 RX DQS gating : PASS
7112 12:32:56.779837 RX DQ/DQS(RDDQC) : PASS
7113 12:32:56.782960 TX DQ/DQS : PASS
7114 12:32:56.786116 RX DATLAT : PASS
7115 12:32:56.786234 RX DQ/DQS(Engine): PASS
7116 12:32:56.789567 TX OE : NO K
7117 12:32:56.789663 All Pass.
7118 12:32:56.789761
7119 12:32:56.792573 CH 1, Rank 1
7120 12:32:56.792652 SW Impedance : PASS
7121 12:32:56.796447 DUTY Scan : NO K
7122 12:32:56.799820 ZQ Calibration : PASS
7123 12:32:56.799906 Jitter Meter : NO K
7124 12:32:56.802598 CBT Training : PASS
7125 12:32:56.806498 Write leveling : NO K
7126 12:32:56.806585 RX DQS gating : PASS
7127 12:32:56.809866 RX DQ/DQS(RDDQC) : PASS
7128 12:32:56.809955 TX DQ/DQS : PASS
7129 12:32:56.812970 RX DATLAT : PASS
7130 12:32:56.816208 RX DQ/DQS(Engine): PASS
7131 12:32:56.816297 TX OE : NO K
7132 12:32:56.819395 All Pass.
7133 12:32:56.819481
7134 12:32:56.819548 DramC Write-DBI off
7135 12:32:56.822781 PER_BANK_REFRESH: Hybrid Mode
7136 12:32:56.826063 TX_TRACKING: ON
7137 12:32:56.832736 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7138 12:32:56.835967 [FAST_K] Save calibration result to emmc
7139 12:32:56.842538 dramc_set_vcore_voltage set vcore to 725000
7140 12:32:56.842625 Read voltage for 1600, 0
7141 12:32:56.842693 Vio18 = 0
7142 12:32:56.845895 Vcore = 725000
7143 12:32:56.845979 Vdram = 0
7144 12:32:56.846048 Vddq = 0
7145 12:32:56.848968 Vmddr = 0
7146 12:32:56.852385 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7147 12:32:56.859401 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7148 12:32:56.862550 MEM_TYPE=3, freq_sel=13
7149 12:32:56.862636 sv_algorithm_assistance_LP4_3733
7150 12:32:56.868808 ============ PULL DRAM RESETB DOWN ============
7151 12:32:56.872506 ========== PULL DRAM RESETB DOWN end =========
7152 12:32:56.875798 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7153 12:32:56.879153 ===================================
7154 12:32:56.882429 LPDDR4 DRAM CONFIGURATION
7155 12:32:56.885617 ===================================
7156 12:32:56.888981 EX_ROW_EN[0] = 0x0
7157 12:32:56.889067 EX_ROW_EN[1] = 0x0
7158 12:32:56.892928 LP4Y_EN = 0x0
7159 12:32:56.893013 WORK_FSP = 0x1
7160 12:32:56.896148 WL = 0x5
7161 12:32:56.896232 RL = 0x5
7162 12:32:56.899303 BL = 0x2
7163 12:32:56.899426 RPST = 0x0
7164 12:32:56.902513 RD_PRE = 0x0
7165 12:32:56.902624 WR_PRE = 0x1
7166 12:32:56.905823 WR_PST = 0x1
7167 12:32:56.905905 DBI_WR = 0x0
7168 12:32:56.908868 DBI_RD = 0x0
7169 12:32:56.908951 OTF = 0x1
7170 12:32:56.912172 ===================================
7171 12:32:56.915472 ===================================
7172 12:32:56.918818 ANA top config
7173 12:32:56.921923 ===================================
7174 12:32:56.925262 DLL_ASYNC_EN = 0
7175 12:32:56.925365 ALL_SLAVE_EN = 0
7176 12:32:56.928571 NEW_RANK_MODE = 1
7177 12:32:56.931970 DLL_IDLE_MODE = 1
7178 12:32:56.935987 LP45_APHY_COMB_EN = 1
7179 12:32:56.936071 TX_ODT_DIS = 0
7180 12:32:56.938505 NEW_8X_MODE = 1
7181 12:32:56.942346 ===================================
7182 12:32:56.945701 ===================================
7183 12:32:56.948912 data_rate = 3200
7184 12:32:56.952182 CKR = 1
7185 12:32:56.955318 DQ_P2S_RATIO = 8
7186 12:32:56.958950 ===================================
7187 12:32:56.962503 CA_P2S_RATIO = 8
7188 12:32:56.962589 DQ_CA_OPEN = 0
7189 12:32:56.965511 DQ_SEMI_OPEN = 0
7190 12:32:56.968729 CA_SEMI_OPEN = 0
7191 12:32:56.971916 CA_FULL_RATE = 0
7192 12:32:56.975030 DQ_CKDIV4_EN = 0
7193 12:32:56.978332 CA_CKDIV4_EN = 0
7194 12:32:56.978433 CA_PREDIV_EN = 0
7195 12:32:56.981545 PH8_DLY = 12
7196 12:32:56.985252 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7197 12:32:56.988610 DQ_AAMCK_DIV = 4
7198 12:32:56.991930 CA_AAMCK_DIV = 4
7199 12:32:56.995250 CA_ADMCK_DIV = 4
7200 12:32:56.998501 DQ_TRACK_CA_EN = 0
7201 12:32:56.998606 CA_PICK = 1600
7202 12:32:57.001753 CA_MCKIO = 1600
7203 12:32:57.005105 MCKIO_SEMI = 0
7204 12:32:57.008638 PLL_FREQ = 3068
7205 12:32:57.011843 DQ_UI_PI_RATIO = 32
7206 12:32:57.015091 CA_UI_PI_RATIO = 0
7207 12:32:57.018421 ===================================
7208 12:32:57.021767 ===================================
7209 12:32:57.024918 memory_type:LPDDR4
7210 12:32:57.024997 GP_NUM : 10
7211 12:32:57.028383 SRAM_EN : 1
7212 12:32:57.028470 MD32_EN : 0
7213 12:32:57.031644 ===================================
7214 12:32:57.034865 [ANA_INIT] >>>>>>>>>>>>>>
7215 12:32:57.037940 <<<<<< [CONFIGURE PHASE]: ANA_TX
7216 12:32:57.041287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7217 12:32:57.045151 ===================================
7218 12:32:57.048527 data_rate = 3200,PCW = 0X7600
7219 12:32:57.051767 ===================================
7220 12:32:57.054970 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7221 12:32:57.058199 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7222 12:32:57.064688 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7223 12:32:57.068018 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7224 12:32:57.074308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7225 12:32:57.078033 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7226 12:32:57.078152 [ANA_INIT] flow start
7227 12:32:57.081310 [ANA_INIT] PLL >>>>>>>>
7228 12:32:57.084382 [ANA_INIT] PLL <<<<<<<<
7229 12:32:57.084472 [ANA_INIT] MIDPI >>>>>>>>
7230 12:32:57.087468 [ANA_INIT] MIDPI <<<<<<<<
7231 12:32:57.090737 [ANA_INIT] DLL >>>>>>>>
7232 12:32:57.090815 [ANA_INIT] DLL <<<<<<<<
7233 12:32:57.094044 [ANA_INIT] flow end
7234 12:32:57.097917 ============ LP4 DIFF to SE enter ============
7235 12:32:57.101312 ============ LP4 DIFF to SE exit ============
7236 12:32:57.104010 [ANA_INIT] <<<<<<<<<<<<<
7237 12:32:57.107819 [Flow] Enable top DCM control >>>>>
7238 12:32:57.111173 [Flow] Enable top DCM control <<<<<
7239 12:32:57.114351 Enable DLL master slave shuffle
7240 12:32:57.120884 ==============================================================
7241 12:32:57.121007 Gating Mode config
7242 12:32:57.127854 ==============================================================
7243 12:32:57.127963 Config description:
7244 12:32:57.137830 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7245 12:32:57.143807 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7246 12:32:57.150940 SELPH_MODE 0: By rank 1: By Phase
7247 12:32:57.154165 ==============================================================
7248 12:32:57.157526 GAT_TRACK_EN = 1
7249 12:32:57.160885 RX_GATING_MODE = 2
7250 12:32:57.164111 RX_GATING_TRACK_MODE = 2
7251 12:32:57.167262 SELPH_MODE = 1
7252 12:32:57.170548 PICG_EARLY_EN = 1
7253 12:32:57.173829 VALID_LAT_VALUE = 1
7254 12:32:57.180792 ==============================================================
7255 12:32:57.183595 Enter into Gating configuration >>>>
7256 12:32:57.187174 Exit from Gating configuration <<<<
7257 12:32:57.190278 Enter into DVFS_PRE_config >>>>>
7258 12:32:57.200038 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7259 12:32:57.203249 Exit from DVFS_PRE_config <<<<<
7260 12:32:57.207255 Enter into PICG configuration >>>>
7261 12:32:57.210456 Exit from PICG configuration <<<<
7262 12:32:57.213672 [RX_INPUT] configuration >>>>>
7263 12:32:57.213779 [RX_INPUT] configuration <<<<<
7264 12:32:57.220262 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7265 12:32:57.226942 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7266 12:32:57.230074 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7267 12:32:57.236892 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7268 12:32:57.243270 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7269 12:32:57.249971 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7270 12:32:57.253701 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7271 12:32:57.256835 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7272 12:32:57.263300 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7273 12:32:57.266601 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7274 12:32:57.269893 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7275 12:32:57.276886 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7276 12:32:57.277004 ===================================
7277 12:32:57.280572 LPDDR4 DRAM CONFIGURATION
7278 12:32:57.283814 ===================================
7279 12:32:57.287135 EX_ROW_EN[0] = 0x0
7280 12:32:57.287220 EX_ROW_EN[1] = 0x0
7281 12:32:57.290178 LP4Y_EN = 0x0
7282 12:32:57.290261 WORK_FSP = 0x1
7283 12:32:57.293532 WL = 0x5
7284 12:32:57.293634 RL = 0x5
7285 12:32:57.297284 BL = 0x2
7286 12:32:57.297368 RPST = 0x0
7287 12:32:57.299979 RD_PRE = 0x0
7288 12:32:57.303780 WR_PRE = 0x1
7289 12:32:57.303882 WR_PST = 0x1
7290 12:32:57.306553 DBI_WR = 0x0
7291 12:32:57.306680 DBI_RD = 0x0
7292 12:32:57.309871 OTF = 0x1
7293 12:32:57.313197 ===================================
7294 12:32:57.316373 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7295 12:32:57.320192 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7296 12:32:57.323314 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7297 12:32:57.326821 ===================================
7298 12:32:57.330159 LPDDR4 DRAM CONFIGURATION
7299 12:32:57.333309 ===================================
7300 12:32:57.336651 EX_ROW_EN[0] = 0x10
7301 12:32:57.336734 EX_ROW_EN[1] = 0x0
7302 12:32:57.340080 LP4Y_EN = 0x0
7303 12:32:57.340163 WORK_FSP = 0x1
7304 12:32:57.343531 WL = 0x5
7305 12:32:57.343614 RL = 0x5
7306 12:32:57.346804 BL = 0x2
7307 12:32:57.346911 RPST = 0x0
7308 12:32:57.349958 RD_PRE = 0x0
7309 12:32:57.350064 WR_PRE = 0x1
7310 12:32:57.353477 WR_PST = 0x1
7311 12:32:57.356606 DBI_WR = 0x0
7312 12:32:57.356707 DBI_RD = 0x0
7313 12:32:57.359801 OTF = 0x1
7314 12:32:57.363131 ===================================
7315 12:32:57.366356 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7316 12:32:57.369741 ==
7317 12:32:57.369852 Dram Type= 6, Freq= 0, CH_0, rank 0
7318 12:32:57.376224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7319 12:32:57.376339 ==
7320 12:32:57.379968 [Duty_Offset_Calibration]
7321 12:32:57.380072 B0:2 B1:-1 CA:1
7322 12:32:57.380164
7323 12:32:57.383059 [DutyScan_Calibration_Flow] k_type=0
7324 12:32:57.391955
7325 12:32:57.392047 ==CLK 0==
7326 12:32:57.395261 Final CLK duty delay cell = -4
7327 12:32:57.398564 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7328 12:32:57.401784 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7329 12:32:57.404991 [-4] AVG Duty = 4937%(X100)
7330 12:32:57.405104
7331 12:32:57.408395 CH0 CLK Duty spec in!! Max-Min= 187%
7332 12:32:57.411662 [DutyScan_Calibration_Flow] ====Done====
7333 12:32:57.411774
7334 12:32:57.414875 [DutyScan_Calibration_Flow] k_type=1
7335 12:32:57.431322
7336 12:32:57.431436 ==DQS 0 ==
7337 12:32:57.434511 Final DQS duty delay cell = 0
7338 12:32:57.437833 [0] MAX Duty = 5125%(X100), DQS PI = 22
7339 12:32:57.441272 [0] MIN Duty = 5000%(X100), DQS PI = 14
7340 12:32:57.444621 [0] AVG Duty = 5062%(X100)
7341 12:32:57.444701
7342 12:32:57.444767 ==DQS 1 ==
7343 12:32:57.447849 Final DQS duty delay cell = -4
7344 12:32:57.451045 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7345 12:32:57.454357 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7346 12:32:57.457629 [-4] AVG Duty = 5046%(X100)
7347 12:32:57.457739
7348 12:32:57.460982 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7349 12:32:57.461084
7350 12:32:57.464324 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7351 12:32:57.467648 [DutyScan_Calibration_Flow] ====Done====
7352 12:32:57.467723
7353 12:32:57.470730 [DutyScan_Calibration_Flow] k_type=3
7354 12:32:57.488798
7355 12:32:57.488915 ==DQM 0 ==
7356 12:32:57.492107 Final DQM duty delay cell = 0
7357 12:32:57.495084 [0] MAX Duty = 5000%(X100), DQS PI = 20
7358 12:32:57.498624 [0] MIN Duty = 4875%(X100), DQS PI = 4
7359 12:32:57.501967 [0] AVG Duty = 4937%(X100)
7360 12:32:57.502051
7361 12:32:57.502114 ==DQM 1 ==
7362 12:32:57.505098 Final DQM duty delay cell = 0
7363 12:32:57.509016 [0] MAX Duty = 5218%(X100), DQS PI = 58
7364 12:32:57.512147 [0] MIN Duty = 4969%(X100), DQS PI = 20
7365 12:32:57.515367 [0] AVG Duty = 5093%(X100)
7366 12:32:57.515448
7367 12:32:57.518704 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7368 12:32:57.518786
7369 12:32:57.521965 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7370 12:32:57.525021 [DutyScan_Calibration_Flow] ====Done====
7371 12:32:57.525147
7372 12:32:57.528312 [DutyScan_Calibration_Flow] k_type=2
7373 12:32:57.545189
7374 12:32:57.545277 ==DQ 0 ==
7375 12:32:57.548514 Final DQ duty delay cell = -4
7376 12:32:57.551765 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7377 12:32:57.555171 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7378 12:32:57.558385 [-4] AVG Duty = 4937%(X100)
7379 12:32:57.558467
7380 12:32:57.558574 ==DQ 1 ==
7381 12:32:57.561710 Final DQ duty delay cell = 0
7382 12:32:57.564985 [0] MAX Duty = 5031%(X100), DQS PI = 30
7383 12:32:57.568314 [0] MIN Duty = 4938%(X100), DQS PI = 10
7384 12:32:57.571370 [0] AVG Duty = 4984%(X100)
7385 12:32:57.571470
7386 12:32:57.574866 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7387 12:32:57.574950
7388 12:32:57.578113 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7389 12:32:57.581422 [DutyScan_Calibration_Flow] ====Done====
7390 12:32:57.581508 ==
7391 12:32:57.584510 Dram Type= 6, Freq= 0, CH_1, rank 0
7392 12:32:57.587866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7393 12:32:57.587937 ==
7394 12:32:57.591008 [Duty_Offset_Calibration]
7395 12:32:57.591086 B0:1 B1:1 CA:2
7396 12:32:57.591149
7397 12:32:57.594272 [DutyScan_Calibration_Flow] k_type=0
7398 12:32:57.605365
7399 12:32:57.605449 ==CLK 0==
7400 12:32:57.608567 Final CLK duty delay cell = 0
7401 12:32:57.612299 [0] MAX Duty = 5218%(X100), DQS PI = 24
7402 12:32:57.615648 [0] MIN Duty = 4938%(X100), DQS PI = 48
7403 12:32:57.615732 [0] AVG Duty = 5078%(X100)
7404 12:32:57.618805
7405 12:32:57.622109 CH1 CLK Duty spec in!! Max-Min= 280%
7406 12:32:57.625490 [DutyScan_Calibration_Flow] ====Done====
7407 12:32:57.625571
7408 12:32:57.628739 [DutyScan_Calibration_Flow] k_type=1
7409 12:32:57.644798
7410 12:32:57.644904 ==DQS 0 ==
7411 12:32:57.648115 Final DQS duty delay cell = 0
7412 12:32:57.651547 [0] MAX Duty = 5062%(X100), DQS PI = 22
7413 12:32:57.654928 [0] MIN Duty = 4813%(X100), DQS PI = 52
7414 12:32:57.658054 [0] AVG Duty = 4937%(X100)
7415 12:32:57.658179
7416 12:32:57.658275 ==DQS 1 ==
7417 12:32:57.661483 Final DQS duty delay cell = 0
7418 12:32:57.664875 [0] MAX Duty = 5062%(X100), DQS PI = 34
7419 12:32:57.668093 [0] MIN Duty = 4938%(X100), DQS PI = 12
7420 12:32:57.671441 [0] AVG Duty = 5000%(X100)
7421 12:32:57.671564
7422 12:32:57.674561 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7423 12:32:57.674655
7424 12:32:57.677852 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7425 12:32:57.681164 [DutyScan_Calibration_Flow] ====Done====
7426 12:32:57.681249
7427 12:32:57.684542 [DutyScan_Calibration_Flow] k_type=3
7428 12:32:57.702321
7429 12:32:57.702429 ==DQM 0 ==
7430 12:32:57.705480 Final DQM duty delay cell = 0
7431 12:32:57.708693 [0] MAX Duty = 5124%(X100), DQS PI = 18
7432 12:32:57.711901 [0] MIN Duty = 4876%(X100), DQS PI = 46
7433 12:32:57.715023 [0] AVG Duty = 5000%(X100)
7434 12:32:57.715108
7435 12:32:57.715225 ==DQM 1 ==
7436 12:32:57.718399 Final DQM duty delay cell = 0
7437 12:32:57.721635 [0] MAX Duty = 5125%(X100), DQS PI = 8
7438 12:32:57.725045 [0] MIN Duty = 4875%(X100), DQS PI = 22
7439 12:32:57.728343 [0] AVG Duty = 5000%(X100)
7440 12:32:57.728427
7441 12:32:57.731588 CH1 DQM 0 Duty spec in!! Max-Min= 248%
7442 12:32:57.731672
7443 12:32:57.735304 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7444 12:32:57.738911 [DutyScan_Calibration_Flow] ====Done====
7445 12:32:57.738997
7446 12:32:57.741333 [DutyScan_Calibration_Flow] k_type=2
7447 12:32:57.758651
7448 12:32:57.758772 ==DQ 0 ==
7449 12:32:57.761940 Final DQ duty delay cell = 0
7450 12:32:57.765327 [0] MAX Duty = 5156%(X100), DQS PI = 20
7451 12:32:57.769268 [0] MIN Duty = 4907%(X100), DQS PI = 52
7452 12:32:57.769354 [0] AVG Duty = 5031%(X100)
7453 12:32:57.769422
7454 12:32:57.771888 ==DQ 1 ==
7455 12:32:57.775139 Final DQ duty delay cell = 0
7456 12:32:57.779000 [0] MAX Duty = 5093%(X100), DQS PI = 6
7457 12:32:57.782484 [0] MIN Duty = 5031%(X100), DQS PI = 0
7458 12:32:57.782562 [0] AVG Duty = 5062%(X100)
7459 12:32:57.782626
7460 12:32:57.785794 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7461 12:32:57.785880
7462 12:32:57.791607 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7463 12:32:57.794836 [DutyScan_Calibration_Flow] ====Done====
7464 12:32:57.798804 nWR fixed to 30
7465 12:32:57.798900 [ModeRegInit_LP4] CH0 RK0
7466 12:32:57.801892 [ModeRegInit_LP4] CH0 RK1
7467 12:32:57.805106 [ModeRegInit_LP4] CH1 RK0
7468 12:32:57.805192 [ModeRegInit_LP4] CH1 RK1
7469 12:32:57.808102 match AC timing 5
7470 12:32:57.812046 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7471 12:32:57.818471 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7472 12:32:57.821612 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7473 12:32:57.828413 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7474 12:32:57.831754 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7475 12:32:57.831869 [MiockJmeterHQA]
7476 12:32:57.831970
7477 12:32:57.835031 [DramcMiockJmeter] u1RxGatingPI = 0
7478 12:32:57.838344 0 : 4254, 4029
7479 12:32:57.838457 4 : 4255, 4027
7480 12:32:57.841544 8 : 4252, 4027
7481 12:32:57.841631 12 : 4252, 4027
7482 12:32:57.841699 16 : 4253, 4027
7483 12:32:57.844492 20 : 4254, 4029
7484 12:32:57.844605 24 : 4257, 4029
7485 12:32:57.847888 28 : 4253, 4027
7486 12:32:57.847974 32 : 4366, 4140
7487 12:32:57.851735 36 : 4254, 4029
7488 12:32:57.851843 40 : 4363, 4138
7489 12:32:57.855005 44 : 4252, 4026
7490 12:32:57.855091 48 : 4252, 4027
7491 12:32:57.855158 52 : 4363, 4138
7492 12:32:57.857721 56 : 4253, 4027
7493 12:32:57.857834 60 : 4252, 4026
7494 12:32:57.861693 64 : 4255, 4029
7495 12:32:57.861800 68 : 4255, 4030
7496 12:32:57.864799 72 : 4363, 4139
7497 12:32:57.864905 76 : 4252, 4029
7498 12:32:57.868165 80 : 4255, 4029
7499 12:32:57.868276 84 : 4363, 4140
7500 12:32:57.868369 88 : 4252, 4029
7501 12:32:57.871418 92 : 4253, 4029
7502 12:32:57.871521 96 : 4257, 2956
7503 12:32:57.874805 100 : 4363, 0
7504 12:32:57.874943 104 : 4250, 0
7505 12:32:57.875067 108 : 4255, 0
7506 12:32:57.877896 112 : 4367, 0
7507 12:32:57.878009 116 : 4250, 0
7508 12:32:57.881375 120 : 4250, 0
7509 12:32:57.881490 124 : 4363, 0
7510 12:32:57.881587 128 : 4255, 0
7511 12:32:57.884641 132 : 4361, 0
7512 12:32:57.884754 136 : 4250, 0
7513 12:32:57.887918 140 : 4249, 0
7514 12:32:57.888025 144 : 4252, 0
7515 12:32:57.888120 148 : 4249, 0
7516 12:32:57.891206 152 : 4250, 0
7517 12:32:57.891319 156 : 4255, 0
7518 12:32:57.894517 160 : 4250, 0
7519 12:32:57.894600 164 : 4252, 0
7520 12:32:57.894666 168 : 4252, 0
7521 12:32:57.897979 172 : 4252, 0
7522 12:32:57.898070 176 : 4361, 0
7523 12:32:57.898136 180 : 4363, 0
7524 12:32:57.901078 184 : 4253, 0
7525 12:32:57.901160 188 : 4252, 0
7526 12:32:57.904107 192 : 4257, 0
7527 12:32:57.904220 196 : 4254, 0
7528 12:32:57.904318 200 : 4250, 0
7529 12:32:57.907555 204 : 4258, 0
7530 12:32:57.907628 208 : 4253, 0
7531 12:32:57.910696 212 : 4250, 203
7532 12:32:57.910771 216 : 4258, 3786
7533 12:32:57.914349 220 : 4361, 4137
7534 12:32:57.914454 224 : 4250, 4026
7535 12:32:57.917486 228 : 4250, 4027
7536 12:32:57.917590 232 : 4257, 4034
7537 12:32:57.917662 236 : 4365, 4140
7538 12:32:57.920881 240 : 4360, 4138
7539 12:32:57.920982 244 : 4252, 4029
7540 12:32:57.924011 248 : 4363, 4140
7541 12:32:57.924122 252 : 4252, 4029
7542 12:32:57.927110 256 : 4252, 4030
7543 12:32:57.927223 260 : 4249, 4027
7544 12:32:57.930473 264 : 4252, 4030
7545 12:32:57.930556 268 : 4257, 4031
7546 12:32:57.933648 272 : 4363, 4140
7547 12:32:57.933732 276 : 4250, 4027
7548 12:32:57.937001 280 : 4255, 4029
7549 12:32:57.937115 284 : 4255, 4029
7550 12:32:57.940979 288 : 4250, 4027
7551 12:32:57.941078 292 : 4361, 4137
7552 12:32:57.943578 296 : 4250, 4027
7553 12:32:57.943669 300 : 4255, 4029
7554 12:32:57.943737 304 : 4250, 4027
7555 12:32:57.947257 308 : 4250, 4027
7556 12:32:57.947399 312 : 4250, 4027
7557 12:32:57.950407 316 : 4250, 4027
7558 12:32:57.950526 320 : 4250, 4027
7559 12:32:57.953643 324 : 4361, 4137
7560 12:32:57.953768 328 : 4255, 4028
7561 12:32:57.957051 332 : 4363, 3065
7562 12:32:57.957160 336 : 4255, 39
7563 12:32:57.957253
7564 12:32:57.960322 MIOCK jitter meter ch=0
7565 12:32:57.960419
7566 12:32:57.963500 1T = (336-100) = 236 dly cells
7567 12:32:57.967270 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7568 12:32:57.970603 ==
7569 12:32:57.973856 Dram Type= 6, Freq= 0, CH_0, rank 0
7570 12:32:57.977038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7571 12:32:57.977136 ==
7572 12:32:57.980321 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7573 12:32:57.987073 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7574 12:32:57.990422 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7575 12:32:57.996898 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7576 12:32:58.005465 [CA 0] Center 44 (14~75) winsize 62
7577 12:32:58.008570 [CA 1] Center 44 (13~75) winsize 63
7578 12:32:58.011868 [CA 2] Center 40 (11~69) winsize 59
7579 12:32:58.015085 [CA 3] Center 39 (10~69) winsize 60
7580 12:32:58.018222 [CA 4] Center 38 (8~68) winsize 61
7581 12:32:58.021999 [CA 5] Center 37 (7~67) winsize 61
7582 12:32:58.022091
7583 12:32:58.025334 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7584 12:32:58.025421
7585 12:32:58.031566 [CATrainingPosCal] consider 1 rank data
7586 12:32:58.031660 u2DelayCellTimex100 = 275/100 ps
7587 12:32:58.038726 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7588 12:32:58.041372 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7589 12:32:58.045320 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7590 12:32:58.048469 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7591 12:32:58.051659 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7592 12:32:58.054792 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7593 12:32:58.054907
7594 12:32:58.057922 CA PerBit enable=1, Macro0, CA PI delay=37
7595 12:32:58.058012
7596 12:32:58.061361 [CBTSetCACLKResult] CA Dly = 37
7597 12:32:58.064780 CS Dly: 11 (0~42)
7598 12:32:58.067984 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7599 12:32:58.071136 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7600 12:32:58.071244 ==
7601 12:32:58.074534 Dram Type= 6, Freq= 0, CH_0, rank 1
7602 12:32:58.081725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 12:32:58.081824 ==
7604 12:32:58.084510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7605 12:32:58.091859 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7606 12:32:58.094486 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7607 12:32:58.101075 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7608 12:32:58.108903 [CA 0] Center 44 (14~75) winsize 62
7609 12:32:58.112657 [CA 1] Center 44 (14~75) winsize 62
7610 12:32:58.115862 [CA 2] Center 39 (10~69) winsize 60
7611 12:32:58.119183 [CA 3] Center 39 (10~69) winsize 60
7612 12:32:58.122717 [CA 4] Center 38 (9~68) winsize 60
7613 12:32:58.125831 [CA 5] Center 37 (7~67) winsize 61
7614 12:32:58.125939
7615 12:32:58.129154 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7616 12:32:58.129233
7617 12:32:58.132480 [CATrainingPosCal] consider 2 rank data
7618 12:32:58.135641 u2DelayCellTimex100 = 275/100 ps
7619 12:32:58.142252 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7620 12:32:58.145556 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7621 12:32:58.148796 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7622 12:32:58.152650 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7623 12:32:58.155748 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
7624 12:32:58.158902 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7625 12:32:58.158982
7626 12:32:58.162279 CA PerBit enable=1, Macro0, CA PI delay=37
7627 12:32:58.162359
7628 12:32:58.165513 [CBTSetCACLKResult] CA Dly = 37
7629 12:32:58.168896 CS Dly: 12 (0~44)
7630 12:32:58.172054 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7631 12:32:58.175317 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7632 12:32:58.175421
7633 12:32:58.178663 ----->DramcWriteLeveling(PI) begin...
7634 12:32:58.178751 ==
7635 12:32:58.182600 Dram Type= 6, Freq= 0, CH_0, rank 0
7636 12:32:58.188625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7637 12:32:58.188713 ==
7638 12:32:58.191910 Write leveling (Byte 0): 34 => 34
7639 12:32:58.195822 Write leveling (Byte 1): 28 => 28
7640 12:32:58.195934 DramcWriteLeveling(PI) end<-----
7641 12:32:58.196018
7642 12:32:58.199100 ==
7643 12:32:58.202477 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 12:32:58.205606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 12:32:58.205686 ==
7646 12:32:58.208361 [Gating] SW mode calibration
7647 12:32:58.215584 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7648 12:32:58.218896 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7649 12:32:58.225315 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7650 12:32:58.228511 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 12:32:58.231712 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 12:32:58.238724 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 12:32:58.242089 1 4 16 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7654 12:32:58.245403 1 4 20 | B1->B0 | 2423 3434 | 1 0 | (0 0) (0 0)
7655 12:32:58.251965 1 4 24 | B1->B0 | 3433 3434 | 1 1 | (1 1) (1 1)
7656 12:32:58.255297 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7657 12:32:58.258553 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7658 12:32:58.264928 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7659 12:32:58.268880 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7660 12:32:58.272187 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7661 12:32:58.278159 1 5 16 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7662 12:32:58.281519 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7663 12:32:58.284764 1 5 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
7664 12:32:58.291906 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7665 12:32:58.295160 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 12:32:58.298540 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 12:32:58.301844 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7668 12:32:58.308666 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7669 12:32:58.311967 1 6 16 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
7670 12:32:58.315241 1 6 20 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7671 12:32:58.321722 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7672 12:32:58.324861 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7673 12:32:58.328124 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7674 12:32:58.335039 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 12:32:58.338275 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 12:32:58.341413 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7677 12:32:58.348461 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 12:32:58.351751 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7679 12:32:58.355099 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7680 12:32:58.361698 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 12:32:58.364787 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 12:32:58.368121 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 12:32:58.374688 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 12:32:58.377770 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 12:32:58.381763 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 12:32:58.388180 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 12:32:58.391598 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 12:32:58.395016 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 12:32:58.401507 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 12:32:58.404633 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 12:32:58.407984 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 12:32:58.414677 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 12:32:58.417980 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7694 12:32:58.421073 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7695 12:32:58.424363 Total UI for P1: 0, mck2ui 16
7696 12:32:58.428210 best dqsien dly found for B0: ( 1, 9, 16)
7697 12:32:58.434278 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7698 12:32:58.437578 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7699 12:32:58.441243 Total UI for P1: 0, mck2ui 16
7700 12:32:58.444559 best dqsien dly found for B1: ( 1, 9, 22)
7701 12:32:58.447728 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7702 12:32:58.451010 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7703 12:32:58.451094
7704 12:32:58.454272 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7705 12:32:58.457651 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7706 12:32:58.460957 [Gating] SW calibration Done
7707 12:32:58.461042 ==
7708 12:32:58.464299 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 12:32:58.467593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 12:32:58.467678 ==
7711 12:32:58.470738 RX Vref Scan: 0
7712 12:32:58.470849
7713 12:32:58.474040 RX Vref 0 -> 0, step: 1
7714 12:32:58.474127
7715 12:32:58.474194 RX Delay 0 -> 252, step: 8
7716 12:32:58.481310 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7717 12:32:58.484479 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7718 12:32:58.487775 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7719 12:32:58.490909 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7720 12:32:58.494426 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7721 12:32:58.500966 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7722 12:32:58.504175 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7723 12:32:58.507580 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7724 12:32:58.510871 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7725 12:32:58.514109 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7726 12:32:58.520510 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7727 12:32:58.524430 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7728 12:32:58.527901 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7729 12:32:58.531100 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7730 12:32:58.534563 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7731 12:32:58.540650 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7732 12:32:58.540785 ==
7733 12:32:58.544428 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 12:32:58.547457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 12:32:58.547577 ==
7736 12:32:58.547650 DQS Delay:
7737 12:32:58.550582 DQS0 = 0, DQS1 = 0
7738 12:32:58.550655 DQM Delay:
7739 12:32:58.554343 DQM0 = 131, DQM1 = 123
7740 12:32:58.554442 DQ Delay:
7741 12:32:58.557521 DQ0 =131, DQ1 =135, DQ2 =123, DQ3 =127
7742 12:32:58.560904 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7743 12:32:58.564270 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7744 12:32:58.567626 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7745 12:32:58.567738
7746 12:32:58.570999
7747 12:32:58.571095 ==
7748 12:32:58.574132 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 12:32:58.577148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 12:32:58.577300 ==
7751 12:32:58.577403
7752 12:32:58.577495
7753 12:32:58.581250 TX Vref Scan disable
7754 12:32:58.581385 == TX Byte 0 ==
7755 12:32:58.587617 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7756 12:32:58.590783 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7757 12:32:58.590970 == TX Byte 1 ==
7758 12:32:58.597526 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7759 12:32:58.600810 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7760 12:32:58.600926 ==
7761 12:32:58.604068 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 12:32:58.607235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 12:32:58.607368 ==
7764 12:32:58.622635
7765 12:32:58.625749 TX Vref early break, caculate TX vref
7766 12:32:58.628924 TX Vref=16, minBit 1, minWin=21, winSum=364
7767 12:32:58.632781 TX Vref=18, minBit 0, minWin=22, winSum=370
7768 12:32:58.636288 TX Vref=20, minBit 12, minWin=22, winSum=379
7769 12:32:58.638902 TX Vref=22, minBit 4, minWin=23, winSum=394
7770 12:32:58.642897 TX Vref=24, minBit 7, minWin=23, winSum=395
7771 12:32:58.649102 TX Vref=26, minBit 4, minWin=24, winSum=412
7772 12:32:58.652289 TX Vref=28, minBit 4, minWin=24, winSum=414
7773 12:32:58.656151 TX Vref=30, minBit 3, minWin=25, winSum=420
7774 12:32:58.659191 TX Vref=32, minBit 4, minWin=24, winSum=415
7775 12:32:58.662402 TX Vref=34, minBit 4, minWin=24, winSum=407
7776 12:32:58.665510 TX Vref=36, minBit 4, minWin=23, winSum=392
7777 12:32:58.672417 [TxChooseVref] Worse bit 3, Min win 25, Win sum 420, Final Vref 30
7778 12:32:58.672551
7779 12:32:58.675687 Final TX Range 0 Vref 30
7780 12:32:58.675802
7781 12:32:58.675875 ==
7782 12:32:58.678904 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 12:32:58.682648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 12:32:58.682772 ==
7785 12:32:58.682843
7786 12:32:58.682907
7787 12:32:58.685872 TX Vref Scan disable
7788 12:32:58.692410 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7789 12:32:58.692551 == TX Byte 0 ==
7790 12:32:58.695626 u2DelayCellOfst[0]=14 cells (4 PI)
7791 12:32:58.698511 u2DelayCellOfst[1]=17 cells (5 PI)
7792 12:32:58.701911 u2DelayCellOfst[2]=7 cells (2 PI)
7793 12:32:58.705291 u2DelayCellOfst[3]=14 cells (4 PI)
7794 12:32:58.708410 u2DelayCellOfst[4]=7 cells (2 PI)
7795 12:32:58.712416 u2DelayCellOfst[5]=0 cells (0 PI)
7796 12:32:58.715159 u2DelayCellOfst[6]=21 cells (6 PI)
7797 12:32:58.719058 u2DelayCellOfst[7]=17 cells (5 PI)
7798 12:32:58.721777 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7799 12:32:58.725047 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7800 12:32:58.728334 == TX Byte 1 ==
7801 12:32:58.732321 u2DelayCellOfst[8]=3 cells (1 PI)
7802 12:32:58.734960 u2DelayCellOfst[9]=0 cells (0 PI)
7803 12:32:58.735047 u2DelayCellOfst[10]=7 cells (2 PI)
7804 12:32:58.738446 u2DelayCellOfst[11]=3 cells (1 PI)
7805 12:32:58.741679 u2DelayCellOfst[12]=14 cells (4 PI)
7806 12:32:58.745691 u2DelayCellOfst[13]=14 cells (4 PI)
7807 12:32:58.748987 u2DelayCellOfst[14]=17 cells (5 PI)
7808 12:32:58.751631 u2DelayCellOfst[15]=10 cells (3 PI)
7809 12:32:58.758262 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7810 12:32:58.762012 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7811 12:32:58.762144 DramC Write-DBI on
7812 12:32:58.762224 ==
7813 12:32:58.765117 Dram Type= 6, Freq= 0, CH_0, rank 0
7814 12:32:58.771927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7815 12:32:58.772060 ==
7816 12:32:58.772133
7817 12:32:58.772205
7818 12:32:58.772285 TX Vref Scan disable
7819 12:32:58.775789 == TX Byte 0 ==
7820 12:32:58.779031 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7821 12:32:58.782363 == TX Byte 1 ==
7822 12:32:58.786084 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7823 12:32:58.786175 DramC Write-DBI off
7824 12:32:58.789360
7825 12:32:58.789446 [DATLAT]
7826 12:32:58.789513 Freq=1600, CH0 RK0
7827 12:32:58.789576
7828 12:32:58.792324 DATLAT Default: 0xf
7829 12:32:58.792437 0, 0xFFFF, sum = 0
7830 12:32:58.795667 1, 0xFFFF, sum = 0
7831 12:32:58.795795 2, 0xFFFF, sum = 0
7832 12:32:58.798948 3, 0xFFFF, sum = 0
7833 12:32:58.802232 4, 0xFFFF, sum = 0
7834 12:32:58.802349 5, 0xFFFF, sum = 0
7835 12:32:58.805678 6, 0xFFFF, sum = 0
7836 12:32:58.805784 7, 0xFFFF, sum = 0
7837 12:32:58.808880 8, 0xFFFF, sum = 0
7838 12:32:58.808973 9, 0xFFFF, sum = 0
7839 12:32:58.812141 10, 0xFFFF, sum = 0
7840 12:32:58.812228 11, 0xFFFF, sum = 0
7841 12:32:58.815578 12, 0xFFFF, sum = 0
7842 12:32:58.815712 13, 0xFFFF, sum = 0
7843 12:32:58.818779 14, 0x0, sum = 1
7844 12:32:58.818850 15, 0x0, sum = 2
7845 12:32:58.821949 16, 0x0, sum = 3
7846 12:32:58.822035 17, 0x0, sum = 4
7847 12:32:58.825413 best_step = 15
7848 12:32:58.825497
7849 12:32:58.825563 ==
7850 12:32:58.828639 Dram Type= 6, Freq= 0, CH_0, rank 0
7851 12:32:58.832008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7852 12:32:58.832096 ==
7853 12:32:58.835153 RX Vref Scan: 1
7854 12:32:58.835237
7855 12:32:58.835304 Set Vref Range= 24 -> 127
7856 12:32:58.835394
7857 12:32:58.838532 RX Vref 24 -> 127, step: 1
7858 12:32:58.838616
7859 12:32:58.841801 RX Delay 11 -> 252, step: 4
7860 12:32:58.841905
7861 12:32:58.845977 Set Vref, RX VrefLevel [Byte0]: 24
7862 12:32:58.848690 [Byte1]: 24
7863 12:32:58.848792
7864 12:32:58.851927 Set Vref, RX VrefLevel [Byte0]: 25
7865 12:32:58.855024 [Byte1]: 25
7866 12:32:58.858404
7867 12:32:58.858529 Set Vref, RX VrefLevel [Byte0]: 26
7868 12:32:58.861665 [Byte1]: 26
7869 12:32:58.866170
7870 12:32:58.866284 Set Vref, RX VrefLevel [Byte0]: 27
7871 12:32:58.869345 [Byte1]: 27
7872 12:32:58.873885
7873 12:32:58.874089 Set Vref, RX VrefLevel [Byte0]: 28
7874 12:32:58.877322 [Byte1]: 28
7875 12:32:58.881171
7876 12:32:58.881347 Set Vref, RX VrefLevel [Byte0]: 29
7877 12:32:58.884409 [Byte1]: 29
7878 12:32:58.888802
7879 12:32:58.888940 Set Vref, RX VrefLevel [Byte0]: 30
7880 12:32:58.892659 [Byte1]: 30
7881 12:32:58.896378
7882 12:32:58.896503 Set Vref, RX VrefLevel [Byte0]: 31
7883 12:32:58.900193 [Byte1]: 31
7884 12:32:58.904356
7885 12:32:58.904495 Set Vref, RX VrefLevel [Byte0]: 32
7886 12:32:58.907628 [Byte1]: 32
7887 12:32:58.912299
7888 12:32:58.912416 Set Vref, RX VrefLevel [Byte0]: 33
7889 12:32:58.915496 [Byte1]: 33
7890 12:32:58.919601
7891 12:32:58.919712 Set Vref, RX VrefLevel [Byte0]: 34
7892 12:32:58.922826 [Byte1]: 34
7893 12:32:58.926874
7894 12:32:58.926988 Set Vref, RX VrefLevel [Byte0]: 35
7895 12:32:58.930681 [Byte1]: 35
7896 12:32:58.934635
7897 12:32:58.934720 Set Vref, RX VrefLevel [Byte0]: 36
7898 12:32:58.937901 [Byte1]: 36
7899 12:32:58.942452
7900 12:32:58.942537 Set Vref, RX VrefLevel [Byte0]: 37
7901 12:32:58.945665 [Byte1]: 37
7902 12:32:58.949624
7903 12:32:58.949733 Set Vref, RX VrefLevel [Byte0]: 38
7904 12:32:58.953506 [Byte1]: 38
7905 12:32:58.957568
7906 12:32:58.957688 Set Vref, RX VrefLevel [Byte0]: 39
7907 12:32:58.960928 [Byte1]: 39
7908 12:32:58.964946
7909 12:32:58.965056 Set Vref, RX VrefLevel [Byte0]: 40
7910 12:32:58.968662 [Byte1]: 40
7911 12:32:58.972973
7912 12:32:58.973116 Set Vref, RX VrefLevel [Byte0]: 41
7913 12:32:58.976059 [Byte1]: 41
7914 12:32:58.980424
7915 12:32:58.980535 Set Vref, RX VrefLevel [Byte0]: 42
7916 12:32:58.983541 [Byte1]: 42
7917 12:32:58.987903
7918 12:32:58.987988 Set Vref, RX VrefLevel [Byte0]: 43
7919 12:32:58.991202 [Byte1]: 43
7920 12:32:58.995725
7921 12:32:58.995823 Set Vref, RX VrefLevel [Byte0]: 44
7922 12:32:58.998952 [Byte1]: 44
7923 12:32:59.003192
7924 12:32:59.003288 Set Vref, RX VrefLevel [Byte0]: 45
7925 12:32:59.006536 [Byte1]: 45
7926 12:32:59.010654
7927 12:32:59.010783 Set Vref, RX VrefLevel [Byte0]: 46
7928 12:32:59.013821 [Byte1]: 46
7929 12:32:59.018493
7930 12:32:59.018615 Set Vref, RX VrefLevel [Byte0]: 47
7931 12:32:59.021745 [Byte1]: 47
7932 12:32:59.026193
7933 12:32:59.026306 Set Vref, RX VrefLevel [Byte0]: 48
7934 12:32:59.029614 [Byte1]: 48
7935 12:32:59.033571
7936 12:32:59.033669 Set Vref, RX VrefLevel [Byte0]: 49
7937 12:32:59.036917 [Byte1]: 49
7938 12:32:59.041606
7939 12:32:59.041700 Set Vref, RX VrefLevel [Byte0]: 50
7940 12:32:59.044913 [Byte1]: 50
7941 12:32:59.048886
7942 12:32:59.048974 Set Vref, RX VrefLevel [Byte0]: 51
7943 12:32:59.052144 [Byte1]: 51
7944 12:32:59.056776
7945 12:32:59.056861 Set Vref, RX VrefLevel [Byte0]: 52
7946 12:32:59.060150 [Byte1]: 52
7947 12:32:59.064205
7948 12:32:59.064289 Set Vref, RX VrefLevel [Byte0]: 53
7949 12:32:59.067506 [Byte1]: 53
7950 12:32:59.072079
7951 12:32:59.072188 Set Vref, RX VrefLevel [Byte0]: 54
7952 12:32:59.075186 [Byte1]: 54
7953 12:32:59.079494
7954 12:32:59.079580 Set Vref, RX VrefLevel [Byte0]: 55
7955 12:32:59.082773 [Byte1]: 55
7956 12:32:59.086880
7957 12:32:59.086963 Set Vref, RX VrefLevel [Byte0]: 56
7958 12:32:59.089977 [Byte1]: 56
7959 12:32:59.094337
7960 12:32:59.094447 Set Vref, RX VrefLevel [Byte0]: 57
7961 12:32:59.098094 [Byte1]: 57
7962 12:32:59.102403
7963 12:32:59.102491 Set Vref, RX VrefLevel [Byte0]: 58
7964 12:32:59.105534 [Byte1]: 58
7965 12:32:59.109819
7966 12:32:59.109915 Set Vref, RX VrefLevel [Byte0]: 59
7967 12:32:59.113090 [Byte1]: 59
7968 12:32:59.117644
7969 12:32:59.117797 Set Vref, RX VrefLevel [Byte0]: 60
7970 12:32:59.120918 [Byte1]: 60
7971 12:32:59.124925
7972 12:32:59.125037 Set Vref, RX VrefLevel [Byte0]: 61
7973 12:32:59.128164 [Byte1]: 61
7974 12:32:59.132720
7975 12:32:59.132806 Set Vref, RX VrefLevel [Byte0]: 62
7976 12:32:59.136210 [Byte1]: 62
7977 12:32:59.140236
7978 12:32:59.140382 Set Vref, RX VrefLevel [Byte0]: 63
7979 12:32:59.143513 [Byte1]: 63
7980 12:32:59.147521
7981 12:32:59.151316 Set Vref, RX VrefLevel [Byte0]: 64
7982 12:32:59.154105 [Byte1]: 64
7983 12:32:59.154198
7984 12:32:59.158001 Set Vref, RX VrefLevel [Byte0]: 65
7985 12:32:59.161388 [Byte1]: 65
7986 12:32:59.161475
7987 12:32:59.164644 Set Vref, RX VrefLevel [Byte0]: 66
7988 12:32:59.167428 [Byte1]: 66
7989 12:32:59.167512
7990 12:32:59.170863 Set Vref, RX VrefLevel [Byte0]: 67
7991 12:32:59.174305 [Byte1]: 67
7992 12:32:59.178443
7993 12:32:59.178550 Set Vref, RX VrefLevel [Byte0]: 68
7994 12:32:59.181729 [Byte1]: 68
7995 12:32:59.185938
7996 12:32:59.186078 Set Vref, RX VrefLevel [Byte0]: 69
7997 12:32:59.189101 [Byte1]: 69
7998 12:32:59.193491
7999 12:32:59.193578 Set Vref, RX VrefLevel [Byte0]: 70
8000 12:32:59.196669 [Byte1]: 70
8001 12:32:59.200948
8002 12:32:59.201038 Set Vref, RX VrefLevel [Byte0]: 71
8003 12:32:59.204170 [Byte1]: 71
8004 12:32:59.208678
8005 12:32:59.208778 Set Vref, RX VrefLevel [Byte0]: 72
8006 12:32:59.211674 [Byte1]: 72
8007 12:32:59.216267
8008 12:32:59.216371 Set Vref, RX VrefLevel [Byte0]: 73
8009 12:32:59.219537 [Byte1]: 73
8010 12:32:59.223946
8011 12:32:59.224038 Set Vref, RX VrefLevel [Byte0]: 74
8012 12:32:59.227262 [Byte1]: 74
8013 12:32:59.231896
8014 12:32:59.231990 Set Vref, RX VrefLevel [Byte0]: 75
8015 12:32:59.235262 [Byte1]: 75
8016 12:32:59.239093
8017 12:32:59.239195 Set Vref, RX VrefLevel [Byte0]: 76
8018 12:32:59.242333 [Byte1]: 76
8019 12:32:59.246744
8020 12:32:59.246852 Set Vref, RX VrefLevel [Byte0]: 77
8021 12:32:59.250234 [Byte1]: 77
8022 12:32:59.254895
8023 12:32:59.255018 Final RX Vref Byte 0 = 63 to rank0
8024 12:32:59.258130 Final RX Vref Byte 1 = 61 to rank0
8025 12:32:59.261423 Final RX Vref Byte 0 = 63 to rank1
8026 12:32:59.264723 Final RX Vref Byte 1 = 61 to rank1==
8027 12:32:59.268086 Dram Type= 6, Freq= 0, CH_0, rank 0
8028 12:32:59.274807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 12:32:59.274938 ==
8030 12:32:59.275075 DQS Delay:
8031 12:32:59.275209 DQS0 = 0, DQS1 = 0
8032 12:32:59.277347 DQM Delay:
8033 12:32:59.277438 DQM0 = 130, DQM1 = 121
8034 12:32:59.281322 DQ Delay:
8035 12:32:59.284534 DQ0 =130, DQ1 =134, DQ2 =126, DQ3 =126
8036 12:32:59.287708 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8037 12:32:59.290899 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
8038 12:32:59.294185 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
8039 12:32:59.294293
8040 12:32:59.294361
8041 12:32:59.294424
8042 12:32:59.297307 [DramC_TX_OE_Calibration] TA2
8043 12:32:59.301168 Original DQ_B0 (3 6) =30, OEN = 27
8044 12:32:59.304115 Original DQ_B1 (3 6) =30, OEN = 27
8045 12:32:59.307908 24, 0x0, End_B0=24 End_B1=24
8046 12:32:59.308021 25, 0x0, End_B0=25 End_B1=25
8047 12:32:59.311171 26, 0x0, End_B0=26 End_B1=26
8048 12:32:59.314232 27, 0x0, End_B0=27 End_B1=27
8049 12:32:59.317274 28, 0x0, End_B0=28 End_B1=28
8050 12:32:59.321141 29, 0x0, End_B0=29 End_B1=29
8051 12:32:59.321266 30, 0x0, End_B0=30 End_B1=30
8052 12:32:59.324435 31, 0x4141, End_B0=30 End_B1=30
8053 12:32:59.327691 Byte0 end_step=30 best_step=27
8054 12:32:59.330915 Byte1 end_step=30 best_step=27
8055 12:32:59.334258 Byte0 TX OE(2T, 0.5T) = (3, 3)
8056 12:32:59.337598 Byte1 TX OE(2T, 0.5T) = (3, 3)
8057 12:32:59.337704
8058 12:32:59.337772
8059 12:32:59.344146 [DQSOSCAuto] RK0, (LSB)MR18= 0x1408, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8060 12:32:59.347117 CH0 RK0: MR19=303, MR18=1408
8061 12:32:59.353889 CH0_RK0: MR19=0x303, MR18=0x1408, DQSOSC=399, MR23=63, INC=23, DEC=15
8062 12:32:59.354022
8063 12:32:59.357049 ----->DramcWriteLeveling(PI) begin...
8064 12:32:59.357145 ==
8065 12:32:59.360480 Dram Type= 6, Freq= 0, CH_0, rank 1
8066 12:32:59.364258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8067 12:32:59.364368 ==
8068 12:32:59.366963 Write leveling (Byte 0): 34 => 34
8069 12:32:59.370289 Write leveling (Byte 1): 26 => 26
8070 12:32:59.373555 DramcWriteLeveling(PI) end<-----
8071 12:32:59.373653
8072 12:32:59.373721 ==
8073 12:32:59.376958 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 12:32:59.380256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 12:32:59.380357 ==
8076 12:32:59.383363 [Gating] SW mode calibration
8077 12:32:59.390240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8078 12:32:59.397053 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8079 12:32:59.400092 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 12:32:59.406779 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 12:32:59.410614 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 12:32:59.413268 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8083 12:32:59.420423 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8084 12:32:59.423534 1 4 20 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
8085 12:32:59.426728 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8086 12:32:59.430047 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8087 12:32:59.436682 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8088 12:32:59.439985 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8089 12:32:59.443142 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8090 12:32:59.449698 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8091 12:32:59.453174 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8092 12:32:59.456252 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8093 12:32:59.463530 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8094 12:32:59.466822 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8095 12:32:59.469529 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8096 12:32:59.476716 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 12:32:59.479935 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8098 12:32:59.483271 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8099 12:32:59.489285 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8100 12:32:59.493247 1 6 20 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
8101 12:32:59.496463 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 12:32:59.502737 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8103 12:32:59.505884 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 12:32:59.509707 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8105 12:32:59.515947 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 12:32:59.519623 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8107 12:32:59.522749 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8108 12:32:59.529201 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8109 12:32:59.532402 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 12:32:59.535683 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 12:32:59.542290 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 12:32:59.545615 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 12:32:59.549612 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 12:32:59.556209 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 12:32:59.559305 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 12:32:59.562612 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 12:32:59.569312 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 12:32:59.572651 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 12:32:59.575840 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 12:32:59.582594 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 12:32:59.585953 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8122 12:32:59.589341 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8123 12:32:59.595962 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8124 12:32:59.596089 Total UI for P1: 0, mck2ui 16
8125 12:32:59.601802 best dqsien dly found for B0: ( 1, 9, 10)
8126 12:32:59.605571 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8127 12:32:59.608854 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8128 12:32:59.611937 Total UI for P1: 0, mck2ui 16
8129 12:32:59.615016 best dqsien dly found for B1: ( 1, 9, 18)
8130 12:32:59.618922 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8131 12:32:59.621967 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8132 12:32:59.622081
8133 12:32:59.628795 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8134 12:32:59.632110 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8135 12:32:59.635028 [Gating] SW calibration Done
8136 12:32:59.635154 ==
8137 12:32:59.638176 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 12:32:59.642073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 12:32:59.642184 ==
8140 12:32:59.642255 RX Vref Scan: 0
8141 12:32:59.642317
8142 12:32:59.645085 RX Vref 0 -> 0, step: 1
8143 12:32:59.645201
8144 12:32:59.648549 RX Delay 0 -> 252, step: 8
8145 12:32:59.651718 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8146 12:32:59.655102 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8147 12:32:59.661806 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8148 12:32:59.664918 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8149 12:32:59.668162 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8150 12:32:59.671325 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8151 12:32:59.674632 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8152 12:32:59.678023 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8153 12:32:59.685171 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8154 12:32:59.688480 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8155 12:32:59.691840 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8156 12:32:59.694606 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8157 12:32:59.698613 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8158 12:32:59.705070 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8159 12:32:59.708162 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8160 12:32:59.711533 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8161 12:32:59.711667 ==
8162 12:32:59.714622 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 12:32:59.718276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 12:32:59.721557 ==
8165 12:32:59.721684 DQS Delay:
8166 12:32:59.721782 DQS0 = 0, DQS1 = 0
8167 12:32:59.724647 DQM Delay:
8168 12:32:59.724736 DQM0 = 131, DQM1 = 123
8169 12:32:59.728400 DQ Delay:
8170 12:32:59.731562 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8171 12:32:59.734886 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8172 12:32:59.738110 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
8173 12:32:59.741345 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8174 12:32:59.741472
8175 12:32:59.741569
8176 12:32:59.741659 ==
8177 12:32:59.744482 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 12:32:59.748483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 12:32:59.748614 ==
8180 12:32:59.748702
8181 12:32:59.751126
8182 12:32:59.751216 TX Vref Scan disable
8183 12:32:59.754535 == TX Byte 0 ==
8184 12:32:59.757832 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8185 12:32:59.761050 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8186 12:32:59.765011 == TX Byte 1 ==
8187 12:32:59.767615 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8188 12:32:59.771520 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8189 12:32:59.771657 ==
8190 12:32:59.774710 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 12:32:59.781165 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 12:32:59.781297 ==
8193 12:32:59.795180
8194 12:32:59.798546 TX Vref early break, caculate TX vref
8195 12:32:59.801275 TX Vref=16, minBit 5, minWin=22, winSum=371
8196 12:32:59.805150 TX Vref=18, minBit 9, minWin=22, winSum=378
8197 12:32:59.808504 TX Vref=20, minBit 8, minWin=23, winSum=389
8198 12:32:59.811640 TX Vref=22, minBit 9, minWin=23, winSum=394
8199 12:32:59.814772 TX Vref=24, minBit 4, minWin=24, winSum=407
8200 12:32:59.821198 TX Vref=26, minBit 4, minWin=24, winSum=412
8201 12:32:59.824997 TX Vref=28, minBit 2, minWin=25, winSum=418
8202 12:32:59.828072 TX Vref=30, minBit 4, minWin=25, winSum=419
8203 12:32:59.831117 TX Vref=32, minBit 0, minWin=25, winSum=411
8204 12:32:59.834924 TX Vref=34, minBit 1, minWin=24, winSum=402
8205 12:32:59.837993 TX Vref=36, minBit 0, minWin=23, winSum=393
8206 12:32:59.844764 [TxChooseVref] Worse bit 4, Min win 25, Win sum 419, Final Vref 30
8207 12:32:59.844875
8208 12:32:59.848079 Final TX Range 0 Vref 30
8209 12:32:59.848196
8210 12:32:59.848291 ==
8211 12:32:59.851206 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 12:32:59.854391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 12:32:59.854490 ==
8214 12:32:59.854554
8215 12:32:59.857635
8216 12:32:59.857754 TX Vref Scan disable
8217 12:32:59.864281 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8218 12:32:59.864389 == TX Byte 0 ==
8219 12:32:59.868223 u2DelayCellOfst[0]=14 cells (4 PI)
8220 12:32:59.870916 u2DelayCellOfst[1]=17 cells (5 PI)
8221 12:32:59.874847 u2DelayCellOfst[2]=10 cells (3 PI)
8222 12:32:59.877431 u2DelayCellOfst[3]=10 cells (3 PI)
8223 12:32:59.880904 u2DelayCellOfst[4]=10 cells (3 PI)
8224 12:32:59.884284 u2DelayCellOfst[5]=0 cells (0 PI)
8225 12:32:59.887486 u2DelayCellOfst[6]=17 cells (5 PI)
8226 12:32:59.890801 u2DelayCellOfst[7]=17 cells (5 PI)
8227 12:32:59.894224 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8228 12:32:59.897523 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8229 12:32:59.900877 == TX Byte 1 ==
8230 12:32:59.904040 u2DelayCellOfst[8]=0 cells (0 PI)
8231 12:32:59.907311 u2DelayCellOfst[9]=0 cells (0 PI)
8232 12:32:59.910578 u2DelayCellOfst[10]=7 cells (2 PI)
8233 12:32:59.914399 u2DelayCellOfst[11]=0 cells (0 PI)
8234 12:32:59.914518 u2DelayCellOfst[12]=10 cells (3 PI)
8235 12:32:59.917499 u2DelayCellOfst[13]=7 cells (2 PI)
8236 12:32:59.920576 u2DelayCellOfst[14]=14 cells (4 PI)
8237 12:32:59.924434 u2DelayCellOfst[15]=10 cells (3 PI)
8238 12:32:59.930939 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8239 12:32:59.933911 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8240 12:32:59.934020 DramC Write-DBI on
8241 12:32:59.937804 ==
8242 12:32:59.937907 Dram Type= 6, Freq= 0, CH_0, rank 1
8243 12:32:59.944381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 12:32:59.944488 ==
8245 12:32:59.944584
8246 12:32:59.944672
8247 12:32:59.947424 TX Vref Scan disable
8248 12:32:59.947502 == TX Byte 0 ==
8249 12:32:59.953858 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8250 12:32:59.953961 == TX Byte 1 ==
8251 12:32:59.956969 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8252 12:32:59.960304 DramC Write-DBI off
8253 12:32:59.960406
8254 12:32:59.960503 [DATLAT]
8255 12:32:59.964128 Freq=1600, CH0 RK1
8256 12:32:59.964204
8257 12:32:59.964274 DATLAT Default: 0xf
8258 12:32:59.966738 0, 0xFFFF, sum = 0
8259 12:32:59.966838 1, 0xFFFF, sum = 0
8260 12:32:59.970672 2, 0xFFFF, sum = 0
8261 12:32:59.970778 3, 0xFFFF, sum = 0
8262 12:32:59.973411 4, 0xFFFF, sum = 0
8263 12:32:59.973522 5, 0xFFFF, sum = 0
8264 12:32:59.977444 6, 0xFFFF, sum = 0
8265 12:32:59.977599 7, 0xFFFF, sum = 0
8266 12:32:59.980543 8, 0xFFFF, sum = 0
8267 12:32:59.983981 9, 0xFFFF, sum = 0
8268 12:32:59.984114 10, 0xFFFF, sum = 0
8269 12:32:59.987308 11, 0xFFFF, sum = 0
8270 12:32:59.987433 12, 0xFFFF, sum = 0
8271 12:32:59.989963 13, 0xFFFF, sum = 0
8272 12:32:59.990078 14, 0x0, sum = 1
8273 12:32:59.993389 15, 0x0, sum = 2
8274 12:32:59.993511 16, 0x0, sum = 3
8275 12:32:59.996724 17, 0x0, sum = 4
8276 12:32:59.996846 best_step = 15
8277 12:32:59.996943
8278 12:32:59.997036 ==
8279 12:32:59.999990 Dram Type= 6, Freq= 0, CH_0, rank 1
8280 12:33:00.003277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8281 12:33:00.003409 ==
8282 12:33:00.006727 RX Vref Scan: 0
8283 12:33:00.006800
8284 12:33:00.010044 RX Vref 0 -> 0, step: 1
8285 12:33:00.010154
8286 12:33:00.010247 RX Delay 11 -> 252, step: 4
8287 12:33:00.017390 iDelay=191, Bit 0, Center 128 (71 ~ 186) 116
8288 12:33:00.020687 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8289 12:33:00.023893 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8290 12:33:00.027308 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8291 12:33:00.030531 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8292 12:33:00.037696 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8293 12:33:00.040704 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8294 12:33:00.043844 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8295 12:33:00.047138 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8296 12:33:00.050644 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8297 12:33:00.057156 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8298 12:33:00.060503 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8299 12:33:00.063692 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8300 12:33:00.067057 iDelay=191, Bit 13, Center 128 (71 ~ 186) 116
8301 12:33:00.073689 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8302 12:33:00.076903 iDelay=191, Bit 15, Center 132 (75 ~ 190) 116
8303 12:33:00.077013 ==
8304 12:33:00.080365 Dram Type= 6, Freq= 0, CH_0, rank 1
8305 12:33:00.083770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 12:33:00.083873 ==
8307 12:33:00.087204 DQS Delay:
8308 12:33:00.087300 DQS0 = 0, DQS1 = 0
8309 12:33:00.087404 DQM Delay:
8310 12:33:00.090580 DQM0 = 128, DQM1 = 122
8311 12:33:00.090651 DQ Delay:
8312 12:33:00.093897 DQ0 =128, DQ1 =130, DQ2 =124, DQ3 =126
8313 12:33:00.097317 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8314 12:33:00.100629 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8315 12:33:00.106761 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8316 12:33:00.106845
8317 12:33:00.106911
8318 12:33:00.106972
8319 12:33:00.109988 [DramC_TX_OE_Calibration] TA2
8320 12:33:00.110087 Original DQ_B0 (3 6) =30, OEN = 27
8321 12:33:00.113505 Original DQ_B1 (3 6) =30, OEN = 27
8322 12:33:00.116839 24, 0x0, End_B0=24 End_B1=24
8323 12:33:00.120281 25, 0x0, End_B0=25 End_B1=25
8324 12:33:00.123570 26, 0x0, End_B0=26 End_B1=26
8325 12:33:00.126854 27, 0x0, End_B0=27 End_B1=27
8326 12:33:00.126924 28, 0x0, End_B0=28 End_B1=28
8327 12:33:00.130252 29, 0x0, End_B0=29 End_B1=29
8328 12:33:00.133586 30, 0x0, End_B0=30 End_B1=30
8329 12:33:00.136743 31, 0x4141, End_B0=30 End_B1=30
8330 12:33:00.139872 Byte0 end_step=30 best_step=27
8331 12:33:00.139976 Byte1 end_step=30 best_step=27
8332 12:33:00.143110 Byte0 TX OE(2T, 0.5T) = (3, 3)
8333 12:33:00.146465 Byte1 TX OE(2T, 0.5T) = (3, 3)
8334 12:33:00.146611
8335 12:33:00.146737
8336 12:33:00.156577 [DQSOSCAuto] RK1, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8337 12:33:00.156740 CH0 RK1: MR19=303, MR18=180D
8338 12:33:00.163118 CH0_RK1: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8339 12:33:00.166282 [RxdqsGatingPostProcess] freq 1600
8340 12:33:00.172964 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8341 12:33:00.176235 best DQS0 dly(2T, 0.5T) = (1, 1)
8342 12:33:00.179710 best DQS1 dly(2T, 0.5T) = (1, 1)
8343 12:33:00.183002 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8344 12:33:00.186431 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8345 12:33:00.189825 best DQS0 dly(2T, 0.5T) = (1, 1)
8346 12:33:00.190156 best DQS1 dly(2T, 0.5T) = (1, 1)
8347 12:33:00.193174 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8348 12:33:00.195888 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8349 12:33:00.199693 Pre-setting of DQS Precalculation
8350 12:33:00.206368 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8351 12:33:00.206740 ==
8352 12:33:00.209587 Dram Type= 6, Freq= 0, CH_1, rank 0
8353 12:33:00.212925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8354 12:33:00.213258 ==
8355 12:33:00.218901 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8356 12:33:00.222938 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8357 12:33:00.225911 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8358 12:33:00.232689 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8359 12:33:00.241788 [CA 0] Center 43 (15~72) winsize 58
8360 12:33:00.245027 [CA 1] Center 42 (14~71) winsize 58
8361 12:33:00.248906 [CA 2] Center 38 (10~67) winsize 58
8362 12:33:00.252144 [CA 3] Center 37 (8~66) winsize 59
8363 12:33:00.255820 [CA 4] Center 38 (9~67) winsize 59
8364 12:33:00.258216 [CA 5] Center 37 (8~66) winsize 59
8365 12:33:00.258570
8366 12:33:00.261995 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8367 12:33:00.262386
8368 12:33:00.265214 [CATrainingPosCal] consider 1 rank data
8369 12:33:00.268492 u2DelayCellTimex100 = 275/100 ps
8370 12:33:00.275067 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8371 12:33:00.278230 CA1 delay=42 (14~71),Diff = 5 PI (17 cell)
8372 12:33:00.281545 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8373 12:33:00.285095 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8374 12:33:00.288409 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8375 12:33:00.291698 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8376 12:33:00.292058
8377 12:33:00.295109 CA PerBit enable=1, Macro0, CA PI delay=37
8378 12:33:00.295567
8379 12:33:00.298368 [CBTSetCACLKResult] CA Dly = 37
8380 12:33:00.301671 CS Dly: 9 (0~40)
8381 12:33:00.305103 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8382 12:33:00.308309 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8383 12:33:00.308668 ==
8384 12:33:00.311722 Dram Type= 6, Freq= 0, CH_1, rank 1
8385 12:33:00.314878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8386 12:33:00.318322 ==
8387 12:33:00.321594 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8388 12:33:00.324911 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8389 12:33:00.331597 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8390 12:33:00.337441 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8391 12:33:00.345148 [CA 0] Center 43 (14~72) winsize 59
8392 12:33:00.347894 [CA 1] Center 43 (14~72) winsize 59
8393 12:33:00.351856 [CA 2] Center 38 (9~67) winsize 59
8394 12:33:00.355274 [CA 3] Center 37 (8~67) winsize 60
8395 12:33:00.358267 [CA 4] Center 38 (8~68) winsize 61
8396 12:33:00.361613 [CA 5] Center 37 (8~66) winsize 59
8397 12:33:00.361707
8398 12:33:00.364799 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8399 12:33:00.364903
8400 12:33:00.368173 [CATrainingPosCal] consider 2 rank data
8401 12:33:00.371499 u2DelayCellTimex100 = 275/100 ps
8402 12:33:00.374733 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8403 12:33:00.381187 CA1 delay=42 (14~71),Diff = 5 PI (17 cell)
8404 12:33:00.384398 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8405 12:33:00.387779 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8406 12:33:00.391338 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8407 12:33:00.394758 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8408 12:33:00.395128
8409 12:33:00.397983 CA PerBit enable=1, Macro0, CA PI delay=37
8410 12:33:00.398351
8411 12:33:00.401365 [CBTSetCACLKResult] CA Dly = 37
8412 12:33:00.404716 CS Dly: 11 (0~44)
8413 12:33:00.408215 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8414 12:33:00.411616 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8415 12:33:00.411983
8416 12:33:00.414915 ----->DramcWriteLeveling(PI) begin...
8417 12:33:00.415287 ==
8418 12:33:00.418326 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 12:33:00.424998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 12:33:00.425483 ==
8421 12:33:00.428223 Write leveling (Byte 0): 25 => 25
8422 12:33:00.428632 Write leveling (Byte 1): 28 => 28
8423 12:33:00.431670 DramcWriteLeveling(PI) end<-----
8424 12:33:00.432117
8425 12:33:00.432451 ==
8426 12:33:00.434855 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 12:33:00.441292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 12:33:00.441685 ==
8429 12:33:00.445087 [Gating] SW mode calibration
8430 12:33:00.451408 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8431 12:33:00.454761 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8432 12:33:00.461306 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 12:33:00.464609 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 12:33:00.467923 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 12:33:00.475019 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 12:33:00.478221 1 4 16 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
8437 12:33:00.481484 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8438 12:33:00.487884 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8439 12:33:00.491243 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8440 12:33:00.494502 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8441 12:33:00.501261 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8442 12:33:00.504561 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8443 12:33:00.507937 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8444 12:33:00.514731 1 5 16 | B1->B0 | 2a2a 2f2f | 0 1 | (0 1) (1 0)
8445 12:33:00.517737 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8446 12:33:00.521128 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8447 12:33:00.524612 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 12:33:00.530644 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 12:33:00.534084 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 12:33:00.537370 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 12:33:00.543860 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 12:33:00.547858 1 6 16 | B1->B0 | 3030 2b2b | 1 0 | (0 0) (0 0)
8453 12:33:00.551199 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 12:33:00.557464 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8455 12:33:00.560773 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 12:33:00.563922 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 12:33:00.570653 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 12:33:00.574060 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 12:33:00.577142 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 12:33:00.583637 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8461 12:33:00.586916 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8462 12:33:00.590218 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 12:33:00.596835 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 12:33:00.600153 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 12:33:00.603464 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 12:33:00.610167 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 12:33:00.613523 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 12:33:00.616945 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 12:33:00.623655 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 12:33:00.626981 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 12:33:00.630400 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 12:33:00.636961 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 12:33:00.640403 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 12:33:00.643630 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 12:33:00.650386 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8476 12:33:00.653667 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8477 12:33:00.656793 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8478 12:33:00.660352 Total UI for P1: 0, mck2ui 16
8479 12:33:00.663780 best dqsien dly found for B0: ( 1, 9, 14)
8480 12:33:00.667037 Total UI for P1: 0, mck2ui 16
8481 12:33:00.670238 best dqsien dly found for B1: ( 1, 9, 16)
8482 12:33:00.673398 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8483 12:33:00.676678 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8484 12:33:00.677042
8485 12:33:00.680012 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8486 12:33:00.687159 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8487 12:33:00.687606 [Gating] SW calibration Done
8488 12:33:00.690375 ==
8489 12:33:00.690768 Dram Type= 6, Freq= 0, CH_1, rank 0
8490 12:33:00.696904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8491 12:33:00.697301 ==
8492 12:33:00.697612 RX Vref Scan: 0
8493 12:33:00.697905
8494 12:33:00.700311 RX Vref 0 -> 0, step: 1
8495 12:33:00.700700
8496 12:33:00.703593 RX Delay 0 -> 252, step: 8
8497 12:33:00.707034 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8498 12:33:00.710314 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8499 12:33:00.713695 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8500 12:33:00.719794 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8501 12:33:00.723660 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8502 12:33:00.726280 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8503 12:33:00.729608 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8504 12:33:00.733480 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8505 12:33:00.740278 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8506 12:33:00.743398 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8507 12:33:00.746847 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8508 12:33:00.750126 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8509 12:33:00.753391 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8510 12:33:00.760069 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8511 12:33:00.763254 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8512 12:33:00.766450 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8513 12:33:00.766844 ==
8514 12:33:00.769618 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 12:33:00.772899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 12:33:00.773293 ==
8517 12:33:00.776689 DQS Delay:
8518 12:33:00.777083 DQS0 = 0, DQS1 = 0
8519 12:33:00.779883 DQM Delay:
8520 12:33:00.780433 DQM0 = 135, DQM1 = 127
8521 12:33:00.780797 DQ Delay:
8522 12:33:00.785958 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8523 12:33:00.789312 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =131
8524 12:33:00.793277 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8525 12:33:00.795938 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8526 12:33:00.796034
8527 12:33:00.796108
8528 12:33:00.796178 ==
8529 12:33:00.799882 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 12:33:00.802502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 12:33:00.802605 ==
8532 12:33:00.802687
8533 12:33:00.802764
8534 12:33:00.805931 TX Vref Scan disable
8535 12:33:00.809297 == TX Byte 0 ==
8536 12:33:00.812505 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8537 12:33:00.815811 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8538 12:33:00.819926 == TX Byte 1 ==
8539 12:33:00.822494 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8540 12:33:00.825923 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8541 12:33:00.826099 ==
8542 12:33:00.829237 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 12:33:00.832609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 12:33:00.835986 ==
8545 12:33:00.847222
8546 12:33:00.850565 TX Vref early break, caculate TX vref
8547 12:33:00.854391 TX Vref=16, minBit 5, minWin=21, winSum=362
8548 12:33:00.857932 TX Vref=18, minBit 8, minWin=21, winSum=372
8549 12:33:00.861170 TX Vref=20, minBit 8, minWin=22, winSum=384
8550 12:33:00.864579 TX Vref=22, minBit 8, minWin=23, winSum=395
8551 12:33:00.867259 TX Vref=24, minBit 8, minWin=23, winSum=401
8552 12:33:00.874482 TX Vref=26, minBit 8, minWin=24, winSum=410
8553 12:33:00.877203 TX Vref=28, minBit 8, minWin=25, winSum=420
8554 12:33:00.881136 TX Vref=30, minBit 1, minWin=25, winSum=418
8555 12:33:00.884294 TX Vref=32, minBit 8, minWin=24, winSum=409
8556 12:33:00.887655 TX Vref=34, minBit 8, minWin=23, winSum=398
8557 12:33:00.894254 [TxChooseVref] Worse bit 8, Min win 25, Win sum 420, Final Vref 28
8558 12:33:00.894767
8559 12:33:00.897572 Final TX Range 0 Vref 28
8560 12:33:00.898143
8561 12:33:00.898537 ==
8562 12:33:00.900894 Dram Type= 6, Freq= 0, CH_1, rank 0
8563 12:33:00.904227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8564 12:33:00.904792 ==
8565 12:33:00.905223
8566 12:33:00.905567
8567 12:33:00.907334 TX Vref Scan disable
8568 12:33:00.914196 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8569 12:33:00.914759 == TX Byte 0 ==
8570 12:33:00.917487 u2DelayCellOfst[0]=17 cells (5 PI)
8571 12:33:00.920784 u2DelayCellOfst[1]=10 cells (3 PI)
8572 12:33:00.924182 u2DelayCellOfst[2]=0 cells (0 PI)
8573 12:33:00.927454 u2DelayCellOfst[3]=7 cells (2 PI)
8574 12:33:00.930774 u2DelayCellOfst[4]=10 cells (3 PI)
8575 12:33:00.934158 u2DelayCellOfst[5]=21 cells (6 PI)
8576 12:33:00.934865 u2DelayCellOfst[6]=17 cells (5 PI)
8577 12:33:00.937420 u2DelayCellOfst[7]=7 cells (2 PI)
8578 12:33:00.943936 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8579 12:33:00.947185 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8580 12:33:00.947671 == TX Byte 1 ==
8581 12:33:00.950533 u2DelayCellOfst[8]=0 cells (0 PI)
8582 12:33:00.953855 u2DelayCellOfst[9]=7 cells (2 PI)
8583 12:33:00.957152 u2DelayCellOfst[10]=10 cells (3 PI)
8584 12:33:00.960285 u2DelayCellOfst[11]=7 cells (2 PI)
8585 12:33:00.964126 u2DelayCellOfst[12]=14 cells (4 PI)
8586 12:33:00.966895 u2DelayCellOfst[13]=17 cells (5 PI)
8587 12:33:00.970211 u2DelayCellOfst[14]=17 cells (5 PI)
8588 12:33:00.974103 u2DelayCellOfst[15]=17 cells (5 PI)
8589 12:33:00.976846 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8590 12:33:00.983762 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8591 12:33:00.984191 DramC Write-DBI on
8592 12:33:00.984558 ==
8593 12:33:00.986986 Dram Type= 6, Freq= 0, CH_1, rank 0
8594 12:33:00.990070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8595 12:33:00.990652 ==
8596 12:33:00.993864
8597 12:33:00.994286
8598 12:33:00.994595 TX Vref Scan disable
8599 12:33:00.997077 == TX Byte 0 ==
8600 12:33:01.000349 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8601 12:33:01.003607 == TX Byte 1 ==
8602 12:33:01.006970 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8603 12:33:01.007452 DramC Write-DBI off
8604 12:33:01.010301
8605 12:33:01.010691 [DATLAT]
8606 12:33:01.011004 Freq=1600, CH1 RK0
8607 12:33:01.011298
8608 12:33:01.013598 DATLAT Default: 0xf
8609 12:33:01.013995 0, 0xFFFF, sum = 0
8610 12:33:01.016914 1, 0xFFFF, sum = 0
8611 12:33:01.017315 2, 0xFFFF, sum = 0
8612 12:33:01.020288 3, 0xFFFF, sum = 0
8613 12:33:01.020687 4, 0xFFFF, sum = 0
8614 12:33:01.023692 5, 0xFFFF, sum = 0
8615 12:33:01.027052 6, 0xFFFF, sum = 0
8616 12:33:01.027484 7, 0xFFFF, sum = 0
8617 12:33:01.030472 8, 0xFFFF, sum = 0
8618 12:33:01.030886 9, 0xFFFF, sum = 0
8619 12:33:01.033176 10, 0xFFFF, sum = 0
8620 12:33:01.033572 11, 0xFFFF, sum = 0
8621 12:33:01.037063 12, 0xFFFF, sum = 0
8622 12:33:01.037458 13, 0xFFFF, sum = 0
8623 12:33:01.040390 14, 0x0, sum = 1
8624 12:33:01.040786 15, 0x0, sum = 2
8625 12:33:01.043560 16, 0x0, sum = 3
8626 12:33:01.043954 17, 0x0, sum = 4
8627 12:33:01.046875 best_step = 15
8628 12:33:01.047264
8629 12:33:01.047609 ==
8630 12:33:01.050338 Dram Type= 6, Freq= 0, CH_1, rank 0
8631 12:33:01.053611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8632 12:33:01.054048 ==
8633 12:33:01.054360 RX Vref Scan: 1
8634 12:33:01.057107
8635 12:33:01.057498 Set Vref Range= 24 -> 127
8636 12:33:01.057807
8637 12:33:01.060257 RX Vref 24 -> 127, step: 1
8638 12:33:01.060649
8639 12:33:01.063022 RX Delay 11 -> 252, step: 4
8640 12:33:01.063451
8641 12:33:01.066334 Set Vref, RX VrefLevel [Byte0]: 24
8642 12:33:01.069799 [Byte1]: 24
8643 12:33:01.070191
8644 12:33:01.073045 Set Vref, RX VrefLevel [Byte0]: 25
8645 12:33:01.076349 [Byte1]: 25
8646 12:33:01.076754
8647 12:33:01.079625 Set Vref, RX VrefLevel [Byte0]: 26
8648 12:33:01.082985 [Byte1]: 26
8649 12:33:01.087058
8650 12:33:01.087598 Set Vref, RX VrefLevel [Byte0]: 27
8651 12:33:01.090497 [Byte1]: 27
8652 12:33:01.094818
8653 12:33:01.095390 Set Vref, RX VrefLevel [Byte0]: 28
8654 12:33:01.097959 [Byte1]: 28
8655 12:33:01.102613
8656 12:33:01.103037 Set Vref, RX VrefLevel [Byte0]: 29
8657 12:33:01.105854 [Byte1]: 29
8658 12:33:01.109871
8659 12:33:01.110427 Set Vref, RX VrefLevel [Byte0]: 30
8660 12:33:01.113064 [Byte1]: 30
8661 12:33:01.117456
8662 12:33:01.117971 Set Vref, RX VrefLevel [Byte0]: 31
8663 12:33:01.120976 [Byte1]: 31
8664 12:33:01.124988
8665 12:33:01.125557 Set Vref, RX VrefLevel [Byte0]: 32
8666 12:33:01.128341 [Byte1]: 32
8667 12:33:01.132990
8668 12:33:01.133407 Set Vref, RX VrefLevel [Byte0]: 33
8669 12:33:01.136530 [Byte1]: 33
8670 12:33:01.140361
8671 12:33:01.140759 Set Vref, RX VrefLevel [Byte0]: 34
8672 12:33:01.143664 [Byte1]: 34
8673 12:33:01.148370
8674 12:33:01.148927 Set Vref, RX VrefLevel [Byte0]: 35
8675 12:33:01.151221 [Byte1]: 35
8676 12:33:01.155179
8677 12:33:01.155280 Set Vref, RX VrefLevel [Byte0]: 36
8678 12:33:01.158630 [Byte1]: 36
8679 12:33:01.162653
8680 12:33:01.162736 Set Vref, RX VrefLevel [Byte0]: 37
8681 12:33:01.166124 [Byte1]: 37
8682 12:33:01.170902
8683 12:33:01.171069 Set Vref, RX VrefLevel [Byte0]: 38
8684 12:33:01.174241 [Byte1]: 38
8685 12:33:01.178349
8686 12:33:01.178466 Set Vref, RX VrefLevel [Byte0]: 39
8687 12:33:01.181573 [Byte1]: 39
8688 12:33:01.185538
8689 12:33:01.185652 Set Vref, RX VrefLevel [Byte0]: 40
8690 12:33:01.189484 [Byte1]: 40
8691 12:33:01.193339
8692 12:33:01.193509 Set Vref, RX VrefLevel [Byte0]: 41
8693 12:33:01.196547 [Byte1]: 41
8694 12:33:01.201171
8695 12:33:01.201371 Set Vref, RX VrefLevel [Byte0]: 42
8696 12:33:01.207529 [Byte1]: 42
8697 12:33:01.207707
8698 12:33:01.210908 Set Vref, RX VrefLevel [Byte0]: 43
8699 12:33:01.214260 [Byte1]: 43
8700 12:33:01.214467
8701 12:33:01.217679 Set Vref, RX VrefLevel [Byte0]: 44
8702 12:33:01.220884 [Byte1]: 44
8703 12:33:01.224067
8704 12:33:01.224448 Set Vref, RX VrefLevel [Byte0]: 45
8705 12:33:01.227447 [Byte1]: 45
8706 12:33:01.231610
8707 12:33:01.232074 Set Vref, RX VrefLevel [Byte0]: 46
8708 12:33:01.234909 [Byte1]: 46
8709 12:33:01.239390
8710 12:33:01.239936 Set Vref, RX VrefLevel [Byte0]: 47
8711 12:33:01.242754 [Byte1]: 47
8712 12:33:01.246672
8713 12:33:01.247280 Set Vref, RX VrefLevel [Byte0]: 48
8714 12:33:01.250118 [Byte1]: 48
8715 12:33:01.254813
8716 12:33:01.255411 Set Vref, RX VrefLevel [Byte0]: 49
8717 12:33:01.258054 [Byte1]: 49
8718 12:33:01.261944
8719 12:33:01.262544 Set Vref, RX VrefLevel [Byte0]: 50
8720 12:33:01.265376 [Byte1]: 50
8721 12:33:01.270038
8722 12:33:01.270630 Set Vref, RX VrefLevel [Byte0]: 51
8723 12:33:01.273277 [Byte1]: 51
8724 12:33:01.277413
8725 12:33:01.278009 Set Vref, RX VrefLevel [Byte0]: 52
8726 12:33:01.280667 [Byte1]: 52
8727 12:33:01.285275
8728 12:33:01.285897 Set Vref, RX VrefLevel [Byte0]: 53
8729 12:33:01.288457 [Byte1]: 53
8730 12:33:01.292553
8731 12:33:01.292985 Set Vref, RX VrefLevel [Byte0]: 54
8732 12:33:01.295824 [Byte1]: 54
8733 12:33:01.300243
8734 12:33:01.300836 Set Vref, RX VrefLevel [Byte0]: 55
8735 12:33:01.306628 [Byte1]: 55
8736 12:33:01.307234
8737 12:33:01.309834 Set Vref, RX VrefLevel [Byte0]: 56
8738 12:33:01.313057 [Byte1]: 56
8739 12:33:01.313610
8740 12:33:01.316474 Set Vref, RX VrefLevel [Byte0]: 57
8741 12:33:01.320463 [Byte1]: 57
8742 12:33:01.320897
8743 12:33:01.323799 Set Vref, RX VrefLevel [Byte0]: 58
8744 12:33:01.326951 [Byte1]: 58
8745 12:33:01.330879
8746 12:33:01.331303 Set Vref, RX VrefLevel [Byte0]: 59
8747 12:33:01.334148 [Byte1]: 59
8748 12:33:01.338119
8749 12:33:01.338546 Set Vref, RX VrefLevel [Byte0]: 60
8750 12:33:01.341574 [Byte1]: 60
8751 12:33:01.346187
8752 12:33:01.346608 Set Vref, RX VrefLevel [Byte0]: 61
8753 12:33:01.349531 [Byte1]: 61
8754 12:33:01.353356
8755 12:33:01.353781 Set Vref, RX VrefLevel [Byte0]: 62
8756 12:33:01.356859 [Byte1]: 62
8757 12:33:01.360844
8758 12:33:01.361269 Set Vref, RX VrefLevel [Byte0]: 63
8759 12:33:01.364164 [Byte1]: 63
8760 12:33:01.368933
8761 12:33:01.369361 Set Vref, RX VrefLevel [Byte0]: 64
8762 12:33:01.372366 [Byte1]: 64
8763 12:33:01.376265
8764 12:33:01.376698 Set Vref, RX VrefLevel [Byte0]: 65
8765 12:33:01.379419 [Byte1]: 65
8766 12:33:01.384162
8767 12:33:01.384629 Set Vref, RX VrefLevel [Byte0]: 66
8768 12:33:01.387533 [Byte1]: 66
8769 12:33:01.391501
8770 12:33:01.391946 Set Vref, RX VrefLevel [Byte0]: 67
8771 12:33:01.394857 [Byte1]: 67
8772 12:33:01.399424
8773 12:33:01.399851 Set Vref, RX VrefLevel [Byte0]: 68
8774 12:33:01.402600 [Byte1]: 68
8775 12:33:01.406522
8776 12:33:01.406912 Set Vref, RX VrefLevel [Byte0]: 69
8777 12:33:01.409834 [Byte1]: 69
8778 12:33:01.414222
8779 12:33:01.414616 Set Vref, RX VrefLevel [Byte0]: 70
8780 12:33:01.417747 [Byte1]: 70
8781 12:33:01.421514
8782 12:33:01.421598 Set Vref, RX VrefLevel [Byte0]: 71
8783 12:33:01.424934 [Byte1]: 71
8784 12:33:01.429381
8785 12:33:01.429463 Set Vref, RX VrefLevel [Byte0]: 72
8786 12:33:01.432582 [Byte1]: 72
8787 12:33:01.437272
8788 12:33:01.437354 Set Vref, RX VrefLevel [Byte0]: 73
8789 12:33:01.440686 [Byte1]: 73
8790 12:33:01.444723
8791 12:33:01.444807 Final RX Vref Byte 0 = 57 to rank0
8792 12:33:01.448122 Final RX Vref Byte 1 = 55 to rank0
8793 12:33:01.451480 Final RX Vref Byte 0 = 57 to rank1
8794 12:33:01.454740 Final RX Vref Byte 1 = 55 to rank1==
8795 12:33:01.457535 Dram Type= 6, Freq= 0, CH_1, rank 0
8796 12:33:01.464204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8797 12:33:01.464309 ==
8798 12:33:01.464392 DQS Delay:
8799 12:33:01.464469 DQS0 = 0, DQS1 = 0
8800 12:33:01.467677 DQM Delay:
8801 12:33:01.467789 DQM0 = 131, DQM1 = 124
8802 12:33:01.470809 DQ Delay:
8803 12:33:01.474200 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8804 12:33:01.477597 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8805 12:33:01.480786 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =118
8806 12:33:01.484118 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8807 12:33:01.484274
8808 12:33:01.484394
8809 12:33:01.484529
8810 12:33:01.487368 [DramC_TX_OE_Calibration] TA2
8811 12:33:01.490727 Original DQ_B0 (3 6) =30, OEN = 27
8812 12:33:01.494237 Original DQ_B1 (3 6) =30, OEN = 27
8813 12:33:01.497545 24, 0x0, End_B0=24 End_B1=24
8814 12:33:01.497802 25, 0x0, End_B0=25 End_B1=25
8815 12:33:01.500879 26, 0x0, End_B0=26 End_B1=26
8816 12:33:01.504181 27, 0x0, End_B0=27 End_B1=27
8817 12:33:01.508052 28, 0x0, End_B0=28 End_B1=28
8818 12:33:01.511325 29, 0x0, End_B0=29 End_B1=29
8819 12:33:01.511802 30, 0x0, End_B0=30 End_B1=30
8820 12:33:01.514551 31, 0x4141, End_B0=30 End_B1=30
8821 12:33:01.517850 Byte0 end_step=30 best_step=27
8822 12:33:01.521146 Byte1 end_step=30 best_step=27
8823 12:33:01.524514 Byte0 TX OE(2T, 0.5T) = (3, 3)
8824 12:33:01.527936 Byte1 TX OE(2T, 0.5T) = (3, 3)
8825 12:33:01.528367
8826 12:33:01.528737
8827 12:33:01.534695 [DQSOSCAuto] RK0, (LSB)MR18= 0x14fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 399 ps
8828 12:33:01.537814 CH1 RK0: MR19=302, MR18=14FE
8829 12:33:01.544402 CH1_RK0: MR19=0x302, MR18=0x14FE, DQSOSC=399, MR23=63, INC=23, DEC=15
8830 12:33:01.544904
8831 12:33:01.547798 ----->DramcWriteLeveling(PI) begin...
8832 12:33:01.548424 ==
8833 12:33:01.550576 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 12:33:01.553993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 12:33:01.554463 ==
8836 12:33:01.558026 Write leveling (Byte 0): 24 => 24
8837 12:33:01.560637 Write leveling (Byte 1): 27 => 27
8838 12:33:01.564045 DramcWriteLeveling(PI) end<-----
8839 12:33:01.564478
8840 12:33:01.564817 ==
8841 12:33:01.567474 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 12:33:01.570669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 12:33:01.571118 ==
8844 12:33:01.574065 [Gating] SW mode calibration
8845 12:33:01.580724 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8846 12:33:01.586736 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8847 12:33:01.590692 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 12:33:01.596763 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 12:33:01.600729 1 4 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
8850 12:33:01.604079 1 4 12 | B1->B0 | 2929 3434 | 0 1 | (1 1) (1 1)
8851 12:33:01.610732 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8852 12:33:01.613889 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8853 12:33:01.617203 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8854 12:33:01.620397 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8855 12:33:01.627018 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8856 12:33:01.630326 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8857 12:33:01.633713 1 5 8 | B1->B0 | 3434 2c2c | 0 0 | (0 0) (0 1)
8858 12:33:01.640958 1 5 12 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
8859 12:33:01.644165 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 12:33:01.647536 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 12:33:01.654071 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 12:33:01.657415 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8863 12:33:01.660200 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8864 12:33:01.666817 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8865 12:33:01.670148 1 6 8 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8866 12:33:01.673501 1 6 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8867 12:33:01.680082 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 12:33:01.683566 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 12:33:01.686719 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 12:33:01.693415 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 12:33:01.696767 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8872 12:33:01.700582 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8873 12:33:01.707080 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8874 12:33:01.710428 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8875 12:33:01.713899 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8876 12:33:01.720399 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 12:33:01.723783 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 12:33:01.726872 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 12:33:01.733400 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 12:33:01.736546 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 12:33:01.739952 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 12:33:01.746516 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 12:33:01.749717 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 12:33:01.754003 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 12:33:01.759812 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 12:33:01.763157 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 12:33:01.766559 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8888 12:33:01.769965 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 12:33:01.776698 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8890 12:33:01.779911 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8891 12:33:01.783048 Total UI for P1: 0, mck2ui 16
8892 12:33:01.786414 best dqsien dly found for B0: ( 1, 9, 8)
8893 12:33:01.789797 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8894 12:33:01.796674 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8895 12:33:01.799997 Total UI for P1: 0, mck2ui 16
8896 12:33:01.803243 best dqsien dly found for B1: ( 1, 9, 14)
8897 12:33:01.806499 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8898 12:33:01.809924 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8899 12:33:01.810432
8900 12:33:01.813419 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8901 12:33:01.816626 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8902 12:33:01.819619 [Gating] SW calibration Done
8903 12:33:01.819706 ==
8904 12:33:01.822922 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 12:33:01.826239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 12:33:01.826325 ==
8907 12:33:01.829509 RX Vref Scan: 0
8908 12:33:01.829620
8909 12:33:01.829694 RX Vref 0 -> 0, step: 1
8910 12:33:01.832637
8911 12:33:01.832722 RX Delay 0 -> 252, step: 8
8912 12:33:01.835815 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8913 12:33:01.842966 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8914 12:33:01.845790 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8915 12:33:01.849264 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8916 12:33:01.852639 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8917 12:33:01.856010 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8918 12:33:01.862657 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8919 12:33:01.866255 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8920 12:33:01.869527 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8921 12:33:01.872882 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8922 12:33:01.876133 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8923 12:33:01.882674 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8924 12:33:01.886008 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8925 12:33:01.889364 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8926 12:33:01.892885 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8927 12:33:01.899329 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8928 12:33:01.899793 ==
8929 12:33:01.902768 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 12:33:01.906370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 12:33:01.906902 ==
8932 12:33:01.907249 DQS Delay:
8933 12:33:01.909547 DQS0 = 0, DQS1 = 0
8934 12:33:01.910077 DQM Delay:
8935 12:33:01.912662 DQM0 = 132, DQM1 = 127
8936 12:33:01.913170 DQ Delay:
8937 12:33:01.916080 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8938 12:33:01.919449 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8939 12:33:01.922827 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8940 12:33:01.926195 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8941 12:33:01.926726
8942 12:33:01.927112
8943 12:33:01.929345 ==
8944 12:33:01.932647 Dram Type= 6, Freq= 0, CH_1, rank 1
8945 12:33:01.935899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8946 12:33:01.936392 ==
8947 12:33:01.936793
8948 12:33:01.937119
8949 12:33:01.939196 TX Vref Scan disable
8950 12:33:01.939737 == TX Byte 0 ==
8951 12:33:01.942481 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8952 12:33:01.949050 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8953 12:33:01.949509 == TX Byte 1 ==
8954 12:33:01.952379 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8955 12:33:01.959494 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8956 12:33:01.959929 ==
8957 12:33:01.962793 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 12:33:01.966123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 12:33:01.966562 ==
8960 12:33:01.978755
8961 12:33:01.982012 TX Vref early break, caculate TX vref
8962 12:33:01.985259 TX Vref=16, minBit 8, minWin=22, winSum=376
8963 12:33:01.988630 TX Vref=18, minBit 8, minWin=23, winSum=388
8964 12:33:01.991923 TX Vref=20, minBit 6, minWin=24, winSum=396
8965 12:33:01.995231 TX Vref=22, minBit 11, minWin=24, winSum=408
8966 12:33:01.998587 TX Vref=24, minBit 6, minWin=25, winSum=414
8967 12:33:02.005831 TX Vref=26, minBit 6, minWin=25, winSum=421
8968 12:33:02.009134 TX Vref=28, minBit 0, minWin=26, winSum=428
8969 12:33:02.012475 TX Vref=30, minBit 0, minWin=25, winSum=423
8970 12:33:02.015727 TX Vref=32, minBit 0, minWin=25, winSum=413
8971 12:33:02.018928 TX Vref=34, minBit 0, minWin=24, winSum=404
8972 12:33:02.025618 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8973 12:33:02.025967
8974 12:33:02.028916 Final TX Range 0 Vref 28
8975 12:33:02.029335
8976 12:33:02.029708 ==
8977 12:33:02.031565 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 12:33:02.035315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 12:33:02.035714 ==
8980 12:33:02.035962
8981 12:33:02.036186
8982 12:33:02.038701 TX Vref Scan disable
8983 12:33:02.045112 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8984 12:33:02.045417 == TX Byte 0 ==
8985 12:33:02.048429 u2DelayCellOfst[0]=17 cells (5 PI)
8986 12:33:02.051403 u2DelayCellOfst[1]=14 cells (4 PI)
8987 12:33:02.054851 u2DelayCellOfst[2]=0 cells (0 PI)
8988 12:33:02.058236 u2DelayCellOfst[3]=7 cells (2 PI)
8989 12:33:02.062050 u2DelayCellOfst[4]=7 cells (2 PI)
8990 12:33:02.065404 u2DelayCellOfst[5]=17 cells (5 PI)
8991 12:33:02.068137 u2DelayCellOfst[6]=17 cells (5 PI)
8992 12:33:02.071589 u2DelayCellOfst[7]=7 cells (2 PI)
8993 12:33:02.074919 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8994 12:33:02.077923 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8995 12:33:02.081092 == TX Byte 1 ==
8996 12:33:02.081200 u2DelayCellOfst[8]=0 cells (0 PI)
8997 12:33:02.084951 u2DelayCellOfst[9]=3 cells (1 PI)
8998 12:33:02.088138 u2DelayCellOfst[10]=10 cells (3 PI)
8999 12:33:02.090910 u2DelayCellOfst[11]=3 cells (1 PI)
9000 12:33:02.094961 u2DelayCellOfst[12]=14 cells (4 PI)
9001 12:33:02.098314 u2DelayCellOfst[13]=14 cells (4 PI)
9002 12:33:02.100961 u2DelayCellOfst[14]=17 cells (5 PI)
9003 12:33:02.104386 u2DelayCellOfst[15]=17 cells (5 PI)
9004 12:33:02.107702 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9005 12:33:02.114338 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9006 12:33:02.114488 DramC Write-DBI on
9007 12:33:02.114610 ==
9008 12:33:02.117584 Dram Type= 6, Freq= 0, CH_1, rank 1
9009 12:33:02.120967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9010 12:33:02.124415 ==
9011 12:33:02.124624
9012 12:33:02.124785
9013 12:33:02.124943 TX Vref Scan disable
9014 12:33:02.127764 == TX Byte 0 ==
9015 12:33:02.131224 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9016 12:33:02.134557 == TX Byte 1 ==
9017 12:33:02.137989 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9018 12:33:02.141462 DramC Write-DBI off
9019 12:33:02.142100
9020 12:33:02.142455 [DATLAT]
9021 12:33:02.142759 Freq=1600, CH1 RK1
9022 12:33:02.143043
9023 12:33:02.144677 DATLAT Default: 0xf
9024 12:33:02.145106 0, 0xFFFF, sum = 0
9025 12:33:02.147993 1, 0xFFFF, sum = 0
9026 12:33:02.151072 2, 0xFFFF, sum = 0
9027 12:33:02.151543 3, 0xFFFF, sum = 0
9028 12:33:02.154910 4, 0xFFFF, sum = 0
9029 12:33:02.155667 5, 0xFFFF, sum = 0
9030 12:33:02.158124 6, 0xFFFF, sum = 0
9031 12:33:02.158669 7, 0xFFFF, sum = 0
9032 12:33:02.161553 8, 0xFFFF, sum = 0
9033 12:33:02.161984 9, 0xFFFF, sum = 0
9034 12:33:02.164826 10, 0xFFFF, sum = 0
9035 12:33:02.165453 11, 0xFFFF, sum = 0
9036 12:33:02.168077 12, 0xFFFF, sum = 0
9037 12:33:02.168509 13, 0xFFFF, sum = 0
9038 12:33:02.171498 14, 0x0, sum = 1
9039 12:33:02.171931 15, 0x0, sum = 2
9040 12:33:02.174815 16, 0x0, sum = 3
9041 12:33:02.175247 17, 0x0, sum = 4
9042 12:33:02.178175 best_step = 15
9043 12:33:02.178600
9044 12:33:02.178936 ==
9045 12:33:02.181410 Dram Type= 6, Freq= 0, CH_1, rank 1
9046 12:33:02.184676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9047 12:33:02.185178 ==
9048 12:33:02.188079 RX Vref Scan: 0
9049 12:33:02.188506
9050 12:33:02.188844 RX Vref 0 -> 0, step: 1
9051 12:33:02.189157
9052 12:33:02.191215 RX Delay 11 -> 252, step: 4
9053 12:33:02.194690 iDelay=195, Bit 0, Center 130 (79 ~ 182) 104
9054 12:33:02.201396 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9055 12:33:02.204236 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9056 12:33:02.207511 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9057 12:33:02.210886 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
9058 12:33:02.214216 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9059 12:33:02.220760 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9060 12:33:02.224062 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9061 12:33:02.228085 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9062 12:33:02.230767 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9063 12:33:02.234034 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9064 12:33:02.240636 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
9065 12:33:02.244015 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9066 12:33:02.247057 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9067 12:33:02.251191 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9068 12:33:02.257517 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9069 12:33:02.258049 ==
9070 12:33:02.260732 Dram Type= 6, Freq= 0, CH_1, rank 1
9071 12:33:02.263888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9072 12:33:02.264473 ==
9073 12:33:02.265003 DQS Delay:
9074 12:33:02.267221 DQS0 = 0, DQS1 = 0
9075 12:33:02.267785 DQM Delay:
9076 12:33:02.270498 DQM0 = 128, DQM1 = 126
9077 12:33:02.271025 DQ Delay:
9078 12:33:02.273841 DQ0 =130, DQ1 =124, DQ2 =116, DQ3 =126
9079 12:33:02.277295 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
9080 12:33:02.280544 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9081 12:33:02.283833 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
9082 12:33:02.284442
9083 12:33:02.284846
9084 12:33:02.287040
9085 12:33:02.287563 [DramC_TX_OE_Calibration] TA2
9086 12:33:02.290484 Original DQ_B0 (3 6) =30, OEN = 27
9087 12:33:02.293735 Original DQ_B1 (3 6) =30, OEN = 27
9088 12:33:02.297177 24, 0x0, End_B0=24 End_B1=24
9089 12:33:02.300403 25, 0x0, End_B0=25 End_B1=25
9090 12:33:02.303636 26, 0x0, End_B0=26 End_B1=26
9091 12:33:02.304295 27, 0x0, End_B0=27 End_B1=27
9092 12:33:02.306976 28, 0x0, End_B0=28 End_B1=28
9093 12:33:02.310151 29, 0x0, End_B0=29 End_B1=29
9094 12:33:02.313670 30, 0x0, End_B0=30 End_B1=30
9095 12:33:02.316874 31, 0x4545, End_B0=30 End_B1=30
9096 12:33:02.317598 Byte0 end_step=30 best_step=27
9097 12:33:02.320222 Byte1 end_step=30 best_step=27
9098 12:33:02.323551 Byte0 TX OE(2T, 0.5T) = (3, 3)
9099 12:33:02.326877 Byte1 TX OE(2T, 0.5T) = (3, 3)
9100 12:33:02.327469
9101 12:33:02.327903
9102 12:33:02.333321 [DQSOSCAuto] RK1, (LSB)MR18= 0xf15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9103 12:33:02.336615 CH1 RK1: MR19=303, MR18=F15
9104 12:33:02.343280 CH1_RK1: MR19=0x303, MR18=0xF15, DQSOSC=399, MR23=63, INC=23, DEC=15
9105 12:33:02.346748 [RxdqsGatingPostProcess] freq 1600
9106 12:33:02.353191 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9107 12:33:02.356524 best DQS0 dly(2T, 0.5T) = (1, 1)
9108 12:33:02.356964 best DQS1 dly(2T, 0.5T) = (1, 1)
9109 12:33:02.359890 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9110 12:33:02.363143 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9111 12:33:02.366379 best DQS0 dly(2T, 0.5T) = (1, 1)
9112 12:33:02.369574 best DQS1 dly(2T, 0.5T) = (1, 1)
9113 12:33:02.372865 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9114 12:33:02.376672 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9115 12:33:02.380074 Pre-setting of DQS Precalculation
9116 12:33:02.382654 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9117 12:33:02.392650 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9118 12:33:02.399455 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9119 12:33:02.399906
9120 12:33:02.400240
9121 12:33:02.402796 [Calibration Summary] 3200 Mbps
9122 12:33:02.403219 CH 0, Rank 0
9123 12:33:02.406105 SW Impedance : PASS
9124 12:33:02.406548 DUTY Scan : NO K
9125 12:33:02.409516 ZQ Calibration : PASS
9126 12:33:02.412844 Jitter Meter : NO K
9127 12:33:02.413268 CBT Training : PASS
9128 12:33:02.416038 Write leveling : PASS
9129 12:33:02.419340 RX DQS gating : PASS
9130 12:33:02.419920 RX DQ/DQS(RDDQC) : PASS
9131 12:33:02.422576 TX DQ/DQS : PASS
9132 12:33:02.425864 RX DATLAT : PASS
9133 12:33:02.426286 RX DQ/DQS(Engine): PASS
9134 12:33:02.429287 TX OE : PASS
9135 12:33:02.429712 All Pass.
9136 12:33:02.430045
9137 12:33:02.432603 CH 0, Rank 1
9138 12:33:02.433059 SW Impedance : PASS
9139 12:33:02.435907 DUTY Scan : NO K
9140 12:33:02.439295 ZQ Calibration : PASS
9141 12:33:02.439908 Jitter Meter : NO K
9142 12:33:02.442665 CBT Training : PASS
9143 12:33:02.446109 Write leveling : PASS
9144 12:33:02.446702 RX DQS gating : PASS
9145 12:33:02.449373 RX DQ/DQS(RDDQC) : PASS
9146 12:33:02.452737 TX DQ/DQS : PASS
9147 12:33:02.453305 RX DATLAT : PASS
9148 12:33:02.456087 RX DQ/DQS(Engine): PASS
9149 12:33:02.456519 TX OE : PASS
9150 12:33:02.459331 All Pass.
9151 12:33:02.459791
9152 12:33:02.460130 CH 1, Rank 0
9153 12:33:02.462736 SW Impedance : PASS
9154 12:33:02.463167 DUTY Scan : NO K
9155 12:33:02.465765 ZQ Calibration : PASS
9156 12:33:02.469142 Jitter Meter : NO K
9157 12:33:02.469708 CBT Training : PASS
9158 12:33:02.472323 Write leveling : PASS
9159 12:33:02.475767 RX DQS gating : PASS
9160 12:33:02.476200 RX DQ/DQS(RDDQC) : PASS
9161 12:33:02.479043 TX DQ/DQS : PASS
9162 12:33:02.482225 RX DATLAT : PASS
9163 12:33:02.482803 RX DQ/DQS(Engine): PASS
9164 12:33:02.485483 TX OE : PASS
9165 12:33:02.485913 All Pass.
9166 12:33:02.486253
9167 12:33:02.488850 CH 1, Rank 1
9168 12:33:02.489279 SW Impedance : PASS
9169 12:33:02.492237 DUTY Scan : NO K
9170 12:33:02.495930 ZQ Calibration : PASS
9171 12:33:02.496366 Jitter Meter : NO K
9172 12:33:02.499132 CBT Training : PASS
9173 12:33:02.502518 Write leveling : PASS
9174 12:33:02.503053 RX DQS gating : PASS
9175 12:33:02.505931 RX DQ/DQS(RDDQC) : PASS
9176 12:33:02.509101 TX DQ/DQS : PASS
9177 12:33:02.509680 RX DATLAT : PASS
9178 12:33:02.512461 RX DQ/DQS(Engine): PASS
9179 12:33:02.515823 TX OE : PASS
9180 12:33:02.516355 All Pass.
9181 12:33:02.516854
9182 12:33:02.517350 DramC Write-DBI on
9183 12:33:02.518889 PER_BANK_REFRESH: Hybrid Mode
9184 12:33:02.522272 TX_TRACKING: ON
9185 12:33:02.528893 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9186 12:33:02.538898 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9187 12:33:02.545793 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9188 12:33:02.549194 [FAST_K] Save calibration result to emmc
9189 12:33:02.552241 sync common calibartion params.
9190 12:33:02.552798 sync cbt_mode0:1, 1:1
9191 12:33:02.555613 dram_init: ddr_geometry: 2
9192 12:33:02.558806 dram_init: ddr_geometry: 2
9193 12:33:02.561886 dram_init: ddr_geometry: 2
9194 12:33:02.562312 0:dram_rank_size:100000000
9195 12:33:02.565271 1:dram_rank_size:100000000
9196 12:33:02.571805 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9197 12:33:02.572236 DFS_SHUFFLE_HW_MODE: ON
9198 12:33:02.578046 dramc_set_vcore_voltage set vcore to 725000
9199 12:33:02.578129 Read voltage for 1600, 0
9200 12:33:02.581307 Vio18 = 0
9201 12:33:02.581390 Vcore = 725000
9202 12:33:02.581456 Vdram = 0
9203 12:33:02.584768 Vddq = 0
9204 12:33:02.584856 Vmddr = 0
9205 12:33:02.588132 switch to 3200 Mbps bootup
9206 12:33:02.588222 [DramcRunTimeConfig]
9207 12:33:02.588292 PHYPLL
9208 12:33:02.591617 DPM_CONTROL_AFTERK: ON
9209 12:33:02.595042 PER_BANK_REFRESH: ON
9210 12:33:02.595157 REFRESH_OVERHEAD_REDUCTION: ON
9211 12:33:02.598403 CMD_PICG_NEW_MODE: OFF
9212 12:33:02.601698 XRTWTW_NEW_MODE: ON
9213 12:33:02.601843 XRTRTR_NEW_MODE: ON
9214 12:33:02.604456 TX_TRACKING: ON
9215 12:33:02.604589 RDSEL_TRACKING: OFF
9216 12:33:02.607693 DQS Precalculation for DVFS: ON
9217 12:33:02.607818 RX_TRACKING: OFF
9218 12:33:02.611312 HW_GATING DBG: ON
9219 12:33:02.611760 ZQCS_ENABLE_LP4: ON
9220 12:33:02.614771 RX_PICG_NEW_MODE: ON
9221 12:33:02.618039 TX_PICG_NEW_MODE: ON
9222 12:33:02.618599 ENABLE_RX_DCM_DPHY: ON
9223 12:33:02.621318 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9224 12:33:02.624761 DUMMY_READ_FOR_TRACKING: OFF
9225 12:33:02.628048 !!! SPM_CONTROL_AFTERK: OFF
9226 12:33:02.631450 !!! SPM could not control APHY
9227 12:33:02.631877 IMPEDANCE_TRACKING: ON
9228 12:33:02.634713 TEMP_SENSOR: ON
9229 12:33:02.635265 HW_SAVE_FOR_SR: OFF
9230 12:33:02.638113 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9231 12:33:02.641388 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9232 12:33:02.644773 Read ODT Tracking: ON
9233 12:33:02.645218 Refresh Rate DeBounce: ON
9234 12:33:02.648016 DFS_NO_QUEUE_FLUSH: ON
9235 12:33:02.651290 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9236 12:33:02.654697 ENABLE_DFS_RUNTIME_MRW: OFF
9237 12:33:02.655116 DDR_RESERVE_NEW_MODE: ON
9238 12:33:02.657983 MR_CBT_SWITCH_FREQ: ON
9239 12:33:02.661225 =========================
9240 12:33:02.679170 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9241 12:33:02.682596 dram_init: ddr_geometry: 2
9242 12:33:02.700509 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9243 12:33:02.704421 dram_init: dram init end (result: 0)
9244 12:33:02.710911 DRAM-K: Full calibration passed in 24582 msecs
9245 12:33:02.714357 MRC: failed to locate region type 0.
9246 12:33:02.714598 DRAM rank0 size:0x100000000,
9247 12:33:02.717605 DRAM rank1 size=0x100000000
9248 12:33:02.727645 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9249 12:33:02.733824 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9250 12:33:02.740606 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9251 12:33:02.747224 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9252 12:33:02.750349 DRAM rank0 size:0x100000000,
9253 12:33:02.753608 DRAM rank1 size=0x100000000
9254 12:33:02.753696 CBMEM:
9255 12:33:02.756841 IMD: root @ 0xfffff000 254 entries.
9256 12:33:02.760326 IMD: root @ 0xffffec00 62 entries.
9257 12:33:02.763605 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9258 12:33:02.766860 WARNING: RO_VPD is uninitialized or empty.
9259 12:33:02.773506 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9260 12:33:02.780719 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9261 12:33:02.793650 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9262 12:33:02.804645 BS: romstage times (exec / console): total (unknown) / 24085 ms
9263 12:33:02.804754
9264 12:33:02.804835
9265 12:33:02.814628 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9266 12:33:02.818003 ARM64: Exception handlers installed.
9267 12:33:02.821408 ARM64: Testing exception
9268 12:33:02.824653 ARM64: Done test exception
9269 12:33:02.824736 Enumerating buses...
9270 12:33:02.827919 Show all devs... Before device enumeration.
9271 12:33:02.831193 Root Device: enabled 1
9272 12:33:02.834504 CPU_CLUSTER: 0: enabled 1
9273 12:33:02.834587 CPU: 00: enabled 1
9274 12:33:02.837966 Compare with tree...
9275 12:33:02.838049 Root Device: enabled 1
9276 12:33:02.841748 CPU_CLUSTER: 0: enabled 1
9277 12:33:02.845113 CPU: 00: enabled 1
9278 12:33:02.845534 Root Device scanning...
9279 12:33:02.848476 scan_static_bus for Root Device
9280 12:33:02.851805 CPU_CLUSTER: 0 enabled
9281 12:33:02.855275 scan_static_bus for Root Device done
9282 12:33:02.858578 scan_bus: bus Root Device finished in 8 msecs
9283 12:33:02.859002 done
9284 12:33:02.864770 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9285 12:33:02.868158 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9286 12:33:02.874697 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9287 12:33:02.877748 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9288 12:33:02.881193 Allocating resources...
9289 12:33:02.884327 Reading resources...
9290 12:33:02.887667 Root Device read_resources bus 0 link: 0
9291 12:33:02.888336 DRAM rank0 size:0x100000000,
9292 12:33:02.891643 DRAM rank1 size=0x100000000
9293 12:33:02.894846 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9294 12:33:02.898177 CPU: 00 missing read_resources
9295 12:33:02.904655 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9296 12:33:02.907890 Root Device read_resources bus 0 link: 0 done
9297 12:33:02.908319 Done reading resources.
9298 12:33:02.914330 Show resources in subtree (Root Device)...After reading.
9299 12:33:02.918276 Root Device child on link 0 CPU_CLUSTER: 0
9300 12:33:02.921487 CPU_CLUSTER: 0 child on link 0 CPU: 00
9301 12:33:02.931330 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9302 12:33:02.931825 CPU: 00
9303 12:33:02.934596 Root Device assign_resources, bus 0 link: 0
9304 12:33:02.937904 CPU_CLUSTER: 0 missing set_resources
9305 12:33:02.944566 Root Device assign_resources, bus 0 link: 0 done
9306 12:33:02.945139 Done setting resources.
9307 12:33:02.951248 Show resources in subtree (Root Device)...After assigning values.
9308 12:33:02.954466 Root Device child on link 0 CPU_CLUSTER: 0
9309 12:33:02.957899 CPU_CLUSTER: 0 child on link 0 CPU: 00
9310 12:33:02.967841 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9311 12:33:02.968403 CPU: 00
9312 12:33:02.971067 Done allocating resources.
9313 12:33:02.977225 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9314 12:33:02.977700 Enabling resources...
9315 12:33:02.978038 done.
9316 12:33:02.984483 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9317 12:33:02.984927 Initializing devices...
9318 12:33:02.987138 Root Device init
9319 12:33:02.987679 init hardware done!
9320 12:33:02.990872 0x00000018: ctrlr->caps
9321 12:33:02.994140 52.000 MHz: ctrlr->f_max
9322 12:33:02.994832 0.400 MHz: ctrlr->f_min
9323 12:33:02.997430 0x40ff8080: ctrlr->voltages
9324 12:33:03.000678 sclk: 390625
9325 12:33:03.001301 Bus Width = 1
9326 12:33:03.001866 sclk: 390625
9327 12:33:03.003914 Bus Width = 1
9328 12:33:03.004571 Early init status = 3
9329 12:33:03.010896 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9330 12:33:03.014076 in-header: 03 fc 00 00 01 00 00 00
9331 12:33:03.014633 in-data: 00
9332 12:33:03.020455 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9333 12:33:03.023822 in-header: 03 fd 00 00 00 00 00 00
9334 12:33:03.027029 in-data:
9335 12:33:03.030375 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9336 12:33:03.034358 in-header: 03 fc 00 00 01 00 00 00
9337 12:33:03.037544 in-data: 00
9338 12:33:03.040894 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9339 12:33:03.045469 in-header: 03 fd 00 00 00 00 00 00
9340 12:33:03.048866 in-data:
9341 12:33:03.052178 [SSUSB] Setting up USB HOST controller...
9342 12:33:03.055409 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9343 12:33:03.058671 [SSUSB] phy power-on done.
9344 12:33:03.061729 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9345 12:33:03.068179 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9346 12:33:03.071364 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9347 12:33:03.078589 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9348 12:33:03.085321 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9349 12:33:03.091255 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9350 12:33:03.098380 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9351 12:33:03.104920 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9352 12:33:03.108144 SPM: binary array size = 0x9dc
9353 12:33:03.111529 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9354 12:33:03.118048 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9355 12:33:03.124973 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9356 12:33:03.128817 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9357 12:33:03.134671 configure_display: Starting display init
9358 12:33:03.169057 anx7625_power_on_init: Init interface.
9359 12:33:03.172260 anx7625_disable_pd_protocol: Disabled PD feature.
9360 12:33:03.175686 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9361 12:33:03.202849 anx7625_start_dp_work: Secure OCM version=00
9362 12:33:03.206040 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9363 12:33:03.220868 sp_tx_get_edid_block: EDID Block = 1
9364 12:33:03.323751 Extracted contents:
9365 12:33:03.326966 header: 00 ff ff ff ff ff ff 00
9366 12:33:03.330151 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9367 12:33:03.333883 version: 01 04
9368 12:33:03.337133 basic params: 95 1f 11 78 0a
9369 12:33:03.340580 chroma info: 76 90 94 55 54 90 27 21 50 54
9370 12:33:03.343907 established: 00 00 00
9371 12:33:03.349843 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9372 12:33:03.353179 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9373 12:33:03.359872 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9374 12:33:03.366617 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9375 12:33:03.373294 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9376 12:33:03.376813 extensions: 00
9377 12:33:03.377232 checksum: fb
9378 12:33:03.377559
9379 12:33:03.380174 Manufacturer: IVO Model 57d Serial Number 0
9380 12:33:03.383405 Made week 0 of 2020
9381 12:33:03.386861 EDID version: 1.4
9382 12:33:03.387276 Digital display
9383 12:33:03.390245 6 bits per primary color channel
9384 12:33:03.390671 DisplayPort interface
9385 12:33:03.393135 Maximum image size: 31 cm x 17 cm
9386 12:33:03.396461 Gamma: 220%
9387 12:33:03.396879 Check DPMS levels
9388 12:33:03.399633 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9389 12:33:03.406746 First detailed timing is preferred timing
9390 12:33:03.407167 Established timings supported:
9391 12:33:03.409995 Standard timings supported:
9392 12:33:03.413283 Detailed timings
9393 12:33:03.416569 Hex of detail: 383680a07038204018303c0035ae10000019
9394 12:33:03.423097 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9395 12:33:03.426529 0780 0798 07c8 0820 hborder 0
9396 12:33:03.429754 0438 043b 0447 0458 vborder 0
9397 12:33:03.433025 -hsync -vsync
9398 12:33:03.433450 Did detailed timing
9399 12:33:03.439296 Hex of detail: 000000000000000000000000000000000000
9400 12:33:03.442617 Manufacturer-specified data, tag 0
9401 12:33:03.446652 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9402 12:33:03.449760 ASCII string: InfoVision
9403 12:33:03.452591 Hex of detail: 000000fe00523134304e574635205248200a
9404 12:33:03.456037 ASCII string: R140NWF5 RH
9405 12:33:03.456483 Checksum
9406 12:33:03.459213 Checksum: 0xfb (valid)
9407 12:33:03.462524 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9408 12:33:03.465947 DSI data_rate: 832800000 bps
9409 12:33:03.472495 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9410 12:33:03.475881 anx7625_parse_edid: pixelclock(138800).
9411 12:33:03.479228 hactive(1920), hsync(48), hfp(24), hbp(88)
9412 12:33:03.482696 vactive(1080), vsync(12), vfp(3), vbp(17)
9413 12:33:03.485871 anx7625_dsi_config: config dsi.
9414 12:33:03.492325 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9415 12:33:03.506125 anx7625_dsi_config: success to config DSI
9416 12:33:03.509441 anx7625_dp_start: MIPI phy setup OK.
9417 12:33:03.512623 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9418 12:33:03.516053 mtk_ddp_mode_set invalid vrefresh 60
9419 12:33:03.519262 main_disp_path_setup
9420 12:33:03.519803 ovl_layer_smi_id_en
9421 12:33:03.522479 ovl_layer_smi_id_en
9422 12:33:03.522881 ccorr_config
9423 12:33:03.523280 aal_config
9424 12:33:03.525761 gamma_config
9425 12:33:03.526147 postmask_config
9426 12:33:03.528901 dither_config
9427 12:33:03.531992 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9428 12:33:03.539142 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9429 12:33:03.542311 Root Device init finished in 551 msecs
9430 12:33:03.545646 CPU_CLUSTER: 0 init
9431 12:33:03.552180 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9432 12:33:03.555456 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9433 12:33:03.558799 APU_MBOX 0x190000b0 = 0x10001
9434 12:33:03.562141 APU_MBOX 0x190001b0 = 0x10001
9435 12:33:03.565472 APU_MBOX 0x190005b0 = 0x10001
9436 12:33:03.568815 APU_MBOX 0x190006b0 = 0x10001
9437 12:33:03.572061 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9438 12:33:03.584868 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9439 12:33:03.597275 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9440 12:33:03.604164 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9441 12:33:03.615812 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9442 12:33:03.624781 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9443 12:33:03.628030 CPU_CLUSTER: 0 init finished in 81 msecs
9444 12:33:03.631412 Devices initialized
9445 12:33:03.634703 Show all devs... After init.
9446 12:33:03.635128 Root Device: enabled 1
9447 12:33:03.637996 CPU_CLUSTER: 0: enabled 1
9448 12:33:03.641180 CPU: 00: enabled 1
9449 12:33:03.644399 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9450 12:33:03.647854 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9451 12:33:03.650974 ELOG: NV offset 0x57f000 size 0x1000
9452 12:33:03.657645 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9453 12:33:03.664164 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9454 12:33:03.667636 ELOG: Event(17) added with size 13 at 2023-06-06 12:33:14 UTC
9455 12:33:03.674208 out: cmd=0x121: 03 db 21 01 00 00 00 00
9456 12:33:03.677385 in-header: 03 cd 00 00 2c 00 00 00
9457 12:33:03.687300 in-data: 92 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9458 12:33:03.694041 ELOG: Event(A1) added with size 10 at 2023-06-06 12:33:14 UTC
9459 12:33:03.700619 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9460 12:33:03.707249 ELOG: Event(A0) added with size 9 at 2023-06-06 12:33:14 UTC
9461 12:33:03.710590 elog_add_boot_reason: Logged dev mode boot
9462 12:33:03.717200 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9463 12:33:03.717929 Finalize devices...
9464 12:33:03.721119 Devices finalized
9465 12:33:03.724331 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9466 12:33:03.727558 Writing coreboot table at 0xffe64000
9467 12:33:03.730664 0. 000000000010a000-0000000000113fff: RAMSTAGE
9468 12:33:03.737351 1. 0000000040000000-00000000400fffff: RAM
9469 12:33:03.741627 2. 0000000040100000-000000004032afff: RAMSTAGE
9470 12:33:03.744134 3. 000000004032b000-00000000545fffff: RAM
9471 12:33:03.747286 4. 0000000054600000-000000005465ffff: BL31
9472 12:33:03.750542 5. 0000000054660000-00000000ffe63fff: RAM
9473 12:33:03.757087 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9474 12:33:03.761070 7. 0000000100000000-000000023fffffff: RAM
9475 12:33:03.764450 Passing 5 GPIOs to payload:
9476 12:33:03.767836 NAME | PORT | POLARITY | VALUE
9477 12:33:03.771065 EC in RW | 0x000000aa | low | undefined
9478 12:33:03.777771 EC interrupt | 0x00000005 | low | undefined
9479 12:33:03.781064 TPM interrupt | 0x000000ab | high | undefined
9480 12:33:03.787644 SD card detect | 0x00000011 | high | undefined
9481 12:33:03.790887 speaker enable | 0x00000093 | high | undefined
9482 12:33:03.794097 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9483 12:33:03.797482 in-header: 03 f9 00 00 02 00 00 00
9484 12:33:03.800741 in-data: 02 00
9485 12:33:03.801167 ADC[4]: Raw value=900959 ID=7
9486 12:33:03.803993 ADC[3]: Raw value=213336 ID=1
9487 12:33:03.807413 RAM Code: 0x71
9488 12:33:03.807973 ADC[6]: Raw value=74557 ID=0
9489 12:33:03.810646 ADC[5]: Raw value=212229 ID=1
9490 12:33:03.813968 SKU Code: 0x1
9491 12:33:03.817227 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9492 12:33:03.820579 coreboot table: 964 bytes.
9493 12:33:03.823870 IMD ROOT 0. 0xfffff000 0x00001000
9494 12:33:03.827232 IMD SMALL 1. 0xffffe000 0x00001000
9495 12:33:03.830371 RO MCACHE 2. 0xffffc000 0x00001104
9496 12:33:03.833569 CONSOLE 3. 0xfff7c000 0x00080000
9497 12:33:03.836923 FMAP 4. 0xfff7b000 0x00000452
9498 12:33:03.840244 TIME STAMP 5. 0xfff7a000 0x00000910
9499 12:33:03.843651 VBOOT WORK 6. 0xfff66000 0x00014000
9500 12:33:03.846884 RAMOOPS 7. 0xffe66000 0x00100000
9501 12:33:03.849980 COREBOOT 8. 0xffe64000 0x00002000
9502 12:33:03.850575 IMD small region:
9503 12:33:03.857247 IMD ROOT 0. 0xffffec00 0x00000400
9504 12:33:03.860507 VPD 1. 0xffffeba0 0x0000004c
9505 12:33:03.863900 MMC STATUS 2. 0xffffeb80 0x00000004
9506 12:33:03.866950 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9507 12:33:03.870045 Probing TPM: done!
9508 12:33:03.873333 Connected to device vid:did:rid of 1ae0:0028:00
9509 12:33:03.884108 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9510 12:33:03.887556 Initialized TPM device CR50 revision 0
9511 12:33:03.890698 Checking cr50 for pending updates
9512 12:33:03.894629 Reading cr50 TPM mode
9513 12:33:03.903257 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9514 12:33:03.909971 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9515 12:33:03.949892 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9516 12:33:03.953111 Checking segment from ROM address 0x40100000
9517 12:33:03.956615 Checking segment from ROM address 0x4010001c
9518 12:33:03.963744 Loading segment from ROM address 0x40100000
9519 12:33:03.964255 code (compression=0)
9520 12:33:03.970140 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9521 12:33:03.980005 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9522 12:33:03.980442 it's not compressed!
9523 12:33:03.987127 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9524 12:33:03.989793 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9525 12:33:04.010770 Loading segment from ROM address 0x4010001c
9526 12:33:04.011210 Entry Point 0x80000000
9527 12:33:04.013949 Loaded segments
9528 12:33:04.017329 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9529 12:33:04.023850 Jumping to boot code at 0x80000000(0xffe64000)
9530 12:33:04.030355 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9531 12:33:04.036857 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9532 12:33:04.044879 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9533 12:33:04.048164 Checking segment from ROM address 0x40100000
9534 12:33:04.051310 Checking segment from ROM address 0x4010001c
9535 12:33:04.058496 Loading segment from ROM address 0x40100000
9536 12:33:04.059079 code (compression=1)
9537 12:33:04.065107 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9538 12:33:04.074943 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9539 12:33:04.075577 using LZMA
9540 12:33:04.083377 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9541 12:33:04.089850 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9542 12:33:04.093187 Loading segment from ROM address 0x4010001c
9543 12:33:04.093627 Entry Point 0x54601000
9544 12:33:04.096509 Loaded segments
9545 12:33:04.099827 NOTICE: MT8192 bl31_setup
9546 12:33:04.106369 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9547 12:33:04.109763 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9548 12:33:04.113288 WARNING: region 0:
9549 12:33:04.116642 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9550 12:33:04.116796 WARNING: region 1:
9551 12:33:04.123329 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9552 12:33:04.126027 WARNING: region 2:
9553 12:33:04.129962 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9554 12:33:04.133292 WARNING: region 3:
9555 12:33:04.136636 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9556 12:33:04.139997 WARNING: region 4:
9557 12:33:04.146487 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9558 12:33:04.146589 WARNING: region 5:
9559 12:33:04.149861 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9560 12:33:04.153167 WARNING: region 6:
9561 12:33:04.156583 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9562 12:33:04.159867 WARNING: region 7:
9563 12:33:04.163048 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9564 12:33:04.169577 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9565 12:33:04.172837 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9566 12:33:04.176033 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9567 12:33:04.182801 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9568 12:33:04.186829 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9569 12:33:04.190182 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9570 12:33:04.197012 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9571 12:33:04.200251 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9572 12:33:04.206315 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9573 12:33:04.209840 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9574 12:33:04.213120 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9575 12:33:04.219872 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9576 12:33:04.223178 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9577 12:33:04.226469 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9578 12:33:04.233224 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9579 12:33:04.236651 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9580 12:33:04.243011 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9581 12:33:04.246923 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9582 12:33:04.250363 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9583 12:33:04.257126 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9584 12:33:04.259715 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9585 12:33:04.263574 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9586 12:33:04.270002 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9587 12:33:04.273259 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9588 12:33:04.279869 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9589 12:33:04.283549 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9590 12:33:04.286796 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9591 12:33:04.293239 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9592 12:33:04.296621 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9593 12:33:04.303110 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9594 12:33:04.306588 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9595 12:33:04.309915 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9596 12:33:04.316709 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9597 12:33:04.320004 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9598 12:33:04.323176 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9599 12:33:04.326539 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9600 12:33:04.333194 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9601 12:33:04.336563 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9602 12:33:04.339981 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9603 12:33:04.343139 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9604 12:33:04.349789 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9605 12:33:04.352963 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9606 12:33:04.356916 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9607 12:33:04.360062 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9608 12:33:04.366655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9609 12:33:04.370113 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9610 12:33:04.373493 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9611 12:33:04.376753 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9612 12:33:04.383543 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9613 12:33:04.386802 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9614 12:33:04.393290 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9615 12:33:04.396579 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9616 12:33:04.403283 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9617 12:33:04.406429 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9618 12:33:04.409822 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9619 12:33:04.416579 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9620 12:33:04.419963 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9621 12:33:04.426688 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9622 12:33:04.430094 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9623 12:33:04.436272 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9624 12:33:04.439723 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9625 12:33:04.443089 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9626 12:33:04.449680 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9627 12:33:04.452979 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9628 12:33:04.459533 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9629 12:33:04.463423 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9630 12:33:04.470053 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9631 12:33:04.473291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9632 12:33:04.476732 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9633 12:33:04.483385 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9634 12:33:04.486520 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9635 12:33:04.493087 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9636 12:33:04.496532 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9637 12:33:04.499818 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9638 12:33:04.506274 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9639 12:33:04.509730 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9640 12:33:04.516517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9641 12:33:04.519754 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9642 12:33:04.526491 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9643 12:33:04.529867 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9644 12:33:04.536667 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9645 12:33:04.539466 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9646 12:33:04.543472 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9647 12:33:04.549586 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9648 12:33:04.553439 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9649 12:33:04.559841 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9650 12:33:04.563059 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9651 12:33:04.569526 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9652 12:33:04.572936 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9653 12:33:04.576223 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9654 12:33:04.582913 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9655 12:33:04.586320 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9656 12:33:04.592950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9657 12:33:04.596759 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9658 12:33:04.603381 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9659 12:33:04.606685 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9660 12:33:04.610076 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9661 12:33:04.616752 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9662 12:33:04.620149 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9663 12:33:04.623433 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9664 12:33:04.626773 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9665 12:33:04.633407 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9666 12:33:04.636978 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9667 12:33:04.643063 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9668 12:33:04.646648 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9669 12:33:04.649963 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9670 12:33:04.656755 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9671 12:33:04.660114 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9672 12:33:04.663516 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9673 12:33:04.669969 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9674 12:33:04.673877 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9675 12:33:04.680507 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9676 12:33:04.683906 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9677 12:33:04.687128 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9678 12:33:04.693726 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9679 12:33:04.696932 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9680 12:33:04.700227 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9681 12:33:04.706709 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9682 12:33:04.709863 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9683 12:33:04.713183 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9684 12:33:04.719973 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9685 12:33:04.723291 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9686 12:33:04.726822 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9687 12:33:04.730171 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9688 12:33:04.737082 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9689 12:33:04.740274 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9690 12:33:04.743755 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9691 12:33:04.750529 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9692 12:33:04.753277 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9693 12:33:04.760494 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9694 12:33:04.763786 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9695 12:33:04.767146 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9696 12:33:04.773069 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9697 12:33:04.777124 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9698 12:33:04.783638 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9699 12:33:04.786853 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9700 12:33:04.790233 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9701 12:33:04.796990 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9702 12:33:04.800273 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9703 12:33:04.803418 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9704 12:33:04.810028 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9705 12:33:04.813351 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9706 12:33:04.819856 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9707 12:33:04.823190 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9708 12:33:04.826697 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9709 12:33:04.833490 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9710 12:33:04.836791 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9711 12:33:04.843456 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9712 12:33:04.846837 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9713 12:33:04.850135 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9714 12:33:04.856782 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9715 12:33:04.860295 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9716 12:33:04.863530 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9717 12:33:04.870026 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9718 12:33:04.873401 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9719 12:33:04.880159 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9720 12:33:04.883920 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9721 12:33:04.887110 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9722 12:33:04.893693 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9723 12:33:04.897011 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9724 12:33:04.903105 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9725 12:33:04.906384 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9726 12:33:04.910300 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9727 12:33:04.916812 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9728 12:33:04.919915 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9729 12:33:04.923246 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9730 12:33:04.929844 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9731 12:33:04.933135 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9732 12:33:04.940128 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9733 12:33:04.943483 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9734 12:33:04.949544 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9735 12:33:04.952846 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9736 12:33:04.956244 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9737 12:33:04.963135 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9738 12:33:04.966392 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9739 12:33:04.969793 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9740 12:33:04.976276 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9741 12:33:04.979517 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9742 12:33:04.986175 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9743 12:33:04.989701 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9744 12:33:04.992818 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9745 12:33:04.999304 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9746 12:33:05.002647 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9747 12:33:05.009259 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9748 12:33:05.012698 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9749 12:33:05.015895 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9750 12:33:05.022535 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9751 12:33:05.025848 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9752 12:33:05.032680 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9753 12:33:05.035912 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9754 12:33:05.041947 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9755 12:33:05.045287 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9756 12:33:05.048715 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9757 12:33:05.055434 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9758 12:33:05.058899 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9759 12:33:05.065456 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9760 12:33:05.068891 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9761 12:33:05.072172 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9762 12:33:05.078884 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9763 12:33:05.082171 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9764 12:33:05.088503 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9765 12:33:05.092046 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9766 12:33:05.098498 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9767 12:33:05.101833 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9768 12:33:05.105187 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9769 12:33:05.111991 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9770 12:33:05.115229 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9771 12:33:05.121776 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9772 12:33:05.125060 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9773 12:33:05.128449 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9774 12:33:05.134945 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9775 12:33:05.138446 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9776 12:33:05.145129 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9777 12:33:05.148687 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9778 12:33:05.155117 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9779 12:33:05.158622 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9780 12:33:05.161803 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9781 12:33:05.168459 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9782 12:33:05.171277 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9783 12:33:05.177958 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9784 12:33:05.181794 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9785 12:33:05.184488 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9786 12:33:05.191516 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9787 12:33:05.194795 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9788 12:33:05.201543 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9789 12:33:05.204942 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9790 12:33:05.211774 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9791 12:33:05.214357 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9792 12:33:05.218242 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9793 12:33:05.224903 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9794 12:33:05.228004 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9795 12:33:05.231541 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9796 12:33:05.234587 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9797 12:33:05.237929 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9798 12:33:05.244595 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9799 12:33:05.247976 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9800 12:33:05.254633 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9801 12:33:05.257454 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9802 12:33:05.260884 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9803 12:33:05.267573 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9804 12:33:05.270865 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9805 12:33:05.277614 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9806 12:33:05.281016 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9807 12:33:05.284364 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9808 12:33:05.290928 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9809 12:33:05.294159 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9810 12:33:05.297452 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9811 12:33:05.303936 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9812 12:33:05.307234 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9813 12:33:05.310563 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9814 12:33:05.317118 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9815 12:33:05.320583 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9816 12:33:05.327091 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9817 12:33:05.330510 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9818 12:33:05.333808 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9819 12:33:05.340388 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9820 12:33:05.343634 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9821 12:33:05.347028 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9822 12:33:05.354002 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9823 12:33:05.357297 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9824 12:33:05.360769 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9825 12:33:05.366906 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9826 12:33:05.370276 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9827 12:33:05.374270 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9828 12:33:05.380278 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9829 12:33:05.383716 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9830 12:33:05.390187 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9831 12:33:05.393549 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9832 12:33:05.396888 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9833 12:33:05.400309 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9834 12:33:05.406777 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9835 12:33:05.410181 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9836 12:33:05.413324 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9837 12:33:05.416648 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9838 12:33:05.423999 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9839 12:33:05.426799 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9840 12:33:05.430019 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9841 12:33:05.433346 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9842 12:33:05.439829 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9843 12:33:05.443704 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9844 12:33:05.446906 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9845 12:33:05.453643 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9846 12:33:05.456812 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9847 12:33:05.460284 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9848 12:33:05.466362 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9849 12:33:05.469758 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9850 12:33:05.476553 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9851 12:33:05.479851 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9852 12:33:05.486629 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9853 12:33:05.489871 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9854 12:33:05.493279 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9855 12:33:05.499879 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9856 12:33:05.503109 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9857 12:33:05.509639 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9858 12:33:05.512797 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9859 12:33:05.516147 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9860 12:33:05.522868 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9861 12:33:05.526065 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9862 12:33:05.532817 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9863 12:33:05.536100 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9864 12:33:05.539359 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9865 12:33:05.546071 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9866 12:33:05.549304 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9867 12:33:05.556383 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9868 12:33:05.559651 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9869 12:33:05.562970 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9870 12:33:05.569678 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9871 12:33:05.573207 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9872 12:33:05.579088 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9873 12:33:05.582422 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9874 12:33:05.589076 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9875 12:33:05.592383 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9876 12:33:05.598974 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9877 12:33:05.602274 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9878 12:33:05.605605 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9879 12:33:05.612105 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9880 12:33:05.615267 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9881 12:33:05.622438 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9882 12:33:05.625600 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9883 12:33:05.628890 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9884 12:33:05.635596 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9885 12:33:05.639003 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9886 12:33:05.645635 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9887 12:33:05.648894 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9888 12:33:05.652124 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9889 12:33:05.658748 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9890 12:33:05.662175 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9891 12:33:05.668829 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9892 12:33:05.672113 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9893 12:33:05.675387 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9894 12:33:05.681746 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9895 12:33:05.685030 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9896 12:33:05.691857 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9897 12:33:05.695006 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9898 12:33:05.701827 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9899 12:33:05.705052 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9900 12:33:05.708275 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9901 12:33:05.714891 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9902 12:33:05.718174 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9903 12:33:05.724562 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9904 12:33:05.728394 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9905 12:33:05.731798 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9906 12:33:05.738206 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9907 12:33:05.741643 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9908 12:33:05.748281 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9909 12:33:05.751148 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9910 12:33:05.754477 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9911 12:33:05.761705 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9912 12:33:05.764352 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9913 12:33:05.771254 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9914 12:33:05.774575 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9915 12:33:05.781266 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9916 12:33:05.784625 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9917 12:33:05.787918 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9918 12:33:05.794580 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9919 12:33:05.797906 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9920 12:33:05.804494 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9921 12:33:05.807774 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9922 12:33:05.814318 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9923 12:33:05.817723 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9924 12:33:05.820898 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9925 12:33:05.827482 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9926 12:33:05.831169 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9927 12:33:05.837830 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9928 12:33:05.841115 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9929 12:33:05.847876 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9930 12:33:05.851232 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9931 12:33:05.853941 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9932 12:33:05.860733 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9933 12:33:05.864067 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9934 12:33:05.870777 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9935 12:33:05.874040 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9936 12:33:05.880838 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9937 12:33:05.884251 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9938 12:33:05.887613 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9939 12:33:05.893894 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9940 12:33:05.896637 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9941 12:33:05.903868 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9942 12:33:05.906631 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9943 12:33:05.913653 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9944 12:33:05.916939 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9945 12:33:05.923430 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9946 12:33:05.926920 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9947 12:33:05.930030 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9948 12:33:05.937007 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9949 12:33:05.940365 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9950 12:33:05.947043 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9951 12:33:05.950352 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9952 12:33:05.957282 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9953 12:33:05.960536 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9954 12:33:05.963707 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9955 12:33:05.970697 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9956 12:33:05.973925 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9957 12:33:05.980028 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9958 12:33:05.983452 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9959 12:33:05.990206 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9960 12:33:05.993757 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9961 12:33:05.997032 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9962 12:33:06.003768 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9963 12:33:06.006980 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9964 12:33:06.013274 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9965 12:33:06.016799 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9966 12:33:06.020158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9967 12:33:06.026747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9968 12:33:06.030002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9969 12:33:06.036449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9970 12:33:06.039660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9971 12:33:06.046661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9972 12:33:06.049746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9973 12:33:06.056321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9974 12:33:06.059650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9975 12:33:06.066357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9976 12:33:06.069788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9977 12:33:06.075901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9978 12:33:06.079317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9979 12:33:06.086110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9980 12:33:06.089576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9981 12:33:06.095854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9982 12:33:06.099193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9983 12:33:06.105980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9984 12:33:06.109343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9985 12:33:06.115975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9986 12:33:06.119337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9987 12:33:06.126196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9988 12:33:06.128815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9989 12:33:06.135549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9990 12:33:06.138920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9991 12:33:06.145619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9992 12:33:06.149442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9993 12:33:06.155992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9994 12:33:06.159234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9995 12:33:06.165590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9996 12:33:06.168780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9997 12:33:06.175786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9998 12:33:06.178963 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9999 12:33:06.179217 INFO: [APUAPC] vio 0
10000 12:33:06.186564 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10001 12:33:06.189996 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10002 12:33:06.193429 INFO: [APUAPC] D0_APC_0: 0x400510
10003 12:33:06.197101 INFO: [APUAPC] D0_APC_1: 0x0
10004 12:33:06.200437 INFO: [APUAPC] D0_APC_2: 0x1540
10005 12:33:06.203286 INFO: [APUAPC] D0_APC_3: 0x0
10006 12:33:06.206567 INFO: [APUAPC] D1_APC_0: 0xffffffff
10007 12:33:06.209742 INFO: [APUAPC] D1_APC_1: 0xffffffff
10008 12:33:06.213095 INFO: [APUAPC] D1_APC_2: 0x3fffff
10009 12:33:06.216692 INFO: [APUAPC] D1_APC_3: 0x0
10010 12:33:06.220055 INFO: [APUAPC] D2_APC_0: 0xffffffff
10011 12:33:06.223267 INFO: [APUAPC] D2_APC_1: 0xffffffff
10012 12:33:06.226708 INFO: [APUAPC] D2_APC_2: 0x3fffff
10013 12:33:06.230010 INFO: [APUAPC] D2_APC_3: 0x0
10014 12:33:06.233361 INFO: [APUAPC] D3_APC_0: 0xffffffff
10015 12:33:06.236720 INFO: [APUAPC] D3_APC_1: 0xffffffff
10016 12:33:06.240055 INFO: [APUAPC] D3_APC_2: 0x3fffff
10017 12:33:06.243132 INFO: [APUAPC] D3_APC_3: 0x0
10018 12:33:06.246516 INFO: [APUAPC] D4_APC_0: 0xffffffff
10019 12:33:06.249742 INFO: [APUAPC] D4_APC_1: 0xffffffff
10020 12:33:06.253096 INFO: [APUAPC] D4_APC_2: 0x3fffff
10021 12:33:06.256268 INFO: [APUAPC] D4_APC_3: 0x0
10022 12:33:06.259862 INFO: [APUAPC] D5_APC_0: 0xffffffff
10023 12:33:06.263068 INFO: [APUAPC] D5_APC_1: 0xffffffff
10024 12:33:06.266601 INFO: [APUAPC] D5_APC_2: 0x3fffff
10025 12:33:06.267081 INFO: [APUAPC] D5_APC_3: 0x0
10026 12:33:06.269494 INFO: [APUAPC] D6_APC_0: 0xffffffff
10027 12:33:06.276191 INFO: [APUAPC] D6_APC_1: 0xffffffff
10028 12:33:06.276653 INFO: [APUAPC] D6_APC_2: 0x3fffff
10029 12:33:06.279443 INFO: [APUAPC] D6_APC_3: 0x0
10030 12:33:06.282638 INFO: [APUAPC] D7_APC_0: 0xffffffff
10031 12:33:06.285803 INFO: [APUAPC] D7_APC_1: 0xffffffff
10032 12:33:06.289303 INFO: [APUAPC] D7_APC_2: 0x3fffff
10033 12:33:06.292810 INFO: [APUAPC] D7_APC_3: 0x0
10034 12:33:06.296313 INFO: [APUAPC] D8_APC_0: 0xffffffff
10035 12:33:06.299631 INFO: [APUAPC] D8_APC_1: 0xffffffff
10036 12:33:06.302952 INFO: [APUAPC] D8_APC_2: 0x3fffff
10037 12:33:06.306183 INFO: [APUAPC] D8_APC_3: 0x0
10038 12:33:06.309640 INFO: [APUAPC] D9_APC_0: 0xffffffff
10039 12:33:06.312969 INFO: [APUAPC] D9_APC_1: 0xffffffff
10040 12:33:06.316253 INFO: [APUAPC] D9_APC_2: 0x3fffff
10041 12:33:06.319470 INFO: [APUAPC] D9_APC_3: 0x0
10042 12:33:06.322890 INFO: [APUAPC] D10_APC_0: 0xffffffff
10043 12:33:06.325550 INFO: [APUAPC] D10_APC_1: 0xffffffff
10044 12:33:06.328913 INFO: [APUAPC] D10_APC_2: 0x3fffff
10045 12:33:06.332284 INFO: [APUAPC] D10_APC_3: 0x0
10046 12:33:06.335671 INFO: [APUAPC] D11_APC_0: 0xffffffff
10047 12:33:06.338983 INFO: [APUAPC] D11_APC_1: 0xffffffff
10048 12:33:06.342271 INFO: [APUAPC] D11_APC_2: 0x3fffff
10049 12:33:06.345586 INFO: [APUAPC] D11_APC_3: 0x0
10050 12:33:06.349459 INFO: [APUAPC] D12_APC_0: 0xffffffff
10051 12:33:06.352080 INFO: [APUAPC] D12_APC_1: 0xffffffff
10052 12:33:06.356030 INFO: [APUAPC] D12_APC_2: 0x3fffff
10053 12:33:06.359211 INFO: [APUAPC] D12_APC_3: 0x0
10054 12:33:06.362321 INFO: [APUAPC] D13_APC_0: 0xffffffff
10055 12:33:06.365630 INFO: [APUAPC] D13_APC_1: 0xffffffff
10056 12:33:06.369007 INFO: [APUAPC] D13_APC_2: 0x3fffff
10057 12:33:06.372344 INFO: [APUAPC] D13_APC_3: 0x0
10058 12:33:06.375764 INFO: [APUAPC] D14_APC_0: 0xffffffff
10059 12:33:06.379049 INFO: [APUAPC] D14_APC_1: 0xffffffff
10060 12:33:06.382540 INFO: [APUAPC] D14_APC_2: 0x3fffff
10061 12:33:06.385540 INFO: [APUAPC] D14_APC_3: 0x0
10062 12:33:06.388848 INFO: [APUAPC] D15_APC_0: 0xffffffff
10063 12:33:06.392143 INFO: [APUAPC] D15_APC_1: 0xffffffff
10064 12:33:06.395299 INFO: [APUAPC] D15_APC_2: 0x3fffff
10065 12:33:06.398785 INFO: [APUAPC] D15_APC_3: 0x0
10066 12:33:06.402192 INFO: [APUAPC] APC_CON: 0x4
10067 12:33:06.405916 INFO: [NOCDAPC] D0_APC_0: 0x0
10068 12:33:06.409277 INFO: [NOCDAPC] D0_APC_1: 0x0
10069 12:33:06.412404 INFO: [NOCDAPC] D1_APC_0: 0x0
10070 12:33:06.415536 INFO: [NOCDAPC] D1_APC_1: 0xfff
10071 12:33:06.418990 INFO: [NOCDAPC] D2_APC_0: 0x0
10072 12:33:06.421678 INFO: [NOCDAPC] D2_APC_1: 0xfff
10073 12:33:06.421864 INFO: [NOCDAPC] D3_APC_0: 0x0
10074 12:33:06.425172 INFO: [NOCDAPC] D3_APC_1: 0xfff
10075 12:33:06.428460 INFO: [NOCDAPC] D4_APC_0: 0x0
10076 12:33:06.431927 INFO: [NOCDAPC] D4_APC_1: 0xfff
10077 12:33:06.435479 INFO: [NOCDAPC] D5_APC_0: 0x0
10078 12:33:06.438280 INFO: [NOCDAPC] D5_APC_1: 0xfff
10079 12:33:06.441645 INFO: [NOCDAPC] D6_APC_0: 0x0
10080 12:33:06.444946 INFO: [NOCDAPC] D6_APC_1: 0xfff
10081 12:33:06.448325 INFO: [NOCDAPC] D7_APC_0: 0x0
10082 12:33:06.451689 INFO: [NOCDAPC] D7_APC_1: 0xfff
10083 12:33:06.455004 INFO: [NOCDAPC] D8_APC_0: 0x0
10084 12:33:06.455223 INFO: [NOCDAPC] D8_APC_1: 0xfff
10085 12:33:06.458375 INFO: [NOCDAPC] D9_APC_0: 0x0
10086 12:33:06.461593 INFO: [NOCDAPC] D9_APC_1: 0xfff
10087 12:33:06.464977 INFO: [NOCDAPC] D10_APC_0: 0x0
10088 12:33:06.468763 INFO: [NOCDAPC] D10_APC_1: 0xfff
10089 12:33:06.472159 INFO: [NOCDAPC] D11_APC_0: 0x0
10090 12:33:06.474836 INFO: [NOCDAPC] D11_APC_1: 0xfff
10091 12:33:06.478766 INFO: [NOCDAPC] D12_APC_0: 0x0
10092 12:33:06.481594 INFO: [NOCDAPC] D12_APC_1: 0xfff
10093 12:33:06.485029 INFO: [NOCDAPC] D13_APC_0: 0x0
10094 12:33:06.488321 INFO: [NOCDAPC] D13_APC_1: 0xfff
10095 12:33:06.491198 INFO: [NOCDAPC] D14_APC_0: 0x0
10096 12:33:06.494446 INFO: [NOCDAPC] D14_APC_1: 0xfff
10097 12:33:06.497941 INFO: [NOCDAPC] D15_APC_0: 0x0
10098 12:33:06.498026 INFO: [NOCDAPC] D15_APC_1: 0xfff
10099 12:33:06.501458 INFO: [NOCDAPC] APC_CON: 0x4
10100 12:33:06.504996 INFO: [APUAPC] set_apusys_apc done
10101 12:33:06.508258 INFO: [DEVAPC] devapc_init done
10102 12:33:06.515038 INFO: GICv3 without legacy support detected.
10103 12:33:06.517753 INFO: ARM GICv3 driver initialized in EL3
10104 12:33:06.521144 INFO: Maximum SPI INTID supported: 639
10105 12:33:06.524742 INFO: BL31: Initializing runtime services
10106 12:33:06.530951 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10107 12:33:06.534476 INFO: SPM: enable CPC mode
10108 12:33:06.537791 INFO: mcdi ready for mcusys-off-idle and system suspend
10109 12:33:06.544471 INFO: BL31: Preparing for EL3 exit to normal world
10110 12:33:06.548067 INFO: Entry point address = 0x80000000
10111 12:33:06.548190 INFO: SPSR = 0x8
10112 12:33:06.554632
10113 12:33:06.554768
10114 12:33:06.554876
10115 12:33:06.558274 Starting depthcharge on Spherion...
10116 12:33:06.558427
10117 12:33:06.558547 Wipe memory regions:
10118 12:33:06.558658
10119 12:33:06.559616 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10120 12:33:06.559799 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10121 12:33:06.559950 Setting prompt string to ['asurada:']
10122 12:33:06.560096 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10123 12:33:06.561501 [0x00000040000000, 0x00000054600000)
10124 12:33:06.683207
10125 12:33:06.683341 [0x00000054660000, 0x00000080000000)
10126 12:33:06.944465
10127 12:33:06.944981 [0x000000821a7280, 0x000000ffe64000)
10128 12:33:07.688687
10129 12:33:07.688840 [0x00000100000000, 0x00000240000000)
10130 12:33:09.579226
10131 12:33:09.581751 Initializing XHCI USB controller at 0x11200000.
10132 12:33:10.619264
10133 12:33:10.622550 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10134 12:33:10.622634
10135 12:33:10.622700
10136 12:33:10.622768
10137 12:33:10.623085 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10139 12:33:10.723548 asurada: tftpboot 192.168.201.1 10605810/tftp-deploy-chfj_5iw/kernel/image.itb 10605810/tftp-deploy-chfj_5iw/kernel/cmdline
10140 12:33:10.724147 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10141 12:33:10.724588 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10142 12:33:10.729220 tftpboot 192.168.201.1 10605810/tftp-deploy-chfj_5iw/kernel/image.itp-deploy-chfj_5iw/kernel/cmdline
10143 12:33:10.729695
10144 12:33:10.730065 Waiting for link
10145 12:33:10.889153
10146 12:33:10.889881 R8152: Initializing
10147 12:33:10.890412
10148 12:33:10.892341 Version 6 (ocp_data = 5c30)
10149 12:33:10.892759
10150 12:33:10.895770 R8152: Done initializing
10151 12:33:10.896234
10152 12:33:10.896674 Adding net device
10153 12:33:12.861034
10154 12:33:12.861520 done.
10155 12:33:12.861870
10156 12:33:12.862189 MAC: 00:24:32:30:78:52
10157 12:33:12.862500
10158 12:33:12.864170 Sending DHCP discover... done.
10159 12:33:12.864638
10160 12:33:12.867566 Waiting for reply... done.
10161 12:33:12.868003
10162 12:33:12.871047 Sending DHCP request... done.
10163 12:33:12.871604
10164 12:33:12.878378 Waiting for reply... done.
10165 12:33:12.878812
10166 12:33:12.879153 My ip is 192.168.201.14
10167 12:33:12.879512
10168 12:33:12.881632 The DHCP server ip is 192.168.201.1
10169 12:33:12.882095
10170 12:33:12.888183 TFTP server IP predefined by user: 192.168.201.1
10171 12:33:12.888613
10172 12:33:12.894859 Bootfile predefined by user: 10605810/tftp-deploy-chfj_5iw/kernel/image.itb
10173 12:33:12.895438
10174 12:33:12.897576 Sending tftp read request... done.
10175 12:33:12.898380
10176 12:33:12.904130 Waiting for the transfer...
10177 12:33:12.904631
10178 12:33:13.500849 00000000 ################################################################
10179 12:33:13.501400
10180 12:33:14.101053 00080000 ################################################################
10181 12:33:14.101629
10182 12:33:14.724885 00100000 ################################################################
10183 12:33:14.725400
10184 12:33:15.320189 00180000 ################################################################
10185 12:33:15.320341
10186 12:33:15.894928 00200000 ################################################################
10187 12:33:15.895114
10188 12:33:16.434309 00280000 ################################################################
10189 12:33:16.434533
10190 12:33:16.964976 00300000 ################################################################
10191 12:33:16.965114
10192 12:33:17.498716 00380000 ################################################################
10193 12:33:17.498903
10194 12:33:18.028779 00400000 ################################################################
10195 12:33:18.028945
10196 12:33:18.572635 00480000 ################################################################
10197 12:33:18.572779
10198 12:33:19.115188 00500000 ################################################################
10199 12:33:19.115399
10200 12:33:19.661462 00580000 ################################################################
10201 12:33:19.661605
10202 12:33:20.209740 00600000 ################################################################
10203 12:33:20.209881
10204 12:33:20.754997 00680000 ################################################################
10205 12:33:20.755170
10206 12:33:21.293258 00700000 ################################################################
10207 12:33:21.293426
10208 12:33:21.856051 00780000 ################################################################
10209 12:33:21.856200
10210 12:33:22.408381 00800000 ################################################################
10211 12:33:22.408516
10212 12:33:23.025499 00880000 ################################################################
10213 12:33:23.026022
10214 12:33:23.673565 00900000 ################################################################
10215 12:33:23.674087
10216 12:33:24.319605 00980000 ################################################################
10217 12:33:24.319741
10218 12:33:24.945840 00a00000 ################################################################
10219 12:33:24.946378
10220 12:33:25.582736 00a80000 ################################################################
10221 12:33:25.583261
10222 12:33:26.165023 00b00000 ################################################################
10223 12:33:26.165605
10224 12:33:26.790425 00b80000 ################################################################
10225 12:33:26.790570
10226 12:33:27.367798 00c00000 ################################################################
10227 12:33:27.368358
10228 12:33:27.977082 00c80000 ################################################################
10229 12:33:27.977237
10230 12:33:28.597108 00d00000 ################################################################
10231 12:33:28.597265
10232 12:33:29.156688 00d80000 ################################################################
10233 12:33:29.156857
10234 12:33:29.817305 00e00000 ################################################################
10235 12:33:29.817828
10236 12:33:30.465492 00e80000 ################################################################
10237 12:33:30.466014
10238 12:33:31.050997 00f00000 ################################################################
10239 12:33:31.051181
10240 12:33:31.611738 00f80000 ################################################################
10241 12:33:31.611887
10242 12:33:32.227838 01000000 ################################################################
10243 12:33:32.228543
10244 12:33:32.810558 01080000 ################################################################
10245 12:33:32.811206
10246 12:33:33.415491 01100000 ################################################################
10247 12:33:33.415999
10248 12:33:33.958957 01180000 ################################################################
10249 12:33:33.959678
10250 12:33:34.580073 01200000 ################################################################
10251 12:33:34.580684
10252 12:33:35.219225 01280000 ################################################################
10253 12:33:35.219962
10254 12:33:35.847399 01300000 ################################################################
10255 12:33:35.848042
10256 12:33:36.465520 01380000 ################################################################
10257 12:33:36.465741
10258 12:33:37.066239 01400000 ################################################################
10259 12:33:37.066503
10260 12:33:37.667632 01480000 ################################################################
10261 12:33:37.668300
10262 12:33:38.293031 01500000 ################################################################
10263 12:33:38.293174
10264 12:33:38.865641 01580000 ################################################################
10265 12:33:38.865777
10266 12:33:39.479267 01600000 ################################################################
10267 12:33:39.479828
10268 12:33:40.143815 01680000 ################################################################
10269 12:33:40.144346
10270 12:33:40.773920 01700000 ################################################################
10271 12:33:40.774460
10272 12:33:41.370786 01780000 ################################################################
10273 12:33:41.371345
10274 12:33:41.976657 01800000 ################################################################
10275 12:33:41.977166
10276 12:33:42.630695 01880000 ################################################################
10277 12:33:42.631217
10278 12:33:43.205265 01900000 ################################################################
10279 12:33:43.205412
10280 12:33:43.766341 01980000 ################################################################
10281 12:33:43.766593
10282 12:33:44.296499 01a00000 ############################################################### done.
10283 12:33:44.296695
10284 12:33:44.299610 The bootfile was 27772398 bytes long.
10285 12:33:44.299712
10286 12:33:44.302667 Sending tftp read request... done.
10287 12:33:44.302760
10288 12:33:44.305939 Waiting for the transfer...
10289 12:33:44.306039
10290 12:33:44.306137 00000000 # done.
10291 12:33:44.306231
10292 12:33:44.316374 Command line loaded dynamically from TFTP file: 10605810/tftp-deploy-chfj_5iw/kernel/cmdline
10293 12:33:44.316497
10294 12:33:44.336090 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605810/extract-nfsrootfs-mg6xi24_,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10295 12:33:44.336185
10296 12:33:44.336254 Loading FIT.
10297 12:33:44.336316
10298 12:33:44.339075 Image ramdisk-1 has 17636691 bytes.
10299 12:33:44.339173
10300 12:33:44.342426 Image fdt-1 has 46924 bytes.
10301 12:33:44.342510
10302 12:33:44.345847 Image kernel-1 has 10086749 bytes.
10303 12:33:44.345947
10304 12:33:44.352451 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10305 12:33:44.352562
10306 12:33:44.372582 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10307 12:33:44.372691
10308 12:33:44.375765 Choosing best match conf-1 for compat google,spherion-rev2.
10309 12:33:44.381001
10310 12:33:44.385102 Connected to device vid:did:rid of 1ae0:0028:00
10311 12:33:44.392565
10312 12:33:44.395851 tpm_get_response: command 0x17b, return code 0x0
10313 12:33:44.396062
10314 12:33:44.399168 ec_init: CrosEC protocol v3 supported (256, 248)
10315 12:33:44.404422
10316 12:33:44.407543 tpm_cleanup: add release locality here.
10317 12:33:44.407873
10318 12:33:44.408092 Shutting down all USB controllers.
10319 12:33:44.410626
10320 12:33:44.410743 Removing current net device
10321 12:33:44.410838
10322 12:33:44.417170 Exiting depthcharge with code 4 at timestamp: 67266580
10323 12:33:44.417267
10324 12:33:44.420898 LZMA decompressing kernel-1 to 0x821a6718
10325 12:33:44.420994
10326 12:33:44.424410 LZMA decompressing kernel-1 to 0x40000000
10327 12:33:45.690663
10328 12:33:45.690872 jumping to kernel
10329 12:33:45.691298 end: 2.2.4 bootloader-commands (duration 00:00:39) [common]
10330 12:33:45.691414 start: 2.2.5 auto-login-action (timeout 00:03:46) [common]
10331 12:33:45.691537 Setting prompt string to ['Linux version [0-9]']
10332 12:33:45.691666 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10333 12:33:45.691748 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10334 12:33:45.771740
10335 12:33:45.774927 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10336 12:33:45.778332 start: 2.2.5.1 login-action (timeout 00:03:46) [common]
10337 12:33:45.778450 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10338 12:33:45.778539 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10339 12:33:45.778621 Using line separator: #'\n'#
10340 12:33:45.778723 No login prompt set.
10341 12:33:45.778815 Parsing kernel messages
10342 12:33:45.778904 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10343 12:33:45.779076 [login-action] Waiting for messages, (timeout 00:03:46)
10344 12:33:45.798512 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614976-arm64-gcc-10-defconfig-arm64-chromebook-lgg5p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023
10345 12:33:45.801201 [ 0.000000] random: crng init done
10346 12:33:45.804992 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10347 12:33:45.808125 [ 0.000000] efi: UEFI not found.
10348 12:33:45.817976 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10349 12:33:45.824719 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10350 12:33:45.834674 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10351 12:33:45.844711 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10352 12:33:45.851239 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10353 12:33:45.854582 [ 0.000000] printk: bootconsole [mtk8250] enabled
10354 12:33:45.863288 [ 0.000000] NUMA: No NUMA configuration found
10355 12:33:45.869782 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10356 12:33:45.875959 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10357 12:33:45.876105 [ 0.000000] Zone ranges:
10358 12:33:45.882958 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10359 12:33:45.886172 [ 0.000000] DMA32 empty
10360 12:33:45.893120 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10361 12:33:45.896394 [ 0.000000] Movable zone start for each node
10362 12:33:45.899237 [ 0.000000] Early memory node ranges
10363 12:33:45.906289 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10364 12:33:45.912717 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10365 12:33:45.919149 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10366 12:33:45.925957 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10367 12:33:45.932578 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10368 12:33:45.939158 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10369 12:33:45.995448 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10370 12:33:46.002158 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10371 12:33:46.008515 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10372 12:33:46.012401 [ 0.000000] psci: probing for conduit method from DT.
10373 12:33:46.018776 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10374 12:33:46.021987 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10375 12:33:46.028522 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10376 12:33:46.031940 [ 0.000000] psci: SMC Calling Convention v1.2
10377 12:33:46.038575 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10378 12:33:46.041928 [ 0.000000] Detected VIPT I-cache on CPU0
10379 12:33:46.048518 [ 0.000000] CPU features: detected: GIC system register CPU interface
10380 12:33:46.055159 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10381 12:33:46.061718 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10382 12:33:46.068331 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10383 12:33:46.078291 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10384 12:33:46.085103 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10385 12:33:46.088410 [ 0.000000] alternatives: applying boot alternatives
10386 12:33:46.095102 [ 0.000000] Fallback order for Node 0: 0
10387 12:33:46.101566 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10388 12:33:46.104773 [ 0.000000] Policy zone: Normal
10389 12:33:46.124859 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605810/extract-nfsrootfs-mg6xi24_,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10390 12:33:46.135089 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10391 12:33:46.146332 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10392 12:33:46.156114 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10393 12:33:46.162578 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10394 12:33:46.165722 <6>[ 0.000000] software IO TLB: area num 8.
10395 12:33:46.222893 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10396 12:33:46.371651 <6>[ 0.000000] Memory: 7955720K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397048K reserved, 32768K cma-reserved)
10397 12:33:46.378327 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10398 12:33:46.385157 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10399 12:33:46.388321 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10400 12:33:46.395571 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10401 12:33:46.402210 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10402 12:33:46.405548 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10403 12:33:46.415310 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10404 12:33:46.421685 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10405 12:33:46.424909 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10406 12:33:46.432729 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10407 12:33:46.436623 <6>[ 0.000000] GICv3: 608 SPIs implemented
10408 12:33:46.443110 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10409 12:33:46.446375 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10410 12:33:46.449585 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10411 12:33:46.459676 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10412 12:33:46.469708 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10413 12:33:46.482924 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10414 12:33:46.489524 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10415 12:33:46.498771 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10416 12:33:46.511730 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10417 12:33:46.518229 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10418 12:33:46.525268 <6>[ 0.009178] Console: colour dummy device 80x25
10419 12:33:46.534823 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10420 12:33:46.541316 <6>[ 0.024347] pid_max: default: 32768 minimum: 301
10421 12:33:46.544610 <6>[ 0.029221] LSM: Security Framework initializing
10422 12:33:46.551768 <6>[ 0.034189] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10423 12:33:46.561112 <6>[ 0.042001] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10424 12:33:46.571103 <6>[ 0.051480] cblist_init_generic: Setting adjustable number of callback queues.
10425 12:33:46.577695 <6>[ 0.058935] cblist_init_generic: Setting shift to 3 and lim to 1.
10426 12:33:46.581038 <6>[ 0.065313] cblist_init_generic: Setting shift to 3 and lim to 1.
10427 12:33:46.587728 <6>[ 0.071722] rcu: Hierarchical SRCU implementation.
10428 12:33:46.594406 <6>[ 0.076737] rcu: Max phase no-delay instances is 1000.
10429 12:33:46.601215 <6>[ 0.083753] EFI services will not be available.
10430 12:33:46.603876 <6>[ 0.088753] smp: Bringing up secondary CPUs ...
10431 12:33:46.611916 <6>[ 0.093803] Detected VIPT I-cache on CPU1
10432 12:33:46.618378 <6>[ 0.093875] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10433 12:33:46.625448 <6>[ 0.093906] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10434 12:33:46.628542 <6>[ 0.094242] Detected VIPT I-cache on CPU2
10435 12:33:46.634973 <6>[ 0.094290] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10436 12:33:46.642004 <6>[ 0.094305] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10437 12:33:46.648408 <6>[ 0.094564] Detected VIPT I-cache on CPU3
10438 12:33:46.654887 <6>[ 0.094611] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10439 12:33:46.661574 <6>[ 0.094625] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10440 12:33:46.664795 <6>[ 0.094931] CPU features: detected: Spectre-v4
10441 12:33:46.671487 <6>[ 0.094938] CPU features: detected: Spectre-BHB
10442 12:33:46.674761 <6>[ 0.094943] Detected PIPT I-cache on CPU4
10443 12:33:46.681502 <6>[ 0.095001] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10444 12:33:46.688231 <6>[ 0.095018] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10445 12:33:46.694764 <6>[ 0.095317] Detected PIPT I-cache on CPU5
10446 12:33:46.701570 <6>[ 0.095381] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10447 12:33:46.708361 <6>[ 0.095397] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10448 12:33:46.711625 <6>[ 0.095683] Detected PIPT I-cache on CPU6
10449 12:33:46.718270 <6>[ 0.095747] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10450 12:33:46.724874 <6>[ 0.095763] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10451 12:33:46.731655 <6>[ 0.096062] Detected PIPT I-cache on CPU7
10452 12:33:46.737728 <6>[ 0.096125] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10453 12:33:46.744231 <6>[ 0.096142] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10454 12:33:46.747943 <6>[ 0.096189] smp: Brought up 1 node, 8 CPUs
10455 12:33:46.754817 <6>[ 0.237608] SMP: Total of 8 processors activated.
10456 12:33:46.758004 <6>[ 0.242559] CPU features: detected: 32-bit EL0 Support
10457 12:33:46.767718 <6>[ 0.247956] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10458 12:33:46.774326 <6>[ 0.256811] CPU features: detected: Common not Private translations
10459 12:33:46.781031 <6>[ 0.263286] CPU features: detected: CRC32 instructions
10460 12:33:46.784416 <6>[ 0.268671] CPU features: detected: RCpc load-acquire (LDAPR)
10461 12:33:46.790912 <6>[ 0.274667] CPU features: detected: LSE atomic instructions
10462 12:33:46.797560 <6>[ 0.280485] CPU features: detected: Privileged Access Never
10463 12:33:46.804221 <6>[ 0.286264] CPU features: detected: RAS Extension Support
10464 12:33:46.810891 <6>[ 0.291873] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10465 12:33:46.814257 <6>[ 0.299094] CPU: All CPU(s) started at EL2
10466 12:33:46.820881 <6>[ 0.303438] alternatives: applying system-wide alternatives
10467 12:33:46.829488 <6>[ 0.314140] devtmpfs: initialized
10468 12:33:46.842280 <6>[ 0.323037] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10469 12:33:46.851930 <6>[ 0.333003] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10470 12:33:46.858900 <6>[ 0.341019] pinctrl core: initialized pinctrl subsystem
10471 12:33:46.862225 <6>[ 0.347693] DMI not present or invalid.
10472 12:33:46.868561 <6>[ 0.352105] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10473 12:33:46.878512 <6>[ 0.358973] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10474 12:33:46.885263 <6>[ 0.366560] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10475 12:33:46.895067 <6>[ 0.374778] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10476 12:33:46.898392 <6>[ 0.383025] audit: initializing netlink subsys (disabled)
10477 12:33:46.908343 <5>[ 0.388720] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10478 12:33:46.915003 <6>[ 0.389395] thermal_sys: Registered thermal governor 'step_wise'
10479 12:33:46.921644 <6>[ 0.396688] thermal_sys: Registered thermal governor 'power_allocator'
10480 12:33:46.924877 <6>[ 0.402942] cpuidle: using governor menu
10481 12:33:46.931567 <6>[ 0.413906] NET: Registered PF_QIPCRTR protocol family
10482 12:33:46.938234 <6>[ 0.419394] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10483 12:33:46.941663 <6>[ 0.426500] ASID allocator initialised with 32768 entries
10484 12:33:46.948818 <6>[ 0.433071] Serial: AMBA PL011 UART driver
10485 12:33:46.957829 <4>[ 0.441737] Trying to register duplicate clock ID: 134
10486 12:33:47.013239 <6>[ 0.500941] KASLR enabled
10487 12:33:47.027884 <6>[ 0.508664] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10488 12:33:47.034539 <6>[ 0.515676] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10489 12:33:47.041183 <6>[ 0.522165] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10490 12:33:47.047317 <6>[ 0.529170] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10491 12:33:47.054106 <6>[ 0.535659] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10492 12:33:47.060563 <6>[ 0.542664] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10493 12:33:47.067419 <6>[ 0.549153] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10494 12:33:47.074441 <6>[ 0.556158] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10495 12:33:47.077617 <6>[ 0.563647] ACPI: Interpreter disabled.
10496 12:33:47.085551 <6>[ 0.570039] iommu: Default domain type: Translated
10497 12:33:47.092193 <6>[ 0.575202] iommu: DMA domain TLB invalidation policy: strict mode
10498 12:33:47.095534 <5>[ 0.581865] SCSI subsystem initialized
10499 12:33:47.102182 <6>[ 0.586099] usbcore: registered new interface driver usbfs
10500 12:33:47.108779 <6>[ 0.591834] usbcore: registered new interface driver hub
10501 12:33:47.112098 <6>[ 0.597389] usbcore: registered new device driver usb
10502 12:33:47.119279 <6>[ 0.603496] pps_core: LinuxPPS API ver. 1 registered
10503 12:33:47.128735 <6>[ 0.608690] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10504 12:33:47.132185 <6>[ 0.618037] PTP clock support registered
10505 12:33:47.135521 <6>[ 0.622277] EDAC MC: Ver: 3.0.0
10506 12:33:47.143419 <6>[ 0.627466] FPGA manager framework
10507 12:33:47.150074 <6>[ 0.631144] Advanced Linux Sound Architecture Driver Initialized.
10508 12:33:47.152746 <6>[ 0.637921] vgaarb: loaded
10509 12:33:47.159313 <6>[ 0.641092] clocksource: Switched to clocksource arch_sys_counter
10510 12:33:47.163214 <5>[ 0.647543] VFS: Disk quotas dquot_6.6.0
10511 12:33:47.169518 <6>[ 0.651729] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10512 12:33:47.172832 <6>[ 0.658926] pnp: PnP ACPI: disabled
10513 12:33:47.181555 <6>[ 0.665658] NET: Registered PF_INET protocol family
10514 12:33:47.191147 <6>[ 0.671257] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10515 12:33:47.202266 <6>[ 0.683571] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10516 12:33:47.212460 <6>[ 0.692386] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10517 12:33:47.219091 <6>[ 0.700357] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10518 12:33:47.225826 <6>[ 0.709055] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10519 12:33:47.237743 <6>[ 0.718797] TCP: Hash tables configured (established 65536 bind 65536)
10520 12:33:47.244447 <6>[ 0.725654] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10521 12:33:47.250959 <6>[ 0.732856] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10522 12:33:47.257544 <6>[ 0.740557] NET: Registered PF_UNIX/PF_LOCAL protocol family
10523 12:33:47.264251 <6>[ 0.746721] RPC: Registered named UNIX socket transport module.
10524 12:33:47.267582 <6>[ 0.752878] RPC: Registered udp transport module.
10525 12:33:47.273909 <6>[ 0.757811] RPC: Registered tcp transport module.
10526 12:33:47.281077 <6>[ 0.762743] RPC: Registered tcp NFSv4.1 backchannel transport module.
10527 12:33:47.284198 <6>[ 0.769414] PCI: CLS 0 bytes, default 64
10528 12:33:47.287575 <6>[ 0.773834] Unpacking initramfs...
10529 12:33:47.297145 <6>[ 0.777998] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10530 12:33:47.303922 <6>[ 0.786658] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10531 12:33:47.311171 <6>[ 0.795494] kvm [1]: IPA Size Limit: 40 bits
10532 12:33:47.314462 <6>[ 0.800022] kvm [1]: GICv3: no GICV resource entry
10533 12:33:47.321177 <6>[ 0.805046] kvm [1]: disabling GICv2 emulation
10534 12:33:47.327830 <6>[ 0.809737] kvm [1]: GIC system register CPU interface enabled
10535 12:33:47.331073 <6>[ 0.815921] kvm [1]: vgic interrupt IRQ18
10536 12:33:47.337789 <6>[ 0.820283] kvm [1]: VHE mode initialized successfully
10537 12:33:47.340575 <5>[ 0.826809] Initialise system trusted keyrings
10538 12:33:47.347218 <6>[ 0.831631] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10539 12:33:47.357167 <6>[ 0.841862] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10540 12:33:47.363763 <5>[ 0.848247] NFS: Registering the id_resolver key type
10541 12:33:47.367051 <5>[ 0.853551] Key type id_resolver registered
10542 12:33:47.374241 <5>[ 0.857966] Key type id_legacy registered
10543 12:33:47.380864 <6>[ 0.862261] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10544 12:33:47.387427 <6>[ 0.869185] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10545 12:33:47.393788 <6>[ 0.876918] 9p: Installing v9fs 9p2000 file system support
10546 12:33:47.429376 <5>[ 0.913884] Key type asymmetric registered
10547 12:33:47.432732 <5>[ 0.918216] Asymmetric key parser 'x509' registered
10548 12:33:47.442970 <6>[ 0.923360] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10549 12:33:47.445648 <6>[ 0.930979] io scheduler mq-deadline registered
10550 12:33:47.448914 <6>[ 0.935740] io scheduler kyber registered
10551 12:33:47.467958 <6>[ 0.952583] EINJ: ACPI disabled.
10552 12:33:47.500499 <4>[ 0.978170] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10553 12:33:47.510607 <4>[ 0.988828] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10554 12:33:47.525568 <6>[ 1.009665] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10555 12:33:47.533109 <6>[ 1.017645] printk: console [ttyS0] disabled
10556 12:33:47.561042 <6>[ 1.042291] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10557 12:33:47.568290 <6>[ 1.051770] printk: console [ttyS0] enabled
10558 12:33:47.570984 <6>[ 1.051770] printk: console [ttyS0] enabled
10559 12:33:47.577669 <6>[ 1.060665] printk: bootconsole [mtk8250] disabled
10560 12:33:47.581080 <6>[ 1.060665] printk: bootconsole [mtk8250] disabled
10561 12:33:47.587543 <6>[ 1.071926] SuperH (H)SCI(F) driver initialized
10562 12:33:47.590782 <6>[ 1.077208] msm_serial: driver initialized
10563 12:33:47.605504 <6>[ 1.086122] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10564 12:33:47.615177 <6>[ 1.094671] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10565 12:33:47.621635 <6>[ 1.103213] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10566 12:33:47.631671 <6>[ 1.111840] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10567 12:33:47.641576 <6>[ 1.120547] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10568 12:33:47.648255 <6>[ 1.129267] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10569 12:33:47.658234 <6>[ 1.137808] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10570 12:33:47.664323 <6>[ 1.146616] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10571 12:33:47.674354 <6>[ 1.155162] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10572 12:33:47.686923 <6>[ 1.170969] loop: module loaded
10573 12:33:47.693277 <6>[ 1.177068] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10574 12:33:47.715992 <4>[ 1.200446] mtk-pmic-keys: Failed to locate of_node [id: -1]
10575 12:33:47.722944 <6>[ 1.207242] megasas: 07.719.03.00-rc1
10576 12:33:47.732110 <6>[ 1.216787] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10577 12:33:47.740085 <6>[ 1.224536] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10578 12:33:47.757122 <6>[ 1.241311] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10579 12:33:47.817321 <6>[ 1.295369] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10580 12:33:48.016304 <6>[ 1.500943] Freeing initrd memory: 17220K
10581 12:33:48.026808 <6>[ 1.511177] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10582 12:33:48.037976 <6>[ 1.522085] tun: Universal TUN/TAP device driver, 1.6
10583 12:33:48.041166 <6>[ 1.528135] thunder_xcv, ver 1.0
10584 12:33:48.044728 <6>[ 1.531639] thunder_bgx, ver 1.0
10585 12:33:48.047990 <6>[ 1.535134] nicpf, ver 1.0
10586 12:33:48.057851 <6>[ 1.539125] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10587 12:33:48.061174 <6>[ 1.546602] hns3: Copyright (c) 2017 Huawei Corporation.
10588 12:33:48.067759 <6>[ 1.552188] hclge is initializing
10589 12:33:48.071082 <6>[ 1.555768] e1000: Intel(R) PRO/1000 Network Driver
10590 12:33:48.077683 <6>[ 1.560897] e1000: Copyright (c) 1999-2006 Intel Corporation.
10591 12:33:48.081029 <6>[ 1.566910] e1000e: Intel(R) PRO/1000 Network Driver
10592 12:33:48.087826 <6>[ 1.572126] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10593 12:33:48.094521 <6>[ 1.578315] igb: Intel(R) Gigabit Ethernet Network Driver
10594 12:33:48.101150 <6>[ 1.583965] igb: Copyright (c) 2007-2014 Intel Corporation.
10595 12:33:48.107668 <6>[ 1.589801] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10596 12:33:48.114097 <6>[ 1.596319] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10597 12:33:48.117366 <6>[ 1.602774] sky2: driver version 1.30
10598 12:33:48.123756 <6>[ 1.607750] VFIO - User Level meta-driver version: 0.3
10599 12:33:48.131794 <6>[ 1.615928] usbcore: registered new interface driver usb-storage
10600 12:33:48.138382 <6>[ 1.622379] usbcore: registered new device driver onboard-usb-hub
10601 12:33:48.146709 <6>[ 1.631488] mt6397-rtc mt6359-rtc: registered as rtc0
10602 12:33:48.157399 <6>[ 1.636960] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:33:59 UTC (1686054839)
10603 12:33:48.160041 <6>[ 1.646553] i2c_dev: i2c /dev entries driver
10604 12:33:48.177346 <6>[ 1.658171] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10605 12:33:48.184232 <6>[ 1.668352] sdhci: Secure Digital Host Controller Interface driver
10606 12:33:48.190715 <6>[ 1.674790] sdhci: Copyright(c) Pierre Ossman
10607 12:33:48.197328 <6>[ 1.680179] Synopsys Designware Multimedia Card Interface Driver
10608 12:33:48.200601 <6>[ 1.686839] mmc0: CQHCI version 5.10
10609 12:33:48.207211 <6>[ 1.687333] sdhci-pltfm: SDHCI platform and OF driver helper
10610 12:33:48.214450 <6>[ 1.698782] ledtrig-cpu: registered to indicate activity on CPUs
10611 12:33:48.224856 <6>[ 1.706103] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10612 12:33:48.228719 <6>[ 1.713500] usbcore: registered new interface driver usbhid
10613 12:33:48.235185 <6>[ 1.719332] usbhid: USB HID core driver
10614 12:33:48.241602 <6>[ 1.723573] spi_master spi0: will run message pump with realtime priority
10615 12:33:48.290010 <6>[ 1.767556] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10616 12:33:48.305989 <6>[ 1.783850] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10617 12:33:48.313929 <6>[ 1.797434] mmc0: Command Queue Engine enabled
10618 12:33:48.320411 <6>[ 1.799179] cros-ec-spi spi0.0: Chrome EC device registered
10619 12:33:48.324128 <6>[ 1.802172] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10620 12:33:48.330667 <6>[ 1.815281] mmcblk0: mmc0:0001 DA4128 116 GiB
10621 12:33:48.345513 <6>[ 1.826456] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10622 12:33:48.352040 <6>[ 1.827849] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10623 12:33:48.359083 <6>[ 1.837934] NET: Registered PF_PACKET protocol family
10624 12:33:48.362385 <6>[ 1.843156] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10625 12:33:48.369060 <6>[ 1.847084] 9pnet: Installing 9P2000 support
10626 12:33:48.372232 <6>[ 1.852882] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10627 12:33:48.375665 <5>[ 1.856792] Key type dns_resolver registered
10628 12:33:48.382455 <6>[ 1.862661] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10629 12:33:48.389118 <6>[ 1.867107] registered taskstats version 1
10630 12:33:48.392367 <5>[ 1.877396] Loading compiled-in X.509 certificates
10631 12:33:48.426453 <4>[ 1.904187] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10632 12:33:48.436588 <4>[ 1.914917] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10633 12:33:48.446916 <3>[ 1.927906] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10634 12:33:48.458868 <6>[ 1.943450] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10635 12:33:48.466115 <6>[ 1.950199] xhci-mtk 11200000.usb: xHCI Host Controller
10636 12:33:48.472213 <6>[ 1.955705] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10637 12:33:48.482206 <6>[ 1.963559] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10638 12:33:48.488836 <6>[ 1.972987] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10639 12:33:48.495761 <6>[ 1.979174] xhci-mtk 11200000.usb: xHCI Host Controller
10640 12:33:48.502470 <6>[ 1.984671] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10641 12:33:48.509037 <6>[ 1.992336] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10642 12:33:48.515696 <6>[ 2.000218] hub 1-0:1.0: USB hub found
10643 12:33:48.519135 <6>[ 2.004252] hub 1-0:1.0: 1 port detected
10644 12:33:48.529133 <6>[ 2.008603] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10645 12:33:48.532426 <6>[ 2.017417] hub 2-0:1.0: USB hub found
10646 12:33:48.535497 <6>[ 2.021450] hub 2-0:1.0: 1 port detected
10647 12:33:48.544472 <6>[ 2.028597] mtk-msdc 11f70000.mmc: Got CD GPIO
10648 12:33:48.561403 <6>[ 2.042405] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10649 12:33:48.567989 <6>[ 2.050431] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10650 12:33:48.577811 <4>[ 2.058507] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10651 12:33:48.588074 <6>[ 2.068167] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10652 12:33:48.594818 <6>[ 2.076291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10653 12:33:48.601499 <6>[ 2.084315] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10654 12:33:48.610815 <6>[ 2.092265] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10655 12:33:48.617575 <6>[ 2.100088] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10656 12:33:48.627485 <6>[ 2.107936] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10657 12:33:48.637823 <6>[ 2.118695] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10658 12:33:48.644327 <6>[ 2.127099] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10659 12:33:48.654114 <6>[ 2.135449] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10660 12:33:48.664041 <6>[ 2.143820] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10661 12:33:48.671141 <6>[ 2.152165] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10662 12:33:48.681055 <6>[ 2.160536] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10663 12:33:48.687638 <6>[ 2.168881] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10664 12:33:48.697128 <6>[ 2.177248] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10665 12:33:48.703803 <6>[ 2.185594] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10666 12:33:48.713909 <6>[ 2.193961] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10667 12:33:48.720459 <6>[ 2.202306] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10668 12:33:48.730582 <6>[ 2.210650] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10669 12:33:48.737099 <6>[ 2.218993] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10670 12:33:48.747607 <6>[ 2.227337] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10671 12:33:48.754033 <6>[ 2.235686] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10672 12:33:48.760525 <6>[ 2.244593] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10673 12:33:48.767674 <6>[ 2.252028] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10674 12:33:48.774849 <6>[ 2.259045] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10675 12:33:48.781496 <6>[ 2.266117] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10676 12:33:48.788815 <6>[ 2.273394] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10677 12:33:48.798988 <6>[ 2.280296] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10678 12:33:48.808988 <6>[ 2.289436] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10679 12:33:48.818833 <6>[ 2.298565] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10680 12:33:48.828871 <6>[ 2.307918] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10681 12:33:48.838813 <6>[ 2.317510] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10682 12:33:48.845568 <6>[ 2.326987] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10683 12:33:48.855856 <6>[ 2.336115] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10684 12:33:48.865477 <6>[ 2.345588] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10685 12:33:48.875573 <6>[ 2.354716] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10686 12:33:48.885400 <6>[ 2.364018] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10687 12:33:48.895404 <6>[ 2.374185] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10688 12:33:48.905435 <6>[ 2.385350] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10689 12:33:48.911338 <6>[ 2.395259] Trying to probe devices needed for running init ...
10690 12:33:48.964129 <6>[ 2.445366] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10691 12:33:49.118582 <6>[ 2.602809] hub 1-1:1.0: USB hub found
10692 12:33:49.121237 <6>[ 2.607283] hub 1-1:1.0: 4 ports detected
10693 12:33:49.244163 <6>[ 2.725586] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10694 12:33:49.269329 <6>[ 2.753816] hub 2-1:1.0: USB hub found
10695 12:33:49.272434 <6>[ 2.758212] hub 2-1:1.0: 3 ports detected
10696 12:33:49.444042 <6>[ 2.925377] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10697 12:33:49.576905 <6>[ 3.061624] hub 1-1.4:1.0: USB hub found
10698 12:33:49.580057 <6>[ 3.066298] hub 1-1.4:1.0: 2 ports detected
10699 12:33:49.655769 <6>[ 3.137451] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10700 12:33:49.880191 <6>[ 3.361366] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10701 12:33:50.072166 <6>[ 3.553364] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10702 12:34:01.184987 <6>[ 14.673927] ALSA device list:
10703 12:34:01.190868 <6>[ 14.677183] No soundcards found.
10704 12:34:01.203664 <6>[ 14.689599] Freeing unused kernel memory: 8384K
10705 12:34:01.206734 <6>[ 14.694533] Run /init as init process
10706 12:34:01.218133 Loading, please wait...
10707 12:34:01.237512 Starting version 247.3-7+deb11u2
10708 12:34:01.562750 <6>[ 15.045340] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10709 12:34:01.576921 <6>[ 15.062570] remoteproc remoteproc0: scp is available
10710 12:34:01.586949 <4>[ 15.068112] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10711 12:34:01.592934 <6>[ 15.077975] remoteproc remoteproc0: powering up scp
10712 12:34:01.599696 <6>[ 15.080235] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10713 12:34:01.609650 <4>[ 15.083149] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10714 12:34:01.616205 <3>[ 15.100607] remoteproc remoteproc0: request_firmware failed: -2
10715 12:34:01.622909 <4>[ 15.103401] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10716 12:34:01.629418 <4>[ 15.103401] Fallback method does not support PEC.
10717 12:34:01.655435 <3>[ 15.138084] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10718 12:34:01.662335 <6>[ 15.139630] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10719 12:34:01.672226 <3>[ 15.140988] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 12:34:01.678896 <3>[ 15.141009] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 12:34:01.688880 <3>[ 15.141018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 12:34:01.695402 <3>[ 15.141456] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 12:34:01.705357 <3>[ 15.141473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 12:34:01.712165 <3>[ 15.141483] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 12:34:01.718773 <3>[ 15.141493] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 12:34:01.729186 <3>[ 15.141499] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 12:34:01.735909 <3>[ 15.141555] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 12:34:01.742520 <6>[ 15.143559] mc: Linux media interface: v0.10
10729 12:34:01.749138 <3>[ 15.145906] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 12:34:01.755335 <3>[ 15.145929] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 12:34:01.765755 <3>[ 15.145937] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 12:34:01.772101 <4>[ 15.147960] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10733 12:34:01.782171 <6>[ 15.154529] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10734 12:34:01.788261 <3>[ 15.157002] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 12:34:01.798292 <3>[ 15.157027] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 12:34:01.804935 <3>[ 15.157041] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 12:34:01.814896 <3>[ 15.157052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 12:34:01.821619 <3>[ 15.157066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 12:34:01.831330 <3>[ 15.168235] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 12:34:01.837986 <4>[ 15.168252] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10741 12:34:01.844356 <6>[ 15.170661] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10742 12:34:01.851172 <6>[ 15.188725] videodev: Linux video capture interface: v2.00
10743 12:34:01.857892 <6>[ 15.189872] usbcore: registered new interface driver r8152
10744 12:34:01.867638 <3>[ 15.225804] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10745 12:34:01.874161 <6>[ 15.273600] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10746 12:34:01.884234 <6>[ 15.278021] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10747 12:34:01.891047 <6>[ 15.278420] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10748 12:34:01.900428 <6>[ 15.279832] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10749 12:34:01.907116 <6>[ 15.294710] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10750 12:34:01.913811 <6>[ 15.305212] usbcore: registered new interface driver cdc_ether
10751 12:34:01.920547 <6>[ 15.313353] pci_bus 0000:00: root bus resource [bus 00-ff]
10752 12:34:01.930724 <4>[ 15.318149] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10753 12:34:01.937134 <4>[ 15.318160] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10754 12:34:01.940289 <6>[ 15.329072] Bluetooth: Core ver 2.22
10755 12:34:01.947454 <6>[ 15.329106] usbcore: registered new interface driver r8153_ecm
10756 12:34:01.954000 <6>[ 15.336817] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10757 12:34:01.960274 <6>[ 15.342628] NET: Registered PF_BLUETOOTH protocol family
10758 12:34:01.970114 <6>[ 15.348405] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10759 12:34:01.977217 <6>[ 15.349531] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10760 12:34:01.990484 <6>[ 15.351190] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10761 12:34:01.997242 <6>[ 15.351334] usbcore: registered new interface driver uvcvideo
10762 12:34:02.003510 <6>[ 15.357069] Bluetooth: HCI device and connection manager initialized
10763 12:34:02.006385 <6>[ 15.357102] Bluetooth: HCI socket layer initialized
10764 12:34:02.013318 <6>[ 15.364375] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10765 12:34:02.019660 <6>[ 15.374314] Bluetooth: L2CAP socket layer initialized
10766 12:34:02.026427 <6>[ 15.383501] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10767 12:34:02.033292 <6>[ 15.384213] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10768 12:34:02.036743 <6>[ 15.392663] Bluetooth: SCO socket layer initialized
10769 12:34:02.043274 <6>[ 15.401267] r8152 2-1.3:1.0 eth0: v1.12.13
10770 12:34:02.046511 <6>[ 15.405714] pci 0000:00:00.0: supports D1 D2
10771 12:34:02.053000 <6>[ 15.419379] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10772 12:34:02.059295 <6>[ 15.420425] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10773 12:34:02.065908 <6>[ 15.439006] usbcore: registered new interface driver btusb
10774 12:34:02.075968 <4>[ 15.439761] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10775 12:34:02.083007 <3>[ 15.439772] Bluetooth: hci0: Failed to load firmware file (-2)
10776 12:34:02.089073 <3>[ 15.439776] Bluetooth: hci0: Failed to set up firmware (-2)
10777 12:34:02.099134 <4>[ 15.439780] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10778 12:34:02.105985 <6>[ 15.447336] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10779 12:34:02.112666 <6>[ 15.597617] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10780 12:34:02.119140 <6>[ 15.603909] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10781 12:34:02.129346 <6>[ 15.611464] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10782 12:34:02.135998 <6>[ 15.618958] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10783 12:34:02.139262 <6>[ 15.626544] pci 0000:01:00.0: supports D1 D2
10784 12:34:02.145445 <6>[ 15.631068] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10785 12:34:02.166148 <6>[ 15.649303] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10786 12:34:02.173006 <6>[ 15.656221] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10787 12:34:02.179433 <6>[ 15.664311] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10788 12:34:02.189186 <6>[ 15.672318] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10789 12:34:02.195883 <6>[ 15.680327] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10790 12:34:02.205966 <6>[ 15.688333] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10791 12:34:02.209333 <6>[ 15.696340] pci 0000:00:00.0: PCI bridge to [bus 01]
10792 12:34:02.219386 <6>[ 15.701563] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10793 12:34:02.226094 <6>[ 15.709721] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10794 12:34:02.232175 <6>[ 15.716927] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10795 12:34:02.238731 <6>[ 15.723729] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10796 12:34:02.257342 <5>[ 15.740174] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10797 12:34:02.277138 <5>[ 15.759758] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10798 12:34:02.283561 <4>[ 15.766674] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10799 12:34:02.290021 <6>[ 15.775556] cfg80211: failed to load regulatory.db
10800 12:34:02.340367 <6>[ 15.823213] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10801 12:34:02.347137 <6>[ 15.830734] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10802 12:34:02.371415 <6>[ 15.857475] mt7921e 0000:01:00.0: ASIC revision: 79610010
10803 12:34:02.477181 <4>[ 15.956831] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10804 12:34:02.491223 Begin: Loading essential drivers ... done.
10805 12:34:02.497640 Begin: Running /scripts/init-premount ... done.
10806 12:34:02.504734 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10807 12:34:02.511601 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10808 12:34:02.514236 Device /sys/class/net/enx002432307852 found
10809 12:34:02.517515 done.
10810 12:34:02.596213 <4>[ 16.075926] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10811 12:34:02.602555 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10812 12:34:02.715860 <4>[ 16.195138] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10813 12:34:02.831587 <4>[ 16.311041] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10814 12:34:02.947644 <4>[ 16.426937] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10815 12:34:03.063395 <4>[ 16.542905] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10816 12:34:03.179340 <4>[ 16.658812] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10817 12:34:03.295136 <4>[ 16.774794] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10818 12:34:03.410976 <4>[ 16.890716] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10819 12:34:03.527256 <4>[ 17.006664] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10820 12:34:03.572374 <6>[ 17.058775] r8152 2-1.3:1.0 enx002432307852: carrier on
10821 12:34:03.634240 <3>[ 17.120598] mt7921e 0000:01:00.0: hardware init failed
10822 12:34:03.650616 IP-Config: no response after 2 secs - giving up
10823 12:34:03.706512 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10824 12:34:03.709900 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10825 12:34:03.716284 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10826 12:34:03.726019 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10827 12:34:03.732660 host : mt8192-asurada-spherion-r0-cbg-3
10828 12:34:03.739251 domain : lava-rack
10829 12:34:03.742631 rootserver: 192.168.201.1 rootpath:
10830 12:34:03.742738 filename :
10831 12:34:03.756290 done.
10832 12:34:03.764140 Begin: Running /scripts/nfs-bottom ... done.
10833 12:34:03.782140 Begin: Running /scripts/init-bottom ... done.
10834 12:34:04.888206 <6>[ 18.374247] NET: Registered PF_INET6 protocol family
10835 12:34:04.894820 <6>[ 18.380560] Segment Routing with IPv6
10836 12:34:04.898249 <6>[ 18.384495] In-situ OAM (IOAM) with IPv6
10837 12:34:05.009965 <30>[ 18.476548] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10838 12:34:05.013174 <30>[ 18.500377] systemd[1]: Detected architecture arm64.
10839 12:34:05.033821
10840 12:34:05.036870 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10841 12:34:05.036958
10842 12:34:05.053030 <30>[ 18.539800] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10843 12:34:05.627535 <30>[ 19.110970] systemd[1]: Queued start job for default target Graphical Interface.
10844 12:34:05.647736 <30>[ 19.134391] systemd[1]: Created slice system-getty.slice.
10845 12:34:05.654585 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10846 12:34:05.671600 <30>[ 19.157959] systemd[1]: Created slice system-modprobe.slice.
10847 12:34:05.678100 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10848 12:34:05.696336 <30>[ 19.182532] systemd[1]: Created slice system-serial\x2dgetty.slice.
10849 12:34:05.706321 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10850 12:34:05.719517 <30>[ 19.205827] systemd[1]: Created slice User and Session Slice.
10851 12:34:05.725883 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10852 12:34:05.746141 <30>[ 19.229598] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10853 12:34:05.756053 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10854 12:34:05.770717 <30>[ 19.253506] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10855 12:34:05.776569 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10856 12:34:05.797903 <30>[ 19.277465] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10857 12:34:05.803851 <30>[ 19.289500] systemd[1]: Reached target Local Encrypted Volumes.
10858 12:34:05.810393 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10859 12:34:05.826742 <30>[ 19.313479] systemd[1]: Reached target Paths.
10860 12:34:05.830024 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10861 12:34:05.846728 <30>[ 19.333380] systemd[1]: Reached target Remote File Systems.
10862 12:34:05.853452 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10863 12:34:05.866855 <30>[ 19.353367] systemd[1]: Reached target Slices.
10864 12:34:05.870140 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10865 12:34:05.887125 <30>[ 19.373334] systemd[1]: Reached target Swap.
10866 12:34:05.890486 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10867 12:34:05.910139 <30>[ 19.393641] systemd[1]: Listening on initctl Compatibility Named Pipe.
10868 12:34:05.917385 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10869 12:34:05.923364 <30>[ 19.409004] systemd[1]: Listening on Journal Audit Socket.
10870 12:34:05.930577 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10871 12:34:05.943557 <30>[ 19.430317] systemd[1]: Listening on Journal Socket (/dev/log).
10872 12:34:05.950361 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10873 12:34:05.967638 <30>[ 19.454184] systemd[1]: Listening on Journal Socket.
10874 12:34:05.974294 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10875 12:34:05.991441 <30>[ 19.474717] systemd[1]: Listening on Network Service Netlink Socket.
10876 12:34:05.997780 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10877 12:34:06.013487 <30>[ 19.499907] systemd[1]: Listening on udev Control Socket.
10878 12:34:06.020147 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10879 12:34:06.034753 <30>[ 19.521660] systemd[1]: Listening on udev Kernel Socket.
10880 12:34:06.041883 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10881 12:34:06.090830 <30>[ 19.577551] systemd[1]: Mounting Huge Pages File System...
10882 12:34:06.097351 Mounting [0;1;39mHuge Pages File System[0m...
10883 12:34:06.113083 <30>[ 19.599501] systemd[1]: Mounting POSIX Message Queue File System...
10884 12:34:06.119718 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10885 12:34:06.137093 <30>[ 19.623664] systemd[1]: Mounting Kernel Debug File System...
10886 12:34:06.143609 Mounting [0;1;39mKernel Debug File System[0m...
10887 12:34:06.162476 <30>[ 19.645580] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10888 12:34:06.179199 <30>[ 19.662541] systemd[1]: Starting Create list of static device nodes for the current kernel...
10889 12:34:06.185844 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10890 12:34:06.205506 <30>[ 19.691993] systemd[1]: Starting Load Kernel Module configfs...
10891 12:34:06.212094 Starting [0;1;39mLoad Kernel Module configfs[0m...
10892 12:34:06.229363 <30>[ 19.715690] systemd[1]: Starting Load Kernel Module drm...
10893 12:34:06.235453 Starting [0;1;39mLoad Kernel Module drm[0m...
10894 12:34:06.253323 <30>[ 19.739704] systemd[1]: Starting Load Kernel Module fuse...
10895 12:34:06.259856 Starting [0;1;39mLoad Kernel Module fuse[0m...
10896 12:34:06.290345 <6>[ 19.776531] fuse: init (API version 7.37)
10897 12:34:06.299640 <30>[ 19.782006] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10898 12:34:06.335261 <30>[ 19.821802] systemd[1]: Starting Journal Service...
10899 12:34:06.338577 Starting [0;1;39mJournal Service[0m...
10900 12:34:06.364399 <30>[ 19.850422] systemd[1]: Starting Load Kernel Modules...
10901 12:34:06.370217 Starting [0;1;39mLoad Kernel Modules[0m...
10902 12:34:06.388751 <30>[ 19.871889] systemd[1]: Starting Remount Root and Kernel File Systems...
10903 12:34:06.395609 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10904 12:34:06.411251 <30>[ 19.897345] systemd[1]: Starting Coldplug All udev Devices...
10905 12:34:06.417449 Starting [0;1;39mColdplug All udev Devices[0m...
10906 12:34:06.433895 <30>[ 19.920338] systemd[1]: Mounted Huge Pages File System.
10907 12:34:06.440805 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10908 12:34:06.459860 <30>[ 19.945831] systemd[1]: Mounted POSIX Message Queue File System.
10909 12:34:06.465825 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10910 12:34:06.487797 <30>[ 19.974018] systemd[1]: Mounted Kernel Debug File System.
10911 12:34:06.494431 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10912 12:34:06.504804 <3>[ 19.987912] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 12:34:06.515206 <30>[ 19.998164] systemd[1]: Finished Create list of static device nodes for the current kernel.
10914 12:34:06.525504 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10915 12:34:06.536419 <3>[ 20.019553] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 12:34:06.543697 <30>[ 20.030307] systemd[1]: modprobe@configfs.service: Succeeded.
10917 12:34:06.550471 <30>[ 20.036930] systemd[1]: Finished Load Kernel Module configfs.
10918 12:34:06.557002 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10919 12:34:06.571706 <30>[ 20.058145] systemd[1]: modprobe@drm.service: Succeeded.
10920 12:34:06.578360 <30>[ 20.064357] systemd[1]: Finished Load Kernel Module drm.
10921 12:34:06.588355 <3>[ 20.066201] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 12:34:06.591688 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10923 12:34:06.612380 <30>[ 20.098589] systemd[1]: modprobe@fuse.service: Succeeded.
10924 12:34:06.622045 <3>[ 20.101168] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 12:34:06.628551 <30>[ 20.104923] systemd[1]: Finished Load Kernel Module fuse.
10926 12:34:06.634924 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10927 12:34:06.647842 <30>[ 20.134450] systemd[1]: Finished Load Kernel Modules.
10928 12:34:06.657804 <3>[ 20.135892] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 12:34:06.663796 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10930 12:34:06.680260 <30>[ 20.166462] systemd[1]: Finished Remount Root and Kernel File Systems.
10931 12:34:06.690373 <3>[ 20.169528] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 12:34:06.696378 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10933 12:34:06.721763 <3>[ 20.205213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 12:34:06.752095 <3>[ 20.235724] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 12:34:06.758773 <30>[ 20.237786] systemd[1]: Mounting FUSE Control File System...
10936 12:34:06.765392 Mounting [0;1;39mFUSE Control File System[0m...
10937 12:34:06.782766 <3>[ 20.265949] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 12:34:06.794360 <30>[ 20.277539] systemd[1]: Mounting Kernel Configuration File System...
10939 12:34:06.797694 Mounting [0;1;39mKernel Configuration File System[0m...
10940 12:34:06.811912 <3>[ 20.295456] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 12:34:06.827389 <30>[ 20.310495] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10942 12:34:06.837348 <30>[ 20.319508] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10943 12:34:06.847191 <3>[ 20.325198] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 12:34:06.850462 <30>[ 20.331523] systemd[1]: Starting Load/Save Random Seed...
10945 12:34:06.857056 Starting [0;1;39mLoad/Save Random Seed[0m...
10946 12:34:06.874902 <3>[ 20.358500] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 12:34:06.884146 <30>[ 20.370756] systemd[1]: Starting Apply Kernel Variables...
10948 12:34:06.890638 Starting [0;1;39mApply Kernel Variables[0m...
10949 12:34:06.907118 <3>[ 20.389985] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 12:34:06.913842 <30>[ 20.392543] systemd[1]: Starting Create System Users...
10951 12:34:06.917138 Starting [0;1;39mCreate System Users[0m...
10952 12:34:06.936793 <3>[ 20.420087] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 12:34:06.946413 <30>[ 20.433355] systemd[1]: Mounted FUSE Control File System.
10954 12:34:06.953280 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10955 12:34:06.970846 <3>[ 20.453591] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 12:34:06.977494 <30>[ 20.453962] systemd[1]: Mounted Kernel Configuration File System.
10957 12:34:06.983971 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10958 12:34:07.000127 <30>[ 20.486596] systemd[1]: Finished Load/Save Random Seed.
10959 12:34:07.006707 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10960 12:34:07.023400 <30>[ 20.509838] systemd[1]: Started Journal Service.
10961 12:34:07.030084 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10962 12:34:07.045098 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10963 12:34:07.063908 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10964 12:34:07.107231 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10965 12:34:07.125474 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10966 12:34:07.150719 <4>[ 20.627287] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10967 12:34:07.160605 <3>[ 20.643115] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10968 12:34:07.192497 [[0;1;31mFAILED[0m] Failed to <46>[ 20.673513] systemd-journald[293]: Received client request to flush runtime journal.
10969 12:34:07.195155 start [0;1;39mColdplug All udev Devices[0m.
10970 12:34:07.210849 See 'systemctl status systemd-udev-trigger.service' for details.
10971 12:34:07.231493 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10972 12:34:07.243311 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10973 12:34:07.259028 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10974 12:34:07.319311 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10975 12:34:08.560821 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10976 12:34:08.615473 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10977 12:34:08.653773 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10978 12:34:08.675973 Starting [0;1;39mNetwork Service[0m...
10979 12:34:09.030021 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10980 12:34:09.086529 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10981 12:34:09.106244 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10982 12:34:09.261994 <6>[ 22.748611] remoteproc remoteproc0: powering up scp
10983 12:34:09.293409 <4>[ 22.776903] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10984 12:34:09.299877 <3>[ 22.787037] remoteproc remoteproc0: request_firmware failed: -2
10985 12:34:09.309775 <3>[ 22.793269] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10986 12:34:09.439397 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10987 12:34:09.455094 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10988 12:34:09.476082 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10989 12:34:09.493937 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10990 12:34:09.523189 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10991 12:34:09.546971 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10992 12:34:09.566794 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10993 12:34:09.619029 Starting [0;1;39mNetwork Name Resolution[0m...
10994 12:34:09.644122 Starting [0;1;39mNetwork Time Synchronization[0m...
10995 12:34:09.661379 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10996 12:34:09.707190 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10997 12:34:09.873146 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10998 12:34:09.890803 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10999 12:34:09.910304 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11000 12:34:09.926376 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11001 12:34:09.942588 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11002 12:34:10.097675 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11003 12:34:10.147499 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11004 12:34:10.262604 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11005 12:34:10.708134 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11006 12:34:10.722440 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11007 12:34:10.887365 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11008 12:34:10.898854 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11009 12:34:10.914676 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11010 12:34:10.951332 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11011 12:34:11.283047 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11012 12:34:11.342648 Starting [0;1;39mUser Login Management[0m...
11013 12:34:11.359672 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11014 12:34:11.375628 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11015 12:34:11.393826 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11016 12:34:11.431064 Starting [0;1;39mPermit User Sessions[0m...
11017 12:34:11.536502 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11018 12:34:11.590730 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11019 12:34:11.641059 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11020 12:34:11.659363 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11021 12:34:11.679582 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11022 12:34:11.696261 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11023 12:34:11.711625 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11024 12:34:11.726857 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11025 12:34:11.774395 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11026 12:34:11.820374 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11027 12:34:11.896585
11028 12:34:11.896754
11029 12:34:11.899997 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11030 12:34:11.900105
11031 12:34:11.903414 debian-bullseye-arm64 login: root (automatic login)
11032 12:34:11.903497
11033 12:34:11.903568
11034 12:34:12.232420 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023 aarch64
11035 12:34:12.232561
11036 12:34:12.238812 The programs included with the Debian GNU/Linux system are free software;
11037 12:34:12.245564 the exact distribution terms for each program are described in the
11038 12:34:12.248929 individual files in /usr/share/doc/*/copyright.
11039 12:34:12.249036
11040 12:34:12.254950 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11041 12:34:12.255059 permitted by applicable law.
11042 12:34:13.082371 Matched prompt #10: / #
11044 12:34:13.082759 Setting prompt string to ['/ #']
11045 12:34:13.082888 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11047 12:34:13.083194 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11048 12:34:13.083316 start: 2.2.6 expect-shell-connection (timeout 00:03:19) [common]
11049 12:34:13.083444 Setting prompt string to ['/ #']
11050 12:34:13.083509 Forcing a shell prompt, looking for ['/ #']
11052 12:34:13.133711 / #
11053 12:34:13.133888 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11054 12:34:13.134002 Waiting using forced prompt support (timeout 00:02:30)
11055 12:34:13.139028
11056 12:34:13.139337 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11057 12:34:13.139446 start: 2.2.7 export-device-env (timeout 00:03:19) [common]
11059 12:34:13.239787 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605810/extract-nfsrootfs-mg6xi24_'
11060 12:34:13.245018 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605810/extract-nfsrootfs-mg6xi24_'
11062 12:34:13.345579 / # export NFS_SERVER_IP='192.168.201.1'
11063 12:34:13.350404 export NFS_SERVER_IP='192.168.201.1'
11064 12:34:13.350699 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11065 12:34:13.350814 end: 2.2 depthcharge-retry (duration 00:01:42) [common]
11066 12:34:13.350925 end: 2 depthcharge-action (duration 00:01:42) [common]
11067 12:34:13.351037 start: 3 lava-test-retry (timeout 00:07:30) [common]
11068 12:34:13.351140 start: 3.1 lava-test-shell (timeout 00:07:30) [common]
11069 12:34:13.351252 Using namespace: common
11071 12:34:13.451695 / # #
11072 12:34:13.451885 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11073 12:34:13.456562 #
11074 12:34:13.456867 Using /lava-10605810
11076 12:34:13.557332 / # export SHELL=/bin/bash
11077 12:34:13.562965 export SHELL=/bin/bash
11079 12:34:13.664675 / # . /lava-10605810/environment
11080 12:34:13.671114 . /lava-10605810/environment
11082 12:34:13.778018 / # /lava-10605810/bin/lava-test-runner /lava-10605810/0
11083 12:34:13.778703 Test shell timeout: 10s (minimum of the action and connection timeout)
11084 12:34:13.784673 /lava-10605810/bin/lava-test-runner /lava-10605810/0
11085 12:34:14.069388 + export TESTRUN_ID=0_timesync-off
11086 12:34:14.072519 + TESTRUN_ID=0_timesync-off
11087 12:34:14.075866 + cd /lava-10605810/0/tests/0_timesync-off
11088 12:34:14.079299 ++ cat uuid
11089 12:34:14.083265 + UUID=10605810_1.6.2.3.1
11090 12:34:14.083398 + set +x
11091 12:34:14.089847 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10605810_1.6.2.3.1>
11092 12:34:14.090152 Received signal: <STARTRUN> 0_timesync-off 10605810_1.6.2.3.1
11093 12:34:14.090261 Starting test lava.0_timesync-off (10605810_1.6.2.3.1)
11094 12:34:14.090380 Skipping test definition patterns.
11095 12:34:14.093102 + systemctl stop systemd-timesyncd
11096 12:34:14.131083 + set +x
11097 12:34:14.134343 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10605810_1.6.2.3.1>
11098 12:34:14.134628 Received signal: <ENDRUN> 0_timesync-off 10605810_1.6.2.3.1
11099 12:34:14.134755 Ending use of test pattern.
11100 12:34:14.134850 Ending test lava.0_timesync-off (10605810_1.6.2.3.1), duration 0.04
11102 12:34:14.211020 + export TESTRUN_ID=1_kselftest-arm64
11103 12:34:14.211159 + TESTRUN_ID=1_kselftest-arm64
11104 12:34:14.217615 + cd /lava-10605810/0/tests/1_kselftest-arm64
11105 12:34:14.217724 ++ cat uuid
11106 12:34:14.220904 + UUID=10605810_1.6.2.3.5
11107 12:34:14.221015 + set +x
11108 12:34:14.227309 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 10605810_1.6.2.3.5>
11109 12:34:14.227621 Received signal: <STARTRUN> 1_kselftest-arm64 10605810_1.6.2.3.5
11110 12:34:14.227720 Starting test lava.1_kselftest-arm64 (10605810_1.6.2.3.5)
11111 12:34:14.227835 Skipping test definition patterns.
11112 12:34:14.230574 + cd ./automated/linux/kselftest/
11113 12:34:14.256807 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11114 12:34:14.289487 INFO: install_deps skipped
11115 12:34:14.457523 --2023-06-06 12:34:14-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11116 12:34:14.478338 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11117 12:34:14.621348 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11118 12:34:14.764498 HTTP request sent, awaiting response... 200 OK
11119 12:34:14.767891 Length: 2699740 (2.6M) [application/octet-stream]
11120 12:34:14.771165 Saving to: 'kselftest.tar.xz'
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11133 12:34:16.920514
11134 12:34:17.154879 2023-06-06 12:34:17 (1.20 MB/s) - 'kselftest.tar.xz' saved [2699740/2699740]
11135 12:34:17.155045
11136 12:34:22.611539 skiplist:
11137 12:34:22.614969 ========================================
11138 12:34:22.618380 ========================================
11139 12:34:22.662905 arm64:tags_test
11140 12:34:22.666272 arm64:run_tags_test.sh
11141 12:34:22.666394 arm64:fake_sigreturn_bad_magic
11142 12:34:22.668998 arm64:fake_sigreturn_bad_size
11143 12:34:22.672305 arm64:fake_sigreturn_bad_size_for_magic0
11144 12:34:22.675523 arm64:fake_sigreturn_duplicated_fpsimd
11145 12:34:22.679438 arm64:fake_sigreturn_misaligned_sp
11146 12:34:22.682807 arm64:fake_sigreturn_missing_fpsimd
11147 12:34:22.685493 arm64:fake_sigreturn_sme_change_vl
11148 12:34:22.688791 arm64:fake_sigreturn_sve_change_vl
11149 12:34:22.692018 arm64:mangle_pstate_invalid_compat_toggle
11150 12:34:22.695454 arm64:mangle_pstate_invalid_daif_bits
11151 12:34:22.698770 arm64:mangle_pstate_invalid_mode_el1h
11152 12:34:22.702514 arm64:mangle_pstate_invalid_mode_el1t
11153 12:34:22.705909 arm64:mangle_pstate_invalid_mode_el2h
11154 12:34:22.708634 arm64:mangle_pstate_invalid_mode_el2t
11155 12:34:22.711973 arm64:mangle_pstate_invalid_mode_el3h
11156 12:34:22.715275 arm64:mangle_pstate_invalid_mode_el3t
11157 12:34:22.718611 arm64:sme_trap_no_sm
11158 12:34:22.722003 arm64:sme_trap_non_streaming
11159 12:34:22.722114 arm64:sme_trap_za
11160 12:34:22.725314 arm64:sme_vl
11161 12:34:22.725439 arm64:ssve_regs
11162 12:34:22.728760 arm64:sve_regs
11163 12:34:22.728843 arm64:sve_vl
11164 12:34:22.728909 arm64:za_no_regs
11165 12:34:22.732214 arm64:za_regs
11166 12:34:22.732307 arm64:pac
11167 12:34:22.735644 arm64:fp-stress
11168 12:34:22.735733 arm64:sve-ptrace
11169 12:34:22.738994 arm64:sve-probe-vls
11170 12:34:22.739099 arm64:vec-syscfg
11171 12:34:22.739197 arm64:za-fork
11172 12:34:22.741740 arm64:za-ptrace
11173 12:34:22.744967 arm64:check_buffer_fill
11174 12:34:22.745053 arm64:check_child_memory
11175 12:34:22.748355 arm64:check_gcr_el1_cswitch
11176 12:34:22.751594 arm64:check_ksm_options
11177 12:34:22.751681 arm64:check_mmap_options
11178 12:34:22.755532 arm64:check_prctl
11179 12:34:22.758846 arm64:check_tags_inclusion
11180 12:34:22.758932 arm64:check_user_mem
11181 12:34:22.761446 arm64:btitest
11182 12:34:22.761531 arm64:nobtitest
11183 12:34:22.761599 arm64:hwcap
11184 12:34:22.764824 arm64:ptrace
11185 12:34:22.764926 arm64:syscall-abi
11186 12:34:22.768222 arm64:tpidr2
11187 12:34:22.771613 ============== Tests to run ===============
11188 12:34:22.771706 arm64:tags_test
11189 12:34:22.775143 arm64:run_tags_test.sh
11190 12:34:22.778468 arm64:fake_sigreturn_bad_magic
11191 12:34:22.778562 arm64:fake_sigreturn_bad_size
11192 12:34:22.784975 arm64:fake_sigreturn_bad_size_for_magic0
11193 12:34:22.788355 arm64:fake_sigreturn_duplicated_fpsimd
11194 12:34:22.791641 arm64:fake_sigreturn_misaligned_sp
11195 12:34:22.794906 arm64:fake_sigreturn_missing_fpsimd
11196 12:34:22.794993 arm64:fake_sigreturn_sme_change_vl
11197 12:34:22.798018 arm64:fake_sigreturn_sve_change_vl
11198 12:34:22.804813 arm64:mangle_pstate_invalid_compat_toggle
11199 12:34:22.807900 arm64:mangle_pstate_invalid_daif_bits
11200 12:34:22.811209 arm64:mangle_pstate_invalid_mode_el1h
11201 12:34:22.814526 arm64:mangle_pstate_invalid_mode_el1t
11202 12:34:22.817942 arm64:mangle_pstate_invalid_mode_el2h
11203 12:34:22.821266 arm64:mangle_pstate_invalid_mode_el2t
11204 12:34:22.824759 arm64:mangle_pstate_invalid_mode_el3h
11205 12:34:22.828125 arm64:mangle_pstate_invalid_mode_el3t
11206 12:34:22.828211 arm64:sme_trap_no_sm
11207 12:34:22.831483 arm64:sme_trap_non_streaming
11208 12:34:22.834789 arm64:sme_trap_za
11209 12:34:22.834873 arm64:sme_vl
11210 12:34:22.834939 arm64:ssve_regs
11211 12:34:22.838220 arm64:sve_regs
11212 12:34:22.838304 arm64:sve_vl
11213 12:34:22.841597 arm64:za_no_regs
11214 12:34:22.841685 arm64:za_regs
11215 12:34:22.841752 arm64:pac
11216 12:34:22.844985 arm64:fp-stress
11217 12:34:22.845069 arm64:sve-ptrace
11218 12:34:22.848214 arm64:sve-probe-vls
11219 12:34:22.848298 arm64:vec-syscfg
11220 12:34:22.851386 arm64:za-fork
11221 12:34:22.851470 arm64:za-ptrace
11222 12:34:22.854744 arm64:check_buffer_fill
11223 12:34:22.854828 arm64:check_child_memory
11224 12:34:22.857948 arm64:check_gcr_el1_cswitch
11225 12:34:22.861265 arm64:check_ksm_options
11226 12:34:22.864574 arm64:check_mmap_options
11227 12:34:22.864687 arm64:check_prctl
11228 12:34:22.867826 arm64:check_tags_inclusion
11229 12:34:22.867930 arm64:check_user_mem
11230 12:34:22.871175 arm64:btitest
11231 12:34:22.871277 arm64:nobtitest
11232 12:34:22.874499 arm64:hwcap
11233 12:34:22.874578 arm64:ptrace
11234 12:34:22.874640 arm64:syscall-abi
11235 12:34:22.877995 arm64:tpidr2
11236 12:34:22.880598 ===========End Tests to run ===============
11237 12:34:23.133992 <12>[ 36.622022] kselftest: Running tests in arm64
11238 12:34:23.145829 TAP version 13
11239 12:34:23.161111 1..48
11240 12:34:23.180828 # selftests: arm64: tags_test
11241 12:34:23.590202 ok 1 selftests: arm64: tags_test
11242 12:34:23.605894 # selftests: arm64: run_tags_test.sh
11243 12:34:23.660936 # --------------------
11244 12:34:23.664351 # running tags test
11245 12:34:23.664759 # --------------------
11246 12:34:23.667622 # [PASS]
11247 12:34:23.670959 ok 2 selftests: arm64: run_tags_test.sh
11248 12:34:23.683781 # selftests: arm64: fake_sigreturn_bad_magic
11249 12:34:23.736773 # Registered handlers for all signals.
11250 12:34:23.737240 # Detected MINSTKSIGSZ:4720
11251 12:34:23.739390 # Testcase initialized.
11252 12:34:23.742867 # uc context validated.
11253 12:34:23.746126 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11254 12:34:23.749375 # Handled SIG_COPYCTX
11255 12:34:23.749805 # Available space:3568
11256 12:34:23.756483 # Using badly built context - ERR: BAD MAGIC !
11257 12:34:23.762471 # SIG_OK -- SP:0xFFFFC7E3FE40 si_addr@:0xffffc7e3fe40 si_code:2 token@:0xffffc7e3ebe0 offset:-4704
11258 12:34:23.765836 # ==>> completed. PASS(1)
11259 12:34:23.772493 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11260 12:34:23.779162 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC7E3EBE0
11261 12:34:23.783034 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11262 12:34:23.789544 # selftests: arm64: fake_sigreturn_bad_size
11263 12:34:23.811265 # Registered handlers for all signals.
11264 12:34:23.811798 # Detected MINSTKSIGSZ:4720
11265 12:34:23.814511 # Testcase initialized.
11266 12:34:23.817886 # uc context validated.
11267 12:34:23.821121 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11268 12:34:23.824527 # Handled SIG_COPYCTX
11269 12:34:23.824978 # Available space:3568
11270 12:34:23.827858 # uc context validated.
11271 12:34:23.834440 # Using badly built context - ERR: Bad size for esr_context
11272 12:34:23.840865 # SIG_OK -- SP:0xFFFFC69D1380 si_addr@:0xffffc69d1380 si_code:2 token@:0xffffc69d0120 offset:-4704
11273 12:34:23.844330 # ==>> completed. PASS(1)
11274 12:34:23.850640 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11275 12:34:23.857664 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC69D0120
11276 12:34:23.860684 ok 4 selftests: arm64: fake_sigreturn_bad_size
11277 12:34:23.867339 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11278 12:34:23.886423 # Registered handlers for all signals.
11279 12:34:23.886512 # Detected MINSTKSIGSZ:4720
11280 12:34:23.889116 # Testcase initialized.
11281 12:34:23.892435 # uc context validated.
11282 12:34:23.895631 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11283 12:34:23.898825 # Handled SIG_COPYCTX
11284 12:34:23.898910 # Available space:3568
11285 12:34:23.905369 # Using badly built context - ERR: Bad size for terminator
11286 12:34:23.915228 # SIG_OK -- SP:0xFFFFDE70AB90 si_addr@:0xffffde70ab90 si_code:2 token@:0xffffde709930 offset:-4704
11287 12:34:23.915314 # ==>> completed. PASS(1)
11288 12:34:23.925657 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11289 12:34:23.932369 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDE709930
11290 12:34:23.935628 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11291 12:34:23.942060 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11292 12:34:23.957087 # Registered handlers for all signals.
11293 12:34:23.957229 # Detected MINSTKSIGSZ:4720
11294 12:34:23.960303 # Testcase initialized.
11295 12:34:23.964157 # uc context validated.
11296 12:34:23.967313 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11297 12:34:23.970681 # Handled SIG_COPYCTX
11298 12:34:23.970765 # Available space:3568
11299 12:34:23.977305 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11300 12:34:23.987260 # SIG_OK -- SP:0xFFFFF58367D0 si_addr@:0xfffff58367d0 si_code:2 token@:0xfffff5835570 offset:-4704
11301 12:34:23.987396 # ==>> completed. PASS(1)
11302 12:34:23.997144 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11303 12:34:24.003717 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF5835570
11304 12:34:24.007002 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11305 12:34:24.010131 # selftests: arm64: fake_sigreturn_misaligned_sp
11306 12:34:24.028956 # Registered handlers for all signals.
11307 12:34:24.029065 # Detected MINSTKSIGSZ:4720
11308 12:34:24.032204 # Testcase initialized.
11309 12:34:24.035378 # uc context validated.
11310 12:34:24.038703 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11311 12:34:24.042019 # Handled SIG_COPYCTX
11312 12:34:24.048986 # SIG_OK -- SP:0xFFFFCB8656A3 si_addr@:0xffffcb8656a3 si_code:2 token@:0xffffcb8656a3 offset:0
11313 12:34:24.052000 # ==>> completed. PASS(1)
11314 12:34:24.058561 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11315 12:34:24.065309 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCB8656A3
11316 12:34:24.071635 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11317 12:34:24.074824 # selftests: arm64: fake_sigreturn_missing_fpsimd
11318 12:34:24.100131 # Registered handlers for all signals.
11319 12:34:24.100263 # Detected MINSTKSIGSZ:4720
11320 12:34:24.103279 # Testcase initialized.
11321 12:34:24.106625 # uc context validated.
11322 12:34:24.109815 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11323 12:34:24.113171 # Handled SIG_COPYCTX
11324 12:34:24.116431 # Mangling template header. Spare space:4096
11325 12:34:24.119666 # Using badly built context - ERR: Missing FPSIMD
11326 12:34:24.129953 # SIG_OK -- SP:0xFFFFDAFB3130 si_addr@:0xffffdafb3130 si_code:2 token@:0xffffdafb1ed0 offset:-4704
11327 12:34:24.133280 # ==>> completed. PASS(1)
11328 12:34:24.139957 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11329 12:34:24.146359 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDAFB1ED0
11330 12:34:24.149783 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11331 12:34:24.156271 # selftests: arm64: fake_sigreturn_sme_change_vl
11332 12:34:24.170404 # Registered handlers for all signals.
11333 12:34:24.170607 # Detected MINSTKSIGSZ:4720
11334 12:34:24.173631 # ==>> completed. SKIP.
11335 12:34:24.180649 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11336 12:34:24.183950 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11337 12:34:24.190428 # selftests: arm64: fake_sigreturn_sve_change_vl
11338 12:34:24.243248 # Registered handlers for all signals.
11339 12:34:24.243450 # Detected MINSTKSIGSZ:4720
11340 12:34:24.246480 # ==>> completed. SKIP.
11341 12:34:24.253111 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11342 12:34:24.256961 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11343 12:34:24.263269 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11344 12:34:24.317263 # Registered handlers for all signals.
11345 12:34:24.317869 # Detected MINSTKSIGSZ:4720
11346 12:34:24.320773 # Testcase initialized.
11347 12:34:24.324047 # uc context validated.
11348 12:34:24.324517 # Handled SIG_TRIG
11349 12:34:24.333652 # SIG_OK -- SP:0xFFFFCAB687D0 si_addr@:0xffffcab687d0 si_code:2 token@:(nil) offset:-281474082703312
11350 12:34:24.336719 # ==>> completed. PASS(1)
11351 12:34:24.343267 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11352 12:34:24.350609 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11353 12:34:24.353254 # selftests: arm64: mangle_pstate_invalid_daif_bits
11354 12:34:24.390190 # Registered handlers for all signals.
11355 12:34:24.390674 # Detected MINSTKSIGSZ:4720
11356 12:34:24.394088 # Testcase initialized.
11357 12:34:24.397439 # uc context validated.
11358 12:34:24.397869 # Handled SIG_TRIG
11359 12:34:24.407292 # SIG_OK -- SP:0xFFFFDF39CBD0 si_addr@:0xffffdf39cbd0 si_code:2 token@:(nil) offset:-281474426850256
11360 12:34:24.410484 # ==>> completed. PASS(1)
11361 12:34:24.417035 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11362 12:34:24.420400 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11363 12:34:24.426927 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11364 12:34:24.463314 # Registered handlers for all signals.
11365 12:34:24.463789 # Detected MINSTKSIGSZ:4720
11366 12:34:24.466490 # Testcase initialized.
11367 12:34:24.469641 # uc context validated.
11368 12:34:24.470080 # Handled SIG_TRIG
11369 12:34:24.479119 # SIG_OK -- SP:0xFFFFD9FDE120 si_addr@:0xffffd9fde120 si_code:2 token@:(nil) offset:-281474339037472
11370 12:34:24.482343 # ==>> completed. PASS(1)
11371 12:34:24.489455 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11372 12:34:24.492627 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11373 12:34:24.499078 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11374 12:34:24.537237 # Registered handlers for all signals.
11375 12:34:24.537677 # Detected MINSTKSIGSZ:4720
11376 12:34:24.540449 # Testcase initialized.
11377 12:34:24.543789 # uc context validated.
11378 12:34:24.544214 # Handled SIG_TRIG
11379 12:34:24.553693 # SIG_OK -- SP:0xFFFFE8B12EC0 si_addr@:0xffffe8b12ec0 si_code:2 token@:(nil) offset:-281474585669312
11380 12:34:24.557537 # ==>> completed. PASS(1)
11381 12:34:24.564218 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11382 12:34:24.567564 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11383 12:34:24.573365 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11384 12:34:24.613214 # Registered handlers for all signals.
11385 12:34:24.613835 # Detected MINSTKSIGSZ:4720
11386 12:34:24.616472 # Testcase initialized.
11387 12:34:24.619867 # uc context validated.
11388 12:34:24.620513 # Handled SIG_TRIG
11389 12:34:24.629692 # SIG_OK -- SP:0xFFFFEF2EA160 si_addr@:0xffffef2ea160 si_code:2 token@:(nil) offset:-281474694553952
11390 12:34:24.632907 # ==>> completed. PASS(1)
11391 12:34:24.639521 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11392 12:34:24.642762 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11393 12:34:24.649291 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11394 12:34:24.686083 # Registered handlers for all signals.
11395 12:34:24.686785 # Detected MINSTKSIGSZ:4720
11396 12:34:24.689276 # Testcase initialized.
11397 12:34:24.692405 # uc context validated.
11398 12:34:24.693053 # Handled SIG_TRIG
11399 12:34:24.702790 # SIG_OK -- SP:0xFFFFCD88D1A0 si_addr@:0xffffcd88d1a0 si_code:2 token@:(nil) offset:-281474130039200
11400 12:34:24.705908 # ==>> completed. PASS(1)
11401 12:34:24.712265 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11402 12:34:24.716075 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11403 12:34:24.722505 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11404 12:34:24.758682 # Registered handlers for all signals.
11405 12:34:24.759118 # Detected MINSTKSIGSZ:4720
11406 12:34:24.761883 # Testcase initialized.
11407 12:34:24.765697 # uc context validated.
11408 12:34:24.766193 # Handled SIG_TRIG
11409 12:34:24.775473 # SIG_OK -- SP:0xFFFFC59B0FE0 si_addr@:0xffffc59b0fe0 si_code:2 token@:(nil) offset:-281473997017056
11410 12:34:24.778796 # ==>> completed. PASS(1)
11411 12:34:24.785118 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11412 12:34:24.788116 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11413 12:34:24.795287 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11414 12:34:24.832241 # Registered handlers for all signals.
11415 12:34:24.832774 # Detected MINSTKSIGSZ:4720
11416 12:34:24.835318 # Testcase initialized.
11417 12:34:24.839193 # uc context validated.
11418 12:34:24.839839 # Handled SIG_TRIG
11419 12:34:24.849096 # SIG_OK -- SP:0xFFFFC9200E60 si_addr@:0xffffc9200e60 si_code:2 token@:(nil) offset:-281474056064608
11420 12:34:24.852475 # ==>> completed. PASS(1)
11421 12:34:24.858879 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11422 12:34:24.862207 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11423 12:34:24.865384 # selftests: arm64: sme_trap_no_sm
11424 12:34:24.906290 # Registered handlers for all signals.
11425 12:34:24.907080 # Detected MINSTKSIGSZ:4720
11426 12:34:24.909648 # ==>> completed. SKIP.
11427 12:34:24.919089 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11428 12:34:24.923034 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11429 12:34:24.926346 # selftests: arm64: sme_trap_non_streaming
11430 12:34:24.978067 # Registered handlers for all signals.
11431 12:34:24.978200 # Detected MINSTKSIGSZ:4720
11432 12:34:24.981354 # ==>> completed. SKIP.
11433 12:34:24.991248 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11434 12:34:24.998021 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11435 12:34:25.001227 # selftests: arm64: sme_trap_za
11436 12:34:25.049469 # Registered handlers for all signals.
11437 12:34:25.049908 # Detected MINSTKSIGSZ:4720
11438 12:34:25.052818 # Testcase initialized.
11439 12:34:25.062639 # SIG_OK -- SP:0xFFFFFF8F58B0 si_addr@:0xaaaaaee92510 si_code:1 token@:(nil) offset:-187650055677200
11440 12:34:25.063274 # ==>> completed. PASS(1)
11441 12:34:25.072428 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11442 12:34:25.075717 ok 21 selftests: arm64: sme_trap_za
11443 12:34:25.076380 # selftests: arm64: sme_vl
11444 12:34:25.123414 # Registered handlers for all signals.
11445 12:34:25.123888 # Detected MINSTKSIGSZ:4720
11446 12:34:25.127251 # ==>> completed. SKIP.
11447 12:34:25.130359 # # SME VL :: Check that we get the right SME VL reported
11448 12:34:25.136838 ok 22 selftests: arm64: sme_vl # SKIP
11449 12:34:25.140334 # selftests: arm64: ssve_regs
11450 12:34:25.197390 # Registered handlers for all signals.
11451 12:34:25.198070 # Detected MINSTKSIGSZ:4720
11452 12:34:25.200786 # ==>> completed. SKIP.
11453 12:34:25.207308 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11454 12:34:25.213849 ok 23 selftests: arm64: ssve_regs # SKIP
11455 12:34:25.214536 # selftests: arm64: sve_regs
11456 12:34:25.269670 # Registered handlers for all signals.
11457 12:34:25.269813 # Detected MINSTKSIGSZ:4720
11458 12:34:25.273049 # ==>> completed. SKIP.
11459 12:34:25.279567 # # SVE registers :: Check that we get the right SVE registers reported
11460 12:34:25.282249 ok 24 selftests: arm64: sve_regs # SKIP
11461 12:34:25.285940 # selftests: arm64: sve_vl
11462 12:34:25.340839 # Registered handlers for all signals.
11463 12:34:25.341065 # Detected MINSTKSIGSZ:4720
11464 12:34:25.343995 # ==>> completed. SKIP.
11465 12:34:25.350994 # # SVE VL :: Check that we get the right SVE VL reported
11466 12:34:25.354278 ok 25 selftests: arm64: sve_vl # SKIP
11467 12:34:25.357174 # selftests: arm64: za_no_regs
11468 12:34:25.412773 # Registered handlers for all signals.
11469 12:34:25.413405 # Detected MINSTKSIGSZ:4720
11470 12:34:25.416175 # ==>> completed. SKIP.
11471 12:34:25.422662 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11472 12:34:25.426291 ok 26 selftests: arm64: za_no_regs # SKIP
11473 12:34:25.429788 # selftests: arm64: za_regs
11474 12:34:25.486695 # Registered handlers for all signals.
11475 12:34:25.487455 # Detected MINSTKSIGSZ:4720
11476 12:34:25.490470 # ==>> completed. SKIP.
11477 12:34:25.496813 # # ZA register :: Check that we get the right ZA registers reported
11478 12:34:25.500190 ok 27 selftests: arm64: za_regs # SKIP
11479 12:34:25.503344 # selftests: arm64: pac
11480 12:34:25.558565 # TAP version 13
11481 12:34:25.559064 # 1..7
11482 12:34:25.562196 # # Starting 7 tests from 1 test cases.
11483 12:34:25.565345 # # RUN global.corrupt_pac ...
11484 12:34:25.569156 # # SKIP PAUTH not enabled
11485 12:34:25.572281 # # OK global.corrupt_pac
11486 12:34:25.575591 # ok 1 # SKIP PAUTH not enabled
11487 12:34:25.582116 # # RUN global.pac_instructions_not_nop ...
11488 12:34:25.585589 # # SKIP PAUTH not enabled
11489 12:34:25.588875 # # OK global.pac_instructions_not_nop
11490 12:34:25.592271 # ok 2 # SKIP PAUTH not enabled
11491 12:34:25.598783 # # RUN global.pac_instructions_not_nop_generic ...
11492 12:34:25.602107 # # SKIP Generic PAUTH not enabled
11493 12:34:25.605304 # # OK global.pac_instructions_not_nop_generic
11494 12:34:25.608506 # ok 3 # SKIP Generic PAUTH not enabled
11495 12:34:25.615087 # # RUN global.single_thread_different_keys ...
11496 12:34:25.618504 # # SKIP PAUTH not enabled
11497 12:34:25.625053 # # OK global.single_thread_different_keys
11498 12:34:25.625489 # ok 4 # SKIP PAUTH not enabled
11499 12:34:25.631668 # # RUN global.exec_changed_keys ...
11500 12:34:25.635011 # # SKIP PAUTH not enabled
11501 12:34:25.638367 # # OK global.exec_changed_keys
11502 12:34:25.641738 # ok 5 # SKIP PAUTH not enabled
11503 12:34:25.645004 # # RUN global.context_switch_keep_keys ...
11504 12:34:25.648322 # # SKIP PAUTH not enabled
11505 12:34:25.654907 # # OK global.context_switch_keep_keys
11506 12:34:25.655383 # ok 6 # SKIP PAUTH not enabled
11507 12:34:25.661998 # # RUN global.context_switch_keep_keys_generic ...
11508 12:34:25.665013 # # SKIP Generic PAUTH not enabled
11509 12:34:25.671456 # # OK global.context_switch_keep_keys_generic
11510 12:34:25.674630 # ok 7 # SKIP Generic PAUTH not enabled
11511 12:34:25.678250 # # PASSED: 7 / 7 tests passed.
11512 12:34:25.681366 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11513 12:34:25.684583 ok 28 selftests: arm64: pac
11514 12:34:25.687856 # selftests: arm64: fp-stress
11515 12:34:32.668208 <6>[ 46.161178] vpu: disabling
11516 12:34:32.671432 <6>[ 46.164239] vproc2: disabling
11517 12:34:32.674638 <6>[ 46.167526] vproc1: disabling
11518 12:34:32.677938 <6>[ 46.170802] vaud18: disabling
11519 12:34:32.685057 <6>[ 46.174238] vsram_others: disabling
11520 12:34:32.688176 <6>[ 46.178136] va09: disabling
11521 12:34:32.691060 <6>[ 46.181256] vsram_md: disabling
11522 12:34:32.694797 <6>[ 46.184754] Vgpu: disabling
11523 12:34:35.648403 # TAP version 13
11524 12:34:35.648603 # 1..16
11525 12:34:35.651309 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11526 12:34:35.655511 # # Will run for 10s
11527 12:34:35.655937 # # Started FPSIMD-0-0
11528 12:34:35.658527 # # Started FPSIMD-0-1
11529 12:34:35.661675 # # Started FPSIMD-1-0
11530 12:34:35.661758 # # Started FPSIMD-1-1
11531 12:34:35.665181 # # Started FPSIMD-2-0
11532 12:34:35.665264 # # Started FPSIMD-2-1
11533 12:34:35.668057 # # Started FPSIMD-3-0
11534 12:34:35.671319 # # Started FPSIMD-3-1
11535 12:34:35.671409 # # Started FPSIMD-4-0
11536 12:34:35.675199 # # Started FPSIMD-4-1
11537 12:34:35.678341 # # Started FPSIMD-5-0
11538 12:34:35.678423 # # Started FPSIMD-5-1
11539 12:34:35.681787 # # Started FPSIMD-6-0
11540 12:34:35.681875 # # Started FPSIMD-6-1
11541 12:34:35.685037 # # Started FPSIMD-7-0
11542 12:34:35.688128 # # Started FPSIMD-7-1
11543 12:34:35.691249 # # FPSIMD-0-1: Vector length: 128 bits
11544 12:34:35.694355 # # FPSIMD-0-1: PID: 1136
11545 12:34:35.698188 # # FPSIMD-0-0: Vector length: 128 bits
11546 12:34:35.698269 # # FPSIMD-0-0: PID: 1135
11547 12:34:35.701313 # # FPSIMD-1-0: Vector length: 128 bits
11548 12:34:35.704649 # # FPSIMD-1-0: PID: 1137
11549 12:34:35.707827 # # FPSIMD-5-1: Vector length: 128 bits
11550 12:34:35.711030 # # FPSIMD-5-1: PID: 1146
11551 12:34:35.714255 # # FPSIMD-3-0: Vector length: 128 bits
11552 12:34:35.717636 # # FPSIMD-3-0: PID: 1141
11553 12:34:35.720890 # # FPSIMD-2-1: Vector length: 128 bits
11554 12:34:35.720978 # # FPSIMD-2-1: PID: 1140
11555 12:34:35.727863 # # FPSIMD-4-0: Vector length: 128 bits
11556 12:34:35.727959 # # FPSIMD-4-0: PID: 1143
11557 12:34:35.731089 # # FPSIMD-5-0: Vector length: 128 bits
11558 12:34:35.734486 # # FPSIMD-5-0: PID: 1145
11559 12:34:35.737458 # # FPSIMD-1-1: Vector length: 128 bits
11560 12:34:35.740796 # # FPSIMD-1-1: PID: 1138
11561 12:34:35.743895 # # FPSIMD-2-0: Vector length: 128 bits
11562 12:34:35.747650 # # FPSIMD-2-0: PID: 1139
11563 12:34:35.750882 # # FPSIMD-6-0: Vector length: 128 bits
11564 12:34:35.751307 # # FPSIMD-6-0: PID: 1147
11565 12:34:35.754028 # # FPSIMD-4-1: Vector length: 128 bits
11566 12:34:35.757820 # # FPSIMD-4-1: PID: 1144
11567 12:34:35.760983 # # FPSIMD-7-0: Vector length: 128 bits
11568 12:34:35.764316 # # FPSIMD-7-0: PID: 1149
11569 12:34:35.767387 # # FPSIMD-3-1: Vector length: 128 bits
11570 12:34:35.770622 # # FPSIMD-3-1: PID: 1142
11571 12:34:35.773934 # # FPSIMD-6-1: Vector length: 128 bits
11572 12:34:35.777287 # # FPSIMD-6-1: PID: 1148
11573 12:34:35.780485 # # FPSIMD-7-1: Vector length: 128 bits
11574 12:34:35.780913 # # FPSIMD-7-1: PID: 1150
11575 12:34:35.784288 # # Finishing up...
11576 12:34:35.791043 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=375823, signals=10
11577 12:34:35.797158 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1406777, signals=10
11578 12:34:35.804179 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=417122, signals=10
11579 12:34:35.814147 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=345564, signals=10
11580 12:34:35.820338 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1518775, signals=10
11581 12:34:35.826921 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1260464, signals=10
11582 12:34:35.833497 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1844219, signals=10
11583 12:34:35.836702 # ok 1 FPSIMD-0-0
11584 12:34:35.837136 # ok 2 FPSIMD-0-1
11585 12:34:35.839965 # ok 3 FPSIMD-1-0
11586 12:34:35.840427 # ok 4 FPSIMD-1-1
11587 12:34:35.843655 # ok 5 FPSIMD-2-0
11588 12:34:35.844116 # ok 6 FPSIMD-2-1
11589 12:34:35.846683 # ok 7 FPSIMD-3-0
11590 12:34:35.847115 # ok 8 FPSIMD-3-1
11591 12:34:35.850189 # ok 9 FPSIMD-4-0
11592 12:34:35.850622 # ok 10 FPSIMD-4-1
11593 12:34:35.853426 # ok 11 FPSIMD-5-0
11594 12:34:35.853859 # ok 12 FPSIMD-5-1
11595 12:34:35.856563 # ok 13 FPSIMD-6-0
11596 12:34:35.857020 # ok 14 FPSIMD-6-1
11597 12:34:35.860270 # ok 15 FPSIMD-7-0
11598 12:34:35.860702 # ok 16 FPSIMD-7-1
11599 12:34:35.866655 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1271613, signals=9
11600 12:34:35.873708 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=348928, signals=10
11601 12:34:35.883419 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=358912, signals=10
11602 12:34:35.889845 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=916422, signals=10
11603 12:34:35.896446 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=463534, signals=10
11604 12:34:35.903204 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=361711, signals=9
11605 12:34:35.909554 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=371003, signals=10
11606 12:34:35.916794 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=489088, signals=10
11607 12:34:35.926289 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=982065, signals=10
11608 12:34:35.929567 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11609 12:34:35.932910 ok 29 selftests: arm64: fp-stress
11610 12:34:35.936192 # selftests: arm64: sve-ptrace
11611 12:34:35.936623 # TAP version 13
11612 12:34:35.939486 # 1..4104
11613 12:34:35.939948 # ok 2 # SKIP SVE not available
11614 12:34:35.946331 # # Planned tests != run tests (4104 != 1)
11615 12:34:35.949610 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11616 12:34:35.952853 ok 30 selftests: arm64: sve-ptrace # SKIP
11617 12:34:35.956511 # selftests: arm64: sve-probe-vls
11618 12:34:35.959644 # TAP version 13
11619 12:34:35.960072 # 1..2
11620 12:34:35.963115 # ok 2 # SKIP SVE not available
11621 12:34:35.966390 # # Planned tests != run tests (2 != 1)
11622 12:34:35.969573 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11623 12:34:35.975748 ok 31 selftests: arm64: sve-probe-vls # SKIP
11624 12:34:35.976327 # selftests: arm64: vec-syscfg
11625 12:34:35.979054 # TAP version 13
11626 12:34:35.979669 # 1..20
11627 12:34:35.982838 # ok 1 # SKIP SVE not supported
11628 12:34:35.986155 # ok 2 # SKIP SVE not supported
11629 12:34:35.989414 # ok 3 # SKIP SVE not supported
11630 12:34:35.992639 # ok 4 # SKIP SVE not supported
11631 12:34:35.993154 # ok 5 # SKIP SVE not supported
11632 12:34:35.995813 # ok 6 # SKIP SVE not supported
11633 12:34:35.999101 # ok 7 # SKIP SVE not supported
11634 12:34:36.002628 # ok 8 # SKIP SVE not supported
11635 12:34:36.005783 # ok 9 # SKIP SVE not supported
11636 12:34:36.008855 # ok 10 # SKIP SVE not supported
11637 12:34:36.012459 # ok 11 # SKIP SME not supported
11638 12:34:36.015634 # ok 12 # SKIP SME not supported
11639 12:34:36.016106 # ok 13 # SKIP SME not supported
11640 12:34:36.018942 # ok 14 # SKIP SME not supported
11641 12:34:36.021979 # ok 15 # SKIP SME not supported
11642 12:34:36.026016 # ok 16 # SKIP SME not supported
11643 12:34:36.029210 # ok 17 # SKIP SME not supported
11644 12:34:36.032355 # ok 18 # SKIP SME not supported
11645 12:34:36.035663 # ok 19 # SKIP SME not supported
11646 12:34:36.038930 # ok 20 # SKIP SME not supported
11647 12:34:36.042193 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11648 12:34:36.045366 ok 32 selftests: arm64: vec-syscfg
11649 12:34:36.048582 # selftests: arm64: za-fork
11650 12:34:36.049012 # TAP version 13
11651 12:34:36.051859 # 1..1
11652 12:34:36.052289 # # PID: 1221
11653 12:34:36.055087 # # SME support not present
11654 12:34:36.055559 # ok 0 skipped
11655 12:34:36.062056 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11656 12:34:36.065226 ok 33 selftests: arm64: za-fork
11657 12:34:36.065662 # selftests: arm64: za-ptrace
11658 12:34:36.068601 # TAP version 13
11659 12:34:36.069031 # 1..1
11660 12:34:36.071581 # ok 2 # SKIP SME not available
11661 12:34:36.075070 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11662 12:34:36.081537 ok 34 selftests: arm64: za-ptrace # SKIP
11663 12:34:36.085104 # selftests: arm64: check_buffer_fill
11664 12:34:36.115021 # # SKIP: MTE features unavailable
11665 12:34:36.121788 ok 35 selftests: arm64: check_buffer_fill # SKIP
11666 12:34:36.135862 # selftests: arm64: check_child_memory
11667 12:34:36.184053 # # SKIP: MTE features unavailable
11668 12:34:36.190661 ok 36 selftests: arm64: check_child_memory # SKIP
11669 12:34:36.204158 # selftests: arm64: check_gcr_el1_cswitch
11670 12:34:36.254853 # # SKIP: MTE features unavailable
11671 12:34:36.261399 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11672 12:34:36.276216 # selftests: arm64: check_ksm_options
11673 12:34:36.326784 # # SKIP: MTE features unavailable
11674 12:34:36.333624 ok 38 selftests: arm64: check_ksm_options # SKIP
11675 12:34:36.350517 # selftests: arm64: check_mmap_options
11676 12:34:36.402243 # # SKIP: MTE features unavailable
11677 12:34:36.409305 ok 39 selftests: arm64: check_mmap_options # SKIP
11678 12:34:36.420752 # selftests: arm64: check_prctl
11679 12:34:36.470881 # TAP version 13
11680 12:34:36.470997 # 1..5
11681 12:34:36.474209 # ok 1 check_basic_read
11682 12:34:36.474294 # ok 2 NONE
11683 12:34:36.477541 # ok 3 # SKIP SYNC
11684 12:34:36.477625 # ok 4 # SKIP ASYNC
11685 12:34:36.480883 # ok 5 # SKIP SYNC+ASYNC
11686 12:34:36.484137 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11687 12:34:36.487236 ok 40 selftests: arm64: check_prctl
11688 12:34:36.493476 # selftests: arm64: check_tags_inclusion
11689 12:34:36.540537 # # SKIP: MTE features unavailable
11690 12:34:36.547505 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11691 12:34:36.560291 # selftests: arm64: check_user_mem
11692 12:34:36.614027 # # SKIP: MTE features unavailable
11693 12:34:36.620143 ok 42 selftests: arm64: check_user_mem # SKIP
11694 12:34:36.634809 # selftests: arm64: btitest
11695 12:34:36.694763 # TAP version 13
11696 12:34:36.695292 # 1..18
11697 12:34:36.698364 # # HWCAP_PACA not present
11698 12:34:36.701788 # # HWCAP2_BTI not present
11699 12:34:36.702271 # # Test binary built for BTI
11700 12:34:36.707979 # ok 1 nohint_func/call_using_br_x0 # SKIP
11701 12:34:36.711333 # ok 1 nohint_func/call_using_br_x16 # SKIP
11702 12:34:36.714401 # ok 1 nohint_func/call_using_blr # SKIP
11703 12:34:36.718423 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11704 12:34:36.721632 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11705 12:34:36.725013 # ok 1 bti_none_func/call_using_blr # SKIP
11706 12:34:36.731142 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11707 12:34:36.734795 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11708 12:34:36.738353 # ok 1 bti_c_func/call_using_blr # SKIP
11709 12:34:36.741348 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11710 12:34:36.744936 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11711 12:34:36.747787 # ok 1 bti_j_func/call_using_blr # SKIP
11712 12:34:36.751719 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11713 12:34:36.754804 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11714 12:34:36.761051 # ok 1 bti_jc_func/call_using_blr # SKIP
11715 12:34:36.764807 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11716 12:34:36.767518 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11717 12:34:36.771333 # ok 1 paciasp_func/call_using_blr # SKIP
11718 12:34:36.777890 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11719 12:34:36.781401 # # WARNING - EXPECTED TEST COUNT WRONG
11720 12:34:36.784394 ok 43 selftests: arm64: btitest
11721 12:34:36.784828 # selftests: arm64: nobtitest
11722 12:34:36.787535 # TAP version 13
11723 12:34:36.787964 # 1..18
11724 12:34:36.790764 # # HWCAP_PACA not present
11725 12:34:36.794137 # # HWCAP2_BTI not present
11726 12:34:36.794564 # # Test binary not built for BTI
11727 12:34:36.800549 # ok 1 nohint_func/call_using_br_x0 # SKIP
11728 12:34:36.803794 # ok 1 nohint_func/call_using_br_x16 # SKIP
11729 12:34:36.807766 # ok 1 nohint_func/call_using_blr # SKIP
11730 12:34:36.810798 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11731 12:34:36.813719 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11732 12:34:36.821139 # ok 1 bti_none_func/call_using_blr # SKIP
11733 12:34:36.824180 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11734 12:34:36.827455 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11735 12:34:36.830609 # ok 1 bti_c_func/call_using_blr # SKIP
11736 12:34:36.833813 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11737 12:34:36.837042 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11738 12:34:36.840504 # ok 1 bti_j_func/call_using_blr # SKIP
11739 12:34:36.843992 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11740 12:34:36.850472 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11741 12:34:36.853536 # ok 1 bti_jc_func/call_using_blr # SKIP
11742 12:34:36.857144 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11743 12:34:36.860196 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11744 12:34:36.863241 # ok 1 paciasp_func/call_using_blr # SKIP
11745 12:34:36.870534 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11746 12:34:36.873865 # # WARNING - EXPECTED TEST COUNT WRONG
11747 12:34:36.876997 ok 44 selftests: arm64: nobtitest
11748 12:34:36.877562 # selftests: arm64: hwcap
11749 12:34:36.880334 # TAP version 13
11750 12:34:36.880844 # 1..28
11751 12:34:36.883630 # ok 1 cpuinfo_match_RNG
11752 12:34:36.886816 # # SIGILL reported for RNG
11753 12:34:36.887246 # ok 2 # SKIP sigill_RNG
11754 12:34:36.890075 # ok 3 cpuinfo_match_SME
11755 12:34:36.893253 # ok 4 sigill_SME
11756 12:34:36.893837 # ok 5 cpuinfo_match_SVE
11757 12:34:36.896430 # ok 6 sigill_SVE
11758 12:34:36.897010 # ok 7 cpuinfo_match_SVE 2
11759 12:34:36.899633 # # SIGILL reported for SVE 2
11760 12:34:36.902960 # ok 8 # SKIP sigill_SVE 2
11761 12:34:36.906848 # ok 9 cpuinfo_match_SVE AES
11762 12:34:36.910141 # # SIGILL reported for SVE AES
11763 12:34:36.910601 # ok 10 # SKIP sigill_SVE AES
11764 12:34:36.913221 # ok 11 cpuinfo_match_SVE2 PMULL
11765 12:34:36.916451 # # SIGILL reported for SVE2 PMULL
11766 12:34:36.919801 # ok 12 # SKIP sigill_SVE2 PMULL
11767 12:34:36.923204 # ok 13 cpuinfo_match_SVE2 BITPERM
11768 12:34:36.926332 # # SIGILL reported for SVE2 BITPERM
11769 12:34:36.929577 # ok 14 # SKIP sigill_SVE2 BITPERM
11770 12:34:36.932741 # ok 15 cpuinfo_match_SVE2 SHA3
11771 12:34:36.936024 # # SIGILL reported for SVE2 SHA3
11772 12:34:36.939131 # ok 16 # SKIP sigill_SVE2 SHA3
11773 12:34:36.943061 # ok 17 cpuinfo_match_SVE2 SM4
11774 12:34:36.943660 # # SIGILL reported for SVE2 SM4
11775 12:34:36.946248 # ok 18 # SKIP sigill_SVE2 SM4
11776 12:34:36.949421 # ok 19 cpuinfo_match_SVE2 I8MM
11777 12:34:36.952388 # # SIGILL reported for SVE2 I8MM
11778 12:34:36.956076 # ok 20 # SKIP sigill_SVE2 I8MM
11779 12:34:36.959153 # ok 21 cpuinfo_match_SVE2 F32MM
11780 12:34:36.962779 # # SIGILL reported for SVE2 F32MM
11781 12:34:36.965792 # ok 22 # SKIP sigill_SVE2 F32MM
11782 12:34:36.969470 # ok 23 cpuinfo_match_SVE2 F64MM
11783 12:34:36.972979 # # SIGILL reported for SVE2 F64MM
11784 12:34:36.973406 # ok 24 # SKIP sigill_SVE2 F64MM
11785 12:34:36.976041 # ok 25 cpuinfo_match_SVE2 BF16
11786 12:34:36.979387 # # SIGILL reported for SVE2 BF16
11787 12:34:36.982531 # ok 26 # SKIP sigill_SVE2 BF16
11788 12:34:36.985785 # ok 27 cpuinfo_match_SVE2 EBF16
11789 12:34:36.989066 # ok 28 # SKIP sigill_SVE2 EBF16
11790 12:34:36.992391 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11791 12:34:36.995626 ok 45 selftests: arm64: hwcap
11792 12:34:36.998852 # selftests: arm64: ptrace
11793 12:34:36.999282 # TAP version 13
11794 12:34:37.002325 # 1..7
11795 12:34:37.005589 # # Parent is 1450, child is 1451
11796 12:34:37.006020 # ok 1 read_tpidr_one
11797 12:34:37.008923 # ok 2 write_tpidr_one
11798 12:34:37.009352 # ok 3 verify_tpidr_one
11799 12:34:37.012189 # ok 4 count_tpidrs
11800 12:34:37.015555 # ok 5 tpidr2_write
11801 12:34:37.015988 # ok 6 tpidr2_read
11802 12:34:37.018705 # ok 7 write_tpidr_only
11803 12:34:37.022262 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11804 12:34:37.025487 ok 46 selftests: arm64: ptrace
11805 12:34:37.028649 # selftests: arm64: syscall-abi
11806 12:34:37.029196 # TAP version 13
11807 12:34:37.031958 # 1..2
11808 12:34:37.032392 # ok 1 getpid() FPSIMD
11809 12:34:37.035179 # ok 2 sched_yield() FPSIMD
11810 12:34:37.041913 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11811 12:34:37.044923 ok 47 selftests: arm64: syscall-abi
11812 12:34:37.045379 # selftests: arm64: tpidr2
11813 12:34:37.074211 # TAP version 13
11814 12:34:37.074644 # 1..5
11815 12:34:37.077475 # # PID: 1485
11816 12:34:37.077909 # # SME support not present
11817 12:34:37.080804 # ok 0 skipped, TPIDR2 not supported
11818 12:34:37.083846 # ok 1 skipped, TPIDR2 not supported
11819 12:34:37.087210 # ok 2 skipped, TPIDR2 not supported
11820 12:34:37.090945 # ok 3 skipped, TPIDR2 not supported
11821 12:34:37.094040 # ok 4 skipped, TPIDR2 not supported
11822 12:34:37.100634 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11823 12:34:37.103785 ok 48 selftests: arm64: tpidr2
11824 12:34:37.636228 arm64_tags_test pass
11825 12:34:37.639424 arm64_run_tags_test_sh pass
11826 12:34:37.642656 arm64_fake_sigreturn_bad_magic pass
11827 12:34:37.646331 arm64_fake_sigreturn_bad_size pass
11828 12:34:37.649748 arm64_fake_sigreturn_bad_size_for_magic0 pass
11829 12:34:37.652995 arm64_fake_sigreturn_duplicated_fpsimd pass
11830 12:34:37.656219 arm64_fake_sigreturn_misaligned_sp pass
11831 12:34:37.659464 arm64_fake_sigreturn_missing_fpsimd pass
11832 12:34:37.662513 arm64_fake_sigreturn_sme_change_vl skip
11833 12:34:37.666315 arm64_fake_sigreturn_sve_change_vl skip
11834 12:34:37.672941 arm64_mangle_pstate_invalid_compat_toggle pass
11835 12:34:37.676178 arm64_mangle_pstate_invalid_daif_bits pass
11836 12:34:37.679282 arm64_mangle_pstate_invalid_mode_el1h pass
11837 12:34:37.682625 arm64_mangle_pstate_invalid_mode_el1t pass
11838 12:34:37.685794 arm64_mangle_pstate_invalid_mode_el2h pass
11839 12:34:37.692280 arm64_mangle_pstate_invalid_mode_el2t pass
11840 12:34:37.695525 arm64_mangle_pstate_invalid_mode_el3h pass
11841 12:34:37.698753 arm64_mangle_pstate_invalid_mode_el3t pass
11842 12:34:37.702592 arm64_sme_trap_no_sm skip
11843 12:34:37.702676 arm64_sme_trap_non_streaming skip
11844 12:34:37.705779 arm64_sme_trap_za pass
11845 12:34:37.709021 arm64_sme_vl skip
11846 12:34:37.709104 arm64_ssve_regs skip
11847 12:34:37.712027 arm64_sve_regs skip
11848 12:34:37.712110 arm64_sve_vl skip
11849 12:34:37.715759 arm64_za_no_regs skip
11850 12:34:37.715897 arm64_za_regs skip
11851 12:34:37.718692 arm64_pac_PAUTH_not_enabled skip
11852 12:34:37.723417 arm64_pac_PAUTH_not_enabled skip
11853 12:34:37.725880 arm64_pac_Generic_PAUTH_not_enabled skip
11854 12:34:37.729050 arm64_pac_PAUTH_not_enabled skip
11855 12:34:37.732355 arm64_pac_PAUTH_not_enabled skip
11856 12:34:37.735753 arm64_pac_PAUTH_not_enabled skip
11857 12:34:37.739428 arm64_pac_Generic_PAUTH_not_enabled skip
11858 12:34:37.739882 arm64_pac pass
11859 12:34:37.742694 arm64_fp-stress_FPSIMD-0-0 pass
11860 12:34:37.745882 arm64_fp-stress_FPSIMD-0-1 pass
11861 12:34:37.748976 arm64_fp-stress_FPSIMD-1-0 pass
11862 12:34:37.752169 arm64_fp-stress_FPSIMD-1-1 pass
11863 12:34:37.755298 arm64_fp-stress_FPSIMD-2-0 pass
11864 12:34:37.759156 arm64_fp-stress_FPSIMD-2-1 pass
11865 12:34:37.759704 arm64_fp-stress_FPSIMD-3-0 pass
11866 12:34:37.762374 arm64_fp-stress_FPSIMD-3-1 pass
11867 12:34:37.765548 arm64_fp-stress_FPSIMD-4-0 pass
11868 12:34:37.768871 arm64_fp-stress_FPSIMD-4-1 pass
11869 12:34:37.771762 arm64_fp-stress_FPSIMD-5-0 pass
11870 12:34:37.775861 arm64_fp-stress_FPSIMD-5-1 pass
11871 12:34:37.778453 arm64_fp-stress_FPSIMD-6-0 pass
11872 12:34:37.782186 arm64_fp-stress_FPSIMD-6-1 pass
11873 12:34:37.782611 arm64_fp-stress_FPSIMD-7-0 pass
11874 12:34:37.785326 arm64_fp-stress_FPSIMD-7-1 pass
11875 12:34:37.788475 arm64_fp-stress pass
11876 12:34:37.791652 arm64_sve-ptrace_SVE_not_available skip
11877 12:34:37.794838 arm64_sve-ptrace skip
11878 12:34:37.798695 arm64_sve-probe-vls_SVE_not_available skip
11879 12:34:37.799232 arm64_sve-probe-vls skip
11880 12:34:37.802231 arm64_vec-syscfg_SVE_not_supported skip
11881 12:34:37.808725 arm64_vec-syscfg_SVE_not_supported skip
11882 12:34:37.812054 arm64_vec-syscfg_SVE_not_supported skip
11883 12:34:37.814996 arm64_vec-syscfg_SVE_not_supported skip
11884 12:34:37.818725 arm64_vec-syscfg_SVE_not_supported skip
11885 12:34:37.821611 arm64_vec-syscfg_SVE_not_supported skip
11886 12:34:37.825320 arm64_vec-syscfg_SVE_not_supported skip
11887 12:34:37.828405 arm64_vec-syscfg_SVE_not_supported skip
11888 12:34:37.832045 arm64_vec-syscfg_SVE_not_supported skip
11889 12:34:37.834849 arm64_vec-syscfg_SVE_not_supported skip
11890 12:34:37.838415 arm64_vec-syscfg_SME_not_supported skip
11891 12:34:37.841746 arm64_vec-syscfg_SME_not_supported skip
11892 12:34:37.845066 arm64_vec-syscfg_SME_not_supported skip
11893 12:34:37.848330 arm64_vec-syscfg_SME_not_supported skip
11894 12:34:37.854804 arm64_vec-syscfg_SME_not_supported skip
11895 12:34:37.857923 arm64_vec-syscfg_SME_not_supported skip
11896 12:34:37.861350 arm64_vec-syscfg_SME_not_supported skip
11897 12:34:37.864435 arm64_vec-syscfg_SME_not_supported skip
11898 12:34:37.867868 arm64_vec-syscfg_SME_not_supported skip
11899 12:34:37.871468 arm64_vec-syscfg_SME_not_supported skip
11900 12:34:37.874481 arm64_vec-syscfg pass
11901 12:34:37.874997 arm64_za-fork_skipped pass
11902 12:34:37.878241 arm64_za-fork pass
11903 12:34:37.881654 arm64_za-ptrace_SME_not_available skip
11904 12:34:37.882082 arm64_za-ptrace skip
11905 12:34:37.884351 arm64_check_buffer_fill skip
11906 12:34:37.888004 arm64_check_child_memory skip
11907 12:34:37.891591 arm64_check_gcr_el1_cswitch skip
11908 12:34:37.894957 arm64_check_ksm_options skip
11909 12:34:37.898231 arm64_check_mmap_options skip
11910 12:34:37.901617 arm64_check_prctl_check_basic_read pass
11911 12:34:37.902187 arm64_check_prctl_NONE pass
11912 12:34:37.904706 arm64_check_prctl_SYNC skip
11913 12:34:37.907765 arm64_check_prctl_ASYNC skip
11914 12:34:37.911122 arm64_check_prctl_SYNC_ASYNC skip
11915 12:34:37.911595 arm64_check_prctl pass
11916 12:34:37.914291 arm64_check_tags_inclusion skip
11917 12:34:37.917501 arm64_check_user_mem skip
11918 12:34:37.921102 arm64_btitest_nohint_func_call_using_br_x0 skip
11919 12:34:37.927206 arm64_btitest_nohint_func_call_using_br_x16 skip
11920 12:34:37.930681 arm64_btitest_nohint_func_call_using_blr skip
11921 12:34:37.934145 arm64_btitest_bti_none_func_call_using_br_x0 skip
11922 12:34:37.940715 arm64_btitest_bti_none_func_call_using_br_x16 skip
11923 12:34:37.943786 arm64_btitest_bti_none_func_call_using_blr skip
11924 12:34:37.947454 arm64_btitest_bti_c_func_call_using_br_x0 skip
11925 12:34:37.950479 arm64_btitest_bti_c_func_call_using_br_x16 skip
11926 12:34:37.957038 arm64_btitest_bti_c_func_call_using_blr skip
11927 12:34:37.960752 arm64_btitest_bti_j_func_call_using_br_x0 skip
11928 12:34:37.963477 arm64_btitest_bti_j_func_call_using_br_x16 skip
11929 12:34:37.966840 arm64_btitest_bti_j_func_call_using_blr skip
11930 12:34:37.973314 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11931 12:34:37.976425 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11932 12:34:37.979665 arm64_btitest_bti_jc_func_call_using_blr skip
11933 12:34:37.986326 arm64_btitest_paciasp_func_call_using_br_x0 skip
11934 12:34:37.989637 arm64_btitest_paciasp_func_call_using_br_x16 skip
11935 12:34:37.992804 arm64_btitest_paciasp_func_call_using_blr skip
11936 12:34:37.996018 arm64_btitest pass
11937 12:34:37.999876 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11938 12:34:38.003181 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11939 12:34:38.009653 arm64_nobtitest_nohint_func_call_using_blr skip
11940 12:34:38.012880 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11941 12:34:38.016251 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11942 12:34:38.022766 arm64_nobtitest_bti_none_func_call_using_blr skip
11943 12:34:38.025948 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11944 12:34:38.029324 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11945 12:34:38.036118 arm64_nobtitest_bti_c_func_call_using_blr skip
11946 12:34:38.039628 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11947 12:34:38.042549 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11948 12:34:38.049217 arm64_nobtitest_bti_j_func_call_using_blr skip
11949 12:34:38.052926 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11950 12:34:38.055790 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11951 12:34:38.062373 arm64_nobtitest_bti_jc_func_call_using_blr skip
11952 12:34:38.066312 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11953 12:34:38.069288 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11954 12:34:38.075825 arm64_nobtitest_paciasp_func_call_using_blr skip
11955 12:34:38.075909 arm64_nobtitest pass
11956 12:34:38.079563 arm64_hwcap_cpuinfo_match_RNG pass
11957 12:34:38.082794 arm64_hwcap_sigill_RNG skip
11958 12:34:38.086158 arm64_hwcap_cpuinfo_match_SME pass
11959 12:34:38.089126 arm64_hwcap_sigill_SME pass
11960 12:34:38.092225 arm64_hwcap_cpuinfo_match_SVE pass
11961 12:34:38.092308 arm64_hwcap_sigill_SVE pass
11962 12:34:38.095623 arm64_hwcap_cpuinfo_match_SVE_2 pass
11963 12:34:38.098884 arm64_hwcap_sigill_SVE_2 skip
11964 12:34:38.102157 arm64_hwcap_cpuinfo_match_SVE_AES pass
11965 12:34:38.105461 arm64_hwcap_sigill_SVE_AES skip
11966 12:34:38.109145 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11967 12:34:38.112679 arm64_hwcap_sigill_SVE2_PMULL skip
11968 12:34:38.115880 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11969 12:34:38.119117 arm64_hwcap_sigill_SVE2_BITPERM skip
11970 12:34:38.122280 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11971 12:34:38.125474 arm64_hwcap_sigill_SVE2_SHA3 skip
11972 12:34:38.128733 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11973 12:34:38.132637 arm64_hwcap_sigill_SVE2_SM4 skip
11974 12:34:38.135744 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11975 12:34:38.139059 arm64_hwcap_sigill_SVE2_I8MM skip
11976 12:34:38.142419 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11977 12:34:38.145388 arm64_hwcap_sigill_SVE2_F32MM skip
11978 12:34:38.148932 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11979 12:34:38.151835 arm64_hwcap_sigill_SVE2_F64MM skip
11980 12:34:38.158379 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11981 12:34:38.158462 arm64_hwcap_sigill_SVE2_BF16 skip
11982 12:34:38.164940 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11983 12:34:38.168838 arm64_hwcap_sigill_SVE2_EBF16 skip
11984 12:34:38.168921 arm64_hwcap pass
11985 12:34:38.171765 arm64_ptrace_read_tpidr_one pass
11986 12:34:38.175294 arm64_ptrace_write_tpidr_one pass
11987 12:34:38.178366 arm64_ptrace_verify_tpidr_one pass
11988 12:34:38.181508 arm64_ptrace_count_tpidrs pass
11989 12:34:38.181591 arm64_ptrace_tpidr2_write pass
11990 12:34:38.184784 arm64_ptrace_tpidr2_read pass
11991 12:34:38.188583 arm64_ptrace_write_tpidr_only pass
11992 12:34:38.191777 arm64_ptrace pass
11993 12:34:38.194766 arm64_syscall-abi_getpid_FPSIMD pass
11994 12:34:38.198105 arm64_syscall-abi_sched_yield_FPSIMD pass
11995 12:34:38.198188 arm64_syscall-abi pass
11996 12:34:38.205233 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11997 12:34:38.207860 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11998 12:34:38.211566 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11999 12:34:38.218278 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12000 12:34:38.221287 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12001 12:34:38.221365 arm64_tpidr2 pass
12002 12:34:38.227815 + ../../utils/send-to-lava.sh ./output/result.txt
12003 12:34:38.231145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
12004 12:34:38.231422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
12006 12:34:38.237606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12007 12:34:38.237884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12009 12:34:38.244671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12010 12:34:38.244918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12012 12:34:38.251269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12013 12:34:38.251573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12015 12:34:38.294041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12016 12:34:38.294333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12018 12:34:38.356873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12019 12:34:38.357191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12021 12:34:38.414019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12022 12:34:38.414327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12024 12:34:38.480588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12025 12:34:38.481481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12027 12:34:38.541415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12028 12:34:38.542297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12030 12:34:38.616699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12031 12:34:38.617632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12033 12:34:38.674692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12034 12:34:38.675601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12036 12:34:38.738455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12037 12:34:38.739459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12039 12:34:38.805674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12040 12:34:38.806562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12042 12:34:38.867992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12043 12:34:38.868889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12045 12:34:38.939788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12046 12:34:38.940706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12048 12:34:38.999919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12049 12:34:39.000655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12051 12:34:39.064551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12052 12:34:39.065454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12054 12:34:39.129587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12055 12:34:39.129878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12057 12:34:39.182980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12058 12:34:39.183283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12060 12:34:39.241083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12062 12:34:39.243822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12063 12:34:39.301698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12064 12:34:39.302464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12066 12:34:39.370752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12067 12:34:39.371118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12069 12:34:39.422415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12070 12:34:39.423315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12072 12:34:39.482759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12073 12:34:39.483602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12075 12:34:39.551845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12076 12:34:39.552805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12078 12:34:39.616272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12079 12:34:39.616562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12081 12:34:39.670992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12082 12:34:39.671875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12084 12:34:39.727583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12086 12:34:39.730565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12087 12:34:39.791264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12089 12:34:39.793836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12090 12:34:39.860423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12091 12:34:39.861423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12093 12:34:39.922518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12095 12:34:39.925529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12096 12:34:39.983475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12098 12:34:39.986225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12099 12:34:40.045896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12101 12:34:40.048761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12102 12:34:40.101548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12103 12:34:40.102319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12105 12:34:40.157348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12106 12:34:40.157935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12108 12:34:40.224541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12109 12:34:40.224860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12111 12:34:40.287842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12112 12:34:40.288166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12114 12:34:40.347912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12115 12:34:40.348219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12117 12:34:40.409143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12118 12:34:40.409431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12120 12:34:40.466560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12121 12:34:40.466855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12123 12:34:40.530279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12124 12:34:40.530560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12126 12:34:40.584985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12127 12:34:40.585266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12129 12:34:40.640537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12130 12:34:40.640803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12132 12:34:40.698013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12133 12:34:40.698277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12135 12:34:40.762582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12136 12:34:40.763286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12138 12:34:40.827200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12139 12:34:40.827934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12141 12:34:40.888656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12142 12:34:40.889522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12144 12:34:40.945726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12145 12:34:40.946440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12147 12:34:41.007070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12148 12:34:41.007859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12150 12:34:41.068428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12151 12:34:41.069142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12153 12:34:41.134554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12154 12:34:41.134879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12156 12:34:41.196535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12157 12:34:41.196855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12159 12:34:41.260308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12160 12:34:41.260663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12162 12:34:41.313851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12163 12:34:41.314130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12165 12:34:41.367987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12166 12:34:41.368280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12168 12:34:41.416592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12169 12:34:41.416860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12171 12:34:41.466528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12172 12:34:41.466806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12174 12:34:41.514158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12175 12:34:41.514449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12177 12:34:41.560167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12178 12:34:41.560439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12180 12:34:41.611254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12181 12:34:41.611512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12183 12:34:41.663463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12184 12:34:41.663733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12186 12:34:41.718234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12187 12:34:41.719007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12189 12:34:41.774586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12190 12:34:41.775283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12192 12:34:41.829616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12193 12:34:41.829889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12195 12:34:41.887462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12196 12:34:41.888315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12198 12:34:41.946538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12199 12:34:41.947509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12201 12:34:42.004104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12202 12:34:42.004868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12204 12:34:42.058362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12205 12:34:42.058938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12207 12:34:42.112231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12208 12:34:42.112713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12210 12:34:42.169311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12211 12:34:42.170061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12213 12:34:42.230069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12214 12:34:42.230371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12216 12:34:42.287191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12217 12:34:42.287977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12219 12:34:42.341204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12220 12:34:42.341486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12222 12:34:42.389566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12223 12:34:42.389856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12225 12:34:42.452985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12226 12:34:42.453331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12228 12:34:42.510245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12229 12:34:42.510558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12231 12:34:42.573618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12232 12:34:42.573924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12234 12:34:42.634414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12235 12:34:42.634691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12237 12:34:42.692105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12238 12:34:42.692383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12240 12:34:42.749885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12241 12:34:42.750165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12243 12:34:42.803879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12244 12:34:42.804168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12246 12:34:42.860161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12247 12:34:42.860432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12249 12:34:42.915508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12250 12:34:42.915771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12252 12:34:42.971956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12254 12:34:42.975040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12255 12:34:43.035120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12256 12:34:43.035387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12258 12:34:43.087280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12259 12:34:43.087662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12261 12:34:43.143429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12262 12:34:43.143757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12264 12:34:43.191148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12265 12:34:43.191449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12267 12:34:43.241697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12268 12:34:43.242010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12270 12:34:43.287434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12271 12:34:43.287759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12273 12:34:43.338012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12275 12:34:43.340866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12276 12:34:43.393040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12277 12:34:43.393362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12279 12:34:43.442042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12280 12:34:43.442369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12282 12:34:43.501918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12283 12:34:43.502805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12285 12:34:43.566482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12286 12:34:43.567215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12288 12:34:43.622946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12289 12:34:43.623718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12291 12:34:43.681292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12292 12:34:43.681652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12294 12:34:43.737436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12295 12:34:43.737705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12297 12:34:43.785075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12298 12:34:43.785342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12300 12:34:43.834640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12301 12:34:43.834899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12303 12:34:43.900743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12304 12:34:43.901024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12306 12:34:43.957778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12307 12:34:43.958135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12309 12:34:44.019158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12310 12:34:44.019453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12312 12:34:44.070779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12313 12:34:44.071124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12315 12:34:44.118622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12316 12:34:44.118901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12318 12:34:44.163615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12319 12:34:44.163912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12321 12:34:44.219028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12322 12:34:44.219303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12324 12:34:44.277965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12325 12:34:44.278254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12327 12:34:44.327582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12328 12:34:44.327858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12330 12:34:44.388582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12331 12:34:44.389429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12333 12:34:44.452112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12334 12:34:44.452879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12336 12:34:44.527815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12337 12:34:44.528515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12339 12:34:44.581979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12340 12:34:44.582246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12342 12:34:44.636220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12343 12:34:44.636490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12345 12:34:44.687971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12346 12:34:44.688242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12348 12:34:44.742662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12349 12:34:44.742929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12351 12:34:44.799290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12352 12:34:44.799594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12354 12:34:44.862150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12355 12:34:44.862851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12357 12:34:44.929665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12358 12:34:44.930370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12360 12:34:44.990875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12361 12:34:44.991808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12363 12:34:45.059678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12364 12:34:45.060440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12366 12:34:45.120202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12367 12:34:45.120916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12369 12:34:45.182412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12370 12:34:45.183135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12372 12:34:45.241931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12373 12:34:45.242635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12375 12:34:45.306542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12376 12:34:45.306849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12378 12:34:45.365110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12379 12:34:45.365410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12381 12:34:45.436507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12382 12:34:45.436825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12384 12:34:45.496223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12385 12:34:45.496528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12387 12:34:45.555769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12388 12:34:45.556086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12390 12:34:45.613533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12391 12:34:45.613839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12393 12:34:45.664189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12394 12:34:45.664488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12396 12:34:45.723267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12397 12:34:45.723587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12399 12:34:45.776232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12400 12:34:45.776717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12402 12:34:45.835780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12403 12:34:45.836620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12405 12:34:45.899879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12406 12:34:45.900618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12408 12:34:45.960480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12409 12:34:45.961439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12411 12:34:46.037495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12412 12:34:46.038194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12414 12:34:46.093042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12415 12:34:46.093736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12417 12:34:46.161795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12418 12:34:46.162685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12420 12:34:46.217022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12421 12:34:46.217292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12423 12:34:46.279939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12424 12:34:46.280218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12426 12:34:46.332573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12427 12:34:46.332831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12429 12:34:46.393338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12430 12:34:46.393615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12432 12:34:46.453671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12433 12:34:46.453995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12435 12:34:46.513155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12436 12:34:46.513441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12438 12:34:46.569440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12439 12:34:46.569729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12441 12:34:46.625837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12442 12:34:46.626114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12444 12:34:46.672927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12446 12:34:46.676076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12447 12:34:46.728178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12448 12:34:46.728447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12450 12:34:46.792263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12452 12:34:46.795213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12453 12:34:46.863996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12454 12:34:46.864323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12456 12:34:46.922314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12458 12:34:46.925436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12459 12:34:46.994911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12460 12:34:46.995217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12462 12:34:47.052853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12463 12:34:47.053587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12465 12:34:47.117884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12466 12:34:47.118734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12468 12:34:47.172671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12469 12:34:47.173494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12471 12:34:47.235262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12472 12:34:47.235563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12474 12:34:47.284700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12476 12:34:47.287792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12477 12:34:47.342536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12478 12:34:47.342803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12480 12:34:47.394719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12481 12:34:47.395482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12483 12:34:47.456930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12484 12:34:47.457682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12486 12:34:47.512852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12488 12:34:47.515781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12489 12:34:47.582937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12491 12:34:47.586193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12492 12:34:47.646387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12493 12:34:47.646716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12495 12:34:47.709354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12496 12:34:47.709678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12498 12:34:47.762061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12499 12:34:47.762338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12501 12:34:47.813909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12502 12:34:47.814172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12504 12:34:47.870221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12505 12:34:47.870496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12507 12:34:47.928693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12508 12:34:47.929008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12510 12:34:47.983704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12511 12:34:47.984007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12513 12:34:48.043857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12514 12:34:48.044762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12516 12:34:48.104138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12517 12:34:48.104942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12519 12:34:48.170339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12520 12:34:48.170648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12522 12:34:48.231723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12523 12:34:48.232041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12525 12:34:48.284237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12526 12:34:48.284556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12528 12:34:48.330977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12529 12:34:48.331244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12531 12:34:48.389350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12532 12:34:48.389649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12534 12:34:48.442561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12535 12:34:48.442655 + set +x
12536 12:34:48.442892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12538 12:34:48.449338 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 10605810_1.6.2.3.5>
12539 12:34:48.449592 Received signal: <ENDRUN> 1_kselftest-arm64 10605810_1.6.2.3.5
12540 12:34:48.449668 Ending use of test pattern.
12541 12:34:48.449733 Ending test lava.1_kselftest-arm64 (10605810_1.6.2.3.5), duration 34.22
12543 12:34:48.452682 <LAVA_TEST_RUNNER EXIT>
12544 12:34:48.452934 ok: lava_test_shell seems to have completed
12545 12:34:48.453897 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
12546 12:34:48.454042 end: 3.1 lava-test-shell (duration 00:00:35) [common]
12547 12:34:48.454133 end: 3 lava-test-retry (duration 00:00:35) [common]
12548 12:34:48.454220 start: 4 finalize (timeout 00:06:55) [common]
12549 12:34:48.454310 start: 4.1 power-off (timeout 00:00:30) [common]
12550 12:34:48.454462 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
12551 12:34:48.531205 >> Command sent successfully.
12552 12:34:48.534929 Returned 0 in 0 seconds
12553 12:34:48.635424 end: 4.1 power-off (duration 00:00:00) [common]
12555 12:34:48.635777 start: 4.2 read-feedback (timeout 00:06:55) [common]
12556 12:34:48.636037 Listened to connection for namespace 'common' for up to 1s
12557 12:34:49.637132 Finalising connection for namespace 'common'
12558 12:34:49.638074 Disconnecting from shell: Finalise
12559 12:34:49.638735 / #
12560 12:34:49.739892 end: 4.2 read-feedback (duration 00:00:01) [common]
12561 12:34:49.740773 end: 4 finalize (duration 00:00:01) [common]
12562 12:34:49.741650 Cleaning after the job
12563 12:34:49.742328 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/ramdisk
12564 12:34:49.751722 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/kernel
12565 12:34:49.774469 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/dtb
12566 12:34:49.774812 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/nfsrootfs
12567 12:34:49.844393 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605810/tftp-deploy-chfj_5iw/modules
12568 12:34:49.849631 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605810
12569 12:34:50.385016 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605810
12570 12:34:50.385233 Job finished correctly