Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 131
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 27
1 12:25:17.772675 lava-dispatcher, installed at version: 2023.05.1
2 12:25:17.772894 start: 0 validate
3 12:25:17.773026 Start time: 2023-06-06 12:25:17.773019+00:00 (UTC)
4 12:25:17.773152 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:25:17.773280 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 12:25:18.072598 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:25:18.073355 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:25:39.374883 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:25:39.375529 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:25:39.675930 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:25:39.676946 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1320-gc38e4a9845945%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:25:43.473418 validate duration: 25.70
14 12:25:43.473734 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:25:43.473835 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:25:43.473985 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:25:43.474120 Not decompressing ramdisk as can be used compressed.
18 12:25:43.474213 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/rootfs.cpio.gz
19 12:25:43.474278 saving as /var/lib/lava/dispatcher/tmp/10605776/tftp-deploy-yypd6nms/ramdisk/rootfs.cpio.gz
20 12:25:43.474349 total size: 84903995 (80MB)
21 12:25:43.767930 progress 0% (0MB)
22 12:25:43.795449 progress 5% (4MB)
23 12:25:43.819577 progress 10% (8MB)
24 12:25:43.844294 progress 15% (12MB)
25 12:25:43.877774 progress 20% (16MB)
26 12:25:43.907305 progress 25% (20MB)
27 12:25:43.933092 progress 30% (24MB)
28 12:25:43.964949 progress 35% (28MB)
29 12:25:43.999661 progress 40% (32MB)
30 12:25:44.035540 progress 45% (36MB)
31 12:25:44.063212 progress 50% (40MB)
32 12:25:44.096311 progress 55% (44MB)
33 12:25:44.130107 progress 60% (48MB)
34 12:25:44.161862 progress 65% (52MB)
35 12:25:44.194547 progress 70% (56MB)
36 12:25:44.228990 progress 75% (60MB)
37 12:25:44.262285 progress 80% (64MB)
38 12:25:44.292786 progress 85% (68MB)
39 12:25:44.324855 progress 90% (72MB)
40 12:25:44.357800 progress 95% (76MB)
41 12:25:44.390655 progress 100% (80MB)
42 12:25:44.390877 80MB downloaded in 0.92s (88.35MB/s)
43 12:25:44.391093 end: 1.1.1 http-download (duration 00:00:01) [common]
45 12:25:44.391473 end: 1.1 download-retry (duration 00:00:01) [common]
46 12:25:44.391600 start: 1.2 download-retry (timeout 00:09:59) [common]
47 12:25:44.391727 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 12:25:44.391888 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:25:44.391995 saving as /var/lib/lava/dispatcher/tmp/10605776/tftp-deploy-yypd6nms/kernel/Image
50 12:25:44.392101 total size: 45746688 (43MB)
51 12:25:44.392192 No compression specified
52 12:25:44.393816 progress 0% (0MB)
53 12:25:44.411275 progress 5% (2MB)
54 12:25:44.429606 progress 10% (4MB)
55 12:25:44.446688 progress 15% (6MB)
56 12:25:44.462796 progress 20% (8MB)
57 12:25:44.478022 progress 25% (10MB)
58 12:25:44.496078 progress 30% (13MB)
59 12:25:44.514466 progress 35% (15MB)
60 12:25:44.531247 progress 40% (17MB)
61 12:25:44.549842 progress 45% (19MB)
62 12:25:44.563294 progress 50% (21MB)
63 12:25:44.576672 progress 55% (24MB)
64 12:25:44.590296 progress 60% (26MB)
65 12:25:44.603995 progress 65% (28MB)
66 12:25:44.617820 progress 70% (30MB)
67 12:25:44.632629 progress 75% (32MB)
68 12:25:44.648924 progress 80% (34MB)
69 12:25:44.666894 progress 85% (37MB)
70 12:25:44.680875 progress 90% (39MB)
71 12:25:44.694580 progress 95% (41MB)
72 12:25:44.713274 progress 100% (43MB)
73 12:25:44.713618 43MB downloaded in 0.32s (135.70MB/s)
74 12:25:44.713863 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:25:44.714259 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:25:44.714389 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:25:44.714545 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:25:44.714743 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:25:44.714881 saving as /var/lib/lava/dispatcher/tmp/10605776/tftp-deploy-yypd6nms/dtb/mt8192-asurada-spherion-r0.dtb
81 12:25:44.714977 total size: 46924 (0MB)
82 12:25:44.715069 No compression specified
83 12:25:44.716861 progress 69% (0MB)
84 12:25:44.717309 progress 100% (0MB)
85 12:25:44.717555 0MB downloaded in 0.00s (17.39MB/s)
86 12:25:44.717761 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:25:44.718158 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:25:44.718288 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:25:44.718419 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:25:44.718628 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:25:44.718732 saving as /var/lib/lava/dispatcher/tmp/10605776/tftp-deploy-yypd6nms/modules/modules.tar
93 12:25:44.718863 total size: 8539116 (8MB)
94 12:25:44.718961 Using unxz to decompress xz
95 12:25:44.724259 progress 0% (0MB)
96 12:25:44.756247 progress 5% (0MB)
97 12:25:44.799507 progress 10% (0MB)
98 12:25:44.827712 progress 15% (1MB)
99 12:25:44.864305 progress 20% (1MB)
100 12:25:44.899214 progress 25% (2MB)
101 12:25:44.933838 progress 30% (2MB)
102 12:25:44.970607 progress 35% (2MB)
103 12:25:45.005239 progress 40% (3MB)
104 12:25:45.042206 progress 45% (3MB)
105 12:25:45.078847 progress 50% (4MB)
106 12:25:45.113505 progress 55% (4MB)
107 12:25:45.149528 progress 60% (4MB)
108 12:25:45.185819 progress 65% (5MB)
109 12:25:45.220542 progress 70% (5MB)
110 12:25:45.258745 progress 75% (6MB)
111 12:25:45.304133 progress 80% (6MB)
112 12:25:45.336819 progress 85% (6MB)
113 12:25:45.372894 progress 90% (7MB)
114 12:25:45.408993 progress 95% (7MB)
115 12:25:45.442873 progress 100% (8MB)
116 12:25:45.450217 8MB downloaded in 0.73s (11.14MB/s)
117 12:25:45.450690 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:25:45.451144 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:25:45.451260 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 12:25:45.451399 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 12:25:45.451533 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:25:45.451733 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 12:25:45.452143 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx
125 12:25:45.452353 makedir: /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin
126 12:25:45.452523 makedir: /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/tests
127 12:25:45.452631 makedir: /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/results
128 12:25:45.452774 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-add-keys
129 12:25:45.452977 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-add-sources
130 12:25:45.453221 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-background-process-start
131 12:25:45.453405 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-background-process-stop
132 12:25:45.453620 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-common-functions
133 12:25:45.453807 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-echo-ipv4
134 12:25:45.454030 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-install-packages
135 12:25:45.454231 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-installed-packages
136 12:25:45.454432 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-os-build
137 12:25:45.454627 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-probe-channel
138 12:25:45.454832 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-probe-ip
139 12:25:45.455030 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-target-ip
140 12:25:45.455231 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-target-mac
141 12:25:45.455434 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-target-storage
142 12:25:45.455634 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-test-case
143 12:25:45.455845 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-test-event
144 12:25:45.456047 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-test-feedback
145 12:25:45.456261 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-test-raise
146 12:25:45.456476 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-test-reference
147 12:25:45.456674 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-test-runner
148 12:25:45.456875 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-test-set
149 12:25:45.457066 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-test-shell
150 12:25:45.457265 Updating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-install-packages (oe)
151 12:25:45.457510 Updating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/bin/lava-installed-packages (oe)
152 12:25:45.457718 Creating /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/environment
153 12:25:45.457902 LAVA metadata
154 12:25:45.458018 - LAVA_JOB_ID=10605776
155 12:25:45.458167 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:25:45.458354 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 12:25:45.458496 skipped lava-vland-overlay
158 12:25:45.458638 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:25:45.458779 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 12:25:45.458903 skipped lava-multinode-overlay
161 12:25:45.459020 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:25:45.459163 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 12:25:45.459280 Loading test definitions
164 12:25:45.459441 start: 1.5.2.3.1 git-repo-action (timeout 00:09:58) [common]
165 12:25:45.459558 Using /lava-10605776 at stage 0
166 12:25:45.459726 Fetching tests from https://github.com/kernelci/kernelci-core
167 12:25:45.459872 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/0/tests/0_sleep'
168 12:25:46.232153 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/0/tests/0_sleep
169 12:25:46.233798 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 12:25:46.234682 uuid=10605776_1.5.2.3.1 testdef=None
171 12:25:46.234927 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 12:25:46.235356 start: 1.5.2.3.2 test-overlay (timeout 00:09:57) [common]
174 12:25:46.236302 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 12:25:46.236713 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:57) [common]
177 12:25:46.237868 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 12:25:46.238334 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:57) [common]
180 12:25:46.239642 runner path: /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/0/tests/0_sleep test_uuid 10605776_1.5.2.3.1
181 12:25:46.239846 sleep_params='mem freeze'
182 12:25:46.240085 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 12:25:46.240431 Creating lava-test-runner.conf files
185 12:25:46.240575 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605776/lava-overlay-jdg9vowx/lava-10605776/0 for stage 0
186 12:25:46.240722 - 0_sleep
187 12:25:46.240879 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 12:25:46.241019 start: 1.5.2.4 compress-overlay (timeout 00:09:57) [common]
189 12:25:46.409310 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 12:25:46.409530 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:57) [common]
191 12:25:46.409660 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 12:25:46.409812 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 12:25:46.409945 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
194 12:25:49.451067 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 12:25:49.451479 start: 1.5.4 extract-modules (timeout 00:09:54) [common]
196 12:25:49.451656 extracting modules file /var/lib/lava/dispatcher/tmp/10605776/tftp-deploy-yypd6nms/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605776/extract-overlay-ramdisk-elnbgirx/ramdisk
197 12:25:49.789480 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 12:25:49.789734 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
199 12:25:49.789873 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605776/compress-overlay-w9t5yx_q/overlay-1.5.2.4.tar.gz to ramdisk
200 12:25:49.789977 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605776/compress-overlay-w9t5yx_q/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605776/extract-overlay-ramdisk-elnbgirx/ramdisk
201 12:25:49.927443 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 12:25:49.927661 start: 1.5.6 configure-preseed-file (timeout 00:09:54) [common]
203 12:25:49.927864 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 12:25:49.928027 start: 1.5.7 compress-ramdisk (timeout 00:09:54) [common]
205 12:25:49.928184 Building ramdisk /var/lib/lava/dispatcher/tmp/10605776/extract-overlay-ramdisk-elnbgirx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605776/extract-overlay-ramdisk-elnbgirx/ramdisk
206 12:25:51.862137 >> 561596 blocks
207 12:26:02.181516 rename /var/lib/lava/dispatcher/tmp/10605776/extract-overlay-ramdisk-elnbgirx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605776/tftp-deploy-yypd6nms/ramdisk/ramdisk.cpio.gz
208 12:26:02.181977 end: 1.5.7 compress-ramdisk (duration 00:00:12) [common]
209 12:26:02.182107 start: 1.5.8 prepare-kernel (timeout 00:09:41) [common]
210 12:26:02.182212 start: 1.5.8.1 prepare-fit (timeout 00:09:41) [common]
211 12:26:02.182335 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605776/tftp-deploy-yypd6nms/kernel/Image'
212 12:26:15.571148 Returned 0 in 13 seconds
213 12:26:15.671745 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605776/tftp-deploy-yypd6nms/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605776/tftp-deploy-yypd6nms/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605776/tftp-deploy-yypd6nms/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605776/tftp-deploy-yypd6nms/kernel/image.itb
214 12:26:17.211058 output: FIT description: Kernel Image image with one or more FDT blobs
215 12:26:17.211501 output: Created: Tue Jun 6 13:26:16 2023
216 12:26:17.211625 output: Image 0 (kernel-1)
217 12:26:17.211736 output: Description:
218 12:26:17.211854 output: Created: Tue Jun 6 13:26:16 2023
219 12:26:17.211967 output: Type: Kernel Image
220 12:26:17.212076 output: Compression: lzma compressed
221 12:26:17.212198 output: Data Size: 10086749 Bytes = 9850.34 KiB = 9.62 MiB
222 12:26:17.212297 output: Architecture: AArch64
223 12:26:17.212406 output: OS: Linux
224 12:26:17.212500 output: Load Address: 0x00000000
225 12:26:17.212614 output: Entry Point: 0x00000000
226 12:26:17.212715 output: Hash algo: crc32
227 12:26:17.212828 output: Hash value: a26c3f91
228 12:26:17.212925 output: Image 1 (fdt-1)
229 12:26:17.213017 output: Description: mt8192-asurada-spherion-r0
230 12:26:17.213118 output: Created: Tue Jun 6 13:26:16 2023
231 12:26:17.213232 output: Type: Flat Device Tree
232 12:26:17.213325 output: Compression: uncompressed
233 12:26:17.213426 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
234 12:26:17.213521 output: Architecture: AArch64
235 12:26:17.213621 output: Hash algo: crc32
236 12:26:17.213711 output: Hash value: 1df858fa
237 12:26:17.213799 output: Image 2 (ramdisk-1)
238 12:26:17.213886 output: Description: unavailable
239 12:26:17.213983 output: Created: Tue Jun 6 13:26:16 2023
240 12:26:17.214073 output: Type: RAMDisk Image
241 12:26:17.214176 output: Compression: Unknown Compression
242 12:26:17.214267 output: Data Size: 98134786 Bytes = 95834.75 KiB = 93.59 MiB
243 12:26:17.214375 output: Architecture: AArch64
244 12:26:17.214474 output: OS: Linux
245 12:26:17.214573 output: Load Address: unavailable
246 12:26:17.214678 output: Entry Point: unavailable
247 12:26:17.214771 output: Hash algo: crc32
248 12:26:17.214864 output: Hash value: 80a96f4c
249 12:26:17.214956 output: Default Configuration: 'conf-1'
250 12:26:17.215050 output: Configuration 0 (conf-1)
251 12:26:17.215145 output: Description: mt8192-asurada-spherion-r0
252 12:26:17.215248 output: Kernel: kernel-1
253 12:26:17.215359 output: Init Ramdisk: ramdisk-1
254 12:26:17.215460 output: FDT: fdt-1
255 12:26:17.215561 output: Loadables: kernel-1
256 12:26:17.215666 output:
257 12:26:17.215946 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
258 12:26:17.216111 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
259 12:26:17.216274 end: 1.5 prepare-tftp-overlay (duration 00:00:32) [common]
260 12:26:17.216437 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:26) [common]
261 12:26:17.216565 No LXC device requested
262 12:26:17.216699 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 12:26:17.216832 start: 1.7 deploy-device-env (timeout 00:09:26) [common]
264 12:26:17.216966 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 12:26:17.217083 Checking files for TFTP limit of 4294967296 bytes.
266 12:26:17.217803 end: 1 tftp-deploy (duration 00:00:34) [common]
267 12:26:17.217956 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 12:26:17.218107 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 12:26:17.218291 substitutions:
270 12:26:17.218417 - {DTB}: 10605776/tftp-deploy-yypd6nms/dtb/mt8192-asurada-spherion-r0.dtb
271 12:26:17.218519 - {INITRD}: 10605776/tftp-deploy-yypd6nms/ramdisk/ramdisk.cpio.gz
272 12:26:17.218629 - {KERNEL}: 10605776/tftp-deploy-yypd6nms/kernel/Image
273 12:26:17.218741 - {LAVA_MAC}: None
274 12:26:17.218834 - {PRESEED_CONFIG}: None
275 12:26:17.218935 - {PRESEED_LOCAL}: None
276 12:26:17.219028 - {RAMDISK}: 10605776/tftp-deploy-yypd6nms/ramdisk/ramdisk.cpio.gz
277 12:26:17.219127 - {ROOT_PART}: None
278 12:26:17.219230 - {ROOT}: None
279 12:26:17.219324 - {SERVER_IP}: 192.168.201.1
280 12:26:17.219438 - {TEE}: None
281 12:26:17.219536 Parsed boot commands:
282 12:26:17.219635 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 12:26:17.219884 Parsed boot commands: tftpboot 192.168.201.1 10605776/tftp-deploy-yypd6nms/kernel/image.itb 10605776/tftp-deploy-yypd6nms/kernel/cmdline
284 12:26:17.220026 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 12:26:17.220177 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 12:26:17.220324 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 12:26:17.220465 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 12:26:17.220580 Not connected, no need to disconnect.
289 12:26:17.220703 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 12:26:17.220828 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 12:26:17.220950 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
292 12:26:17.224930 Setting prompt string to ['lava-test: # ']
293 12:26:17.225440 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 12:26:17.225629 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 12:26:17.225784 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 12:26:17.225930 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 12:26:17.226236 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
298 12:26:22.364360 >> Command sent successfully.
299 12:26:22.366719 Returned 0 in 5 seconds
300 12:26:22.467100 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 12:26:22.467419 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 12:26:22.467541 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 12:26:22.467654 Setting prompt string to 'Starting depthcharge on Spherion...'
305 12:26:22.467732 Changing prompt to 'Starting depthcharge on Spherion...'
306 12:26:22.467806 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 12:26:22.468079 [Enter `^Ec?' for help]
308 12:26:22.640057
309 12:26:22.640217
310 12:26:22.640306 F0: 102B 0000
311 12:26:22.640382
312 12:26:22.643292 F3: 1001 0000 [0200]
313 12:26:22.643381
314 12:26:22.643450 F3: 1001 0000
315 12:26:22.643514
316 12:26:22.643576 F7: 102D 0000
317 12:26:22.643636
318 12:26:22.646951 F1: 0000 0000
319 12:26:22.647059
320 12:26:22.647129 V0: 0000 0000 [0001]
321 12:26:22.647194
322 12:26:22.650714 00: 0007 8000
323 12:26:22.650824
324 12:26:22.650895 01: 0000 0000
325 12:26:22.650963
326 12:26:22.651025 BP: 0C00 0209 [0000]
327 12:26:22.651087
328 12:26:22.654345 G0: 1182 0000
329 12:26:22.654443
330 12:26:22.654522 EC: 0000 0021 [4000]
331 12:26:22.654594
332 12:26:22.657942 S7: 0000 0000 [0000]
333 12:26:22.658035
334 12:26:22.658104 CC: 0000 0000 [0001]
335 12:26:22.658168
336 12:26:22.661039 T0: 0000 0040 [010F]
337 12:26:22.661141
338 12:26:22.661213 Jump to BL
339 12:26:22.661279
340 12:26:22.687846
341 12:26:22.687993
342 12:26:22.688080
343 12:26:22.694869 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 12:26:22.698731 ARM64: Exception handlers installed.
345 12:26:22.702354 ARM64: Testing exception
346 12:26:22.706229 ARM64: Done test exception
347 12:26:22.713633 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 12:26:22.719757 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 12:26:22.727280 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 12:26:22.737967 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 12:26:22.744164 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 12:26:22.754764 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 12:26:22.765200 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 12:26:22.771499 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 12:26:22.790355 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 12:26:22.793411 WDT: Last reset was cold boot
357 12:26:22.796478 SPI1(PAD0) initialized at 2873684 Hz
358 12:26:22.799635 SPI5(PAD0) initialized at 992727 Hz
359 12:26:22.803394 VBOOT: Loading verstage.
360 12:26:22.810134 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 12:26:22.813254 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 12:26:22.816155 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 12:26:22.819879 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 12:26:22.827342 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 12:26:22.834700 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 12:26:22.845034 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 12:26:22.845205
368 12:26:22.845308
369 12:26:22.854752 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 12:26:22.857918 ARM64: Exception handlers installed.
371 12:26:22.861606 ARM64: Testing exception
372 12:26:22.864705 ARM64: Done test exception
373 12:26:22.868178 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 12:26:22.871760 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 12:26:22.885988 Probing TPM: . done!
376 12:26:22.886157 TPM ready after 0 ms
377 12:26:22.893639 Connected to device vid:did:rid of 1ae0:0028:00
378 12:26:22.899924 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
379 12:26:22.958693 Initialized TPM device CR50 revision 0
380 12:26:22.969947 tlcl_send_startup: Startup return code is 0
381 12:26:22.970114 TPM: setup succeeded
382 12:26:22.981974 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 12:26:22.990185 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 12:26:23.002205 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 12:26:23.012419 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 12:26:23.015450 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 12:26:23.021084 in-header: 03 07 00 00 08 00 00 00
388 12:26:23.024309 in-data: aa e4 47 04 13 02 00 00
389 12:26:23.028100 Chrome EC: UHEPI supported
390 12:26:23.034918 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 12:26:23.038697 in-header: 03 95 00 00 08 00 00 00
392 12:26:23.042371 in-data: 18 20 20 08 00 00 00 00
393 12:26:23.042483 Phase 1
394 12:26:23.046168 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 12:26:23.053229 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 12:26:23.056831 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 12:26:23.060659 Recovery requested (1009000e)
398 12:26:23.069253 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 12:26:23.075145 tlcl_extend: response is 0
400 12:26:23.084509 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 12:26:23.089908 tlcl_extend: response is 0
402 12:26:23.096580 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 12:26:23.116850 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 12:26:23.123580 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 12:26:23.123719
406 12:26:23.123793
407 12:26:23.133284 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 12:26:23.136922 ARM64: Exception handlers installed.
409 12:26:23.140128 ARM64: Testing exception
410 12:26:23.140223 ARM64: Done test exception
411 12:26:23.161897 pmic_efuse_setting: Set efuses in 11 msecs
412 12:26:23.165528 pmwrap_interface_init: Select PMIF_VLD_RDY
413 12:26:23.171799 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 12:26:23.175062 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 12:26:23.182211 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 12:26:23.185703 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 12:26:23.189355 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 12:26:23.196827 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 12:26:23.200276 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 12:26:23.204018 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 12:26:23.211388 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 12:26:23.215302 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 12:26:23.218520 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 12:26:23.222970 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 12:26:23.229715 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 12:26:23.233294 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 12:26:23.240787 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 12:26:23.244534 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 12:26:23.251335 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 12:26:23.258746 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 12:26:23.262904 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 12:26:23.270097 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 12:26:23.273709 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 12:26:23.281240 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 12:26:23.284739 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 12:26:23.292245 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 12:26:23.295914 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 12:26:23.303071 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 12:26:23.306576 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 12:26:23.310364 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 12:26:23.317767 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 12:26:23.321401 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 12:26:23.325229 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 12:26:23.332454 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 12:26:23.335683 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 12:26:23.339431 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 12:26:23.346777 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 12:26:23.350652 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 12:26:23.358036 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 12:26:23.361872 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 12:26:23.365416 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 12:26:23.368924 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 12:26:23.372503 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 12:26:23.379708 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 12:26:23.383924 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 12:26:23.387673 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 12:26:23.391290 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 12:26:23.394995 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 12:26:23.398591 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 12:26:23.405425 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 12:26:23.409436 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 12:26:23.413204 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 12:26:23.416264 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 12:26:23.424217 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 12:26:23.435539 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 12:26:23.439063 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 12:26:23.446527 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 12:26:23.453949 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 12:26:23.457687 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 12:26:23.465109 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 12:26:23.469443 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 12:26:23.476482 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x3
473 12:26:23.479505 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 12:26:23.486969 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
475 12:26:23.490053 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 12:26:23.499436 [RTC]rtc_get_frequency_meter,154: input=15, output=851
477 12:26:23.509368 [RTC]rtc_get_frequency_meter,154: input=7, output=724
478 12:26:23.518936 [RTC]rtc_get_frequency_meter,154: input=11, output=788
479 12:26:23.528265 [RTC]rtc_get_frequency_meter,154: input=13, output=820
480 12:26:23.537457 [RTC]rtc_get_frequency_meter,154: input=12, output=803
481 12:26:23.546812 [RTC]rtc_get_frequency_meter,154: input=11, output=788
482 12:26:23.556295 [RTC]rtc_get_frequency_meter,154: input=12, output=804
483 12:26:23.560219 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
484 12:26:23.566935 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
485 12:26:23.570863 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 12:26:23.575177 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 12:26:23.578180 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 12:26:23.582385 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 12:26:23.585434 ADC[4]: Raw value=903694 ID=7
490 12:26:23.589339 ADC[3]: Raw value=213916 ID=1
491 12:26:23.589446 RAM Code: 0x71
492 12:26:23.593004 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 12:26:23.600027 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 12:26:23.608097 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 12:26:23.614909 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 12:26:23.618451 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 12:26:23.622084 in-header: 03 07 00 00 08 00 00 00
498 12:26:23.626297 in-data: aa e4 47 04 13 02 00 00
499 12:26:23.626414 Chrome EC: UHEPI supported
500 12:26:23.633379 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 12:26:23.637236 in-header: 03 95 00 00 08 00 00 00
502 12:26:23.640767 in-data: 18 20 20 08 00 00 00 00
503 12:26:23.644602 MRC: failed to locate region type 0.
504 12:26:23.651421 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 12:26:23.655777 DRAM-K: Running full calibration
506 12:26:23.658924 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 12:26:23.662590 header.status = 0x0
508 12:26:23.667033 header.version = 0x6 (expected: 0x6)
509 12:26:23.670109 header.size = 0xd00 (expected: 0xd00)
510 12:26:23.670212 header.flags = 0x0
511 12:26:23.676810 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 12:26:23.707149 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
513 12:26:23.707307 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 12:26:23.707418 dram_init: ddr_geometry: 2
515 12:26:23.707507 [EMI] MDL number = 2
516 12:26:23.709477 [EMI] Get MDL freq = 0
517 12:26:23.709572 dram_init: ddr_type: 0
518 12:26:23.713368 is_discrete_lpddr4: 1
519 12:26:23.716864 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 12:26:23.716964
521 12:26:23.717037
522 12:26:23.717103 [Bian_co] ETT version 0.0.0.1
523 12:26:23.723993 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 12:26:23.724146
525 12:26:23.728091 dramc_set_vcore_voltage set vcore to 650000
526 12:26:23.728206 Read voltage for 800, 4
527 12:26:23.731271 Vio18 = 0
528 12:26:23.731371 Vcore = 650000
529 12:26:23.731443 Vdram = 0
530 12:26:23.734292 Vddq = 0
531 12:26:23.734380 Vmddr = 0
532 12:26:23.738028 dram_init: config_dvfs: 1
533 12:26:23.741087 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 12:26:23.748070 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 12:26:23.751808 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
536 12:26:23.755944 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
537 12:26:23.759607 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
538 12:26:23.763438 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
539 12:26:23.763574 MEM_TYPE=3, freq_sel=18
540 12:26:23.766554 sv_algorithm_assistance_LP4_1600
541 12:26:23.770232 ============ PULL DRAM RESETB DOWN ============
542 12:26:23.777125 ========== PULL DRAM RESETB DOWN end =========
543 12:26:23.780251 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 12:26:23.783642 ===================================
545 12:26:23.786741 LPDDR4 DRAM CONFIGURATION
546 12:26:23.814529 ===================================
547 12:26:23.814774 EX_ROW_EN[0] = 0x0
548 12:26:23.815120 EX_ROW_EN[1] = 0x0
549 12:26:23.815255 LP4Y_EN = 0x0
550 12:26:23.815383 WORK_FSP = 0x0
551 12:26:23.815511 WL = 0x2
552 12:26:23.815635 RL = 0x2
553 12:26:23.815756 BL = 0x2
554 12:26:23.815879 RPST = 0x0
555 12:26:23.815996 RD_PRE = 0x0
556 12:26:23.816123 WR_PRE = 0x1
557 12:26:23.816234 WR_PST = 0x0
558 12:26:23.816325 DBI_WR = 0x0
559 12:26:23.816415 DBI_RD = 0x0
560 12:26:23.816503 OTF = 0x1
561 12:26:23.818130 ===================================
562 12:26:23.821233 ===================================
563 12:26:23.821343 ANA top config
564 12:26:23.824843 ===================================
565 12:26:23.828437 DLL_ASYNC_EN = 0
566 12:26:23.831556 ALL_SLAVE_EN = 1
567 12:26:23.831685 NEW_RANK_MODE = 1
568 12:26:23.834687 DLL_IDLE_MODE = 1
569 12:26:23.838216 LP45_APHY_COMB_EN = 1
570 12:26:23.842023 TX_ODT_DIS = 1
571 12:26:23.845023 NEW_8X_MODE = 1
572 12:26:23.845153 ===================================
573 12:26:23.848203 ===================================
574 12:26:23.851882 data_rate = 1600
575 12:26:23.855039 CKR = 1
576 12:26:23.857929 DQ_P2S_RATIO = 8
577 12:26:23.861872 ===================================
578 12:26:23.864882 CA_P2S_RATIO = 8
579 12:26:23.868658 DQ_CA_OPEN = 0
580 12:26:23.868781 DQ_SEMI_OPEN = 0
581 12:26:23.871747 CA_SEMI_OPEN = 0
582 12:26:23.875288 CA_FULL_RATE = 0
583 12:26:23.878361 DQ_CKDIV4_EN = 1
584 12:26:23.882123 CA_CKDIV4_EN = 1
585 12:26:23.885214 CA_PREDIV_EN = 0
586 12:26:23.885337 PH8_DLY = 0
587 12:26:23.888780 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 12:26:23.891714 DQ_AAMCK_DIV = 4
589 12:26:23.895295 CA_AAMCK_DIV = 4
590 12:26:23.898495 CA_ADMCK_DIV = 4
591 12:26:23.898634 DQ_TRACK_CA_EN = 0
592 12:26:23.902368 CA_PICK = 800
593 12:26:23.905461 CA_MCKIO = 800
594 12:26:23.908483 MCKIO_SEMI = 0
595 12:26:23.912419 PLL_FREQ = 3068
596 12:26:23.915850 DQ_UI_PI_RATIO = 32
597 12:26:23.915986 CA_UI_PI_RATIO = 0
598 12:26:23.920026 ===================================
599 12:26:23.923008 ===================================
600 12:26:23.927178 memory_type:LPDDR4
601 12:26:23.927336 GP_NUM : 10
602 12:26:23.930757 SRAM_EN : 1
603 12:26:23.934249 MD32_EN : 0
604 12:26:23.934383 ===================================
605 12:26:23.938093 [ANA_INIT] >>>>>>>>>>>>>>
606 12:26:23.941596 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 12:26:23.945370 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 12:26:23.949098 ===================================
609 12:26:23.952261 data_rate = 1600,PCW = 0X7600
610 12:26:23.952385 ===================================
611 12:26:23.958989 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 12:26:23.962287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 12:26:23.968999 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 12:26:23.972049 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 12:26:23.975071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 12:26:23.978218 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 12:26:23.981886 [ANA_INIT] flow start
618 12:26:23.984992 [ANA_INIT] PLL >>>>>>>>
619 12:26:23.985085 [ANA_INIT] PLL <<<<<<<<
620 12:26:23.988149 [ANA_INIT] MIDPI >>>>>>>>
621 12:26:23.991907 [ANA_INIT] MIDPI <<<<<<<<
622 12:26:23.992003 [ANA_INIT] DLL >>>>>>>>
623 12:26:23.994901 [ANA_INIT] flow end
624 12:26:23.998506 ============ LP4 DIFF to SE enter ============
625 12:26:24.005051 ============ LP4 DIFF to SE exit ============
626 12:26:24.005182 [ANA_INIT] <<<<<<<<<<<<<
627 12:26:24.008704 [Flow] Enable top DCM control >>>>>
628 12:26:24.011824 [Flow] Enable top DCM control <<<<<
629 12:26:24.014868 Enable DLL master slave shuffle
630 12:26:24.021639 ==============================================================
631 12:26:24.021792 Gating Mode config
632 12:26:24.028203 ==============================================================
633 12:26:24.031864 Config description:
634 12:26:24.038304 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 12:26:24.044970 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 12:26:24.051670 SELPH_MODE 0: By rank 1: By Phase
637 12:26:24.057693 ==============================================================
638 12:26:24.061486 GAT_TRACK_EN = 1
639 12:26:24.061633 RX_GATING_MODE = 2
640 12:26:24.064469 RX_GATING_TRACK_MODE = 2
641 12:26:24.067721 SELPH_MODE = 1
642 12:26:24.071291 PICG_EARLY_EN = 1
643 12:26:24.074564 VALID_LAT_VALUE = 1
644 12:26:24.080745 ==============================================================
645 12:26:24.084414 Enter into Gating configuration >>>>
646 12:26:24.087443 Exit from Gating configuration <<<<
647 12:26:24.091123 Enter into DVFS_PRE_config >>>>>
648 12:26:24.100789 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 12:26:24.104449 Exit from DVFS_PRE_config <<<<<
650 12:26:24.107425 Enter into PICG configuration >>>>
651 12:26:24.111035 Exit from PICG configuration <<<<
652 12:26:24.114401 [RX_INPUT] configuration >>>>>
653 12:26:24.117294 [RX_INPUT] configuration <<<<<
654 12:26:24.120377 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 12:26:24.127237 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 12:26:24.133756 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 12:26:24.140500 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 12:26:24.143580 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 12:26:24.150000 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 12:26:24.156736 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 12:26:24.160426 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 12:26:24.163339 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 12:26:24.166661 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 12:26:24.169805 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 12:26:24.176551 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 12:26:24.180248 ===================================
667 12:26:24.183409 LPDDR4 DRAM CONFIGURATION
668 12:26:24.186487 ===================================
669 12:26:24.186604 EX_ROW_EN[0] = 0x0
670 12:26:24.190089 EX_ROW_EN[1] = 0x0
671 12:26:24.190202 LP4Y_EN = 0x0
672 12:26:24.193116 WORK_FSP = 0x0
673 12:26:24.193264 WL = 0x2
674 12:26:24.196789 RL = 0x2
675 12:26:24.196910 BL = 0x2
676 12:26:24.199936 RPST = 0x0
677 12:26:24.200052 RD_PRE = 0x0
678 12:26:24.203491 WR_PRE = 0x1
679 12:26:24.203611 WR_PST = 0x0
680 12:26:24.206345 DBI_WR = 0x0
681 12:26:24.206463 DBI_RD = 0x0
682 12:26:24.209874 OTF = 0x1
683 12:26:24.212849 ===================================
684 12:26:24.216742 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 12:26:24.219834 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 12:26:24.226424 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 12:26:24.229548 ===================================
688 12:26:24.233382 LPDDR4 DRAM CONFIGURATION
689 12:26:24.236110 ===================================
690 12:26:24.236216 EX_ROW_EN[0] = 0x10
691 12:26:24.239725 EX_ROW_EN[1] = 0x0
692 12:26:24.239847 LP4Y_EN = 0x0
693 12:26:24.242785 WORK_FSP = 0x0
694 12:26:24.242891 WL = 0x2
695 12:26:24.246388 RL = 0x2
696 12:26:24.246501 BL = 0x2
697 12:26:24.249338 RPST = 0x0
698 12:26:24.249457 RD_PRE = 0x0
699 12:26:24.252819 WR_PRE = 0x1
700 12:26:24.252917 WR_PST = 0x0
701 12:26:24.255837 DBI_WR = 0x0
702 12:26:24.255948 DBI_RD = 0x0
703 12:26:24.259331 OTF = 0x1
704 12:26:24.262558 ===================================
705 12:26:24.269281 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 12:26:24.273048 nWR fixed to 40
707 12:26:24.275992 [ModeRegInit_LP4] CH0 RK0
708 12:26:24.276111 [ModeRegInit_LP4] CH0 RK1
709 12:26:24.279070 [ModeRegInit_LP4] CH1 RK0
710 12:26:24.282561 [ModeRegInit_LP4] CH1 RK1
711 12:26:24.282678 match AC timing 13
712 12:26:24.289372 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 12:26:24.292485 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 12:26:24.295548 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 12:26:24.302257 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 12:26:24.305943 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 12:26:24.309049 [EMI DOE] emi_dcm 0
718 12:26:24.312439 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 12:26:24.312542 ==
720 12:26:24.315897 Dram Type= 6, Freq= 0, CH_0, rank 0
721 12:26:24.319070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 12:26:24.319173 ==
723 12:26:24.325908 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 12:26:24.332277 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 12:26:24.340242 [CA 0] Center 37 (7~68) winsize 62
726 12:26:24.343773 [CA 1] Center 37 (6~68) winsize 63
727 12:26:24.346858 [CA 2] Center 34 (4~65) winsize 62
728 12:26:24.350293 [CA 3] Center 34 (4~65) winsize 62
729 12:26:24.353239 [CA 4] Center 33 (3~64) winsize 62
730 12:26:24.357011 [CA 5] Center 33 (3~64) winsize 62
731 12:26:24.357120
732 12:26:24.359839 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 12:26:24.359967
734 12:26:24.363476 [CATrainingPosCal] consider 1 rank data
735 12:26:24.366738 u2DelayCellTimex100 = 270/100 ps
736 12:26:24.370405 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
737 12:26:24.376455 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
738 12:26:24.380275 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
739 12:26:24.383243 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
740 12:26:24.386827 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
741 12:26:24.390095 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 12:26:24.390212
743 12:26:24.393235 CA PerBit enable=1, Macro0, CA PI delay=33
744 12:26:24.393335
745 12:26:24.396879 [CBTSetCACLKResult] CA Dly = 33
746 12:26:24.396974 CS Dly: 5 (0~36)
747 12:26:24.400022 ==
748 12:26:24.403237 Dram Type= 6, Freq= 0, CH_0, rank 1
749 12:26:24.406412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 12:26:24.406530 ==
751 12:26:24.409584 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 12:26:24.416685 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 12:26:24.426593 [CA 0] Center 38 (7~69) winsize 63
754 12:26:24.429638 [CA 1] Center 37 (7~68) winsize 62
755 12:26:24.432851 [CA 2] Center 35 (4~66) winsize 63
756 12:26:24.436567 [CA 3] Center 35 (4~66) winsize 63
757 12:26:24.439691 [CA 4] Center 34 (3~65) winsize 63
758 12:26:24.442547 [CA 5] Center 33 (3~64) winsize 62
759 12:26:24.442644
760 12:26:24.446372 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 12:26:24.446466
762 12:26:24.449362 [CATrainingPosCal] consider 2 rank data
763 12:26:24.452557 u2DelayCellTimex100 = 270/100 ps
764 12:26:24.456006 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 12:26:24.462481 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
766 12:26:24.466232 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
767 12:26:24.469662 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
768 12:26:24.472704 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
769 12:26:24.475797 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 12:26:24.475917
771 12:26:24.478925 CA PerBit enable=1, Macro0, CA PI delay=33
772 12:26:24.479018
773 12:26:24.482220 [CBTSetCACLKResult] CA Dly = 33
774 12:26:24.485996 CS Dly: 6 (0~38)
775 12:26:24.486136
776 12:26:24.488880 ----->DramcWriteLeveling(PI) begin...
777 12:26:24.489011 ==
778 12:26:24.493396 Dram Type= 6, Freq= 0, CH_0, rank 0
779 12:26:24.496521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 12:26:24.496668 ==
781 12:26:24.500171 Write leveling (Byte 0): 31 => 31
782 12:26:24.504022 Write leveling (Byte 1): 26 => 26
783 12:26:24.504193 DramcWriteLeveling(PI) end<-----
784 12:26:24.504299
785 12:26:24.504405 ==
786 12:26:24.507732 Dram Type= 6, Freq= 0, CH_0, rank 0
787 12:26:24.514549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 12:26:24.514707 ==
789 12:26:24.514789 [Gating] SW mode calibration
790 12:26:24.521212 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 12:26:24.528455 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 12:26:24.531519 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 12:26:24.538147 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
794 12:26:24.541137 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
795 12:26:24.544893 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
796 12:26:24.551000 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:26:24.554710 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:26:24.558254 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:26:24.565087 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:26:24.567917 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:26:24.571057 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:26:24.574658 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:26:24.581409 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:26:24.584425 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:26:24.587666 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:26:24.594337 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:26:24.597510 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:26:24.601259 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:26:24.607691 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
810 12:26:24.611285 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
811 12:26:24.614488 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:26:24.621236 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:26:24.624274 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 12:26:24.627432 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 12:26:24.634538 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:26:24.637204 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:26:24.640717 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:26:24.647631 0 9 8 | B1->B0 | 2322 2d2d | 1 0 | (0 0) (0 0)
819 12:26:24.650699 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
820 12:26:24.653817 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 12:26:24.660712 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 12:26:24.663601 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 12:26:24.667355 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 12:26:24.673697 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 12:26:24.677230 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
826 12:26:24.680359 0 10 8 | B1->B0 | 3232 2727 | 0 0 | (0 0) (0 0)
827 12:26:24.687170 0 10 12 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
828 12:26:24.690255 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 12:26:24.694082 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 12:26:24.700177 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 12:26:24.703960 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 12:26:24.706997 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 12:26:24.713818 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
834 12:26:24.717074 0 11 8 | B1->B0 | 2525 3e3e | 0 0 | (0 0) (0 0)
835 12:26:24.720112 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
836 12:26:24.726872 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 12:26:24.729958 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 12:26:24.733448 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 12:26:24.740000 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 12:26:24.743600 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 12:26:24.746795 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 12:26:24.753435 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
843 12:26:24.756534 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:26:24.760105 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:26:24.766837 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:26:24.769957 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:26:24.773380 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:26:24.776449 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:26:24.783119 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:26:24.786971 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:26:24.790039 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:26:24.796731 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 12:26:24.799960 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 12:26:24.803248 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 12:26:24.809889 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 12:26:24.813136 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 12:26:24.816978 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 12:26:24.823169 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
859 12:26:24.826153 Total UI for P1: 0, mck2ui 16
860 12:26:24.829742 best dqsien dly found for B0: ( 0, 14, 6)
861 12:26:24.832937 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 12:26:24.836589 Total UI for P1: 0, mck2ui 16
863 12:26:24.839724 best dqsien dly found for B1: ( 0, 14, 8)
864 12:26:24.843004 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
865 12:26:24.845870 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 12:26:24.845961
867 12:26:24.849363 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
868 12:26:24.852539 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 12:26:24.856183 [Gating] SW calibration Done
870 12:26:24.856289 ==
871 12:26:24.859521 Dram Type= 6, Freq= 0, CH_0, rank 0
872 12:26:24.863047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 12:26:24.867098 ==
874 12:26:24.867254 RX Vref Scan: 0
875 12:26:24.867357
876 12:26:24.870163 RX Vref 0 -> 0, step: 1
877 12:26:24.870280
878 12:26:24.870377 RX Delay -130 -> 252, step: 16
879 12:26:24.877060 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
880 12:26:24.880423 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
881 12:26:24.883546 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 12:26:24.887426 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 12:26:24.890255 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
884 12:26:24.897108 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
885 12:26:24.900352 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
886 12:26:24.903394 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
887 12:26:24.907058 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
888 12:26:24.910133 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
889 12:26:24.916850 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
890 12:26:24.920042 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
891 12:26:24.923616 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
892 12:26:24.926782 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
893 12:26:24.929803 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
894 12:26:24.936578 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
895 12:26:24.936701 ==
896 12:26:24.939634 Dram Type= 6, Freq= 0, CH_0, rank 0
897 12:26:24.943474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 12:26:24.943598 ==
899 12:26:24.943708 DQS Delay:
900 12:26:24.946446 DQS0 = 0, DQS1 = 0
901 12:26:24.946567 DQM Delay:
902 12:26:24.950042 DQM0 = 88, DQM1 = 74
903 12:26:24.950157 DQ Delay:
904 12:26:24.952869 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
905 12:26:24.956353 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =101
906 12:26:24.959371 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
907 12:26:24.963110 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
908 12:26:24.963221
909 12:26:24.963295
910 12:26:24.963360 ==
911 12:26:24.966172 Dram Type= 6, Freq= 0, CH_0, rank 0
912 12:26:24.972817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 12:26:24.972950 ==
914 12:26:24.973024
915 12:26:24.973101
916 12:26:24.973168 TX Vref Scan disable
917 12:26:24.976617 == TX Byte 0 ==
918 12:26:24.979604 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
919 12:26:24.986266 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
920 12:26:24.986413 == TX Byte 1 ==
921 12:26:24.989818 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
922 12:26:24.996175 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
923 12:26:24.996329 ==
924 12:26:24.999405 Dram Type= 6, Freq= 0, CH_0, rank 0
925 12:26:25.002450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 12:26:25.002604 ==
927 12:26:25.015743 TX Vref=22, minBit 1, minWin=26, winSum=435
928 12:26:25.019006 TX Vref=24, minBit 1, minWin=26, winSum=440
929 12:26:25.022639 TX Vref=26, minBit 1, minWin=27, winSum=445
930 12:26:25.025792 TX Vref=28, minBit 1, minWin=27, winSum=449
931 12:26:25.029376 TX Vref=30, minBit 7, minWin=27, winSum=451
932 12:26:25.032426 TX Vref=32, minBit 2, minWin=27, winSum=449
933 12:26:25.039496 [TxChooseVref] Worse bit 7, Min win 27, Win sum 451, Final Vref 30
934 12:26:25.039648
935 12:26:25.042498 Final TX Range 1 Vref 30
936 12:26:25.042593
937 12:26:25.042662 ==
938 12:26:25.045936 Dram Type= 6, Freq= 0, CH_0, rank 0
939 12:26:25.048904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 12:26:25.049006 ==
941 12:26:25.052111
942 12:26:25.052246
943 12:26:25.052353 TX Vref Scan disable
944 12:26:25.055734 == TX Byte 0 ==
945 12:26:25.059310 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
946 12:26:25.062959 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
947 12:26:25.066003 == TX Byte 1 ==
948 12:26:25.069071 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
949 12:26:25.075656 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
950 12:26:25.075778
951 12:26:25.075856 [DATLAT]
952 12:26:25.075926 Freq=800, CH0 RK0
953 12:26:25.076005
954 12:26:25.079214 DATLAT Default: 0xa
955 12:26:25.079311 0, 0xFFFF, sum = 0
956 12:26:25.082293 1, 0xFFFF, sum = 0
957 12:26:25.082393 2, 0xFFFF, sum = 0
958 12:26:25.085817 3, 0xFFFF, sum = 0
959 12:26:25.089342 4, 0xFFFF, sum = 0
960 12:26:25.089459 5, 0xFFFF, sum = 0
961 12:26:25.092342 6, 0xFFFF, sum = 0
962 12:26:25.092439 7, 0xFFFF, sum = 0
963 12:26:25.095856 8, 0xFFFF, sum = 0
964 12:26:25.095944 9, 0x0, sum = 1
965 12:26:25.096047 10, 0x0, sum = 2
966 12:26:25.099002 11, 0x0, sum = 3
967 12:26:25.099080 12, 0x0, sum = 4
968 12:26:25.102124 best_step = 10
969 12:26:25.102245
970 12:26:25.102315 ==
971 12:26:25.105927 Dram Type= 6, Freq= 0, CH_0, rank 0
972 12:26:25.109040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 12:26:25.109129 ==
974 12:26:25.112172 RX Vref Scan: 1
975 12:26:25.112266
976 12:26:25.115861 Set Vref Range= 32 -> 127
977 12:26:25.115975
978 12:26:25.116086 RX Vref 32 -> 127, step: 1
979 12:26:25.116153
980 12:26:25.118816 RX Delay -111 -> 252, step: 8
981 12:26:25.118908
982 12:26:25.122469 Set Vref, RX VrefLevel [Byte0]: 32
983 12:26:25.125726 [Byte1]: 32
984 12:26:25.125882
985 12:26:25.129252 Set Vref, RX VrefLevel [Byte0]: 33
986 12:26:25.132235 [Byte1]: 33
987 12:26:25.136485
988 12:26:25.136628 Set Vref, RX VrefLevel [Byte0]: 34
989 12:26:25.139736 [Byte1]: 34
990 12:26:25.144072
991 12:26:25.144207 Set Vref, RX VrefLevel [Byte0]: 35
992 12:26:25.147169 [Byte1]: 35
993 12:26:25.151580
994 12:26:25.151698 Set Vref, RX VrefLevel [Byte0]: 36
995 12:26:25.155173 [Byte1]: 36
996 12:26:25.159536
997 12:26:25.159687 Set Vref, RX VrefLevel [Byte0]: 37
998 12:26:25.162949 [Byte1]: 37
999 12:26:25.167147
1000 12:26:25.167294 Set Vref, RX VrefLevel [Byte0]: 38
1001 12:26:25.170862 [Byte1]: 38
1002 12:26:25.175136
1003 12:26:25.175280 Set Vref, RX VrefLevel [Byte0]: 39
1004 12:26:25.178448 [Byte1]: 39
1005 12:26:25.182688
1006 12:26:25.182823 Set Vref, RX VrefLevel [Byte0]: 40
1007 12:26:25.186263 [Byte1]: 40
1008 12:26:25.190677
1009 12:26:25.190786 Set Vref, RX VrefLevel [Byte0]: 41
1010 12:26:25.193533 [Byte1]: 41
1011 12:26:25.197861
1012 12:26:25.197995 Set Vref, RX VrefLevel [Byte0]: 42
1013 12:26:25.200961 [Byte1]: 42
1014 12:26:25.205095
1015 12:26:25.205222 Set Vref, RX VrefLevel [Byte0]: 43
1016 12:26:25.208125 [Byte1]: 43
1017 12:26:25.212461
1018 12:26:25.212584 Set Vref, RX VrefLevel [Byte0]: 44
1019 12:26:25.216195 [Byte1]: 44
1020 12:26:25.220500
1021 12:26:25.220614 Set Vref, RX VrefLevel [Byte0]: 45
1022 12:26:25.223584 [Byte1]: 45
1023 12:26:25.227822
1024 12:26:25.227956 Set Vref, RX VrefLevel [Byte0]: 46
1025 12:26:25.231468 [Byte1]: 46
1026 12:26:25.235766
1027 12:26:25.235894 Set Vref, RX VrefLevel [Byte0]: 47
1028 12:26:25.238623 [Byte1]: 47
1029 12:26:25.243203
1030 12:26:25.243321 Set Vref, RX VrefLevel [Byte0]: 48
1031 12:26:25.246896 [Byte1]: 48
1032 12:26:25.251310
1033 12:26:25.251438 Set Vref, RX VrefLevel [Byte0]: 49
1034 12:26:25.254195 [Byte1]: 49
1035 12:26:25.258573
1036 12:26:25.258705 Set Vref, RX VrefLevel [Byte0]: 50
1037 12:26:25.262361 [Byte1]: 50
1038 12:26:25.266460
1039 12:26:25.266586 Set Vref, RX VrefLevel [Byte0]: 51
1040 12:26:25.269299 [Byte1]: 51
1041 12:26:25.273917
1042 12:26:25.274043 Set Vref, RX VrefLevel [Byte0]: 52
1043 12:26:25.277440 [Byte1]: 52
1044 12:26:25.281619
1045 12:26:25.281750 Set Vref, RX VrefLevel [Byte0]: 53
1046 12:26:25.284742 [Byte1]: 53
1047 12:26:25.289336
1048 12:26:25.289458 Set Vref, RX VrefLevel [Byte0]: 54
1049 12:26:25.292645 [Byte1]: 54
1050 12:26:25.296664
1051 12:26:25.296794 Set Vref, RX VrefLevel [Byte0]: 55
1052 12:26:25.300225 [Byte1]: 55
1053 12:26:25.304412
1054 12:26:25.304546 Set Vref, RX VrefLevel [Byte0]: 56
1055 12:26:25.307612 [Byte1]: 56
1056 12:26:25.311830
1057 12:26:25.311958 Set Vref, RX VrefLevel [Byte0]: 57
1058 12:26:25.315855 [Byte1]: 57
1059 12:26:25.319985
1060 12:26:25.320114 Set Vref, RX VrefLevel [Byte0]: 58
1061 12:26:25.323114 [Byte1]: 58
1062 12:26:25.327373
1063 12:26:25.327504 Set Vref, RX VrefLevel [Byte0]: 59
1064 12:26:25.330646 [Byte1]: 59
1065 12:26:25.335287
1066 12:26:25.335412 Set Vref, RX VrefLevel [Byte0]: 60
1067 12:26:25.338352 [Byte1]: 60
1068 12:26:25.342561
1069 12:26:25.342684 Set Vref, RX VrefLevel [Byte0]: 61
1070 12:26:25.345751 [Byte1]: 61
1071 12:26:25.350099
1072 12:26:25.350232 Set Vref, RX VrefLevel [Byte0]: 62
1073 12:26:25.353621 [Byte1]: 62
1074 12:26:25.357839
1075 12:26:25.357964 Set Vref, RX VrefLevel [Byte0]: 63
1076 12:26:25.361638 [Byte1]: 63
1077 12:26:25.365457
1078 12:26:25.365549 Set Vref, RX VrefLevel [Byte0]: 64
1079 12:26:25.369094 [Byte1]: 64
1080 12:26:25.373003
1081 12:26:25.373110 Set Vref, RX VrefLevel [Byte0]: 65
1082 12:26:25.376962 [Byte1]: 65
1083 12:26:25.380928
1084 12:26:25.381027 Set Vref, RX VrefLevel [Byte0]: 66
1085 12:26:25.383853 [Byte1]: 66
1086 12:26:25.388757
1087 12:26:25.388854 Set Vref, RX VrefLevel [Byte0]: 67
1088 12:26:25.391707 [Byte1]: 67
1089 12:26:25.396135
1090 12:26:25.396233 Set Vref, RX VrefLevel [Byte0]: 68
1091 12:26:25.399639 [Byte1]: 68
1092 12:26:25.403771
1093 12:26:25.403897 Set Vref, RX VrefLevel [Byte0]: 69
1094 12:26:25.407285 [Byte1]: 69
1095 12:26:25.411490
1096 12:26:25.411601 Set Vref, RX VrefLevel [Byte0]: 70
1097 12:26:25.414654 [Byte1]: 70
1098 12:26:25.419019
1099 12:26:25.419121 Set Vref, RX VrefLevel [Byte0]: 71
1100 12:26:25.422166 [Byte1]: 71
1101 12:26:25.426815
1102 12:26:25.426952 Set Vref, RX VrefLevel [Byte0]: 72
1103 12:26:25.430441 [Byte1]: 72
1104 12:26:25.434175
1105 12:26:25.434297 Set Vref, RX VrefLevel [Byte0]: 73
1106 12:26:25.437854 [Byte1]: 73
1107 12:26:25.442190
1108 12:26:25.442316 Set Vref, RX VrefLevel [Byte0]: 74
1109 12:26:25.445239 [Byte1]: 74
1110 12:26:25.449538
1111 12:26:25.449624 Final RX Vref Byte 0 = 56 to rank0
1112 12:26:25.453054 Final RX Vref Byte 1 = 62 to rank0
1113 12:26:25.456237 Final RX Vref Byte 0 = 56 to rank1
1114 12:26:25.459303 Final RX Vref Byte 1 = 62 to rank1==
1115 12:26:25.463038 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 12:26:25.469805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 12:26:25.469952 ==
1118 12:26:25.470061 DQS Delay:
1119 12:26:25.472835 DQS0 = 0, DQS1 = 0
1120 12:26:25.472944 DQM Delay:
1121 12:26:25.473040 DQM0 = 88, DQM1 = 76
1122 12:26:25.475855 DQ Delay:
1123 12:26:25.479426 DQ0 =88, DQ1 =88, DQ2 =88, DQ3 =84
1124 12:26:25.482791 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1125 12:26:25.485788 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1126 12:26:25.489536 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1127 12:26:25.489659
1128 12:26:25.489756
1129 12:26:25.495486 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1130 12:26:25.499183 CH0 RK0: MR19=606, MR18=2E28
1131 12:26:25.505757 CH0_RK0: MR19=0x606, MR18=0x2E28, DQSOSC=398, MR23=63, INC=93, DEC=62
1132 12:26:25.505897
1133 12:26:25.508734 ----->DramcWriteLeveling(PI) begin...
1134 12:26:25.508847 ==
1135 12:26:25.512247 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 12:26:25.515363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 12:26:25.515477 ==
1138 12:26:25.519172 Write leveling (Byte 0): 32 => 32
1139 12:26:25.522177 Write leveling (Byte 1): 26 => 26
1140 12:26:25.525211 DramcWriteLeveling(PI) end<-----
1141 12:26:25.525328
1142 12:26:25.525424 ==
1143 12:26:25.528827 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 12:26:25.532410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 12:26:25.532530 ==
1146 12:26:25.535573 [Gating] SW mode calibration
1147 12:26:25.542365 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 12:26:25.548514 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 12:26:25.552176 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 12:26:25.595652 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 12:26:25.596286 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 12:26:25.597012 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 12:26:25.597330 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 12:26:25.597425 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 12:26:25.597499 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:26:25.597564 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:26:25.597644 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:26:25.597896 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:26:25.597963 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:26:25.600597 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:26:25.604322 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:26:25.610882 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:26:25.614127 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:26:25.617347 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:26:25.624143 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1166 12:26:25.627851 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1167 12:26:25.630900 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1168 12:26:25.637628 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:26:25.640648 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:26:25.644418 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:26:25.650531 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:26:25.654206 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:26:25.657174 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:26:25.664048 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1175 12:26:25.667515 0 9 8 | B1->B0 | 2525 3333 | 0 1 | (0 0) (1 1)
1176 12:26:25.670780 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1177 12:26:25.677372 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 12:26:25.680420 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 12:26:25.683995 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 12:26:25.690383 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 12:26:25.693844 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 12:26:25.697484 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 1)
1183 12:26:25.703616 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
1184 12:26:25.707282 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 12:26:25.710242 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 12:26:25.716722 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:26:25.720399 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:26:25.723472 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:26:25.730381 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:26:25.733600 0 11 4 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
1191 12:26:25.737194 0 11 8 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
1192 12:26:25.740935 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 12:26:25.748317 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 12:26:25.752013 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 12:26:25.755181 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 12:26:25.759008 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 12:26:25.765523 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 12:26:25.769279 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1199 12:26:25.772367 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1200 12:26:25.776208 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 12:26:25.782920 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 12:26:25.786049 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 12:26:25.789088 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:26:25.796165 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:26:25.799212 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:26:25.802232 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:26:25.808931 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:26:25.812654 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:26:25.815650 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:26:25.822292 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:26:25.825895 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:26:25.829134 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:26:25.835303 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:26:25.839044 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:26:25.842089 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1216 12:26:25.845312 Total UI for P1: 0, mck2ui 16
1217 12:26:25.849090 best dqsien dly found for B0: ( 0, 14, 6)
1218 12:26:25.855270 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 12:26:25.855395 Total UI for P1: 0, mck2ui 16
1220 12:26:25.861926 best dqsien dly found for B1: ( 0, 14, 8)
1221 12:26:25.865089 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1222 12:26:25.868653 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1223 12:26:25.868790
1224 12:26:25.871640 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1225 12:26:25.875232 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 12:26:25.878385 [Gating] SW calibration Done
1227 12:26:25.878509 ==
1228 12:26:25.881449 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 12:26:25.885235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 12:26:25.885352 ==
1231 12:26:25.888279 RX Vref Scan: 0
1232 12:26:25.888362
1233 12:26:25.888428 RX Vref 0 -> 0, step: 1
1234 12:26:25.888490
1235 12:26:25.891882 RX Delay -130 -> 252, step: 16
1236 12:26:25.894956 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1237 12:26:25.901540 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1238 12:26:25.904653 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1239 12:26:25.908326 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1240 12:26:25.911409 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1241 12:26:25.914987 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1242 12:26:25.921676 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1243 12:26:25.924661 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1244 12:26:25.928055 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1245 12:26:25.931765 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1246 12:26:25.934894 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1247 12:26:25.941156 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1248 12:26:25.944808 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1249 12:26:25.947998 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1250 12:26:25.950960 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1251 12:26:25.957786 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1252 12:26:25.957935 ==
1253 12:26:25.961085 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 12:26:25.964688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 12:26:25.964787 ==
1256 12:26:25.964857 DQS Delay:
1257 12:26:25.967612 DQS0 = 0, DQS1 = 0
1258 12:26:25.967728 DQM Delay:
1259 12:26:25.971285 DQM0 = 84, DQM1 = 79
1260 12:26:25.971447 DQ Delay:
1261 12:26:25.974264 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1262 12:26:25.977509 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =85
1263 12:26:25.981162 DQ8 =69, DQ9 =61, DQ10 =85, DQ11 =77
1264 12:26:25.984256 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1265 12:26:25.984354
1266 12:26:25.984424
1267 12:26:25.984487 ==
1268 12:26:25.987367 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 12:26:25.990964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 12:26:25.991085 ==
1271 12:26:25.991183
1272 12:26:25.993992
1273 12:26:25.994106 TX Vref Scan disable
1274 12:26:25.997577 == TX Byte 0 ==
1275 12:26:26.000743 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1276 12:26:26.004225 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1277 12:26:26.007348 == TX Byte 1 ==
1278 12:26:26.010512 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1279 12:26:26.014112 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1280 12:26:26.014256 ==
1281 12:26:26.017187 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 12:26:26.023736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 12:26:26.023885 ==
1284 12:26:26.036398 TX Vref=22, minBit 1, minWin=27, winSum=443
1285 12:26:26.040117 TX Vref=24, minBit 1, minWin=27, winSum=445
1286 12:26:26.043107 TX Vref=26, minBit 2, minWin=27, winSum=444
1287 12:26:26.046585 TX Vref=28, minBit 1, minWin=27, winSum=449
1288 12:26:26.049710 TX Vref=30, minBit 1, minWin=27, winSum=451
1289 12:26:26.056409 TX Vref=32, minBit 4, minWin=27, winSum=448
1290 12:26:26.059415 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 30
1291 12:26:26.059533
1292 12:26:26.063282 Final TX Range 1 Vref 30
1293 12:26:26.063379
1294 12:26:26.063450 ==
1295 12:26:26.066367 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 12:26:26.069704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 12:26:26.069819 ==
1298 12:26:26.072704
1299 12:26:26.072807
1300 12:26:26.072878 TX Vref Scan disable
1301 12:26:26.076456 == TX Byte 0 ==
1302 12:26:26.079599 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1303 12:26:26.086940 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1304 12:26:26.087100 == TX Byte 1 ==
1305 12:26:26.089999 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1306 12:26:26.096712 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1307 12:26:26.096840
1308 12:26:26.096914 [DATLAT]
1309 12:26:26.096977 Freq=800, CH0 RK1
1310 12:26:26.097038
1311 12:26:26.099677 DATLAT Default: 0xa
1312 12:26:26.099776 0, 0xFFFF, sum = 0
1313 12:26:26.103316 1, 0xFFFF, sum = 0
1314 12:26:26.103440 2, 0xFFFF, sum = 0
1315 12:26:26.106362 3, 0xFFFF, sum = 0
1316 12:26:26.109935 4, 0xFFFF, sum = 0
1317 12:26:26.110058 5, 0xFFFF, sum = 0
1318 12:26:26.112837 6, 0xFFFF, sum = 0
1319 12:26:26.112950 7, 0xFFFF, sum = 0
1320 12:26:26.116360 8, 0xFFFF, sum = 0
1321 12:26:26.116515 9, 0x0, sum = 1
1322 12:26:26.119481 10, 0x0, sum = 2
1323 12:26:26.119597 11, 0x0, sum = 3
1324 12:26:26.119696 12, 0x0, sum = 4
1325 12:26:26.123153 best_step = 10
1326 12:26:26.123229
1327 12:26:26.123290 ==
1328 12:26:26.126310 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 12:26:26.129897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 12:26:26.129999 ==
1331 12:26:26.132877 RX Vref Scan: 0
1332 12:26:26.132966
1333 12:26:26.133032 RX Vref 0 -> 0, step: 1
1334 12:26:26.136250
1335 12:26:26.136340 RX Delay -95 -> 252, step: 8
1336 12:26:26.143049 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1337 12:26:26.146853 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1338 12:26:26.149805 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1339 12:26:26.152958 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1340 12:26:26.156570 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1341 12:26:26.163496 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1342 12:26:26.166438 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1343 12:26:26.169585 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1344 12:26:26.173369 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1345 12:26:26.176467 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1346 12:26:26.183145 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1347 12:26:26.186306 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1348 12:26:26.189441 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1349 12:26:26.193081 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1350 12:26:26.199641 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1351 12:26:26.202828 iDelay=209, Bit 15, Center 84 (-23 ~ 192) 216
1352 12:26:26.202942 ==
1353 12:26:26.205939 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 12:26:26.209672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 12:26:26.209760 ==
1356 12:26:26.212627 DQS Delay:
1357 12:26:26.212729 DQS0 = 0, DQS1 = 0
1358 12:26:26.212829 DQM Delay:
1359 12:26:26.215966 DQM0 = 86, DQM1 = 77
1360 12:26:26.216076 DQ Delay:
1361 12:26:26.219023 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1362 12:26:26.222822 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1363 12:26:26.225812 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1364 12:26:26.229357 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1365 12:26:26.229485
1366 12:26:26.229580
1367 12:26:26.239130 [DQSOSCAuto] RK1, (LSB)MR18= 0x2623, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1368 12:26:26.239258 CH0 RK1: MR19=606, MR18=2623
1369 12:26:26.245749 CH0_RK1: MR19=0x606, MR18=0x2623, DQSOSC=400, MR23=63, INC=92, DEC=61
1370 12:26:26.249364 [RxdqsGatingPostProcess] freq 800
1371 12:26:26.255961 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 12:26:26.258977 Pre-setting of DQS Precalculation
1373 12:26:26.262538 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 12:26:26.262670 ==
1375 12:26:26.265602 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 12:26:26.272390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 12:26:26.272498 ==
1378 12:26:26.275448 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 12:26:26.282296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 12:26:26.291468 [CA 0] Center 36 (6~67) winsize 62
1381 12:26:26.294641 [CA 1] Center 36 (6~67) winsize 62
1382 12:26:26.298255 [CA 2] Center 35 (5~65) winsize 61
1383 12:26:26.301550 [CA 3] Center 34 (4~65) winsize 62
1384 12:26:26.304677 [CA 4] Center 34 (4~65) winsize 62
1385 12:26:26.307655 [CA 5] Center 34 (3~65) winsize 63
1386 12:26:26.307744
1387 12:26:26.311399 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 12:26:26.311485
1389 12:26:26.314470 [CATrainingPosCal] consider 1 rank data
1390 12:26:26.318107 u2DelayCellTimex100 = 270/100 ps
1391 12:26:26.321036 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1392 12:26:26.328305 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1393 12:26:26.331343 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1394 12:26:26.334470 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1395 12:26:26.338212 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1396 12:26:26.341095 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1397 12:26:26.341176
1398 12:26:26.344715 CA PerBit enable=1, Macro0, CA PI delay=34
1399 12:26:26.344796
1400 12:26:26.348167 [CBTSetCACLKResult] CA Dly = 34
1401 12:26:26.348249 CS Dly: 4 (0~35)
1402 12:26:26.351149 ==
1403 12:26:26.354801 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 12:26:26.357776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 12:26:26.357894 ==
1406 12:26:26.360865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 12:26:26.367602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 12:26:26.377485 [CA 0] Center 37 (6~68) winsize 63
1409 12:26:26.381052 [CA 1] Center 36 (6~67) winsize 62
1410 12:26:26.384325 [CA 2] Center 34 (4~65) winsize 62
1411 12:26:26.387343 [CA 3] Center 33 (3~64) winsize 62
1412 12:26:26.391079 [CA 4] Center 34 (3~65) winsize 63
1413 12:26:26.394089 [CA 5] Center 34 (4~65) winsize 62
1414 12:26:26.394207
1415 12:26:26.397780 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1416 12:26:26.397893
1417 12:26:26.400763 [CATrainingPosCal] consider 2 rank data
1418 12:26:26.404547 u2DelayCellTimex100 = 270/100 ps
1419 12:26:26.408271 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 12:26:26.411953 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1421 12:26:26.415177 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1422 12:26:26.418673 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1423 12:26:26.422324 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 12:26:26.425878 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 12:26:26.425995
1426 12:26:26.430060 CA PerBit enable=1, Macro0, CA PI delay=34
1427 12:26:26.430185
1428 12:26:26.433811 [CBTSetCACLKResult] CA Dly = 34
1429 12:26:26.436809 CS Dly: 5 (0~37)
1430 12:26:26.436898
1431 12:26:26.440408 ----->DramcWriteLeveling(PI) begin...
1432 12:26:26.440539 ==
1433 12:26:26.444127 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 12:26:26.447114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 12:26:26.447209 ==
1436 12:26:26.450735 Write leveling (Byte 0): 27 => 27
1437 12:26:26.453608 Write leveling (Byte 1): 27 => 27
1438 12:26:26.457367 DramcWriteLeveling(PI) end<-----
1439 12:26:26.457456
1440 12:26:26.457526 ==
1441 12:26:26.460457 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 12:26:26.464200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 12:26:26.464304 ==
1444 12:26:26.467339 [Gating] SW mode calibration
1445 12:26:26.473555 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 12:26:26.480421 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 12:26:26.483523 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 12:26:26.487039 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1449 12:26:26.493840 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1450 12:26:26.496979 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 12:26:26.500071 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 12:26:26.506804 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 12:26:26.510556 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:26:26.513475 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:26:26.517197 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:26:26.523733 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:26:26.526869 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:26:26.530268 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:26:26.537063 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:26:26.540046 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:26:26.543594 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:26:26.550075 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:26:26.553683 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:26:26.556863 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1465 12:26:26.563299 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:26:26.566748 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:26:26.570019 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:26:26.576691 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:26:26.579972 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:26:26.582984 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:26:26.589695 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:26:26.592941 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:26:26.596637 0 9 8 | B1->B0 | 2929 3333 | 1 0 | (1 1) (0 0)
1474 12:26:26.603469 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 12:26:26.606463 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 12:26:26.609601 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 12:26:26.616338 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 12:26:26.619999 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 12:26:26.623025 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 12:26:26.629687 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
1481 12:26:26.633355 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1482 12:26:26.636203 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 12:26:26.642865 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:26:26.646584 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:26:26.650179 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:26:26.655978 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:26:26.659665 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:26:26.662820 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1489 12:26:26.669252 0 11 8 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (0 0)
1490 12:26:26.672985 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 12:26:26.676258 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 12:26:26.682409 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 12:26:26.685559 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 12:26:26.689332 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 12:26:26.695600 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 12:26:26.699181 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1497 12:26:26.702398 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 12:26:26.708820 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 12:26:26.711946 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 12:26:26.715809 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 12:26:26.721980 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:26:26.725726 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:26:26.728715 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:26:26.735748 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:26:26.738661 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:26:26.742213 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:26:26.745304 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:26:26.752216 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:26:26.755297 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:26:26.758931 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:26:26.765471 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:26:26.768752 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1513 12:26:26.772241 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1514 12:26:26.775227 Total UI for P1: 0, mck2ui 16
1515 12:26:26.778857 best dqsien dly found for B0: ( 0, 14, 4)
1516 12:26:26.785027 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 12:26:26.788728 Total UI for P1: 0, mck2ui 16
1518 12:26:26.791871 best dqsien dly found for B1: ( 0, 14, 6)
1519 12:26:26.795041 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1520 12:26:26.798574 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1521 12:26:26.798665
1522 12:26:26.801756 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1523 12:26:26.805460 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1524 12:26:26.808429 [Gating] SW calibration Done
1525 12:26:26.808513 ==
1526 12:26:26.811577 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 12:26:26.815228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 12:26:26.815353 ==
1529 12:26:26.818222 RX Vref Scan: 0
1530 12:26:26.818338
1531 12:26:26.818434 RX Vref 0 -> 0, step: 1
1532 12:26:26.818529
1533 12:26:26.821919 RX Delay -130 -> 252, step: 16
1534 12:26:26.828102 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1535 12:26:26.831876 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1536 12:26:26.834891 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1537 12:26:26.838675 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1538 12:26:26.841765 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1539 12:26:26.845263 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1540 12:26:26.852063 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1541 12:26:26.855016 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1542 12:26:26.858107 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1543 12:26:26.861717 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1544 12:26:26.867850 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1545 12:26:26.871200 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1546 12:26:26.874772 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1547 12:26:26.878438 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1548 12:26:26.881427 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1549 12:26:26.888336 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1550 12:26:26.888445 ==
1551 12:26:26.891303 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 12:26:26.894435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 12:26:26.894549 ==
1554 12:26:26.894647 DQS Delay:
1555 12:26:26.898210 DQS0 = 0, DQS1 = 0
1556 12:26:26.898323 DQM Delay:
1557 12:26:26.901335 DQM0 = 86, DQM1 = 81
1558 12:26:26.901417 DQ Delay:
1559 12:26:26.904301 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1560 12:26:26.908075 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1561 12:26:26.911143 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1562 12:26:26.914312 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =93
1563 12:26:26.914390
1564 12:26:26.914457
1565 12:26:26.914519 ==
1566 12:26:26.917930 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 12:26:26.921037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 12:26:26.921114 ==
1569 12:26:26.924900
1570 12:26:26.925011
1571 12:26:26.925105 TX Vref Scan disable
1572 12:26:26.927850 == TX Byte 0 ==
1573 12:26:26.930829 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1574 12:26:26.934048 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1575 12:26:26.937798 == TX Byte 1 ==
1576 12:26:26.940640 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1577 12:26:26.944233 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1578 12:26:26.947376 ==
1579 12:26:26.947498 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 12:26:26.954323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 12:26:26.954414 ==
1582 12:26:26.966399 TX Vref=22, minBit 2, minWin=27, winSum=446
1583 12:26:26.969453 TX Vref=24, minBit 2, minWin=27, winSum=449
1584 12:26:26.972915 TX Vref=26, minBit 5, minWin=27, winSum=450
1585 12:26:26.976132 TX Vref=28, minBit 4, minWin=27, winSum=454
1586 12:26:26.979894 TX Vref=30, minBit 5, minWin=27, winSum=454
1587 12:26:26.983490 TX Vref=32, minBit 5, minWin=27, winSum=454
1588 12:26:26.990327 [TxChooseVref] Worse bit 4, Min win 27, Win sum 454, Final Vref 28
1589 12:26:26.990447
1590 12:26:26.993905 Final TX Range 1 Vref 28
1591 12:26:26.994022
1592 12:26:26.994116 ==
1593 12:26:26.997128 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 12:26:27.000655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 12:26:27.000741 ==
1596 12:26:27.000809
1597 12:26:27.000871
1598 12:26:27.003670 TX Vref Scan disable
1599 12:26:27.006786 == TX Byte 0 ==
1600 12:26:27.010340 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1601 12:26:27.014100 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1602 12:26:27.017218 == TX Byte 1 ==
1603 12:26:27.020297 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1604 12:26:27.023844 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1605 12:26:27.023956
1606 12:26:27.026801 [DATLAT]
1607 12:26:27.026914 Freq=800, CH1 RK0
1608 12:26:27.027019
1609 12:26:27.030450 DATLAT Default: 0xa
1610 12:26:27.030539 0, 0xFFFF, sum = 0
1611 12:26:27.034117 1, 0xFFFF, sum = 0
1612 12:26:27.034203 2, 0xFFFF, sum = 0
1613 12:26:27.037341 3, 0xFFFF, sum = 0
1614 12:26:27.037428 4, 0xFFFF, sum = 0
1615 12:26:27.040310 5, 0xFFFF, sum = 0
1616 12:26:27.040397 6, 0xFFFF, sum = 0
1617 12:26:27.043314 7, 0xFFFF, sum = 0
1618 12:26:27.043396 8, 0xFFFF, sum = 0
1619 12:26:27.047146 9, 0x0, sum = 1
1620 12:26:27.047227 10, 0x0, sum = 2
1621 12:26:27.050085 11, 0x0, sum = 3
1622 12:26:27.050170 12, 0x0, sum = 4
1623 12:26:27.053694 best_step = 10
1624 12:26:27.053812
1625 12:26:27.053926 ==
1626 12:26:27.056677 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 12:26:27.060202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 12:26:27.060289 ==
1629 12:26:27.060363 RX Vref Scan: 1
1630 12:26:27.063387
1631 12:26:27.063470 Set Vref Range= 32 -> 127
1632 12:26:27.063536
1633 12:26:27.067086 RX Vref 32 -> 127, step: 1
1634 12:26:27.067192
1635 12:26:27.070145 RX Delay -95 -> 252, step: 8
1636 12:26:27.070230
1637 12:26:27.073813 Set Vref, RX VrefLevel [Byte0]: 32
1638 12:26:27.076709 [Byte1]: 32
1639 12:26:27.076811
1640 12:26:27.080410 Set Vref, RX VrefLevel [Byte0]: 33
1641 12:26:27.084148 [Byte1]: 33
1642 12:26:27.084230
1643 12:26:27.086523 Set Vref, RX VrefLevel [Byte0]: 34
1644 12:26:27.090052 [Byte1]: 34
1645 12:26:27.093720
1646 12:26:27.093808 Set Vref, RX VrefLevel [Byte0]: 35
1647 12:26:27.097306 [Byte1]: 35
1648 12:26:27.101482
1649 12:26:27.101609 Set Vref, RX VrefLevel [Byte0]: 36
1650 12:26:27.104708 [Byte1]: 36
1651 12:26:27.109090
1652 12:26:27.109207 Set Vref, RX VrefLevel [Byte0]: 37
1653 12:26:27.112679 [Byte1]: 37
1654 12:26:27.116895
1655 12:26:27.117000 Set Vref, RX VrefLevel [Byte0]: 38
1656 12:26:27.120052 [Byte1]: 38
1657 12:26:27.124528
1658 12:26:27.124648 Set Vref, RX VrefLevel [Byte0]: 39
1659 12:26:27.127433 [Byte1]: 39
1660 12:26:27.131689
1661 12:26:27.131806 Set Vref, RX VrefLevel [Byte0]: 40
1662 12:26:27.135359 [Byte1]: 40
1663 12:26:27.139646
1664 12:26:27.139752 Set Vref, RX VrefLevel [Byte0]: 41
1665 12:26:27.142695 [Byte1]: 41
1666 12:26:27.147241
1667 12:26:27.147358 Set Vref, RX VrefLevel [Byte0]: 42
1668 12:26:27.150374 [Byte1]: 42
1669 12:26:27.154550
1670 12:26:27.154630 Set Vref, RX VrefLevel [Byte0]: 43
1671 12:26:27.158017 [Byte1]: 43
1672 12:26:27.162226
1673 12:26:27.162308 Set Vref, RX VrefLevel [Byte0]: 44
1674 12:26:27.165358 [Byte1]: 44
1675 12:26:27.170227
1676 12:26:27.170317 Set Vref, RX VrefLevel [Byte0]: 45
1677 12:26:27.173304 [Byte1]: 45
1678 12:26:27.177468
1679 12:26:27.177555 Set Vref, RX VrefLevel [Byte0]: 46
1680 12:26:27.181157 [Byte1]: 46
1681 12:26:27.185153
1682 12:26:27.185265 Set Vref, RX VrefLevel [Byte0]: 47
1683 12:26:27.188308 [Byte1]: 47
1684 12:26:27.192891
1685 12:26:27.193004 Set Vref, RX VrefLevel [Byte0]: 48
1686 12:26:27.195775 [Byte1]: 48
1687 12:26:27.200576
1688 12:26:27.200665 Set Vref, RX VrefLevel [Byte0]: 49
1689 12:26:27.203649 [Byte1]: 49
1690 12:26:27.207849
1691 12:26:27.207956 Set Vref, RX VrefLevel [Byte0]: 50
1692 12:26:27.211011 [Byte1]: 50
1693 12:26:27.215346
1694 12:26:27.215456 Set Vref, RX VrefLevel [Byte0]: 51
1695 12:26:27.219125 [Byte1]: 51
1696 12:26:27.223319
1697 12:26:27.223417 Set Vref, RX VrefLevel [Byte0]: 52
1698 12:26:27.226524 [Byte1]: 52
1699 12:26:27.230777
1700 12:26:27.230894 Set Vref, RX VrefLevel [Byte0]: 53
1701 12:26:27.234311 [Byte1]: 53
1702 12:26:27.238521
1703 12:26:27.241810 Set Vref, RX VrefLevel [Byte0]: 54
1704 12:26:27.244890 [Byte1]: 54
1705 12:26:27.244974
1706 12:26:27.248014 Set Vref, RX VrefLevel [Byte0]: 55
1707 12:26:27.251564 [Byte1]: 55
1708 12:26:27.251654
1709 12:26:27.254734 Set Vref, RX VrefLevel [Byte0]: 56
1710 12:26:27.258381 [Byte1]: 56
1711 12:26:27.258464
1712 12:26:27.261212 Set Vref, RX VrefLevel [Byte0]: 57
1713 12:26:27.264862 [Byte1]: 57
1714 12:26:27.268526
1715 12:26:27.268608 Set Vref, RX VrefLevel [Byte0]: 58
1716 12:26:27.272459 [Byte1]: 58
1717 12:26:27.276650
1718 12:26:27.276750 Set Vref, RX VrefLevel [Byte0]: 59
1719 12:26:27.279722 [Byte1]: 59
1720 12:26:27.284160
1721 12:26:27.284261 Set Vref, RX VrefLevel [Byte0]: 60
1722 12:26:27.287231 [Byte1]: 60
1723 12:26:27.291231
1724 12:26:27.291311 Set Vref, RX VrefLevel [Byte0]: 61
1725 12:26:27.294676 [Byte1]: 61
1726 12:26:27.298939
1727 12:26:27.299045 Set Vref, RX VrefLevel [Byte0]: 62
1728 12:26:27.302540 [Byte1]: 62
1729 12:26:27.306545
1730 12:26:27.306658 Set Vref, RX VrefLevel [Byte0]: 63
1731 12:26:27.310166 [Byte1]: 63
1732 12:26:27.314546
1733 12:26:27.314667 Set Vref, RX VrefLevel [Byte0]: 64
1734 12:26:27.317665 [Byte1]: 64
1735 12:26:27.322062
1736 12:26:27.322144 Set Vref, RX VrefLevel [Byte0]: 65
1737 12:26:27.325172 [Byte1]: 65
1738 12:26:27.329574
1739 12:26:27.329691 Set Vref, RX VrefLevel [Byte0]: 66
1740 12:26:27.332633 [Byte1]: 66
1741 12:26:27.336768
1742 12:26:27.340381 Set Vref, RX VrefLevel [Byte0]: 67
1743 12:26:27.343445 [Byte1]: 67
1744 12:26:27.343557
1745 12:26:27.347137 Set Vref, RX VrefLevel [Byte0]: 68
1746 12:26:27.350197 [Byte1]: 68
1747 12:26:27.350281
1748 12:26:27.353400 Set Vref, RX VrefLevel [Byte0]: 69
1749 12:26:27.357158 [Byte1]: 69
1750 12:26:27.357240
1751 12:26:27.360190 Set Vref, RX VrefLevel [Byte0]: 70
1752 12:26:27.363231 [Byte1]: 70
1753 12:26:27.367289
1754 12:26:27.367414 Set Vref, RX VrefLevel [Byte0]: 71
1755 12:26:27.370989 [Byte1]: 71
1756 12:26:27.375190
1757 12:26:27.375278 Set Vref, RX VrefLevel [Byte0]: 72
1758 12:26:27.378354 [Byte1]: 72
1759 12:26:27.382456
1760 12:26:27.382551 Set Vref, RX VrefLevel [Byte0]: 73
1761 12:26:27.386084 [Byte1]: 73
1762 12:26:27.390226
1763 12:26:27.390309 Set Vref, RX VrefLevel [Byte0]: 74
1764 12:26:27.393717 [Byte1]: 74
1765 12:26:27.397857
1766 12:26:27.397939 Set Vref, RX VrefLevel [Byte0]: 75
1767 12:26:27.400953 [Byte1]: 75
1768 12:26:27.405598
1769 12:26:27.405685 Set Vref, RX VrefLevel [Byte0]: 76
1770 12:26:27.409270 [Byte1]: 76
1771 12:26:27.412929
1772 12:26:27.413016 Final RX Vref Byte 0 = 57 to rank0
1773 12:26:27.416623 Final RX Vref Byte 1 = 59 to rank0
1774 12:26:27.419554 Final RX Vref Byte 0 = 57 to rank1
1775 12:26:27.422575 Final RX Vref Byte 1 = 59 to rank1==
1776 12:26:27.426438 Dram Type= 6, Freq= 0, CH_1, rank 0
1777 12:26:27.432606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1778 12:26:27.432726 ==
1779 12:26:27.432824 DQS Delay:
1780 12:26:27.436254 DQS0 = 0, DQS1 = 0
1781 12:26:27.436357 DQM Delay:
1782 12:26:27.436449 DQM0 = 85, DQM1 = 81
1783 12:26:27.439406 DQ Delay:
1784 12:26:27.442537 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1785 12:26:27.446130 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1786 12:26:27.449372 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1787 12:26:27.452461 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
1788 12:26:27.452546
1789 12:26:27.452613
1790 12:26:27.459157 [DQSOSCAuto] RK0, (LSB)MR18= 0x1527, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 404 ps
1791 12:26:27.462964 CH1 RK0: MR19=606, MR18=1527
1792 12:26:27.469134 CH1_RK0: MR19=0x606, MR18=0x1527, DQSOSC=400, MR23=63, INC=92, DEC=61
1793 12:26:27.469227
1794 12:26:27.472589 ----->DramcWriteLeveling(PI) begin...
1795 12:26:27.472680 ==
1796 12:26:27.476216 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 12:26:27.479491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 12:26:27.479574 ==
1799 12:26:27.482477 Write leveling (Byte 0): 26 => 26
1800 12:26:27.485999 Write leveling (Byte 1): 30 => 30
1801 12:26:27.489008 DramcWriteLeveling(PI) end<-----
1802 12:26:27.489094
1803 12:26:27.489163 ==
1804 12:26:27.492665 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 12:26:27.495686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 12:26:27.495791 ==
1807 12:26:27.499403 [Gating] SW mode calibration
1808 12:26:27.505869 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1809 12:26:27.512460 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1810 12:26:27.515483 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1811 12:26:27.522214 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1812 12:26:27.525369 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1813 12:26:27.529015 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:26:27.535771 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:26:27.538860 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:26:27.542496 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:26:27.548486 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:26:27.552327 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:26:27.555267 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:26:27.559003 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:26:27.565231 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:26:27.568358 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:26:27.571966 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:26:27.578472 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:26:27.582324 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:26:27.585223 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1827 12:26:27.592199 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1828 12:26:27.595093 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:26:27.598338 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:26:27.605203 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:26:27.608218 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:26:27.611719 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:26:27.618256 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:26:27.621774 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:26:27.624758 0 9 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1836 12:26:27.631846 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1837 12:26:27.634972 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 12:26:27.638250 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 12:26:27.644642 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 12:26:27.648297 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 12:26:27.651396 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 12:26:27.658242 0 10 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1843 12:26:27.661227 0 10 4 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 1)
1844 12:26:27.665007 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1845 12:26:27.671252 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:26:27.675013 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 12:26:27.677894 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 12:26:27.684498 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 12:26:27.687485 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 12:26:27.691173 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 12:26:27.697397 0 11 4 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
1852 12:26:27.701011 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
1853 12:26:27.704049 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 12:26:27.711025 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 12:26:27.714052 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 12:26:27.717504 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 12:26:27.724171 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 12:26:27.727730 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1859 12:26:27.730844 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1860 12:26:27.737529 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1861 12:26:27.741208 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:26:27.744270 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:26:27.747394 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:26:27.754239 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:26:27.757871 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:26:27.760897 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:26:27.767281 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:26:27.770987 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:26:27.777071 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:26:27.780785 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:26:27.783695 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 12:26:27.787197 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 12:26:27.794068 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:26:27.797119 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1875 12:26:27.800186 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1876 12:26:27.803700 Total UI for P1: 0, mck2ui 16
1877 12:26:27.807527 best dqsien dly found for B0: ( 0, 14, 0)
1878 12:26:27.813649 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 12:26:27.817331 Total UI for P1: 0, mck2ui 16
1880 12:26:27.820178 best dqsien dly found for B1: ( 0, 14, 6)
1881 12:26:27.823736 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1882 12:26:27.827322 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1883 12:26:27.827413
1884 12:26:27.830111 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1885 12:26:27.833721 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1886 12:26:27.836832 [Gating] SW calibration Done
1887 12:26:27.836923 ==
1888 12:26:27.840428 Dram Type= 6, Freq= 0, CH_1, rank 1
1889 12:26:27.843626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1890 12:26:27.843746 ==
1891 12:26:27.846717 RX Vref Scan: 0
1892 12:26:27.846822
1893 12:26:27.846932 RX Vref 0 -> 0, step: 1
1894 12:26:27.850330
1895 12:26:27.850432 RX Delay -130 -> 252, step: 16
1896 12:26:27.856514 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1897 12:26:27.860156 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1898 12:26:27.863213 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1899 12:26:27.866851 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1900 12:26:27.870065 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1901 12:26:27.876895 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1902 12:26:27.880136 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1903 12:26:27.883068 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1904 12:26:27.886599 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1905 12:26:27.889666 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1906 12:26:27.896826 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1907 12:26:27.900026 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1908 12:26:27.903282 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1909 12:26:27.906224 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1910 12:26:27.909933 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1911 12:26:27.916478 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1912 12:26:27.916598 ==
1913 12:26:27.919538 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 12:26:27.922693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 12:26:27.922784 ==
1916 12:26:27.922853 DQS Delay:
1917 12:26:27.926340 DQS0 = 0, DQS1 = 0
1918 12:26:27.926426 DQM Delay:
1919 12:26:27.929778 DQM0 = 83, DQM1 = 80
1920 12:26:27.929866 DQ Delay:
1921 12:26:27.932878 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1922 12:26:27.936317 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1923 12:26:27.939510 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1924 12:26:27.942636 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1925 12:26:27.942724
1926 12:26:27.942792
1927 12:26:27.942854 ==
1928 12:26:27.946244 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 12:26:27.949397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 12:26:27.952404 ==
1931 12:26:27.952489
1932 12:26:27.952575
1933 12:26:27.952643 TX Vref Scan disable
1934 12:26:27.956106 == TX Byte 0 ==
1935 12:26:27.959185 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1936 12:26:27.965907 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1937 12:26:27.965998 == TX Byte 1 ==
1938 12:26:27.968998 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1939 12:26:27.975807 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1940 12:26:27.975929 ==
1941 12:26:27.978885 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 12:26:27.982671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 12:26:27.982759 ==
1944 12:26:27.995444 TX Vref=22, minBit 0, minWin=27, winSum=443
1945 12:26:27.998515 TX Vref=24, minBit 1, minWin=27, winSum=449
1946 12:26:28.001863 TX Vref=26, minBit 1, minWin=27, winSum=447
1947 12:26:28.005098 TX Vref=28, minBit 6, minWin=27, winSum=455
1948 12:26:28.008784 TX Vref=30, minBit 0, minWin=28, winSum=457
1949 12:26:28.015343 TX Vref=32, minBit 0, minWin=27, winSum=449
1950 12:26:28.018343 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
1951 12:26:28.018434
1952 12:26:28.022049 Final TX Range 1 Vref 30
1953 12:26:28.022125
1954 12:26:28.022188 ==
1955 12:26:28.025070 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 12:26:28.027984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 12:26:28.031673 ==
1958 12:26:28.031795
1959 12:26:28.031901
1960 12:26:28.032006 TX Vref Scan disable
1961 12:26:28.035117 == TX Byte 0 ==
1962 12:26:28.038619 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1963 12:26:28.045250 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1964 12:26:28.045389 == TX Byte 1 ==
1965 12:26:28.048489 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1966 12:26:28.055132 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1967 12:26:28.055257
1968 12:26:28.055374 [DATLAT]
1969 12:26:28.055474 Freq=800, CH1 RK1
1970 12:26:28.055585
1971 12:26:28.058274 DATLAT Default: 0xa
1972 12:26:28.058394 0, 0xFFFF, sum = 0
1973 12:26:28.061970 1, 0xFFFF, sum = 0
1974 12:26:28.064870 2, 0xFFFF, sum = 0
1975 12:26:28.064987 3, 0xFFFF, sum = 0
1976 12:26:28.067990 4, 0xFFFF, sum = 0
1977 12:26:28.068113 5, 0xFFFF, sum = 0
1978 12:26:28.071707 6, 0xFFFF, sum = 0
1979 12:26:28.071833 7, 0xFFFF, sum = 0
1980 12:26:28.074806 8, 0xFFFF, sum = 0
1981 12:26:28.074926 9, 0x0, sum = 1
1982 12:26:28.078486 10, 0x0, sum = 2
1983 12:26:28.078602 11, 0x0, sum = 3
1984 12:26:28.078718 12, 0x0, sum = 4
1985 12:26:28.081622 best_step = 10
1986 12:26:28.081738
1987 12:26:28.081855 ==
1988 12:26:28.084768 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 12:26:28.087866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 12:26:28.087999 ==
1991 12:26:28.091475 RX Vref Scan: 0
1992 12:26:28.091599
1993 12:26:28.094473 RX Vref 0 -> 0, step: 1
1994 12:26:28.094603
1995 12:26:28.094705 RX Delay -95 -> 252, step: 8
1996 12:26:28.101538 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1997 12:26:28.104920 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1998 12:26:28.108661 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1999 12:26:28.111734 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2000 12:26:28.114834 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2001 12:26:28.121495 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2002 12:26:28.125034 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2003 12:26:28.127983 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2004 12:26:28.131620 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2005 12:26:28.138177 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2006 12:26:28.141284 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2007 12:26:28.144962 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2008 12:26:28.147983 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2009 12:26:28.151085 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2010 12:26:28.158214 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2011 12:26:28.161343 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2012 12:26:28.161471 ==
2013 12:26:28.164499 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 12:26:28.167720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 12:26:28.167842 ==
2016 12:26:28.171463 DQS Delay:
2017 12:26:28.171584 DQS0 = 0, DQS1 = 0
2018 12:26:28.171686 DQM Delay:
2019 12:26:28.174567 DQM0 = 87, DQM1 = 83
2020 12:26:28.174695 DQ Delay:
2021 12:26:28.177568 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2022 12:26:28.181320 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2023 12:26:28.184520 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
2024 12:26:28.188154 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2025 12:26:28.188273
2026 12:26:28.188389
2027 12:26:28.197801 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2028 12:26:28.200818 CH1 RK1: MR19=606, MR18=1E39
2029 12:26:28.204274 CH1_RK1: MR19=0x606, MR18=0x1E39, DQSOSC=395, MR23=63, INC=94, DEC=63
2030 12:26:28.207299 [RxdqsGatingPostProcess] freq 800
2031 12:26:28.214062 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2032 12:26:28.217109 Pre-setting of DQS Precalculation
2033 12:26:28.220776 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2034 12:26:28.230875 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2035 12:26:28.237538 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2036 12:26:28.237734
2037 12:26:28.237847
2038 12:26:28.240650 [Calibration Summary] 1600 Mbps
2039 12:26:28.240769 CH 0, Rank 0
2040 12:26:28.244324 SW Impedance : PASS
2041 12:26:28.244446 DUTY Scan : NO K
2042 12:26:28.247197 ZQ Calibration : PASS
2043 12:26:28.250626 Jitter Meter : NO K
2044 12:26:28.250746 CBT Training : PASS
2045 12:26:28.254157 Write leveling : PASS
2046 12:26:28.257261 RX DQS gating : PASS
2047 12:26:28.257377 RX DQ/DQS(RDDQC) : PASS
2048 12:26:28.260243 TX DQ/DQS : PASS
2049 12:26:28.264146 RX DATLAT : PASS
2050 12:26:28.264266 RX DQ/DQS(Engine): PASS
2051 12:26:28.267082 TX OE : NO K
2052 12:26:28.267208 All Pass.
2053 12:26:28.267314
2054 12:26:28.270197 CH 0, Rank 1
2055 12:26:28.270325 SW Impedance : PASS
2056 12:26:28.274070 DUTY Scan : NO K
2057 12:26:28.277270 ZQ Calibration : PASS
2058 12:26:28.277399 Jitter Meter : NO K
2059 12:26:28.280303 CBT Training : PASS
2060 12:26:28.280429 Write leveling : PASS
2061 12:26:28.283580 RX DQS gating : PASS
2062 12:26:28.287090 RX DQ/DQS(RDDQC) : PASS
2063 12:26:28.287217 TX DQ/DQS : PASS
2064 12:26:28.290251 RX DATLAT : PASS
2065 12:26:28.293440 RX DQ/DQS(Engine): PASS
2066 12:26:28.293567 TX OE : NO K
2067 12:26:28.297054 All Pass.
2068 12:26:28.297168
2069 12:26:28.297276 CH 1, Rank 0
2070 12:26:28.300237 SW Impedance : PASS
2071 12:26:28.300355 DUTY Scan : NO K
2072 12:26:28.303771 ZQ Calibration : PASS
2073 12:26:28.306627 Jitter Meter : NO K
2074 12:26:28.306760 CBT Training : PASS
2075 12:26:28.310216 Write leveling : PASS
2076 12:26:28.313307 RX DQS gating : PASS
2077 12:26:28.313436 RX DQ/DQS(RDDQC) : PASS
2078 12:26:28.316725 TX DQ/DQS : PASS
2079 12:26:28.320476 RX DATLAT : PASS
2080 12:26:28.320611 RX DQ/DQS(Engine): PASS
2081 12:26:28.323682 TX OE : NO K
2082 12:26:28.323807 All Pass.
2083 12:26:28.323912
2084 12:26:28.326654 CH 1, Rank 1
2085 12:26:28.326785 SW Impedance : PASS
2086 12:26:28.329863 DUTY Scan : NO K
2087 12:26:28.333281 ZQ Calibration : PASS
2088 12:26:28.333420 Jitter Meter : NO K
2089 12:26:28.336875 CBT Training : PASS
2090 12:26:28.339920 Write leveling : PASS
2091 12:26:28.340040 RX DQS gating : PASS
2092 12:26:28.343074 RX DQ/DQS(RDDQC) : PASS
2093 12:26:28.343155 TX DQ/DQS : PASS
2094 12:26:28.346662 RX DATLAT : PASS
2095 12:26:28.349678 RX DQ/DQS(Engine): PASS
2096 12:26:28.349763 TX OE : NO K
2097 12:26:28.353361 All Pass.
2098 12:26:28.353445
2099 12:26:28.353513 DramC Write-DBI off
2100 12:26:28.356090 PER_BANK_REFRESH: Hybrid Mode
2101 12:26:28.359664 TX_TRACKING: ON
2102 12:26:28.362664 [GetDramInforAfterCalByMRR] Vendor 6.
2103 12:26:28.366377 [GetDramInforAfterCalByMRR] Revision 606.
2104 12:26:28.369561 [GetDramInforAfterCalByMRR] Revision 2 0.
2105 12:26:28.369648 MR0 0x3b3b
2106 12:26:28.369716 MR8 0x5151
2107 12:26:28.376260 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 12:26:28.376355
2109 12:26:28.376423 MR0 0x3b3b
2110 12:26:28.376487 MR8 0x5151
2111 12:26:28.379492 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 12:26:28.379597
2113 12:26:28.389312 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2114 12:26:28.392482 [FAST_K] Save calibration result to emmc
2115 12:26:28.395618 [FAST_K] Save calibration result to emmc
2116 12:26:28.399296 dram_init: config_dvfs: 1
2117 12:26:28.402468 dramc_set_vcore_voltage set vcore to 662500
2118 12:26:28.405968 Read voltage for 1200, 2
2119 12:26:28.406053 Vio18 = 0
2120 12:26:28.409217 Vcore = 662500
2121 12:26:28.409314 Vdram = 0
2122 12:26:28.409384 Vddq = 0
2123 12:26:28.409449 Vmddr = 0
2124 12:26:28.415933 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2125 12:26:28.422322 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2126 12:26:28.422443 MEM_TYPE=3, freq_sel=15
2127 12:26:28.425933 sv_algorithm_assistance_LP4_1600
2128 12:26:28.429128 ============ PULL DRAM RESETB DOWN ============
2129 12:26:28.435721 ========== PULL DRAM RESETB DOWN end =========
2130 12:26:28.438949 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2131 12:26:28.442397 ===================================
2132 12:26:28.445371 LPDDR4 DRAM CONFIGURATION
2133 12:26:28.448591 ===================================
2134 12:26:28.448672 EX_ROW_EN[0] = 0x0
2135 12:26:28.452332 EX_ROW_EN[1] = 0x0
2136 12:26:28.452417 LP4Y_EN = 0x0
2137 12:26:28.455707 WORK_FSP = 0x0
2138 12:26:28.455813 WL = 0x4
2139 12:26:28.459156 RL = 0x4
2140 12:26:28.462001 BL = 0x2
2141 12:26:28.462082 RPST = 0x0
2142 12:26:28.465562 RD_PRE = 0x0
2143 12:26:28.465652 WR_PRE = 0x1
2144 12:26:28.468479 WR_PST = 0x0
2145 12:26:28.468561 DBI_WR = 0x0
2146 12:26:28.472228 DBI_RD = 0x0
2147 12:26:28.472308 OTF = 0x1
2148 12:26:28.475256 ===================================
2149 12:26:28.478990 ===================================
2150 12:26:28.482032 ANA top config
2151 12:26:28.485610 ===================================
2152 12:26:28.485730 DLL_ASYNC_EN = 0
2153 12:26:28.488704 ALL_SLAVE_EN = 0
2154 12:26:28.491839 NEW_RANK_MODE = 1
2155 12:26:28.495046 DLL_IDLE_MODE = 1
2156 12:26:28.495151 LP45_APHY_COMB_EN = 1
2157 12:26:28.498640 TX_ODT_DIS = 1
2158 12:26:28.501834 NEW_8X_MODE = 1
2159 12:26:28.505426 ===================================
2160 12:26:28.508613 ===================================
2161 12:26:28.511526 data_rate = 2400
2162 12:26:28.515395 CKR = 1
2163 12:26:28.518293 DQ_P2S_RATIO = 8
2164 12:26:28.521921 ===================================
2165 12:26:28.522009 CA_P2S_RATIO = 8
2166 12:26:28.525034 DQ_CA_OPEN = 0
2167 12:26:28.528267 DQ_SEMI_OPEN = 0
2168 12:26:28.531968 CA_SEMI_OPEN = 0
2169 12:26:28.535190 CA_FULL_RATE = 0
2170 12:26:28.538784 DQ_CKDIV4_EN = 0
2171 12:26:28.538881 CA_CKDIV4_EN = 0
2172 12:26:28.541754 CA_PREDIV_EN = 0
2173 12:26:28.544762 PH8_DLY = 17
2174 12:26:28.548167 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2175 12:26:28.551811 DQ_AAMCK_DIV = 4
2176 12:26:28.554816 CA_AAMCK_DIV = 4
2177 12:26:28.554906 CA_ADMCK_DIV = 4
2178 12:26:28.558554 DQ_TRACK_CA_EN = 0
2179 12:26:28.561598 CA_PICK = 1200
2180 12:26:28.565165 CA_MCKIO = 1200
2181 12:26:28.568003 MCKIO_SEMI = 0
2182 12:26:28.571561 PLL_FREQ = 2366
2183 12:26:28.574576 DQ_UI_PI_RATIO = 32
2184 12:26:28.574671 CA_UI_PI_RATIO = 0
2185 12:26:28.578188 ===================================
2186 12:26:28.581391 ===================================
2187 12:26:28.585052 memory_type:LPDDR4
2188 12:26:28.588173 GP_NUM : 10
2189 12:26:28.588270 SRAM_EN : 1
2190 12:26:28.591272 MD32_EN : 0
2191 12:26:28.595053 ===================================
2192 12:26:28.598189 [ANA_INIT] >>>>>>>>>>>>>>
2193 12:26:28.601174 <<<<<< [CONFIGURE PHASE]: ANA_TX
2194 12:26:28.604853 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2195 12:26:28.607840 ===================================
2196 12:26:28.607924 data_rate = 2400,PCW = 0X5b00
2197 12:26:28.611586 ===================================
2198 12:26:28.614746 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2199 12:26:28.621316 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 12:26:28.627760 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 12:26:28.631340 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2202 12:26:28.634318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2203 12:26:28.637974 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2204 12:26:28.641482 [ANA_INIT] flow start
2205 12:26:28.644571 [ANA_INIT] PLL >>>>>>>>
2206 12:26:28.644679 [ANA_INIT] PLL <<<<<<<<
2207 12:26:28.647513 [ANA_INIT] MIDPI >>>>>>>>
2208 12:26:28.651046 [ANA_INIT] MIDPI <<<<<<<<
2209 12:26:28.651155 [ANA_INIT] DLL >>>>>>>>
2210 12:26:28.654613 [ANA_INIT] DLL <<<<<<<<
2211 12:26:28.657769 [ANA_INIT] flow end
2212 12:26:28.660835 ============ LP4 DIFF to SE enter ============
2213 12:26:28.664843 ============ LP4 DIFF to SE exit ============
2214 12:26:28.667499 [ANA_INIT] <<<<<<<<<<<<<
2215 12:26:28.670672 [Flow] Enable top DCM control >>>>>
2216 12:26:28.674019 [Flow] Enable top DCM control <<<<<
2217 12:26:28.677568 Enable DLL master slave shuffle
2218 12:26:28.680609 ==============================================================
2219 12:26:28.684264 Gating Mode config
2220 12:26:28.690496 ==============================================================
2221 12:26:28.690617 Config description:
2222 12:26:28.700405 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2223 12:26:28.707124 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2224 12:26:28.710751 SELPH_MODE 0: By rank 1: By Phase
2225 12:26:28.717541 ==============================================================
2226 12:26:28.720839 GAT_TRACK_EN = 1
2227 12:26:28.723601 RX_GATING_MODE = 2
2228 12:26:28.727149 RX_GATING_TRACK_MODE = 2
2229 12:26:28.730869 SELPH_MODE = 1
2230 12:26:28.733976 PICG_EARLY_EN = 1
2231 12:26:28.737013 VALID_LAT_VALUE = 1
2232 12:26:28.740507 ==============================================================
2233 12:26:28.744139 Enter into Gating configuration >>>>
2234 12:26:28.747048 Exit from Gating configuration <<<<
2235 12:26:28.750686 Enter into DVFS_PRE_config >>>>>
2236 12:26:28.763990 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2237 12:26:28.764157 Exit from DVFS_PRE_config <<<<<
2238 12:26:28.767159 Enter into PICG configuration >>>>
2239 12:26:28.770271 Exit from PICG configuration <<<<
2240 12:26:28.773694 [RX_INPUT] configuration >>>>>
2241 12:26:28.777155 [RX_INPUT] configuration <<<<<
2242 12:26:28.783712 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2243 12:26:28.786932 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2244 12:26:28.793631 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2245 12:26:28.800318 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2246 12:26:28.807200 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 12:26:28.813340 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 12:26:28.816390 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2249 12:26:28.819515 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2250 12:26:28.823351 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2251 12:26:28.829836 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2252 12:26:28.833028 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2253 12:26:28.836636 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2254 12:26:28.839790 ===================================
2255 12:26:28.843217 LPDDR4 DRAM CONFIGURATION
2256 12:26:28.846195 ===================================
2257 12:26:28.849341 EX_ROW_EN[0] = 0x0
2258 12:26:28.849431 EX_ROW_EN[1] = 0x0
2259 12:26:28.853002 LP4Y_EN = 0x0
2260 12:26:28.853082 WORK_FSP = 0x0
2261 12:26:28.856136 WL = 0x4
2262 12:26:28.856225 RL = 0x4
2263 12:26:28.859623 BL = 0x2
2264 12:26:28.859711 RPST = 0x0
2265 12:26:28.862564 RD_PRE = 0x0
2266 12:26:28.862686 WR_PRE = 0x1
2267 12:26:28.866338 WR_PST = 0x0
2268 12:26:28.866458 DBI_WR = 0x0
2269 12:26:28.869343 DBI_RD = 0x0
2270 12:26:28.869432 OTF = 0x1
2271 12:26:28.872597 ===================================
2272 12:26:28.879300 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2273 12:26:28.882245 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2274 12:26:28.885645 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2275 12:26:28.889273 ===================================
2276 12:26:28.892439 LPDDR4 DRAM CONFIGURATION
2277 12:26:28.895763 ===================================
2278 12:26:28.898939 EX_ROW_EN[0] = 0x10
2279 12:26:28.899037 EX_ROW_EN[1] = 0x0
2280 12:26:28.902038 LP4Y_EN = 0x0
2281 12:26:28.902120 WORK_FSP = 0x0
2282 12:26:28.905708 WL = 0x4
2283 12:26:28.905836 RL = 0x4
2284 12:26:28.908663 BL = 0x2
2285 12:26:28.908755 RPST = 0x0
2286 12:26:28.912526 RD_PRE = 0x0
2287 12:26:28.912626 WR_PRE = 0x1
2288 12:26:28.915635 WR_PST = 0x0
2289 12:26:28.915739 DBI_WR = 0x0
2290 12:26:28.918637 DBI_RD = 0x0
2291 12:26:28.922388 OTF = 0x1
2292 12:26:28.925452 ===================================
2293 12:26:28.928678 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2294 12:26:28.928788 ==
2295 12:26:28.931776 Dram Type= 6, Freq= 0, CH_0, rank 0
2296 12:26:28.938834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2297 12:26:28.938923 ==
2298 12:26:28.938994 [Duty_Offset_Calibration]
2299 12:26:28.941844 B0:2 B1:0 CA:4
2300 12:26:28.941930
2301 12:26:28.945511 [DutyScan_Calibration_Flow] k_type=0
2302 12:26:28.953860
2303 12:26:28.953960 ==CLK 0==
2304 12:26:28.957411 Final CLK duty delay cell = -4
2305 12:26:28.960565 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2306 12:26:28.963582 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2307 12:26:28.967357 [-4] AVG Duty = 4937%(X100)
2308 12:26:28.967444
2309 12:26:28.970143 CH0 CLK Duty spec in!! Max-Min= 187%
2310 12:26:28.973721 [DutyScan_Calibration_Flow] ====Done====
2311 12:26:28.973809
2312 12:26:28.976726 [DutyScan_Calibration_Flow] k_type=1
2313 12:26:28.992373
2314 12:26:28.992488 ==DQS 0 ==
2315 12:26:28.995828 Final DQS duty delay cell = -4
2316 12:26:28.998894 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2317 12:26:29.002610 [-4] MIN Duty = 4876%(X100), DQS PI = 2
2318 12:26:29.005671 [-4] AVG Duty = 4922%(X100)
2319 12:26:29.005783
2320 12:26:29.005888 ==DQS 1 ==
2321 12:26:29.008790 Final DQS duty delay cell = 0
2322 12:26:29.012520 [0] MAX Duty = 5125%(X100), DQS PI = 6
2323 12:26:29.015562 [0] MIN Duty = 4969%(X100), DQS PI = 14
2324 12:26:29.019213 [0] AVG Duty = 5047%(X100)
2325 12:26:29.019296
2326 12:26:29.022467 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2327 12:26:29.022551
2328 12:26:29.025553 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2329 12:26:29.029193 [DutyScan_Calibration_Flow] ====Done====
2330 12:26:29.029303
2331 12:26:29.032210 [DutyScan_Calibration_Flow] k_type=3
2332 12:26:29.049160
2333 12:26:29.049299 ==DQM 0 ==
2334 12:26:29.052803 Final DQM duty delay cell = 0
2335 12:26:29.055753 [0] MAX Duty = 5094%(X100), DQS PI = 20
2336 12:26:29.059370 [0] MIN Duty = 4844%(X100), DQS PI = 54
2337 12:26:29.062385 [0] AVG Duty = 4969%(X100)
2338 12:26:29.062494
2339 12:26:29.062590 ==DQM 1 ==
2340 12:26:29.065421 Final DQM duty delay cell = 0
2341 12:26:29.069111 [0] MAX Duty = 4969%(X100), DQS PI = 2
2342 12:26:29.072112 [0] MIN Duty = 4876%(X100), DQS PI = 26
2343 12:26:29.075551 [0] AVG Duty = 4922%(X100)
2344 12:26:29.075663
2345 12:26:29.079271 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2346 12:26:29.079361
2347 12:26:29.082266 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2348 12:26:29.085363 [DutyScan_Calibration_Flow] ====Done====
2349 12:26:29.085449
2350 12:26:29.088928 [DutyScan_Calibration_Flow] k_type=2
2351 12:26:29.105244
2352 12:26:29.105366 ==DQ 0 ==
2353 12:26:29.108966 Final DQ duty delay cell = 0
2354 12:26:29.112021 [0] MAX Duty = 5125%(X100), DQS PI = 18
2355 12:26:29.115737 [0] MIN Duty = 4969%(X100), DQS PI = 58
2356 12:26:29.115818 [0] AVG Duty = 5047%(X100)
2357 12:26:29.118787
2358 12:26:29.118872 ==DQ 1 ==
2359 12:26:29.121810 Final DQ duty delay cell = 0
2360 12:26:29.125480 [0] MAX Duty = 5125%(X100), DQS PI = 4
2361 12:26:29.128490 [0] MIN Duty = 4938%(X100), DQS PI = 16
2362 12:26:29.128569 [0] AVG Duty = 5031%(X100)
2363 12:26:29.131558
2364 12:26:29.135165 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2365 12:26:29.135252
2366 12:26:29.138290 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2367 12:26:29.141318 [DutyScan_Calibration_Flow] ====Done====
2368 12:26:29.141405 ==
2369 12:26:29.144559 Dram Type= 6, Freq= 0, CH_1, rank 0
2370 12:26:29.148206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 12:26:29.148320 ==
2372 12:26:29.151689 [Duty_Offset_Calibration]
2373 12:26:29.151796 B0:0 B1:-1 CA:3
2374 12:26:29.151892
2375 12:26:29.154759 [DutyScan_Calibration_Flow] k_type=0
2376 12:26:29.164711
2377 12:26:29.164796 ==CLK 0==
2378 12:26:29.168402 Final CLK duty delay cell = -4
2379 12:26:29.171383 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2380 12:26:29.174530 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2381 12:26:29.178187 [-4] AVG Duty = 4938%(X100)
2382 12:26:29.178277
2383 12:26:29.181127 CH1 CLK Duty spec in!! Max-Min= 124%
2384 12:26:29.184830 [DutyScan_Calibration_Flow] ====Done====
2385 12:26:29.184913
2386 12:26:29.187865 [DutyScan_Calibration_Flow] k_type=1
2387 12:26:29.204164
2388 12:26:29.204299 ==DQS 0 ==
2389 12:26:29.207847 Final DQS duty delay cell = 0
2390 12:26:29.210893 [0] MAX Duty = 5187%(X100), DQS PI = 18
2391 12:26:29.214503 [0] MIN Duty = 4907%(X100), DQS PI = 38
2392 12:26:29.217552 [0] AVG Duty = 5047%(X100)
2393 12:26:29.217630
2394 12:26:29.217704 ==DQS 1 ==
2395 12:26:29.220569 Final DQS duty delay cell = 0
2396 12:26:29.224268 [0] MAX Duty = 5156%(X100), DQS PI = 8
2397 12:26:29.227490 [0] MIN Duty = 5031%(X100), DQS PI = 24
2398 12:26:29.230689 [0] AVG Duty = 5093%(X100)
2399 12:26:29.230805
2400 12:26:29.234191 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2401 12:26:29.234299
2402 12:26:29.237263 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2403 12:26:29.240999 [DutyScan_Calibration_Flow] ====Done====
2404 12:26:29.241081
2405 12:26:29.244125 [DutyScan_Calibration_Flow] k_type=3
2406 12:26:29.260872
2407 12:26:29.260978 ==DQM 0 ==
2408 12:26:29.263977 Final DQM duty delay cell = 0
2409 12:26:29.267557 [0] MAX Duty = 5031%(X100), DQS PI = 28
2410 12:26:29.270599 [0] MIN Duty = 4782%(X100), DQS PI = 38
2411 12:26:29.274386 [0] AVG Duty = 4906%(X100)
2412 12:26:29.274490
2413 12:26:29.274565 ==DQM 1 ==
2414 12:26:29.277455 Final DQM duty delay cell = 0
2415 12:26:29.280567 [0] MAX Duty = 4969%(X100), DQS PI = 32
2416 12:26:29.283708 [0] MIN Duty = 4844%(X100), DQS PI = 0
2417 12:26:29.287150 [0] AVG Duty = 4906%(X100)
2418 12:26:29.287234
2419 12:26:29.290722 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2420 12:26:29.290811
2421 12:26:29.293861 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2422 12:26:29.297273 [DutyScan_Calibration_Flow] ====Done====
2423 12:26:29.297350
2424 12:26:29.300228 [DutyScan_Calibration_Flow] k_type=2
2425 12:26:29.316391
2426 12:26:29.316490 ==DQ 0 ==
2427 12:26:29.319972 Final DQ duty delay cell = -4
2428 12:26:29.323047 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2429 12:26:29.326680 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2430 12:26:29.329902 [-4] AVG Duty = 4953%(X100)
2431 12:26:29.329988
2432 12:26:29.330056 ==DQ 1 ==
2433 12:26:29.332856 Final DQ duty delay cell = 0
2434 12:26:29.335996 [0] MAX Duty = 5031%(X100), DQS PI = 34
2435 12:26:29.339539 [0] MIN Duty = 4844%(X100), DQS PI = 62
2436 12:26:29.343291 [0] AVG Duty = 4937%(X100)
2437 12:26:29.343385
2438 12:26:29.346298 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2439 12:26:29.346386
2440 12:26:29.349955 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2441 12:26:29.352919 [DutyScan_Calibration_Flow] ====Done====
2442 12:26:29.356007 nWR fixed to 30
2443 12:26:29.359655 [ModeRegInit_LP4] CH0 RK0
2444 12:26:29.359742 [ModeRegInit_LP4] CH0 RK1
2445 12:26:29.362608 [ModeRegInit_LP4] CH1 RK0
2446 12:26:29.366104 [ModeRegInit_LP4] CH1 RK1
2447 12:26:29.366191 match AC timing 7
2448 12:26:29.372518 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2449 12:26:29.375768 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2450 12:26:29.379395 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2451 12:26:29.386181 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2452 12:26:29.389181 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2453 12:26:29.389289 ==
2454 12:26:29.392762 Dram Type= 6, Freq= 0, CH_0, rank 0
2455 12:26:29.395860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2456 12:26:29.395965 ==
2457 12:26:29.402492 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2458 12:26:29.409025 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2459 12:26:29.416957 [CA 0] Center 39 (9~70) winsize 62
2460 12:26:29.419999 [CA 1] Center 39 (9~70) winsize 62
2461 12:26:29.423544 [CA 2] Center 35 (5~66) winsize 62
2462 12:26:29.426530 [CA 3] Center 35 (5~66) winsize 62
2463 12:26:29.430310 [CA 4] Center 33 (3~64) winsize 62
2464 12:26:29.433459 [CA 5] Center 33 (3~63) winsize 61
2465 12:26:29.433547
2466 12:26:29.436467 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2467 12:26:29.436572
2468 12:26:29.440199 [CATrainingPosCal] consider 1 rank data
2469 12:26:29.443291 u2DelayCellTimex100 = 270/100 ps
2470 12:26:29.446389 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2471 12:26:29.453301 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2472 12:26:29.456248 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2473 12:26:29.459998 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2474 12:26:29.463070 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2475 12:26:29.466600 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2476 12:26:29.466708
2477 12:26:29.469470 CA PerBit enable=1, Macro0, CA PI delay=33
2478 12:26:29.469560
2479 12:26:29.472970 [CBTSetCACLKResult] CA Dly = 33
2480 12:26:29.473053 CS Dly: 7 (0~38)
2481 12:26:29.476264 ==
2482 12:26:29.479982 Dram Type= 6, Freq= 0, CH_0, rank 1
2483 12:26:29.482994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2484 12:26:29.483080 ==
2485 12:26:29.489645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2486 12:26:29.492680 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2487 12:26:29.502472 [CA 0] Center 39 (9~70) winsize 62
2488 12:26:29.506104 [CA 1] Center 39 (9~70) winsize 62
2489 12:26:29.509106 [CA 2] Center 35 (5~66) winsize 62
2490 12:26:29.512725 [CA 3] Center 35 (5~66) winsize 62
2491 12:26:29.515646 [CA 4] Center 34 (4~65) winsize 62
2492 12:26:29.518853 [CA 5] Center 33 (3~64) winsize 62
2493 12:26:29.518931
2494 12:26:29.522618 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2495 12:26:29.522707
2496 12:26:29.525687 [CATrainingPosCal] consider 2 rank data
2497 12:26:29.529142 u2DelayCellTimex100 = 270/100 ps
2498 12:26:29.532391 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2499 12:26:29.539299 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2500 12:26:29.542258 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2501 12:26:29.546030 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2502 12:26:29.549238 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2503 12:26:29.552216 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2504 12:26:29.552297
2505 12:26:29.555827 CA PerBit enable=1, Macro0, CA PI delay=33
2506 12:26:29.555940
2507 12:26:29.559031 [CBTSetCACLKResult] CA Dly = 33
2508 12:26:29.559138 CS Dly: 8 (0~41)
2509 12:26:29.559236
2510 12:26:29.562632 ----->DramcWriteLeveling(PI) begin...
2511 12:26:29.565822 ==
2512 12:26:29.568834 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 12:26:29.572366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 12:26:29.572449 ==
2515 12:26:29.575974 Write leveling (Byte 0): 32 => 32
2516 12:26:29.578954 Write leveling (Byte 1): 27 => 27
2517 12:26:29.582719 DramcWriteLeveling(PI) end<-----
2518 12:26:29.582839
2519 12:26:29.582937 ==
2520 12:26:29.585934 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 12:26:29.589199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 12:26:29.589287 ==
2523 12:26:29.592207 [Gating] SW mode calibration
2524 12:26:29.598945 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2525 12:26:29.605325 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2526 12:26:29.609026 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2527 12:26:29.611927 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2528 12:26:29.618531 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 12:26:29.622211 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 12:26:29.625481 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 12:26:29.632153 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 12:26:29.635213 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2533 12:26:29.638357 0 15 28 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
2534 12:26:29.645078 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
2535 12:26:29.648722 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2536 12:26:29.651811 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 12:26:29.658608 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 12:26:29.661668 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 12:26:29.665391 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 12:26:29.668344 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2541 12:26:29.675118 1 0 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
2542 12:26:29.678175 1 1 0 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2543 12:26:29.681582 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2544 12:26:29.688146 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 12:26:29.691843 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 12:26:29.694945 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 12:26:29.701541 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 12:26:29.704556 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 12:26:29.708102 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2550 12:26:29.714764 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2551 12:26:29.718405 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2552 12:26:29.721316 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:26:29.728162 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 12:26:29.731283 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:26:29.734777 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:26:29.741028 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:26:29.744126 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:26:29.747839 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:26:29.754147 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:26:29.757727 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:26:29.760640 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 12:26:29.767504 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 12:26:29.771223 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 12:26:29.774314 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:26:29.780983 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2566 12:26:29.781083 Total UI for P1: 0, mck2ui 16
2567 12:26:29.787530 best dqsien dly found for B0: ( 1, 3, 26)
2568 12:26:29.790544 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2569 12:26:29.794092 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2570 12:26:29.800607 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 12:26:29.800694 Total UI for P1: 0, mck2ui 16
2572 12:26:29.807335 best dqsien dly found for B1: ( 1, 4, 0)
2573 12:26:29.810841 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2574 12:26:29.813986 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2575 12:26:29.814093
2576 12:26:29.816963 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2577 12:26:29.820480 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2578 12:26:29.824095 [Gating] SW calibration Done
2579 12:26:29.824178 ==
2580 12:26:29.827052 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 12:26:29.830176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 12:26:29.830256 ==
2583 12:26:29.833803 RX Vref Scan: 0
2584 12:26:29.833890
2585 12:26:29.833958 RX Vref 0 -> 0, step: 1
2586 12:26:29.834021
2587 12:26:29.837040 RX Delay -40 -> 252, step: 8
2588 12:26:29.840193 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2589 12:26:29.846867 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2590 12:26:29.849968 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2591 12:26:29.853632 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2592 12:26:29.856783 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2593 12:26:29.860367 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2594 12:26:29.867005 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2595 12:26:29.870160 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2596 12:26:29.873657 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2597 12:26:29.876958 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2598 12:26:29.879785 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2599 12:26:29.886615 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2600 12:26:29.890122 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2601 12:26:29.893289 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2602 12:26:29.896354 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2603 12:26:29.902861 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2604 12:26:29.902954 ==
2605 12:26:29.906519 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 12:26:29.909573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 12:26:29.909661 ==
2608 12:26:29.909729 DQS Delay:
2609 12:26:29.913321 DQS0 = 0, DQS1 = 0
2610 12:26:29.913440 DQM Delay:
2611 12:26:29.916274 DQM0 = 117, DQM1 = 107
2612 12:26:29.916367 DQ Delay:
2613 12:26:29.919864 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2614 12:26:29.922863 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2615 12:26:29.926539 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2616 12:26:29.929383 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2617 12:26:29.929489
2618 12:26:29.929594
2619 12:26:29.933051 ==
2620 12:26:29.936093 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 12:26:29.939612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 12:26:29.939728 ==
2623 12:26:29.939825
2624 12:26:29.939925
2625 12:26:29.942961 TX Vref Scan disable
2626 12:26:29.943041 == TX Byte 0 ==
2627 12:26:29.945933 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2628 12:26:29.952994 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2629 12:26:29.953075 == TX Byte 1 ==
2630 12:26:29.956122 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2631 12:26:29.962903 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2632 12:26:29.963037 ==
2633 12:26:29.966041 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 12:26:29.969136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 12:26:29.969220 ==
2636 12:26:29.981546 TX Vref=22, minBit 3, minWin=25, winSum=411
2637 12:26:29.985189 TX Vref=24, minBit 1, minWin=25, winSum=415
2638 12:26:29.988196 TX Vref=26, minBit 10, minWin=25, winSum=422
2639 12:26:29.991922 TX Vref=28, minBit 5, minWin=26, winSum=429
2640 12:26:29.994856 TX Vref=30, minBit 4, minWin=26, winSum=428
2641 12:26:30.001797 TX Vref=32, minBit 5, minWin=26, winSum=431
2642 12:26:30.004716 [TxChooseVref] Worse bit 5, Min win 26, Win sum 431, Final Vref 32
2643 12:26:30.004827
2644 12:26:30.008397 Final TX Range 1 Vref 32
2645 12:26:30.008513
2646 12:26:30.008630 ==
2647 12:26:30.011334 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 12:26:30.014616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 12:26:30.018114 ==
2650 12:26:30.018214
2651 12:26:30.018319
2652 12:26:30.018423 TX Vref Scan disable
2653 12:26:30.021618 == TX Byte 0 ==
2654 12:26:30.024764 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2655 12:26:30.031756 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2656 12:26:30.031874 == TX Byte 1 ==
2657 12:26:30.034772 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2658 12:26:30.041476 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2659 12:26:30.041613
2660 12:26:30.041714 [DATLAT]
2661 12:26:30.041808 Freq=1200, CH0 RK0
2662 12:26:30.041900
2663 12:26:30.044655 DATLAT Default: 0xd
2664 12:26:30.047801 0, 0xFFFF, sum = 0
2665 12:26:30.047896 1, 0xFFFF, sum = 0
2666 12:26:30.051672 2, 0xFFFF, sum = 0
2667 12:26:30.051762 3, 0xFFFF, sum = 0
2668 12:26:30.054768 4, 0xFFFF, sum = 0
2669 12:26:30.054859 5, 0xFFFF, sum = 0
2670 12:26:30.057761 6, 0xFFFF, sum = 0
2671 12:26:30.057845 7, 0xFFFF, sum = 0
2672 12:26:30.061368 8, 0xFFFF, sum = 0
2673 12:26:30.061476 9, 0xFFFF, sum = 0
2674 12:26:30.064476 10, 0xFFFF, sum = 0
2675 12:26:30.064559 11, 0xFFFF, sum = 0
2676 12:26:30.067651 12, 0x0, sum = 1
2677 12:26:30.067737 13, 0x0, sum = 2
2678 12:26:30.071390 14, 0x0, sum = 3
2679 12:26:30.071478 15, 0x0, sum = 4
2680 12:26:30.074513 best_step = 13
2681 12:26:30.074627
2682 12:26:30.074710 ==
2683 12:26:30.078236 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 12:26:30.081278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 12:26:30.081398 ==
2686 12:26:30.081475 RX Vref Scan: 1
2687 12:26:30.084425
2688 12:26:30.084504 Set Vref Range= 32 -> 127
2689 12:26:30.084570
2690 12:26:30.087465 RX Vref 32 -> 127, step: 1
2691 12:26:30.087571
2692 12:26:30.091089 RX Delay -21 -> 252, step: 4
2693 12:26:30.091170
2694 12:26:30.094314 Set Vref, RX VrefLevel [Byte0]: 32
2695 12:26:30.097864 [Byte1]: 32
2696 12:26:30.097977
2697 12:26:30.101742 Set Vref, RX VrefLevel [Byte0]: 33
2698 12:26:30.104021 [Byte1]: 33
2699 12:26:30.108029
2700 12:26:30.108130 Set Vref, RX VrefLevel [Byte0]: 34
2701 12:26:30.111478 [Byte1]: 34
2702 12:26:30.115829
2703 12:26:30.115918 Set Vref, RX VrefLevel [Byte0]: 35
2704 12:26:30.119521 [Byte1]: 35
2705 12:26:30.123867
2706 12:26:30.123980 Set Vref, RX VrefLevel [Byte0]: 36
2707 12:26:30.126961 [Byte1]: 36
2708 12:26:30.131673
2709 12:26:30.131767 Set Vref, RX VrefLevel [Byte0]: 37
2710 12:26:30.135264 [Byte1]: 37
2711 12:26:30.140009
2712 12:26:30.140132 Set Vref, RX VrefLevel [Byte0]: 38
2713 12:26:30.143233 [Byte1]: 38
2714 12:26:30.147548
2715 12:26:30.147644 Set Vref, RX VrefLevel [Byte0]: 39
2716 12:26:30.151207 [Byte1]: 39
2717 12:26:30.155551
2718 12:26:30.155646 Set Vref, RX VrefLevel [Byte0]: 40
2719 12:26:30.158825 [Byte1]: 40
2720 12:26:30.163857
2721 12:26:30.163976 Set Vref, RX VrefLevel [Byte0]: 41
2722 12:26:30.166779 [Byte1]: 41
2723 12:26:30.171687
2724 12:26:30.171778 Set Vref, RX VrefLevel [Byte0]: 42
2725 12:26:30.174768 [Byte1]: 42
2726 12:26:30.179142
2727 12:26:30.179231 Set Vref, RX VrefLevel [Byte0]: 43
2728 12:26:30.182761 [Byte1]: 43
2729 12:26:30.187533
2730 12:26:30.187622 Set Vref, RX VrefLevel [Byte0]: 44
2731 12:26:30.190499 [Byte1]: 44
2732 12:26:30.194963
2733 12:26:30.195050 Set Vref, RX VrefLevel [Byte0]: 45
2734 12:26:30.198546 [Byte1]: 45
2735 12:26:30.203416
2736 12:26:30.203504 Set Vref, RX VrefLevel [Byte0]: 46
2737 12:26:30.206476 [Byte1]: 46
2738 12:26:30.211335
2739 12:26:30.211423 Set Vref, RX VrefLevel [Byte0]: 47
2740 12:26:30.214338 [Byte1]: 47
2741 12:26:30.218756
2742 12:26:30.218844 Set Vref, RX VrefLevel [Byte0]: 48
2743 12:26:30.222561 [Byte1]: 48
2744 12:26:30.226808
2745 12:26:30.226893 Set Vref, RX VrefLevel [Byte0]: 49
2746 12:26:30.230556 [Byte1]: 49
2747 12:26:30.234890
2748 12:26:30.234978 Set Vref, RX VrefLevel [Byte0]: 50
2749 12:26:30.238350 [Byte1]: 50
2750 12:26:30.243023
2751 12:26:30.243110 Set Vref, RX VrefLevel [Byte0]: 51
2752 12:26:30.245856 [Byte1]: 51
2753 12:26:30.250730
2754 12:26:30.250809 Set Vref, RX VrefLevel [Byte0]: 52
2755 12:26:30.253790 [Byte1]: 52
2756 12:26:30.258832
2757 12:26:30.258910 Set Vref, RX VrefLevel [Byte0]: 53
2758 12:26:30.261794 [Byte1]: 53
2759 12:26:30.266673
2760 12:26:30.266782 Set Vref, RX VrefLevel [Byte0]: 54
2761 12:26:30.269840 [Byte1]: 54
2762 12:26:30.274835
2763 12:26:30.274951 Set Vref, RX VrefLevel [Byte0]: 55
2764 12:26:30.277788 [Byte1]: 55
2765 12:26:30.282785
2766 12:26:30.282909 Set Vref, RX VrefLevel [Byte0]: 56
2767 12:26:30.285818 [Byte1]: 56
2768 12:26:30.290818
2769 12:26:30.290919 Set Vref, RX VrefLevel [Byte0]: 57
2770 12:26:30.293859 [Byte1]: 57
2771 12:26:30.298319
2772 12:26:30.298404 Set Vref, RX VrefLevel [Byte0]: 58
2773 12:26:30.301960 [Byte1]: 58
2774 12:26:30.306232
2775 12:26:30.306315 Set Vref, RX VrefLevel [Byte0]: 59
2776 12:26:30.309579 [Byte1]: 59
2777 12:26:30.313870
2778 12:26:30.313953 Set Vref, RX VrefLevel [Byte0]: 60
2779 12:26:30.317544 [Byte1]: 60
2780 12:26:30.322281
2781 12:26:30.322364 Set Vref, RX VrefLevel [Byte0]: 61
2782 12:26:30.325387 [Byte1]: 61
2783 12:26:30.329669
2784 12:26:30.329752 Set Vref, RX VrefLevel [Byte0]: 62
2785 12:26:30.333368 [Byte1]: 62
2786 12:26:30.337863
2787 12:26:30.337946 Set Vref, RX VrefLevel [Byte0]: 63
2788 12:26:30.341377 [Byte1]: 63
2789 12:26:30.345869
2790 12:26:30.345952 Set Vref, RX VrefLevel [Byte0]: 64
2791 12:26:30.348880 [Byte1]: 64
2792 12:26:30.353578
2793 12:26:30.353671 Set Vref, RX VrefLevel [Byte0]: 65
2794 12:26:30.357420 [Byte1]: 65
2795 12:26:30.361635
2796 12:26:30.361719 Set Vref, RX VrefLevel [Byte0]: 66
2797 12:26:30.364795 [Byte1]: 66
2798 12:26:30.369765
2799 12:26:30.369849 Set Vref, RX VrefLevel [Byte0]: 67
2800 12:26:30.372648 [Byte1]: 67
2801 12:26:30.377612
2802 12:26:30.377697 Set Vref, RX VrefLevel [Byte0]: 68
2803 12:26:30.380640 [Byte1]: 68
2804 12:26:30.385581
2805 12:26:30.385665 Set Vref, RX VrefLevel [Byte0]: 69
2806 12:26:30.388567 [Byte1]: 69
2807 12:26:30.393500
2808 12:26:30.393585 Final RX Vref Byte 0 = 51 to rank0
2809 12:26:30.396716 Final RX Vref Byte 1 = 58 to rank0
2810 12:26:30.399852 Final RX Vref Byte 0 = 51 to rank1
2811 12:26:30.403409 Final RX Vref Byte 1 = 58 to rank1==
2812 12:26:30.406664 Dram Type= 6, Freq= 0, CH_0, rank 0
2813 12:26:30.410134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2814 12:26:30.413594 ==
2815 12:26:30.413695 DQS Delay:
2816 12:26:30.413796 DQS0 = 0, DQS1 = 0
2817 12:26:30.416518 DQM Delay:
2818 12:26:30.416600 DQM0 = 117, DQM1 = 105
2819 12:26:30.420004 DQ Delay:
2820 12:26:30.423081 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =114
2821 12:26:30.426571 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2822 12:26:30.430400 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2823 12:26:30.433425 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2824 12:26:30.433510
2825 12:26:30.433576
2826 12:26:30.440140 [DQSOSCAuto] RK0, (LSB)MR18= 0xfb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2827 12:26:30.443393 CH0 RK0: MR19=403, MR18=FB
2828 12:26:30.450301 CH0_RK0: MR19=0x403, MR18=0xFB, DQSOSC=410, MR23=63, INC=39, DEC=26
2829 12:26:30.450387
2830 12:26:30.453088 ----->DramcWriteLeveling(PI) begin...
2831 12:26:30.453186 ==
2832 12:26:30.456675 Dram Type= 6, Freq= 0, CH_0, rank 1
2833 12:26:30.460539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 12:26:30.460623 ==
2835 12:26:30.463522 Write leveling (Byte 0): 32 => 32
2836 12:26:30.466499 Write leveling (Byte 1): 26 => 26
2837 12:26:30.470287 DramcWriteLeveling(PI) end<-----
2838 12:26:30.470371
2839 12:26:30.470438 ==
2840 12:26:30.473392 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 12:26:30.476558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2842 12:26:30.480234 ==
2843 12:26:30.480344 [Gating] SW mode calibration
2844 12:26:30.486724 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2845 12:26:30.493493 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2846 12:26:30.496639 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2847 12:26:30.503197 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2848 12:26:30.506895 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 12:26:30.510179 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 12:26:30.516641 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 12:26:30.519637 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 12:26:30.523272 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2853 12:26:30.529887 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
2854 12:26:30.533107 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2855 12:26:30.536842 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2856 12:26:30.542888 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 12:26:30.546445 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 12:26:30.549518 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 12:26:30.556273 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 12:26:30.559715 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2861 12:26:30.562850 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2862 12:26:30.569739 1 1 0 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
2863 12:26:30.572823 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 12:26:30.575928 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 12:26:30.582685 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 12:26:30.586288 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 12:26:30.589229 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 12:26:30.596267 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2869 12:26:30.599498 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2870 12:26:30.602415 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2871 12:26:30.609181 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 12:26:30.612311 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 12:26:30.616131 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 12:26:30.619084 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 12:26:30.625602 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 12:26:30.629236 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 12:26:30.635439 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 12:26:30.639119 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 12:26:30.642040 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 12:26:30.645645 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 12:26:30.652536 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 12:26:30.655605 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 12:26:30.658468 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 12:26:30.665121 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2885 12:26:30.668585 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2886 12:26:30.671624 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2887 12:26:30.675390 Total UI for P1: 0, mck2ui 16
2888 12:26:30.678482 best dqsien dly found for B0: ( 1, 3, 26)
2889 12:26:30.685076 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 12:26:30.688274 Total UI for P1: 0, mck2ui 16
2891 12:26:30.691881 best dqsien dly found for B1: ( 1, 4, 0)
2892 12:26:30.695347 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2893 12:26:30.698536 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2894 12:26:30.698620
2895 12:26:30.701699 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2896 12:26:30.704756 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2897 12:26:30.708581 [Gating] SW calibration Done
2898 12:26:30.708658 ==
2899 12:26:30.711846 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 12:26:30.714887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2901 12:26:30.714970 ==
2902 12:26:30.718503 RX Vref Scan: 0
2903 12:26:30.718577
2904 12:26:30.718652 RX Vref 0 -> 0, step: 1
2905 12:26:30.718720
2906 12:26:30.722090 RX Delay -40 -> 252, step: 8
2907 12:26:30.728599 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2908 12:26:30.731620 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2909 12:26:30.734711 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2910 12:26:30.737883 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2911 12:26:30.741460 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2912 12:26:30.748304 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2913 12:26:30.751275 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2914 12:26:30.754896 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2915 12:26:30.758019 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2916 12:26:30.761157 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2917 12:26:30.764621 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2918 12:26:30.771244 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2919 12:26:30.774795 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2920 12:26:30.777861 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2921 12:26:30.781499 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2922 12:26:30.788116 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2923 12:26:30.788202 ==
2924 12:26:30.791186 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 12:26:30.794831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 12:26:30.794919 ==
2927 12:26:30.794988 DQS Delay:
2928 12:26:30.797847 DQS0 = 0, DQS1 = 0
2929 12:26:30.797929 DQM Delay:
2930 12:26:30.801594 DQM0 = 116, DQM1 = 108
2931 12:26:30.801674 DQ Delay:
2932 12:26:30.804547 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2933 12:26:30.807798 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2934 12:26:30.811508 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =103
2935 12:26:30.814512 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2936 12:26:30.814624
2937 12:26:30.814718
2938 12:26:30.814808 ==
2939 12:26:30.817668 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 12:26:30.824621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 12:26:30.824704 ==
2942 12:26:30.824771
2943 12:26:30.824830
2944 12:26:30.824888 TX Vref Scan disable
2945 12:26:30.828175 == TX Byte 0 ==
2946 12:26:30.831720 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2947 12:26:30.835084 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2948 12:26:30.838258 == TX Byte 1 ==
2949 12:26:30.841371 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2950 12:26:30.847868 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2951 12:26:30.847994 ==
2952 12:26:30.851552 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 12:26:30.854540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 12:26:30.854624 ==
2955 12:26:30.866437 TX Vref=22, minBit 4, minWin=25, winSum=420
2956 12:26:30.870088 TX Vref=24, minBit 13, minWin=25, winSum=421
2957 12:26:30.873295 TX Vref=26, minBit 4, minWin=26, winSum=426
2958 12:26:30.876841 TX Vref=28, minBit 8, minWin=26, winSum=430
2959 12:26:30.879799 TX Vref=30, minBit 10, minWin=26, winSum=429
2960 12:26:30.886471 TX Vref=32, minBit 8, minWin=26, winSum=428
2961 12:26:30.889679 [TxChooseVref] Worse bit 8, Min win 26, Win sum 430, Final Vref 28
2962 12:26:30.889768
2963 12:26:30.893441 Final TX Range 1 Vref 28
2964 12:26:30.893530
2965 12:26:30.893597 ==
2966 12:26:30.896567 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 12:26:30.900021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 12:26:30.903004 ==
2969 12:26:30.903110
2970 12:26:30.903204
2971 12:26:30.903279 TX Vref Scan disable
2972 12:26:30.906713 == TX Byte 0 ==
2973 12:26:30.909794 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2974 12:26:30.916642 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2975 12:26:30.916758 == TX Byte 1 ==
2976 12:26:30.919631 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2977 12:26:30.926479 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2978 12:26:30.926589
2979 12:26:30.926685 [DATLAT]
2980 12:26:30.926777 Freq=1200, CH0 RK1
2981 12:26:30.926869
2982 12:26:30.929484 DATLAT Default: 0xd
2983 12:26:30.929585 0, 0xFFFF, sum = 0
2984 12:26:30.933211 1, 0xFFFF, sum = 0
2985 12:26:30.936319 2, 0xFFFF, sum = 0
2986 12:26:30.936404 3, 0xFFFF, sum = 0
2987 12:26:30.939783 4, 0xFFFF, sum = 0
2988 12:26:30.939891 5, 0xFFFF, sum = 0
2989 12:26:30.943055 6, 0xFFFF, sum = 0
2990 12:26:30.943148 7, 0xFFFF, sum = 0
2991 12:26:30.946032 8, 0xFFFF, sum = 0
2992 12:26:30.946151 9, 0xFFFF, sum = 0
2993 12:26:30.949785 10, 0xFFFF, sum = 0
2994 12:26:30.949886 11, 0xFFFF, sum = 0
2995 12:26:30.952881 12, 0x0, sum = 1
2996 12:26:30.952996 13, 0x0, sum = 2
2997 12:26:30.955814 14, 0x0, sum = 3
2998 12:26:30.955918 15, 0x0, sum = 4
2999 12:26:30.959363 best_step = 13
3000 12:26:30.959446
3001 12:26:30.959513 ==
3002 12:26:30.963021 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 12:26:30.966238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 12:26:30.966322 ==
3005 12:26:30.966388 RX Vref Scan: 0
3006 12:26:30.969210
3007 12:26:30.969293 RX Vref 0 -> 0, step: 1
3008 12:26:30.969360
3009 12:26:30.972839 RX Delay -21 -> 252, step: 4
3010 12:26:30.979502 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3011 12:26:30.982543 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3012 12:26:30.986109 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3013 12:26:30.989266 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3014 12:26:30.992455 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3015 12:26:30.999123 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3016 12:26:31.002764 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3017 12:26:31.006157 iDelay=195, Bit 7, Center 120 (55 ~ 186) 132
3018 12:26:31.009193 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3019 12:26:31.012344 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3020 12:26:31.015899 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3021 12:26:31.022615 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3022 12:26:31.025741 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3023 12:26:31.029417 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3024 12:26:31.032396 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3025 12:26:31.039032 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3026 12:26:31.039163 ==
3027 12:26:31.042495 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 12:26:31.045671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 12:26:31.045750 ==
3030 12:26:31.045828 DQS Delay:
3031 12:26:31.048726 DQS0 = 0, DQS1 = 0
3032 12:26:31.048877 DQM Delay:
3033 12:26:31.052226 DQM0 = 115, DQM1 = 106
3034 12:26:31.052302 DQ Delay:
3035 12:26:31.055348 DQ0 =114, DQ1 =116, DQ2 =112, DQ3 =112
3036 12:26:31.058992 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =120
3037 12:26:31.061972 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =100
3038 12:26:31.065081 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =112
3039 12:26:31.065160
3040 12:26:31.065226
3041 12:26:31.075343 [DQSOSCAuto] RK1, (LSB)MR18= 0xfaf8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
3042 12:26:31.078347 CH0 RK1: MR19=303, MR18=FAF8
3043 12:26:31.085102 CH0_RK1: MR19=0x303, MR18=0xFAF8, DQSOSC=412, MR23=63, INC=38, DEC=25
3044 12:26:31.085264 [RxdqsGatingPostProcess] freq 1200
3045 12:26:31.092061 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3046 12:26:31.095160 best DQS0 dly(2T, 0.5T) = (0, 11)
3047 12:26:31.098681 best DQS1 dly(2T, 0.5T) = (0, 12)
3048 12:26:31.101783 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3049 12:26:31.104907 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3050 12:26:31.108572 best DQS0 dly(2T, 0.5T) = (0, 11)
3051 12:26:31.111627 best DQS1 dly(2T, 0.5T) = (0, 12)
3052 12:26:31.114767 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3053 12:26:31.118588 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3054 12:26:31.121806 Pre-setting of DQS Precalculation
3055 12:26:31.124796 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3056 12:26:31.124898 ==
3057 12:26:31.127999 Dram Type= 6, Freq= 0, CH_1, rank 0
3058 12:26:31.131669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 12:26:31.134800 ==
3060 12:26:31.137787 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3061 12:26:31.144536 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3062 12:26:31.153170 [CA 0] Center 38 (8~68) winsize 61
3063 12:26:31.156246 [CA 1] Center 37 (7~68) winsize 62
3064 12:26:31.159368 [CA 2] Center 35 (5~65) winsize 61
3065 12:26:31.163030 [CA 3] Center 34 (4~64) winsize 61
3066 12:26:31.165872 [CA 4] Center 34 (4~64) winsize 61
3067 12:26:31.169598 [CA 5] Center 34 (4~64) winsize 61
3068 12:26:31.169714
3069 12:26:31.172629 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3070 12:26:31.172723
3071 12:26:31.176186 [CATrainingPosCal] consider 1 rank data
3072 12:26:31.179163 u2DelayCellTimex100 = 270/100 ps
3073 12:26:31.182912 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3074 12:26:31.189112 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3075 12:26:31.192654 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3076 12:26:31.196139 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3077 12:26:31.199318 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3078 12:26:31.202456 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3079 12:26:31.202546
3080 12:26:31.206228 CA PerBit enable=1, Macro0, CA PI delay=34
3081 12:26:31.206316
3082 12:26:31.209173 [CBTSetCACLKResult] CA Dly = 34
3083 12:26:31.209261 CS Dly: 5 (0~36)
3084 12:26:31.213020 ==
3085 12:26:31.216051 Dram Type= 6, Freq= 0, CH_1, rank 1
3086 12:26:31.219256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 12:26:31.219343 ==
3088 12:26:31.222349 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3089 12:26:31.229339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3090 12:26:31.238478 [CA 0] Center 37 (7~68) winsize 62
3091 12:26:31.241513 [CA 1] Center 38 (8~68) winsize 61
3092 12:26:31.245145 [CA 2] Center 35 (5~65) winsize 61
3093 12:26:31.248353 [CA 3] Center 34 (4~64) winsize 61
3094 12:26:31.251922 [CA 4] Center 34 (4~64) winsize 61
3095 12:26:31.254985 [CA 5] Center 33 (3~64) winsize 62
3096 12:26:31.255074
3097 12:26:31.258530 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3098 12:26:31.258617
3099 12:26:31.261640 [CATrainingPosCal] consider 2 rank data
3100 12:26:31.265224 u2DelayCellTimex100 = 270/100 ps
3101 12:26:31.268245 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3102 12:26:31.274868 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3103 12:26:31.278673 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3104 12:26:31.281629 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3105 12:26:31.285231 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3106 12:26:31.288276 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3107 12:26:31.288393
3108 12:26:31.291888 CA PerBit enable=1, Macro0, CA PI delay=34
3109 12:26:31.291978
3110 12:26:31.294958 [CBTSetCACLKResult] CA Dly = 34
3111 12:26:31.295082 CS Dly: 6 (0~38)
3112 12:26:31.295188
3113 12:26:31.301757 ----->DramcWriteLeveling(PI) begin...
3114 12:26:31.301850 ==
3115 12:26:31.304672 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 12:26:31.308288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 12:26:31.308416 ==
3118 12:26:31.311352 Write leveling (Byte 0): 27 => 27
3119 12:26:31.314954 Write leveling (Byte 1): 27 => 27
3120 12:26:31.318139 DramcWriteLeveling(PI) end<-----
3121 12:26:31.318247
3122 12:26:31.318341 ==
3123 12:26:31.321788 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 12:26:31.324947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 12:26:31.325034 ==
3126 12:26:31.328059 [Gating] SW mode calibration
3127 12:26:31.334999 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3128 12:26:31.341169 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3129 12:26:31.344757 0 15 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
3130 12:26:31.347868 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 12:26:31.354619 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 12:26:31.357538 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 12:26:31.361533 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 12:26:31.367730 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 12:26:31.370828 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
3136 12:26:31.374695 0 15 28 | B1->B0 | 3333 2424 | 0 1 | (0 1) (1 0)
3137 12:26:31.380804 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 12:26:31.384055 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 12:26:31.387715 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 12:26:31.394269 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 12:26:31.397285 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 12:26:31.400897 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 12:26:31.407337 1 0 24 | B1->B0 | 2626 2d2d | 0 0 | (1 1) (1 1)
3144 12:26:31.410462 1 0 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3145 12:26:31.414133 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 12:26:31.420267 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 12:26:31.424053 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 12:26:31.427175 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 12:26:31.433883 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 12:26:31.437119 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 12:26:31.440280 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3152 12:26:31.447015 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3153 12:26:31.450234 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 12:26:31.453784 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 12:26:31.459941 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 12:26:31.463620 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 12:26:31.466610 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 12:26:31.473320 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 12:26:31.476850 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 12:26:31.480100 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 12:26:31.483431 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 12:26:31.490195 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 12:26:31.493290 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 12:26:31.496364 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 12:26:31.503523 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 12:26:31.506555 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 12:26:31.510055 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3168 12:26:31.516559 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3169 12:26:31.520336 Total UI for P1: 0, mck2ui 16
3170 12:26:31.523437 best dqsien dly found for B0: ( 1, 3, 24)
3171 12:26:31.526374 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 12:26:31.530151 Total UI for P1: 0, mck2ui 16
3173 12:26:31.533247 best dqsien dly found for B1: ( 1, 3, 26)
3174 12:26:31.536388 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3175 12:26:31.540122 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3176 12:26:31.540201
3177 12:26:31.543368 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3178 12:26:31.546343 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3179 12:26:31.550197 [Gating] SW calibration Done
3180 12:26:31.550274 ==
3181 12:26:31.553114 Dram Type= 6, Freq= 0, CH_1, rank 0
3182 12:26:31.559953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3183 12:26:31.560092 ==
3184 12:26:31.560162 RX Vref Scan: 0
3185 12:26:31.560238
3186 12:26:31.563038 RX Vref 0 -> 0, step: 1
3187 12:26:31.563113
3188 12:26:31.566281 RX Delay -40 -> 252, step: 8
3189 12:26:31.569852 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3190 12:26:31.572938 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3191 12:26:31.576716 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3192 12:26:31.579491 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3193 12:26:31.586378 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3194 12:26:31.589618 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3195 12:26:31.592613 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3196 12:26:31.596222 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3197 12:26:31.599320 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3198 12:26:31.606083 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3199 12:26:31.609555 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3200 12:26:31.613000 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3201 12:26:31.615984 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3202 12:26:31.619438 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3203 12:26:31.626246 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3204 12:26:31.629518 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3205 12:26:31.629595 ==
3206 12:26:31.632617 Dram Type= 6, Freq= 0, CH_1, rank 0
3207 12:26:31.636190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3208 12:26:31.636269 ==
3209 12:26:31.639314 DQS Delay:
3210 12:26:31.639386 DQS0 = 0, DQS1 = 0
3211 12:26:31.639448 DQM Delay:
3212 12:26:31.643141 DQM0 = 116, DQM1 = 112
3213 12:26:31.643224 DQ Delay:
3214 12:26:31.646022 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =119
3215 12:26:31.649739 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3216 12:26:31.652765 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3217 12:26:31.659672 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3218 12:26:31.659760
3219 12:26:31.659827
3220 12:26:31.659889 ==
3221 12:26:31.662635 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 12:26:31.666408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 12:26:31.666492 ==
3224 12:26:31.666559
3225 12:26:31.666620
3226 12:26:31.669334 TX Vref Scan disable
3227 12:26:31.669418 == TX Byte 0 ==
3228 12:26:31.676006 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3229 12:26:31.679066 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3230 12:26:31.679160 == TX Byte 1 ==
3231 12:26:31.686024 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3232 12:26:31.689160 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3233 12:26:31.689247 ==
3234 12:26:31.692754 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 12:26:31.695871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 12:26:31.695981 ==
3237 12:26:31.708541 TX Vref=22, minBit 9, minWin=24, winSum=404
3238 12:26:31.712067 TX Vref=24, minBit 9, minWin=24, winSum=411
3239 12:26:31.715108 TX Vref=26, minBit 9, minWin=24, winSum=417
3240 12:26:31.718433 TX Vref=28, minBit 11, minWin=25, winSum=426
3241 12:26:31.722054 TX Vref=30, minBit 9, minWin=25, winSum=425
3242 12:26:31.728564 TX Vref=32, minBit 4, minWin=26, winSum=424
3243 12:26:31.731697 [TxChooseVref] Worse bit 4, Min win 26, Win sum 424, Final Vref 32
3244 12:26:31.731784
3245 12:26:31.734942 Final TX Range 1 Vref 32
3246 12:26:31.735028
3247 12:26:31.735095 ==
3248 12:26:31.738499 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 12:26:31.741767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 12:26:31.744785 ==
3251 12:26:31.744868
3252 12:26:31.744934
3253 12:26:31.744995 TX Vref Scan disable
3254 12:26:31.748459 == TX Byte 0 ==
3255 12:26:31.751462 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3256 12:26:31.758260 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3257 12:26:31.758349 == TX Byte 1 ==
3258 12:26:31.761302 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3259 12:26:31.768169 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3260 12:26:31.768253
3261 12:26:31.768320 [DATLAT]
3262 12:26:31.768391 Freq=1200, CH1 RK0
3263 12:26:31.768453
3264 12:26:31.771380 DATLAT Default: 0xd
3265 12:26:31.771460 0, 0xFFFF, sum = 0
3266 12:26:31.774864 1, 0xFFFF, sum = 0
3267 12:26:31.777834 2, 0xFFFF, sum = 0
3268 12:26:31.777925 3, 0xFFFF, sum = 0
3269 12:26:31.781476 4, 0xFFFF, sum = 0
3270 12:26:31.781565 5, 0xFFFF, sum = 0
3271 12:26:31.784475 6, 0xFFFF, sum = 0
3272 12:26:31.784559 7, 0xFFFF, sum = 0
3273 12:26:31.787654 8, 0xFFFF, sum = 0
3274 12:26:31.787739 9, 0xFFFF, sum = 0
3275 12:26:31.790910 10, 0xFFFF, sum = 0
3276 12:26:31.791027 11, 0xFFFF, sum = 0
3277 12:26:31.794526 12, 0x0, sum = 1
3278 12:26:31.794618 13, 0x0, sum = 2
3279 12:26:31.797600 14, 0x0, sum = 3
3280 12:26:31.797712 15, 0x0, sum = 4
3281 12:26:31.801427 best_step = 13
3282 12:26:31.801553
3283 12:26:31.801685 ==
3284 12:26:31.804625 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 12:26:31.807434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 12:26:31.807520 ==
3287 12:26:31.810937 RX Vref Scan: 1
3288 12:26:31.811091
3289 12:26:31.811251 Set Vref Range= 32 -> 127
3290 12:26:31.811315
3291 12:26:31.814020 RX Vref 32 -> 127, step: 1
3292 12:26:31.814128
3293 12:26:31.817629 RX Delay -13 -> 252, step: 4
3294 12:26:31.817742
3295 12:26:31.820694 Set Vref, RX VrefLevel [Byte0]: 32
3296 12:26:31.824211 [Byte1]: 32
3297 12:26:31.824359
3298 12:26:31.827778 Set Vref, RX VrefLevel [Byte0]: 33
3299 12:26:31.830948 [Byte1]: 33
3300 12:26:31.834498
3301 12:26:31.834621 Set Vref, RX VrefLevel [Byte0]: 34
3302 12:26:31.837776 [Byte1]: 34
3303 12:26:31.842747
3304 12:26:31.842832 Set Vref, RX VrefLevel [Byte0]: 35
3305 12:26:31.845838 [Byte1]: 35
3306 12:26:31.850231
3307 12:26:31.850314 Set Vref, RX VrefLevel [Byte0]: 36
3308 12:26:31.853373 [Byte1]: 36
3309 12:26:31.858158
3310 12:26:31.858249 Set Vref, RX VrefLevel [Byte0]: 37
3311 12:26:31.861248 [Byte1]: 37
3312 12:26:31.866373
3313 12:26:31.866459 Set Vref, RX VrefLevel [Byte0]: 38
3314 12:26:31.869405 [Byte1]: 38
3315 12:26:31.873951
3316 12:26:31.874043 Set Vref, RX VrefLevel [Byte0]: 39
3317 12:26:31.877408 [Byte1]: 39
3318 12:26:31.881675
3319 12:26:31.881805 Set Vref, RX VrefLevel [Byte0]: 40
3320 12:26:31.885315 [Byte1]: 40
3321 12:26:31.889489
3322 12:26:31.889605 Set Vref, RX VrefLevel [Byte0]: 41
3323 12:26:31.893401 [Byte1]: 41
3324 12:26:31.897473
3325 12:26:31.897591 Set Vref, RX VrefLevel [Byte0]: 42
3326 12:26:31.900641 [Byte1]: 42
3327 12:26:31.905503
3328 12:26:31.905592 Set Vref, RX VrefLevel [Byte0]: 43
3329 12:26:31.908555 [Byte1]: 43
3330 12:26:31.913390
3331 12:26:31.913498 Set Vref, RX VrefLevel [Byte0]: 44
3332 12:26:31.916860 [Byte1]: 44
3333 12:26:31.921083
3334 12:26:31.921164 Set Vref, RX VrefLevel [Byte0]: 45
3335 12:26:31.924680 [Byte1]: 45
3336 12:26:31.929310
3337 12:26:31.929419 Set Vref, RX VrefLevel [Byte0]: 46
3338 12:26:31.932326 [Byte1]: 46
3339 12:26:31.937386
3340 12:26:31.937496 Set Vref, RX VrefLevel [Byte0]: 47
3341 12:26:31.940590 [Byte1]: 47
3342 12:26:31.944810
3343 12:26:31.944887 Set Vref, RX VrefLevel [Byte0]: 48
3344 12:26:31.948597 [Byte1]: 48
3345 12:26:31.953021
3346 12:26:31.953105 Set Vref, RX VrefLevel [Byte0]: 49
3347 12:26:31.956231 [Byte1]: 49
3348 12:26:31.960947
3349 12:26:31.961034 Set Vref, RX VrefLevel [Byte0]: 50
3350 12:26:31.964236 [Byte1]: 50
3351 12:26:31.968552
3352 12:26:31.968637 Set Vref, RX VrefLevel [Byte0]: 51
3353 12:26:31.971617 [Byte1]: 51
3354 12:26:31.976619
3355 12:26:31.976697 Set Vref, RX VrefLevel [Byte0]: 52
3356 12:26:31.979759 [Byte1]: 52
3357 12:26:31.984461
3358 12:26:31.984544 Set Vref, RX VrefLevel [Byte0]: 53
3359 12:26:31.987540 [Byte1]: 53
3360 12:26:31.992577
3361 12:26:31.992667 Set Vref, RX VrefLevel [Byte0]: 54
3362 12:26:31.995302 [Byte1]: 54
3363 12:26:32.000266
3364 12:26:32.000371 Set Vref, RX VrefLevel [Byte0]: 55
3365 12:26:32.003328 [Byte1]: 55
3366 12:26:32.008412
3367 12:26:32.008546 Set Vref, RX VrefLevel [Byte0]: 56
3368 12:26:32.011281 [Byte1]: 56
3369 12:26:32.015707
3370 12:26:32.015803 Set Vref, RX VrefLevel [Byte0]: 57
3371 12:26:32.019302 [Byte1]: 57
3372 12:26:32.024166
3373 12:26:32.024254 Set Vref, RX VrefLevel [Byte0]: 58
3374 12:26:32.027130 [Byte1]: 58
3375 12:26:32.031786
3376 12:26:32.031871 Set Vref, RX VrefLevel [Byte0]: 59
3377 12:26:32.035242 [Byte1]: 59
3378 12:26:32.039238
3379 12:26:32.039323 Set Vref, RX VrefLevel [Byte0]: 60
3380 12:26:32.043016 [Byte1]: 60
3381 12:26:32.047408
3382 12:26:32.047501 Set Vref, RX VrefLevel [Byte0]: 61
3383 12:26:32.050513 [Byte1]: 61
3384 12:26:32.055373
3385 12:26:32.055464 Set Vref, RX VrefLevel [Byte0]: 62
3386 12:26:32.058458 [Byte1]: 62
3387 12:26:32.063495
3388 12:26:32.063586 Set Vref, RX VrefLevel [Byte0]: 63
3389 12:26:32.066607 [Byte1]: 63
3390 12:26:32.070793
3391 12:26:32.070904 Set Vref, RX VrefLevel [Byte0]: 64
3392 12:26:32.074633 [Byte1]: 64
3393 12:26:32.078874
3394 12:26:32.079035 Set Vref, RX VrefLevel [Byte0]: 65
3395 12:26:32.082100 [Byte1]: 65
3396 12:26:32.086645
3397 12:26:32.086760 Set Vref, RX VrefLevel [Byte0]: 66
3398 12:26:32.090236 [Byte1]: 66
3399 12:26:32.094475
3400 12:26:32.094579 Final RX Vref Byte 0 = 50 to rank0
3401 12:26:32.098168 Final RX Vref Byte 1 = 49 to rank0
3402 12:26:32.101106 Final RX Vref Byte 0 = 50 to rank1
3403 12:26:32.104862 Final RX Vref Byte 1 = 49 to rank1==
3404 12:26:32.107869 Dram Type= 6, Freq= 0, CH_1, rank 0
3405 12:26:32.114621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3406 12:26:32.114748 ==
3407 12:26:32.114853 DQS Delay:
3408 12:26:32.117792 DQS0 = 0, DQS1 = 0
3409 12:26:32.117921 DQM Delay:
3410 12:26:32.118024 DQM0 = 114, DQM1 = 112
3411 12:26:32.120917 DQ Delay:
3412 12:26:32.124506 DQ0 =120, DQ1 =108, DQ2 =106, DQ3 =116
3413 12:26:32.127886 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3414 12:26:32.130971 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3415 12:26:32.134483 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3416 12:26:32.134621
3417 12:26:32.134719
3418 12:26:32.144001 [DQSOSCAuto] RK0, (LSB)MR18= 0xeffb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 417 ps
3419 12:26:32.144183 CH1 RK0: MR19=303, MR18=EFFB
3420 12:26:32.150949 CH1_RK0: MR19=0x303, MR18=0xEFFB, DQSOSC=412, MR23=63, INC=38, DEC=25
3421 12:26:32.151090
3422 12:26:32.154598 ----->DramcWriteLeveling(PI) begin...
3423 12:26:32.154692 ==
3424 12:26:32.157756 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 12:26:32.164242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3426 12:26:32.164381 ==
3427 12:26:32.167453 Write leveling (Byte 0): 23 => 23
3428 12:26:32.167561 Write leveling (Byte 1): 28 => 28
3429 12:26:32.171274 DramcWriteLeveling(PI) end<-----
3430 12:26:32.171385
3431 12:26:32.171454 ==
3432 12:26:32.174096 Dram Type= 6, Freq= 0, CH_1, rank 1
3433 12:26:32.181048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 12:26:32.181170 ==
3435 12:26:32.184222 [Gating] SW mode calibration
3436 12:26:32.190693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3437 12:26:32.194198 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3438 12:26:32.200657 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3439 12:26:32.204287 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 12:26:32.207420 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 12:26:32.214005 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 12:26:32.217162 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 12:26:32.220227 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
3444 12:26:32.227064 0 15 24 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
3445 12:26:32.230721 0 15 28 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
3446 12:26:32.233619 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 12:26:32.240620 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 12:26:32.243794 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 12:26:32.247278 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 12:26:32.253880 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 12:26:32.256858 1 0 20 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
3452 12:26:32.259944 1 0 24 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
3453 12:26:32.266881 1 0 28 | B1->B0 | 3232 4646 | 0 0 | (1 1) (0 0)
3454 12:26:32.269886 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 12:26:32.273711 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 12:26:32.279793 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 12:26:32.283508 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 12:26:32.286679 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 12:26:32.292933 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 12:26:32.296473 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3461 12:26:32.299470 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3462 12:26:32.306153 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 12:26:32.309208 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 12:26:32.313064 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 12:26:32.319262 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 12:26:32.322674 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 12:26:32.326467 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 12:26:32.332759 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 12:26:32.335700 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 12:26:32.339127 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 12:26:32.345592 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 12:26:32.349337 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 12:26:32.352346 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 12:26:32.358981 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 12:26:32.361986 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 12:26:32.365177 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3477 12:26:32.372039 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3478 12:26:32.372130 Total UI for P1: 0, mck2ui 16
3479 12:26:32.378843 best dqsien dly found for B0: ( 1, 3, 24)
3480 12:26:32.382052 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 12:26:32.385189 Total UI for P1: 0, mck2ui 16
3482 12:26:32.388203 best dqsien dly found for B1: ( 1, 3, 28)
3483 12:26:32.392003 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3484 12:26:32.395254 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3485 12:26:32.395342
3486 12:26:32.398217 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3487 12:26:32.401818 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3488 12:26:32.404813 [Gating] SW calibration Done
3489 12:26:32.404906 ==
3490 12:26:32.408490 Dram Type= 6, Freq= 0, CH_1, rank 1
3491 12:26:32.414772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 12:26:32.414872 ==
3493 12:26:32.414960 RX Vref Scan: 0
3494 12:26:32.415044
3495 12:26:32.418589 RX Vref 0 -> 0, step: 1
3496 12:26:32.418674
3497 12:26:32.421570 RX Delay -40 -> 252, step: 8
3498 12:26:32.424638 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3499 12:26:32.428330 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3500 12:26:32.431367 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3501 12:26:32.434419 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3502 12:26:32.441286 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3503 12:26:32.444208 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3504 12:26:32.447735 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3505 12:26:32.451262 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3506 12:26:32.454328 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3507 12:26:32.460965 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3508 12:26:32.464079 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3509 12:26:32.467351 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3510 12:26:32.471172 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3511 12:26:32.477489 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3512 12:26:32.480884 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3513 12:26:32.483824 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3514 12:26:32.483934 ==
3515 12:26:32.487198 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 12:26:32.490307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 12:26:32.490411 ==
3518 12:26:32.494098 DQS Delay:
3519 12:26:32.494210 DQS0 = 0, DQS1 = 0
3520 12:26:32.497126 DQM Delay:
3521 12:26:32.497199 DQM0 = 115, DQM1 = 111
3522 12:26:32.500217 DQ Delay:
3523 12:26:32.503453 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3524 12:26:32.507221 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3525 12:26:32.510462 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3526 12:26:32.513524 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3527 12:26:32.513632
3528 12:26:32.513747
3529 12:26:32.513841 ==
3530 12:26:32.517189 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 12:26:32.520470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 12:26:32.520576 ==
3533 12:26:32.520676
3534 12:26:32.520767
3535 12:26:32.523648 TX Vref Scan disable
3536 12:26:32.526674 == TX Byte 0 ==
3537 12:26:32.530429 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3538 12:26:32.533521 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3539 12:26:32.536596 == TX Byte 1 ==
3540 12:26:32.540337 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3541 12:26:32.543459 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3542 12:26:32.543568 ==
3543 12:26:32.546708 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 12:26:32.553441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 12:26:32.553553 ==
3546 12:26:32.563878 TX Vref=22, minBit 2, minWin=25, winSum=418
3547 12:26:32.567534 TX Vref=24, minBit 2, minWin=25, winSum=420
3548 12:26:32.570703 TX Vref=26, minBit 1, minWin=26, winSum=426
3549 12:26:32.573959 TX Vref=28, minBit 9, minWin=26, winSum=433
3550 12:26:32.577262 TX Vref=30, minBit 9, minWin=26, winSum=435
3551 12:26:32.583531 TX Vref=32, minBit 2, minWin=26, winSum=432
3552 12:26:32.586782 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3553 12:26:32.586898
3554 12:26:32.590005 Final TX Range 1 Vref 30
3555 12:26:32.590104
3556 12:26:32.590171 ==
3557 12:26:32.593651 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 12:26:32.599916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 12:26:32.600042 ==
3560 12:26:32.600145
3561 12:26:32.600243
3562 12:26:32.600342 TX Vref Scan disable
3563 12:26:32.603753 == TX Byte 0 ==
3564 12:26:32.606893 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3565 12:26:32.613931 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3566 12:26:32.614044 == TX Byte 1 ==
3567 12:26:32.616526 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3568 12:26:32.623280 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3569 12:26:32.623372
3570 12:26:32.623440 [DATLAT]
3571 12:26:32.623504 Freq=1200, CH1 RK1
3572 12:26:32.623565
3573 12:26:32.626435 DATLAT Default: 0xd
3574 12:26:32.630179 0, 0xFFFF, sum = 0
3575 12:26:32.630266 1, 0xFFFF, sum = 0
3576 12:26:32.633358 2, 0xFFFF, sum = 0
3577 12:26:32.633444 3, 0xFFFF, sum = 0
3578 12:26:32.636324 4, 0xFFFF, sum = 0
3579 12:26:32.636411 5, 0xFFFF, sum = 0
3580 12:26:32.639980 6, 0xFFFF, sum = 0
3581 12:26:32.640077 7, 0xFFFF, sum = 0
3582 12:26:32.643157 8, 0xFFFF, sum = 0
3583 12:26:32.643243 9, 0xFFFF, sum = 0
3584 12:26:32.646302 10, 0xFFFF, sum = 0
3585 12:26:32.646417 11, 0xFFFF, sum = 0
3586 12:26:32.649432 12, 0x0, sum = 1
3587 12:26:32.649546 13, 0x0, sum = 2
3588 12:26:32.653339 14, 0x0, sum = 3
3589 12:26:32.653425 15, 0x0, sum = 4
3590 12:26:32.656272 best_step = 13
3591 12:26:32.656357
3592 12:26:32.656424 ==
3593 12:26:32.659262 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 12:26:32.662556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 12:26:32.662641 ==
3596 12:26:32.666289 RX Vref Scan: 0
3597 12:26:32.666368
3598 12:26:32.666435 RX Vref 0 -> 0, step: 1
3599 12:26:32.666498
3600 12:26:32.669211 RX Delay -13 -> 252, step: 4
3601 12:26:32.675630 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3602 12:26:32.679311 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3603 12:26:32.682399 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3604 12:26:32.685628 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3605 12:26:32.692553 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3606 12:26:32.695767 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3607 12:26:32.699106 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3608 12:26:32.702258 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3609 12:26:32.705295 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3610 12:26:32.712289 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3611 12:26:32.715358 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3612 12:26:32.718628 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3613 12:26:32.721885 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3614 12:26:32.724986 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3615 12:26:32.731538 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3616 12:26:32.734818 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3617 12:26:32.734907 ==
3618 12:26:32.738111 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 12:26:32.741780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 12:26:32.741862 ==
3621 12:26:32.744663 DQS Delay:
3622 12:26:32.744745 DQS0 = 0, DQS1 = 0
3623 12:26:32.747937 DQM Delay:
3624 12:26:32.748021 DQM0 = 115, DQM1 = 111
3625 12:26:32.748131 DQ Delay:
3626 12:26:32.751661 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =114
3627 12:26:32.757852 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3628 12:26:32.761053 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3629 12:26:32.764638 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3630 12:26:32.764720
3631 12:26:32.764803
3632 12:26:32.771516 [DQSOSCAuto] RK1, (LSB)MR18= 0xf407, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 415 ps
3633 12:26:32.774505 CH1 RK1: MR19=304, MR18=F407
3634 12:26:32.781289 CH1_RK1: MR19=0x304, MR18=0xF407, DQSOSC=407, MR23=63, INC=39, DEC=26
3635 12:26:32.784493 [RxdqsGatingPostProcess] freq 1200
3636 12:26:32.790805 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3637 12:26:32.794145 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 12:26:32.794230 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 12:26:32.797244 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 12:26:32.800329 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 12:26:32.804208 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 12:26:32.807176 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 12:26:32.810542 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 12:26:32.813594 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 12:26:32.816855 Pre-setting of DQS Precalculation
3646 12:26:32.823366 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3647 12:26:32.830472 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3648 12:26:32.837052 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3649 12:26:32.837139
3650 12:26:32.837219
3651 12:26:32.840231 [Calibration Summary] 2400 Mbps
3652 12:26:32.840323 CH 0, Rank 0
3653 12:26:32.843376 SW Impedance : PASS
3654 12:26:32.846478 DUTY Scan : NO K
3655 12:26:32.846585 ZQ Calibration : PASS
3656 12:26:32.850193 Jitter Meter : NO K
3657 12:26:32.853215 CBT Training : PASS
3658 12:26:32.853294 Write leveling : PASS
3659 12:26:32.856479 RX DQS gating : PASS
3660 12:26:32.859579 RX DQ/DQS(RDDQC) : PASS
3661 12:26:32.859660 TX DQ/DQS : PASS
3662 12:26:32.863251 RX DATLAT : PASS
3663 12:26:32.866163 RX DQ/DQS(Engine): PASS
3664 12:26:32.866252 TX OE : NO K
3665 12:26:32.869973 All Pass.
3666 12:26:32.870066
3667 12:26:32.870132 CH 0, Rank 1
3668 12:26:32.873204 SW Impedance : PASS
3669 12:26:32.873307 DUTY Scan : NO K
3670 12:26:32.876136 ZQ Calibration : PASS
3671 12:26:32.879712 Jitter Meter : NO K
3672 12:26:32.879852 CBT Training : PASS
3673 12:26:32.882810 Write leveling : PASS
3674 12:26:32.886209 RX DQS gating : PASS
3675 12:26:32.886310 RX DQ/DQS(RDDQC) : PASS
3676 12:26:32.889372 TX DQ/DQS : PASS
3677 12:26:32.892562 RX DATLAT : PASS
3678 12:26:32.892651 RX DQ/DQS(Engine): PASS
3679 12:26:32.895896 TX OE : NO K
3680 12:26:32.895980 All Pass.
3681 12:26:32.896068
3682 12:26:32.899596 CH 1, Rank 0
3683 12:26:32.899679 SW Impedance : PASS
3684 12:26:32.902892 DUTY Scan : NO K
3685 12:26:32.905861 ZQ Calibration : PASS
3686 12:26:32.905945 Jitter Meter : NO K
3687 12:26:32.909242 CBT Training : PASS
3688 12:26:32.912401 Write leveling : PASS
3689 12:26:32.912486 RX DQS gating : PASS
3690 12:26:32.915438 RX DQ/DQS(RDDQC) : PASS
3691 12:26:32.915522 TX DQ/DQS : PASS
3692 12:26:32.918855 RX DATLAT : PASS
3693 12:26:32.922628 RX DQ/DQS(Engine): PASS
3694 12:26:32.922730 TX OE : NO K
3695 12:26:32.925775 All Pass.
3696 12:26:32.925872
3697 12:26:32.925938 CH 1, Rank 1
3698 12:26:32.929126 SW Impedance : PASS
3699 12:26:32.929208 DUTY Scan : NO K
3700 12:26:32.932161 ZQ Calibration : PASS
3701 12:26:32.935195 Jitter Meter : NO K
3702 12:26:32.935279 CBT Training : PASS
3703 12:26:32.938994 Write leveling : PASS
3704 12:26:32.941918 RX DQS gating : PASS
3705 12:26:32.942001 RX DQ/DQS(RDDQC) : PASS
3706 12:26:32.945257 TX DQ/DQS : PASS
3707 12:26:32.948193 RX DATLAT : PASS
3708 12:26:32.948285 RX DQ/DQS(Engine): PASS
3709 12:26:32.951975 TX OE : NO K
3710 12:26:32.952125 All Pass.
3711 12:26:32.952215
3712 12:26:32.955092 DramC Write-DBI off
3713 12:26:32.958300 PER_BANK_REFRESH: Hybrid Mode
3714 12:26:32.958382 TX_TRACKING: ON
3715 12:26:32.968173 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3716 12:26:32.971248 [FAST_K] Save calibration result to emmc
3717 12:26:32.974968 dramc_set_vcore_voltage set vcore to 650000
3718 12:26:32.977960 Read voltage for 600, 5
3719 12:26:32.978041 Vio18 = 0
3720 12:26:32.981558 Vcore = 650000
3721 12:26:32.981647 Vdram = 0
3722 12:26:32.981732 Vddq = 0
3723 12:26:32.981811 Vmddr = 0
3724 12:26:32.987737 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3725 12:26:32.994640 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3726 12:26:32.994728 MEM_TYPE=3, freq_sel=19
3727 12:26:32.997781 sv_algorithm_assistance_LP4_1600
3728 12:26:33.001022 ============ PULL DRAM RESETB DOWN ============
3729 12:26:33.007783 ========== PULL DRAM RESETB DOWN end =========
3730 12:26:33.011053 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3731 12:26:33.014199 ===================================
3732 12:26:33.017438 LPDDR4 DRAM CONFIGURATION
3733 12:26:33.020656 ===================================
3734 12:26:33.020739 EX_ROW_EN[0] = 0x0
3735 12:26:33.024526 EX_ROW_EN[1] = 0x0
3736 12:26:33.027645 LP4Y_EN = 0x0
3737 12:26:33.027758 WORK_FSP = 0x0
3738 12:26:33.030635 WL = 0x2
3739 12:26:33.030736 RL = 0x2
3740 12:26:33.034012 BL = 0x2
3741 12:26:33.034092 RPST = 0x0
3742 12:26:33.037705 RD_PRE = 0x0
3743 12:26:33.037789 WR_PRE = 0x1
3744 12:26:33.040775 WR_PST = 0x0
3745 12:26:33.040856 DBI_WR = 0x0
3746 12:26:33.043713 DBI_RD = 0x0
3747 12:26:33.043845 OTF = 0x1
3748 12:26:33.047564 ===================================
3749 12:26:33.050674 ===================================
3750 12:26:33.053718 ANA top config
3751 12:26:33.056976 ===================================
3752 12:26:33.057067 DLL_ASYNC_EN = 0
3753 12:26:33.060583 ALL_SLAVE_EN = 1
3754 12:26:33.063692 NEW_RANK_MODE = 1
3755 12:26:33.066998 DLL_IDLE_MODE = 1
3756 12:26:33.070648 LP45_APHY_COMB_EN = 1
3757 12:26:33.070737 TX_ODT_DIS = 1
3758 12:26:33.073482 NEW_8X_MODE = 1
3759 12:26:33.076576 ===================================
3760 12:26:33.080341 ===================================
3761 12:26:33.083252 data_rate = 1200
3762 12:26:33.086397 CKR = 1
3763 12:26:33.090048 DQ_P2S_RATIO = 8
3764 12:26:33.092952 ===================================
3765 12:26:33.096318 CA_P2S_RATIO = 8
3766 12:26:33.096397 DQ_CA_OPEN = 0
3767 12:26:33.099515 DQ_SEMI_OPEN = 0
3768 12:26:33.103269 CA_SEMI_OPEN = 0
3769 12:26:33.106583 CA_FULL_RATE = 0
3770 12:26:33.109606 DQ_CKDIV4_EN = 1
3771 12:26:33.112833 CA_CKDIV4_EN = 1
3772 12:26:33.112911 CA_PREDIV_EN = 0
3773 12:26:33.115960 PH8_DLY = 0
3774 12:26:33.119289 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3775 12:26:33.122996 DQ_AAMCK_DIV = 4
3776 12:26:33.126265 CA_AAMCK_DIV = 4
3777 12:26:33.129324 CA_ADMCK_DIV = 4
3778 12:26:33.129408 DQ_TRACK_CA_EN = 0
3779 12:26:33.132836 CA_PICK = 600
3780 12:26:33.136165 CA_MCKIO = 600
3781 12:26:33.139424 MCKIO_SEMI = 0
3782 12:26:33.142504 PLL_FREQ = 2288
3783 12:26:33.145759 DQ_UI_PI_RATIO = 32
3784 12:26:33.149352 CA_UI_PI_RATIO = 0
3785 12:26:33.152389 ===================================
3786 12:26:33.155465 ===================================
3787 12:26:33.155539 memory_type:LPDDR4
3788 12:26:33.158682 GP_NUM : 10
3789 12:26:33.162427 SRAM_EN : 1
3790 12:26:33.162510 MD32_EN : 0
3791 12:26:33.165451 ===================================
3792 12:26:33.168583 [ANA_INIT] >>>>>>>>>>>>>>
3793 12:26:33.172437 <<<<<< [CONFIGURE PHASE]: ANA_TX
3794 12:26:33.175339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3795 12:26:33.179005 ===================================
3796 12:26:33.182094 data_rate = 1200,PCW = 0X5800
3797 12:26:33.185317 ===================================
3798 12:26:33.188456 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3799 12:26:33.194972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 12:26:33.198126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3801 12:26:33.205331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3802 12:26:33.208566 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3803 12:26:33.211741 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3804 12:26:33.211825 [ANA_INIT] flow start
3805 12:26:33.214647 [ANA_INIT] PLL >>>>>>>>
3806 12:26:33.218470 [ANA_INIT] PLL <<<<<<<<
3807 12:26:33.218550 [ANA_INIT] MIDPI >>>>>>>>
3808 12:26:33.221764 [ANA_INIT] MIDPI <<<<<<<<
3809 12:26:33.224902 [ANA_INIT] DLL >>>>>>>>
3810 12:26:33.224991 [ANA_INIT] flow end
3811 12:26:33.231207 ============ LP4 DIFF to SE enter ============
3812 12:26:33.234365 ============ LP4 DIFF to SE exit ============
3813 12:26:33.238006 [ANA_INIT] <<<<<<<<<<<<<
3814 12:26:33.241053 [Flow] Enable top DCM control >>>>>
3815 12:26:33.244130 [Flow] Enable top DCM control <<<<<
3816 12:26:33.247409 Enable DLL master slave shuffle
3817 12:26:33.251096 ==============================================================
3818 12:26:33.254064 Gating Mode config
3819 12:26:33.257904 ==============================================================
3820 12:26:33.260989 Config description:
3821 12:26:33.270370 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3822 12:26:33.277386 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3823 12:26:33.280385 SELPH_MODE 0: By rank 1: By Phase
3824 12:26:33.287133 ==============================================================
3825 12:26:33.290238 GAT_TRACK_EN = 1
3826 12:26:33.293962 RX_GATING_MODE = 2
3827 12:26:33.296992 RX_GATING_TRACK_MODE = 2
3828 12:26:33.300069 SELPH_MODE = 1
3829 12:26:33.303454 PICG_EARLY_EN = 1
3830 12:26:33.306663 VALID_LAT_VALUE = 1
3831 12:26:33.310513 ==============================================================
3832 12:26:33.313522 Enter into Gating configuration >>>>
3833 12:26:33.316727 Exit from Gating configuration <<<<
3834 12:26:33.319804 Enter into DVFS_PRE_config >>>>>
3835 12:26:33.333232 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3836 12:26:33.336453 Exit from DVFS_PRE_config <<<<<
3837 12:26:33.339578 Enter into PICG configuration >>>>
3838 12:26:33.339676 Exit from PICG configuration <<<<
3839 12:26:33.343522 [RX_INPUT] configuration >>>>>
3840 12:26:33.346262 [RX_INPUT] configuration <<<<<
3841 12:26:33.352614 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3842 12:26:33.356297 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3843 12:26:33.362577 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3844 12:26:33.369372 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3845 12:26:33.375584 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3846 12:26:33.382541 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3847 12:26:33.385708 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3848 12:26:33.389077 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3849 12:26:33.395347 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3850 12:26:33.398978 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3851 12:26:33.401998 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3852 12:26:33.409099 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3853 12:26:33.412271 ===================================
3854 12:26:33.412352 LPDDR4 DRAM CONFIGURATION
3855 12:26:33.415335 ===================================
3856 12:26:33.418307 EX_ROW_EN[0] = 0x0
3857 12:26:33.418388 EX_ROW_EN[1] = 0x0
3858 12:26:33.422082 LP4Y_EN = 0x0
3859 12:26:33.422160 WORK_FSP = 0x0
3860 12:26:33.425273 WL = 0x2
3861 12:26:33.428419 RL = 0x2
3862 12:26:33.428497 BL = 0x2
3863 12:26:33.431594 RPST = 0x0
3864 12:26:33.431673 RD_PRE = 0x0
3865 12:26:33.434748 WR_PRE = 0x1
3866 12:26:33.434828 WR_PST = 0x0
3867 12:26:33.438096 DBI_WR = 0x0
3868 12:26:33.438194 DBI_RD = 0x0
3869 12:26:33.441229 OTF = 0x1
3870 12:26:33.445046 ===================================
3871 12:26:33.448062 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3872 12:26:33.451217 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3873 12:26:33.457841 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3874 12:26:33.461126 ===================================
3875 12:26:33.461205 LPDDR4 DRAM CONFIGURATION
3876 12:26:33.464971 ===================================
3877 12:26:33.467953 EX_ROW_EN[0] = 0x10
3878 12:26:33.471157 EX_ROW_EN[1] = 0x0
3879 12:26:33.471234 LP4Y_EN = 0x0
3880 12:26:33.474302 WORK_FSP = 0x0
3881 12:26:33.474379 WL = 0x2
3882 12:26:33.477420 RL = 0x2
3883 12:26:33.477497 BL = 0x2
3884 12:26:33.481173 RPST = 0x0
3885 12:26:33.481249 RD_PRE = 0x0
3886 12:26:33.484279 WR_PRE = 0x1
3887 12:26:33.484361 WR_PST = 0x0
3888 12:26:33.487409 DBI_WR = 0x0
3889 12:26:33.487492 DBI_RD = 0x0
3890 12:26:33.491009 OTF = 0x1
3891 12:26:33.494043 ===================================
3892 12:26:33.500966 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3893 12:26:33.504023 nWR fixed to 30
3894 12:26:33.507625 [ModeRegInit_LP4] CH0 RK0
3895 12:26:33.507708 [ModeRegInit_LP4] CH0 RK1
3896 12:26:33.510721 [ModeRegInit_LP4] CH1 RK0
3897 12:26:33.514030 [ModeRegInit_LP4] CH1 RK1
3898 12:26:33.514149 match AC timing 17
3899 12:26:33.520230 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3900 12:26:33.523978 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3901 12:26:33.527219 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3902 12:26:33.533507 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3903 12:26:33.536814 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3904 12:26:33.536898 ==
3905 12:26:33.540016 Dram Type= 6, Freq= 0, CH_0, rank 0
3906 12:26:33.543692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3907 12:26:33.543775 ==
3908 12:26:33.550129 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3909 12:26:33.556656 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3910 12:26:33.559714 [CA 0] Center 36 (6~67) winsize 62
3911 12:26:33.562903 [CA 1] Center 36 (6~66) winsize 61
3912 12:26:33.566643 [CA 2] Center 34 (4~65) winsize 62
3913 12:26:33.569878 [CA 3] Center 34 (4~65) winsize 62
3914 12:26:33.573121 [CA 4] Center 33 (3~64) winsize 62
3915 12:26:33.576174 [CA 5] Center 33 (3~64) winsize 62
3916 12:26:33.576275
3917 12:26:33.579936 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3918 12:26:33.580053
3919 12:26:33.582989 [CATrainingPosCal] consider 1 rank data
3920 12:26:33.586195 u2DelayCellTimex100 = 270/100 ps
3921 12:26:33.590043 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3922 12:26:33.593229 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3923 12:26:33.596235 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3924 12:26:33.599420 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3925 12:26:33.606078 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3926 12:26:33.609173 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3927 12:26:33.609257
3928 12:26:33.613073 CA PerBit enable=1, Macro0, CA PI delay=33
3929 12:26:33.613157
3930 12:26:33.616202 [CBTSetCACLKResult] CA Dly = 33
3931 12:26:33.616286 CS Dly: 6 (0~37)
3932 12:26:33.616353 ==
3933 12:26:33.619190 Dram Type= 6, Freq= 0, CH_0, rank 1
3934 12:26:33.626077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3935 12:26:33.626161 ==
3936 12:26:33.629247 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3937 12:26:33.635669 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3938 12:26:33.638742 [CA 0] Center 36 (6~67) winsize 62
3939 12:26:33.642042 [CA 1] Center 36 (6~67) winsize 62
3940 12:26:33.645730 [CA 2] Center 34 (4~65) winsize 62
3941 12:26:33.648878 [CA 3] Center 34 (4~65) winsize 62
3942 12:26:33.651976 [CA 4] Center 33 (3~64) winsize 62
3943 12:26:33.655696 [CA 5] Center 33 (3~64) winsize 62
3944 12:26:33.655780
3945 12:26:33.658577 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3946 12:26:33.658659
3947 12:26:33.661798 [CATrainingPosCal] consider 2 rank data
3948 12:26:33.665554 u2DelayCellTimex100 = 270/100 ps
3949 12:26:33.668556 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3950 12:26:33.674932 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3951 12:26:33.678450 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3952 12:26:33.681568 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3953 12:26:33.684777 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3954 12:26:33.687963 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3955 12:26:33.688097
3956 12:26:33.691695 CA PerBit enable=1, Macro0, CA PI delay=33
3957 12:26:33.691797
3958 12:26:33.694780 [CBTSetCACLKResult] CA Dly = 33
3959 12:26:33.698027 CS Dly: 6 (0~37)
3960 12:26:33.698154
3961 12:26:33.701508 ----->DramcWriteLeveling(PI) begin...
3962 12:26:33.701585 ==
3963 12:26:33.704450 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 12:26:33.707647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 12:26:33.707724 ==
3966 12:26:33.711367 Write leveling (Byte 0): 33 => 33
3967 12:26:33.714476 Write leveling (Byte 1): 31 => 31
3968 12:26:33.717632 DramcWriteLeveling(PI) end<-----
3969 12:26:33.717715
3970 12:26:33.717781 ==
3971 12:26:33.721331 Dram Type= 6, Freq= 0, CH_0, rank 0
3972 12:26:33.724453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 12:26:33.724641 ==
3974 12:26:33.727641 [Gating] SW mode calibration
3975 12:26:33.734107 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3976 12:26:33.740951 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3977 12:26:33.744143 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 12:26:33.750456 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 12:26:33.753691 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 12:26:33.757402 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3981 12:26:33.763465 0 9 16 | B1->B0 | 2d2d 2525 | 0 0 | (0 0) (0 0)
3982 12:26:33.767251 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 12:26:33.770231 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 12:26:33.777121 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 12:26:33.780192 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 12:26:33.783450 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 12:26:33.790238 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 12:26:33.793286 0 10 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
3989 12:26:33.796606 0 10 16 | B1->B0 | 3e3e 4242 | 0 0 | (0 0) (0 0)
3990 12:26:33.803474 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 12:26:33.806652 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 12:26:33.809757 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 12:26:33.816040 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 12:26:33.819740 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 12:26:33.822816 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 12:26:33.829302 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3997 12:26:33.833096 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3998 12:26:33.836328 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 12:26:33.842799 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 12:26:33.845993 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 12:26:33.849178 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 12:26:33.856075 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 12:26:33.859185 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 12:26:33.862399 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 12:26:33.869207 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 12:26:33.872233 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 12:26:33.875939 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 12:26:33.882275 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 12:26:33.886064 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 12:26:33.889239 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 12:26:33.895521 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 12:26:33.898546 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4013 12:26:33.902394 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 12:26:33.905485 Total UI for P1: 0, mck2ui 16
4015 12:26:33.908607 best dqsien dly found for B0: ( 0, 13, 12)
4016 12:26:33.912231 Total UI for P1: 0, mck2ui 16
4017 12:26:33.915279 best dqsien dly found for B1: ( 0, 13, 14)
4018 12:26:33.918489 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4019 12:26:33.922002 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4020 12:26:33.922081
4021 12:26:33.928589 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4022 12:26:33.931810 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4023 12:26:33.931889 [Gating] SW calibration Done
4024 12:26:33.935080 ==
4025 12:26:33.938365 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 12:26:33.941465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 12:26:33.941550 ==
4028 12:26:33.941621 RX Vref Scan: 0
4029 12:26:33.941683
4030 12:26:33.945139 RX Vref 0 -> 0, step: 1
4031 12:26:33.945217
4032 12:26:33.948215 RX Delay -230 -> 252, step: 16
4033 12:26:33.951368 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4034 12:26:33.955136 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4035 12:26:33.961790 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4036 12:26:33.964766 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4037 12:26:33.967947 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4038 12:26:33.971788 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4039 12:26:33.978007 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4040 12:26:33.981141 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4041 12:26:33.984302 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4042 12:26:33.987936 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4043 12:26:33.994163 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4044 12:26:33.997962 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4045 12:26:34.001103 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4046 12:26:34.004157 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4047 12:26:34.010995 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4048 12:26:34.013946 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4049 12:26:34.014038 ==
4050 12:26:34.017128 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 12:26:34.020995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 12:26:34.021079 ==
4053 12:26:34.023938 DQS Delay:
4054 12:26:34.024063 DQS0 = 0, DQS1 = 0
4055 12:26:34.024189 DQM Delay:
4056 12:26:34.026993 DQM0 = 45, DQM1 = 31
4057 12:26:34.027098 DQ Delay:
4058 12:26:34.030693 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4059 12:26:34.033662 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4060 12:26:34.036913 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4061 12:26:34.040141 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4062 12:26:34.040224
4063 12:26:34.040299
4064 12:26:34.040376 ==
4065 12:26:34.043989 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 12:26:34.050417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 12:26:34.050499 ==
4068 12:26:34.050629
4069 12:26:34.050737
4070 12:26:34.050839 TX Vref Scan disable
4071 12:26:34.054163 == TX Byte 0 ==
4072 12:26:34.057429 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4073 12:26:34.063823 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4074 12:26:34.063933 == TX Byte 1 ==
4075 12:26:34.066918 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4076 12:26:34.073695 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4077 12:26:34.073790 ==
4078 12:26:34.077341 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 12:26:34.080207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 12:26:34.080326 ==
4081 12:26:34.080443
4082 12:26:34.080548
4083 12:26:34.083800 TX Vref Scan disable
4084 12:26:34.086826 == TX Byte 0 ==
4085 12:26:34.090552 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4086 12:26:34.093941 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4087 12:26:34.096893 == TX Byte 1 ==
4088 12:26:34.100614 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4089 12:26:34.103682 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4090 12:26:34.103793
4091 12:26:34.103897 [DATLAT]
4092 12:26:34.107233 Freq=600, CH0 RK0
4093 12:26:34.107314
4094 12:26:34.110505 DATLAT Default: 0x9
4095 12:26:34.110591 0, 0xFFFF, sum = 0
4096 12:26:34.113644 1, 0xFFFF, sum = 0
4097 12:26:34.113729 2, 0xFFFF, sum = 0
4098 12:26:34.116872 3, 0xFFFF, sum = 0
4099 12:26:34.116958 4, 0xFFFF, sum = 0
4100 12:26:34.119859 5, 0xFFFF, sum = 0
4101 12:26:34.119959 6, 0xFFFF, sum = 0
4102 12:26:34.123607 7, 0xFFFF, sum = 0
4103 12:26:34.123682 8, 0x0, sum = 1
4104 12:26:34.126697 9, 0x0, sum = 2
4105 12:26:34.126809 10, 0x0, sum = 3
4106 12:26:34.129593 11, 0x0, sum = 4
4107 12:26:34.129720 best_step = 9
4108 12:26:34.129801
4109 12:26:34.129875 ==
4110 12:26:34.133469 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 12:26:34.136514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 12:26:34.139645 ==
4113 12:26:34.139757 RX Vref Scan: 1
4114 12:26:34.139851
4115 12:26:34.142977 RX Vref 0 -> 0, step: 1
4116 12:26:34.143061
4117 12:26:34.146078 RX Delay -195 -> 252, step: 8
4118 12:26:34.146157
4119 12:26:34.149300 Set Vref, RX VrefLevel [Byte0]: 51
4120 12:26:34.153157 [Byte1]: 58
4121 12:26:34.153235
4122 12:26:34.156290 Final RX Vref Byte 0 = 51 to rank0
4123 12:26:34.159368 Final RX Vref Byte 1 = 58 to rank0
4124 12:26:34.162650 Final RX Vref Byte 0 = 51 to rank1
4125 12:26:34.166029 Final RX Vref Byte 1 = 58 to rank1==
4126 12:26:34.169090 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 12:26:34.172336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 12:26:34.172422 ==
4129 12:26:34.175845 DQS Delay:
4130 12:26:34.175931 DQS0 = 0, DQS1 = 0
4131 12:26:34.176015 DQM Delay:
4132 12:26:34.178977 DQM0 = 42, DQM1 = 33
4133 12:26:34.179061 DQ Delay:
4134 12:26:34.182434 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4135 12:26:34.185562 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4136 12:26:34.188873 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =32
4137 12:26:34.191931 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4138 12:26:34.192015
4139 12:26:34.192095
4140 12:26:34.202176 [DQSOSCAuto] RK0, (LSB)MR18= 0x473e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4141 12:26:34.205114 CH0 RK0: MR19=808, MR18=473E
4142 12:26:34.212122 CH0_RK0: MR19=0x808, MR18=0x473E, DQSOSC=396, MR23=63, INC=167, DEC=111
4143 12:26:34.212243
4144 12:26:34.215188 ----->DramcWriteLeveling(PI) begin...
4145 12:26:34.215296 ==
4146 12:26:34.218369 Dram Type= 6, Freq= 0, CH_0, rank 1
4147 12:26:34.221589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 12:26:34.221674 ==
4149 12:26:34.225316 Write leveling (Byte 0): 34 => 34
4150 12:26:34.228241 Write leveling (Byte 1): 29 => 29
4151 12:26:34.231333 DramcWriteLeveling(PI) end<-----
4152 12:26:34.231438
4153 12:26:34.231543 ==
4154 12:26:34.234491 Dram Type= 6, Freq= 0, CH_0, rank 1
4155 12:26:34.238002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 12:26:34.238089 ==
4157 12:26:34.241495 [Gating] SW mode calibration
4158 12:26:34.247808 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4159 12:26:34.254210 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4160 12:26:34.257995 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 12:26:34.261188 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 12:26:34.267645 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 12:26:34.270897 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
4164 12:26:34.274104 0 9 16 | B1->B0 | 2e2e 2626 | 1 1 | (1 0) (1 0)
4165 12:26:34.280873 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 12:26:34.283957 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 12:26:34.287436 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 12:26:34.293579 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 12:26:34.297022 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 12:26:34.303831 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 12:26:34.307031 0 10 12 | B1->B0 | 2828 3232 | 0 1 | (1 1) (0 0)
4172 12:26:34.310662 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4173 12:26:34.316681 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 12:26:34.319892 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 12:26:34.323672 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 12:26:34.329873 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 12:26:34.333412 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 12:26:34.336540 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 12:26:34.343146 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4180 12:26:34.346282 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4181 12:26:34.349632 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 12:26:34.356719 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 12:26:34.359846 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 12:26:34.362948 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 12:26:34.369230 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 12:26:34.372485 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 12:26:34.376278 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 12:26:34.382484 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 12:26:34.386143 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 12:26:34.389212 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 12:26:34.395511 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 12:26:34.399262 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 12:26:34.402448 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 12:26:34.409330 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 12:26:34.412643 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 12:26:34.415731 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4197 12:26:34.418801 Total UI for P1: 0, mck2ui 16
4198 12:26:34.422353 best dqsien dly found for B0: ( 0, 13, 14)
4199 12:26:34.428866 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 12:26:34.428950 Total UI for P1: 0, mck2ui 16
4201 12:26:34.432190 best dqsien dly found for B1: ( 0, 13, 16)
4202 12:26:34.438866 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4203 12:26:34.442125 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4204 12:26:34.442212
4205 12:26:34.445604 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4206 12:26:34.448649 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4207 12:26:34.451684 [Gating] SW calibration Done
4208 12:26:34.451767 ==
4209 12:26:34.455004 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 12:26:34.458803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 12:26:34.458886 ==
4212 12:26:34.461881 RX Vref Scan: 0
4213 12:26:34.461963
4214 12:26:34.462028 RX Vref 0 -> 0, step: 1
4215 12:26:34.462090
4216 12:26:34.465137 RX Delay -230 -> 252, step: 16
4217 12:26:34.471417 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4218 12:26:34.474646 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4219 12:26:34.478419 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4220 12:26:34.481685 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4221 12:26:34.484849 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4222 12:26:34.491663 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4223 12:26:34.494889 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4224 12:26:34.497701 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4225 12:26:34.501395 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4226 12:26:34.507558 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4227 12:26:34.510852 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4228 12:26:34.514704 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4229 12:26:34.517733 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4230 12:26:34.524504 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4231 12:26:34.527663 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4232 12:26:34.530866 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4233 12:26:34.530950 ==
4234 12:26:34.534134 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 12:26:34.540372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 12:26:34.540457 ==
4237 12:26:34.540523 DQS Delay:
4238 12:26:34.544216 DQS0 = 0, DQS1 = 0
4239 12:26:34.544298 DQM Delay:
4240 12:26:34.544379 DQM0 = 44, DQM1 = 36
4241 12:26:34.547118 DQ Delay:
4242 12:26:34.550079 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4243 12:26:34.553683 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =49
4244 12:26:34.556854 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =33
4245 12:26:34.560479 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4246 12:26:34.560621
4247 12:26:34.560750
4248 12:26:34.560877 ==
4249 12:26:34.563580 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 12:26:34.566760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 12:26:34.566900 ==
4252 12:26:34.567025
4253 12:26:34.567152
4254 12:26:34.570096 TX Vref Scan disable
4255 12:26:34.573192 == TX Byte 0 ==
4256 12:26:34.577035 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4257 12:26:34.580210 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4258 12:26:34.583376 == TX Byte 1 ==
4259 12:26:34.586458 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4260 12:26:34.589623 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4261 12:26:34.589753 ==
4262 12:26:34.593399 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 12:26:34.596596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 12:26:34.599658 ==
4265 12:26:34.599771
4266 12:26:34.599863
4267 12:26:34.599955 TX Vref Scan disable
4268 12:26:34.603767 == TX Byte 0 ==
4269 12:26:34.607463 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4270 12:26:34.613901 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4271 12:26:34.614011 == TX Byte 1 ==
4272 12:26:34.617084 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4273 12:26:34.623763 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4274 12:26:34.623870
4275 12:26:34.623983 [DATLAT]
4276 12:26:34.624089 Freq=600, CH0 RK1
4277 12:26:34.624151
4278 12:26:34.626941 DATLAT Default: 0x9
4279 12:26:34.627053 0, 0xFFFF, sum = 0
4280 12:26:34.630574 1, 0xFFFF, sum = 0
4281 12:26:34.633636 2, 0xFFFF, sum = 0
4282 12:26:34.633751 3, 0xFFFF, sum = 0
4283 12:26:34.636778 4, 0xFFFF, sum = 0
4284 12:26:34.636885 5, 0xFFFF, sum = 0
4285 12:26:34.640019 6, 0xFFFF, sum = 0
4286 12:26:34.640136 7, 0xFFFF, sum = 0
4287 12:26:34.643623 8, 0x0, sum = 1
4288 12:26:34.643756 9, 0x0, sum = 2
4289 12:26:34.646658 10, 0x0, sum = 3
4290 12:26:34.646771 11, 0x0, sum = 4
4291 12:26:34.646873 best_step = 9
4292 12:26:34.646972
4293 12:26:34.650248 ==
4294 12:26:34.650327 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 12:26:34.656992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 12:26:34.657101 ==
4297 12:26:34.657200 RX Vref Scan: 0
4298 12:26:34.657299
4299 12:26:34.660130 RX Vref 0 -> 0, step: 1
4300 12:26:34.660207
4301 12:26:34.663384 RX Delay -195 -> 252, step: 8
4302 12:26:34.669670 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4303 12:26:34.673468 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4304 12:26:34.676632 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4305 12:26:34.679697 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4306 12:26:34.682968 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4307 12:26:34.689789 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4308 12:26:34.693108 iDelay=205, Bit 6, Center 48 (-99 ~ 196) 296
4309 12:26:34.696255 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4310 12:26:34.699302 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4311 12:26:34.705985 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4312 12:26:34.709499 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4313 12:26:34.712524 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4314 12:26:34.715666 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4315 12:26:34.722429 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4316 12:26:34.725596 iDelay=205, Bit 14, Center 44 (-115 ~ 204) 320
4317 12:26:34.729260 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4318 12:26:34.729351 ==
4319 12:26:34.732324 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 12:26:34.739153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 12:26:34.739235 ==
4322 12:26:34.739299 DQS Delay:
4323 12:26:34.739359 DQS0 = 0, DQS1 = 0
4324 12:26:34.742377 DQM Delay:
4325 12:26:34.742510 DQM0 = 40, DQM1 = 33
4326 12:26:34.745541 DQ Delay:
4327 12:26:34.749114 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4328 12:26:34.752169 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4329 12:26:34.752252 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4330 12:26:34.759001 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4331 12:26:34.759108
4332 12:26:34.759238
4333 12:26:34.765383 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c37, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4334 12:26:34.768354 CH0 RK1: MR19=808, MR18=3C37
4335 12:26:34.774744 CH0_RK1: MR19=0x808, MR18=0x3C37, DQSOSC=398, MR23=63, INC=165, DEC=110
4336 12:26:34.778415 [RxdqsGatingPostProcess] freq 600
4337 12:26:34.781637 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4338 12:26:34.784687 Pre-setting of DQS Precalculation
4339 12:26:34.791697 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4340 12:26:34.791807 ==
4341 12:26:34.794721 Dram Type= 6, Freq= 0, CH_1, rank 0
4342 12:26:34.798000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 12:26:34.798085 ==
4344 12:26:34.804242 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4345 12:26:34.811157 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4346 12:26:34.814679 [CA 0] Center 35 (5~66) winsize 62
4347 12:26:34.817739 [CA 1] Center 35 (5~66) winsize 62
4348 12:26:34.820791 [CA 2] Center 34 (4~65) winsize 62
4349 12:26:34.823948 [CA 3] Center 33 (3~64) winsize 62
4350 12:26:34.827679 [CA 4] Center 34 (4~65) winsize 62
4351 12:26:34.830799 [CA 5] Center 33 (3~64) winsize 62
4352 12:26:34.830870
4353 12:26:34.833879 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4354 12:26:34.833949
4355 12:26:34.837499 [CATrainingPosCal] consider 1 rank data
4356 12:26:34.840717 u2DelayCellTimex100 = 270/100 ps
4357 12:26:34.843702 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4358 12:26:34.847492 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4359 12:26:34.850633 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4360 12:26:34.853643 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4361 12:26:34.857104 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4362 12:26:34.863868 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4363 12:26:34.863945
4364 12:26:34.866704 CA PerBit enable=1, Macro0, CA PI delay=33
4365 12:26:34.866776
4366 12:26:34.870586 [CBTSetCACLKResult] CA Dly = 33
4367 12:26:34.870660 CS Dly: 5 (0~36)
4368 12:26:34.870723 ==
4369 12:26:34.873669 Dram Type= 6, Freq= 0, CH_1, rank 1
4370 12:26:34.879970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 12:26:34.880120 ==
4372 12:26:34.883331 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4373 12:26:34.889663 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4374 12:26:34.892816 [CA 0] Center 36 (6~66) winsize 61
4375 12:26:34.896548 [CA 1] Center 36 (6~66) winsize 61
4376 12:26:34.899861 [CA 2] Center 34 (4~65) winsize 62
4377 12:26:34.902911 [CA 3] Center 33 (3~64) winsize 62
4378 12:26:34.906165 [CA 4] Center 34 (4~65) winsize 62
4379 12:26:34.909362 [CA 5] Center 33 (3~64) winsize 62
4380 12:26:34.909445
4381 12:26:34.912597 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4382 12:26:34.912681
4383 12:26:34.916389 [CATrainingPosCal] consider 2 rank data
4384 12:26:34.919267 u2DelayCellTimex100 = 270/100 ps
4385 12:26:34.922976 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4386 12:26:34.929294 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4387 12:26:34.932481 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4388 12:26:34.935766 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4389 12:26:34.939352 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4390 12:26:34.942533 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4391 12:26:34.942610
4392 12:26:34.945557 CA PerBit enable=1, Macro0, CA PI delay=33
4393 12:26:34.945634
4394 12:26:34.948691 [CBTSetCACLKResult] CA Dly = 33
4395 12:26:34.952432 CS Dly: 5 (0~36)
4396 12:26:34.952512
4397 12:26:34.955709 ----->DramcWriteLeveling(PI) begin...
4398 12:26:34.955827 ==
4399 12:26:34.958603 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 12:26:34.962228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 12:26:34.962317 ==
4402 12:26:34.965390 Write leveling (Byte 0): 28 => 28
4403 12:26:34.968384 Write leveling (Byte 1): 32 => 32
4404 12:26:34.972193 DramcWriteLeveling(PI) end<-----
4405 12:26:34.972273
4406 12:26:34.972339 ==
4407 12:26:34.975266 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 12:26:34.978536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 12:26:34.978631 ==
4410 12:26:34.981632 [Gating] SW mode calibration
4411 12:26:34.988474 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4412 12:26:34.994984 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4413 12:26:34.998132 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 12:26:35.001980 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 12:26:35.008238 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4416 12:26:35.011302 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (1 1) (1 1)
4417 12:26:35.014487 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 12:26:35.021375 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 12:26:35.024350 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 12:26:35.027987 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 12:26:35.034425 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 12:26:35.037590 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 12:26:35.044233 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 12:26:35.047277 0 10 12 | B1->B0 | 3131 3a3a | 1 1 | (0 0) (0 0)
4425 12:26:35.050879 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 12:26:35.057241 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 12:26:35.060840 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 12:26:35.063950 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 12:26:35.070286 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 12:26:35.073781 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 12:26:35.076815 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 12:26:35.083740 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4433 12:26:35.086954 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4434 12:26:35.090053 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 12:26:35.096866 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 12:26:35.099893 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 12:26:35.103157 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 12:26:35.109587 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 12:26:35.113336 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 12:26:35.116495 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 12:26:35.123449 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 12:26:35.126474 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 12:26:35.129646 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 12:26:35.135912 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 12:26:35.139729 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 12:26:35.142957 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 12:26:35.149085 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 12:26:35.152896 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4449 12:26:35.155926 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 12:26:35.159181 Total UI for P1: 0, mck2ui 16
4451 12:26:35.162299 best dqsien dly found for B0: ( 0, 13, 14)
4452 12:26:35.165543 Total UI for P1: 0, mck2ui 16
4453 12:26:35.169205 best dqsien dly found for B1: ( 0, 13, 12)
4454 12:26:35.172476 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4455 12:26:35.175606 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4456 12:26:35.175680
4457 12:26:35.182136 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4458 12:26:35.185465 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4459 12:26:35.188545 [Gating] SW calibration Done
4460 12:26:35.188646 ==
4461 12:26:35.192279 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 12:26:35.195426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 12:26:35.195507 ==
4464 12:26:35.195581 RX Vref Scan: 0
4465 12:26:35.198537
4466 12:26:35.198611 RX Vref 0 -> 0, step: 1
4467 12:26:35.198702
4468 12:26:35.201732 RX Delay -230 -> 252, step: 16
4469 12:26:35.205474 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4470 12:26:35.211701 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4471 12:26:35.214900 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4472 12:26:35.218536 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4473 12:26:35.221773 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4474 12:26:35.228143 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4475 12:26:35.231339 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4476 12:26:35.234779 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4477 12:26:35.238301 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4478 12:26:35.241348 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4479 12:26:35.248203 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4480 12:26:35.251146 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4481 12:26:35.254366 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4482 12:26:35.258060 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4483 12:26:35.264309 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4484 12:26:35.267487 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4485 12:26:35.267564 ==
4486 12:26:35.271214 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 12:26:35.274317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 12:26:35.274388 ==
4489 12:26:35.277509 DQS Delay:
4490 12:26:35.277584 DQS0 = 0, DQS1 = 0
4491 12:26:35.280691 DQM Delay:
4492 12:26:35.280798 DQM0 = 42, DQM1 = 38
4493 12:26:35.280889 DQ Delay:
4494 12:26:35.283871 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =41
4495 12:26:35.287536 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4496 12:26:35.290666 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4497 12:26:35.293932 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4498 12:26:35.294005
4499 12:26:35.294073
4500 12:26:35.297584 ==
4501 12:26:35.300699 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 12:26:35.304023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 12:26:35.304137 ==
4504 12:26:35.304202
4505 12:26:35.304263
4506 12:26:35.307094 TX Vref Scan disable
4507 12:26:35.307159 == TX Byte 0 ==
4508 12:26:35.314090 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4509 12:26:35.317347 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4510 12:26:35.317420 == TX Byte 1 ==
4511 12:26:35.323593 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4512 12:26:35.326776 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4513 12:26:35.326853 ==
4514 12:26:35.330522 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 12:26:35.333646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 12:26:35.333719 ==
4517 12:26:35.333781
4518 12:26:35.333848
4519 12:26:35.336975 TX Vref Scan disable
4520 12:26:35.340140 == TX Byte 0 ==
4521 12:26:35.343564 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4522 12:26:35.346493 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4523 12:26:35.349932 == TX Byte 1 ==
4524 12:26:35.353011 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4525 12:26:35.359669 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4526 12:26:35.359751
4527 12:26:35.359816 [DATLAT]
4528 12:26:35.359876 Freq=600, CH1 RK0
4529 12:26:35.359935
4530 12:26:35.363354 DATLAT Default: 0x9
4531 12:26:35.363424 0, 0xFFFF, sum = 0
4532 12:26:35.366349 1, 0xFFFF, sum = 0
4533 12:26:35.366425 2, 0xFFFF, sum = 0
4534 12:26:35.370156 3, 0xFFFF, sum = 0
4535 12:26:35.373225 4, 0xFFFF, sum = 0
4536 12:26:35.373306 5, 0xFFFF, sum = 0
4537 12:26:35.376315 6, 0xFFFF, sum = 0
4538 12:26:35.376403 7, 0xFFFF, sum = 0
4539 12:26:35.379507 8, 0x0, sum = 1
4540 12:26:35.379590 9, 0x0, sum = 2
4541 12:26:35.379653 10, 0x0, sum = 3
4542 12:26:35.382682 11, 0x0, sum = 4
4543 12:26:35.382759 best_step = 9
4544 12:26:35.382839
4545 12:26:35.382926 ==
4546 12:26:35.386303 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 12:26:35.393058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 12:26:35.393157 ==
4549 12:26:35.393223 RX Vref Scan: 1
4550 12:26:35.393286
4551 12:26:35.396183 RX Vref 0 -> 0, step: 1
4552 12:26:35.396275
4553 12:26:35.399264 RX Delay -179 -> 252, step: 8
4554 12:26:35.399342
4555 12:26:35.403261 Set Vref, RX VrefLevel [Byte0]: 50
4556 12:26:35.406217 [Byte1]: 49
4557 12:26:35.406295
4558 12:26:35.409438 Final RX Vref Byte 0 = 50 to rank0
4559 12:26:35.412556 Final RX Vref Byte 1 = 49 to rank0
4560 12:26:35.415663 Final RX Vref Byte 0 = 50 to rank1
4561 12:26:35.419349 Final RX Vref Byte 1 = 49 to rank1==
4562 12:26:35.422638 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 12:26:35.425844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 12:26:35.428929 ==
4565 12:26:35.429012 DQS Delay:
4566 12:26:35.429113 DQS0 = 0, DQS1 = 0
4567 12:26:35.432284 DQM Delay:
4568 12:26:35.432368 DQM0 = 41, DQM1 = 34
4569 12:26:35.436028 DQ Delay:
4570 12:26:35.436153 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =40
4571 12:26:35.439251 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4572 12:26:35.442521 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4573 12:26:35.445484 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4574 12:26:35.448562
4575 12:26:35.448633
4576 12:26:35.455419 [DQSOSCAuto] RK0, (LSB)MR18= 0x2841, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
4577 12:26:35.458528 CH1 RK0: MR19=808, MR18=2841
4578 12:26:35.465299 CH1_RK0: MR19=0x808, MR18=0x2841, DQSOSC=397, MR23=63, INC=166, DEC=110
4579 12:26:35.465383
4580 12:26:35.468386 ----->DramcWriteLeveling(PI) begin...
4581 12:26:35.468461 ==
4582 12:26:35.471887 Dram Type= 6, Freq= 0, CH_1, rank 1
4583 12:26:35.475008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 12:26:35.475081 ==
4585 12:26:35.478124 Write leveling (Byte 0): 29 => 29
4586 12:26:35.482016 Write leveling (Byte 1): 30 => 30
4587 12:26:35.485167 DramcWriteLeveling(PI) end<-----
4588 12:26:35.485241
4589 12:26:35.485310 ==
4590 12:26:35.488280 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 12:26:35.491702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 12:26:35.491784 ==
4593 12:26:35.494839 [Gating] SW mode calibration
4594 12:26:35.501570 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4595 12:26:35.507932 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4596 12:26:35.510974 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 12:26:35.517935 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4598 12:26:35.520985 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4599 12:26:35.524147 0 9 12 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 0)
4600 12:26:35.531098 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4601 12:26:35.534292 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 12:26:35.537506 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 12:26:35.544251 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 12:26:35.547415 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 12:26:35.550672 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 12:26:35.557379 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4607 12:26:35.560632 0 10 12 | B1->B0 | 2c2c 4242 | 0 1 | (0 0) (0 0)
4608 12:26:35.563794 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 12:26:35.570406 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 12:26:35.573558 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 12:26:35.577217 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 12:26:35.583380 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 12:26:35.587016 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 12:26:35.590370 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 12:26:35.596903 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4616 12:26:35.600074 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 12:26:35.603683 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 12:26:35.609799 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 12:26:35.613088 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 12:26:35.616182 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 12:26:35.622917 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 12:26:35.626163 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 12:26:35.629421 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 12:26:35.636300 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 12:26:35.639488 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 12:26:35.642647 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 12:26:35.649466 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 12:26:35.652637 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 12:26:35.655768 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 12:26:35.662738 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 12:26:35.665792 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4632 12:26:35.668976 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 12:26:35.672488 Total UI for P1: 0, mck2ui 16
4634 12:26:35.675438 best dqsien dly found for B0: ( 0, 13, 12)
4635 12:26:35.679341 Total UI for P1: 0, mck2ui 16
4636 12:26:35.682498 best dqsien dly found for B1: ( 0, 13, 12)
4637 12:26:35.685608 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4638 12:26:35.692424 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4639 12:26:35.692508
4640 12:26:35.695552 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4641 12:26:35.698556 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4642 12:26:35.701657 [Gating] SW calibration Done
4643 12:26:35.701731 ==
4644 12:26:35.705313 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 12:26:35.708471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 12:26:35.708557 ==
4647 12:26:35.711661 RX Vref Scan: 0
4648 12:26:35.711744
4649 12:26:35.711808 RX Vref 0 -> 0, step: 1
4650 12:26:35.711868
4651 12:26:35.715302 RX Delay -230 -> 252, step: 16
4652 12:26:35.718542 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4653 12:26:35.724980 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4654 12:26:35.728132 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4655 12:26:35.731312 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4656 12:26:35.734577 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4657 12:26:35.741502 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4658 12:26:35.744809 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4659 12:26:35.747923 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4660 12:26:35.751548 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4661 12:26:35.757817 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4662 12:26:35.761012 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4663 12:26:35.764723 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4664 12:26:35.767414 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4665 12:26:35.774096 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4666 12:26:35.777791 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4667 12:26:35.781093 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4668 12:26:35.781408 ==
4669 12:26:35.784203 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 12:26:35.787441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 12:26:35.791346 ==
4672 12:26:35.791769 DQS Delay:
4673 12:26:35.792213 DQS0 = 0, DQS1 = 0
4674 12:26:35.794287 DQM Delay:
4675 12:26:35.794722 DQM0 = 42, DQM1 = 39
4676 12:26:35.797622 DQ Delay:
4677 12:26:35.800665 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4678 12:26:35.801171 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4679 12:26:35.804281 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4680 12:26:35.810400 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4681 12:26:35.810889
4682 12:26:35.811348
4683 12:26:35.811771 ==
4684 12:26:35.814252 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 12:26:35.817381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 12:26:35.817847 ==
4687 12:26:35.818303
4688 12:26:35.818728
4689 12:26:35.820308 TX Vref Scan disable
4690 12:26:35.820886 == TX Byte 0 ==
4691 12:26:35.827280 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4692 12:26:35.830548 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4693 12:26:35.831128 == TX Byte 1 ==
4694 12:26:35.837416 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4695 12:26:35.840504 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4696 12:26:35.841078 ==
4697 12:26:35.843774 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 12:26:35.846983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 12:26:35.847553 ==
4700 12:26:35.849813
4701 12:26:35.850392
4702 12:26:35.850861 TX Vref Scan disable
4703 12:26:35.853601 == TX Byte 0 ==
4704 12:26:35.857408 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4705 12:26:35.863794 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4706 12:26:35.864280 == TX Byte 1 ==
4707 12:26:35.866837 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4708 12:26:35.873582 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4709 12:26:35.874026
4710 12:26:35.874385 [DATLAT]
4711 12:26:35.874711 Freq=600, CH1 RK1
4712 12:26:35.875146
4713 12:26:35.876776 DATLAT Default: 0x9
4714 12:26:35.880348 0, 0xFFFF, sum = 0
4715 12:26:35.880807 1, 0xFFFF, sum = 0
4716 12:26:35.883156 2, 0xFFFF, sum = 0
4717 12:26:35.883655 3, 0xFFFF, sum = 0
4718 12:26:35.886857 4, 0xFFFF, sum = 0
4719 12:26:35.887486 5, 0xFFFF, sum = 0
4720 12:26:35.889895 6, 0xFFFF, sum = 0
4721 12:26:35.890354 7, 0xFFFF, sum = 0
4722 12:26:35.893221 8, 0x0, sum = 1
4723 12:26:35.893679 9, 0x0, sum = 2
4724 12:26:35.896276 10, 0x0, sum = 3
4725 12:26:35.896718 11, 0x0, sum = 4
4726 12:26:35.897160 best_step = 9
4727 12:26:35.897570
4728 12:26:35.900122 ==
4729 12:26:35.903366 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 12:26:35.906332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 12:26:35.906895 ==
4732 12:26:35.907421 RX Vref Scan: 0
4733 12:26:35.907929
4734 12:26:35.909472 RX Vref 0 -> 0, step: 1
4735 12:26:35.909905
4736 12:26:35.912965 RX Delay -179 -> 252, step: 8
4737 12:26:35.919694 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4738 12:26:35.922958 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4739 12:26:35.926221 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4740 12:26:35.929293 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4741 12:26:35.936137 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4742 12:26:35.939024 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4743 12:26:35.942486 iDelay=205, Bit 6, Center 40 (-115 ~ 196) 312
4744 12:26:35.945566 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4745 12:26:35.948750 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4746 12:26:35.955507 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4747 12:26:35.958690 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4748 12:26:35.962344 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4749 12:26:35.965566 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4750 12:26:35.971817 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4751 12:26:35.975605 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4752 12:26:35.978603 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4753 12:26:35.979084 ==
4754 12:26:35.982050 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 12:26:35.988558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 12:26:35.989006 ==
4757 12:26:35.989376 DQS Delay:
4758 12:26:35.991691 DQS0 = 0, DQS1 = 0
4759 12:26:35.992166 DQM Delay:
4760 12:26:35.992522 DQM0 = 36, DQM1 = 34
4761 12:26:35.995222 DQ Delay:
4762 12:26:35.998598 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4763 12:26:36.001614 DQ4 =36, DQ5 =48, DQ6 =40, DQ7 =32
4764 12:26:36.005270 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4765 12:26:36.008332 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4766 12:26:36.008764
4767 12:26:36.009120
4768 12:26:36.015182 [DQSOSCAuto] RK1, (LSB)MR18= 0x3156, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4769 12:26:36.018112 CH1 RK1: MR19=808, MR18=3156
4770 12:26:36.024826 CH1_RK1: MR19=0x808, MR18=0x3156, DQSOSC=393, MR23=63, INC=169, DEC=113
4771 12:26:36.027901 [RxdqsGatingPostProcess] freq 600
4772 12:26:36.031078 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4773 12:26:36.034527 Pre-setting of DQS Precalculation
4774 12:26:36.041205 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4775 12:26:36.047642 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4776 12:26:36.054545 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4777 12:26:36.054979
4778 12:26:36.055318
4779 12:26:36.057663 [Calibration Summary] 1200 Mbps
4780 12:26:36.060890 CH 0, Rank 0
4781 12:26:36.061322 SW Impedance : PASS
4782 12:26:36.064677 DUTY Scan : NO K
4783 12:26:36.067700 ZQ Calibration : PASS
4784 12:26:36.068181 Jitter Meter : NO K
4785 12:26:36.071004 CBT Training : PASS
4786 12:26:36.071502 Write leveling : PASS
4787 12:26:36.074001 RX DQS gating : PASS
4788 12:26:36.077284 RX DQ/DQS(RDDQC) : PASS
4789 12:26:36.077749 TX DQ/DQS : PASS
4790 12:26:36.081064 RX DATLAT : PASS
4791 12:26:36.084100 RX DQ/DQS(Engine): PASS
4792 12:26:36.084537 TX OE : NO K
4793 12:26:36.087086 All Pass.
4794 12:26:36.087511
4795 12:26:36.087851 CH 0, Rank 1
4796 12:26:36.090675 SW Impedance : PASS
4797 12:26:36.091097 DUTY Scan : NO K
4798 12:26:36.093768 ZQ Calibration : PASS
4799 12:26:36.096932 Jitter Meter : NO K
4800 12:26:36.097358 CBT Training : PASS
4801 12:26:36.100571 Write leveling : PASS
4802 12:26:36.103570 RX DQS gating : PASS
4803 12:26:36.103992 RX DQ/DQS(RDDQC) : PASS
4804 12:26:36.106715 TX DQ/DQS : PASS
4805 12:26:36.110318 RX DATLAT : PASS
4806 12:26:36.110763 RX DQ/DQS(Engine): PASS
4807 12:26:36.113525 TX OE : NO K
4808 12:26:36.113959 All Pass.
4809 12:26:36.114325
4810 12:26:36.116622 CH 1, Rank 0
4811 12:26:36.117072 SW Impedance : PASS
4812 12:26:36.120381 DUTY Scan : NO K
4813 12:26:36.123502 ZQ Calibration : PASS
4814 12:26:36.123934 Jitter Meter : NO K
4815 12:26:36.127004 CBT Training : PASS
4816 12:26:36.129977 Write leveling : PASS
4817 12:26:36.130585 RX DQS gating : PASS
4818 12:26:36.133545 RX DQ/DQS(RDDQC) : PASS
4819 12:26:36.136652 TX DQ/DQS : PASS
4820 12:26:36.137219 RX DATLAT : PASS
4821 12:26:36.139675 RX DQ/DQS(Engine): PASS
4822 12:26:36.142865 TX OE : NO K
4823 12:26:36.143495 All Pass.
4824 12:26:36.143959
4825 12:26:36.144347 CH 1, Rank 1
4826 12:26:36.146178 SW Impedance : PASS
4827 12:26:36.150185 DUTY Scan : NO K
4828 12:26:36.150728 ZQ Calibration : PASS
4829 12:26:36.153127 Jitter Meter : NO K
4830 12:26:36.156140 CBT Training : PASS
4831 12:26:36.156757 Write leveling : PASS
4832 12:26:36.159257 RX DQS gating : PASS
4833 12:26:36.159779 RX DQ/DQS(RDDQC) : PASS
4834 12:26:36.162986 TX DQ/DQS : PASS
4835 12:26:36.166269 RX DATLAT : PASS
4836 12:26:36.166833 RX DQ/DQS(Engine): PASS
4837 12:26:36.169364 TX OE : NO K
4838 12:26:36.169799 All Pass.
4839 12:26:36.170169
4840 12:26:36.173216 DramC Write-DBI off
4841 12:26:36.176374 PER_BANK_REFRESH: Hybrid Mode
4842 12:26:36.176828 TX_TRACKING: ON
4843 12:26:36.186002 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4844 12:26:36.189342 [FAST_K] Save calibration result to emmc
4845 12:26:36.192126 dramc_set_vcore_voltage set vcore to 662500
4846 12:26:36.195975 Read voltage for 933, 3
4847 12:26:36.196539 Vio18 = 0
4848 12:26:36.199053 Vcore = 662500
4849 12:26:36.199584 Vdram = 0
4850 12:26:36.199931 Vddq = 0
4851 12:26:36.200312 Vmddr = 0
4852 12:26:36.205397 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4853 12:26:36.211963 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4854 12:26:36.212433 MEM_TYPE=3, freq_sel=17
4855 12:26:36.215588 sv_algorithm_assistance_LP4_1600
4856 12:26:36.218816 ============ PULL DRAM RESETB DOWN ============
4857 12:26:36.225221 ========== PULL DRAM RESETB DOWN end =========
4858 12:26:36.228814 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4859 12:26:36.231874 ===================================
4860 12:26:36.235646 LPDDR4 DRAM CONFIGURATION
4861 12:26:36.238910 ===================================
4862 12:26:36.239338 EX_ROW_EN[0] = 0x0
4863 12:26:36.241954 EX_ROW_EN[1] = 0x0
4864 12:26:36.242386 LP4Y_EN = 0x0
4865 12:26:36.245085 WORK_FSP = 0x0
4866 12:26:36.248752 WL = 0x3
4867 12:26:36.249189 RL = 0x3
4868 12:26:36.251971 BL = 0x2
4869 12:26:36.252458 RPST = 0x0
4870 12:26:36.255228 RD_PRE = 0x0
4871 12:26:36.255650 WR_PRE = 0x1
4872 12:26:36.258406 WR_PST = 0x0
4873 12:26:36.258830 DBI_WR = 0x0
4874 12:26:36.261479 DBI_RD = 0x0
4875 12:26:36.261902 OTF = 0x1
4876 12:26:36.265429 ===================================
4877 12:26:36.268389 ===================================
4878 12:26:36.271591 ANA top config
4879 12:26:36.274717 ===================================
4880 12:26:36.275144 DLL_ASYNC_EN = 0
4881 12:26:36.277828 ALL_SLAVE_EN = 1
4882 12:26:36.281718 NEW_RANK_MODE = 1
4883 12:26:36.285002 DLL_IDLE_MODE = 1
4884 12:26:36.287977 LP45_APHY_COMB_EN = 1
4885 12:26:36.288461 TX_ODT_DIS = 1
4886 12:26:36.291602 NEW_8X_MODE = 1
4887 12:26:36.294836 ===================================
4888 12:26:36.297881 ===================================
4889 12:26:36.301004 data_rate = 1866
4890 12:26:36.304705 CKR = 1
4891 12:26:36.307847 DQ_P2S_RATIO = 8
4892 12:26:36.310791 ===================================
4893 12:26:36.314248 CA_P2S_RATIO = 8
4894 12:26:36.314676 DQ_CA_OPEN = 0
4895 12:26:36.317267 DQ_SEMI_OPEN = 0
4896 12:26:36.320764 CA_SEMI_OPEN = 0
4897 12:26:36.323751 CA_FULL_RATE = 0
4898 12:26:36.327736 DQ_CKDIV4_EN = 1
4899 12:26:36.330780 CA_CKDIV4_EN = 1
4900 12:26:36.331204 CA_PREDIV_EN = 0
4901 12:26:36.333623 PH8_DLY = 0
4902 12:26:36.337552 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4903 12:26:36.340727 DQ_AAMCK_DIV = 4
4904 12:26:36.343672 CA_AAMCK_DIV = 4
4905 12:26:36.346759 CA_ADMCK_DIV = 4
4906 12:26:36.350743 DQ_TRACK_CA_EN = 0
4907 12:26:36.351328 CA_PICK = 933
4908 12:26:36.353793 CA_MCKIO = 933
4909 12:26:36.357005 MCKIO_SEMI = 0
4910 12:26:36.360182 PLL_FREQ = 3732
4911 12:26:36.363285 DQ_UI_PI_RATIO = 32
4912 12:26:36.366388 CA_UI_PI_RATIO = 0
4913 12:26:36.370238 ===================================
4914 12:26:36.373606 ===================================
4915 12:26:36.376639 memory_type:LPDDR4
4916 12:26:36.377096 GP_NUM : 10
4917 12:26:36.379646 SRAM_EN : 1
4918 12:26:36.380116 MD32_EN : 0
4919 12:26:36.382903 ===================================
4920 12:26:36.386246 [ANA_INIT] >>>>>>>>>>>>>>
4921 12:26:36.389337 <<<<<< [CONFIGURE PHASE]: ANA_TX
4922 12:26:36.393052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4923 12:26:36.396075 ===================================
4924 12:26:36.399473 data_rate = 1866,PCW = 0X8f00
4925 12:26:36.402480 ===================================
4926 12:26:36.406064 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4927 12:26:36.412400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4928 12:26:36.415608 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4929 12:26:36.422372 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4930 12:26:36.425931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4931 12:26:36.428872 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4932 12:26:36.429295 [ANA_INIT] flow start
4933 12:26:36.432591 [ANA_INIT] PLL >>>>>>>>
4934 12:26:36.435750 [ANA_INIT] PLL <<<<<<<<
4935 12:26:36.439059 [ANA_INIT] MIDPI >>>>>>>>
4936 12:26:36.439480 [ANA_INIT] MIDPI <<<<<<<<
4937 12:26:36.441982 [ANA_INIT] DLL >>>>>>>>
4938 12:26:36.445599 [ANA_INIT] flow end
4939 12:26:36.448675 ============ LP4 DIFF to SE enter ============
4940 12:26:36.452335 ============ LP4 DIFF to SE exit ============
4941 12:26:36.455627 [ANA_INIT] <<<<<<<<<<<<<
4942 12:26:36.458800 [Flow] Enable top DCM control >>>>>
4943 12:26:36.462040 [Flow] Enable top DCM control <<<<<
4944 12:26:36.464971 Enable DLL master slave shuffle
4945 12:26:36.468878 ==============================================================
4946 12:26:36.472067 Gating Mode config
4947 12:26:36.478343 ==============================================================
4948 12:26:36.478770 Config description:
4949 12:26:36.487821 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4950 12:26:36.494853 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4951 12:26:36.498123 SELPH_MODE 0: By rank 1: By Phase
4952 12:26:36.504770 ==============================================================
4953 12:26:36.507828 GAT_TRACK_EN = 1
4954 12:26:36.511605 RX_GATING_MODE = 2
4955 12:26:36.514726 RX_GATING_TRACK_MODE = 2
4956 12:26:36.517954 SELPH_MODE = 1
4957 12:26:36.521126 PICG_EARLY_EN = 1
4958 12:26:36.524017 VALID_LAT_VALUE = 1
4959 12:26:36.527667 ==============================================================
4960 12:26:36.530735 Enter into Gating configuration >>>>
4961 12:26:36.534255 Exit from Gating configuration <<<<
4962 12:26:36.537119 Enter into DVFS_PRE_config >>>>>
4963 12:26:36.550634 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4964 12:26:36.553796 Exit from DVFS_PRE_config <<<<<
4965 12:26:36.557417 Enter into PICG configuration >>>>
4966 12:26:36.560492 Exit from PICG configuration <<<<
4967 12:26:36.561080 [RX_INPUT] configuration >>>>>
4968 12:26:36.563795 [RX_INPUT] configuration <<<<<
4969 12:26:36.570014 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4970 12:26:36.573968 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4971 12:26:36.580360 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4972 12:26:36.586573 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4973 12:26:36.593636 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4974 12:26:36.600117 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4975 12:26:36.603614 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4976 12:26:36.606618 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4977 12:26:36.613491 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4978 12:26:36.616689 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4979 12:26:36.619909 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4980 12:26:36.626066 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4981 12:26:36.629140 ===================================
4982 12:26:36.629554 LPDDR4 DRAM CONFIGURATION
4983 12:26:36.632803 ===================================
4984 12:26:36.635891 EX_ROW_EN[0] = 0x0
4985 12:26:36.636221 EX_ROW_EN[1] = 0x0
4986 12:26:36.639050 LP4Y_EN = 0x0
4987 12:26:36.642688 WORK_FSP = 0x0
4988 12:26:36.643096 WL = 0x3
4989 12:26:36.645747 RL = 0x3
4990 12:26:36.646054 BL = 0x2
4991 12:26:36.649054 RPST = 0x0
4992 12:26:36.649447 RD_PRE = 0x0
4993 12:26:36.652609 WR_PRE = 0x1
4994 12:26:36.652952 WR_PST = 0x0
4995 12:26:36.655662 DBI_WR = 0x0
4996 12:26:36.656009 DBI_RD = 0x0
4997 12:26:36.658918 OTF = 0x1
4998 12:26:36.662022 ===================================
4999 12:26:36.665267 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5000 12:26:36.668990 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5001 12:26:36.675355 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5002 12:26:36.678598 ===================================
5003 12:26:36.678986 LPDDR4 DRAM CONFIGURATION
5004 12:26:36.682167 ===================================
5005 12:26:36.685363 EX_ROW_EN[0] = 0x10
5006 12:26:36.688812 EX_ROW_EN[1] = 0x0
5007 12:26:36.689149 LP4Y_EN = 0x0
5008 12:26:36.692079 WORK_FSP = 0x0
5009 12:26:36.692408 WL = 0x3
5010 12:26:36.695182 RL = 0x3
5011 12:26:36.695547 BL = 0x2
5012 12:26:36.698291 RPST = 0x0
5013 12:26:36.698689 RD_PRE = 0x0
5014 12:26:36.701425 WR_PRE = 0x1
5015 12:26:36.701730 WR_PST = 0x0
5016 12:26:36.705365 DBI_WR = 0x0
5017 12:26:36.705799 DBI_RD = 0x0
5018 12:26:36.708484 OTF = 0x1
5019 12:26:36.711626 ===================================
5020 12:26:36.718429 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5021 12:26:36.721488 nWR fixed to 30
5022 12:26:36.724738 [ModeRegInit_LP4] CH0 RK0
5023 12:26:36.725176 [ModeRegInit_LP4] CH0 RK1
5024 12:26:36.728471 [ModeRegInit_LP4] CH1 RK0
5025 12:26:36.731594 [ModeRegInit_LP4] CH1 RK1
5026 12:26:36.732061 match AC timing 9
5027 12:26:36.738391 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5028 12:26:36.741360 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5029 12:26:36.745116 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5030 12:26:36.751522 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5031 12:26:36.754627 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5032 12:26:36.755032 ==
5033 12:26:36.757693 Dram Type= 6, Freq= 0, CH_0, rank 0
5034 12:26:36.761512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5035 12:26:36.762167 ==
5036 12:26:36.767955 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5037 12:26:36.774408 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5038 12:26:36.777672 [CA 0] Center 37 (7~68) winsize 62
5039 12:26:36.781276 [CA 1] Center 37 (7~68) winsize 62
5040 12:26:36.784635 [CA 2] Center 34 (4~64) winsize 61
5041 12:26:36.787686 [CA 3] Center 34 (4~65) winsize 62
5042 12:26:36.790652 [CA 4] Center 32 (2~63) winsize 62
5043 12:26:36.794624 [CA 5] Center 32 (2~63) winsize 62
5044 12:26:36.795171
5045 12:26:36.797761 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5046 12:26:36.798444
5047 12:26:36.800981 [CATrainingPosCal] consider 1 rank data
5048 12:26:36.804020 u2DelayCellTimex100 = 270/100 ps
5049 12:26:36.807791 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5050 12:26:36.811060 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5051 12:26:36.814114 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5052 12:26:36.817237 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5053 12:26:36.821038 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5054 12:26:36.827633 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5055 12:26:36.828098
5056 12:26:36.830745 CA PerBit enable=1, Macro0, CA PI delay=32
5057 12:26:36.831241
5058 12:26:36.833832 [CBTSetCACLKResult] CA Dly = 32
5059 12:26:36.834316 CS Dly: 5 (0~36)
5060 12:26:36.834661 ==
5061 12:26:36.836936 Dram Type= 6, Freq= 0, CH_0, rank 1
5062 12:26:36.843806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5063 12:26:36.844299 ==
5064 12:26:36.846859 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5065 12:26:36.853691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5066 12:26:36.856668 [CA 0] Center 38 (8~68) winsize 61
5067 12:26:36.859827 [CA 1] Center 37 (7~68) winsize 62
5068 12:26:36.863504 [CA 2] Center 34 (4~65) winsize 62
5069 12:26:36.866682 [CA 3] Center 34 (4~65) winsize 62
5070 12:26:36.870210 [CA 4] Center 33 (3~64) winsize 62
5071 12:26:36.873305 [CA 5] Center 32 (2~63) winsize 62
5072 12:26:36.873731
5073 12:26:36.876330 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5074 12:26:36.876792
5075 12:26:36.879472 [CATrainingPosCal] consider 2 rank data
5076 12:26:36.883115 u2DelayCellTimex100 = 270/100 ps
5077 12:26:36.886355 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5078 12:26:36.892818 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5079 12:26:36.895923 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5080 12:26:36.899157 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5081 12:26:36.902549 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5082 12:26:36.906312 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5083 12:26:36.906740
5084 12:26:36.909777 CA PerBit enable=1, Macro0, CA PI delay=32
5085 12:26:36.910435
5086 12:26:36.912732 [CBTSetCACLKResult] CA Dly = 32
5087 12:26:36.916125 CS Dly: 6 (0~39)
5088 12:26:36.916553
5089 12:26:36.919426 ----->DramcWriteLeveling(PI) begin...
5090 12:26:36.919863 ==
5091 12:26:36.922532 Dram Type= 6, Freq= 0, CH_0, rank 0
5092 12:26:36.925776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 12:26:36.926201 ==
5094 12:26:36.928919 Write leveling (Byte 0): 30 => 30
5095 12:26:36.932640 Write leveling (Byte 1): 28 => 28
5096 12:26:36.935699 DramcWriteLeveling(PI) end<-----
5097 12:26:36.936247
5098 12:26:36.936772 ==
5099 12:26:36.938881 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 12:26:36.942013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 12:26:36.942462 ==
5102 12:26:36.945769 [Gating] SW mode calibration
5103 12:26:36.951771 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5104 12:26:36.958809 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5105 12:26:36.962306 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5106 12:26:36.965507 0 14 4 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
5107 12:26:36.972098 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 12:26:36.975185 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 12:26:36.978215 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 12:26:36.985344 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 12:26:36.988516 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 12:26:36.991769 0 14 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
5113 12:26:36.998026 0 15 0 | B1->B0 | 3030 2424 | 1 0 | (1 0) (1 1)
5114 12:26:37.001216 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 12:26:37.004505 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 12:26:37.011343 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 12:26:37.014428 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 12:26:37.018405 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 12:26:37.024518 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 12:26:37.028072 0 15 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
5121 12:26:37.034247 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5122 12:26:37.037259 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 12:26:37.041002 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 12:26:37.047480 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 12:26:37.050627 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 12:26:37.053709 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 12:26:37.060501 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 12:26:37.063799 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5129 12:26:37.067302 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5130 12:26:37.073489 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 12:26:37.077182 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 12:26:37.080004 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 12:26:37.086931 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 12:26:37.090001 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 12:26:37.093196 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 12:26:37.100150 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 12:26:37.103375 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 12:26:37.106322 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 12:26:37.113055 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 12:26:37.116343 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 12:26:37.119473 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 12:26:37.126502 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 12:26:37.129367 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 12:26:37.132899 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5145 12:26:37.139256 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5146 12:26:37.139729 Total UI for P1: 0, mck2ui 16
5147 12:26:37.145911 best dqsien dly found for B0: ( 1, 2, 28)
5148 12:26:37.149246 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 12:26:37.152764 Total UI for P1: 0, mck2ui 16
5150 12:26:37.155720 best dqsien dly found for B1: ( 1, 3, 0)
5151 12:26:37.159513 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5152 12:26:37.162619 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5153 12:26:37.163182
5154 12:26:37.165739 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5155 12:26:37.169347 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5156 12:26:37.172369 [Gating] SW calibration Done
5157 12:26:37.173080 ==
5158 12:26:37.175302 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 12:26:37.178898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 12:26:37.182079 ==
5161 12:26:37.182516 RX Vref Scan: 0
5162 12:26:37.182864
5163 12:26:37.185867 RX Vref 0 -> 0, step: 1
5164 12:26:37.186353
5165 12:26:37.188810 RX Delay -80 -> 252, step: 8
5166 12:26:37.191849 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5167 12:26:37.195154 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5168 12:26:37.198349 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5169 12:26:37.202140 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5170 12:26:37.205404 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5171 12:26:37.211579 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5172 12:26:37.215305 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5173 12:26:37.218325 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5174 12:26:37.222300 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5175 12:26:37.224902 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5176 12:26:37.231463 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5177 12:26:37.234670 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5178 12:26:37.238363 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5179 12:26:37.241197 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5180 12:26:37.244371 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5181 12:26:37.248212 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5182 12:26:37.251354 ==
5183 12:26:37.254509 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 12:26:37.257656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 12:26:37.257736 ==
5186 12:26:37.257811 DQS Delay:
5187 12:26:37.260757 DQS0 = 0, DQS1 = 0
5188 12:26:37.260836 DQM Delay:
5189 12:26:37.264504 DQM0 = 100, DQM1 = 89
5190 12:26:37.264581 DQ Delay:
5191 12:26:37.267580 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5192 12:26:37.270588 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =111
5193 12:26:37.274440 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5194 12:26:37.277392 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5195 12:26:37.277476
5196 12:26:37.277542
5197 12:26:37.277603 ==
5198 12:26:37.281081 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 12:26:37.284236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 12:26:37.287185 ==
5201 12:26:37.287315
5202 12:26:37.287386
5203 12:26:37.287452 TX Vref Scan disable
5204 12:26:37.290869 == TX Byte 0 ==
5205 12:26:37.293846 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5206 12:26:37.297070 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5207 12:26:37.300496 == TX Byte 1 ==
5208 12:26:37.303692 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5209 12:26:37.306803 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5210 12:26:37.310108 ==
5211 12:26:37.313851 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 12:26:37.317115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 12:26:37.317234 ==
5214 12:26:37.317354
5215 12:26:37.317465
5216 12:26:37.320373 TX Vref Scan disable
5217 12:26:37.320504 == TX Byte 0 ==
5218 12:26:37.326589 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5219 12:26:37.330398 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5220 12:26:37.330562 == TX Byte 1 ==
5221 12:26:37.336921 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5222 12:26:37.339861 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5223 12:26:37.340103
5224 12:26:37.340325 [DATLAT]
5225 12:26:37.343472 Freq=933, CH0 RK0
5226 12:26:37.343692
5227 12:26:37.343960 DATLAT Default: 0xd
5228 12:26:37.346525 0, 0xFFFF, sum = 0
5229 12:26:37.349728 1, 0xFFFF, sum = 0
5230 12:26:37.350094 2, 0xFFFF, sum = 0
5231 12:26:37.353573 3, 0xFFFF, sum = 0
5232 12:26:37.354049 4, 0xFFFF, sum = 0
5233 12:26:37.357004 5, 0xFFFF, sum = 0
5234 12:26:37.357442 6, 0xFFFF, sum = 0
5235 12:26:37.359997 7, 0xFFFF, sum = 0
5236 12:26:37.360470 8, 0xFFFF, sum = 0
5237 12:26:37.363120 9, 0xFFFF, sum = 0
5238 12:26:37.363688 10, 0x0, sum = 1
5239 12:26:37.366365 11, 0x0, sum = 2
5240 12:26:37.366940 12, 0x0, sum = 3
5241 12:26:37.369974 13, 0x0, sum = 4
5242 12:26:37.370538 best_step = 11
5243 12:26:37.370888
5244 12:26:37.371212 ==
5245 12:26:37.373085 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 12:26:37.376279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 12:26:37.376715 ==
5248 12:26:37.379861 RX Vref Scan: 1
5249 12:26:37.380407
5250 12:26:37.382807 RX Vref 0 -> 0, step: 1
5251 12:26:37.383239
5252 12:26:37.383658 RX Delay -61 -> 252, step: 4
5253 12:26:37.386114
5254 12:26:37.386669 Set Vref, RX VrefLevel [Byte0]: 51
5255 12:26:37.389639 [Byte1]: 58
5256 12:26:37.394619
5257 12:26:37.395120 Final RX Vref Byte 0 = 51 to rank0
5258 12:26:37.398290 Final RX Vref Byte 1 = 58 to rank0
5259 12:26:37.401416 Final RX Vref Byte 0 = 51 to rank1
5260 12:26:37.404542 Final RX Vref Byte 1 = 58 to rank1==
5261 12:26:37.407884 Dram Type= 6, Freq= 0, CH_0, rank 0
5262 12:26:37.414281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5263 12:26:37.414712 ==
5264 12:26:37.415058 DQS Delay:
5265 12:26:37.418046 DQS0 = 0, DQS1 = 0
5266 12:26:37.418473 DQM Delay:
5267 12:26:37.418818 DQM0 = 99, DQM1 = 87
5268 12:26:37.420953 DQ Delay:
5269 12:26:37.424093 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5270 12:26:37.427050 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =104
5271 12:26:37.430895 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =82
5272 12:26:37.434234 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =94
5273 12:26:37.434829
5274 12:26:37.435193
5275 12:26:37.440588 [DQSOSCAuto] RK0, (LSB)MR18= 0x1510, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5276 12:26:37.443546 CH0 RK0: MR19=505, MR18=1510
5277 12:26:37.450346 CH0_RK0: MR19=0x505, MR18=0x1510, DQSOSC=415, MR23=63, INC=62, DEC=41
5278 12:26:37.450785
5279 12:26:37.454141 ----->DramcWriteLeveling(PI) begin...
5280 12:26:37.454573 ==
5281 12:26:37.457319 Dram Type= 6, Freq= 0, CH_0, rank 1
5282 12:26:37.460447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 12:26:37.463392 ==
5284 12:26:37.463970 Write leveling (Byte 0): 34 => 34
5285 12:26:37.466642 Write leveling (Byte 1): 27 => 27
5286 12:26:37.469478 DramcWriteLeveling(PI) end<-----
5287 12:26:37.469562
5288 12:26:37.469630 ==
5289 12:26:37.473345 Dram Type= 6, Freq= 0, CH_0, rank 1
5290 12:26:37.479497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 12:26:37.479584 ==
5292 12:26:37.483363 [Gating] SW mode calibration
5293 12:26:37.489536 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5294 12:26:37.492983 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5295 12:26:37.499135 0 14 0 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
5296 12:26:37.502798 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 12:26:37.505976 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 12:26:37.512547 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 12:26:37.515711 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 12:26:37.519323 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 12:26:37.525642 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5302 12:26:37.528827 0 14 28 | B1->B0 | 3434 2626 | 0 1 | (0 0) (0 0)
5303 12:26:37.532026 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5304 12:26:37.538966 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5305 12:26:37.542154 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 12:26:37.545478 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 12:26:37.552028 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 12:26:37.555127 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 12:26:37.558789 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5310 12:26:37.565149 0 15 28 | B1->B0 | 2828 4444 | 0 0 | (0 0) (0 0)
5311 12:26:37.568390 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5312 12:26:37.571813 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 12:26:37.578572 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 12:26:37.581739 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 12:26:37.585000 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 12:26:37.591695 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 12:26:37.594763 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5318 12:26:37.597678 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5319 12:26:37.604599 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5320 12:26:37.607749 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 12:26:37.610974 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 12:26:37.618066 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 12:26:37.621171 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 12:26:37.624257 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 12:26:37.631059 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 12:26:37.634256 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 12:26:37.637611 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 12:26:37.644638 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 12:26:37.647683 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 12:26:37.650935 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 12:26:37.657165 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 12:26:37.661028 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 12:26:37.664179 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 12:26:37.670516 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5335 12:26:37.670619 Total UI for P1: 0, mck2ui 16
5336 12:26:37.677505 best dqsien dly found for B0: ( 1, 2, 26)
5337 12:26:37.680444 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5338 12:26:37.683496 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 12:26:37.687127 Total UI for P1: 0, mck2ui 16
5340 12:26:37.690208 best dqsien dly found for B1: ( 1, 3, 0)
5341 12:26:37.693412 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5342 12:26:37.697052 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5343 12:26:37.697137
5344 12:26:37.703744 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5345 12:26:37.706899 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5346 12:26:37.709876 [Gating] SW calibration Done
5347 12:26:37.709962 ==
5348 12:26:37.713128 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 12:26:37.716894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 12:26:37.716976 ==
5351 12:26:37.717042 RX Vref Scan: 0
5352 12:26:37.717104
5353 12:26:37.720164 RX Vref 0 -> 0, step: 1
5354 12:26:37.720246
5355 12:26:37.723156 RX Delay -80 -> 252, step: 8
5356 12:26:37.726383 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5357 12:26:37.730056 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5358 12:26:37.733247 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5359 12:26:37.739625 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5360 12:26:37.742747 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5361 12:26:37.746555 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5362 12:26:37.749780 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5363 12:26:37.752828 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5364 12:26:37.756155 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5365 12:26:37.763094 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5366 12:26:37.765981 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5367 12:26:37.769140 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5368 12:26:37.773037 iDelay=200, Bit 12, Center 95 (8 ~ 183) 176
5369 12:26:37.776167 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5370 12:26:37.782335 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5371 12:26:37.786033 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5372 12:26:37.786118 ==
5373 12:26:37.789247 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 12:26:37.792441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 12:26:37.792525 ==
5376 12:26:37.792592 DQS Delay:
5377 12:26:37.795739 DQS0 = 0, DQS1 = 0
5378 12:26:37.795814 DQM Delay:
5379 12:26:37.798753 DQM0 = 97, DQM1 = 90
5380 12:26:37.798828 DQ Delay:
5381 12:26:37.802397 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5382 12:26:37.805522 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5383 12:26:37.809132 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5384 12:26:37.812123 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5385 12:26:37.812198
5386 12:26:37.812260
5387 12:26:37.812319 ==
5388 12:26:37.815226 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 12:26:37.821785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 12:26:37.821872 ==
5391 12:26:37.821941
5392 12:26:37.822002
5393 12:26:37.822096 TX Vref Scan disable
5394 12:26:37.825499 == TX Byte 0 ==
5395 12:26:37.828723 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5396 12:26:37.835879 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5397 12:26:37.835989 == TX Byte 1 ==
5398 12:26:37.838459 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5399 12:26:37.845303 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5400 12:26:37.845428 ==
5401 12:26:37.848622 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 12:26:37.851759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 12:26:37.851866 ==
5404 12:26:37.851984
5405 12:26:37.852107
5406 12:26:37.854819 TX Vref Scan disable
5407 12:26:37.858080 == TX Byte 0 ==
5408 12:26:37.861270 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5409 12:26:37.865077 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5410 12:26:37.868594 == TX Byte 1 ==
5411 12:26:37.871601 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5412 12:26:37.874531 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5413 12:26:37.874614
5414 12:26:37.878378 [DATLAT]
5415 12:26:37.878460 Freq=933, CH0 RK1
5416 12:26:37.878602
5417 12:26:37.881487 DATLAT Default: 0xb
5418 12:26:37.881572 0, 0xFFFF, sum = 0
5419 12:26:37.884649 1, 0xFFFF, sum = 0
5420 12:26:37.884765 2, 0xFFFF, sum = 0
5421 12:26:37.887674 3, 0xFFFF, sum = 0
5422 12:26:37.887757 4, 0xFFFF, sum = 0
5423 12:26:37.891042 5, 0xFFFF, sum = 0
5424 12:26:37.891126 6, 0xFFFF, sum = 0
5425 12:26:37.894242 7, 0xFFFF, sum = 0
5426 12:26:37.894326 8, 0xFFFF, sum = 0
5427 12:26:37.897989 9, 0xFFFF, sum = 0
5428 12:26:37.898089 10, 0x0, sum = 1
5429 12:26:37.901179 11, 0x0, sum = 2
5430 12:26:37.901262 12, 0x0, sum = 3
5431 12:26:37.904170 13, 0x0, sum = 4
5432 12:26:37.904270 best_step = 11
5433 12:26:37.904352
5434 12:26:37.904414 ==
5435 12:26:37.907209 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 12:26:37.914022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 12:26:37.914131 ==
5438 12:26:37.914226 RX Vref Scan: 0
5439 12:26:37.914315
5440 12:26:37.917237 RX Vref 0 -> 0, step: 1
5441 12:26:37.917319
5442 12:26:37.920950 RX Delay -53 -> 252, step: 4
5443 12:26:37.924296 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5444 12:26:37.927536 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5445 12:26:37.933767 iDelay=195, Bit 2, Center 94 (3 ~ 186) 184
5446 12:26:37.937082 iDelay=195, Bit 3, Center 94 (7 ~ 182) 176
5447 12:26:37.940749 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5448 12:26:37.943858 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5449 12:26:37.947088 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5450 12:26:37.953438 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5451 12:26:37.956547 iDelay=195, Bit 8, Center 78 (-9 ~ 166) 176
5452 12:26:37.960509 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5453 12:26:37.962977 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5454 12:26:37.966712 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5455 12:26:37.973052 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5456 12:26:37.976579 iDelay=195, Bit 13, Center 94 (3 ~ 186) 184
5457 12:26:37.979727 iDelay=195, Bit 14, Center 102 (15 ~ 190) 176
5458 12:26:37.982806 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5459 12:26:37.982913 ==
5460 12:26:37.986437 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 12:26:37.989481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 12:26:37.992729 ==
5463 12:26:37.992814 DQS Delay:
5464 12:26:37.992881 DQS0 = 0, DQS1 = 0
5465 12:26:37.996469 DQM Delay:
5466 12:26:37.996552 DQM0 = 97, DQM1 = 89
5467 12:26:37.999654 DQ Delay:
5468 12:26:38.002747 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5469 12:26:38.006364 DQ4 =102, DQ5 =86, DQ6 =104, DQ7 =106
5470 12:26:38.009311 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =84
5471 12:26:38.012316 DQ12 =94, DQ13 =94, DQ14 =102, DQ15 =94
5472 12:26:38.012404
5473 12:26:38.012470
5474 12:26:38.019008 [DQSOSCAuto] RK1, (LSB)MR18= 0x1310, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5475 12:26:38.022179 CH0 RK1: MR19=505, MR18=1310
5476 12:26:38.029157 CH0_RK1: MR19=0x505, MR18=0x1310, DQSOSC=415, MR23=63, INC=62, DEC=41
5477 12:26:38.032334 [RxdqsGatingPostProcess] freq 933
5478 12:26:38.035381 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5479 12:26:38.038505 best DQS0 dly(2T, 0.5T) = (0, 10)
5480 12:26:38.042426 best DQS1 dly(2T, 0.5T) = (0, 11)
5481 12:26:38.045513 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5482 12:26:38.048619 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5483 12:26:38.051996 best DQS0 dly(2T, 0.5T) = (0, 10)
5484 12:26:38.055043 best DQS1 dly(2T, 0.5T) = (0, 11)
5485 12:26:38.058841 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5486 12:26:38.061836 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5487 12:26:38.065015 Pre-setting of DQS Precalculation
5488 12:26:38.071835 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5489 12:26:38.071919 ==
5490 12:26:38.075005 Dram Type= 6, Freq= 0, CH_1, rank 0
5491 12:26:38.078253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 12:26:38.078337 ==
5493 12:26:38.084972 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5494 12:26:38.087990 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5495 12:26:38.091897 [CA 0] Center 36 (6~67) winsize 62
5496 12:26:38.095661 [CA 1] Center 36 (6~67) winsize 62
5497 12:26:38.098757 [CA 2] Center 34 (4~65) winsize 62
5498 12:26:38.101921 [CA 3] Center 34 (3~65) winsize 63
5499 12:26:38.105680 [CA 4] Center 34 (4~65) winsize 62
5500 12:26:38.108870 [CA 5] Center 33 (3~64) winsize 62
5501 12:26:38.108971
5502 12:26:38.111918 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5503 12:26:38.112017
5504 12:26:38.114986 [CATrainingPosCal] consider 1 rank data
5505 12:26:38.118492 u2DelayCellTimex100 = 270/100 ps
5506 12:26:38.121577 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5507 12:26:38.128390 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5508 12:26:38.131589 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5509 12:26:38.134750 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5510 12:26:38.138057 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5511 12:26:38.141296 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5512 12:26:38.141380
5513 12:26:38.144544 CA PerBit enable=1, Macro0, CA PI delay=33
5514 12:26:38.144626
5515 12:26:38.147719 [CBTSetCACLKResult] CA Dly = 33
5516 12:26:38.151565 CS Dly: 5 (0~36)
5517 12:26:38.151649 ==
5518 12:26:38.154571 Dram Type= 6, Freq= 0, CH_1, rank 1
5519 12:26:38.157810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 12:26:38.157908 ==
5521 12:26:38.164190 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5522 12:26:38.170593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5523 12:26:38.174459 [CA 0] Center 36 (6~67) winsize 62
5524 12:26:38.177625 [CA 1] Center 36 (6~67) winsize 62
5525 12:26:38.180636 [CA 2] Center 34 (4~65) winsize 62
5526 12:26:38.184356 [CA 3] Center 33 (3~64) winsize 62
5527 12:26:38.187015 [CA 4] Center 33 (3~64) winsize 62
5528 12:26:38.190534 [CA 5] Center 33 (3~64) winsize 62
5529 12:26:38.190618
5530 12:26:38.193705 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5531 12:26:38.193788
5532 12:26:38.197598 [CATrainingPosCal] consider 2 rank data
5533 12:26:38.200751 u2DelayCellTimex100 = 270/100 ps
5534 12:26:38.204022 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5535 12:26:38.207292 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5536 12:26:38.210551 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5537 12:26:38.213593 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5538 12:26:38.217156 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5539 12:26:38.220212 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5540 12:26:38.220295
5541 12:26:38.226899 CA PerBit enable=1, Macro0, CA PI delay=33
5542 12:26:38.227022
5543 12:26:38.227090 [CBTSetCACLKResult] CA Dly = 33
5544 12:26:38.230107 CS Dly: 6 (0~38)
5545 12:26:38.230191
5546 12:26:38.233406 ----->DramcWriteLeveling(PI) begin...
5547 12:26:38.233491 ==
5548 12:26:38.236835 Dram Type= 6, Freq= 0, CH_1, rank 0
5549 12:26:38.239969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 12:26:38.240076 ==
5551 12:26:38.243168 Write leveling (Byte 0): 27 => 27
5552 12:26:38.246502 Write leveling (Byte 1): 27 => 27
5553 12:26:38.249750 DramcWriteLeveling(PI) end<-----
5554 12:26:38.249834
5555 12:26:38.249899 ==
5556 12:26:38.253480 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 12:26:38.259871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 12:26:38.259993 ==
5559 12:26:38.260120 [Gating] SW mode calibration
5560 12:26:38.269448 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5561 12:26:38.273115 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5562 12:26:38.279440 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5563 12:26:38.282569 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 12:26:38.286207 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 12:26:38.293010 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 12:26:38.295980 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 12:26:38.299346 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 12:26:38.305644 0 14 24 | B1->B0 | 3333 3333 | 1 0 | (1 0) (0 1)
5569 12:26:38.308816 0 14 28 | B1->B0 | 2c2c 2727 | 0 0 | (0 1) (1 0)
5570 12:26:38.312467 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 12:26:38.318982 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 12:26:38.322088 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 12:26:38.325638 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 12:26:38.331861 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 12:26:38.335547 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 12:26:38.338601 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5577 12:26:38.345462 0 15 28 | B1->B0 | 3535 3d3d | 0 0 | (1 1) (0 0)
5578 12:26:38.348652 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 12:26:38.351664 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 12:26:38.358592 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 12:26:38.361879 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 12:26:38.365172 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 12:26:38.371468 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 12:26:38.374671 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5585 12:26:38.377859 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5586 12:26:38.384831 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 12:26:38.387944 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 12:26:38.391105 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 12:26:38.397963 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 12:26:38.400721 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 12:26:38.404564 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 12:26:38.410755 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 12:26:38.414001 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 12:26:38.417648 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 12:26:38.423924 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 12:26:38.427570 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 12:26:38.430488 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 12:26:38.437475 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 12:26:38.440527 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 12:26:38.443762 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 12:26:38.450528 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5602 12:26:38.453766 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 12:26:38.456867 Total UI for P1: 0, mck2ui 16
5604 12:26:38.460027 best dqsien dly found for B0: ( 1, 2, 28)
5605 12:26:38.463812 Total UI for P1: 0, mck2ui 16
5606 12:26:38.466965 best dqsien dly found for B1: ( 1, 2, 28)
5607 12:26:38.470212 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5608 12:26:38.473569 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5609 12:26:38.473681
5610 12:26:38.476806 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5611 12:26:38.480237 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5612 12:26:38.483255 [Gating] SW calibration Done
5613 12:26:38.483364 ==
5614 12:26:38.486488 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 12:26:38.492828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 12:26:38.492964 ==
5617 12:26:38.493061 RX Vref Scan: 0
5618 12:26:38.493171
5619 12:26:38.496634 RX Vref 0 -> 0, step: 1
5620 12:26:38.496733
5621 12:26:38.499760 RX Delay -80 -> 252, step: 8
5622 12:26:38.502589 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5623 12:26:38.506496 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5624 12:26:38.509627 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5625 12:26:38.512959 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5626 12:26:38.519387 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5627 12:26:38.522583 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5628 12:26:38.525878 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5629 12:26:38.528964 iDelay=208, Bit 7, Center 91 (0 ~ 183) 184
5630 12:26:38.532582 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5631 12:26:38.538950 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5632 12:26:38.542110 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5633 12:26:38.545273 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5634 12:26:38.548910 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5635 12:26:38.552025 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5636 12:26:38.558541 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5637 12:26:38.562221 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5638 12:26:38.562308 ==
5639 12:26:38.565482 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 12:26:38.568606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 12:26:38.568699 ==
5642 12:26:38.571636 DQS Delay:
5643 12:26:38.571720 DQS0 = 0, DQS1 = 0
5644 12:26:38.571787 DQM Delay:
5645 12:26:38.574817 DQM0 = 99, DQM1 = 95
5646 12:26:38.574902 DQ Delay:
5647 12:26:38.578609 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =103
5648 12:26:38.581741 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =91
5649 12:26:38.585036 DQ8 =83, DQ9 =87, DQ10 =91, DQ11 =87
5650 12:26:38.588058 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5651 12:26:38.588159
5652 12:26:38.588226
5653 12:26:38.591843 ==
5654 12:26:38.595155 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 12:26:38.598352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 12:26:38.598438 ==
5657 12:26:38.598506
5658 12:26:38.598568
5659 12:26:38.601398 TX Vref Scan disable
5660 12:26:38.601482 == TX Byte 0 ==
5661 12:26:38.608071 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5662 12:26:38.611132 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5663 12:26:38.611218 == TX Byte 1 ==
5664 12:26:38.618269 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5665 12:26:38.621357 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5666 12:26:38.621481 ==
5667 12:26:38.624513 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 12:26:38.627809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 12:26:38.627915 ==
5670 12:26:38.628018
5671 12:26:38.628133
5672 12:26:38.631392 TX Vref Scan disable
5673 12:26:38.634444 == TX Byte 0 ==
5674 12:26:38.637574 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5675 12:26:38.641283 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5676 12:26:38.644394 == TX Byte 1 ==
5677 12:26:38.648188 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5678 12:26:38.651259 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5679 12:26:38.651344
5680 12:26:38.654353 [DATLAT]
5681 12:26:38.654437 Freq=933, CH1 RK0
5682 12:26:38.654514
5683 12:26:38.657544 DATLAT Default: 0xd
5684 12:26:38.657628 0, 0xFFFF, sum = 0
5685 12:26:38.660636 1, 0xFFFF, sum = 0
5686 12:26:38.660723 2, 0xFFFF, sum = 0
5687 12:26:38.664583 3, 0xFFFF, sum = 0
5688 12:26:38.664668 4, 0xFFFF, sum = 0
5689 12:26:38.667781 5, 0xFFFF, sum = 0
5690 12:26:38.667865 6, 0xFFFF, sum = 0
5691 12:26:38.670848 7, 0xFFFF, sum = 0
5692 12:26:38.670933 8, 0xFFFF, sum = 0
5693 12:26:38.674200 9, 0xFFFF, sum = 0
5694 12:26:38.674285 10, 0x0, sum = 1
5695 12:26:38.677314 11, 0x0, sum = 2
5696 12:26:38.677399 12, 0x0, sum = 3
5697 12:26:38.680668 13, 0x0, sum = 4
5698 12:26:38.680780 best_step = 11
5699 12:26:38.680873
5700 12:26:38.680963 ==
5701 12:26:38.683813 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 12:26:38.690152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 12:26:38.690236 ==
5704 12:26:38.690303 RX Vref Scan: 1
5705 12:26:38.690364
5706 12:26:38.693981 RX Vref 0 -> 0, step: 1
5707 12:26:38.694089
5708 12:26:38.697028 RX Delay -53 -> 252, step: 4
5709 12:26:38.697111
5710 12:26:38.700224 Set Vref, RX VrefLevel [Byte0]: 50
5711 12:26:38.703343 [Byte1]: 49
5712 12:26:38.703427
5713 12:26:38.706450 Final RX Vref Byte 0 = 50 to rank0
5714 12:26:38.710081 Final RX Vref Byte 1 = 49 to rank0
5715 12:26:38.713540 Final RX Vref Byte 0 = 50 to rank1
5716 12:26:38.716493 Final RX Vref Byte 1 = 49 to rank1==
5717 12:26:38.720276 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 12:26:38.723072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 12:26:38.726228 ==
5720 12:26:38.726311 DQS Delay:
5721 12:26:38.726377 DQS0 = 0, DQS1 = 0
5722 12:26:38.729976 DQM Delay:
5723 12:26:38.730059 DQM0 = 98, DQM1 = 94
5724 12:26:38.733240 DQ Delay:
5725 12:26:38.736481 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =98
5726 12:26:38.739528 DQ4 =94, DQ5 =108, DQ6 =110, DQ7 =94
5727 12:26:38.743212 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5728 12:26:38.746260 DQ12 =104, DQ13 =102, DQ14 =100, DQ15 =102
5729 12:26:38.746343
5730 12:26:38.746409
5731 12:26:38.753043 [DQSOSCAuto] RK0, (LSB)MR18= 0x514, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 420 ps
5732 12:26:38.755884 CH1 RK0: MR19=505, MR18=514
5733 12:26:38.762659 CH1_RK0: MR19=0x505, MR18=0x514, DQSOSC=415, MR23=63, INC=62, DEC=41
5734 12:26:38.762742
5735 12:26:38.766043 ----->DramcWriteLeveling(PI) begin...
5736 12:26:38.766127 ==
5737 12:26:38.769088 Dram Type= 6, Freq= 0, CH_1, rank 1
5738 12:26:38.772785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 12:26:38.772869 ==
5740 12:26:38.775926 Write leveling (Byte 0): 26 => 26
5741 12:26:38.779195 Write leveling (Byte 1): 27 => 27
5742 12:26:38.782347 DramcWriteLeveling(PI) end<-----
5743 12:26:38.782429
5744 12:26:38.782494 ==
5745 12:26:38.786024 Dram Type= 6, Freq= 0, CH_1, rank 1
5746 12:26:38.789144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 12:26:38.792324 ==
5748 12:26:38.792407 [Gating] SW mode calibration
5749 12:26:38.802600 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5750 12:26:38.805629 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5751 12:26:38.808830 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5752 12:26:38.815469 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 12:26:38.818574 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 12:26:38.822085 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 12:26:38.828328 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 12:26:38.831671 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 12:26:38.835293 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5758 12:26:38.841520 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5759 12:26:38.845122 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 12:26:38.848312 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 12:26:38.855082 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 12:26:38.858147 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 12:26:38.861188 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 12:26:38.867851 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 12:26:38.870923 0 15 24 | B1->B0 | 2525 3636 | 1 1 | (0 0) (0 0)
5766 12:26:38.874707 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5767 12:26:38.881115 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 12:26:38.884355 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 12:26:38.887523 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 12:26:38.894053 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 12:26:38.897719 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 12:26:38.900803 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 12:26:38.907348 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 12:26:38.910962 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5775 12:26:38.914163 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5776 12:26:38.920448 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 12:26:38.923493 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 12:26:38.927282 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 12:26:38.933597 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 12:26:38.936776 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 12:26:38.940653 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 12:26:38.946816 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 12:26:38.950343 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 12:26:38.953480 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 12:26:38.959664 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 12:26:38.962985 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 12:26:38.969661 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 12:26:38.973394 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 12:26:38.976462 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5790 12:26:38.982908 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5791 12:26:38.982993 Total UI for P1: 0, mck2ui 16
5792 12:26:38.989937 best dqsien dly found for B0: ( 1, 2, 24)
5793 12:26:38.992979 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 12:26:38.995965 Total UI for P1: 0, mck2ui 16
5795 12:26:38.999237 best dqsien dly found for B1: ( 1, 2, 28)
5796 12:26:39.002816 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5797 12:26:39.006183 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5798 12:26:39.006286
5799 12:26:39.009505 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5800 12:26:39.012697 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5801 12:26:39.015780 [Gating] SW calibration Done
5802 12:26:39.015906 ==
5803 12:26:39.019114 Dram Type= 6, Freq= 0, CH_1, rank 1
5804 12:26:39.022638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 12:26:39.025789 ==
5806 12:26:39.025944 RX Vref Scan: 0
5807 12:26:39.026069
5808 12:26:39.028924 RX Vref 0 -> 0, step: 1
5809 12:26:39.029127
5810 12:26:39.032017 RX Delay -80 -> 252, step: 8
5811 12:26:39.035561 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5812 12:26:39.038941 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5813 12:26:39.041996 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5814 12:26:39.045309 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5815 12:26:39.049021 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5816 12:26:39.055236 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5817 12:26:39.058990 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5818 12:26:39.062100 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5819 12:26:39.065250 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5820 12:26:39.068457 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5821 12:26:39.071996 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5822 12:26:39.078233 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5823 12:26:39.081514 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5824 12:26:39.084723 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5825 12:26:39.088544 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5826 12:26:39.091706 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5827 12:26:39.094875 ==
5828 12:26:39.098210 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 12:26:39.101377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 12:26:39.101508 ==
5831 12:26:39.101625 DQS Delay:
5832 12:26:39.104622 DQS0 = 0, DQS1 = 0
5833 12:26:39.104715 DQM Delay:
5834 12:26:39.107826 DQM0 = 97, DQM1 = 94
5835 12:26:39.107956 DQ Delay:
5836 12:26:39.111009 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5837 12:26:39.114578 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5838 12:26:39.117857 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5839 12:26:39.121071 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5840 12:26:39.121498
5841 12:26:39.121834
5842 12:26:39.122144 ==
5843 12:26:39.124765 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 12:26:39.127743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 12:26:39.131417 ==
5846 12:26:39.131840
5847 12:26:39.132225
5848 12:26:39.132550 TX Vref Scan disable
5849 12:26:39.134438 == TX Byte 0 ==
5850 12:26:39.137512 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5851 12:26:39.141279 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5852 12:26:39.144489 == TX Byte 1 ==
5853 12:26:39.147643 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5854 12:26:39.154221 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5855 12:26:39.154690 ==
5856 12:26:39.157402 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 12:26:39.161028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 12:26:39.161460 ==
5859 12:26:39.161809
5860 12:26:39.162189
5861 12:26:39.164172 TX Vref Scan disable
5862 12:26:39.164599 == TX Byte 0 ==
5863 12:26:39.170649 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5864 12:26:39.174162 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5865 12:26:39.174586 == TX Byte 1 ==
5866 12:26:39.180482 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5867 12:26:39.183643 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5868 12:26:39.184309
5869 12:26:39.184660 [DATLAT]
5870 12:26:39.186865 Freq=933, CH1 RK1
5871 12:26:39.187327
5872 12:26:39.187671 DATLAT Default: 0xb
5873 12:26:39.190614 0, 0xFFFF, sum = 0
5874 12:26:39.193694 1, 0xFFFF, sum = 0
5875 12:26:39.194135 2, 0xFFFF, sum = 0
5876 12:26:39.197003 3, 0xFFFF, sum = 0
5877 12:26:39.197619 4, 0xFFFF, sum = 0
5878 12:26:39.199983 5, 0xFFFF, sum = 0
5879 12:26:39.200498 6, 0xFFFF, sum = 0
5880 12:26:39.203764 7, 0xFFFF, sum = 0
5881 12:26:39.204248 8, 0xFFFF, sum = 0
5882 12:26:39.207020 9, 0xFFFF, sum = 0
5883 12:26:39.207532 10, 0x0, sum = 1
5884 12:26:39.210337 11, 0x0, sum = 2
5885 12:26:39.210849 12, 0x0, sum = 3
5886 12:26:39.213480 13, 0x0, sum = 4
5887 12:26:39.214008 best_step = 11
5888 12:26:39.214409
5889 12:26:39.214765 ==
5890 12:26:39.216510 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 12:26:39.219663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 12:26:39.220130 ==
5893 12:26:39.223346 RX Vref Scan: 0
5894 12:26:39.223825
5895 12:26:39.226427 RX Vref 0 -> 0, step: 1
5896 12:26:39.226872
5897 12:26:39.227388 RX Delay -53 -> 252, step: 4
5898 12:26:39.234295 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5899 12:26:39.237895 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5900 12:26:39.240874 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5901 12:26:39.244410 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5902 12:26:39.247623 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5903 12:26:39.254009 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5904 12:26:39.257282 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5905 12:26:39.261072 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5906 12:26:39.264019 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5907 12:26:39.267077 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5908 12:26:39.274131 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5909 12:26:39.277130 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5910 12:26:39.280870 iDelay=199, Bit 12, Center 102 (15 ~ 190) 176
5911 12:26:39.283840 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5912 12:26:39.287906 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5913 12:26:39.294091 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5914 12:26:39.294557 ==
5915 12:26:39.296910 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 12:26:39.300017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 12:26:39.300458 ==
5918 12:26:39.300796 DQS Delay:
5919 12:26:39.303494 DQS0 = 0, DQS1 = 0
5920 12:26:39.303923 DQM Delay:
5921 12:26:39.306688 DQM0 = 96, DQM1 = 92
5922 12:26:39.307281 DQ Delay:
5923 12:26:39.310331 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5924 12:26:39.313595 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =92
5925 12:26:39.316891 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5926 12:26:39.319827 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =100
5927 12:26:39.320166
5928 12:26:39.320412
5929 12:26:39.330089 [DQSOSCAuto] RK1, (LSB)MR18= 0xe23, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5930 12:26:39.330396 CH1 RK1: MR19=505, MR18=E23
5931 12:26:39.336320 CH1_RK1: MR19=0x505, MR18=0xE23, DQSOSC=410, MR23=63, INC=64, DEC=42
5932 12:26:39.339720 [RxdqsGatingPostProcess] freq 933
5933 12:26:39.346303 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5934 12:26:39.349431 best DQS0 dly(2T, 0.5T) = (0, 10)
5935 12:26:39.352541 best DQS1 dly(2T, 0.5T) = (0, 10)
5936 12:26:39.356404 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5937 12:26:39.359565 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5938 12:26:39.362670 best DQS0 dly(2T, 0.5T) = (0, 10)
5939 12:26:39.365743 best DQS1 dly(2T, 0.5T) = (0, 10)
5940 12:26:39.369415 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5941 12:26:39.372468 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5942 12:26:39.372885 Pre-setting of DQS Precalculation
5943 12:26:39.378841 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5944 12:26:39.385561 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5945 12:26:39.392306 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5946 12:26:39.392600
5947 12:26:39.392837
5948 12:26:39.395825 [Calibration Summary] 1866 Mbps
5949 12:26:39.399037 CH 0, Rank 0
5950 12:26:39.399422 SW Impedance : PASS
5951 12:26:39.402062 DUTY Scan : NO K
5952 12:26:39.405432 ZQ Calibration : PASS
5953 12:26:39.405846 Jitter Meter : NO K
5954 12:26:39.408445 CBT Training : PASS
5955 12:26:39.412379 Write leveling : PASS
5956 12:26:39.412694 RX DQS gating : PASS
5957 12:26:39.415569 RX DQ/DQS(RDDQC) : PASS
5958 12:26:39.418601 TX DQ/DQS : PASS
5959 12:26:39.419013 RX DATLAT : PASS
5960 12:26:39.421790 RX DQ/DQS(Engine): PASS
5961 12:26:39.424932 TX OE : NO K
5962 12:26:39.425318 All Pass.
5963 12:26:39.425577
5964 12:26:39.425805 CH 0, Rank 1
5965 12:26:39.428183 SW Impedance : PASS
5966 12:26:39.431415 DUTY Scan : NO K
5967 12:26:39.431688 ZQ Calibration : PASS
5968 12:26:39.435381 Jitter Meter : NO K
5969 12:26:39.438429 CBT Training : PASS
5970 12:26:39.438783 Write leveling : PASS
5971 12:26:39.441521 RX DQS gating : PASS
5972 12:26:39.441843 RX DQ/DQS(RDDQC) : PASS
5973 12:26:39.444635 TX DQ/DQS : PASS
5974 12:26:39.447984 RX DATLAT : PASS
5975 12:26:39.448426 RX DQ/DQS(Engine): PASS
5976 12:26:39.451782 TX OE : NO K
5977 12:26:39.452117 All Pass.
5978 12:26:39.452367
5979 12:26:39.454863 CH 1, Rank 0
5980 12:26:39.455178 SW Impedance : PASS
5981 12:26:39.458073 DUTY Scan : NO K
5982 12:26:39.461115 ZQ Calibration : PASS
5983 12:26:39.461499 Jitter Meter : NO K
5984 12:26:39.465195 CBT Training : PASS
5985 12:26:39.468320 Write leveling : PASS
5986 12:26:39.468694 RX DQS gating : PASS
5987 12:26:39.471310 RX DQ/DQS(RDDQC) : PASS
5988 12:26:39.474332 TX DQ/DQS : PASS
5989 12:26:39.474638 RX DATLAT : PASS
5990 12:26:39.477937 RX DQ/DQS(Engine): PASS
5991 12:26:39.480983 TX OE : NO K
5992 12:26:39.481289 All Pass.
5993 12:26:39.481534
5994 12:26:39.481761 CH 1, Rank 1
5995 12:26:39.484669 SW Impedance : PASS
5996 12:26:39.487906 DUTY Scan : NO K
5997 12:26:39.488331 ZQ Calibration : PASS
5998 12:26:39.491007 Jitter Meter : NO K
5999 12:26:39.493969 CBT Training : PASS
6000 12:26:39.494281 Write leveling : PASS
6001 12:26:39.497758 RX DQS gating : PASS
6002 12:26:39.500919 RX DQ/DQS(RDDQC) : PASS
6003 12:26:39.501218 TX DQ/DQS : PASS
6004 12:26:39.504081 RX DATLAT : PASS
6005 12:26:39.507272 RX DQ/DQS(Engine): PASS
6006 12:26:39.507577 TX OE : NO K
6007 12:26:39.510926 All Pass.
6008 12:26:39.511264
6009 12:26:39.511520 DramC Write-DBI off
6010 12:26:39.513974 PER_BANK_REFRESH: Hybrid Mode
6011 12:26:39.514277 TX_TRACKING: ON
6012 12:26:39.524090 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6013 12:26:39.527196 [FAST_K] Save calibration result to emmc
6014 12:26:39.530589 dramc_set_vcore_voltage set vcore to 650000
6015 12:26:39.533683 Read voltage for 400, 6
6016 12:26:39.534102 Vio18 = 0
6017 12:26:39.536783 Vcore = 650000
6018 12:26:39.537086 Vdram = 0
6019 12:26:39.537328 Vddq = 0
6020 12:26:39.540109 Vmddr = 0
6021 12:26:39.543733 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6022 12:26:39.550137 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6023 12:26:39.550446 MEM_TYPE=3, freq_sel=20
6024 12:26:39.553347 sv_algorithm_assistance_LP4_800
6025 12:26:39.559920 ============ PULL DRAM RESETB DOWN ============
6026 12:26:39.563140 ========== PULL DRAM RESETB DOWN end =========
6027 12:26:39.566443 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6028 12:26:39.569685 ===================================
6029 12:26:39.573534 LPDDR4 DRAM CONFIGURATION
6030 12:26:39.576473 ===================================
6031 12:26:39.579404 EX_ROW_EN[0] = 0x0
6032 12:26:39.579781 EX_ROW_EN[1] = 0x0
6033 12:26:39.583055 LP4Y_EN = 0x0
6034 12:26:39.583453 WORK_FSP = 0x0
6035 12:26:39.586114 WL = 0x2
6036 12:26:39.586514 RL = 0x2
6037 12:26:39.589418 BL = 0x2
6038 12:26:39.589796 RPST = 0x0
6039 12:26:39.593195 RD_PRE = 0x0
6040 12:26:39.593622 WR_PRE = 0x1
6041 12:26:39.596469 WR_PST = 0x0
6042 12:26:39.596882 DBI_WR = 0x0
6043 12:26:39.599499 DBI_RD = 0x0
6044 12:26:39.599897 OTF = 0x1
6045 12:26:39.602438 ===================================
6046 12:26:39.606229 ===================================
6047 12:26:39.609211 ANA top config
6048 12:26:39.612358 ===================================
6049 12:26:39.615628 DLL_ASYNC_EN = 0
6050 12:26:39.615965 ALL_SLAVE_EN = 1
6051 12:26:39.619450 NEW_RANK_MODE = 1
6052 12:26:39.622708 DLL_IDLE_MODE = 1
6053 12:26:39.625895 LP45_APHY_COMB_EN = 1
6054 12:26:39.628951 TX_ODT_DIS = 1
6055 12:26:39.629363 NEW_8X_MODE = 1
6056 12:26:39.632772 ===================================
6057 12:26:39.635335 ===================================
6058 12:26:39.638575 data_rate = 800
6059 12:26:39.642231 CKR = 1
6060 12:26:39.645470 DQ_P2S_RATIO = 4
6061 12:26:39.648691 ===================================
6062 12:26:39.651950 CA_P2S_RATIO = 4
6063 12:26:39.655801 DQ_CA_OPEN = 0
6064 12:26:39.656250 DQ_SEMI_OPEN = 1
6065 12:26:39.658602 CA_SEMI_OPEN = 1
6066 12:26:39.661986 CA_FULL_RATE = 0
6067 12:26:39.665590 DQ_CKDIV4_EN = 0
6068 12:26:39.668860 CA_CKDIV4_EN = 1
6069 12:26:39.672126 CA_PREDIV_EN = 0
6070 12:26:39.672430 PH8_DLY = 0
6071 12:26:39.675285 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6072 12:26:39.678719 DQ_AAMCK_DIV = 0
6073 12:26:39.681859 CA_AAMCK_DIV = 0
6074 12:26:39.684914 CA_ADMCK_DIV = 4
6075 12:26:39.688486 DQ_TRACK_CA_EN = 0
6076 12:26:39.691593 CA_PICK = 800
6077 12:26:39.691895 CA_MCKIO = 400
6078 12:26:39.694636 MCKIO_SEMI = 400
6079 12:26:39.698597 PLL_FREQ = 3016
6080 12:26:39.701790 DQ_UI_PI_RATIO = 32
6081 12:26:39.704790 CA_UI_PI_RATIO = 32
6082 12:26:39.707695 ===================================
6083 12:26:39.711396 ===================================
6084 12:26:39.714662 memory_type:LPDDR4
6085 12:26:39.714816 GP_NUM : 10
6086 12:26:39.717784 SRAM_EN : 1
6087 12:26:39.721352 MD32_EN : 0
6088 12:26:39.724673 ===================================
6089 12:26:39.724792 [ANA_INIT] >>>>>>>>>>>>>>
6090 12:26:39.727450 <<<<<< [CONFIGURE PHASE]: ANA_TX
6091 12:26:39.730728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6092 12:26:39.734053 ===================================
6093 12:26:39.737767 data_rate = 800,PCW = 0X7400
6094 12:26:39.740844 ===================================
6095 12:26:39.743847 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6096 12:26:39.750799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6097 12:26:39.760885 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6098 12:26:39.764000 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6099 12:26:39.767633 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6100 12:26:39.773904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6101 12:26:39.774038 [ANA_INIT] flow start
6102 12:26:39.777090 [ANA_INIT] PLL >>>>>>>>
6103 12:26:39.780787 [ANA_INIT] PLL <<<<<<<<
6104 12:26:39.780927 [ANA_INIT] MIDPI >>>>>>>>
6105 12:26:39.783982 [ANA_INIT] MIDPI <<<<<<<<
6106 12:26:39.787009 [ANA_INIT] DLL >>>>>>>>
6107 12:26:39.787197 [ANA_INIT] flow end
6108 12:26:39.790576 ============ LP4 DIFF to SE enter ============
6109 12:26:39.797461 ============ LP4 DIFF to SE exit ============
6110 12:26:39.797654 [ANA_INIT] <<<<<<<<<<<<<
6111 12:26:39.800450 [Flow] Enable top DCM control >>>>>
6112 12:26:39.803686 [Flow] Enable top DCM control <<<<<
6113 12:26:39.807440 Enable DLL master slave shuffle
6114 12:26:39.813480 ==============================================================
6115 12:26:39.817357 Gating Mode config
6116 12:26:39.820454 ==============================================================
6117 12:26:39.823627 Config description:
6118 12:26:39.833877 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6119 12:26:39.839846 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6120 12:26:39.843436 SELPH_MODE 0: By rank 1: By Phase
6121 12:26:39.850132 ==============================================================
6122 12:26:39.853478 GAT_TRACK_EN = 0
6123 12:26:39.856644 RX_GATING_MODE = 2
6124 12:26:39.859769 RX_GATING_TRACK_MODE = 2
6125 12:26:39.863343 SELPH_MODE = 1
6126 12:26:39.866637 PICG_EARLY_EN = 1
6127 12:26:39.867354 VALID_LAT_VALUE = 1
6128 12:26:39.872759 ==============================================================
6129 12:26:39.876098 Enter into Gating configuration >>>>
6130 12:26:39.879775 Exit from Gating configuration <<<<
6131 12:26:39.882968 Enter into DVFS_PRE_config >>>>>
6132 12:26:39.892904 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6133 12:26:39.896026 Exit from DVFS_PRE_config <<<<<
6134 12:26:39.899582 Enter into PICG configuration >>>>
6135 12:26:39.902483 Exit from PICG configuration <<<<
6136 12:26:39.905715 [RX_INPUT] configuration >>>>>
6137 12:26:39.908887 [RX_INPUT] configuration <<<<<
6138 12:26:39.915942 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6139 12:26:39.918895 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6140 12:26:39.925279 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6141 12:26:39.931964 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6142 12:26:39.938516 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6143 12:26:39.945409 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6144 12:26:39.948597 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6145 12:26:39.951664 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6146 12:26:39.954763 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6147 12:26:39.961757 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6148 12:26:39.964897 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6149 12:26:39.967981 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6150 12:26:39.971300 ===================================
6151 12:26:39.974886 LPDDR4 DRAM CONFIGURATION
6152 12:26:39.977920 ===================================
6153 12:26:39.981264 EX_ROW_EN[0] = 0x0
6154 12:26:39.981716 EX_ROW_EN[1] = 0x0
6155 12:26:39.984457 LP4Y_EN = 0x0
6156 12:26:39.984818 WORK_FSP = 0x0
6157 12:26:39.987677 WL = 0x2
6158 12:26:39.988084 RL = 0x2
6159 12:26:39.991344 BL = 0x2
6160 12:26:39.991836 RPST = 0x0
6161 12:26:39.994364 RD_PRE = 0x0
6162 12:26:39.994757 WR_PRE = 0x1
6163 12:26:39.998132 WR_PST = 0x0
6164 12:26:40.001320 DBI_WR = 0x0
6165 12:26:40.001745 DBI_RD = 0x0
6166 12:26:40.004519 OTF = 0x1
6167 12:26:40.007522 ===================================
6168 12:26:40.011050 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6169 12:26:40.014329 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6170 12:26:40.017264 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6171 12:26:40.020473 ===================================
6172 12:26:40.024302 LPDDR4 DRAM CONFIGURATION
6173 12:26:40.027438 ===================================
6174 12:26:40.030627 EX_ROW_EN[0] = 0x10
6175 12:26:40.031010 EX_ROW_EN[1] = 0x0
6176 12:26:40.033608 LP4Y_EN = 0x0
6177 12:26:40.033976 WORK_FSP = 0x0
6178 12:26:40.036615 WL = 0x2
6179 12:26:40.036691 RL = 0x2
6180 12:26:40.040485 BL = 0x2
6181 12:26:40.040570 RPST = 0x0
6182 12:26:40.043578 RD_PRE = 0x0
6183 12:26:40.046536 WR_PRE = 0x1
6184 12:26:40.046623 WR_PST = 0x0
6185 12:26:40.050235 DBI_WR = 0x0
6186 12:26:40.050316 DBI_RD = 0x0
6187 12:26:40.053399 OTF = 0x1
6188 12:26:40.056539 ===================================
6189 12:26:40.059749 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6190 12:26:40.065584 nWR fixed to 30
6191 12:26:40.068837 [ModeRegInit_LP4] CH0 RK0
6192 12:26:40.068936 [ModeRegInit_LP4] CH0 RK1
6193 12:26:40.071917 [ModeRegInit_LP4] CH1 RK0
6194 12:26:40.075178 [ModeRegInit_LP4] CH1 RK1
6195 12:26:40.075283 match AC timing 19
6196 12:26:40.081913 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6197 12:26:40.085103 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6198 12:26:40.088806 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6199 12:26:40.095081 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6200 12:26:40.098829 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6201 12:26:40.099019 ==
6202 12:26:40.101898 Dram Type= 6, Freq= 0, CH_0, rank 0
6203 12:26:40.104936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6204 12:26:40.105222 ==
6205 12:26:40.111873 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6206 12:26:40.118295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6207 12:26:40.121524 [CA 0] Center 36 (8~64) winsize 57
6208 12:26:40.125195 [CA 1] Center 36 (8~64) winsize 57
6209 12:26:40.128300 [CA 2] Center 36 (8~64) winsize 57
6210 12:26:40.131891 [CA 3] Center 36 (8~64) winsize 57
6211 12:26:40.134977 [CA 4] Center 36 (8~64) winsize 57
6212 12:26:40.138317 [CA 5] Center 36 (8~64) winsize 57
6213 12:26:40.138855
6214 12:26:40.141292 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6215 12:26:40.141843
6216 12:26:40.144586 [CATrainingPosCal] consider 1 rank data
6217 12:26:40.148462 u2DelayCellTimex100 = 270/100 ps
6218 12:26:40.151557 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 12:26:40.154524 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 12:26:40.157908 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 12:26:40.161010 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 12:26:40.164885 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 12:26:40.167874 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 12:26:40.168404
6225 12:26:40.174111 CA PerBit enable=1, Macro0, CA PI delay=36
6226 12:26:40.174540
6227 12:26:40.174879 [CBTSetCACLKResult] CA Dly = 36
6228 12:26:40.177286 CS Dly: 1 (0~32)
6229 12:26:40.177709 ==
6230 12:26:40.181189 Dram Type= 6, Freq= 0, CH_0, rank 1
6231 12:26:40.184352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6232 12:26:40.184985 ==
6233 12:26:40.190629 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6234 12:26:40.197640 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6235 12:26:40.200778 [CA 0] Center 36 (8~64) winsize 57
6236 12:26:40.203708 [CA 1] Center 36 (8~64) winsize 57
6237 12:26:40.207467 [CA 2] Center 36 (8~64) winsize 57
6238 12:26:40.210507 [CA 3] Center 36 (8~64) winsize 57
6239 12:26:40.213563 [CA 4] Center 36 (8~64) winsize 57
6240 12:26:40.217081 [CA 5] Center 36 (8~64) winsize 57
6241 12:26:40.217552
6242 12:26:40.220099 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6243 12:26:40.220554
6244 12:26:40.223894 [CATrainingPosCal] consider 2 rank data
6245 12:26:40.226987 u2DelayCellTimex100 = 270/100 ps
6246 12:26:40.230131 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 12:26:40.233940 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 12:26:40.236711 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 12:26:40.239684 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 12:26:40.243807 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 12:26:40.246821 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 12:26:40.247499
6253 12:26:40.253206 CA PerBit enable=1, Macro0, CA PI delay=36
6254 12:26:40.254121
6255 12:26:40.254821 [CBTSetCACLKResult] CA Dly = 36
6256 12:26:40.256888 CS Dly: 1 (0~32)
6257 12:26:40.257616
6258 12:26:40.259927 ----->DramcWriteLeveling(PI) begin...
6259 12:26:40.260706 ==
6260 12:26:40.263196 Dram Type= 6, Freq= 0, CH_0, rank 0
6261 12:26:40.266328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 12:26:40.267115 ==
6263 12:26:40.269723 Write leveling (Byte 0): 40 => 8
6264 12:26:40.272839 Write leveling (Byte 1): 40 => 8
6265 12:26:40.275989 DramcWriteLeveling(PI) end<-----
6266 12:26:40.276582
6267 12:26:40.277256 ==
6268 12:26:40.279826 Dram Type= 6, Freq= 0, CH_0, rank 0
6269 12:26:40.283082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6270 12:26:40.286437 ==
6271 12:26:40.286816 [Gating] SW mode calibration
6272 12:26:40.295861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6273 12:26:40.299039 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6274 12:26:40.302216 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 12:26:40.308519 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 12:26:40.312092 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 12:26:40.315330 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 12:26:40.321923 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 12:26:40.325159 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 12:26:40.328931 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 12:26:40.335259 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 12:26:40.338347 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 12:26:40.341948 Total UI for P1: 0, mck2ui 16
6284 12:26:40.345057 best dqsien dly found for B0: ( 0, 14, 24)
6285 12:26:40.348124 Total UI for P1: 0, mck2ui 16
6286 12:26:40.351790 best dqsien dly found for B1: ( 0, 14, 24)
6287 12:26:40.354966 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6288 12:26:40.357978 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6289 12:26:40.358061
6290 12:26:40.361329 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6291 12:26:40.368170 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6292 12:26:40.368255 [Gating] SW calibration Done
6293 12:26:40.371304 ==
6294 12:26:40.371393 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 12:26:40.378227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 12:26:40.378341 ==
6297 12:26:40.378449 RX Vref Scan: 0
6298 12:26:40.378530
6299 12:26:40.381417 RX Vref 0 -> 0, step: 1
6300 12:26:40.381540
6301 12:26:40.384588 RX Delay -410 -> 252, step: 16
6302 12:26:40.387744 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6303 12:26:40.394440 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6304 12:26:40.397167 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6305 12:26:40.401040 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6306 12:26:40.404235 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6307 12:26:40.410723 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6308 12:26:40.413764 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6309 12:26:40.417398 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6310 12:26:40.420464 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6311 12:26:40.427215 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6312 12:26:40.430388 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6313 12:26:40.433347 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6314 12:26:40.437289 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6315 12:26:40.443461 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6316 12:26:40.447042 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6317 12:26:40.450239 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6318 12:26:40.450328 ==
6319 12:26:40.453320 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 12:26:40.460278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 12:26:40.460362 ==
6322 12:26:40.460428 DQS Delay:
6323 12:26:40.463477 DQS0 = 35, DQS1 = 59
6324 12:26:40.463584 DQM Delay:
6325 12:26:40.463651 DQM0 = 4, DQM1 = 16
6326 12:26:40.466663 DQ Delay:
6327 12:26:40.469883 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6328 12:26:40.473000 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6329 12:26:40.473088 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6330 12:26:40.476181 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6331 12:26:40.479794
6332 12:26:40.479875
6333 12:26:40.479939 ==
6334 12:26:40.483008 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 12:26:40.486201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 12:26:40.486282 ==
6337 12:26:40.486346
6338 12:26:40.486406
6339 12:26:40.489444 TX Vref Scan disable
6340 12:26:40.489524 == TX Byte 0 ==
6341 12:26:40.493231 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 12:26:40.499342 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 12:26:40.499424 == TX Byte 1 ==
6344 12:26:40.502439 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6345 12:26:40.509218 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6346 12:26:40.509301 ==
6347 12:26:40.512390 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 12:26:40.516232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 12:26:40.516308 ==
6350 12:26:40.516372
6351 12:26:40.516431
6352 12:26:40.519431 TX Vref Scan disable
6353 12:26:40.519497 == TX Byte 0 ==
6354 12:26:40.525666 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 12:26:40.529267 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 12:26:40.529350 == TX Byte 1 ==
6357 12:26:40.535361 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6358 12:26:40.539005 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6359 12:26:40.539089
6360 12:26:40.539155 [DATLAT]
6361 12:26:40.542006 Freq=400, CH0 RK0
6362 12:26:40.542090
6363 12:26:40.542156 DATLAT Default: 0xf
6364 12:26:40.545336 0, 0xFFFF, sum = 0
6365 12:26:40.545420 1, 0xFFFF, sum = 0
6366 12:26:40.549043 2, 0xFFFF, sum = 0
6367 12:26:40.549127 3, 0xFFFF, sum = 0
6368 12:26:40.552001 4, 0xFFFF, sum = 0
6369 12:26:40.552122 5, 0xFFFF, sum = 0
6370 12:26:40.555068 6, 0xFFFF, sum = 0
6371 12:26:40.555151 7, 0xFFFF, sum = 0
6372 12:26:40.558854 8, 0xFFFF, sum = 0
6373 12:26:40.562021 9, 0xFFFF, sum = 0
6374 12:26:40.562106 10, 0xFFFF, sum = 0
6375 12:26:40.565100 11, 0xFFFF, sum = 0
6376 12:26:40.565184 12, 0xFFFF, sum = 0
6377 12:26:40.568243 13, 0x0, sum = 1
6378 12:26:40.568326 14, 0x0, sum = 2
6379 12:26:40.571952 15, 0x0, sum = 3
6380 12:26:40.572047 16, 0x0, sum = 4
6381 12:26:40.572130 best_step = 14
6382 12:26:40.575137
6383 12:26:40.575219 ==
6384 12:26:40.578088 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 12:26:40.581982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 12:26:40.582065 ==
6387 12:26:40.582131 RX Vref Scan: 1
6388 12:26:40.582193
6389 12:26:40.585093 RX Vref 0 -> 0, step: 1
6390 12:26:40.585178
6391 12:26:40.588411 RX Delay -359 -> 252, step: 8
6392 12:26:40.588493
6393 12:26:40.591269 Set Vref, RX VrefLevel [Byte0]: 51
6394 12:26:40.594461 [Byte1]: 58
6395 12:26:40.598856
6396 12:26:40.598938 Final RX Vref Byte 0 = 51 to rank0
6397 12:26:40.602419 Final RX Vref Byte 1 = 58 to rank0
6398 12:26:40.605492 Final RX Vref Byte 0 = 51 to rank1
6399 12:26:40.608696 Final RX Vref Byte 1 = 58 to rank1==
6400 12:26:40.611541 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 12:26:40.618674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 12:26:40.618757 ==
6403 12:26:40.618871 DQS Delay:
6404 12:26:40.621804 DQS0 = 44, DQS1 = 60
6405 12:26:40.621926 DQM Delay:
6406 12:26:40.621993 DQM0 = 10, DQM1 = 15
6407 12:26:40.624960 DQ Delay:
6408 12:26:40.628660 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6409 12:26:40.631731 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6410 12:26:40.631915 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6411 12:26:40.638456 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6412 12:26:40.638541
6413 12:26:40.638607
6414 12:26:40.644640 [DQSOSCAuto] RK0, (LSB)MR18= 0x978a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6415 12:26:40.648542 CH0 RK0: MR19=C0C, MR18=978A
6416 12:26:40.654660 CH0_RK0: MR19=0xC0C, MR18=0x978A, DQSOSC=390, MR23=63, INC=388, DEC=258
6417 12:26:40.654744 ==
6418 12:26:40.658329 Dram Type= 6, Freq= 0, CH_0, rank 1
6419 12:26:40.661570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 12:26:40.661653 ==
6421 12:26:40.664607 [Gating] SW mode calibration
6422 12:26:40.671463 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6423 12:26:40.677760 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6424 12:26:40.681451 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6425 12:26:40.684594 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 12:26:40.690965 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 12:26:40.694178 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 12:26:40.697946 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 12:26:40.704149 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 12:26:40.707728 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 12:26:40.710675 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 12:26:40.717373 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 12:26:40.720906 Total UI for P1: 0, mck2ui 16
6434 12:26:40.723842 best dqsien dly found for B0: ( 0, 14, 24)
6435 12:26:40.727547 Total UI for P1: 0, mck2ui 16
6436 12:26:40.730749 best dqsien dly found for B1: ( 0, 14, 24)
6437 12:26:40.733850 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6438 12:26:40.737427 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6439 12:26:40.737510
6440 12:26:40.740273 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6441 12:26:40.744068 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6442 12:26:40.746844 [Gating] SW calibration Done
6443 12:26:40.746926 ==
6444 12:26:40.750587 Dram Type= 6, Freq= 0, CH_0, rank 1
6445 12:26:40.753760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 12:26:40.753843 ==
6447 12:26:40.757161 RX Vref Scan: 0
6448 12:26:40.757243
6449 12:26:40.760039 RX Vref 0 -> 0, step: 1
6450 12:26:40.760179
6451 12:26:40.760272 RX Delay -410 -> 252, step: 16
6452 12:26:40.766651 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6453 12:26:40.770630 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6454 12:26:40.773713 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6455 12:26:40.780085 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6456 12:26:40.783677 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6457 12:26:40.786671 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6458 12:26:40.789966 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6459 12:26:40.796838 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6460 12:26:40.799906 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6461 12:26:40.803177 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6462 12:26:40.806445 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6463 12:26:40.813268 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6464 12:26:40.816312 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6465 12:26:40.819851 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6466 12:26:40.826188 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6467 12:26:40.829385 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6468 12:26:40.829517 ==
6469 12:26:40.832398 Dram Type= 6, Freq= 0, CH_0, rank 1
6470 12:26:40.835904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 12:26:40.836011 ==
6472 12:26:40.839282 DQS Delay:
6473 12:26:40.839363 DQS0 = 43, DQS1 = 51
6474 12:26:40.839426 DQM Delay:
6475 12:26:40.842781 DQM0 = 15, DQM1 = 10
6476 12:26:40.842877 DQ Delay:
6477 12:26:40.845927 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6478 12:26:40.848966 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6479 12:26:40.852792 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6480 12:26:40.855995 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6481 12:26:40.856149
6482 12:26:40.856243
6483 12:26:40.856331 ==
6484 12:26:40.859136 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 12:26:40.865614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 12:26:40.865733 ==
6487 12:26:40.865821
6488 12:26:40.865885
6489 12:26:40.865948 TX Vref Scan disable
6490 12:26:40.868578 == TX Byte 0 ==
6491 12:26:40.872480 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6492 12:26:40.875614 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6493 12:26:40.878932 == TX Byte 1 ==
6494 12:26:40.882212 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6495 12:26:40.885235 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6496 12:26:40.885334 ==
6497 12:26:40.888949 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 12:26:40.895302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 12:26:40.895390 ==
6500 12:26:40.895456
6501 12:26:40.895518
6502 12:26:40.895591 TX Vref Scan disable
6503 12:26:40.898298 == TX Byte 0 ==
6504 12:26:40.901676 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6505 12:26:40.904785 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6506 12:26:40.908034 == TX Byte 1 ==
6507 12:26:40.911681 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6508 12:26:40.914853 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6509 12:26:40.917786
6510 12:26:40.917951 [DATLAT]
6511 12:26:40.918063 Freq=400, CH0 RK1
6512 12:26:40.918189
6513 12:26:40.921232 DATLAT Default: 0xe
6514 12:26:40.921307 0, 0xFFFF, sum = 0
6515 12:26:40.924598 1, 0xFFFF, sum = 0
6516 12:26:40.924703 2, 0xFFFF, sum = 0
6517 12:26:40.927721 3, 0xFFFF, sum = 0
6518 12:26:40.931059 4, 0xFFFF, sum = 0
6519 12:26:40.931177 5, 0xFFFF, sum = 0
6520 12:26:40.934691 6, 0xFFFF, sum = 0
6521 12:26:40.934792 7, 0xFFFF, sum = 0
6522 12:26:40.937937 8, 0xFFFF, sum = 0
6523 12:26:40.938012 9, 0xFFFF, sum = 0
6524 12:26:40.941120 10, 0xFFFF, sum = 0
6525 12:26:40.941224 11, 0xFFFF, sum = 0
6526 12:26:40.944198 12, 0xFFFF, sum = 0
6527 12:26:40.944274 13, 0x0, sum = 1
6528 12:26:40.947116 14, 0x0, sum = 2
6529 12:26:40.947216 15, 0x0, sum = 3
6530 12:26:40.950689 16, 0x0, sum = 4
6531 12:26:40.950808 best_step = 14
6532 12:26:40.950925
6533 12:26:40.951031 ==
6534 12:26:40.954033 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 12:26:40.960354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 12:26:40.960435 ==
6537 12:26:40.960509 RX Vref Scan: 0
6538 12:26:40.960574
6539 12:26:40.964048 RX Vref 0 -> 0, step: 1
6540 12:26:40.964149
6541 12:26:40.967245 RX Delay -343 -> 252, step: 8
6542 12:26:40.973763 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6543 12:26:40.977024 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6544 12:26:40.980024 iDelay=209, Bit 2, Center -36 (-271 ~ 200) 472
6545 12:26:40.983710 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6546 12:26:40.990127 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6547 12:26:40.993331 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6548 12:26:40.996498 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6549 12:26:40.999754 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6550 12:26:41.006510 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6551 12:26:41.009673 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6552 12:26:41.012964 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6553 12:26:41.016548 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6554 12:26:41.023329 iDelay=209, Bit 12, Center -40 (-287 ~ 208) 496
6555 12:26:41.026421 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6556 12:26:41.029953 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6557 12:26:41.036473 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6558 12:26:41.036560 ==
6559 12:26:41.039606 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 12:26:41.042836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 12:26:41.042920 ==
6562 12:26:41.042987 DQS Delay:
6563 12:26:41.046398 DQS0 = 44, DQS1 = 60
6564 12:26:41.046481 DQM Delay:
6565 12:26:41.049447 DQM0 = 10, DQM1 = 15
6566 12:26:41.049531 DQ Delay:
6567 12:26:41.052507 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6568 12:26:41.056299 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6569 12:26:41.059406 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6570 12:26:41.062597 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6571 12:26:41.062681
6572 12:26:41.062748
6573 12:26:41.068814 [DQSOSCAuto] RK1, (LSB)MR18= 0x8781, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6574 12:26:41.072478 CH0 RK1: MR19=C0C, MR18=8781
6575 12:26:41.078995 CH0_RK1: MR19=0xC0C, MR18=0x8781, DQSOSC=392, MR23=63, INC=384, DEC=256
6576 12:26:41.082585 [RxdqsGatingPostProcess] freq 400
6577 12:26:41.088789 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6578 12:26:41.092422 best DQS0 dly(2T, 0.5T) = (0, 10)
6579 12:26:41.095517 best DQS1 dly(2T, 0.5T) = (0, 10)
6580 12:26:41.098648 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6581 12:26:41.101798 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6582 12:26:41.101881 best DQS0 dly(2T, 0.5T) = (0, 10)
6583 12:26:41.105140 best DQS1 dly(2T, 0.5T) = (0, 10)
6584 12:26:41.108331 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6585 12:26:41.111990 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6586 12:26:41.115250 Pre-setting of DQS Precalculation
6587 12:26:41.121632 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6588 12:26:41.121716 ==
6589 12:26:41.125411 Dram Type= 6, Freq= 0, CH_1, rank 0
6590 12:26:41.128444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 12:26:41.128526 ==
6592 12:26:41.134955 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6593 12:26:41.141374 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6594 12:26:41.145232 [CA 0] Center 36 (8~64) winsize 57
6595 12:26:41.148271 [CA 1] Center 36 (8~64) winsize 57
6596 12:26:41.151439 [CA 2] Center 36 (8~64) winsize 57
6597 12:26:41.151562 [CA 3] Center 36 (8~64) winsize 57
6598 12:26:41.155123 [CA 4] Center 36 (8~64) winsize 57
6599 12:26:41.158329 [CA 5] Center 36 (8~64) winsize 57
6600 12:26:41.158456
6601 12:26:41.164533 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6602 12:26:41.164667
6603 12:26:41.167733 [CATrainingPosCal] consider 1 rank data
6604 12:26:41.170750 u2DelayCellTimex100 = 270/100 ps
6605 12:26:41.174143 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 12:26:41.177859 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 12:26:41.181086 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 12:26:41.184339 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 12:26:41.187708 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 12:26:41.190849 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 12:26:41.190988
6612 12:26:41.193996 CA PerBit enable=1, Macro0, CA PI delay=36
6613 12:26:41.194228
6614 12:26:41.197690 [CBTSetCACLKResult] CA Dly = 36
6615 12:26:41.200842 CS Dly: 1 (0~32)
6616 12:26:41.200945 ==
6617 12:26:41.204001 Dram Type= 6, Freq= 0, CH_1, rank 1
6618 12:26:41.207151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 12:26:41.207250 ==
6620 12:26:41.214120 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6621 12:26:41.220180 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6622 12:26:41.223914 [CA 0] Center 36 (8~64) winsize 57
6623 12:26:41.227219 [CA 1] Center 36 (8~64) winsize 57
6624 12:26:41.227301 [CA 2] Center 36 (8~64) winsize 57
6625 12:26:41.230293 [CA 3] Center 36 (8~64) winsize 57
6626 12:26:41.233333 [CA 4] Center 36 (8~64) winsize 57
6627 12:26:41.236848 [CA 5] Center 36 (8~64) winsize 57
6628 12:26:41.236922
6629 12:26:41.240561 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6630 12:26:41.243820
6631 12:26:41.246854 [CATrainingPosCal] consider 2 rank data
6632 12:26:41.246937 u2DelayCellTimex100 = 270/100 ps
6633 12:26:41.253695 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 12:26:41.256850 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 12:26:41.259902 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 12:26:41.263533 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 12:26:41.266799 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 12:26:41.269769 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 12:26:41.269857
6640 12:26:41.272847 CA PerBit enable=1, Macro0, CA PI delay=36
6641 12:26:41.272942
6642 12:26:41.276884 [CBTSetCACLKResult] CA Dly = 36
6643 12:26:41.280136 CS Dly: 1 (0~32)
6644 12:26:41.280238
6645 12:26:41.283314 ----->DramcWriteLeveling(PI) begin...
6646 12:26:41.283427 ==
6647 12:26:41.286547 Dram Type= 6, Freq= 0, CH_1, rank 0
6648 12:26:41.289483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 12:26:41.289609 ==
6650 12:26:41.293077 Write leveling (Byte 0): 40 => 8
6651 12:26:41.296049 Write leveling (Byte 1): 40 => 8
6652 12:26:41.299733 DramcWriteLeveling(PI) end<-----
6653 12:26:41.299884
6654 12:26:41.300005 ==
6655 12:26:41.302748 Dram Type= 6, Freq= 0, CH_1, rank 0
6656 12:26:41.305889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6657 12:26:41.306063 ==
6658 12:26:41.309334 [Gating] SW mode calibration
6659 12:26:41.315506 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6660 12:26:41.322485 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6661 12:26:41.326235 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6662 12:26:41.332650 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6663 12:26:41.335652 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 12:26:41.339530 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 12:26:41.346029 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 12:26:41.349103 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 12:26:41.352442 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 12:26:41.359156 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 12:26:41.362391 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 12:26:41.365416 Total UI for P1: 0, mck2ui 16
6671 12:26:41.368468 best dqsien dly found for B0: ( 0, 14, 24)
6672 12:26:41.372062 Total UI for P1: 0, mck2ui 16
6673 12:26:41.375336 best dqsien dly found for B1: ( 0, 14, 24)
6674 12:26:41.378613 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6675 12:26:41.381815 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6676 12:26:41.382701
6677 12:26:41.385322 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6678 12:26:41.388620 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6679 12:26:41.391752 [Gating] SW calibration Done
6680 12:26:41.392376 ==
6681 12:26:41.394767 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 12:26:41.401504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 12:26:41.402064 ==
6684 12:26:41.402436 RX Vref Scan: 0
6685 12:26:41.402762
6686 12:26:41.404458 RX Vref 0 -> 0, step: 1
6687 12:26:41.404899
6688 12:26:41.407808 RX Delay -410 -> 252, step: 16
6689 12:26:41.411696 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6690 12:26:41.414730 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6691 12:26:41.421079 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6692 12:26:41.424232 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6693 12:26:41.427392 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6694 12:26:41.430952 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6695 12:26:41.437993 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6696 12:26:41.440987 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6697 12:26:41.444176 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6698 12:26:41.447292 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6699 12:26:41.453930 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6700 12:26:41.456910 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6701 12:26:41.460307 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6702 12:26:41.467421 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6703 12:26:41.470409 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6704 12:26:41.473565 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6705 12:26:41.474159 ==
6706 12:26:41.477316 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 12:26:41.480487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 12:26:41.483470 ==
6709 12:26:41.483901 DQS Delay:
6710 12:26:41.484364 DQS0 = 35, DQS1 = 51
6711 12:26:41.486603 DQM Delay:
6712 12:26:41.487035 DQM0 = 6, DQM1 = 13
6713 12:26:41.489851 DQ Delay:
6714 12:26:41.490281 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6715 12:26:41.493601 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6716 12:26:41.496712 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6717 12:26:41.499774 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6718 12:26:41.500426
6719 12:26:41.500969
6720 12:26:41.503609 ==
6721 12:26:41.504141 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 12:26:41.509652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 12:26:41.510078 ==
6724 12:26:41.510419
6725 12:26:41.510732
6726 12:26:41.513631 TX Vref Scan disable
6727 12:26:41.514051 == TX Byte 0 ==
6728 12:26:41.516645 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 12:26:41.522934 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 12:26:41.523373 == TX Byte 1 ==
6731 12:26:41.526082 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6732 12:26:41.532908 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6733 12:26:41.533330 ==
6734 12:26:41.535985 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 12:26:41.539166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 12:26:41.539605 ==
6737 12:26:41.539944
6738 12:26:41.540306
6739 12:26:41.542363 TX Vref Scan disable
6740 12:26:41.542782 == TX Byte 0 ==
6741 12:26:41.545911 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 12:26:41.552812 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 12:26:41.553234 == TX Byte 1 ==
6744 12:26:41.555682 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 12:26:41.562565 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 12:26:41.563146
6747 12:26:41.563563 [DATLAT]
6748 12:26:41.565664 Freq=400, CH1 RK0
6749 12:26:41.566259
6750 12:26:41.566878 DATLAT Default: 0xf
6751 12:26:41.568687 0, 0xFFFF, sum = 0
6752 12:26:41.569234 1, 0xFFFF, sum = 0
6753 12:26:41.572187 2, 0xFFFF, sum = 0
6754 12:26:41.572654 3, 0xFFFF, sum = 0
6755 12:26:41.575400 4, 0xFFFF, sum = 0
6756 12:26:41.575909 5, 0xFFFF, sum = 0
6757 12:26:41.578769 6, 0xFFFF, sum = 0
6758 12:26:41.579198 7, 0xFFFF, sum = 0
6759 12:26:41.582062 8, 0xFFFF, sum = 0
6760 12:26:41.582512 9, 0xFFFF, sum = 0
6761 12:26:41.585218 10, 0xFFFF, sum = 0
6762 12:26:41.589088 11, 0xFFFF, sum = 0
6763 12:26:41.589516 12, 0xFFFF, sum = 0
6764 12:26:41.592149 13, 0x0, sum = 1
6765 12:26:41.592609 14, 0x0, sum = 2
6766 12:26:41.592958 15, 0x0, sum = 3
6767 12:26:41.595312 16, 0x0, sum = 4
6768 12:26:41.595844 best_step = 14
6769 12:26:41.596285
6770 12:26:41.598481 ==
6771 12:26:41.598895 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 12:26:41.604897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 12:26:41.605335 ==
6774 12:26:41.605685 RX Vref Scan: 1
6775 12:26:41.606004
6776 12:26:41.608617 RX Vref 0 -> 0, step: 1
6777 12:26:41.609076
6778 12:26:41.611671 RX Delay -343 -> 252, step: 8
6779 12:26:41.612152
6780 12:26:41.614849 Set Vref, RX VrefLevel [Byte0]: 50
6781 12:26:41.617981 [Byte1]: 49
6782 12:26:41.621817
6783 12:26:41.622254 Final RX Vref Byte 0 = 50 to rank0
6784 12:26:41.625015 Final RX Vref Byte 1 = 49 to rank0
6785 12:26:41.628265 Final RX Vref Byte 0 = 50 to rank1
6786 12:26:41.631803 Final RX Vref Byte 1 = 49 to rank1==
6787 12:26:41.634870 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 12:26:41.641590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 12:26:41.642093 ==
6790 12:26:41.642467 DQS Delay:
6791 12:26:41.644527 DQS0 = 44, DQS1 = 56
6792 12:26:41.645145 DQM Delay:
6793 12:26:41.648198 DQM0 = 10, DQM1 = 14
6794 12:26:41.648816 DQ Delay:
6795 12:26:41.651460 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6796 12:26:41.654584 DQ4 =4, DQ5 =20, DQ6 =20, DQ7 =4
6797 12:26:41.655138 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6798 12:26:41.661394 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6799 12:26:41.661829
6800 12:26:41.662171
6801 12:26:41.668236 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f85, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 397 ps
6802 12:26:41.671495 CH1 RK0: MR19=C0C, MR18=5F85
6803 12:26:41.677670 CH1_RK0: MR19=0xC0C, MR18=0x5F85, DQSOSC=393, MR23=63, INC=382, DEC=254
6804 12:26:41.678186 ==
6805 12:26:41.681376 Dram Type= 6, Freq= 0, CH_1, rank 1
6806 12:26:41.684319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 12:26:41.684744 ==
6808 12:26:41.687865 [Gating] SW mode calibration
6809 12:26:41.694300 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6810 12:26:41.701075 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6811 12:26:41.704191 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6812 12:26:41.707321 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6813 12:26:41.714200 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 12:26:41.717298 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 12:26:41.721045 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 12:26:41.727188 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 12:26:41.730658 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 12:26:41.734392 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 12:26:41.740404 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 12:26:41.743619 Total UI for P1: 0, mck2ui 16
6821 12:26:41.746867 best dqsien dly found for B0: ( 0, 14, 24)
6822 12:26:41.750506 Total UI for P1: 0, mck2ui 16
6823 12:26:41.753610 best dqsien dly found for B1: ( 0, 14, 24)
6824 12:26:41.756786 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6825 12:26:41.760016 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6826 12:26:41.760684
6827 12:26:41.763582 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6828 12:26:41.766632 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6829 12:26:41.769748 [Gating] SW calibration Done
6830 12:26:41.770299 ==
6831 12:26:41.773391 Dram Type= 6, Freq= 0, CH_1, rank 1
6832 12:26:41.776587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 12:26:41.777091 ==
6834 12:26:41.779687 RX Vref Scan: 0
6835 12:26:41.780268
6836 12:26:41.783487 RX Vref 0 -> 0, step: 1
6837 12:26:41.784131
6838 12:26:41.784490 RX Delay -410 -> 252, step: 16
6839 12:26:41.789718 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6840 12:26:41.793282 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6841 12:26:41.796416 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6842 12:26:41.803135 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6843 12:26:41.806264 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6844 12:26:41.809489 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6845 12:26:41.813146 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6846 12:26:41.819376 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6847 12:26:41.822553 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6848 12:26:41.825797 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6849 12:26:41.829742 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6850 12:26:41.835794 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6851 12:26:41.839569 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6852 12:26:41.842786 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6853 12:26:41.845773 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6854 12:26:41.852612 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6855 12:26:41.853039 ==
6856 12:26:41.855879 Dram Type= 6, Freq= 0, CH_1, rank 1
6857 12:26:41.859015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 12:26:41.859542 ==
6859 12:26:41.862000 DQS Delay:
6860 12:26:41.862535 DQS0 = 43, DQS1 = 51
6861 12:26:41.863013 DQM Delay:
6862 12:26:41.865794 DQM0 = 9, DQM1 = 13
6863 12:26:41.866294 DQ Delay:
6864 12:26:41.868912 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6865 12:26:41.872145 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6866 12:26:41.875019 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6867 12:26:41.878413 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6868 12:26:41.878843
6869 12:26:41.879183
6870 12:26:41.879495 ==
6871 12:26:41.881546 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 12:26:41.885355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 12:26:41.888406 ==
6874 12:26:41.888831
6875 12:26:41.889170
6876 12:26:41.889484 TX Vref Scan disable
6877 12:26:41.892071 == TX Byte 0 ==
6878 12:26:41.895070 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6879 12:26:41.898645 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6880 12:26:41.901784 == TX Byte 1 ==
6881 12:26:41.904872 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6882 12:26:41.908600 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6883 12:26:41.909238 ==
6884 12:26:41.911122 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 12:26:41.918124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 12:26:41.918725 ==
6887 12:26:41.919253
6888 12:26:41.919750
6889 12:26:41.920325 TX Vref Scan disable
6890 12:26:41.921460 == TX Byte 0 ==
6891 12:26:41.924688 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6892 12:26:41.927837 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6893 12:26:41.931458 == TX Byte 1 ==
6894 12:26:41.934672 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6895 12:26:41.937769 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6896 12:26:41.938340
6897 12:26:41.941562 [DATLAT]
6898 12:26:41.942183 Freq=400, CH1 RK1
6899 12:26:41.942704
6900 12:26:41.944692 DATLAT Default: 0xe
6901 12:26:41.945265 0, 0xFFFF, sum = 0
6902 12:26:41.947711 1, 0xFFFF, sum = 0
6903 12:26:41.948155 2, 0xFFFF, sum = 0
6904 12:26:41.950816 3, 0xFFFF, sum = 0
6905 12:26:41.951233 4, 0xFFFF, sum = 0
6906 12:26:41.953875 5, 0xFFFF, sum = 0
6907 12:26:41.954189 6, 0xFFFF, sum = 0
6908 12:26:41.957695 7, 0xFFFF, sum = 0
6909 12:26:41.958009 8, 0xFFFF, sum = 0
6910 12:26:41.960745 9, 0xFFFF, sum = 0
6911 12:26:41.963994 10, 0xFFFF, sum = 0
6912 12:26:41.964271 11, 0xFFFF, sum = 0
6913 12:26:41.967113 12, 0xFFFF, sum = 0
6914 12:26:41.967349 13, 0x0, sum = 1
6915 12:26:41.970906 14, 0x0, sum = 2
6916 12:26:41.971221 15, 0x0, sum = 3
6917 12:26:41.973881 16, 0x0, sum = 4
6918 12:26:41.974212 best_step = 14
6919 12:26:41.974475
6920 12:26:41.974741 ==
6921 12:26:41.977058 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 12:26:41.980507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 12:26:41.980819 ==
6924 12:26:41.983712 RX Vref Scan: 0
6925 12:26:41.984020
6926 12:26:41.986865 RX Vref 0 -> 0, step: 1
6927 12:26:41.987143
6928 12:26:41.987339 RX Delay -343 -> 252, step: 8
6929 12:26:41.996014 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6930 12:26:41.999114 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6931 12:26:42.002192 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6932 12:26:42.005794 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6933 12:26:42.012732 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6934 12:26:42.015915 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6935 12:26:42.018799 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6936 12:26:42.025746 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6937 12:26:42.029177 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6938 12:26:42.031956 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6939 12:26:42.035793 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6940 12:26:42.042096 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6941 12:26:42.045235 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6942 12:26:42.048919 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6943 12:26:42.052063 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6944 12:26:42.058379 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6945 12:26:42.058990 ==
6946 12:26:42.062061 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 12:26:42.065368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 12:26:42.066004 ==
6949 12:26:42.066652 DQS Delay:
6950 12:26:42.068373 DQS0 = 48, DQS1 = 56
6951 12:26:42.069048 DQM Delay:
6952 12:26:42.072017 DQM0 = 11, DQM1 = 14
6953 12:26:42.072478 DQ Delay:
6954 12:26:42.075286 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6955 12:26:42.078485 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6956 12:26:42.081989 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6957 12:26:42.084816 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6958 12:26:42.085539
6959 12:26:42.086185
6960 12:26:42.094479 [DQSOSCAuto] RK1, (LSB)MR18= 0x71a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
6961 12:26:42.095065 CH1 RK1: MR19=C0C, MR18=71A9
6962 12:26:42.101249 CH1_RK1: MR19=0xC0C, MR18=0x71A9, DQSOSC=388, MR23=63, INC=392, DEC=261
6963 12:26:42.104758 [RxdqsGatingPostProcess] freq 400
6964 12:26:42.111552 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6965 12:26:42.114357 best DQS0 dly(2T, 0.5T) = (0, 10)
6966 12:26:42.117962 best DQS1 dly(2T, 0.5T) = (0, 10)
6967 12:26:42.120998 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6968 12:26:42.124022 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6969 12:26:42.127751 best DQS0 dly(2T, 0.5T) = (0, 10)
6970 12:26:42.128326 best DQS1 dly(2T, 0.5T) = (0, 10)
6971 12:26:42.130879 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6972 12:26:42.134121 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6973 12:26:42.137716 Pre-setting of DQS Precalculation
6974 12:26:42.144467 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6975 12:26:42.150719 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6976 12:26:42.157544 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6977 12:26:42.158176
6978 12:26:42.158729
6979 12:26:42.160408 [Calibration Summary] 800 Mbps
6980 12:26:42.163688 CH 0, Rank 0
6981 12:26:42.164000 SW Impedance : PASS
6982 12:26:42.167246 DUTY Scan : NO K
6983 12:26:42.170345 ZQ Calibration : PASS
6984 12:26:42.170703 Jitter Meter : NO K
6985 12:26:42.173934 CBT Training : PASS
6986 12:26:42.176960 Write leveling : PASS
6987 12:26:42.177140 RX DQS gating : PASS
6988 12:26:42.180091 RX DQ/DQS(RDDQC) : PASS
6989 12:26:42.180250 TX DQ/DQS : PASS
6990 12:26:42.183033 RX DATLAT : PASS
6991 12:26:42.186661 RX DQ/DQS(Engine): PASS
6992 12:26:42.186802 TX OE : NO K
6993 12:26:42.190244 All Pass.
6994 12:26:42.190370
6995 12:26:42.190488 CH 0, Rank 1
6996 12:26:42.193393 SW Impedance : PASS
6997 12:26:42.193539 DUTY Scan : NO K
6998 12:26:42.196474 ZQ Calibration : PASS
6999 12:26:42.199439 Jitter Meter : NO K
7000 12:26:42.199565 CBT Training : PASS
7001 12:26:42.203102 Write leveling : NO K
7002 12:26:42.206154 RX DQS gating : PASS
7003 12:26:42.206242 RX DQ/DQS(RDDQC) : PASS
7004 12:26:42.209204 TX DQ/DQS : PASS
7005 12:26:42.212714 RX DATLAT : PASS
7006 12:26:42.212826 RX DQ/DQS(Engine): PASS
7007 12:26:42.216292 TX OE : NO K
7008 12:26:42.216395 All Pass.
7009 12:26:42.216488
7010 12:26:42.219285 CH 1, Rank 0
7011 12:26:42.219386 SW Impedance : PASS
7012 12:26:42.222855 DUTY Scan : NO K
7013 12:26:42.226057 ZQ Calibration : PASS
7014 12:26:42.226142 Jitter Meter : NO K
7015 12:26:42.229182 CBT Training : PASS
7016 12:26:42.232766 Write leveling : PASS
7017 12:26:42.232852 RX DQS gating : PASS
7018 12:26:42.235754 RX DQ/DQS(RDDQC) : PASS
7019 12:26:42.238963 TX DQ/DQS : PASS
7020 12:26:42.239048 RX DATLAT : PASS
7021 12:26:42.242560 RX DQ/DQS(Engine): PASS
7022 12:26:42.245846 TX OE : NO K
7023 12:26:42.245932 All Pass.
7024 12:26:42.246001
7025 12:26:42.246064 CH 1, Rank 1
7026 12:26:42.248850 SW Impedance : PASS
7027 12:26:42.252002 DUTY Scan : NO K
7028 12:26:42.252098 ZQ Calibration : PASS
7029 12:26:42.255971 Jitter Meter : NO K
7030 12:26:42.258468 CBT Training : PASS
7031 12:26:42.258554 Write leveling : NO K
7032 12:26:42.262147 RX DQS gating : PASS
7033 12:26:42.265153 RX DQ/DQS(RDDQC) : PASS
7034 12:26:42.265240 TX DQ/DQS : PASS
7035 12:26:42.268228 RX DATLAT : PASS
7036 12:26:42.271910 RX DQ/DQS(Engine): PASS
7037 12:26:42.272017 TX OE : NO K
7038 12:26:42.275155 All Pass.
7039 12:26:42.275256
7040 12:26:42.275348 DramC Write-DBI off
7041 12:26:42.278368 PER_BANK_REFRESH: Hybrid Mode
7042 12:26:42.278458 TX_TRACKING: ON
7043 12:26:42.288171 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7044 12:26:42.291348 [FAST_K] Save calibration result to emmc
7045 12:26:42.294773 dramc_set_vcore_voltage set vcore to 725000
7046 12:26:42.298001 Read voltage for 1600, 0
7047 12:26:42.298099 Vio18 = 0
7048 12:26:42.301581 Vcore = 725000
7049 12:26:42.301735 Vdram = 0
7050 12:26:42.301835 Vddq = 0
7051 12:26:42.304724 Vmddr = 0
7052 12:26:42.308335 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7053 12:26:42.314455 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7054 12:26:42.314612 MEM_TYPE=3, freq_sel=13
7055 12:26:42.317803 sv_algorithm_assistance_LP4_3733
7056 12:26:42.324382 ============ PULL DRAM RESETB DOWN ============
7057 12:26:42.327748 ========== PULL DRAM RESETB DOWN end =========
7058 12:26:42.331031 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7059 12:26:42.334060 ===================================
7060 12:26:42.337493 LPDDR4 DRAM CONFIGURATION
7061 12:26:42.340686 ===================================
7062 12:26:42.344295 EX_ROW_EN[0] = 0x0
7063 12:26:42.344382 EX_ROW_EN[1] = 0x0
7064 12:26:42.347278 LP4Y_EN = 0x0
7065 12:26:42.347364 WORK_FSP = 0x1
7066 12:26:42.350386 WL = 0x5
7067 12:26:42.350477 RL = 0x5
7068 12:26:42.354234 BL = 0x2
7069 12:26:42.354346 RPST = 0x0
7070 12:26:42.357253 RD_PRE = 0x0
7071 12:26:42.357368 WR_PRE = 0x1
7072 12:26:42.360487 WR_PST = 0x1
7073 12:26:42.360576 DBI_WR = 0x0
7074 12:26:42.364134 DBI_RD = 0x0
7075 12:26:42.364224 OTF = 0x1
7076 12:26:42.367129 ===================================
7077 12:26:42.370372 ===================================
7078 12:26:42.374066 ANA top config
7079 12:26:42.377248 ===================================
7080 12:26:42.380444 DLL_ASYNC_EN = 0
7081 12:26:42.380533 ALL_SLAVE_EN = 0
7082 12:26:42.383489 NEW_RANK_MODE = 1
7083 12:26:42.387138 DLL_IDLE_MODE = 1
7084 12:26:42.390109 LP45_APHY_COMB_EN = 1
7085 12:26:42.393812 TX_ODT_DIS = 0
7086 12:26:42.393898 NEW_8X_MODE = 1
7087 12:26:42.396730 ===================================
7088 12:26:42.400487 ===================================
7089 12:26:42.403643 data_rate = 3200
7090 12:26:42.406744 CKR = 1
7091 12:26:42.409792 DQ_P2S_RATIO = 8
7092 12:26:42.413458 ===================================
7093 12:26:42.416525 CA_P2S_RATIO = 8
7094 12:26:42.420099 DQ_CA_OPEN = 0
7095 12:26:42.420183 DQ_SEMI_OPEN = 0
7096 12:26:42.423029 CA_SEMI_OPEN = 0
7097 12:26:42.426637 CA_FULL_RATE = 0
7098 12:26:42.429560 DQ_CKDIV4_EN = 0
7099 12:26:42.432721 CA_CKDIV4_EN = 0
7100 12:26:42.436326 CA_PREDIV_EN = 0
7101 12:26:42.439493 PH8_DLY = 12
7102 12:26:42.439590 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7103 12:26:42.442631 DQ_AAMCK_DIV = 4
7104 12:26:42.446187 CA_AAMCK_DIV = 4
7105 12:26:42.449186 CA_ADMCK_DIV = 4
7106 12:26:42.452899 DQ_TRACK_CA_EN = 0
7107 12:26:42.456062 CA_PICK = 1600
7108 12:26:42.459063 CA_MCKIO = 1600
7109 12:26:42.459200 MCKIO_SEMI = 0
7110 12:26:42.462848 PLL_FREQ = 3068
7111 12:26:42.466000 DQ_UI_PI_RATIO = 32
7112 12:26:42.468984 CA_UI_PI_RATIO = 0
7113 12:26:42.472764 ===================================
7114 12:26:42.475714 ===================================
7115 12:26:42.478907 memory_type:LPDDR4
7116 12:26:42.479069 GP_NUM : 10
7117 12:26:42.482557 SRAM_EN : 1
7118 12:26:42.485588 MD32_EN : 0
7119 12:26:42.488715 ===================================
7120 12:26:42.488945 [ANA_INIT] >>>>>>>>>>>>>>
7121 12:26:42.492497 <<<<<< [CONFIGURE PHASE]: ANA_TX
7122 12:26:42.495637 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7123 12:26:42.498717 ===================================
7124 12:26:42.502365 data_rate = 3200,PCW = 0X7600
7125 12:26:42.505450 ===================================
7126 12:26:42.508618 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7127 12:26:42.515380 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7128 12:26:42.521824 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7129 12:26:42.524977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7130 12:26:42.528442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7131 12:26:42.531520 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7132 12:26:42.534891 [ANA_INIT] flow start
7133 12:26:42.535476 [ANA_INIT] PLL >>>>>>>>
7134 12:26:42.538281 [ANA_INIT] PLL <<<<<<<<
7135 12:26:42.541790 [ANA_INIT] MIDPI >>>>>>>>
7136 12:26:42.542215 [ANA_INIT] MIDPI <<<<<<<<
7137 12:26:42.544760 [ANA_INIT] DLL >>>>>>>>
7138 12:26:42.548346 [ANA_INIT] DLL <<<<<<<<
7139 12:26:42.548931 [ANA_INIT] flow end
7140 12:26:42.555238 ============ LP4 DIFF to SE enter ============
7141 12:26:42.558196 ============ LP4 DIFF to SE exit ============
7142 12:26:42.561849 [ANA_INIT] <<<<<<<<<<<<<
7143 12:26:42.564873 [Flow] Enable top DCM control >>>>>
7144 12:26:42.567985 [Flow] Enable top DCM control <<<<<
7145 12:26:42.568592 Enable DLL master slave shuffle
7146 12:26:42.574444 ==============================================================
7147 12:26:42.577931 Gating Mode config
7148 12:26:42.580997 ==============================================================
7149 12:26:42.584733 Config description:
7150 12:26:42.594459 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7151 12:26:42.600600 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7152 12:26:42.603988 SELPH_MODE 0: By rank 1: By Phase
7153 12:26:42.610459 ==============================================================
7154 12:26:42.613694 GAT_TRACK_EN = 1
7155 12:26:42.617300 RX_GATING_MODE = 2
7156 12:26:42.620280 RX_GATING_TRACK_MODE = 2
7157 12:26:42.623673 SELPH_MODE = 1
7158 12:26:42.626958 PICG_EARLY_EN = 1
7159 12:26:42.630097 VALID_LAT_VALUE = 1
7160 12:26:42.633725 ==============================================================
7161 12:26:42.636821 Enter into Gating configuration >>>>
7162 12:26:42.640226 Exit from Gating configuration <<<<
7163 12:26:42.643741 Enter into DVFS_PRE_config >>>>>
7164 12:26:42.656711 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7165 12:26:42.659697 Exit from DVFS_PRE_config <<<<<
7166 12:26:42.659781 Enter into PICG configuration >>>>
7167 12:26:42.662812 Exit from PICG configuration <<<<
7168 12:26:42.666323 [RX_INPUT] configuration >>>>>
7169 12:26:42.669468 [RX_INPUT] configuration <<<<<
7170 12:26:42.676380 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7171 12:26:42.679368 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7172 12:26:42.685786 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7173 12:26:42.692650 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7174 12:26:42.699368 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7175 12:26:42.705674 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7176 12:26:42.709182 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7177 12:26:42.712202 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7178 12:26:42.719141 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7179 12:26:42.722230 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7180 12:26:42.725366 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7181 12:26:42.728699 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7182 12:26:42.732346 ===================================
7183 12:26:42.735458 LPDDR4 DRAM CONFIGURATION
7184 12:26:42.738329 ===================================
7185 12:26:42.741875 EX_ROW_EN[0] = 0x0
7186 12:26:42.742026 EX_ROW_EN[1] = 0x0
7187 12:26:42.745328 LP4Y_EN = 0x0
7188 12:26:42.745480 WORK_FSP = 0x1
7189 12:26:42.748366 WL = 0x5
7190 12:26:42.748530 RL = 0x5
7191 12:26:42.752102 BL = 0x2
7192 12:26:42.755183 RPST = 0x0
7193 12:26:42.755425 RD_PRE = 0x0
7194 12:26:42.758123 WR_PRE = 0x1
7195 12:26:42.758296 WR_PST = 0x1
7196 12:26:42.761748 DBI_WR = 0x0
7197 12:26:42.761912 DBI_RD = 0x0
7198 12:26:42.764858 OTF = 0x1
7199 12:26:42.767963 ===================================
7200 12:26:42.771684 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7201 12:26:42.774608 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7202 12:26:42.781438 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7203 12:26:42.784470 ===================================
7204 12:26:42.784667 LPDDR4 DRAM CONFIGURATION
7205 12:26:42.788244 ===================================
7206 12:26:42.791345 EX_ROW_EN[0] = 0x10
7207 12:26:42.791520 EX_ROW_EN[1] = 0x0
7208 12:26:42.794481 LP4Y_EN = 0x0
7209 12:26:42.794616 WORK_FSP = 0x1
7210 12:26:42.798110 WL = 0x5
7211 12:26:42.801336 RL = 0x5
7212 12:26:42.801516 BL = 0x2
7213 12:26:42.804277 RPST = 0x0
7214 12:26:42.804438 RD_PRE = 0x0
7215 12:26:42.807512 WR_PRE = 0x1
7216 12:26:42.807692 WR_PST = 0x1
7217 12:26:42.811199 DBI_WR = 0x0
7218 12:26:42.811350 DBI_RD = 0x0
7219 12:26:42.814246 OTF = 0x1
7220 12:26:42.817670 ===================================
7221 12:26:42.823955 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7222 12:26:42.824172 ==
7223 12:26:42.827667 Dram Type= 6, Freq= 0, CH_0, rank 0
7224 12:26:42.830738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7225 12:26:42.830891 ==
7226 12:26:42.833710 [Duty_Offset_Calibration]
7227 12:26:42.833825 B0:2 B1:0 CA:4
7228 12:26:42.833893
7229 12:26:42.837429 [DutyScan_Calibration_Flow] k_type=0
7230 12:26:42.847218
7231 12:26:42.847304 ==CLK 0==
7232 12:26:42.850123 Final CLK duty delay cell = -4
7233 12:26:42.853754 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7234 12:26:42.856800 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7235 12:26:42.860348 [-4] AVG Duty = 4937%(X100)
7236 12:26:42.860431
7237 12:26:42.863333 CH0 CLK Duty spec in!! Max-Min= 187%
7238 12:26:42.867006 [DutyScan_Calibration_Flow] ====Done====
7239 12:26:42.867090
7240 12:26:42.870122 [DutyScan_Calibration_Flow] k_type=1
7241 12:26:42.886663
7242 12:26:42.886748 ==DQS 0 ==
7243 12:26:42.889837 Final DQS duty delay cell = -4
7244 12:26:42.892968 [-4] MAX Duty = 4938%(X100), DQS PI = 46
7245 12:26:42.895990 [-4] MIN Duty = 4782%(X100), DQS PI = 12
7246 12:26:42.899716 [-4] AVG Duty = 4860%(X100)
7247 12:26:42.899800
7248 12:26:42.899867 ==DQS 1 ==
7249 12:26:42.902817 Final DQS duty delay cell = 0
7250 12:26:42.905797 [0] MAX Duty = 5156%(X100), DQS PI = 0
7251 12:26:42.909657 [0] MIN Duty = 4969%(X100), DQS PI = 10
7252 12:26:42.912555 [0] AVG Duty = 5062%(X100)
7253 12:26:42.912639
7254 12:26:42.915758 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7255 12:26:42.915868
7256 12:26:42.919438 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7257 12:26:42.922422 [DutyScan_Calibration_Flow] ====Done====
7258 12:26:42.922507
7259 12:26:42.925619 [DutyScan_Calibration_Flow] k_type=3
7260 12:26:42.943653
7261 12:26:42.943756 ==DQM 0 ==
7262 12:26:42.947321 Final DQM duty delay cell = 0
7263 12:26:42.950470 [0] MAX Duty = 5124%(X100), DQS PI = 22
7264 12:26:42.954030 [0] MIN Duty = 4875%(X100), DQS PI = 56
7265 12:26:42.957014 [0] AVG Duty = 4999%(X100)
7266 12:26:42.957145
7267 12:26:42.957281 ==DQM 1 ==
7268 12:26:42.960627 Final DQM duty delay cell = 0
7269 12:26:42.963657 [0] MAX Duty = 4969%(X100), DQS PI = 0
7270 12:26:42.966948 [0] MIN Duty = 4844%(X100), DQS PI = 10
7271 12:26:42.970073 [0] AVG Duty = 4906%(X100)
7272 12:26:42.970253
7273 12:26:42.973722 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7274 12:26:42.973973
7275 12:26:42.976843 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7276 12:26:42.980257 [DutyScan_Calibration_Flow] ====Done====
7277 12:26:42.980541
7278 12:26:42.983328 [DutyScan_Calibration_Flow] k_type=2
7279 12:26:43.001391
7280 12:26:43.001770 ==DQ 0 ==
7281 12:26:43.004490 Final DQ duty delay cell = 0
7282 12:26:43.007545 [0] MAX Duty = 5124%(X100), DQS PI = 18
7283 12:26:43.010784 [0] MIN Duty = 4938%(X100), DQS PI = 12
7284 12:26:43.014548 [0] AVG Duty = 5031%(X100)
7285 12:26:43.014732
7286 12:26:43.014868 ==DQ 1 ==
7287 12:26:43.017634 Final DQ duty delay cell = 0
7288 12:26:43.020816 [0] MAX Duty = 5218%(X100), DQS PI = 2
7289 12:26:43.024367 [0] MIN Duty = 4938%(X100), DQS PI = 12
7290 12:26:43.024511 [0] AVG Duty = 5078%(X100)
7291 12:26:43.024624
7292 12:26:43.273862 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7293 12:26:43.274009
7294 12:26:43.274266 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7295 12:26:43.274333 [DutyScan_Calibration_Flow] ====Done====
7296 12:26:43.274395 ==
7297 12:26:43.274454 Dram Type= 6, Freq= 0, CH_1, rank 0
7298 12:26:43.274512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7299 12:26:43.274568 ==
7300 12:26:43.274623 [Duty_Offset_Calibration]
7301 12:26:43.274677 B0:0 B1:-1 CA:3
7302 12:26:43.274730
7303 12:26:43.274783 [DutyScan_Calibration_Flow] k_type=0
7304 12:26:43.274836
7305 12:26:43.274888 ==CLK 0==
7306 12:26:43.274940 Final CLK duty delay cell = -4
7307 12:26:43.274993 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7308 12:26:43.275044 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7309 12:26:43.275096 [-4] AVG Duty = 4922%(X100)
7310 12:26:43.275147
7311 12:26:43.275198 CH1 CLK Duty spec in!! Max-Min= 156%
7312 12:26:43.275250 [DutyScan_Calibration_Flow] ====Done====
7313 12:26:43.275320
7314 12:26:43.275387 [DutyScan_Calibration_Flow] k_type=1
7315 12:26:43.275439
7316 12:26:43.275490 ==DQS 0 ==
7317 12:26:43.275542 Final DQS duty delay cell = 0
7318 12:26:43.275626 [0] MAX Duty = 5250%(X100), DQS PI = 20
7319 12:26:43.275677 [0] MIN Duty = 4907%(X100), DQS PI = 58
7320 12:26:43.275729 [0] AVG Duty = 5078%(X100)
7321 12:26:43.275780
7322 12:26:43.275831 ==DQS 1 ==
7323 12:26:43.275883 Final DQS duty delay cell = -4
7324 12:26:43.275935 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7325 12:26:43.275985 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7326 12:26:43.276062 [-4] AVG Duty = 4906%(X100)
7327 12:26:43.276130
7328 12:26:43.276181 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7329 12:26:43.276232
7330 12:26:43.276284 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7331 12:26:43.276336 [DutyScan_Calibration_Flow] ====Done====
7332 12:26:43.276387
7333 12:26:43.276438 [DutyScan_Calibration_Flow] k_type=3
7334 12:26:43.276490
7335 12:26:43.276540 ==DQM 0 ==
7336 12:26:43.276592 Final DQM duty delay cell = 0
7337 12:26:43.276644 [0] MAX Duty = 5062%(X100), DQS PI = 30
7338 12:26:43.276712 [0] MIN Duty = 4782%(X100), DQS PI = 40
7339 12:26:43.276765 [0] AVG Duty = 4922%(X100)
7340 12:26:43.276817
7341 12:26:43.276869 ==DQM 1 ==
7342 12:26:43.276923 Final DQM duty delay cell = 0
7343 12:26:43.276989 [0] MAX Duty = 5000%(X100), DQS PI = 32
7344 12:26:43.277041 [0] MIN Duty = 4782%(X100), DQS PI = 62
7345 12:26:43.277093 [0] AVG Duty = 4891%(X100)
7346 12:26:43.277144
7347 12:26:43.277194 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7348 12:26:43.277245
7349 12:26:43.277296 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7350 12:26:43.277347 [DutyScan_Calibration_Flow] ====Done====
7351 12:26:43.277398
7352 12:26:43.277449 [DutyScan_Calibration_Flow] k_type=2
7353 12:26:43.277500
7354 12:26:43.277551 ==DQ 0 ==
7355 12:26:43.277602 Final DQ duty delay cell = -4
7356 12:26:43.277654 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7357 12:26:43.277705 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7358 12:26:43.277756 [-4] AVG Duty = 4891%(X100)
7359 12:26:43.277808
7360 12:26:43.277858 ==DQ 1 ==
7361 12:26:43.277910 Final DQ duty delay cell = 0
7362 12:26:43.277962 [0] MAX Duty = 5062%(X100), DQS PI = 30
7363 12:26:43.278013 [0] MIN Duty = 4875%(X100), DQS PI = 0
7364 12:26:43.278064 [0] AVG Duty = 4968%(X100)
7365 12:26:43.278115
7366 12:26:43.278166 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7367 12:26:43.278217
7368 12:26:43.278268 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7369 12:26:43.278319 [DutyScan_Calibration_Flow] ====Done====
7370 12:26:43.278371 nWR fixed to 30
7371 12:26:43.278423 [ModeRegInit_LP4] CH0 RK0
7372 12:26:43.278492 [ModeRegInit_LP4] CH0 RK1
7373 12:26:43.278558 [ModeRegInit_LP4] CH1 RK0
7374 12:26:43.278609 [ModeRegInit_LP4] CH1 RK1
7375 12:26:43.278660 match AC timing 5
7376 12:26:43.278711 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7377 12:26:43.278763 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7378 12:26:43.278828 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7379 12:26:43.282205 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7380 12:26:43.285224 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7381 12:26:43.288803 [MiockJmeterHQA]
7382 12:26:43.288883
7383 12:26:43.291983 [DramcMiockJmeter] u1RxGatingPI = 0
7384 12:26:43.292088 0 : 4252, 4027
7385 12:26:43.292155 4 : 4253, 4027
7386 12:26:43.295394 8 : 4252, 4027
7387 12:26:43.295475 12 : 4260, 4032
7388 12:26:43.298403 16 : 4368, 4137
7389 12:26:43.298483 20 : 4253, 4026
7390 12:26:43.301688 24 : 4252, 4026
7391 12:26:43.301769 28 : 4252, 4027
7392 12:26:43.301834 32 : 4260, 4032
7393 12:26:43.305130 36 : 4370, 4140
7394 12:26:43.305234 40 : 4260, 4029
7395 12:26:43.308419 44 : 4365, 4137
7396 12:26:43.308500 48 : 4260, 4029
7397 12:26:43.311438 52 : 4255, 4027
7398 12:26:43.311562 56 : 4254, 4027
7399 12:26:43.315209 60 : 4365, 4137
7400 12:26:43.315290 64 : 4363, 4137
7401 12:26:43.315358 68 : 4254, 4026
7402 12:26:43.318353 72 : 4258, 4029
7403 12:26:43.318434 76 : 4252, 4027
7404 12:26:43.322045 80 : 4257, 4029
7405 12:26:43.322127 84 : 4252, 4027
7406 12:26:43.325293 88 : 4363, 4138
7407 12:26:43.325374 92 : 4258, 4029
7408 12:26:43.328367 96 : 4363, 3396
7409 12:26:43.328448 100 : 4257, 0
7410 12:26:43.328513 104 : 4368, 0
7411 12:26:43.331352 108 : 4365, 0
7412 12:26:43.331432 112 : 4257, 0
7413 12:26:43.335068 116 : 4257, 0
7414 12:26:43.335150 120 : 4253, 0
7415 12:26:43.335214 124 : 4363, 0
7416 12:26:43.338342 128 : 4361, 0
7417 12:26:43.338423 132 : 4363, 0
7418 12:26:43.341195 136 : 4250, 0
7419 12:26:43.341276 140 : 4250, 0
7420 12:26:43.341341 144 : 4250, 0
7421 12:26:43.344774 148 : 4250, 0
7422 12:26:43.344855 152 : 4250, 0
7423 12:26:43.344920 156 : 4250, 0
7424 12:26:43.347861 160 : 4253, 0
7425 12:26:43.347942 164 : 4250, 0
7426 12:26:43.351635 168 : 4250, 0
7427 12:26:43.351716 172 : 4253, 0
7428 12:26:43.351779 176 : 4250, 0
7429 12:26:43.354653 180 : 4361, 0
7430 12:26:43.354735 184 : 4361, 0
7431 12:26:43.357533 188 : 4248, 0
7432 12:26:43.357615 192 : 4361, 0
7433 12:26:43.357679 196 : 4250, 0
7434 12:26:43.361170 200 : 4250, 0
7435 12:26:43.361268 204 : 4250, 0
7436 12:26:43.364360 208 : 4361, 0
7437 12:26:43.364441 212 : 4360, 0
7438 12:26:43.364506 216 : 4250, 0
7439 12:26:43.367827 220 : 4250, 538
7440 12:26:43.367953 224 : 4360, 4079
7441 12:26:43.371146 228 : 4250, 4026
7442 12:26:43.371241 232 : 4361, 4137
7443 12:26:43.374229 236 : 4363, 4140
7444 12:26:43.374333 240 : 4250, 4027
7445 12:26:43.377336 244 : 4250, 4026
7446 12:26:43.377436 248 : 4361, 4137
7447 12:26:43.380856 252 : 4250, 4026
7448 12:26:43.380939 256 : 4250, 4027
7449 12:26:43.383971 260 : 4250, 4026
7450 12:26:43.384079 264 : 4250, 4027
7451 12:26:43.384145 268 : 4250, 4027
7452 12:26:43.387573 272 : 4250, 4027
7453 12:26:43.387656 276 : 4360, 4138
7454 12:26:43.390722 280 : 4250, 4027
7455 12:26:43.390835 284 : 4250, 4026
7456 12:26:43.393737 288 : 4361, 4137
7457 12:26:43.393837 292 : 4250, 4027
7458 12:26:43.397046 296 : 4250, 4026
7459 12:26:43.397147 300 : 4361, 4137
7460 12:26:43.400622 304 : 4250, 4026
7461 12:26:43.400811 308 : 4250, 4027
7462 12:26:43.403647 312 : 4250, 4027
7463 12:26:43.403806 316 : 4250, 4027
7464 12:26:43.407282 320 : 4250, 4027
7465 12:26:43.407426 324 : 4250, 4027
7466 12:26:43.410241 328 : 4360, 4137
7467 12:26:43.410329 332 : 4250, 4021
7468 12:26:43.414116 336 : 4250, 2354
7469 12:26:43.414189 340 : 4361, 45
7470 12:26:43.414255
7471 12:26:43.417268 MIOCK jitter meter ch=0
7472 12:26:43.417348
7473 12:26:43.420325 1T = (340-100) = 240 dly cells
7474 12:26:43.423336 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7475 12:26:43.423442 ==
7476 12:26:43.426538 Dram Type= 6, Freq= 0, CH_0, rank 0
7477 12:26:43.433367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7478 12:26:43.433539 ==
7479 12:26:43.436885 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7480 12:26:43.443292 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7481 12:26:43.446850 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7482 12:26:43.452996 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7483 12:26:43.461103 [CA 0] Center 43 (13~73) winsize 61
7484 12:26:43.464069 [CA 1] Center 42 (12~73) winsize 62
7485 12:26:43.467910 [CA 2] Center 37 (8~67) winsize 60
7486 12:26:43.470803 [CA 3] Center 37 (8~67) winsize 60
7487 12:26:43.474214 [CA 4] Center 36 (6~66) winsize 61
7488 12:26:43.477953 [CA 5] Center 35 (5~66) winsize 62
7489 12:26:43.478287
7490 12:26:43.480976 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7491 12:26:43.481793
7492 12:26:43.484576 [CATrainingPosCal] consider 1 rank data
7493 12:26:43.487403 u2DelayCellTimex100 = 271/100 ps
7494 12:26:43.494278 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7495 12:26:43.497289 CA1 delay=42 (12~73),Diff = 7 PI (25 cell)
7496 12:26:43.501077 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7497 12:26:43.504002 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7498 12:26:43.507761 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7499 12:26:43.511329 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7500 12:26:43.511912
7501 12:26:43.514411 CA PerBit enable=1, Macro0, CA PI delay=35
7502 12:26:43.515029
7503 12:26:43.517464 [CBTSetCACLKResult] CA Dly = 35
7504 12:26:43.520569 CS Dly: 10 (0~41)
7505 12:26:43.524326 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7506 12:26:43.527563 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7507 12:26:43.528011 ==
7508 12:26:43.530469 Dram Type= 6, Freq= 0, CH_0, rank 1
7509 12:26:43.537264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7510 12:26:43.537591 ==
7511 12:26:43.540431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7512 12:26:43.543574 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7513 12:26:43.550331 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7514 12:26:43.556955 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7515 12:26:43.564497 [CA 0] Center 44 (14~75) winsize 62
7516 12:26:43.568255 [CA 1] Center 44 (14~74) winsize 61
7517 12:26:43.571387 [CA 2] Center 39 (10~69) winsize 60
7518 12:26:43.574168 [CA 3] Center 39 (10~68) winsize 59
7519 12:26:43.577843 [CA 4] Center 37 (7~67) winsize 61
7520 12:26:43.581149 [CA 5] Center 36 (7~66) winsize 60
7521 12:26:43.581542
7522 12:26:43.584597 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7523 12:26:43.587647
7524 12:26:43.591122 [CATrainingPosCal] consider 2 rank data
7525 12:26:43.591424 u2DelayCellTimex100 = 271/100 ps
7526 12:26:43.597462 CA0 delay=43 (14~73),Diff = 7 PI (25 cell)
7527 12:26:43.600977 CA1 delay=43 (14~73),Diff = 7 PI (25 cell)
7528 12:26:43.603997 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7529 12:26:43.607677 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7530 12:26:43.610684 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7531 12:26:43.613717 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7532 12:26:43.614164
7533 12:26:43.617388 CA PerBit enable=1, Macro0, CA PI delay=36
7534 12:26:43.620494
7535 12:26:43.621147 [CBTSetCACLKResult] CA Dly = 36
7536 12:26:43.623798 CS Dly: 11 (0~44)
7537 12:26:43.626814 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7538 12:26:43.630684 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7539 12:26:43.633746
7540 12:26:43.636867 ----->DramcWriteLeveling(PI) begin...
7541 12:26:43.637346 ==
7542 12:26:43.639926 Dram Type= 6, Freq= 0, CH_0, rank 0
7543 12:26:43.643565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 12:26:43.643804 ==
7545 12:26:43.646607 Write leveling (Byte 0): 35 => 35
7546 12:26:43.649718 Write leveling (Byte 1): 26 => 26
7547 12:26:43.653570 DramcWriteLeveling(PI) end<-----
7548 12:26:43.653789
7549 12:26:43.653964 ==
7550 12:26:43.656558 Dram Type= 6, Freq= 0, CH_0, rank 0
7551 12:26:43.659577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7552 12:26:43.659798 ==
7553 12:26:43.663440 [Gating] SW mode calibration
7554 12:26:43.669644 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7555 12:26:43.676091 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7556 12:26:43.679677 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 12:26:43.682780 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7558 12:26:43.689314 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 12:26:43.692827 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7560 12:26:43.696313 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7561 12:26:43.702871 1 4 20 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7562 12:26:43.705798 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7563 12:26:43.708994 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7564 12:26:43.716135 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7565 12:26:43.718918 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7566 12:26:43.722574 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7567 12:26:43.728774 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
7568 12:26:43.731977 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7569 12:26:43.735246 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
7570 12:26:43.741857 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 12:26:43.745106 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 12:26:43.748962 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 12:26:43.755144 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 12:26:43.758107 1 6 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
7575 12:26:43.761781 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (1 1)
7576 12:26:43.768550 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7577 12:26:43.771738 1 6 20 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
7578 12:26:43.774649 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7579 12:26:43.781424 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 12:26:43.785232 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 12:26:43.788102 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 12:26:43.794718 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 12:26:43.798252 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7584 12:26:43.801100 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7585 12:26:43.807505 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7586 12:26:43.811067 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7587 12:26:43.814105 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 12:26:43.820710 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 12:26:43.823819 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 12:26:43.827576 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 12:26:43.833695 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 12:26:43.837323 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 12:26:43.840523 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 12:26:43.847182 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 12:26:43.850215 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 12:26:43.853312 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 12:26:43.860129 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7598 12:26:43.863652 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7599 12:26:43.869827 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7600 12:26:43.872973 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7601 12:26:43.876734 Total UI for P1: 0, mck2ui 16
7602 12:26:43.879707 best dqsien dly found for B0: ( 1, 9, 8)
7603 12:26:43.883330 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7604 12:26:43.889371 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7605 12:26:43.892979 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 12:26:43.896129 Total UI for P1: 0, mck2ui 16
7607 12:26:43.899830 best dqsien dly found for B1: ( 1, 9, 20)
7608 12:26:43.902776 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7609 12:26:43.906130 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7610 12:26:43.906264
7611 12:26:43.909233 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7612 12:26:43.912840 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7613 12:26:43.915977 [Gating] SW calibration Done
7614 12:26:43.916127 ==
7615 12:26:43.919102 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 12:26:43.922881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 12:26:43.925983 ==
7618 12:26:43.926169 RX Vref Scan: 0
7619 12:26:43.926305
7620 12:26:43.929092 RX Vref 0 -> 0, step: 1
7621 12:26:43.929203
7622 12:26:43.929289 RX Delay 0 -> 252, step: 8
7623 12:26:43.935879 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7624 12:26:43.939123 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7625 12:26:43.942182 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7626 12:26:43.945868 iDelay=192, Bit 3, Center 131 (80 ~ 183) 104
7627 12:26:43.952078 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7628 12:26:43.955864 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7629 12:26:43.959025 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7630 12:26:43.962301 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7631 12:26:43.965181 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7632 12:26:43.971814 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7633 12:26:43.975644 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7634 12:26:43.978722 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7635 12:26:43.981661 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7636 12:26:43.985362 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
7637 12:26:43.991960 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7638 12:26:43.995033 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7639 12:26:43.995387 ==
7640 12:26:43.998574 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 12:26:44.001715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 12:26:44.002220 ==
7643 12:26:44.004691 DQS Delay:
7644 12:26:44.005117 DQS0 = 0, DQS1 = 0
7645 12:26:44.008321 DQM Delay:
7646 12:26:44.008684 DQM0 = 132, DQM1 = 128
7647 12:26:44.008962 DQ Delay:
7648 12:26:44.015146 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
7649 12:26:44.018082 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7650 12:26:44.021218 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7651 12:26:44.024266 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
7652 12:26:44.024472
7653 12:26:44.024629
7654 12:26:44.024777 ==
7655 12:26:44.027794 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 12:26:44.030989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 12:26:44.031177 ==
7658 12:26:44.031321
7659 12:26:44.031453
7660 12:26:44.034032 TX Vref Scan disable
7661 12:26:44.037557 == TX Byte 0 ==
7662 12:26:44.040656 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7663 12:26:44.043771 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7664 12:26:44.047659 == TX Byte 1 ==
7665 12:26:44.050635 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7666 12:26:44.053877 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7667 12:26:44.053995 ==
7668 12:26:44.057020 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 12:26:44.063834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 12:26:44.063983 ==
7671 12:26:44.078094
7672 12:26:44.081102 TX Vref early break, caculate TX vref
7673 12:26:44.084225 TX Vref=16, minBit 7, minWin=20, winSum=357
7674 12:26:44.087230 TX Vref=18, minBit 1, minWin=21, winSum=369
7675 12:26:44.090941 TX Vref=20, minBit 1, minWin=22, winSum=380
7676 12:26:44.094101 TX Vref=22, minBit 0, minWin=23, winSum=390
7677 12:26:44.097805 TX Vref=24, minBit 0, minWin=24, winSum=402
7678 12:26:44.104059 TX Vref=26, minBit 1, minWin=24, winSum=406
7679 12:26:44.107170 TX Vref=28, minBit 2, minWin=23, winSum=404
7680 12:26:44.110858 TX Vref=30, minBit 1, minWin=23, winSum=404
7681 12:26:44.113663 TX Vref=32, minBit 4, minWin=22, winSum=395
7682 12:26:44.117206 TX Vref=34, minBit 0, minWin=23, winSum=387
7683 12:26:44.123767 TX Vref=36, minBit 2, minWin=22, winSum=378
7684 12:26:44.126765 [TxChooseVref] Worse bit 1, Min win 24, Win sum 406, Final Vref 26
7685 12:26:44.127028
7686 12:26:44.130509 Final TX Range 0 Vref 26
7687 12:26:44.130750
7688 12:26:44.130971 ==
7689 12:26:44.133776 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 12:26:44.136813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 12:26:44.140595 ==
7692 12:26:44.140918
7693 12:26:44.141295
7694 12:26:44.141605 TX Vref Scan disable
7695 12:26:44.147140 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7696 12:26:44.147687 == TX Byte 0 ==
7697 12:26:44.150271 u2DelayCellOfst[0]=14 cells (4 PI)
7698 12:26:44.153908 u2DelayCellOfst[1]=18 cells (5 PI)
7699 12:26:44.157149 u2DelayCellOfst[2]=10 cells (3 PI)
7700 12:26:44.160189 u2DelayCellOfst[3]=10 cells (3 PI)
7701 12:26:44.163948 u2DelayCellOfst[4]=10 cells (3 PI)
7702 12:26:44.167255 u2DelayCellOfst[5]=0 cells (0 PI)
7703 12:26:44.170210 u2DelayCellOfst[6]=18 cells (5 PI)
7704 12:26:44.173479 u2DelayCellOfst[7]=18 cells (5 PI)
7705 12:26:44.176973 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7706 12:26:44.179874 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7707 12:26:44.183689 == TX Byte 1 ==
7708 12:26:44.186689 u2DelayCellOfst[8]=0 cells (0 PI)
7709 12:26:44.190214 u2DelayCellOfst[9]=0 cells (0 PI)
7710 12:26:44.193057 u2DelayCellOfst[10]=3 cells (1 PI)
7711 12:26:44.196472 u2DelayCellOfst[11]=0 cells (0 PI)
7712 12:26:44.199559 u2DelayCellOfst[12]=7 cells (2 PI)
7713 12:26:44.203053 u2DelayCellOfst[13]=10 cells (3 PI)
7714 12:26:44.206039 u2DelayCellOfst[14]=14 cells (4 PI)
7715 12:26:44.209091 u2DelayCellOfst[15]=7 cells (2 PI)
7716 12:26:44.212862 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7717 12:26:44.215734 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7718 12:26:44.219336 DramC Write-DBI on
7719 12:26:44.219571 ==
7720 12:26:44.222223 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 12:26:44.225611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 12:26:44.225790 ==
7723 12:26:44.225956
7724 12:26:44.226100
7725 12:26:44.229111 TX Vref Scan disable
7726 12:26:44.232843 == TX Byte 0 ==
7727 12:26:44.235918 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7728 12:26:44.236055 == TX Byte 1 ==
7729 12:26:44.242219 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7730 12:26:44.242332 DramC Write-DBI off
7731 12:26:44.242421
7732 12:26:44.242499 [DATLAT]
7733 12:26:44.245834 Freq=1600, CH0 RK0
7734 12:26:44.245951
7735 12:26:44.249020 DATLAT Default: 0xf
7736 12:26:44.249134 0, 0xFFFF, sum = 0
7737 12:26:44.251973 1, 0xFFFF, sum = 0
7738 12:26:44.252094 2, 0xFFFF, sum = 0
7739 12:26:44.255759 3, 0xFFFF, sum = 0
7740 12:26:44.255865 4, 0xFFFF, sum = 0
7741 12:26:44.258831 5, 0xFFFF, sum = 0
7742 12:26:44.258929 6, 0xFFFF, sum = 0
7743 12:26:44.261990 7, 0xFFFF, sum = 0
7744 12:26:44.262084 8, 0xFFFF, sum = 0
7745 12:26:44.265020 9, 0xFFFF, sum = 0
7746 12:26:44.265117 10, 0xFFFF, sum = 0
7747 12:26:44.269008 11, 0xFFFF, sum = 0
7748 12:26:44.269095 12, 0xFFFF, sum = 0
7749 12:26:44.272136 13, 0xFFFF, sum = 0
7750 12:26:44.272234 14, 0x0, sum = 1
7751 12:26:44.275221 15, 0x0, sum = 2
7752 12:26:44.275310 16, 0x0, sum = 3
7753 12:26:44.278323 17, 0x0, sum = 4
7754 12:26:44.278431 best_step = 15
7755 12:26:44.278526
7756 12:26:44.278626 ==
7757 12:26:44.282028 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 12:26:44.288364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 12:26:44.288445 ==
7760 12:26:44.288523 RX Vref Scan: 1
7761 12:26:44.288590
7762 12:26:44.291368 Set Vref Range= 24 -> 127
7763 12:26:44.291448
7764 12:26:44.295110 RX Vref 24 -> 127, step: 1
7765 12:26:44.295207
7766 12:26:44.298032 RX Delay 19 -> 252, step: 4
7767 12:26:44.298104
7768 12:26:44.301190 Set Vref, RX VrefLevel [Byte0]: 24
7769 12:26:44.304837 [Byte1]: 24
7770 12:26:44.304913
7771 12:26:44.308370 Set Vref, RX VrefLevel [Byte0]: 25
7772 12:26:44.311423 [Byte1]: 25
7773 12:26:44.311554
7774 12:26:44.314801 Set Vref, RX VrefLevel [Byte0]: 26
7775 12:26:44.317928 [Byte1]: 26
7776 12:26:44.321000
7777 12:26:44.321146 Set Vref, RX VrefLevel [Byte0]: 27
7778 12:26:44.324690 [Byte1]: 27
7779 12:26:44.328643
7780 12:26:44.328750 Set Vref, RX VrefLevel [Byte0]: 28
7781 12:26:44.331791 [Byte1]: 28
7782 12:26:44.336535
7783 12:26:44.336620 Set Vref, RX VrefLevel [Byte0]: 29
7784 12:26:44.339614 [Byte1]: 29
7785 12:26:44.343778
7786 12:26:44.343883 Set Vref, RX VrefLevel [Byte0]: 30
7787 12:26:44.346940 [Byte1]: 30
7788 12:26:44.351311
7789 12:26:44.351388 Set Vref, RX VrefLevel [Byte0]: 31
7790 12:26:44.354393 [Byte1]: 31
7791 12:26:44.358698
7792 12:26:44.358800 Set Vref, RX VrefLevel [Byte0]: 32
7793 12:26:44.362358 [Byte1]: 32
7794 12:26:44.366872
7795 12:26:44.366972 Set Vref, RX VrefLevel [Byte0]: 33
7796 12:26:44.369934 [Byte1]: 33
7797 12:26:44.373892
7798 12:26:44.373971 Set Vref, RX VrefLevel [Byte0]: 34
7799 12:26:44.377566 [Byte1]: 34
7800 12:26:44.382029
7801 12:26:44.382132 Set Vref, RX VrefLevel [Byte0]: 35
7802 12:26:44.385238 [Byte1]: 35
7803 12:26:44.389369
7804 12:26:44.389472 Set Vref, RX VrefLevel [Byte0]: 36
7805 12:26:44.392472 [Byte1]: 36
7806 12:26:44.397159
7807 12:26:44.397231 Set Vref, RX VrefLevel [Byte0]: 37
7808 12:26:44.400246 [Byte1]: 37
7809 12:26:44.404497
7810 12:26:44.404601 Set Vref, RX VrefLevel [Byte0]: 38
7811 12:26:44.407736 [Byte1]: 38
7812 12:26:44.411972
7813 12:26:44.412074 Set Vref, RX VrefLevel [Byte0]: 39
7814 12:26:44.415642 [Byte1]: 39
7815 12:26:44.419743
7816 12:26:44.419846 Set Vref, RX VrefLevel [Byte0]: 40
7817 12:26:44.422732 [Byte1]: 40
7818 12:26:44.427032
7819 12:26:44.427115 Set Vref, RX VrefLevel [Byte0]: 41
7820 12:26:44.430751 [Byte1]: 41
7821 12:26:44.434972
7822 12:26:44.435072 Set Vref, RX VrefLevel [Byte0]: 42
7823 12:26:44.437961 [Byte1]: 42
7824 12:26:44.442251
7825 12:26:44.442351 Set Vref, RX VrefLevel [Byte0]: 43
7826 12:26:44.445439 [Byte1]: 43
7827 12:26:44.450255
7828 12:26:44.450361 Set Vref, RX VrefLevel [Byte0]: 44
7829 12:26:44.453333 [Byte1]: 44
7830 12:26:44.457602
7831 12:26:44.457675 Set Vref, RX VrefLevel [Byte0]: 45
7832 12:26:44.460639 [Byte1]: 45
7833 12:26:44.465008
7834 12:26:44.465092 Set Vref, RX VrefLevel [Byte0]: 46
7835 12:26:44.468013 [Byte1]: 46
7836 12:26:44.472594
7837 12:26:44.472676 Set Vref, RX VrefLevel [Byte0]: 47
7838 12:26:44.475721 [Byte1]: 47
7839 12:26:44.480251
7840 12:26:44.480355 Set Vref, RX VrefLevel [Byte0]: 48
7841 12:26:44.483776 [Byte1]: 48
7842 12:26:44.487957
7843 12:26:44.488086 Set Vref, RX VrefLevel [Byte0]: 49
7844 12:26:44.491066 [Byte1]: 49
7845 12:26:44.495186
7846 12:26:44.495287 Set Vref, RX VrefLevel [Byte0]: 50
7847 12:26:44.498834 [Byte1]: 50
7848 12:26:44.502956
7849 12:26:44.503066 Set Vref, RX VrefLevel [Byte0]: 51
7850 12:26:44.505974 [Byte1]: 51
7851 12:26:44.510605
7852 12:26:44.510687 Set Vref, RX VrefLevel [Byte0]: 52
7853 12:26:44.513531 [Byte1]: 52
7854 12:26:44.517825
7855 12:26:44.517899 Set Vref, RX VrefLevel [Byte0]: 53
7856 12:26:44.521460 [Byte1]: 53
7857 12:26:44.525524
7858 12:26:44.525595 Set Vref, RX VrefLevel [Byte0]: 54
7859 12:26:44.529336 [Byte1]: 54
7860 12:26:44.533574
7861 12:26:44.533670 Set Vref, RX VrefLevel [Byte0]: 55
7862 12:26:44.536369 [Byte1]: 55
7863 12:26:44.541054
7864 12:26:44.541132 Set Vref, RX VrefLevel [Byte0]: 56
7865 12:26:44.544067 [Byte1]: 56
7866 12:26:44.548400
7867 12:26:44.548512 Set Vref, RX VrefLevel [Byte0]: 57
7868 12:26:44.551501 [Byte1]: 57
7869 12:26:44.556205
7870 12:26:44.556281 Set Vref, RX VrefLevel [Byte0]: 58
7871 12:26:44.559431 [Byte1]: 58
7872 12:26:44.563566
7873 12:26:44.563662 Set Vref, RX VrefLevel [Byte0]: 59
7874 12:26:44.566603 [Byte1]: 59
7875 12:26:44.571156
7876 12:26:44.571250 Set Vref, RX VrefLevel [Byte0]: 60
7877 12:26:44.574240 [Byte1]: 60
7878 12:26:44.578595
7879 12:26:44.578676 Set Vref, RX VrefLevel [Byte0]: 61
7880 12:26:44.581736 [Byte1]: 61
7881 12:26:44.586116
7882 12:26:44.586188 Set Vref, RX VrefLevel [Byte0]: 62
7883 12:26:44.589207 [Byte1]: 62
7884 12:26:44.593724
7885 12:26:44.593835 Set Vref, RX VrefLevel [Byte0]: 63
7886 12:26:44.597100 [Byte1]: 63
7887 12:26:44.601227
7888 12:26:44.601344 Set Vref, RX VrefLevel [Byte0]: 64
7889 12:26:44.604729 [Byte1]: 64
7890 12:26:44.609142
7891 12:26:44.609267 Set Vref, RX VrefLevel [Byte0]: 65
7892 12:26:44.612237 [Byte1]: 65
7893 12:26:44.616438
7894 12:26:44.616517 Set Vref, RX VrefLevel [Byte0]: 66
7895 12:26:44.620104 [Byte1]: 66
7896 12:26:44.624443
7897 12:26:44.624520 Set Vref, RX VrefLevel [Byte0]: 67
7898 12:26:44.627476 [Byte1]: 67
7899 12:26:44.631568
7900 12:26:44.631648 Set Vref, RX VrefLevel [Byte0]: 68
7901 12:26:44.635159 [Byte1]: 68
7902 12:26:44.639359
7903 12:26:44.639457 Set Vref, RX VrefLevel [Byte0]: 69
7904 12:26:44.642245 [Byte1]: 69
7905 12:26:44.646933
7906 12:26:44.647006 Set Vref, RX VrefLevel [Byte0]: 70
7907 12:26:44.649899 [Byte1]: 70
7908 12:26:44.654288
7909 12:26:44.654385 Set Vref, RX VrefLevel [Byte0]: 71
7910 12:26:44.660974 [Byte1]: 71
7911 12:26:44.661056
7912 12:26:44.664073 Set Vref, RX VrefLevel [Byte0]: 72
7913 12:26:44.667840 [Byte1]: 72
7914 12:26:44.667948
7915 12:26:44.670850 Set Vref, RX VrefLevel [Byte0]: 73
7916 12:26:44.674059 [Byte1]: 73
7917 12:26:44.674141
7918 12:26:44.677635 Final RX Vref Byte 0 = 62 to rank0
7919 12:26:44.680726 Final RX Vref Byte 1 = 57 to rank0
7920 12:26:44.683940 Final RX Vref Byte 0 = 62 to rank1
7921 12:26:44.687106 Final RX Vref Byte 1 = 57 to rank1==
7922 12:26:44.690716 Dram Type= 6, Freq= 0, CH_0, rank 0
7923 12:26:44.697010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7924 12:26:44.697093 ==
7925 12:26:44.697159 DQS Delay:
7926 12:26:44.697231 DQS0 = 0, DQS1 = 0
7927 12:26:44.700001 DQM Delay:
7928 12:26:44.700141 DQM0 = 129, DQM1 = 124
7929 12:26:44.703589 DQ Delay:
7930 12:26:44.707069 DQ0 =132, DQ1 =130, DQ2 =126, DQ3 =124
7931 12:26:44.710543 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =136
7932 12:26:44.713686 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7933 12:26:44.716840 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =132
7934 12:26:44.716911
7935 12:26:44.716971
7936 12:26:44.717028
7937 12:26:44.719926 [DramC_TX_OE_Calibration] TA2
7938 12:26:44.723519 Original DQ_B0 (3 6) =30, OEN = 27
7939 12:26:44.726496 Original DQ_B1 (3 6) =30, OEN = 27
7940 12:26:44.729564 24, 0x0, End_B0=24 End_B1=24
7941 12:26:44.733188 25, 0x0, End_B0=25 End_B1=25
7942 12:26:44.733272 26, 0x0, End_B0=26 End_B1=26
7943 12:26:44.736214 27, 0x0, End_B0=27 End_B1=27
7944 12:26:44.739320 28, 0x0, End_B0=28 End_B1=28
7945 12:26:44.743029 29, 0x0, End_B0=29 End_B1=29
7946 12:26:44.743122 30, 0x0, End_B0=30 End_B1=30
7947 12:26:44.746326 31, 0x4141, End_B0=30 End_B1=30
7948 12:26:44.749733 Byte0 end_step=30 best_step=27
7949 12:26:44.752754 Byte1 end_step=30 best_step=27
7950 12:26:44.756387 Byte0 TX OE(2T, 0.5T) = (3, 3)
7951 12:26:44.759485 Byte1 TX OE(2T, 0.5T) = (3, 3)
7952 12:26:44.759556
7953 12:26:44.759629
7954 12:26:44.766197 [DQSOSCAuto] RK0, (LSB)MR18= 0x1311, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
7955 12:26:44.769207 CH0 RK0: MR19=303, MR18=1311
7956 12:26:44.775933 CH0_RK0: MR19=0x303, MR18=0x1311, DQSOSC=400, MR23=63, INC=23, DEC=15
7957 12:26:44.776042
7958 12:26:44.778983 ----->DramcWriteLeveling(PI) begin...
7959 12:26:44.779087 ==
7960 12:26:44.782151 Dram Type= 6, Freq= 0, CH_0, rank 1
7961 12:26:44.785339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7962 12:26:44.785411 ==
7963 12:26:44.789128 Write leveling (Byte 0): 33 => 33
7964 12:26:44.792227 Write leveling (Byte 1): 27 => 27
7965 12:26:44.795332 DramcWriteLeveling(PI) end<-----
7966 12:26:44.795434
7967 12:26:44.795524 ==
7968 12:26:44.798987 Dram Type= 6, Freq= 0, CH_0, rank 1
7969 12:26:44.805286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7970 12:26:44.805372 ==
7971 12:26:44.805435 [Gating] SW mode calibration
7972 12:26:44.815317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7973 12:26:44.818621 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7974 12:26:44.825316 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7975 12:26:44.828377 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7976 12:26:44.831500 1 4 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (1 1)
7977 12:26:44.838124 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7978 12:26:44.841610 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7979 12:26:44.844603 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7980 12:26:44.851375 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7981 12:26:44.854975 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7982 12:26:44.858107 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7983 12:26:44.864520 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7984 12:26:44.868011 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7985 12:26:44.870995 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7986 12:26:44.877744 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7987 12:26:44.880915 1 5 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
7988 12:26:44.884635 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 12:26:44.890870 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 12:26:44.894036 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 12:26:44.897765 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 12:26:44.903896 1 6 8 | B1->B0 | 2323 3a39 | 0 1 | (0 0) (0 0)
7993 12:26:44.907651 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7994 12:26:44.910712 1 6 16 | B1->B0 | 2e2e 4646 | 0 0 | (1 1) (0 0)
7995 12:26:44.917481 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7996 12:26:44.920599 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 12:26:44.923806 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 12:26:44.930553 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 12:26:44.934188 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8000 12:26:44.937355 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8001 12:26:44.944160 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8002 12:26:44.947000 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8003 12:26:44.950530 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8004 12:26:44.956589 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 12:26:44.959949 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 12:26:44.963100 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 12:26:44.970285 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 12:26:44.973079 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 12:26:44.976896 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 12:26:44.983108 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 12:26:44.986028 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 12:26:44.989780 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 12:26:44.995971 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 12:26:44.999726 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 12:26:45.002769 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8016 12:26:45.009539 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8017 12:26:45.012671 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8018 12:26:45.015715 Total UI for P1: 0, mck2ui 16
8019 12:26:45.019349 best dqsien dly found for B0: ( 1, 9, 6)
8020 12:26:45.022261 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8021 12:26:45.028943 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8022 12:26:45.031982 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 12:26:45.035816 Total UI for P1: 0, mck2ui 16
8024 12:26:45.038988 best dqsien dly found for B1: ( 1, 9, 18)
8025 12:26:45.042103 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8026 12:26:45.045711 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8027 12:26:45.045817
8028 12:26:45.048853 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8029 12:26:45.051855 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8030 12:26:45.055508 [Gating] SW calibration Done
8031 12:26:45.055623 ==
8032 12:26:45.058513 Dram Type= 6, Freq= 0, CH_0, rank 1
8033 12:26:45.065322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8034 12:26:45.065467 ==
8035 12:26:45.065580 RX Vref Scan: 0
8036 12:26:45.065686
8037 12:26:45.068563 RX Vref 0 -> 0, step: 1
8038 12:26:45.068724
8039 12:26:45.071607 RX Delay 0 -> 252, step: 8
8040 12:26:45.075119 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8041 12:26:45.078831 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8042 12:26:45.081796 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8043 12:26:45.085607 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8044 12:26:45.091923 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8045 12:26:45.095040 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8046 12:26:45.098779 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8047 12:26:45.101880 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8048 12:26:45.104990 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8049 12:26:45.111797 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8050 12:26:45.114995 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8051 12:26:45.118096 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8052 12:26:45.121834 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8053 12:26:45.128118 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8054 12:26:45.131696 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8055 12:26:45.134814 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8056 12:26:45.135373 ==
8057 12:26:45.138447 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 12:26:45.141494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 12:26:45.142107 ==
8060 12:26:45.144519 DQS Delay:
8061 12:26:45.145093 DQS0 = 0, DQS1 = 0
8062 12:26:45.148294 DQM Delay:
8063 12:26:45.148997 DQM0 = 132, DQM1 = 126
8064 12:26:45.151251 DQ Delay:
8065 12:26:45.154229 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
8066 12:26:45.157374 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =143
8067 12:26:45.160943 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8068 12:26:45.164171 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8069 12:26:45.164722
8070 12:26:45.165070
8071 12:26:45.165465 ==
8072 12:26:45.167281 Dram Type= 6, Freq= 0, CH_0, rank 1
8073 12:26:45.170746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8074 12:26:45.171356 ==
8075 12:26:45.173944
8076 12:26:45.174365
8077 12:26:45.174702 TX Vref Scan disable
8078 12:26:45.177269 == TX Byte 0 ==
8079 12:26:45.180834 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8080 12:26:45.183811 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8081 12:26:45.187387 == TX Byte 1 ==
8082 12:26:45.190608 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8083 12:26:45.193780 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8084 12:26:45.194308 ==
8085 12:26:45.196774 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 12:26:45.203586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 12:26:45.204188 ==
8088 12:26:45.216112
8089 12:26:45.219778 TX Vref early break, caculate TX vref
8090 12:26:45.222886 TX Vref=16, minBit 0, minWin=22, winSum=376
8091 12:26:45.225936 TX Vref=18, minBit 1, minWin=23, winSum=386
8092 12:26:45.229581 TX Vref=20, minBit 0, minWin=24, winSum=394
8093 12:26:45.232707 TX Vref=22, minBit 0, minWin=23, winSum=398
8094 12:26:45.236385 TX Vref=24, minBit 0, minWin=25, winSum=411
8095 12:26:45.242829 TX Vref=26, minBit 0, minWin=25, winSum=419
8096 12:26:45.246040 TX Vref=28, minBit 0, minWin=25, winSum=417
8097 12:26:45.249005 TX Vref=30, minBit 0, minWin=24, winSum=416
8098 12:26:45.252764 TX Vref=32, minBit 3, minWin=24, winSum=406
8099 12:26:45.255735 TX Vref=34, minBit 0, minWin=24, winSum=396
8100 12:26:45.262515 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 26
8101 12:26:45.263067
8102 12:26:45.265304 Final TX Range 0 Vref 26
8103 12:26:45.265800
8104 12:26:45.266425 ==
8105 12:26:45.269284 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 12:26:45.272173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 12:26:45.272659 ==
8108 12:26:45.273189
8109 12:26:45.273657
8110 12:26:45.275937 TX Vref Scan disable
8111 12:26:45.281994 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8112 12:26:45.282648 == TX Byte 0 ==
8113 12:26:45.285156 u2DelayCellOfst[0]=14 cells (4 PI)
8114 12:26:45.288763 u2DelayCellOfst[1]=18 cells (5 PI)
8115 12:26:45.291791 u2DelayCellOfst[2]=10 cells (3 PI)
8116 12:26:45.295557 u2DelayCellOfst[3]=10 cells (3 PI)
8117 12:26:45.298518 u2DelayCellOfst[4]=10 cells (3 PI)
8118 12:26:45.301696 u2DelayCellOfst[5]=0 cells (0 PI)
8119 12:26:45.304839 u2DelayCellOfst[6]=18 cells (5 PI)
8120 12:26:45.308466 u2DelayCellOfst[7]=18 cells (5 PI)
8121 12:26:45.311594 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8122 12:26:45.314620 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8123 12:26:45.318622 == TX Byte 1 ==
8124 12:26:45.321788 u2DelayCellOfst[8]=3 cells (1 PI)
8125 12:26:45.324702 u2DelayCellOfst[9]=0 cells (0 PI)
8126 12:26:45.328445 u2DelayCellOfst[10]=3 cells (1 PI)
8127 12:26:45.328678 u2DelayCellOfst[11]=0 cells (0 PI)
8128 12:26:45.331550 u2DelayCellOfst[12]=10 cells (3 PI)
8129 12:26:45.335055 u2DelayCellOfst[13]=10 cells (3 PI)
8130 12:26:45.338185 u2DelayCellOfst[14]=18 cells (5 PI)
8131 12:26:45.341004 u2DelayCellOfst[15]=10 cells (3 PI)
8132 12:26:45.347780 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8133 12:26:45.350888 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8134 12:26:45.350995 DramC Write-DBI on
8135 12:26:45.354722 ==
8136 12:26:45.357813 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 12:26:45.360752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 12:26:45.360837 ==
8139 12:26:45.360906
8140 12:26:45.360969
8141 12:26:45.363965 TX Vref Scan disable
8142 12:26:45.364078 == TX Byte 0 ==
8143 12:26:45.370578 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8144 12:26:45.370665 == TX Byte 1 ==
8145 12:26:45.374319 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8146 12:26:45.377120 DramC Write-DBI off
8147 12:26:45.377205
8148 12:26:45.377273 [DATLAT]
8149 12:26:45.380827 Freq=1600, CH0 RK1
8150 12:26:45.380912
8151 12:26:45.380980 DATLAT Default: 0xf
8152 12:26:45.383851 0, 0xFFFF, sum = 0
8153 12:26:45.383965 1, 0xFFFF, sum = 0
8154 12:26:45.387581 2, 0xFFFF, sum = 0
8155 12:26:45.387667 3, 0xFFFF, sum = 0
8156 12:26:45.390704 4, 0xFFFF, sum = 0
8157 12:26:45.393774 5, 0xFFFF, sum = 0
8158 12:26:45.393860 6, 0xFFFF, sum = 0
8159 12:26:45.396924 7, 0xFFFF, sum = 0
8160 12:26:45.397010 8, 0xFFFF, sum = 0
8161 12:26:45.400665 9, 0xFFFF, sum = 0
8162 12:26:45.400751 10, 0xFFFF, sum = 0
8163 12:26:45.403650 11, 0xFFFF, sum = 0
8164 12:26:45.403735 12, 0xFFFF, sum = 0
8165 12:26:45.406909 13, 0xFFFF, sum = 0
8166 12:26:45.407023 14, 0x0, sum = 1
8167 12:26:45.409973 15, 0x0, sum = 2
8168 12:26:45.410059 16, 0x0, sum = 3
8169 12:26:45.413721 17, 0x0, sum = 4
8170 12:26:45.413807 best_step = 15
8171 12:26:45.413874
8172 12:26:45.413936 ==
8173 12:26:45.416804 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 12:26:45.420563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 12:26:45.423508 ==
8176 12:26:45.423594 RX Vref Scan: 0
8177 12:26:45.423662
8178 12:26:45.426721 RX Vref 0 -> 0, step: 1
8179 12:26:45.426831
8180 12:26:45.429855 RX Delay 11 -> 252, step: 4
8181 12:26:45.433677 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8182 12:26:45.436539 iDelay=191, Bit 1, Center 132 (83 ~ 182) 100
8183 12:26:45.439714 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8184 12:26:45.446713 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8185 12:26:45.449848 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8186 12:26:45.453065 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8187 12:26:45.456136 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8188 12:26:45.459861 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8189 12:26:45.466168 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8190 12:26:45.469757 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8191 12:26:45.472854 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8192 12:26:45.476362 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8193 12:26:45.483018 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8194 12:26:45.485969 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8195 12:26:45.489495 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8196 12:26:45.492589 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8197 12:26:45.492672 ==
8198 12:26:45.495786 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 12:26:45.502418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 12:26:45.502503 ==
8201 12:26:45.502570 DQS Delay:
8202 12:26:45.502633 DQS0 = 0, DQS1 = 0
8203 12:26:45.505563 DQM Delay:
8204 12:26:45.505646 DQM0 = 129, DQM1 = 123
8205 12:26:45.509174 DQ Delay:
8206 12:26:45.512443 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =126
8207 12:26:45.515463 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =136
8208 12:26:45.519162 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8209 12:26:45.522197 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =130
8210 12:26:45.522292
8211 12:26:45.522358
8212 12:26:45.522427
8213 12:26:45.525567 [DramC_TX_OE_Calibration] TA2
8214 12:26:45.528588 Original DQ_B0 (3 6) =30, OEN = 27
8215 12:26:45.532137 Original DQ_B1 (3 6) =30, OEN = 27
8216 12:26:45.535403 24, 0x0, End_B0=24 End_B1=24
8217 12:26:45.535478 25, 0x0, End_B0=25 End_B1=25
8218 12:26:45.538340 26, 0x0, End_B0=26 End_B1=26
8219 12:26:45.541564 27, 0x0, End_B0=27 End_B1=27
8220 12:26:45.545177 28, 0x0, End_B0=28 End_B1=28
8221 12:26:45.548330 29, 0x0, End_B0=29 End_B1=29
8222 12:26:45.548415 30, 0x0, End_B0=30 End_B1=30
8223 12:26:45.551782 31, 0x4141, End_B0=30 End_B1=30
8224 12:26:45.554683 Byte0 end_step=30 best_step=27
8225 12:26:45.558240 Byte1 end_step=30 best_step=27
8226 12:26:45.561322 Byte0 TX OE(2T, 0.5T) = (3, 3)
8227 12:26:45.565046 Byte1 TX OE(2T, 0.5T) = (3, 3)
8228 12:26:45.565128
8229 12:26:45.565192
8230 12:26:45.571310 [DQSOSCAuto] RK1, (LSB)MR18= 0x110e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
8231 12:26:45.575003 CH0 RK1: MR19=303, MR18=110E
8232 12:26:45.581429 CH0_RK1: MR19=0x303, MR18=0x110E, DQSOSC=401, MR23=63, INC=22, DEC=15
8233 12:26:45.584457 [RxdqsGatingPostProcess] freq 1600
8234 12:26:45.590959 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8235 12:26:45.591038 best DQS0 dly(2T, 0.5T) = (1, 1)
8236 12:26:45.594495 best DQS1 dly(2T, 0.5T) = (1, 1)
8237 12:26:45.597674 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8238 12:26:45.600952 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8239 12:26:45.604074 best DQS0 dly(2T, 0.5T) = (1, 1)
8240 12:26:45.607628 best DQS1 dly(2T, 0.5T) = (1, 1)
8241 12:26:45.610817 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8242 12:26:45.614605 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8243 12:26:45.617467 Pre-setting of DQS Precalculation
8244 12:26:45.620565 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8245 12:26:45.620651 ==
8246 12:26:45.624303 Dram Type= 6, Freq= 0, CH_1, rank 0
8247 12:26:45.630651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8248 12:26:45.630728 ==
8249 12:26:45.633679 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8250 12:26:45.640335 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8251 12:26:45.644303 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8252 12:26:45.650266 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8253 12:26:45.658535 [CA 0] Center 42 (12~72) winsize 61
8254 12:26:45.662128 [CA 1] Center 42 (13~72) winsize 60
8255 12:26:45.665082 [CA 2] Center 38 (9~67) winsize 59
8256 12:26:45.668187 [CA 3] Center 36 (7~66) winsize 60
8257 12:26:45.671924 [CA 4] Center 37 (7~68) winsize 62
8258 12:26:45.675064 [CA 5] Center 36 (7~66) winsize 60
8259 12:26:45.675171
8260 12:26:45.678136 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8261 12:26:45.678219
8262 12:26:45.684455 [CATrainingPosCal] consider 1 rank data
8263 12:26:45.684538 u2DelayCellTimex100 = 271/100 ps
8264 12:26:45.691538 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8265 12:26:45.694611 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8266 12:26:45.698028 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8267 12:26:45.701495 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8268 12:26:45.704700 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8269 12:26:45.707618 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8270 12:26:45.707728
8271 12:26:45.711398 CA PerBit enable=1, Macro0, CA PI delay=36
8272 12:26:45.711485
8273 12:26:45.714488 [CBTSetCACLKResult] CA Dly = 36
8274 12:26:45.717747 CS Dly: 7 (0~38)
8275 12:26:45.721235 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8276 12:26:45.724374 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8277 12:26:45.724451 ==
8278 12:26:45.727466 Dram Type= 6, Freq= 0, CH_1, rank 1
8279 12:26:45.733848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8280 12:26:45.733948 ==
8281 12:26:45.737481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8282 12:26:45.744242 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8283 12:26:45.747245 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8284 12:26:45.753875 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8285 12:26:45.761974 [CA 0] Center 41 (11~71) winsize 61
8286 12:26:45.764986 [CA 1] Center 41 (12~71) winsize 60
8287 12:26:45.767948 [CA 2] Center 37 (8~67) winsize 60
8288 12:26:45.771509 [CA 3] Center 36 (7~66) winsize 60
8289 12:26:45.774634 [CA 4] Center 36 (7~66) winsize 60
8290 12:26:45.778398 [CA 5] Center 36 (6~66) winsize 61
8291 12:26:45.778480
8292 12:26:45.781427 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8293 12:26:45.781509
8294 12:26:45.788221 [CATrainingPosCal] consider 2 rank data
8295 12:26:45.788314 u2DelayCellTimex100 = 271/100 ps
8296 12:26:45.794928 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8297 12:26:45.797828 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8298 12:26:45.801294 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8299 12:26:45.804700 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8300 12:26:45.807721 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8301 12:26:45.811408 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8302 12:26:45.811489
8303 12:26:45.814357 CA PerBit enable=1, Macro0, CA PI delay=36
8304 12:26:45.814438
8305 12:26:45.818102 [CBTSetCACLKResult] CA Dly = 36
8306 12:26:45.821144 CS Dly: 9 (0~43)
8307 12:26:45.824294 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8308 12:26:45.827343 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8309 12:26:45.827416
8310 12:26:45.831135 ----->DramcWriteLeveling(PI) begin...
8311 12:26:45.831217 ==
8312 12:26:45.834180 Dram Type= 6, Freq= 0, CH_1, rank 0
8313 12:26:45.840573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 12:26:45.840654 ==
8315 12:26:45.844270 Write leveling (Byte 0): 24 => 24
8316 12:26:45.847296 Write leveling (Byte 1): 27 => 27
8317 12:26:45.847376 DramcWriteLeveling(PI) end<-----
8318 12:26:45.847440
8319 12:26:45.850853 ==
8320 12:26:45.853990 Dram Type= 6, Freq= 0, CH_1, rank 0
8321 12:26:45.857271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8322 12:26:45.857347 ==
8323 12:26:45.860851 [Gating] SW mode calibration
8324 12:26:45.867358 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8325 12:26:45.870319 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8326 12:26:45.877427 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 12:26:45.880525 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 12:26:45.883569 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 12:26:45.890444 1 4 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
8330 12:26:45.893474 1 4 16 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8331 12:26:45.897343 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 12:26:45.903344 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 12:26:45.906843 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 12:26:45.909842 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 12:26:45.916557 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 12:26:45.920179 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
8337 12:26:45.923127 1 5 12 | B1->B0 | 3232 2828 | 0 0 | (0 0) (1 0)
8338 12:26:45.929904 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8339 12:26:45.932947 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 12:26:45.936306 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 12:26:45.942585 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 12:26:45.946415 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 12:26:45.949441 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 12:26:45.955982 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8345 12:26:45.959128 1 6 12 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
8346 12:26:45.962944 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 12:26:45.968976 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 12:26:45.972562 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 12:26:45.975471 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 12:26:45.982130 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 12:26:45.985347 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 12:26:45.992206 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 12:26:45.995343 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8354 12:26:45.998359 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8355 12:26:46.005296 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 12:26:46.008373 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 12:26:46.011852 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 12:26:46.018357 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 12:26:46.021752 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 12:26:46.024787 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 12:26:46.031439 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 12:26:46.034630 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 12:26:46.038196 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 12:26:46.044484 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 12:26:46.048017 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 12:26:46.051236 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 12:26:46.058134 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 12:26:46.061251 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8369 12:26:46.064247 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8370 12:26:46.070991 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8371 12:26:46.071101 Total UI for P1: 0, mck2ui 16
8372 12:26:46.077361 best dqsien dly found for B0: ( 1, 9, 10)
8373 12:26:46.080768 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 12:26:46.084210 Total UI for P1: 0, mck2ui 16
8375 12:26:46.087358 best dqsien dly found for B1: ( 1, 9, 16)
8376 12:26:46.090438 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8377 12:26:46.094043 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8378 12:26:46.094125
8379 12:26:46.097182 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8380 12:26:46.100383 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8381 12:26:46.104065 [Gating] SW calibration Done
8382 12:26:46.104160 ==
8383 12:26:46.107152 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 12:26:46.113839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 12:26:46.113923 ==
8386 12:26:46.113989 RX Vref Scan: 0
8387 12:26:46.114050
8388 12:26:46.116958 RX Vref 0 -> 0, step: 1
8389 12:26:46.117040
8390 12:26:46.120622 RX Delay 0 -> 252, step: 8
8391 12:26:46.123492 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8392 12:26:46.127081 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8393 12:26:46.129950 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8394 12:26:46.133681 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8395 12:26:46.139755 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8396 12:26:46.143351 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8397 12:26:46.146574 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8398 12:26:46.150059 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8399 12:26:46.153244 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8400 12:26:46.159883 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8401 12:26:46.162971 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8402 12:26:46.166155 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8403 12:26:46.169886 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8404 12:26:46.175869 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8405 12:26:46.179474 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8406 12:26:46.183237 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8407 12:26:46.183320 ==
8408 12:26:46.185560 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 12:26:46.189288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 12:26:46.192387 ==
8411 12:26:46.192469 DQS Delay:
8412 12:26:46.192534 DQS0 = 0, DQS1 = 0
8413 12:26:46.196074 DQM Delay:
8414 12:26:46.196183 DQM0 = 134, DQM1 = 132
8415 12:26:46.199070 DQ Delay:
8416 12:26:46.202148 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8417 12:26:46.205811 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8418 12:26:46.209015 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8419 12:26:46.212294 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8420 12:26:46.212377
8421 12:26:46.212442
8422 12:26:46.212502 ==
8423 12:26:46.215341 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 12:26:46.219066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8425 12:26:46.219147 ==
8426 12:26:46.222007
8427 12:26:46.222089
8428 12:26:46.222154 TX Vref Scan disable
8429 12:26:46.225398 == TX Byte 0 ==
8430 12:26:46.228830 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8431 12:26:46.231670 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8432 12:26:46.235203 == TX Byte 1 ==
8433 12:26:46.238839 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8434 12:26:46.241742 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8435 12:26:46.245353 ==
8436 12:26:46.245435 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 12:26:46.251533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 12:26:46.251615 ==
8439 12:26:46.264565
8440 12:26:46.267766 TX Vref early break, caculate TX vref
8441 12:26:46.271599 TX Vref=16, minBit 8, minWin=21, winSum=364
8442 12:26:46.274744 TX Vref=18, minBit 9, minWin=22, winSum=379
8443 12:26:46.278389 TX Vref=20, minBit 3, minWin=23, winSum=381
8444 12:26:46.281277 TX Vref=22, minBit 8, minWin=23, winSum=393
8445 12:26:46.284627 TX Vref=24, minBit 8, minWin=24, winSum=410
8446 12:26:46.290976 TX Vref=26, minBit 9, minWin=24, winSum=410
8447 12:26:46.294395 TX Vref=28, minBit 5, minWin=25, winSum=412
8448 12:26:46.297547 TX Vref=30, minBit 0, minWin=25, winSum=412
8449 12:26:46.301390 TX Vref=32, minBit 9, minWin=24, winSum=405
8450 12:26:46.304389 TX Vref=34, minBit 0, minWin=24, winSum=397
8451 12:26:46.311129 TX Vref=36, minBit 0, minWin=23, winSum=388
8452 12:26:46.314365 [TxChooseVref] Worse bit 5, Min win 25, Win sum 412, Final Vref 28
8453 12:26:46.314478
8454 12:26:46.317418 Final TX Range 0 Vref 28
8455 12:26:46.317501
8456 12:26:46.317566 ==
8457 12:26:46.320638 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 12:26:46.324198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 12:26:46.327340 ==
8460 12:26:46.327447
8461 12:26:46.327540
8462 12:26:46.327629 TX Vref Scan disable
8463 12:26:46.333830 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8464 12:26:46.333914 == TX Byte 0 ==
8465 12:26:46.337565 u2DelayCellOfst[0]=18 cells (5 PI)
8466 12:26:46.340556 u2DelayCellOfst[1]=10 cells (3 PI)
8467 12:26:46.344133 u2DelayCellOfst[2]=0 cells (0 PI)
8468 12:26:46.347153 u2DelayCellOfst[3]=7 cells (2 PI)
8469 12:26:46.350285 u2DelayCellOfst[4]=7 cells (2 PI)
8470 12:26:46.353853 u2DelayCellOfst[5]=18 cells (5 PI)
8471 12:26:46.357099 u2DelayCellOfst[6]=18 cells (5 PI)
8472 12:26:46.359984 u2DelayCellOfst[7]=7 cells (2 PI)
8473 12:26:46.363814 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8474 12:26:46.366915 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8475 12:26:46.370140 == TX Byte 1 ==
8476 12:26:46.373222 u2DelayCellOfst[8]=0 cells (0 PI)
8477 12:26:46.376899 u2DelayCellOfst[9]=3 cells (1 PI)
8478 12:26:46.379969 u2DelayCellOfst[10]=14 cells (4 PI)
8479 12:26:46.383022 u2DelayCellOfst[11]=7 cells (2 PI)
8480 12:26:46.386744 u2DelayCellOfst[12]=14 cells (4 PI)
8481 12:26:46.389700 u2DelayCellOfst[13]=18 cells (5 PI)
8482 12:26:46.393193 u2DelayCellOfst[14]=18 cells (5 PI)
8483 12:26:46.396180 u2DelayCellOfst[15]=18 cells (5 PI)
8484 12:26:46.399327 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8485 12:26:46.403011 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8486 12:26:46.405976 DramC Write-DBI on
8487 12:26:46.406072 ==
8488 12:26:46.409289 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 12:26:46.413056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 12:26:46.413139 ==
8491 12:26:46.413226
8492 12:26:46.413318
8493 12:26:46.416269 TX Vref Scan disable
8494 12:26:46.419174 == TX Byte 0 ==
8495 12:26:46.422889 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8496 12:26:46.422971 == TX Byte 1 ==
8497 12:26:46.429099 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8498 12:26:46.429182 DramC Write-DBI off
8499 12:26:46.429248
8500 12:26:46.429307 [DATLAT]
8501 12:26:46.432287 Freq=1600, CH1 RK0
8502 12:26:46.432370
8503 12:26:46.435800 DATLAT Default: 0xf
8504 12:26:46.435882 0, 0xFFFF, sum = 0
8505 12:26:46.438755 1, 0xFFFF, sum = 0
8506 12:26:46.438838 2, 0xFFFF, sum = 0
8507 12:26:46.442421 3, 0xFFFF, sum = 0
8508 12:26:46.442504 4, 0xFFFF, sum = 0
8509 12:26:46.445831 5, 0xFFFF, sum = 0
8510 12:26:46.445915 6, 0xFFFF, sum = 0
8511 12:26:46.449002 7, 0xFFFF, sum = 0
8512 12:26:46.449086 8, 0xFFFF, sum = 0
8513 12:26:46.452472 9, 0xFFFF, sum = 0
8514 12:26:46.452581 10, 0xFFFF, sum = 0
8515 12:26:46.455476 11, 0xFFFF, sum = 0
8516 12:26:46.455559 12, 0xFFFF, sum = 0
8517 12:26:46.458558 13, 0xFFFF, sum = 0
8518 12:26:46.462214 14, 0x0, sum = 1
8519 12:26:46.462300 15, 0x0, sum = 2
8520 12:26:46.462368 16, 0x0, sum = 3
8521 12:26:46.465238 17, 0x0, sum = 4
8522 12:26:46.465321 best_step = 15
8523 12:26:46.465387
8524 12:26:46.468410 ==
8525 12:26:46.468492 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 12:26:46.475050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 12:26:46.475133 ==
8528 12:26:46.475200 RX Vref Scan: 1
8529 12:26:46.475261
8530 12:26:46.478301 Set Vref Range= 24 -> 127
8531 12:26:46.478383
8532 12:26:46.481922 RX Vref 24 -> 127, step: 1
8533 12:26:46.482004
8534 12:26:46.484879 RX Delay 19 -> 252, step: 4
8535 12:26:46.484961
8536 12:26:46.488191 Set Vref, RX VrefLevel [Byte0]: 24
8537 12:26:46.491644 [Byte1]: 24
8538 12:26:46.491727
8539 12:26:46.494719 Set Vref, RX VrefLevel [Byte0]: 25
8540 12:26:46.498254 [Byte1]: 25
8541 12:26:46.498336
8542 12:26:46.501420 Set Vref, RX VrefLevel [Byte0]: 26
8543 12:26:46.504557 [Byte1]: 26
8544 12:26:46.508360
8545 12:26:46.508474 Set Vref, RX VrefLevel [Byte0]: 27
8546 12:26:46.511435 [Byte1]: 27
8547 12:26:46.515618
8548 12:26:46.515701 Set Vref, RX VrefLevel [Byte0]: 28
8549 12:26:46.519197 [Byte1]: 28
8550 12:26:46.523682
8551 12:26:46.523800 Set Vref, RX VrefLevel [Byte0]: 29
8552 12:26:46.526676 [Byte1]: 29
8553 12:26:46.530970
8554 12:26:46.531069 Set Vref, RX VrefLevel [Byte0]: 30
8555 12:26:46.534055 [Byte1]: 30
8556 12:26:46.538444
8557 12:26:46.538527 Set Vref, RX VrefLevel [Byte0]: 31
8558 12:26:46.542104 [Byte1]: 31
8559 12:26:46.546276
8560 12:26:46.546381 Set Vref, RX VrefLevel [Byte0]: 32
8561 12:26:46.549424 [Byte1]: 32
8562 12:26:46.553416
8563 12:26:46.553529 Set Vref, RX VrefLevel [Byte0]: 33
8564 12:26:46.556717 [Byte1]: 33
8565 12:26:46.561069
8566 12:26:46.561153 Set Vref, RX VrefLevel [Byte0]: 34
8567 12:26:46.564721 [Byte1]: 34
8568 12:26:46.569017
8569 12:26:46.569132 Set Vref, RX VrefLevel [Byte0]: 35
8570 12:26:46.572035 [Byte1]: 35
8571 12:26:46.576480
8572 12:26:46.576557 Set Vref, RX VrefLevel [Byte0]: 36
8573 12:26:46.579780 [Byte1]: 36
8574 12:26:46.583924
8575 12:26:46.584035 Set Vref, RX VrefLevel [Byte0]: 37
8576 12:26:46.587187 [Byte1]: 37
8577 12:26:46.591541
8578 12:26:46.591619 Set Vref, RX VrefLevel [Byte0]: 38
8579 12:26:46.594604 [Byte1]: 38
8580 12:26:46.599401
8581 12:26:46.599474 Set Vref, RX VrefLevel [Byte0]: 39
8582 12:26:46.602402 [Byte1]: 39
8583 12:26:46.606507
8584 12:26:46.606591 Set Vref, RX VrefLevel [Byte0]: 40
8585 12:26:46.609644 [Byte1]: 40
8586 12:26:46.613960
8587 12:26:46.614070 Set Vref, RX VrefLevel [Byte0]: 41
8588 12:26:46.617554 [Byte1]: 41
8589 12:26:46.622068
8590 12:26:46.622154 Set Vref, RX VrefLevel [Byte0]: 42
8591 12:26:46.625179 [Byte1]: 42
8592 12:26:46.629454
8593 12:26:46.629530 Set Vref, RX VrefLevel [Byte0]: 43
8594 12:26:46.632744 [Byte1]: 43
8595 12:26:46.636976
8596 12:26:46.637082 Set Vref, RX VrefLevel [Byte0]: 44
8597 12:26:46.640226 [Byte1]: 44
8598 12:26:46.644621
8599 12:26:46.644733 Set Vref, RX VrefLevel [Byte0]: 45
8600 12:26:46.647974 [Byte1]: 45
8601 12:26:46.652057
8602 12:26:46.652143 Set Vref, RX VrefLevel [Byte0]: 46
8603 12:26:46.655576 [Byte1]: 46
8604 12:26:46.659903
8605 12:26:46.660020 Set Vref, RX VrefLevel [Byte0]: 47
8606 12:26:46.662829 [Byte1]: 47
8607 12:26:46.667126
8608 12:26:46.667210 Set Vref, RX VrefLevel [Byte0]: 48
8609 12:26:46.670761 [Byte1]: 48
8610 12:26:46.675000
8611 12:26:46.675081 Set Vref, RX VrefLevel [Byte0]: 49
8612 12:26:46.678086 [Byte1]: 49
8613 12:26:46.682475
8614 12:26:46.682562 Set Vref, RX VrefLevel [Byte0]: 50
8615 12:26:46.685581 [Byte1]: 50
8616 12:26:46.689865
8617 12:26:46.689974 Set Vref, RX VrefLevel [Byte0]: 51
8618 12:26:46.693003 [Byte1]: 51
8619 12:26:46.697312
8620 12:26:46.697416 Set Vref, RX VrefLevel [Byte0]: 52
8621 12:26:46.700990 [Byte1]: 52
8622 12:26:46.705305
8623 12:26:46.705414 Set Vref, RX VrefLevel [Byte0]: 53
8624 12:26:46.708111 [Byte1]: 53
8625 12:26:46.712813
8626 12:26:46.712932 Set Vref, RX VrefLevel [Byte0]: 54
8627 12:26:46.715736 [Byte1]: 54
8628 12:26:46.720023
8629 12:26:46.720139 Set Vref, RX VrefLevel [Byte0]: 55
8630 12:26:46.723742 [Byte1]: 55
8631 12:26:46.728104
8632 12:26:46.728185 Set Vref, RX VrefLevel [Byte0]: 56
8633 12:26:46.731236 [Byte1]: 56
8634 12:26:46.735395
8635 12:26:46.735474 Set Vref, RX VrefLevel [Byte0]: 57
8636 12:26:46.738544 [Byte1]: 57
8637 12:26:46.742725
8638 12:26:46.742806 Set Vref, RX VrefLevel [Byte0]: 58
8639 12:26:46.745880 [Byte1]: 58
8640 12:26:46.750705
8641 12:26:46.750800 Set Vref, RX VrefLevel [Byte0]: 59
8642 12:26:46.753547 [Byte1]: 59
8643 12:26:46.758394
8644 12:26:46.758481 Set Vref, RX VrefLevel [Byte0]: 60
8645 12:26:46.761154 [Byte1]: 60
8646 12:26:46.765913
8647 12:26:46.765998 Set Vref, RX VrefLevel [Byte0]: 61
8648 12:26:46.768853 [Byte1]: 61
8649 12:26:46.773137
8650 12:26:46.773229 Set Vref, RX VrefLevel [Byte0]: 62
8651 12:26:46.776265 [Byte1]: 62
8652 12:26:46.780521
8653 12:26:46.780610 Set Vref, RX VrefLevel [Byte0]: 63
8654 12:26:46.783774 [Byte1]: 63
8655 12:26:46.788085
8656 12:26:46.788173 Set Vref, RX VrefLevel [Byte0]: 64
8657 12:26:46.792020 [Byte1]: 64
8658 12:26:46.795814
8659 12:26:46.795899 Set Vref, RX VrefLevel [Byte0]: 65
8660 12:26:46.798935 [Byte1]: 65
8661 12:26:46.803379
8662 12:26:46.803469 Set Vref, RX VrefLevel [Byte0]: 66
8663 12:26:46.806967 [Byte1]: 66
8664 12:26:46.811223
8665 12:26:46.811329 Set Vref, RX VrefLevel [Byte0]: 67
8666 12:26:46.814190 [Byte1]: 67
8667 12:26:46.819003
8668 12:26:46.819115 Set Vref, RX VrefLevel [Byte0]: 68
8669 12:26:46.821969 [Byte1]: 68
8670 12:26:46.826242
8671 12:26:46.826349 Set Vref, RX VrefLevel [Byte0]: 69
8672 12:26:46.829461 [Byte1]: 69
8673 12:26:46.833894
8674 12:26:46.834003 Set Vref, RX VrefLevel [Byte0]: 70
8675 12:26:46.836928 [Byte1]: 70
8676 12:26:46.841367
8677 12:26:46.841446 Set Vref, RX VrefLevel [Byte0]: 71
8678 12:26:46.844386 [Byte1]: 71
8679 12:26:46.848623
8680 12:26:46.848735 Final RX Vref Byte 0 = 57 to rank0
8681 12:26:46.852455 Final RX Vref Byte 1 = 62 to rank0
8682 12:26:46.855309 Final RX Vref Byte 0 = 57 to rank1
8683 12:26:46.858912 Final RX Vref Byte 1 = 62 to rank1==
8684 12:26:46.861767 Dram Type= 6, Freq= 0, CH_1, rank 0
8685 12:26:46.868251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8686 12:26:46.868363 ==
8687 12:26:46.868461 DQS Delay:
8688 12:26:46.871937 DQS0 = 0, DQS1 = 0
8689 12:26:46.872051 DQM Delay:
8690 12:26:46.875076 DQM0 = 132, DQM1 = 130
8691 12:26:46.875164 DQ Delay:
8692 12:26:46.878740 DQ0 =142, DQ1 =128, DQ2 =118, DQ3 =132
8693 12:26:46.881794 DQ4 =128, DQ5 =142, DQ6 =146, DQ7 =126
8694 12:26:46.884987 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =122
8695 12:26:46.888563 DQ12 =140, DQ13 =140, DQ14 =136, DQ15 =140
8696 12:26:46.888640
8697 12:26:46.888712
8698 12:26:46.888801
8699 12:26:46.891664 [DramC_TX_OE_Calibration] TA2
8700 12:26:46.894838 Original DQ_B0 (3 6) =30, OEN = 27
8701 12:26:46.898570 Original DQ_B1 (3 6) =30, OEN = 27
8702 12:26:46.901567 24, 0x0, End_B0=24 End_B1=24
8703 12:26:46.904732 25, 0x0, End_B0=25 End_B1=25
8704 12:26:46.904845 26, 0x0, End_B0=26 End_B1=26
8705 12:26:46.908354 27, 0x0, End_B0=27 End_B1=27
8706 12:26:46.911332 28, 0x0, End_B0=28 End_B1=28
8707 12:26:46.915020 29, 0x0, End_B0=29 End_B1=29
8708 12:26:46.915130 30, 0x0, End_B0=30 End_B1=30
8709 12:26:46.918039 31, 0x4141, End_B0=30 End_B1=30
8710 12:26:46.921422 Byte0 end_step=30 best_step=27
8711 12:26:46.924495 Byte1 end_step=30 best_step=27
8712 12:26:46.928141 Byte0 TX OE(2T, 0.5T) = (3, 3)
8713 12:26:46.931208 Byte1 TX OE(2T, 0.5T) = (3, 3)
8714 12:26:46.931305
8715 12:26:46.931373
8716 12:26:46.938082 [DQSOSCAuto] RK0, (LSB)MR18= 0xb14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
8717 12:26:46.941004 CH1 RK0: MR19=303, MR18=B14
8718 12:26:46.947408 CH1_RK0: MR19=0x303, MR18=0xB14, DQSOSC=399, MR23=63, INC=23, DEC=15
8719 12:26:46.947491
8720 12:26:46.951067 ----->DramcWriteLeveling(PI) begin...
8721 12:26:46.951188 ==
8722 12:26:46.954079 Dram Type= 6, Freq= 0, CH_1, rank 1
8723 12:26:46.957293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8724 12:26:46.957405 ==
8725 12:26:46.960790 Write leveling (Byte 0): 24 => 24
8726 12:26:46.964206 Write leveling (Byte 1): 26 => 26
8727 12:26:46.967249 DramcWriteLeveling(PI) end<-----
8728 12:26:46.967356
8729 12:26:46.967452 ==
8730 12:26:46.970790 Dram Type= 6, Freq= 0, CH_1, rank 1
8731 12:26:46.973714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8732 12:26:46.977253 ==
8733 12:26:46.977364 [Gating] SW mode calibration
8734 12:26:46.986835 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8735 12:26:46.990580 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8736 12:26:46.993653 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8737 12:26:47.000465 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8738 12:26:47.003562 1 4 8 | B1->B0 | 2323 3433 | 0 1 | (0 0) (1 1)
8739 12:26:47.006559 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (1 1) (1 1)
8740 12:26:47.013451 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8741 12:26:47.016604 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8742 12:26:47.020247 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8743 12:26:47.026747 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 12:26:47.029998 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 12:26:47.033526 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8746 12:26:47.039745 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8747 12:26:47.043427 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8748 12:26:47.046462 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 12:26:47.052727 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 12:26:47.056386 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 12:26:47.059560 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 12:26:47.066266 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 12:26:47.069793 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8754 12:26:47.072608 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8755 12:26:47.079275 1 6 12 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8756 12:26:47.082424 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8757 12:26:47.085870 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 12:26:47.092640 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8759 12:26:47.095588 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 12:26:47.098885 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 12:26:47.105697 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8762 12:26:47.108866 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8763 12:26:47.112505 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8764 12:26:47.118619 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8765 12:26:47.122396 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 12:26:47.125464 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 12:26:47.132451 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 12:26:47.135358 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 12:26:47.138615 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 12:26:47.145333 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 12:26:47.148573 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 12:26:47.151540 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 12:26:47.158519 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 12:26:47.161853 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 12:26:47.164702 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 12:26:47.171398 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 12:26:47.174919 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8778 12:26:47.177894 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8779 12:26:47.184502 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8780 12:26:47.188055 Total UI for P1: 0, mck2ui 16
8781 12:26:47.191065 best dqsien dly found for B0: ( 1, 9, 6)
8782 12:26:47.194877 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8783 12:26:47.197885 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 12:26:47.200970 Total UI for P1: 0, mck2ui 16
8785 12:26:47.204833 best dqsien dly found for B1: ( 1, 9, 12)
8786 12:26:47.207782 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8787 12:26:47.214072 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8788 12:26:47.214161
8789 12:26:47.217620 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8790 12:26:47.220653 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8791 12:26:47.224448 [Gating] SW calibration Done
8792 12:26:47.224533 ==
8793 12:26:47.227415 Dram Type= 6, Freq= 0, CH_1, rank 1
8794 12:26:47.230500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 12:26:47.230589 ==
8796 12:26:47.234117 RX Vref Scan: 0
8797 12:26:47.234203
8798 12:26:47.234271 RX Vref 0 -> 0, step: 1
8799 12:26:47.234336
8800 12:26:47.237144 RX Delay 0 -> 252, step: 8
8801 12:26:47.240589 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8802 12:26:47.246835 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8803 12:26:47.250594 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8804 12:26:47.253622 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8805 12:26:47.256619 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8806 12:26:47.259943 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8807 12:26:47.266625 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8808 12:26:47.270303 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8809 12:26:47.273338 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8810 12:26:47.276911 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8811 12:26:47.279847 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8812 12:26:47.286332 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8813 12:26:47.289528 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8814 12:26:47.292959 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8815 12:26:47.296548 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8816 12:26:47.302761 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8817 12:26:47.302854 ==
8818 12:26:47.306519 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 12:26:47.309563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 12:26:47.309649 ==
8821 12:26:47.309718 DQS Delay:
8822 12:26:47.313142 DQS0 = 0, DQS1 = 0
8823 12:26:47.313232 DQM Delay:
8824 12:26:47.316227 DQM0 = 135, DQM1 = 130
8825 12:26:47.316309 DQ Delay:
8826 12:26:47.319501 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8827 12:26:47.322632 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =135
8828 12:26:47.326105 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8829 12:26:47.329164 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8830 12:26:47.332266
8831 12:26:47.332347
8832 12:26:47.332425 ==
8833 12:26:47.336143 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 12:26:47.339203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 12:26:47.339294 ==
8836 12:26:47.339365
8837 12:26:47.339427
8838 12:26:47.342755 TX Vref Scan disable
8839 12:26:47.342844 == TX Byte 0 ==
8840 12:26:47.349092 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8841 12:26:47.352139 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8842 12:26:47.352254 == TX Byte 1 ==
8843 12:26:47.359121 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8844 12:26:47.362056 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8845 12:26:47.362135 ==
8846 12:26:47.365184 Dram Type= 6, Freq= 0, CH_1, rank 1
8847 12:26:47.368298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8848 12:26:47.368382 ==
8849 12:26:47.384268
8850 12:26:47.387805 TX Vref early break, caculate TX vref
8851 12:26:47.391371 TX Vref=16, minBit 9, minWin=22, winSum=379
8852 12:26:47.394357 TX Vref=18, minBit 9, minWin=22, winSum=387
8853 12:26:47.397378 TX Vref=20, minBit 9, minWin=22, winSum=390
8854 12:26:47.401013 TX Vref=22, minBit 9, minWin=23, winSum=398
8855 12:26:47.404219 TX Vref=24, minBit 9, minWin=24, winSum=408
8856 12:26:47.411021 TX Vref=26, minBit 9, minWin=24, winSum=413
8857 12:26:47.414130 TX Vref=28, minBit 5, minWin=25, winSum=417
8858 12:26:47.417169 TX Vref=30, minBit 5, minWin=25, winSum=414
8859 12:26:47.420857 TX Vref=32, minBit 0, minWin=25, winSum=413
8860 12:26:47.423985 TX Vref=34, minBit 8, minWin=24, winSum=405
8861 12:26:47.430946 TX Vref=36, minBit 9, minWin=23, winSum=400
8862 12:26:47.433980 TX Vref=38, minBit 9, minWin=22, winSum=387
8863 12:26:47.437130 [TxChooseVref] Worse bit 5, Min win 25, Win sum 417, Final Vref 28
8864 12:26:47.440799
8865 12:26:47.440883 Final TX Range 0 Vref 28
8866 12:26:47.440969
8867 12:26:47.441048 ==
8868 12:26:47.443635 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 12:26:47.450081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 12:26:47.450167 ==
8871 12:26:47.450251
8872 12:26:47.450330
8873 12:26:47.450408 TX Vref Scan disable
8874 12:26:47.457442 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8875 12:26:47.457551 == TX Byte 0 ==
8876 12:26:47.461288 u2DelayCellOfst[0]=14 cells (4 PI)
8877 12:26:47.464528 u2DelayCellOfst[1]=10 cells (3 PI)
8878 12:26:47.467549 u2DelayCellOfst[2]=0 cells (0 PI)
8879 12:26:47.470537 u2DelayCellOfst[3]=7 cells (2 PI)
8880 12:26:47.474276 u2DelayCellOfst[4]=7 cells (2 PI)
8881 12:26:47.477387 u2DelayCellOfst[5]=14 cells (4 PI)
8882 12:26:47.480360 u2DelayCellOfst[6]=18 cells (5 PI)
8883 12:26:47.484150 u2DelayCellOfst[7]=7 cells (2 PI)
8884 12:26:47.487156 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8885 12:26:47.490739 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8886 12:26:47.493709 == TX Byte 1 ==
8887 12:26:47.497152 u2DelayCellOfst[8]=0 cells (0 PI)
8888 12:26:47.500290 u2DelayCellOfst[9]=3 cells (1 PI)
8889 12:26:47.503751 u2DelayCellOfst[10]=10 cells (3 PI)
8890 12:26:47.506684 u2DelayCellOfst[11]=7 cells (2 PI)
8891 12:26:47.510358 u2DelayCellOfst[12]=14 cells (4 PI)
8892 12:26:47.513554 u2DelayCellOfst[13]=14 cells (4 PI)
8893 12:26:47.516574 u2DelayCellOfst[14]=18 cells (5 PI)
8894 12:26:47.519769 u2DelayCellOfst[15]=18 cells (5 PI)
8895 12:26:47.523607 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8896 12:26:47.526563 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8897 12:26:47.529768 DramC Write-DBI on
8898 12:26:47.529853 ==
8899 12:26:47.533322 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 12:26:47.536517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 12:26:47.536602 ==
8902 12:26:47.536687
8903 12:26:47.536767
8904 12:26:47.539541 TX Vref Scan disable
8905 12:26:47.542712 == TX Byte 0 ==
8906 12:26:47.546283 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8907 12:26:47.546368 == TX Byte 1 ==
8908 12:26:47.552965 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8909 12:26:47.553050 DramC Write-DBI off
8910 12:26:47.553134
8911 12:26:47.553213 [DATLAT]
8912 12:26:47.556069 Freq=1600, CH1 RK1
8913 12:26:47.556152
8914 12:26:47.559852 DATLAT Default: 0xf
8915 12:26:47.559935 0, 0xFFFF, sum = 0
8916 12:26:47.562945 1, 0xFFFF, sum = 0
8917 12:26:47.563029 2, 0xFFFF, sum = 0
8918 12:26:47.566063 3, 0xFFFF, sum = 0
8919 12:26:47.566147 4, 0xFFFF, sum = 0
8920 12:26:47.569062 5, 0xFFFF, sum = 0
8921 12:26:47.569147 6, 0xFFFF, sum = 0
8922 12:26:47.572635 7, 0xFFFF, sum = 0
8923 12:26:47.572718 8, 0xFFFF, sum = 0
8924 12:26:47.575692 9, 0xFFFF, sum = 0
8925 12:26:47.575776 10, 0xFFFF, sum = 0
8926 12:26:47.579603 11, 0xFFFF, sum = 0
8927 12:26:47.579698 12, 0xFFFF, sum = 0
8928 12:26:47.582028 13, 0xFFFF, sum = 0
8929 12:26:47.586099 14, 0x0, sum = 1
8930 12:26:47.586183 15, 0x0, sum = 2
8931 12:26:47.586250 16, 0x0, sum = 3
8932 12:26:47.588905 17, 0x0, sum = 4
8933 12:26:47.589006 best_step = 15
8934 12:26:47.589104
8935 12:26:47.592831 ==
8936 12:26:47.592915 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 12:26:47.598439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 12:26:47.598561 ==
8939 12:26:47.598673 RX Vref Scan: 0
8940 12:26:47.598763
8941 12:26:47.602163 RX Vref 0 -> 0, step: 1
8942 12:26:47.602318
8943 12:26:47.605095 RX Delay 11 -> 252, step: 4
8944 12:26:47.608488 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8945 12:26:47.611556 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8946 12:26:47.618317 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8947 12:26:47.621327 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8948 12:26:47.625178 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8949 12:26:47.628138 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8950 12:26:47.631436 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8951 12:26:47.638052 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8952 12:26:47.641170 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8953 12:26:47.644784 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8954 12:26:47.648441 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8955 12:26:47.654570 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8956 12:26:47.658232 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8957 12:26:47.661289 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
8958 12:26:47.664958 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8959 12:26:47.668040 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8960 12:26:47.671165 ==
8961 12:26:47.674680 Dram Type= 6, Freq= 0, CH_1, rank 1
8962 12:26:47.677745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8963 12:26:47.677831 ==
8964 12:26:47.677899 DQS Delay:
8965 12:26:47.680911 DQS0 = 0, DQS1 = 0
8966 12:26:47.680996 DQM Delay:
8967 12:26:47.684600 DQM0 = 132, DQM1 = 127
8968 12:26:47.684685 DQ Delay:
8969 12:26:47.687677 DQ0 =136, DQ1 =132, DQ2 =120, DQ3 =130
8970 12:26:47.691247 DQ4 =132, DQ5 =142, DQ6 =140, DQ7 =128
8971 12:26:47.694366 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
8972 12:26:47.697451 DQ12 =136, DQ13 =134, DQ14 =132, DQ15 =138
8973 12:26:47.697544
8974 12:26:47.697611
8975 12:26:47.697673
8976 12:26:47.701051 [DramC_TX_OE_Calibration] TA2
8977 12:26:47.703834 Original DQ_B0 (3 6) =30, OEN = 27
8978 12:26:47.707608 Original DQ_B1 (3 6) =30, OEN = 27
8979 12:26:47.710496 24, 0x0, End_B0=24 End_B1=24
8980 12:26:47.714189 25, 0x0, End_B0=25 End_B1=25
8981 12:26:47.717262 26, 0x0, End_B0=26 End_B1=26
8982 12:26:47.717347 27, 0x0, End_B0=27 End_B1=27
8983 12:26:47.720775 28, 0x0, End_B0=28 End_B1=28
8984 12:26:47.723880 29, 0x0, End_B0=29 End_B1=29
8985 12:26:47.726771 30, 0x0, End_B0=30 End_B1=30
8986 12:26:47.730072 31, 0x4141, End_B0=30 End_B1=30
8987 12:26:47.730158 Byte0 end_step=30 best_step=27
8988 12:26:47.733871 Byte1 end_step=30 best_step=27
8989 12:26:47.737026 Byte0 TX OE(2T, 0.5T) = (3, 3)
8990 12:26:47.740045 Byte1 TX OE(2T, 0.5T) = (3, 3)
8991 12:26:47.740130
8992 12:26:47.740197
8993 12:26:47.746811 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
8994 12:26:47.750069 CH1 RK1: MR19=303, MR18=E1C
8995 12:26:47.756842 CH1_RK1: MR19=0x303, MR18=0xE1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8996 12:26:47.759805 [RxdqsGatingPostProcess] freq 1600
8997 12:26:47.766568 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8998 12:26:47.769724 best DQS0 dly(2T, 0.5T) = (1, 1)
8999 12:26:47.769808 best DQS1 dly(2T, 0.5T) = (1, 1)
9000 12:26:47.773463 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9001 12:26:47.776552 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9002 12:26:47.779409 best DQS0 dly(2T, 0.5T) = (1, 1)
9003 12:26:47.783230 best DQS1 dly(2T, 0.5T) = (1, 1)
9004 12:26:47.786171 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9005 12:26:47.789366 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9006 12:26:47.792538 Pre-setting of DQS Precalculation
9007 12:26:47.799478 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9008 12:26:47.805842 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9009 12:26:47.812500 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9010 12:26:47.812585
9011 12:26:47.812651
9012 12:26:47.815534 [Calibration Summary] 3200 Mbps
9013 12:26:47.815643 CH 0, Rank 0
9014 12:26:47.819073 SW Impedance : PASS
9015 12:26:47.822066 DUTY Scan : NO K
9016 12:26:47.822179 ZQ Calibration : PASS
9017 12:26:47.825273 Jitter Meter : NO K
9018 12:26:47.829205 CBT Training : PASS
9019 12:26:47.829315 Write leveling : PASS
9020 12:26:47.832198 RX DQS gating : PASS
9021 12:26:47.835361 RX DQ/DQS(RDDQC) : PASS
9022 12:26:47.835437 TX DQ/DQS : PASS
9023 12:26:47.838482 RX DATLAT : PASS
9024 12:26:47.842024 RX DQ/DQS(Engine): PASS
9025 12:26:47.842130 TX OE : PASS
9026 12:26:47.845167 All Pass.
9027 12:26:47.845267
9028 12:26:47.845364 CH 0, Rank 1
9029 12:26:47.849026 SW Impedance : PASS
9030 12:26:47.849101 DUTY Scan : NO K
9031 12:26:47.852027 ZQ Calibration : PASS
9032 12:26:47.855133 Jitter Meter : NO K
9033 12:26:47.855250 CBT Training : PASS
9034 12:26:47.858188 Write leveling : PASS
9035 12:26:47.861992 RX DQS gating : PASS
9036 12:26:47.862096 RX DQ/DQS(RDDQC) : PASS
9037 12:26:47.865029 TX DQ/DQS : PASS
9038 12:26:47.865103 RX DATLAT : PASS
9039 12:26:47.868043 RX DQ/DQS(Engine): PASS
9040 12:26:47.871749 TX OE : PASS
9041 12:26:47.871827 All Pass.
9042 12:26:47.871916
9043 12:26:47.874897 CH 1, Rank 0
9044 12:26:47.874996 SW Impedance : PASS
9045 12:26:47.878599 DUTY Scan : NO K
9046 12:26:47.878700 ZQ Calibration : PASS
9047 12:26:47.881639 Jitter Meter : NO K
9048 12:26:47.884653 CBT Training : PASS
9049 12:26:47.884731 Write leveling : PASS
9050 12:26:47.888468 RX DQS gating : PASS
9051 12:26:47.891521 RX DQ/DQS(RDDQC) : PASS
9052 12:26:47.891621 TX DQ/DQS : PASS
9053 12:26:47.894533 RX DATLAT : PASS
9054 12:26:47.897668 RX DQ/DQS(Engine): PASS
9055 12:26:47.897766 TX OE : PASS
9056 12:26:47.901449 All Pass.
9057 12:26:47.901547
9058 12:26:47.901636 CH 1, Rank 1
9059 12:26:47.904568 SW Impedance : PASS
9060 12:26:47.904642 DUTY Scan : NO K
9061 12:26:47.908021 ZQ Calibration : PASS
9062 12:26:47.910938 Jitter Meter : NO K
9063 12:26:47.911047 CBT Training : PASS
9064 12:26:47.914344 Write leveling : PASS
9065 12:26:47.917997 RX DQS gating : PASS
9066 12:26:47.918197 RX DQ/DQS(RDDQC) : PASS
9067 12:26:47.920955 TX DQ/DQS : PASS
9068 12:26:47.923907 RX DATLAT : PASS
9069 12:26:47.924047 RX DQ/DQS(Engine): PASS
9070 12:26:47.927482 TX OE : PASS
9071 12:26:47.927585 All Pass.
9072 12:26:47.927678
9073 12:26:47.930736 DramC Write-DBI on
9074 12:26:47.934322 PER_BANK_REFRESH: Hybrid Mode
9075 12:26:47.934406 TX_TRACKING: ON
9076 12:26:47.943625 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9077 12:26:47.950409 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9078 12:26:47.957126 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9079 12:26:47.964122 [FAST_K] Save calibration result to emmc
9080 12:26:47.964207 sync common calibartion params.
9081 12:26:47.967104 sync cbt_mode0:1, 1:1
9082 12:26:47.970285 dram_init: ddr_geometry: 2
9083 12:26:47.970368 dram_init: ddr_geometry: 2
9084 12:26:47.973264 dram_init: ddr_geometry: 2
9085 12:26:47.977095 0:dram_rank_size:100000000
9086 12:26:47.980077 1:dram_rank_size:100000000
9087 12:26:47.983199 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9088 12:26:47.986915 DFS_SHUFFLE_HW_MODE: ON
9089 12:26:47.989964 dramc_set_vcore_voltage set vcore to 725000
9090 12:26:47.993204 Read voltage for 1600, 0
9091 12:26:47.993305 Vio18 = 0
9092 12:26:47.996910 Vcore = 725000
9093 12:26:47.996989 Vdram = 0
9094 12:26:47.997089 Vddq = 0
9095 12:26:47.997186 Vmddr = 0
9096 12:26:47.999879 switch to 3200 Mbps bootup
9097 12:26:48.002937 [DramcRunTimeConfig]
9098 12:26:48.003041 PHYPLL
9099 12:26:48.006254 DPM_CONTROL_AFTERK: ON
9100 12:26:48.006360 PER_BANK_REFRESH: ON
9101 12:26:48.009824 REFRESH_OVERHEAD_REDUCTION: ON
9102 12:26:48.012787 CMD_PICG_NEW_MODE: OFF
9103 12:26:48.012891 XRTWTW_NEW_MODE: ON
9104 12:26:48.016548 XRTRTR_NEW_MODE: ON
9105 12:26:48.016632 TX_TRACKING: ON
9106 12:26:48.019457 RDSEL_TRACKING: OFF
9107 12:26:48.022917 DQS Precalculation for DVFS: ON
9108 12:26:48.023000 RX_TRACKING: OFF
9109 12:26:48.026153 HW_GATING DBG: ON
9110 12:26:48.026237 ZQCS_ENABLE_LP4: ON
9111 12:26:48.029561 RX_PICG_NEW_MODE: ON
9112 12:26:48.029643 TX_PICG_NEW_MODE: ON
9113 12:26:48.032760 ENABLE_RX_DCM_DPHY: ON
9114 12:26:48.035874 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9115 12:26:48.039516 DUMMY_READ_FOR_TRACKING: OFF
9116 12:26:48.039599 !!! SPM_CONTROL_AFTERK: OFF
9117 12:26:48.042712 !!! SPM could not control APHY
9118 12:26:48.045949 IMPEDANCE_TRACKING: ON
9119 12:26:48.046046 TEMP_SENSOR: ON
9120 12:26:48.048967 HW_SAVE_FOR_SR: OFF
9121 12:26:48.052611 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9122 12:26:48.055893 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9123 12:26:48.055996 Read ODT Tracking: ON
9124 12:26:48.058861 Refresh Rate DeBounce: ON
9125 12:26:48.062156 DFS_NO_QUEUE_FLUSH: ON
9126 12:26:48.065970 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9127 12:26:48.069149 ENABLE_DFS_RUNTIME_MRW: OFF
9128 12:26:48.069241 DDR_RESERVE_NEW_MODE: ON
9129 12:26:48.072160 MR_CBT_SWITCH_FREQ: ON
9130 12:26:48.075190 =========================
9131 12:26:48.093042 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9132 12:26:48.096163 dram_init: ddr_geometry: 2
9133 12:26:48.114596 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9134 12:26:48.117535 dram_init: dram init end (result: 0)
9135 12:26:48.123967 DRAM-K: Full calibration passed in 24458 msecs
9136 12:26:48.127717 MRC: failed to locate region type 0.
9137 12:26:48.127801 DRAM rank0 size:0x100000000,
9138 12:26:48.130949 DRAM rank1 size=0x100000000
9139 12:26:48.140898 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9140 12:26:48.146987 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9141 12:26:48.156799 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9142 12:26:48.163723 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9143 12:26:48.163808 DRAM rank0 size:0x100000000,
9144 12:26:48.166718 DRAM rank1 size=0x100000000
9145 12:26:48.166793 CBMEM:
9146 12:26:48.169954 IMD: root @ 0xfffff000 254 entries.
9147 12:26:48.173604 IMD: root @ 0xffffec00 62 entries.
9148 12:26:48.179760 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9149 12:26:48.183318 WARNING: RO_VPD is uninitialized or empty.
9150 12:26:48.186463 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9151 12:26:48.194630 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9152 12:26:48.206990 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9153 12:26:48.218924 BS: romstage times (exec / console): total (unknown) / 23985 ms
9154 12:26:48.219020
9155 12:26:48.219091
9156 12:26:48.228242 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9157 12:26:48.231643 ARM64: Exception handlers installed.
9158 12:26:48.235144 ARM64: Testing exception
9159 12:26:48.238244 ARM64: Done test exception
9160 12:26:48.238358 Enumerating buses...
9161 12:26:48.241328 Show all devs... Before device enumeration.
9162 12:26:48.244652 Root Device: enabled 1
9163 12:26:48.248208 CPU_CLUSTER: 0: enabled 1
9164 12:26:48.248293 CPU: 00: enabled 1
9165 12:26:48.251279 Compare with tree...
9166 12:26:48.251371 Root Device: enabled 1
9167 12:26:48.254405 CPU_CLUSTER: 0: enabled 1
9168 12:26:48.257944 CPU: 00: enabled 1
9169 12:26:48.258053 Root Device scanning...
9170 12:26:48.261061 scan_static_bus for Root Device
9171 12:26:48.264715 CPU_CLUSTER: 0 enabled
9172 12:26:48.267773 scan_static_bus for Root Device done
9173 12:26:48.270882 scan_bus: bus Root Device finished in 8 msecs
9174 12:26:48.270982 done
9175 12:26:48.277811 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9176 12:26:48.280879 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9177 12:26:48.287438 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9178 12:26:48.294093 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9179 12:26:48.294204 Allocating resources...
9180 12:26:48.298015 Reading resources...
9181 12:26:48.300974 Root Device read_resources bus 0 link: 0
9182 12:26:48.304087 DRAM rank0 size:0x100000000,
9183 12:26:48.304164 DRAM rank1 size=0x100000000
9184 12:26:48.311048 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9185 12:26:48.311167 CPU: 00 missing read_resources
9186 12:26:48.317234 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9187 12:26:48.321039 Root Device read_resources bus 0 link: 0 done
9188 12:26:48.323967 Done reading resources.
9189 12:26:48.327025 Show resources in subtree (Root Device)...After reading.
9190 12:26:48.330654 Root Device child on link 0 CPU_CLUSTER: 0
9191 12:26:48.333774 CPU_CLUSTER: 0 child on link 0 CPU: 00
9192 12:26:48.343439 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9193 12:26:48.343616 CPU: 00
9194 12:26:48.350084 Root Device assign_resources, bus 0 link: 0
9195 12:26:48.353362 CPU_CLUSTER: 0 missing set_resources
9196 12:26:48.357142 Root Device assign_resources, bus 0 link: 0 done
9197 12:26:48.360163 Done setting resources.
9198 12:26:48.363225 Show resources in subtree (Root Device)...After assigning values.
9199 12:26:48.367086 Root Device child on link 0 CPU_CLUSTER: 0
9200 12:26:48.373190 CPU_CLUSTER: 0 child on link 0 CPU: 00
9201 12:26:48.379950 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9202 12:26:48.383091 CPU: 00
9203 12:26:48.383174 Done allocating resources.
9204 12:26:48.389886 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9205 12:26:48.389971 Enabling resources...
9206 12:26:48.393328 done.
9207 12:26:48.396335 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9208 12:26:48.399984 Initializing devices...
9209 12:26:48.400100 Root Device init
9210 12:26:48.403156 init hardware done!
9211 12:26:48.403254 0x00000018: ctrlr->caps
9212 12:26:48.406188 52.000 MHz: ctrlr->f_max
9213 12:26:48.409556 0.400 MHz: ctrlr->f_min
9214 12:26:48.413305 0x40ff8080: ctrlr->voltages
9215 12:26:48.413435 sclk: 390625
9216 12:26:48.413552 Bus Width = 1
9217 12:26:48.416248 sclk: 390625
9218 12:26:48.416428 Bus Width = 1
9219 12:26:48.419447 Early init status = 3
9220 12:26:48.422654 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9221 12:26:48.426979 in-header: 03 fc 00 00 01 00 00 00
9222 12:26:48.430697 in-data: 00
9223 12:26:48.433850 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9224 12:26:48.439364 in-header: 03 fd 00 00 00 00 00 00
9225 12:26:48.442885 in-data:
9226 12:26:48.445851 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9227 12:26:48.450337 in-header: 03 fc 00 00 01 00 00 00
9228 12:26:48.453394 in-data: 00
9229 12:26:48.456983 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9230 12:26:48.462301 in-header: 03 fd 00 00 00 00 00 00
9231 12:26:48.465790 in-data:
9232 12:26:48.468974 [SSUSB] Setting up USB HOST controller...
9233 12:26:48.472709 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9234 12:26:48.475747 [SSUSB] phy power-on done.
9235 12:26:48.478992 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9236 12:26:48.485779 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9237 12:26:48.488910 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9238 12:26:48.495569 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9239 12:26:48.502066 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9240 12:26:48.508292 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9241 12:26:48.515039 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9242 12:26:48.521749 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9243 12:26:48.524937 SPM: binary array size = 0x9dc
9244 12:26:48.528464 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9245 12:26:48.534596 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9246 12:26:48.541655 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9247 12:26:48.547774 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9248 12:26:48.551401 configure_display: Starting display init
9249 12:26:48.585576 anx7625_power_on_init: Init interface.
9250 12:26:48.588753 anx7625_disable_pd_protocol: Disabled PD feature.
9251 12:26:48.592211 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9252 12:26:48.620317 anx7625_start_dp_work: Secure OCM version=00
9253 12:26:48.623307 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9254 12:26:48.638066 sp_tx_get_edid_block: EDID Block = 1
9255 12:26:48.740755 Extracted contents:
9256 12:26:48.743883 header: 00 ff ff ff ff ff ff 00
9257 12:26:48.746998 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9258 12:26:48.750313 version: 01 04
9259 12:26:48.753853 basic params: 95 1f 11 78 0a
9260 12:26:48.757263 chroma info: 76 90 94 55 54 90 27 21 50 54
9261 12:26:48.760202 established: 00 00 00
9262 12:26:48.766736 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9263 12:26:48.770478 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9264 12:26:48.776936 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9265 12:26:48.783702 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9266 12:26:48.789810 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9267 12:26:48.793166 extensions: 00
9268 12:26:48.793437 checksum: fb
9269 12:26:48.793623
9270 12:26:48.799785 Manufacturer: IVO Model 57d Serial Number 0
9271 12:26:48.799984 Made week 0 of 2020
9272 12:26:48.803075 EDID version: 1.4
9273 12:26:48.803391 Digital display
9274 12:26:48.806523 6 bits per primary color channel
9275 12:26:48.806686 DisplayPort interface
9276 12:26:48.809637 Maximum image size: 31 cm x 17 cm
9277 12:26:48.813087 Gamma: 220%
9278 12:26:48.813287 Check DPMS levels
9279 12:26:48.819370 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9280 12:26:48.823187 First detailed timing is preferred timing
9281 12:26:48.823344 Established timings supported:
9282 12:26:48.826246 Standard timings supported:
9283 12:26:48.829269 Detailed timings
9284 12:26:48.833052 Hex of detail: 383680a07038204018303c0035ae10000019
9285 12:26:48.839640 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9286 12:26:48.842948 0780 0798 07c8 0820 hborder 0
9287 12:26:48.846067 0438 043b 0447 0458 vborder 0
9288 12:26:48.849061 -hsync -vsync
9289 12:26:48.849237 Did detailed timing
9290 12:26:48.856202 Hex of detail: 000000000000000000000000000000000000
9291 12:26:48.858998 Manufacturer-specified data, tag 0
9292 12:26:48.862632 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9293 12:26:48.865656 ASCII string: InfoVision
9294 12:26:48.869331 Hex of detail: 000000fe00523134304e574635205248200a
9295 12:26:48.872364 ASCII string: R140NWF5 RH
9296 12:26:48.872450 Checksum
9297 12:26:48.875759 Checksum: 0xfb (valid)
9298 12:26:48.879095 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9299 12:26:48.882099 DSI data_rate: 832800000 bps
9300 12:26:48.888762 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9301 12:26:48.892328 anx7625_parse_edid: pixelclock(138800).
9302 12:26:48.895452 hactive(1920), hsync(48), hfp(24), hbp(88)
9303 12:26:48.898686 vactive(1080), vsync(12), vfp(3), vbp(17)
9304 12:26:48.901654 anx7625_dsi_config: config dsi.
9305 12:26:48.908645 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9306 12:26:48.922819 anx7625_dsi_config: success to config DSI
9307 12:26:48.925874 anx7625_dp_start: MIPI phy setup OK.
9308 12:26:48.929471 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9309 12:26:48.932555 mtk_ddp_mode_set invalid vrefresh 60
9310 12:26:48.935623 main_disp_path_setup
9311 12:26:48.935828 ovl_layer_smi_id_en
9312 12:26:48.939483 ovl_layer_smi_id_en
9313 12:26:48.939732 ccorr_config
9314 12:26:48.939941 aal_config
9315 12:26:48.942437 gamma_config
9316 12:26:48.942783 postmask_config
9317 12:26:48.945745 dither_config
9318 12:26:48.949493 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9319 12:26:48.955776 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9320 12:26:48.958894 Root Device init finished in 555 msecs
9321 12:26:48.962242 CPU_CLUSTER: 0 init
9322 12:26:48.968902 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9323 12:26:48.975935 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9324 12:26:48.976591 APU_MBOX 0x190000b0 = 0x10001
9325 12:26:48.978966 APU_MBOX 0x190001b0 = 0x10001
9326 12:26:48.982163 APU_MBOX 0x190005b0 = 0x10001
9327 12:26:48.985795 APU_MBOX 0x190006b0 = 0x10001
9328 12:26:48.991852 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9329 12:26:49.001855 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9330 12:26:49.014578 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9331 12:26:49.020946 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9332 12:26:49.032849 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9333 12:26:49.041509 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9334 12:26:49.045068 CPU_CLUSTER: 0 init finished in 81 msecs
9335 12:26:49.048377 Devices initialized
9336 12:26:49.051266 Show all devs... After init.
9337 12:26:49.051877 Root Device: enabled 1
9338 12:26:49.055062 CPU_CLUSTER: 0: enabled 1
9339 12:26:49.058108 CPU: 00: enabled 1
9340 12:26:49.061273 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9341 12:26:49.064782 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9342 12:26:49.067960 ELOG: NV offset 0x57f000 size 0x1000
9343 12:26:49.074761 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9344 12:26:49.081284 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9345 12:26:49.084800 ELOG: Event(17) added with size 13 at 2023-06-06 12:26:49 UTC
9346 12:26:49.090904 out: cmd=0x121: 03 db 21 01 00 00 00 00
9347 12:26:49.094711 in-header: 03 05 00 00 2c 00 00 00
9348 12:26:49.104459 in-data: 5a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9349 12:26:49.110531 ELOG: Event(A1) added with size 10 at 2023-06-06 12:26:49 UTC
9350 12:26:49.117391 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9351 12:26:49.123767 ELOG: Event(A0) added with size 9 at 2023-06-06 12:26:49 UTC
9352 12:26:49.127241 elog_add_boot_reason: Logged dev mode boot
9353 12:26:49.133965 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9354 12:26:49.134119 Finalize devices...
9355 12:26:49.137168 Devices finalized
9356 12:26:49.140340 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9357 12:26:49.144012 Writing coreboot table at 0xffe64000
9358 12:26:49.147005 0. 000000000010a000-0000000000113fff: RAMSTAGE
9359 12:26:49.153874 1. 0000000040000000-00000000400fffff: RAM
9360 12:26:49.157084 2. 0000000040100000-000000004032afff: RAMSTAGE
9361 12:26:49.160073 3. 000000004032b000-00000000545fffff: RAM
9362 12:26:49.163432 4. 0000000054600000-000000005465ffff: BL31
9363 12:26:49.167017 5. 0000000054660000-00000000ffe63fff: RAM
9364 12:26:49.173190 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9365 12:26:49.176865 7. 0000000100000000-000000023fffffff: RAM
9366 12:26:49.179923 Passing 5 GPIOs to payload:
9367 12:26:49.183365 NAME | PORT | POLARITY | VALUE
9368 12:26:49.189947 EC in RW | 0x000000aa | low | undefined
9369 12:26:49.192825 EC interrupt | 0x00000005 | low | undefined
9370 12:26:49.199541 TPM interrupt | 0x000000ab | high | undefined
9371 12:26:49.202584 SD card detect | 0x00000011 | high | undefined
9372 12:26:49.206020 speaker enable | 0x00000093 | high | undefined
9373 12:26:49.209191 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9374 12:26:49.212809 in-header: 03 f9 00 00 02 00 00 00
9375 12:26:49.216012 in-data: 02 00
9376 12:26:49.219543 ADC[4]: Raw value=902955 ID=7
9377 12:26:49.222577 ADC[3]: Raw value=213546 ID=1
9378 12:26:49.222852 RAM Code: 0x71
9379 12:26:49.226262 ADC[6]: Raw value=75000 ID=0
9380 12:26:49.229263 ADC[5]: Raw value=213546 ID=1
9381 12:26:49.229399 SKU Code: 0x1
9382 12:26:49.236330 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a51a
9383 12:26:49.236422 coreboot table: 964 bytes.
9384 12:26:49.239348 IMD ROOT 0. 0xfffff000 0x00001000
9385 12:26:49.242591 IMD SMALL 1. 0xffffe000 0x00001000
9386 12:26:49.246224 RO MCACHE 2. 0xffffc000 0x00001104
9387 12:26:49.249432 CONSOLE 3. 0xfff7c000 0x00080000
9388 12:26:49.252370 FMAP 4. 0xfff7b000 0x00000452
9389 12:26:49.255483 TIME STAMP 5. 0xfff7a000 0x00000910
9390 12:26:49.259220 VBOOT WORK 6. 0xfff66000 0x00014000
9391 12:26:49.262304 RAMOOPS 7. 0xffe66000 0x00100000
9392 12:26:49.265488 COREBOOT 8. 0xffe64000 0x00002000
9393 12:26:49.269285 IMD small region:
9394 12:26:49.272271 IMD ROOT 0. 0xffffec00 0x00000400
9395 12:26:49.275416 VPD 1. 0xffffeba0 0x0000004c
9396 12:26:49.278510 MMC STATUS 2. 0xffffeb80 0x00000004
9397 12:26:49.285315 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9398 12:26:49.285402 Probing TPM: done!
9399 12:26:49.291720 Connected to device vid:did:rid of 1ae0:0028:00
9400 12:26:49.298810 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9401 12:26:49.301753 Initialized TPM device CR50 revision 0
9402 12:26:49.305577 Checking cr50 for pending updates
9403 12:26:49.310934 Reading cr50 TPM mode
9404 12:26:49.319694 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9405 12:26:49.326578 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9406 12:26:49.366276 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9407 12:26:49.370022 Checking segment from ROM address 0x40100000
9408 12:26:49.373159 Checking segment from ROM address 0x4010001c
9409 12:26:49.379984 Loading segment from ROM address 0x40100000
9410 12:26:49.380242 code (compression=0)
9411 12:26:49.389886 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9412 12:26:49.396473 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9413 12:26:49.396630 it's not compressed!
9414 12:26:49.402825 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9415 12:26:49.409497 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9416 12:26:49.426907 Loading segment from ROM address 0x4010001c
9417 12:26:49.427061 Entry Point 0x80000000
9418 12:26:49.430093 Loaded segments
9419 12:26:49.433724 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9420 12:26:49.440532 Jumping to boot code at 0x80000000(0xffe64000)
9421 12:26:49.447106 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9422 12:26:49.453349 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9423 12:26:49.461625 read SPI 0x8eb68 0x74a8: 3225 us, 9260 KB/s, 74.080 Mbps
9424 12:26:49.464736 Checking segment from ROM address 0x40100000
9425 12:26:49.468437 Checking segment from ROM address 0x4010001c
9426 12:26:49.474769 Loading segment from ROM address 0x40100000
9427 12:26:49.475098 code (compression=1)
9428 12:26:49.481652 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9429 12:26:49.491486 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9430 12:26:49.491979 using LZMA
9431 12:26:49.499570 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9432 12:26:49.505946 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9433 12:26:49.509416 Loading segment from ROM address 0x4010001c
9434 12:26:49.509494 Entry Point 0x54601000
9435 12:26:49.513131 Loaded segments
9436 12:26:49.516049 NOTICE: MT8192 bl31_setup
9437 12:26:49.523346 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9438 12:26:49.526569 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9439 12:26:49.530347 WARNING: region 0:
9440 12:26:49.533309 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9441 12:26:49.533384 WARNING: region 1:
9442 12:26:49.540016 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9443 12:26:49.543075 WARNING: region 2:
9444 12:26:49.546236 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9445 12:26:49.549651 WARNING: region 3:
9446 12:26:49.552934 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9447 12:26:49.556487 WARNING: region 4:
9448 12:26:49.562690 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9449 12:26:49.562765 WARNING: region 5:
9450 12:26:49.566454 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 12:26:49.569692 WARNING: region 6:
9452 12:26:49.572878 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9453 12:26:49.576564 WARNING: region 7:
9454 12:26:49.579615 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9455 12:26:49.585779 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9456 12:26:49.589531 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9457 12:26:49.595763 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9458 12:26:49.598974 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9459 12:26:49.602756 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9460 12:26:49.609217 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9461 12:26:49.612706 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9462 12:26:49.615592 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9463 12:26:49.622207 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9464 12:26:49.625491 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9465 12:26:49.632099 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9466 12:26:49.635389 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9467 12:26:49.638976 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9468 12:26:49.645848 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9469 12:26:49.648959 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9470 12:26:49.651854 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9471 12:26:49.658711 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9472 12:26:49.661818 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9473 12:26:49.669253 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9474 12:26:49.672369 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9475 12:26:49.675305 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9476 12:26:49.682294 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9477 12:26:49.685372 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9478 12:26:49.692044 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9479 12:26:49.695113 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9480 12:26:49.698996 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9481 12:26:49.705110 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9482 12:26:49.708655 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9483 12:26:49.714888 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9484 12:26:49.718538 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9485 12:26:49.721958 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9486 12:26:49.728780 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9487 12:26:49.731766 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9488 12:26:49.734792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9489 12:26:49.741644 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9490 12:26:49.744908 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9491 12:26:49.748438 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9492 12:26:49.751663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9493 12:26:49.755225 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9494 12:26:49.761753 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9495 12:26:49.764944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9496 12:26:49.768810 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9497 12:26:49.771717 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9498 12:26:49.778567 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9499 12:26:49.781518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9500 12:26:49.785177 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9501 12:26:49.791999 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9502 12:26:49.795109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9503 12:26:49.798147 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9504 12:26:49.805033 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9505 12:26:49.807976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9506 12:26:49.814867 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9507 12:26:49.818509 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9508 12:26:49.821593 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9509 12:26:49.828336 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9510 12:26:49.831222 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9511 12:26:49.838272 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9512 12:26:49.841476 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9513 12:26:49.847607 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9514 12:26:49.851380 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9515 12:26:49.858293 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9516 12:26:49.861198 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9517 12:26:49.864232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9518 12:26:49.870905 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9519 12:26:49.874600 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9520 12:26:49.881471 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9521 12:26:49.884519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9522 12:26:49.891242 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9523 12:26:49.894356 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9524 12:26:49.897545 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9525 12:26:49.904342 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9526 12:26:49.907411 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9527 12:26:49.914410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9528 12:26:49.917324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9529 12:26:49.924222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9530 12:26:49.927619 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9531 12:26:49.934239 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9532 12:26:49.937231 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9533 12:26:49.940324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9534 12:26:49.946970 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9535 12:26:49.950769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9536 12:26:49.957422 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9537 12:26:49.960430 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9538 12:26:49.967277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9539 12:26:49.970490 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9540 12:26:49.977305 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9541 12:26:49.980419 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9542 12:26:49.984014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9543 12:26:49.990317 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9544 12:26:49.993719 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9545 12:26:49.999910 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9546 12:26:50.003658 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9547 12:26:50.010252 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9548 12:26:50.013598 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9549 12:26:50.019871 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9550 12:26:50.023462 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9551 12:26:50.027107 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9552 12:26:50.030222 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9553 12:26:50.036554 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9554 12:26:50.040408 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9555 12:26:50.043513 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9556 12:26:50.049923 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9557 12:26:50.053057 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9558 12:26:50.059955 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9559 12:26:50.062957 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9560 12:26:50.066228 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9561 12:26:50.072999 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9562 12:26:50.076095 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9563 12:26:50.082981 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9564 12:26:50.086055 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9565 12:26:50.089218 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9566 12:26:50.095743 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9567 12:26:50.099502 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9568 12:26:50.105902 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9569 12:26:50.109397 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9570 12:26:50.112525 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9571 12:26:50.119571 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9572 12:26:50.122640 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9573 12:26:50.125825 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9574 12:26:50.132739 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9575 12:26:50.135715 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9576 12:26:50.139074 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9577 12:26:50.142223 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9578 12:26:50.148914 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9579 12:26:50.152254 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9580 12:26:50.155799 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9581 12:26:50.162189 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9582 12:26:50.165788 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9583 12:26:50.171975 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9584 12:26:50.175759 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9585 12:26:50.178823 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9586 12:26:50.185597 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9587 12:26:50.188648 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9588 12:26:50.192462 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9589 12:26:50.198553 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9590 12:26:50.202148 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9591 12:26:50.208449 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9592 12:26:50.212281 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9593 12:26:50.215541 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9594 12:26:50.221654 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9595 12:26:50.225540 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9596 12:26:50.231767 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9597 12:26:50.234883 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9598 12:26:50.241876 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9599 12:26:50.244835 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9600 12:26:50.248411 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9601 12:26:50.255132 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9602 12:26:50.258279 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9603 12:26:50.261922 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9604 12:26:50.268126 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9605 12:26:50.271877 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9606 12:26:50.278074 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9607 12:26:50.281147 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9608 12:26:50.284572 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9609 12:26:50.291544 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9610 12:26:50.294544 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9611 12:26:50.301301 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9612 12:26:50.304993 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9613 12:26:50.308214 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9614 12:26:50.314250 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9615 12:26:50.317962 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9616 12:26:50.324100 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9617 12:26:50.327849 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9618 12:26:50.331074 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9619 12:26:50.337225 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9620 12:26:50.340839 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9621 12:26:50.347003 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9622 12:26:50.350569 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9623 12:26:50.353707 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9624 12:26:50.360383 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9625 12:26:50.363641 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9626 12:26:50.369995 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9627 12:26:50.373513 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9628 12:26:50.376725 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9629 12:26:50.383567 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9630 12:26:50.386447 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9631 12:26:50.393318 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9632 12:26:50.396360 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9633 12:26:50.403080 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9634 12:26:50.406206 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9635 12:26:50.410061 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9636 12:26:50.415993 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9637 12:26:50.419942 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9638 12:26:50.426113 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9639 12:26:50.429301 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9640 12:26:50.432875 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9641 12:26:50.439095 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9642 12:26:50.442286 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9643 12:26:50.448924 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9644 12:26:50.452611 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9645 12:26:50.455528 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9646 12:26:50.462163 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9647 12:26:50.465177 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9648 12:26:50.472334 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9649 12:26:50.475562 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9650 12:26:50.481790 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9651 12:26:50.485635 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9652 12:26:50.491562 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9653 12:26:50.495233 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9654 12:26:50.498445 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9655 12:26:50.505087 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9656 12:26:50.508202 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9657 12:26:50.514576 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9658 12:26:50.518043 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9659 12:26:50.524933 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9660 12:26:50.527973 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9661 12:26:50.531315 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9662 12:26:50.538168 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9663 12:26:50.541309 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9664 12:26:50.548198 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9665 12:26:50.551165 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9666 12:26:50.557299 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9667 12:26:50.560967 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9668 12:26:50.563931 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9669 12:26:50.570412 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9670 12:26:50.574152 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9671 12:26:50.580713 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9672 12:26:50.583748 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9673 12:26:50.587153 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9674 12:26:50.594081 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9675 12:26:50.597446 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9676 12:26:50.604083 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9677 12:26:50.607186 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9678 12:26:50.613873 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9679 12:26:50.616915 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9680 12:26:50.620680 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9681 12:26:50.626966 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9682 12:26:50.630038 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9683 12:26:50.636908 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9684 12:26:50.639967 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9685 12:26:50.643637 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9686 12:26:50.646727 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9687 12:26:50.653551 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9688 12:26:50.656515 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9689 12:26:50.659643 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9690 12:26:50.666298 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9691 12:26:50.669882 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9692 12:26:50.672929 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9693 12:26:50.679498 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9694 12:26:50.683177 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9695 12:26:50.686211 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9696 12:26:50.693100 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9697 12:26:50.696266 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9698 12:26:50.702773 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9699 12:26:50.706438 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9700 12:26:50.709478 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9701 12:26:50.716214 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9702 12:26:50.719478 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9703 12:26:50.722521 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9704 12:26:50.729125 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9705 12:26:50.732461 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9706 12:26:50.739174 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9707 12:26:50.742256 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9708 12:26:50.746005 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9709 12:26:50.752194 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9710 12:26:50.755973 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9711 12:26:50.759158 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9712 12:26:50.765782 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9713 12:26:50.768859 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9714 12:26:50.775287 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9715 12:26:50.779001 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9716 12:26:50.782038 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9717 12:26:50.788438 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9718 12:26:50.791787 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9719 12:26:50.795371 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9720 12:26:50.802069 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9721 12:26:50.804997 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9722 12:26:50.811576 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9723 12:26:50.815082 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9724 12:26:50.818140 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9725 12:26:50.821725 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9726 12:26:50.827780 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9727 12:26:50.831597 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9728 12:26:50.834735 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9729 12:26:50.837637 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9730 12:26:50.844728 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9731 12:26:50.847788 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9732 12:26:50.850862 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9733 12:26:50.854599 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9734 12:26:50.860866 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9735 12:26:50.863942 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9736 12:26:50.867452 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9737 12:26:50.874130 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9738 12:26:50.877631 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9739 12:26:50.883668 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9740 12:26:50.887160 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9741 12:26:50.894030 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9742 12:26:50.897073 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9743 12:26:50.899959 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9744 12:26:50.906663 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9745 12:26:50.910392 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9746 12:26:50.916620 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9747 12:26:50.919628 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9748 12:26:50.923338 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9749 12:26:50.929872 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9750 12:26:50.933022 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9751 12:26:50.939632 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9752 12:26:50.942711 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9753 12:26:50.949579 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9754 12:26:50.952658 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9755 12:26:50.955705 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9756 12:26:50.962472 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9757 12:26:50.966173 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9758 12:26:50.972500 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9759 12:26:50.975713 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9760 12:26:50.979246 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9761 12:26:50.985938 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9762 12:26:50.989063 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9763 12:26:50.995731 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9764 12:26:50.998804 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9765 12:26:51.005542 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9766 12:26:51.008580 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9767 12:26:51.015476 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9768 12:26:51.018973 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9769 12:26:51.021688 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9770 12:26:51.028338 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9771 12:26:51.031993 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9772 12:26:51.038215 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9773 12:26:51.042004 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9774 12:26:51.044968 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9775 12:26:51.051756 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9776 12:26:51.054716 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9777 12:26:51.061687 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9778 12:26:51.064646 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9779 12:26:51.070972 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9780 12:26:51.074198 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9781 12:26:51.077855 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9782 12:26:51.084306 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9783 12:26:51.087776 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9784 12:26:51.094063 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9785 12:26:51.097703 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9786 12:26:51.100810 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9787 12:26:51.107521 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9788 12:26:51.110610 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9789 12:26:51.116928 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9790 12:26:51.120462 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9791 12:26:51.126910 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9792 12:26:51.130438 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9793 12:26:51.133630 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9794 12:26:51.140413 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9795 12:26:51.143555 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9796 12:26:51.150524 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9797 12:26:51.153415 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9798 12:26:51.160385 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9799 12:26:51.163280 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9800 12:26:51.166389 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9801 12:26:51.173139 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9802 12:26:51.176233 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9803 12:26:51.182797 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9804 12:26:51.186047 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9805 12:26:51.193066 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9806 12:26:51.196179 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9807 12:26:51.199205 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9808 12:26:51.205937 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9809 12:26:51.209023 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9810 12:26:51.215804 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9811 12:26:51.219420 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9812 12:26:51.225514 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9813 12:26:51.229065 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9814 12:26:51.232632 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9815 12:26:51.239200 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9816 12:26:51.242327 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9817 12:26:51.248624 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9818 12:26:51.252295 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9819 12:26:51.259165 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9820 12:26:51.262223 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9821 12:26:51.268324 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9822 12:26:51.271502 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9823 12:26:51.278169 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9824 12:26:51.281771 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9825 12:26:51.284677 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9826 12:26:51.291333 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9827 12:26:51.294853 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9828 12:26:51.301318 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9829 12:26:51.304510 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9830 12:26:51.311123 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9831 12:26:51.314385 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9832 12:26:51.318049 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9833 12:26:51.324389 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9834 12:26:51.327252 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9835 12:26:51.334409 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9836 12:26:51.337280 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9837 12:26:51.343998 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9838 12:26:51.347070 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9839 12:26:51.353956 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9840 12:26:51.357063 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9841 12:26:51.363711 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9842 12:26:51.367305 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9843 12:26:51.370376 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9844 12:26:51.376639 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9845 12:26:51.380396 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9846 12:26:51.386567 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9847 12:26:51.390233 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9848 12:26:51.396417 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9849 12:26:51.399850 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9850 12:26:51.406331 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9851 12:26:51.409385 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9852 12:26:51.416208 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9853 12:26:51.419725 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9854 12:26:51.422861 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9855 12:26:51.429241 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9856 12:26:51.432760 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9857 12:26:51.439384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9858 12:26:51.442876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9859 12:26:51.449432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9860 12:26:51.452676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9861 12:26:51.458831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9862 12:26:51.462477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9863 12:26:51.468626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9864 12:26:51.472463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9865 12:26:51.478557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9866 12:26:51.482338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9867 12:26:51.488404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9868 12:26:51.492255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9869 12:26:51.495185 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9870 12:26:51.501743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9871 12:26:51.505285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9872 12:26:51.511749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9873 12:26:51.514876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9874 12:26:51.521623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9875 12:26:51.524673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9876 12:26:51.531534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9877 12:26:51.534693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9878 12:26:51.541261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9879 12:26:51.547419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9880 12:26:51.550762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9881 12:26:51.557650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9882 12:26:51.560640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9883 12:26:51.567600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9884 12:26:51.570573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9885 12:26:51.577395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9886 12:26:51.580349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9887 12:26:51.587116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9888 12:26:51.590220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9889 12:26:51.594054 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9890 12:26:51.597033 INFO: [APUAPC] vio 0
9891 12:26:51.603747 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9892 12:26:51.606725 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9893 12:26:51.610191 INFO: [APUAPC] D0_APC_0: 0x400510
9894 12:26:51.613575 INFO: [APUAPC] D0_APC_1: 0x0
9895 12:26:51.616777 INFO: [APUAPC] D0_APC_2: 0x1540
9896 12:26:51.619915 INFO: [APUAPC] D0_APC_3: 0x0
9897 12:26:51.623501 INFO: [APUAPC] D1_APC_0: 0xffffffff
9898 12:26:51.626684 INFO: [APUAPC] D1_APC_1: 0xffffffff
9899 12:26:51.630352 INFO: [APUAPC] D1_APC_2: 0x3fffff
9900 12:26:51.633398 INFO: [APUAPC] D1_APC_3: 0x0
9901 12:26:51.636554 INFO: [APUAPC] D2_APC_0: 0xffffffff
9902 12:26:51.640067 INFO: [APUAPC] D2_APC_1: 0xffffffff
9903 12:26:51.643092 INFO: [APUAPC] D2_APC_2: 0x3fffff
9904 12:26:51.646670 INFO: [APUAPC] D2_APC_3: 0x0
9905 12:26:51.649753 INFO: [APUAPC] D3_APC_0: 0xffffffff
9906 12:26:51.653262 INFO: [APUAPC] D3_APC_1: 0xffffffff
9907 12:26:51.656253 INFO: [APUAPC] D3_APC_2: 0x3fffff
9908 12:26:51.656335 INFO: [APUAPC] D3_APC_3: 0x0
9909 12:26:51.663022 INFO: [APUAPC] D4_APC_0: 0xffffffff
9910 12:26:51.665950 INFO: [APUAPC] D4_APC_1: 0xffffffff
9911 12:26:51.669199 INFO: [APUAPC] D4_APC_2: 0x3fffff
9912 12:26:51.669302 INFO: [APUAPC] D4_APC_3: 0x0
9913 12:26:51.675915 INFO: [APUAPC] D5_APC_0: 0xffffffff
9914 12:26:51.679112 INFO: [APUAPC] D5_APC_1: 0xffffffff
9915 12:26:51.682629 INFO: [APUAPC] D5_APC_2: 0x3fffff
9916 12:26:51.682743 INFO: [APUAPC] D5_APC_3: 0x0
9917 12:26:51.685868 INFO: [APUAPC] D6_APC_0: 0xffffffff
9918 12:26:51.692580 INFO: [APUAPC] D6_APC_1: 0xffffffff
9919 12:26:51.695834 INFO: [APUAPC] D6_APC_2: 0x3fffff
9920 12:26:51.695941 INFO: [APUAPC] D6_APC_3: 0x0
9921 12:26:51.698984 INFO: [APUAPC] D7_APC_0: 0xffffffff
9922 12:26:51.705729 INFO: [APUAPC] D7_APC_1: 0xffffffff
9923 12:26:51.705835 INFO: [APUAPC] D7_APC_2: 0x3fffff
9924 12:26:51.708890 INFO: [APUAPC] D7_APC_3: 0x0
9925 12:26:51.712368 INFO: [APUAPC] D8_APC_0: 0xffffffff
9926 12:26:51.715442 INFO: [APUAPC] D8_APC_1: 0xffffffff
9927 12:26:51.718866 INFO: [APUAPC] D8_APC_2: 0x3fffff
9928 12:26:51.721923 INFO: [APUAPC] D8_APC_3: 0x0
9929 12:26:51.725547 INFO: [APUAPC] D9_APC_0: 0xffffffff
9930 12:26:51.728603 INFO: [APUAPC] D9_APC_1: 0xffffffff
9931 12:26:51.731633 INFO: [APUAPC] D9_APC_2: 0x3fffff
9932 12:26:51.735495 INFO: [APUAPC] D9_APC_3: 0x0
9933 12:26:51.738534 INFO: [APUAPC] D10_APC_0: 0xffffffff
9934 12:26:51.741622 INFO: [APUAPC] D10_APC_1: 0xffffffff
9935 12:26:51.744718 INFO: [APUAPC] D10_APC_2: 0x3fffff
9936 12:26:51.748322 INFO: [APUAPC] D10_APC_3: 0x0
9937 12:26:51.751229 INFO: [APUAPC] D11_APC_0: 0xffffffff
9938 12:26:51.758056 INFO: [APUAPC] D11_APC_1: 0xffffffff
9939 12:26:51.761073 INFO: [APUAPC] D11_APC_2: 0x3fffff
9940 12:26:51.761152 INFO: [APUAPC] D11_APC_3: 0x0
9941 12:26:51.768038 INFO: [APUAPC] D12_APC_0: 0xffffffff
9942 12:26:51.771194 INFO: [APUAPC] D12_APC_1: 0xffffffff
9943 12:26:51.774241 INFO: [APUAPC] D12_APC_2: 0x3fffff
9944 12:26:51.778010 INFO: [APUAPC] D12_APC_3: 0x0
9945 12:26:51.781139 INFO: [APUAPC] D13_APC_0: 0xffffffff
9946 12:26:51.784303 INFO: [APUAPC] D13_APC_1: 0xffffffff
9947 12:26:51.787352 INFO: [APUAPC] D13_APC_2: 0x3fffff
9948 12:26:51.790961 INFO: [APUAPC] D13_APC_3: 0x0
9949 12:26:51.794374 INFO: [APUAPC] D14_APC_0: 0xffffffff
9950 12:26:51.797294 INFO: [APUAPC] D14_APC_1: 0xffffffff
9951 12:26:51.800926 INFO: [APUAPC] D14_APC_2: 0x3fffff
9952 12:26:51.804035 INFO: [APUAPC] D14_APC_3: 0x0
9953 12:26:51.807018 INFO: [APUAPC] D15_APC_0: 0xffffffff
9954 12:26:51.810498 INFO: [APUAPC] D15_APC_1: 0xffffffff
9955 12:26:51.814176 INFO: [APUAPC] D15_APC_2: 0x3fffff
9956 12:26:51.817076 INFO: [APUAPC] D15_APC_3: 0x0
9957 12:26:51.820052 INFO: [APUAPC] APC_CON: 0x4
9958 12:26:51.820160 INFO: [NOCDAPC] D0_APC_0: 0x0
9959 12:26:51.823628 INFO: [NOCDAPC] D0_APC_1: 0x0
9960 12:26:51.826676 INFO: [NOCDAPC] D1_APC_0: 0x0
9961 12:26:51.830172 INFO: [NOCDAPC] D1_APC_1: 0xfff
9962 12:26:51.833222 INFO: [NOCDAPC] D2_APC_0: 0x0
9963 12:26:51.836884 INFO: [NOCDAPC] D2_APC_1: 0xfff
9964 12:26:51.840077 INFO: [NOCDAPC] D3_APC_0: 0x0
9965 12:26:51.843214 INFO: [NOCDAPC] D3_APC_1: 0xfff
9966 12:26:51.846333 INFO: [NOCDAPC] D4_APC_0: 0x0
9967 12:26:51.849907 INFO: [NOCDAPC] D4_APC_1: 0xfff
9968 12:26:51.853025 INFO: [NOCDAPC] D5_APC_0: 0x0
9969 12:26:51.853133 INFO: [NOCDAPC] D5_APC_1: 0xfff
9970 12:26:51.856600 INFO: [NOCDAPC] D6_APC_0: 0x0
9971 12:26:51.859614 INFO: [NOCDAPC] D6_APC_1: 0xfff
9972 12:26:51.862950 INFO: [NOCDAPC] D7_APC_0: 0x0
9973 12:26:51.866459 INFO: [NOCDAPC] D7_APC_1: 0xfff
9974 12:26:51.869455 INFO: [NOCDAPC] D8_APC_0: 0x0
9975 12:26:51.873392 INFO: [NOCDAPC] D8_APC_1: 0xfff
9976 12:26:51.876294 INFO: [NOCDAPC] D9_APC_0: 0x0
9977 12:26:51.879537 INFO: [NOCDAPC] D9_APC_1: 0xfff
9978 12:26:51.882646 INFO: [NOCDAPC] D10_APC_0: 0x0
9979 12:26:51.886413 INFO: [NOCDAPC] D10_APC_1: 0xfff
9980 12:26:51.889520 INFO: [NOCDAPC] D11_APC_0: 0x0
9981 12:26:51.892497 INFO: [NOCDAPC] D11_APC_1: 0xfff
9982 12:26:51.896242 INFO: [NOCDAPC] D12_APC_0: 0x0
9983 12:26:51.896331 INFO: [NOCDAPC] D12_APC_1: 0xfff
9984 12:26:51.899393 INFO: [NOCDAPC] D13_APC_0: 0x0
9985 12:26:51.902424 INFO: [NOCDAPC] D13_APC_1: 0xfff
9986 12:26:51.906095 INFO: [NOCDAPC] D14_APC_0: 0x0
9987 12:26:51.909162 INFO: [NOCDAPC] D14_APC_1: 0xfff
9988 12:26:51.912241 INFO: [NOCDAPC] D15_APC_0: 0x0
9989 12:26:51.915880 INFO: [NOCDAPC] D15_APC_1: 0xfff
9990 12:26:51.919327 INFO: [NOCDAPC] APC_CON: 0x4
9991 12:26:51.922550 INFO: [APUAPC] set_apusys_apc done
9992 12:26:51.925430 INFO: [DEVAPC] devapc_init done
9993 12:26:51.929057 INFO: GICv3 without legacy support detected.
9994 12:26:51.932073 INFO: ARM GICv3 driver initialized in EL3
9995 12:26:51.938675 INFO: Maximum SPI INTID supported: 639
9996 12:26:51.942301 INFO: BL31: Initializing runtime services
9997 12:26:51.948420 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9998 12:26:51.948512 INFO: SPM: enable CPC mode
9999 12:26:51.955377 INFO: mcdi ready for mcusys-off-idle and system suspend
10000 12:26:51.958249 INFO: BL31: Preparing for EL3 exit to normal world
10001 12:26:51.964708 INFO: Entry point address = 0x80000000
10002 12:26:51.964817 INFO: SPSR = 0x8
10003 12:26:51.971175
10004 12:26:51.971270
10005 12:26:51.971350
10006 12:26:51.974272 Starting depthcharge on Spherion...
10007 12:26:51.974369
10008 12:26:51.974433 Wipe memory regions:
10009 12:26:51.974505
10010 12:26:51.975113 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10011 12:26:51.975225 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10012 12:26:51.975314 Setting prompt string to ['asurada:']
10013 12:26:51.975405 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10014 12:26:51.977852 [0x00000040000000, 0x00000054600000)
10015 12:26:52.099922
10016 12:26:52.100134 [0x00000054660000, 0x00000080000000)
10017 12:26:52.360883
10018 12:26:52.361070 [0x000000821a7280, 0x000000ffe64000)
10019 12:26:53.105866
10020 12:26:53.106009 [0x00000100000000, 0x00000240000000)
10021 12:26:54.995583
10022 12:26:54.999140 Initializing XHCI USB controller at 0x11200000.
10023 12:26:56.038078
10024 12:26:56.041124 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10025 12:26:56.041214
10026 12:26:56.041283
10027 12:26:56.041346
10028 12:26:56.041627 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10030 12:26:56.142000 asurada: tftpboot 192.168.201.1 10605776/tftp-deploy-yypd6nms/kernel/image.itb 10605776/tftp-deploy-yypd6nms/kernel/cmdline
10031 12:26:56.142167 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10032 12:26:56.142317 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10033 12:26:56.146358 tftpboot 192.168.201.1 10605776/tftp-deploy-yypd6nms/kernel/image.itp-deploy-yypd6nms/kernel/cmdline
10034 12:26:56.146446
10035 12:26:56.146513 Waiting for link
10036 12:26:56.306717
10037 12:26:56.306876 R8152: Initializing
10038 12:26:56.306978
10039 12:26:56.309847 Version 6 (ocp_data = 5c30)
10040 12:26:56.309952
10041 12:26:56.312857 R8152: Done initializing
10042 12:26:56.312930
10043 12:26:56.312993 Adding net device
10044 12:26:58.247276
10045 12:26:58.247425 done.
10046 12:26:58.247525
10047 12:26:58.247620 MAC: 00:24:32:30:7c:7b
10048 12:26:58.247715
10049 12:26:58.250298 Sending DHCP discover... done.
10050 12:26:58.250399
10051 12:26:58.254027 Waiting for reply... done.
10052 12:26:58.254101
10053 12:26:58.257108 Sending DHCP request... done.
10054 12:26:58.257192
10055 12:26:58.261456 Waiting for reply... done.
10056 12:26:58.261540
10057 12:26:58.261607 My ip is 192.168.201.14
10058 12:26:58.261669
10059 12:26:58.265241 The DHCP server ip is 192.168.201.1
10060 12:26:58.265325
10061 12:26:58.271180 TFTP server IP predefined by user: 192.168.201.1
10062 12:26:58.271265
10063 12:26:58.277891 Bootfile predefined by user: 10605776/tftp-deploy-yypd6nms/kernel/image.itb
10064 12:26:58.277976
10065 12:26:58.281622 Sending tftp read request... done.
10066 12:26:58.281706
10067 12:26:58.285209 Waiting for the transfer...
10068 12:26:58.285300
10069 12:26:58.808278 00000000 ################################################################
10070 12:26:58.808432
10071 12:26:59.326534 00080000 ################################################################
10072 12:26:59.326676
10073 12:26:59.849941 00100000 ################################################################
10074 12:26:59.850078
10075 12:27:00.367513 00180000 ################################################################
10076 12:27:00.367654
10077 12:27:00.884723 00200000 ################################################################
10078 12:27:00.884856
10079 12:27:01.406567 00280000 ################################################################
10080 12:27:01.406704
10081 12:27:01.925639 00300000 ################################################################
10082 12:27:01.925806
10083 12:27:02.446943 00380000 ################################################################
10084 12:27:02.447109
10085 12:27:02.975937 00400000 ################################################################
10086 12:27:02.976140
10087 12:27:03.511177 00480000 ################################################################
10088 12:27:03.511325
10089 12:27:04.044152 00500000 ################################################################
10090 12:27:04.044305
10091 12:27:04.570499 00580000 ################################################################
10092 12:27:04.570651
10093 12:27:05.101189 00600000 ################################################################
10094 12:27:05.101347
10095 12:27:05.628465 00680000 ################################################################
10096 12:27:05.628618
10097 12:27:06.164422 00700000 ################################################################
10098 12:27:06.164557
10099 12:27:06.696443 00780000 ################################################################
10100 12:27:06.696593
10101 12:27:07.226738 00800000 ################################################################
10102 12:27:07.226916
10103 12:27:07.798899 00880000 ################################################################
10104 12:27:07.799048
10105 12:27:08.373641 00900000 ################################################################
10106 12:27:08.373789
10107 12:27:08.943488 00980000 ################################################################
10108 12:27:08.943641
10109 12:27:09.471297 00a00000 ################################################################
10110 12:27:09.471439
10111 12:27:10.013671 00a80000 ################################################################
10112 12:27:10.013865
10113 12:27:10.534038 00b00000 ################################################################
10114 12:27:10.534214
10115 12:27:11.070254 00b80000 ################################################################
10116 12:27:11.070432
10117 12:27:11.602290 00c00000 ################################################################
10118 12:27:11.602447
10119 12:27:12.125185 00c80000 ################################################################
10120 12:27:12.125337
10121 12:27:12.648533 00d00000 ################################################################
10122 12:27:12.648710
10123 12:27:13.166743 00d80000 ################################################################
10124 12:27:13.166903
10125 12:27:13.683968 00e00000 ################################################################
10126 12:27:13.684170
10127 12:27:14.210823 00e80000 ################################################################
10128 12:27:14.210968
10129 12:27:14.737211 00f00000 ################################################################
10130 12:27:14.737361
10131 12:27:15.264880 00f80000 ################################################################
10132 12:27:15.265053
10133 12:27:15.791461 01000000 ################################################################
10134 12:27:15.791613
10135 12:27:16.323039 01080000 ################################################################
10136 12:27:16.323207
10137 12:27:16.867205 01100000 ################################################################
10138 12:27:16.867372
10139 12:27:17.401287 01180000 ################################################################
10140 12:27:17.401458
10141 12:27:17.937196 01200000 ################################################################
10142 12:27:17.937366
10143 12:27:18.488788 01280000 ################################################################
10144 12:27:18.488949
10145 12:27:19.034945 01300000 ################################################################
10146 12:27:19.035149
10147 12:27:19.571034 01380000 ################################################################
10148 12:27:19.571232
10149 12:27:20.119651 01400000 ################################################################
10150 12:27:20.119860
10151 12:27:20.651827 01480000 ################################################################
10152 12:27:20.651989
10153 12:27:21.189268 01500000 ################################################################
10154 12:27:21.189457
10155 12:27:21.723979 01580000 ################################################################
10156 12:27:21.724163
10157 12:27:22.259861 01600000 ################################################################
10158 12:27:22.260106
10159 12:27:22.791280 01680000 ################################################################
10160 12:27:22.791468
10161 12:27:23.332205 01700000 ################################################################
10162 12:27:23.332389
10163 12:27:23.866739 01780000 ################################################################
10164 12:27:23.866926
10165 12:27:24.405727 01800000 ################################################################
10166 12:27:24.405919
10167 12:27:24.939302 01880000 ################################################################
10168 12:27:24.939482
10169 12:27:25.462130 01900000 ################################################################
10170 12:27:25.462274
10171 12:27:25.993312 01980000 ################################################################
10172 12:27:25.993500
10173 12:27:26.542216 01a00000 ################################################################
10174 12:27:26.542409
10175 12:27:27.077523 01a80000 ################################################################
10176 12:27:27.077711
10177 12:27:27.614203 01b00000 ################################################################
10178 12:27:27.614372
10179 12:27:28.181004 01b80000 ################################################################
10180 12:27:28.181202
10181 12:27:28.722886 01c00000 ################################################################
10182 12:27:28.723066
10183 12:27:29.263322 01c80000 ################################################################
10184 12:27:29.263520
10185 12:27:29.816523 01d00000 ################################################################
10186 12:27:29.816698
10187 12:27:30.354724 01d80000 ################################################################
10188 12:27:30.354873
10189 12:27:30.903912 01e00000 ################################################################
10190 12:27:30.904077
10191 12:27:31.485156 01e80000 ################################################################
10192 12:27:31.485312
10193 12:27:32.037434 01f00000 ################################################################
10194 12:27:32.037602
10195 12:27:32.574385 01f80000 ################################################################
10196 12:27:32.574540
10197 12:27:33.128028 02000000 ################################################################
10198 12:27:33.128207
10199 12:27:33.660383 02080000 ################################################################
10200 12:27:33.660551
10201 12:27:34.194980 02100000 ################################################################
10202 12:27:34.195149
10203 12:27:34.730775 02180000 ################################################################
10204 12:27:34.730984
10205 12:27:35.267401 02200000 ################################################################
10206 12:27:35.267561
10207 12:27:35.801579 02280000 ################################################################
10208 12:27:35.801797
10209 12:27:36.338634 02300000 ################################################################
10210 12:27:36.338829
10211 12:27:36.878462 02380000 ################################################################
10212 12:27:36.878619
10213 12:27:37.429108 02400000 ################################################################
10214 12:27:37.429281
10215 12:27:37.990564 02480000 ################################################################
10216 12:27:37.990754
10217 12:27:38.534746 02500000 ################################################################
10218 12:27:38.534938
10219 12:27:39.072460 02580000 ################################################################
10220 12:27:39.072631
10221 12:27:39.628423 02600000 ################################################################
10222 12:27:39.628619
10223 12:27:40.186692 02680000 ################################################################
10224 12:27:40.186865
10225 12:27:40.726194 02700000 ################################################################
10226 12:27:40.726374
10227 12:27:41.283920 02780000 ################################################################
10228 12:27:41.284105
10229 12:27:41.828638 02800000 ################################################################
10230 12:27:41.828794
10231 12:27:42.365865 02880000 ################################################################
10232 12:27:42.366109
10233 12:27:42.929164 02900000 ################################################################
10234 12:27:42.929351
10235 12:27:43.499494 02980000 ################################################################
10236 12:27:43.499649
10237 12:27:44.030352 02a00000 ################################################################
10238 12:27:44.030535
10239 12:27:44.564905 02a80000 ################################################################
10240 12:27:44.565090
10241 12:27:45.100811 02b00000 ################################################################
10242 12:27:45.100966
10243 12:27:45.630044 02b80000 ################################################################
10244 12:27:45.630178
10245 12:27:46.166962 02c00000 ################################################################
10246 12:27:46.167104
10247 12:27:46.734047 02c80000 ################################################################
10248 12:27:46.734213
10249 12:27:47.326627 02d00000 ################################################################
10250 12:27:47.326765
10251 12:27:47.894757 02d80000 ################################################################
10252 12:27:47.894891
10253 12:27:48.533044 02e00000 ################################################################
10254 12:27:48.533202
10255 12:27:49.008058 02e80000 ################################################################
10256 12:27:49.008195
10257 12:27:49.587071 02f00000 ################################################################
10258 12:27:49.587501
10259 12:27:50.169399 02f80000 ################################################################
10260 12:27:50.169542
10261 12:27:50.757215 03000000 ################################################################
10262 12:27:50.757384
10263 12:27:51.348212 03080000 ################################################################
10264 12:27:51.348377
10265 12:27:51.949903 03100000 ################################################################
10266 12:27:51.950101
10267 12:27:52.544719 03180000 ################################################################
10268 12:27:52.544863
10269 12:27:53.138362 03200000 ################################################################
10270 12:27:53.138561
10271 12:27:53.719514 03280000 ################################################################
10272 12:27:53.719700
10273 12:27:54.279310 03300000 ################################################################
10274 12:27:54.279500
10275 12:27:54.824852 03380000 ################################################################
10276 12:27:54.825018
10277 12:27:55.371274 03400000 ################################################################
10278 12:27:55.371436
10279 12:27:55.935352 03480000 ################################################################
10280 12:27:55.935486
10281 12:27:56.498756 03500000 ################################################################
10282 12:27:56.498930
10283 12:27:57.068355 03580000 ################################################################
10284 12:27:57.068525
10285 12:27:57.626001 03600000 ################################################################
10286 12:27:57.626156
10287 12:27:58.188353 03680000 ################################################################
10288 12:27:58.188516
10289 12:27:58.734573 03700000 ################################################################
10290 12:27:58.734744
10291 12:27:59.264054 03780000 ################################################################
10292 12:27:59.264190
10293 12:27:59.795276 03800000 ################################################################
10294 12:27:59.795448
10295 12:28:00.325515 03880000 ################################################################
10296 12:28:00.325689
10297 12:28:00.848869 03900000 ################################################################
10298 12:28:00.849073
10299 12:28:01.387117 03980000 ################################################################
10300 12:28:01.387279
10301 12:28:01.937073 03a00000 ################################################################
10302 12:28:01.937228
10303 12:28:02.469915 03a80000 ################################################################
10304 12:28:02.470067
10305 12:28:03.002607 03b00000 ################################################################
10306 12:28:03.002783
10307 12:28:03.534358 03b80000 ################################################################
10308 12:28:03.534544
10309 12:28:04.071350 03c00000 ################################################################
10310 12:28:04.071533
10311 12:28:04.612989 03c80000 ################################################################
10312 12:28:04.613155
10313 12:28:05.156434 03d00000 ################################################################
10314 12:28:05.156582
10315 12:28:05.699959 03d80000 ################################################################
10316 12:28:05.700139
10317 12:28:06.253045 03e00000 ################################################################
10318 12:28:06.253230
10319 12:28:06.779136 03e80000 ################################################################
10320 12:28:06.779309
10321 12:28:07.311427 03f00000 ################################################################
10322 12:28:07.311615
10323 12:28:07.845507 03f80000 ################################################################
10324 12:28:07.845675
10325 12:28:08.436720 04000000 ################################################################
10326 12:28:08.436874
10327 12:28:09.033820 04080000 ################################################################
10328 12:28:09.033960
10329 12:28:09.581257 04100000 ################################################################
10330 12:28:09.581427
10331 12:28:10.133455 04180000 ################################################################
10332 12:28:10.134087
10333 12:28:10.718701 04200000 ################################################################
10334 12:28:10.718846
10335 12:28:11.312005 04280000 ################################################################
10336 12:28:11.312585
10337 12:28:11.881073 04300000 ################################################################
10338 12:28:11.881233
10339 12:28:12.401302 04380000 ################################################################
10340 12:28:12.401483
10341 12:28:12.969832 04400000 ################################################################
10342 12:28:12.970005
10343 12:28:13.508805 04480000 ################################################################
10344 12:28:13.508955
10345 12:28:14.070581 04500000 ################################################################
10346 12:28:14.071173
10347 12:28:14.705634 04580000 ################################################################
10348 12:28:14.706161
10349 12:28:15.306643 04600000 ################################################################
10350 12:28:15.307161
10351 12:28:15.881122 04680000 ################################################################
10352 12:28:15.881650
10353 12:28:16.495567 04700000 ################################################################
10354 12:28:16.496166
10355 12:28:17.058244 04780000 ################################################################
10356 12:28:17.058387
10357 12:28:17.605080 04800000 ################################################################
10358 12:28:17.605230
10359 12:28:18.147178 04880000 ################################################################
10360 12:28:18.147692
10361 12:28:18.733026 04900000 ################################################################
10362 12:28:18.733171
10363 12:28:19.275181 04980000 ################################################################
10364 12:28:19.275334
10365 12:28:19.817082 04a00000 ################################################################
10366 12:28:19.817230
10367 12:28:20.355736 04a80000 ################################################################
10368 12:28:20.355916
10369 12:28:20.920460 04b00000 ################################################################
10370 12:28:20.920759
10371 12:28:21.475246 04b80000 ################################################################
10372 12:28:21.475403
10373 12:28:22.015101 04c00000 ################################################################
10374 12:28:22.015260
10375 12:28:22.587361 04c80000 ################################################################
10376 12:28:22.587896
10377 12:28:23.213562 04d00000 ################################################################
10378 12:28:23.214088
10379 12:28:23.794711 04d80000 ################################################################
10380 12:28:23.795378
10381 12:28:24.403858 04e00000 ################################################################
10382 12:28:24.404105
10383 12:28:24.972687 04e80000 ################################################################
10384 12:28:24.972848
10385 12:28:25.497167 04f00000 ################################################################
10386 12:28:25.497359
10387 12:28:26.030917 04f80000 ################################################################
10388 12:28:26.031110
10389 12:28:26.567551 05000000 ################################################################
10390 12:28:26.567727
10391 12:28:27.111052 05080000 ################################################################
10392 12:28:27.111233
10393 12:28:27.660613 05100000 ################################################################
10394 12:28:27.660793
10395 12:28:28.209067 05180000 ################################################################
10396 12:28:28.209232
10397 12:28:28.745234 05200000 ################################################################
10398 12:28:28.745398
10399 12:28:29.274514 05280000 ################################################################
10400 12:28:29.274695
10401 12:28:29.798466 05300000 ################################################################
10402 12:28:29.798627
10403 12:28:30.318200 05380000 ################################################################
10404 12:28:30.318380
10405 12:28:30.851947 05400000 ################################################################
10406 12:28:30.852150
10407 12:28:31.385512 05480000 ################################################################
10408 12:28:31.385723
10409 12:28:31.914243 05500000 ################################################################
10410 12:28:31.914394
10411 12:28:32.439797 05580000 ################################################################
10412 12:28:32.439950
10413 12:28:32.960679 05600000 ################################################################
10414 12:28:32.960862
10415 12:28:33.479882 05680000 ################################################################
10416 12:28:33.480073
10417 12:28:34.000905 05700000 ################################################################
10418 12:28:34.001062
10419 12:28:34.521651 05780000 ################################################################
10420 12:28:34.521848
10421 12:28:35.044674 05800000 ################################################################
10422 12:28:35.044842
10423 12:28:35.573980 05880000 ################################################################
10424 12:28:35.574162
10425 12:28:36.116278 05900000 ################################################################
10426 12:28:36.116430
10427 12:28:36.643032 05980000 ################################################################
10428 12:28:36.643207
10429 12:28:37.164682 05a00000 ################################################################
10430 12:28:37.164891
10431 12:28:37.689560 05a80000 ################################################################
10432 12:28:37.689714
10433 12:28:38.219771 05b00000 ################################################################
10434 12:28:38.219963
10435 12:28:38.742321 05b80000 ################################################################
10436 12:28:38.742499
10437 12:28:39.268253 05c00000 ################################################################
10438 12:28:39.268482
10439 12:28:39.798193 05c80000 ################################################################
10440 12:28:39.798393
10441 12:28:40.329322 05d00000 ################################################################
10442 12:28:40.329505
10443 12:28:40.850906 05d80000 ################################################################
10444 12:28:40.851053
10445 12:28:41.380481 05e00000 ################################################################
10446 12:28:41.380634
10447 12:28:41.906008 05e80000 ################################################################
10448 12:28:41.906164
10449 12:28:42.427989 05f00000 ################################################################
10450 12:28:42.428276
10451 12:28:42.966921 05f80000 ################################################################
10452 12:28:42.967189
10453 12:28:43.513978 06000000 ################################################################
10454 12:28:43.514153
10455 12:28:44.044159 06080000 ################################################################
10456 12:28:44.044313
10457 12:28:44.569330 06100000 ################################################################
10458 12:28:44.569486
10459 12:28:45.095776 06180000 ################################################################
10460 12:28:45.095931
10461 12:28:45.619521 06200000 ################################################################
10462 12:28:45.619706
10463 12:28:46.134956 06280000 ################################################################
10464 12:28:46.135144
10465 12:28:46.646755 06300000 ################################################################
10466 12:28:46.646941
10467 12:28:47.157494 06380000 ################################################################
10468 12:28:47.157636
10469 12:28:47.671280 06400000 ################################################################
10470 12:28:47.671525
10471 12:28:48.196930 06480000 ################################################################
10472 12:28:48.197081
10473 12:28:48.720431 06500000 ################################################################
10474 12:28:48.720610
10475 12:28:49.241975 06580000 ################################################################
10476 12:28:49.242130
10477 12:28:49.770863 06600000 ################################################################
10478 12:28:49.771015
10479 12:28:50.299810 06680000 ################################################################
10480 12:28:50.300001
10481 12:28:50.569017 06700000 ################################# done.
10482 12:28:50.569217
10483 12:28:50.572010 The bootfile was 108270494 bytes long.
10484 12:28:50.572136
10485 12:28:50.575712 Sending tftp read request... done.
10486 12:28:50.575848
10487 12:28:50.575953 Waiting for the transfer...
10488 12:28:50.578641
10489 12:28:50.578783 00000000 # done.
10490 12:28:50.578889
10491 12:28:50.585595 Command line loaded dynamically from TFTP file: 10605776/tftp-deploy-yypd6nms/kernel/cmdline
10492 12:28:50.585786
10493 12:28:50.598656 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10494 12:28:50.598850
10495 12:28:50.598955 Loading FIT.
10496 12:28:50.599049
10497 12:28:50.602223 Image ramdisk-1 has 98134786 bytes.
10498 12:28:50.602348
10499 12:28:50.605279 Image fdt-1 has 46924 bytes.
10500 12:28:50.605402
10501 12:28:50.608642 Image kernel-1 has 10086749 bytes.
10502 12:28:50.608767
10503 12:28:50.618157 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10504 12:28:50.618342
10505 12:28:50.634607 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10506 12:28:50.634805
10507 12:28:50.641086 Choosing best match conf-1 for compat google,spherion-rev2.
10508 12:28:50.641242
10509 12:28:50.644557 Connected to device vid:did:rid of 1ae0:0028:00
10510 12:28:50.656468
10511 12:28:50.659717 tpm_get_response: command 0x17b, return code 0x0
10512 12:28:50.659855
10513 12:28:50.663100 ec_init: CrosEC protocol v3 supported (256, 248)
10514 12:28:50.666995
10515 12:28:50.670448 tpm_cleanup: add release locality here.
10516 12:28:50.670579
10517 12:28:50.673882 Shutting down all USB controllers.
10518 12:28:50.674006
10519 12:28:50.674104 Removing current net device
10520 12:28:50.674198
10521 12:28:50.680180 Exiting depthcharge with code 4 at timestamp: 147989713
10522 12:28:50.680321
10523 12:28:50.683787 LZMA decompressing kernel-1 to 0x821a6718
10524 12:28:50.683910
10525 12:28:50.686994 LZMA decompressing kernel-1 to 0x40000000
10526 12:28:51.953899
10527 12:28:51.954056 jumping to kernel
10528 12:28:51.954870 end: 2.2.4 bootloader-commands (duration 00:02:00) [common]
10529 12:28:51.955001 start: 2.2.5 auto-login-action (timeout 00:02:25) [common]
10530 12:28:51.955111 Setting prompt string to ['Linux version [0-9]']
10531 12:28:51.955210 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10532 12:28:51.955307 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10533 12:28:52.035694
10534 12:28:52.039025 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10535 12:28:52.042103 start: 2.2.5.1 login-action (timeout 00:02:25) [common]
10536 12:28:52.042201 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10537 12:28:52.042296 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10538 12:28:52.042376 Using line separator: #'\n'#
10539 12:28:52.042440 No login prompt set.
10540 12:28:52.042505 Parsing kernel messages
10541 12:28:52.042563 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10542 12:28:52.042671 [login-action] Waiting for messages, (timeout 00:02:25)
10543 12:28:52.061980 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614976-arm64-gcc-10-defconfig-arm64-chromebook-lgg5p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023
10544 12:28:52.065047 [ 0.000000] random: crng init done
10545 12:28:52.071484 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10546 12:28:52.074852 [ 0.000000] efi: UEFI not found.
10547 12:28:52.081819 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10548 12:28:52.088008 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10549 12:28:52.097786 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10550 12:28:52.107697 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10551 12:28:52.114544 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10552 12:28:52.121196 [ 0.000000] printk: bootconsole [mtk8250] enabled
10553 12:28:52.127515 [ 0.000000] NUMA: No NUMA configuration found
10554 12:28:52.134406 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10555 12:28:52.137602 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10556 12:28:52.141044 [ 0.000000] Zone ranges:
10557 12:28:52.147276 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10558 12:28:52.150683 [ 0.000000] DMA32 empty
10559 12:28:52.157540 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10560 12:28:52.160886 [ 0.000000] Movable zone start for each node
10561 12:28:52.163878 [ 0.000000] Early memory node ranges
10562 12:28:52.170556 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10563 12:28:52.176997 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10564 12:28:52.183790 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10565 12:28:52.190004 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10566 12:28:52.196655 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10567 12:28:52.203632 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10568 12:28:52.259499 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10569 12:28:52.266205 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10570 12:28:52.272950 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10571 12:28:52.276188 [ 0.000000] psci: probing for conduit method from DT.
10572 12:28:52.282953 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10573 12:28:52.286085 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10574 12:28:52.293036 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10575 12:28:52.295638 [ 0.000000] psci: SMC Calling Convention v1.2
10576 12:28:52.302490 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10577 12:28:52.305805 [ 0.000000] Detected VIPT I-cache on CPU0
10578 12:28:52.312330 [ 0.000000] CPU features: detected: GIC system register CPU interface
10579 12:28:52.318682 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10580 12:28:52.325721 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10581 12:28:52.332292 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10582 12:28:52.341856 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10583 12:28:52.348490 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10584 12:28:52.351886 [ 0.000000] alternatives: applying boot alternatives
10585 12:28:52.358744 [ 0.000000] Fallback order for Node 0: 0
10586 12:28:52.365033 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10587 12:28:52.368204 [ 0.000000] Policy zone: Normal
10588 12:28:52.378540 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10589 12:28:52.391311 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10590 12:28:52.401556 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10591 12:28:52.411651 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10592 12:28:52.418076 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10593 12:28:52.421195 <6>[ 0.000000] software IO TLB: area num 8.
10594 12:28:52.478060 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10595 12:28:52.626786 <6>[ 0.000000] Memory: 7877108K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 475660K reserved, 32768K cma-reserved)
10596 12:28:52.633527 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10597 12:28:52.640267 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10598 12:28:52.643624 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10599 12:28:52.649867 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10600 12:28:52.656606 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10601 12:28:52.659928 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10602 12:28:52.669905 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10603 12:28:52.676535 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10604 12:28:52.682700 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10605 12:28:52.689586 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10606 12:28:52.692841 <6>[ 0.000000] GICv3: 608 SPIs implemented
10607 12:28:52.696093 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10608 12:28:52.702395 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10609 12:28:52.705956 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10610 12:28:52.712661 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10611 12:28:52.725553 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10612 12:28:52.738972 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10613 12:28:52.745626 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10614 12:28:52.753460 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10615 12:28:52.766517 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10616 12:28:52.773216 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10617 12:28:52.780165 <6>[ 0.009172] Console: colour dummy device 80x25
10618 12:28:52.789561 <6>[ 0.013900] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10619 12:28:52.796361 <6>[ 0.024343] pid_max: default: 32768 minimum: 301
10620 12:28:52.799685 <6>[ 0.029246] LSM: Security Framework initializing
10621 12:28:52.806466 <6>[ 0.034146] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10622 12:28:52.816423 <6>[ 0.041959] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10623 12:28:52.825907 <6>[ 0.051276] cblist_init_generic: Setting adjustable number of callback queues.
10624 12:28:52.829663 <6>[ 0.058776] cblist_init_generic: Setting shift to 3 and lim to 1.
10625 12:28:52.835966 <6>[ 0.065114] cblist_init_generic: Setting shift to 3 and lim to 1.
10626 12:28:52.842480 <6>[ 0.071521] rcu: Hierarchical SRCU implementation.
10627 12:28:52.849137 <6>[ 0.076535] rcu: Max phase no-delay instances is 1000.
10628 12:28:52.852699 <6>[ 0.083552] EFI services will not be available.
10629 12:28:52.859165 <6>[ 0.088523] smp: Bringing up secondary CPUs ...
10630 12:28:52.866576 <6>[ 0.093579] Detected VIPT I-cache on CPU1
10631 12:28:52.873343 <6>[ 0.093652] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10632 12:28:52.879938 <6>[ 0.093683] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10633 12:28:52.882960 <6>[ 0.094018] Detected VIPT I-cache on CPU2
10634 12:28:52.893072 <6>[ 0.094066] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10635 12:28:52.899384 <6>[ 0.094081] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10636 12:28:52.902636 <6>[ 0.094340] Detected VIPT I-cache on CPU3
10637 12:28:52.909224 <6>[ 0.094388] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10638 12:28:52.916044 <6>[ 0.094402] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10639 12:28:52.922391 <6>[ 0.094706] CPU features: detected: Spectre-v4
10640 12:28:52.925720 <6>[ 0.094713] CPU features: detected: Spectre-BHB
10641 12:28:52.929055 <6>[ 0.094719] Detected PIPT I-cache on CPU4
10642 12:28:52.938625 <6>[ 0.094776] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10643 12:28:52.945772 <6>[ 0.094792] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10644 12:28:52.948981 <6>[ 0.095087] Detected PIPT I-cache on CPU5
10645 12:28:52.955493 <6>[ 0.095150] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10646 12:28:52.961822 <6>[ 0.095166] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10647 12:28:52.965118 <6>[ 0.095449] Detected PIPT I-cache on CPU6
10648 12:28:52.974949 <6>[ 0.095515] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10649 12:28:52.981743 <6>[ 0.095531] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10650 12:28:52.985093 <6>[ 0.095832] Detected PIPT I-cache on CPU7
10651 12:28:52.991894 <6>[ 0.095898] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10652 12:28:52.998025 <6>[ 0.095914] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10653 12:28:53.001634 <6>[ 0.095961] smp: Brought up 1 node, 8 CPUs
10654 12:28:53.008478 <6>[ 0.237262] SMP: Total of 8 processors activated.
10655 12:28:53.014482 <6>[ 0.242214] CPU features: detected: 32-bit EL0 Support
10656 12:28:53.021568 <6>[ 0.247574] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10657 12:28:53.027710 <6>[ 0.256426] CPU features: detected: Common not Private translations
10658 12:28:53.035041 <6>[ 0.262904] CPU features: detected: CRC32 instructions
10659 12:28:53.041078 <6>[ 0.268257] CPU features: detected: RCpc load-acquire (LDAPR)
10660 12:28:53.044407 <6>[ 0.274216] CPU features: detected: LSE atomic instructions
10661 12:28:53.051053 <6>[ 0.279997] CPU features: detected: Privileged Access Never
10662 12:28:53.057721 <6>[ 0.285821] CPU features: detected: RAS Extension Support
10663 12:28:53.064242 <6>[ 0.291431] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10664 12:28:53.067681 <6>[ 0.298698] CPU: All CPU(s) started at EL2
10665 12:28:53.074379 <6>[ 0.303041] alternatives: applying system-wide alternatives
10666 12:28:53.084576 <6>[ 0.313763] devtmpfs: initialized
10667 12:28:53.096571 <6>[ 0.322565] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10668 12:28:53.106663 <6>[ 0.332528] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10669 12:28:53.113368 <6>[ 0.340749] pinctrl core: initialized pinctrl subsystem
10670 12:28:53.116717 <6>[ 0.347408] DMI not present or invalid.
10671 12:28:53.122989 <6>[ 0.351816] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10672 12:28:53.132656 <6>[ 0.358679] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10673 12:28:53.139327 <6>[ 0.366258] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10674 12:28:53.149312 <6>[ 0.374480] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10675 12:28:53.152743 <6>[ 0.382721] audit: initializing netlink subsys (disabled)
10676 12:28:53.162414 <5>[ 0.388417] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10677 12:28:53.169188 <6>[ 0.389120] thermal_sys: Registered thermal governor 'step_wise'
10678 12:28:53.175717 <6>[ 0.396381] thermal_sys: Registered thermal governor 'power_allocator'
10679 12:28:53.179002 <6>[ 0.402635] cpuidle: using governor menu
10680 12:28:53.185606 <6>[ 0.413597] NET: Registered PF_QIPCRTR protocol family
10681 12:28:53.192271 <6>[ 0.419073] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10682 12:28:53.199142 <6>[ 0.426177] ASID allocator initialised with 32768 entries
10683 12:28:53.202134 <6>[ 0.432746] Serial: AMBA PL011 UART driver
10684 12:28:53.211735 <4>[ 0.441412] Trying to register duplicate clock ID: 134
10685 12:28:53.265884 <6>[ 0.498514] KASLR enabled
10686 12:28:53.280296 <6>[ 0.506247] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10687 12:28:53.286556 <6>[ 0.513262] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10688 12:28:53.293622 <6>[ 0.519750] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10689 12:28:53.300354 <6>[ 0.526755] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10690 12:28:53.306527 <6>[ 0.533243] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10691 12:28:53.313324 <6>[ 0.540248] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10692 12:28:53.320155 <6>[ 0.546734] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10693 12:28:53.326590 <6>[ 0.553740] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10694 12:28:53.329615 <6>[ 0.561260] ACPI: Interpreter disabled.
10695 12:28:53.338473 <6>[ 0.567653] iommu: Default domain type: Translated
10696 12:28:53.344611 <6>[ 0.572765] iommu: DMA domain TLB invalidation policy: strict mode
10697 12:28:53.348104 <5>[ 0.579419] SCSI subsystem initialized
10698 12:28:53.354764 <6>[ 0.583588] usbcore: registered new interface driver usbfs
10699 12:28:53.361736 <6>[ 0.589321] usbcore: registered new interface driver hub
10700 12:28:53.364684 <6>[ 0.594873] usbcore: registered new device driver usb
10701 12:28:53.371799 <6>[ 0.600954] pps_core: LinuxPPS API ver. 1 registered
10702 12:28:53.381379 <6>[ 0.606147] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10703 12:28:53.384555 <6>[ 0.615491] PTP clock support registered
10704 12:28:53.387777 <6>[ 0.619732] EDAC MC: Ver: 3.0.0
10705 12:28:53.395388 <6>[ 0.624886] FPGA manager framework
10706 12:28:53.402556 <6>[ 0.628563] Advanced Linux Sound Architecture Driver Initialized.
10707 12:28:53.405226 <6>[ 0.635334] vgaarb: loaded
10708 12:28:53.411877 <6>[ 0.638497] clocksource: Switched to clocksource arch_sys_counter
10709 12:28:53.415296 <5>[ 0.644936] VFS: Disk quotas dquot_6.6.0
10710 12:28:53.422028 <6>[ 0.649120] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10711 12:28:53.424965 <6>[ 0.656311] pnp: PnP ACPI: disabled
10712 12:28:53.433797 <6>[ 0.663040] NET: Registered PF_INET protocol family
10713 12:28:53.443228 <6>[ 0.668622] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10714 12:28:53.454792 <6>[ 0.680901] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10715 12:28:53.465007 <6>[ 0.689716] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10716 12:28:53.471213 <6>[ 0.697686] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10717 12:28:53.481130 <6>[ 0.706384] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10718 12:28:53.487695 <6>[ 0.716129] TCP: Hash tables configured (established 65536 bind 65536)
10719 12:28:53.494215 <6>[ 0.722985] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10720 12:28:53.504001 <6>[ 0.730182] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10721 12:28:53.510455 <6>[ 0.737858] NET: Registered PF_UNIX/PF_LOCAL protocol family
10722 12:28:53.517123 <6>[ 0.744026] RPC: Registered named UNIX socket transport module.
10723 12:28:53.520876 <6>[ 0.750180] RPC: Registered udp transport module.
10724 12:28:53.526862 <6>[ 0.755111] RPC: Registered tcp transport module.
10725 12:28:53.533596 <6>[ 0.760042] RPC: Registered tcp NFSv4.1 backchannel transport module.
10726 12:28:53.536884 <6>[ 0.766713] PCI: CLS 0 bytes, default 64
10727 12:28:53.540350 <6>[ 0.771068] Unpacking initramfs...
10728 12:28:53.557090 <6>[ 0.783156] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10729 12:28:53.567235 <6>[ 0.791793] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10730 12:28:53.570517 <6>[ 0.800635] kvm [1]: IPA Size Limit: 40 bits
10731 12:28:53.576922 <6>[ 0.805161] kvm [1]: GICv3: no GICV resource entry
10732 12:28:53.580357 <6>[ 0.810182] kvm [1]: disabling GICv2 emulation
10733 12:28:53.586550 <6>[ 0.814867] kvm [1]: GIC system register CPU interface enabled
10734 12:28:53.589932 <6>[ 0.821025] kvm [1]: vgic interrupt IRQ18
10735 12:28:53.597533 <6>[ 0.826697] kvm [1]: VHE mode initialized successfully
10736 12:28:53.604094 <5>[ 0.833112] Initialise system trusted keyrings
10737 12:28:53.610729 <6>[ 0.837959] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10738 12:28:53.618868 <6>[ 0.848025] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10739 12:28:53.625537 <5>[ 0.854408] NFS: Registering the id_resolver key type
10740 12:28:53.629031 <5>[ 0.859709] Key type id_resolver registered
10741 12:28:53.635152 <5>[ 0.864122] Key type id_legacy registered
10742 12:28:53.641808 <6>[ 0.868403] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10743 12:28:53.648499 <6>[ 0.875326] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10744 12:28:53.655345 <6>[ 0.883065] 9p: Installing v9fs 9p2000 file system support
10745 12:28:53.691330 <5>[ 0.920077] Key type asymmetric registered
10746 12:28:53.694139 <5>[ 0.924423] Asymmetric key parser 'x509' registered
10747 12:28:53.704174 <6>[ 0.929578] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10748 12:28:53.707382 <6>[ 0.937192] io scheduler mq-deadline registered
10749 12:28:53.710673 <6>[ 0.941949] io scheduler kyber registered
10750 12:28:53.729453 <6>[ 0.959010] EINJ: ACPI disabled.
10751 12:28:53.762192 <4>[ 0.984531] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10752 12:28:53.771581 <4>[ 0.995208] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10753 12:28:53.786982 <6>[ 1.016151] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10754 12:28:53.794663 <6>[ 1.024052] printk: console [ttyS0] disabled
10755 12:28:53.822565 <6>[ 1.048698] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10756 12:28:53.828945 <6>[ 1.058181] printk: console [ttyS0] enabled
10757 12:28:53.832389 <6>[ 1.058181] printk: console [ttyS0] enabled
10758 12:28:53.839113 <6>[ 1.067074] printk: bootconsole [mtk8250] disabled
10759 12:28:53.842603 <6>[ 1.067074] printk: bootconsole [mtk8250] disabled
10760 12:28:53.848903 <6>[ 1.078373] SuperH (H)SCI(F) driver initialized
10761 12:28:53.852195 <6>[ 1.083663] msm_serial: driver initialized
10762 12:28:53.866587 <6>[ 1.092562] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10763 12:28:53.876516 <6>[ 1.101111] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10764 12:28:53.883009 <6>[ 1.109652] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10765 12:28:53.893308 <6>[ 1.118280] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10766 12:28:53.902808 <6>[ 1.126986] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10767 12:28:53.909460 <6>[ 1.135709] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10768 12:28:53.919265 <6>[ 1.144251] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10769 12:28:53.925883 <6>[ 1.153066] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10770 12:28:53.935585 <6>[ 1.161610] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10771 12:28:53.948101 <6>[ 1.177051] loop: module loaded
10772 12:28:53.954057 <6>[ 1.183082] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10773 12:28:53.977114 <4>[ 1.206438] mtk-pmic-keys: Failed to locate of_node [id: -1]
10774 12:28:53.983769 <6>[ 1.213352] megasas: 07.719.03.00-rc1
10775 12:28:53.993527 <6>[ 1.222950] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10776 12:28:54.004855 <6>[ 1.233871] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10777 12:28:54.021445 <6>[ 1.250644] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10778 12:28:54.078567 <6>[ 1.301031] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10779 12:28:57.527715 <6>[ 4.757764] Freeing initrd memory: 95828K
10780 12:28:57.538234 <6>[ 4.768135] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10781 12:28:57.549052 <6>[ 4.778929] tun: Universal TUN/TAP device driver, 1.6
10782 12:28:57.552495 <6>[ 4.784970] thunder_xcv, ver 1.0
10783 12:28:57.555404 <6>[ 4.788477] thunder_bgx, ver 1.0
10784 12:28:57.558728 <6>[ 4.791974] nicpf, ver 1.0
10785 12:28:57.569322 <6>[ 4.795979] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10786 12:28:57.572897 <6>[ 4.803455] hns3: Copyright (c) 2017 Huawei Corporation.
10787 12:28:57.579689 <6>[ 4.809041] hclge is initializing
10788 12:28:57.582936 <6>[ 4.812615] e1000: Intel(R) PRO/1000 Network Driver
10789 12:28:57.589253 <6>[ 4.817744] e1000: Copyright (c) 1999-2006 Intel Corporation.
10790 12:28:57.592567 <6>[ 4.823774] e1000e: Intel(R) PRO/1000 Network Driver
10791 12:28:57.599236 <6>[ 4.828991] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10792 12:28:57.605880 <6>[ 4.835177] igb: Intel(R) Gigabit Ethernet Network Driver
10793 12:28:57.612733 <6>[ 4.840827] igb: Copyright (c) 2007-2014 Intel Corporation.
10794 12:28:57.619248 <6>[ 4.846662] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10795 12:28:57.625537 <6>[ 4.853180] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10796 12:28:57.629079 <6>[ 4.859637] sky2: driver version 1.30
10797 12:28:57.635477 <6>[ 4.864612] VFIO - User Level meta-driver version: 0.3
10798 12:28:57.642908 <6>[ 4.872794] usbcore: registered new interface driver usb-storage
10799 12:28:57.649777 <6>[ 4.879236] usbcore: registered new device driver onboard-usb-hub
10800 12:28:57.658391 <6>[ 4.888323] mt6397-rtc mt6359-rtc: registered as rtc0
10801 12:28:57.668686 <6>[ 4.893784] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:28:57 UTC (1686054537)
10802 12:28:57.671946 <6>[ 4.903345] i2c_dev: i2c /dev entries driver
10803 12:28:57.688695 <6>[ 4.914967] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10804 12:28:57.695275 <6>[ 4.925110] sdhci: Secure Digital Host Controller Interface driver
10805 12:28:57.701946 <6>[ 4.931550] sdhci: Copyright(c) Pierre Ossman
10806 12:28:57.708568 <6>[ 4.936945] Synopsys Designware Multimedia Card Interface Driver
10807 12:28:57.712098 <6>[ 4.943569] mmc0: CQHCI version 5.10
10808 12:28:57.718413 <6>[ 4.944094] sdhci-pltfm: SDHCI platform and OF driver helper
10809 12:28:57.725353 <6>[ 4.955442] ledtrig-cpu: registered to indicate activity on CPUs
10810 12:28:57.736599 <6>[ 4.962792] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10811 12:28:57.742779 <6>[ 4.970180] usbcore: registered new interface driver usbhid
10812 12:28:57.746156 <6>[ 4.976011] usbhid: USB HID core driver
10813 12:28:57.752583 <6>[ 4.980251] spi_master spi0: will run message pump with realtime priority
10814 12:28:57.798038 <6>[ 5.021122] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10815 12:28:57.816959 <6>[ 5.036617] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10816 12:28:57.820435 <6>[ 5.050195] mmc0: Command Queue Engine enabled
10817 12:28:57.827148 <6>[ 5.051921] cros-ec-spi spi0.0: Chrome EC device registered
10818 12:28:57.833556 <6>[ 5.054964] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10819 12:28:57.837073 <6>[ 5.068077] mmcblk0: mmc0:0001 DA4128 116 GiB
10820 12:28:57.847745 <6>[ 5.077413] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10821 12:28:57.857534 <6>[ 5.078054] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10822 12:28:57.864443 <6>[ 5.084838] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10823 12:28:57.867316 <6>[ 5.094753] NET: Registered PF_PACKET protocol family
10824 12:28:57.874075 <6>[ 5.098533] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10825 12:28:57.877566 <6>[ 5.103326] 9pnet: Installing 9P2000 support
10826 12:28:57.884239 <6>[ 5.109045] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10827 12:28:57.890429 <5>[ 5.112965] Key type dns_resolver registered
10828 12:28:57.894111 <6>[ 5.124575] registered taskstats version 1
10829 12:28:57.900532 <5>[ 5.128961] Loading compiled-in X.509 certificates
10830 12:28:57.933250 <4>[ 5.156108] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10831 12:28:57.943084 <4>[ 5.166906] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10832 12:28:57.953461 <3>[ 5.179671] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10833 12:28:57.965375 <6>[ 5.195153] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10834 12:28:57.972224 <6>[ 5.201912] xhci-mtk 11200000.usb: xHCI Host Controller
10835 12:28:57.978762 <6>[ 5.207418] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10836 12:28:57.988990 <6>[ 5.215283] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10837 12:28:57.995666 <6>[ 5.224713] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10838 12:28:58.002260 <6>[ 5.230897] xhci-mtk 11200000.usb: xHCI Host Controller
10839 12:28:58.008824 <6>[ 5.236389] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10840 12:28:58.015302 <6>[ 5.244055] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10841 12:28:58.022267 <6>[ 5.251927] hub 1-0:1.0: USB hub found
10842 12:28:58.025724 <6>[ 5.255970] hub 1-0:1.0: 1 port detected
10843 12:28:58.035372 <6>[ 5.260320] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10844 12:28:58.038956 <6>[ 5.269134] hub 2-0:1.0: USB hub found
10845 12:28:58.041796 <6>[ 5.273181] hub 2-0:1.0: 1 port detected
10846 12:28:58.050545 <6>[ 5.280532] mtk-msdc 11f70000.mmc: Got CD GPIO
10847 12:28:58.068107 <6>[ 5.294766] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10848 12:28:58.075037 <6>[ 5.302932] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10849 12:28:58.084639 <4>[ 5.310917] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10850 12:28:58.094898 <6>[ 5.320609] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10851 12:28:58.101528 <6>[ 5.328702] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10852 12:28:58.111338 <6>[ 5.336786] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10853 12:28:58.117619 <6>[ 5.344725] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10854 12:28:58.124392 <6>[ 5.352594] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10855 12:28:58.134293 <6>[ 5.360421] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10856 12:28:58.145034 <6>[ 5.371161] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10857 12:28:58.154849 <6>[ 5.379528] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10858 12:28:58.161132 <6>[ 5.387914] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10859 12:28:58.171034 <6>[ 5.396260] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10860 12:28:58.177406 <6>[ 5.404629] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10861 12:28:58.187624 <6>[ 5.412975] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10862 12:28:58.194347 <6>[ 5.421344] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10863 12:28:58.204078 <6>[ 5.429689] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10864 12:28:58.210708 <6>[ 5.438052] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10865 12:28:58.220633 <6>[ 5.446396] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10866 12:28:58.227422 <6>[ 5.454740] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10867 12:28:58.237132 <6>[ 5.463083] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10868 12:28:58.243859 <6>[ 5.471429] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10869 12:28:58.253694 <6>[ 5.479772] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10870 12:28:58.259976 <6>[ 5.488115] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10871 12:28:58.266954 <6>[ 5.497037] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10872 12:28:58.274364 <6>[ 5.504515] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10873 12:28:58.281840 <6>[ 5.511640] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10874 12:28:58.292052 <6>[ 5.518813] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10875 12:28:58.298735 <6>[ 5.526146] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10876 12:28:58.308742 <6>[ 5.533073] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10877 12:28:58.315345 <6>[ 5.542215] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10878 12:28:58.325213 <6>[ 5.551380] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10879 12:28:58.335391 <6>[ 5.560692] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10880 12:28:58.345121 <6>[ 5.570169] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10881 12:28:58.354832 <6>[ 5.579644] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10882 12:28:58.365105 <6>[ 5.588771] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10883 12:28:58.371367 <6>[ 5.598245] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10884 12:28:58.381304 <6>[ 5.607372] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10885 12:28:58.391113 <6>[ 5.616675] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10886 12:28:58.401219 <6>[ 5.626842] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10887 12:28:58.411456 <6>[ 5.638274] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10888 12:28:58.432283 <6>[ 5.658812] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10889 12:28:58.459147 <6>[ 5.689164] hub 2-1:1.0: USB hub found
10890 12:28:58.462701 <6>[ 5.693581] hub 2-1:1.0: 3 ports detected
10891 12:28:58.583863 <6>[ 5.810769] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10892 12:28:58.738429 <6>[ 5.968190] hub 1-1:1.0: USB hub found
10893 12:28:58.741940 <6>[ 5.972618] hub 1-1:1.0: 4 ports detected
10894 12:28:58.820208 <6>[ 6.047013] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10895 12:28:59.064325 <6>[ 6.290770] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10896 12:28:59.196328 <6>[ 6.426335] hub 1-1.4:1.0: USB hub found
10897 12:28:59.199678 <6>[ 6.430983] hub 1-1.4:1.0: 2 ports detected
10898 12:28:59.495925 <6>[ 6.722768] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10899 12:28:59.687960 <6>[ 6.914798] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10900 12:29:10.697075 <6>[ 17.931364] ALSA device list:
10901 12:29:10.703408 <6>[ 17.934619] No soundcards found.
10902 12:29:10.715689 <6>[ 17.947030] Freeing unused kernel memory: 8384K
10903 12:29:10.719073 <6>[ 17.951941] Run /init as init process
10904 12:29:10.749197 <6>[ 17.980522] NET: Registered PF_INET6 protocol family
10905 12:29:10.755617 <6>[ 17.986938] Segment Routing with IPv6
10906 12:29:10.759244 <6>[ 17.990880] In-situ OAM (IOAM) with IPv6
10907 12:29:10.793482 <30>[ 18.005140] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10908 12:29:10.797153 <30>[ 18.028902] systemd[1]: Detected architecture arm64.
10909 12:29:10.797244
10910 12:29:10.803899 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10911 12:29:10.804001
10912 12:29:10.819599 <30>[ 18.050918] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10913 12:29:10.962874 <30>[ 18.190713] systemd[1]: Queued start job for default target Graphical Interface.
10914 12:29:10.992737 <30>[ 18.224223] systemd[1]: Created slice system-getty.slice.
10915 12:29:10.999268 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10916 12:29:11.016395 <30>[ 18.247403] systemd[1]: Created slice system-modprobe.slice.
10917 12:29:11.022818 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10918 12:29:11.040569 <30>[ 18.271909] systemd[1]: Created slice system-serial\x2dgetty.slice.
10919 12:29:11.050553 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10920 12:29:11.063921 <30>[ 18.295254] systemd[1]: Created slice User and Session Slice.
10921 12:29:11.070415 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10922 12:29:11.091352 <30>[ 18.319322] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10923 12:29:11.101336 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10924 12:29:11.119035 <30>[ 18.347280] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10925 12:29:11.125620 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10926 12:29:11.146304 <30>[ 18.370882] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10927 12:29:11.152797 <30>[ 18.382931] systemd[1]: Reached target Local Encrypted Volumes.
10928 12:29:11.159607 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10929 12:29:11.175994 <30>[ 18.407107] systemd[1]: Reached target Paths.
10930 12:29:11.179522 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10931 12:29:11.195238 <30>[ 18.426825] systemd[1]: Reached target Remote File Systems.
10932 12:29:11.201869 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10933 12:29:11.219704 <30>[ 18.451044] systemd[1]: Reached target Slices.
10934 12:29:11.226174 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10935 12:29:11.239585 <30>[ 18.471058] systemd[1]: Reached target Swap.
10936 12:29:11.242951 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10937 12:29:11.262878 <30>[ 18.491126] systemd[1]: Listening on initctl Compatibility Named Pipe.
10938 12:29:11.269932 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10939 12:29:11.276334 <30>[ 18.505908] systemd[1]: Listening on Journal Audit Socket.
10940 12:29:11.282630 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10941 12:29:11.295984 <30>[ 18.527087] systemd[1]: Listening on Journal Socket (/dev/log).
10942 12:29:11.302050 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10943 12:29:11.320080 <30>[ 18.551538] systemd[1]: Listening on Journal Socket.
10944 12:29:11.326997 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10945 12:29:11.339916 <30>[ 18.571110] systemd[1]: Listening on udev Control Socket.
10946 12:29:11.346173 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10947 12:29:11.364397 <30>[ 18.595443] systemd[1]: Listening on udev Kernel Socket.
10948 12:29:11.370552 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10949 12:29:11.407528 <30>[ 18.639074] systemd[1]: Mounting Huge Pages File System...
10950 12:29:11.414065 Mounting [0;1;39mHuge Pages File System[0m...
10951 12:29:11.429338 <30>[ 18.660761] systemd[1]: Mounting POSIX Message Queue File System...
10952 12:29:11.435759 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10953 12:29:11.453807 <30>[ 18.684965] systemd[1]: Mounting Kernel Debug File System...
10954 12:29:11.459962 Mounting [0;1;39mKernel Debug File System[0m...
10955 12:29:11.479240 <30>[ 18.707108] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10956 12:29:11.490589 <30>[ 18.718087] systemd[1]: Starting Create list of static device nodes for the current kernel...
10957 12:29:11.496581 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10958 12:29:11.514159 <30>[ 18.745170] systemd[1]: Starting Load Kernel Module configfs...
10959 12:29:11.520619 Starting [0;1;39mLoad Kernel Module configfs[0m...
10960 12:29:11.537732 <30>[ 18.769027] systemd[1]: Starting Load Kernel Module drm...
10961 12:29:11.544246 Starting [0;1;39mLoad Kernel Module drm[0m...
10962 12:29:11.562938 <30>[ 18.790975] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10963 12:29:11.573498 <30>[ 18.804729] systemd[1]: Starting Journal Service...
10964 12:29:11.576979 Starting [0;1;39mJournal Service[0m...
10965 12:29:11.594358 <30>[ 18.825790] systemd[1]: Starting Load Kernel Modules...
10966 12:29:11.600800 Starting [0;1;39mLoad Kernel Modules[0m...
10967 12:29:11.621492 <30>[ 18.849829] systemd[1]: Starting Remount Root and Kernel File Systems...
10968 12:29:11.628492 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10969 12:29:11.645985 <30>[ 18.877407] systemd[1]: Starting Coldplug All udev Devices...
10970 12:29:11.652445 Starting [0;1;39mColdplug All udev Devices[0m...
10971 12:29:11.669789 <30>[ 18.901369] systemd[1]: Mounted Huge Pages File System.
10972 12:29:11.676485 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10973 12:29:11.692136 <30>[ 18.923223] systemd[1]: Started Journal Service.
10974 12:29:11.697993 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10975 12:29:11.713641 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10976 12:29:11.728283 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10977 12:29:11.748058 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10978 12:29:11.768946 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10979 12:29:11.785281 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10980 12:29:11.804630 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10981 12:29:11.828491 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10982 12:29:11.847293 See 'systemctl status systemd-remount-fs.service' for details.
10983 12:29:11.892339 Mounting [0;1;39mKernel Configuration File System[0m...
10984 12:29:11.910274 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10985 12:29:11.927310 <46>[ 19.155325] systemd-journald[178]: Received client request to flush runtime journal.
10986 12:29:11.935892 Starting [0;1;39mLoad/Save Random Seed[0m...
10987 12:29:11.957898 Starting [0;1;39mApply Kernel Variables[0m...
10988 12:29:11.978494 Starting [0;1;39mCreate System Users[0m...
10989 12:29:11.999635 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10990 12:29:12.023726 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10991 12:29:12.036120 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10992 12:29:12.052513 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10993 12:29:12.072349 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10994 12:29:12.087963 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10995 12:29:12.139704 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10996 12:29:12.163934 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10997 12:29:12.175846 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10998 12:29:12.191723 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10999 12:29:12.235597 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11000 12:29:12.259672 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11001 12:29:12.284411 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11002 12:29:12.303728 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11003 12:29:12.357768 Starting [0;1;39mNetwork Time Synchronization[0m...
11004 12:29:12.378848 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11005 12:29:12.426018 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11006 12:29:12.455779 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11007 12:29:12.488233 <6>[ 19.716518] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11008 12:29:12.504249 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11009 12:29:12.514309 <6>[ 19.745758] remoteproc remoteproc0: scp is available
11010 12:29:12.524170 <4>[ 19.751293] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11011 12:29:12.531226 <6>[ 19.761744] remoteproc remoteproc0: powering up scp
11012 12:29:12.540879 <4>[ 19.767333] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11013 12:29:12.547246 <3>[ 19.777185] remoteproc remoteproc0: request_firmware failed: -2
11014 12:29:12.554302 <3>[ 19.783619] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11015 12:29:12.563758 <6>[ 19.784588] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11016 12:29:12.570678 <3>[ 19.791738] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11017 12:29:12.580818 <6>[ 19.799333] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11018 12:29:12.587296 <3>[ 19.810817] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11019 12:29:12.596695 [[0;32m OK [<6>[ 19.818030] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11020 12:29:12.603316 0m] Started [0;1;39mNetwork Time Synchronization[0m.
11021 12:29:12.613623 <3>[ 19.840855] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11022 12:29:12.619985 <3>[ 19.849835] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11023 12:29:12.629855 <3>[ 19.858205] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11024 12:29:12.636931 <4>[ 19.863913] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11025 12:29:12.646619 <3>[ 19.866312] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11026 12:29:12.653105 <4>[ 19.879944] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11027 12:29:12.660117 <3>[ 19.881682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11028 12:29:12.669473 <3>[ 19.897214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11029 12:29:12.676486 <6>[ 19.900973] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11030 12:29:12.682984 [[0;32m OK [<6>[ 19.914246] mc: Linux media interface: v0.10
11031 12:29:12.689429 <3>[ 19.916770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11032 12:29:12.699369 0m] Finished [0<6>[ 19.921688] usbcore: registered new interface driver r8152
11033 12:29:12.706310 ;1;39mLoad/Save <3>[ 19.927352] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11034 12:29:12.715977 Screen …s of l<3>[ 19.944592] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11035 12:29:12.726122 eds:white:kbd_ba<3>[ 19.954300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11036 12:29:12.728958 cklight[0m.
11037 12:29:12.735838 <6>[ 19.957340] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11038 12:29:12.742430 <3>[ 19.962871] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11039 12:29:12.749053 <6>[ 19.971149] pci_bus 0000:00: root bus resource [bus 00-ff]
11040 12:29:12.755439 <3>[ 19.979074] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11041 12:29:12.765498 <4>[ 19.985641] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11042 12:29:12.768883 <4>[ 19.985641] Fallback method does not support PEC.
11043 12:29:12.778349 <6>[ 19.987081] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11044 12:29:12.788393 <6>[ 19.987093] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11045 12:29:12.795469 <6>[ 19.987146] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11046 12:29:12.801990 <6>[ 19.987165] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11047 12:29:12.804967 <6>[ 19.987245] pci 0000:00:00.0: supports D1 D2
11048 12:29:12.811902 <6>[ 19.987249] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11049 12:29:12.821558 <6>[ 19.989211] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11050 12:29:12.828303 <6>[ 19.989344] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11051 12:29:12.834670 <6>[ 19.989375] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11052 12:29:12.841571 <6>[ 19.989394] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11053 12:29:12.851009 <6>[ 19.989412] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11054 12:29:12.854427 <6>[ 19.989525] pci 0000:01:00.0: supports D1 D2
11055 12:29:12.861422 <6>[ 19.989529] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11056 12:29:12.871141 <3>[ 19.992946] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11057 12:29:12.877723 <6>[ 19.998764] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11058 12:29:12.884203 <6>[ 19.998817] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11059 12:29:12.894112 <6>[ 19.998825] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11060 12:29:12.900689 <6>[ 19.998840] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11061 12:29:12.907264 <6>[ 19.998857] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11062 12:29:12.917218 <6>[ 19.998873] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11063 12:29:12.920580 <6>[ 19.998889] pci 0000:00:00.0: PCI bridge to [bus 01]
11064 12:29:12.930221 <6>[ 19.998897] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11065 12:29:12.937077 <6>[ 19.999148] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11066 12:29:12.941114 <6>[ 20.004330] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11067 12:29:12.947189 <6>[ 20.004817] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11068 12:29:12.957406 <6>[ 20.008099] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11069 12:29:12.967865 <3>[ 20.014240] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11070 12:29:12.974435 <6>[ 20.024049] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11071 12:29:12.983920 <6>[ 20.024698] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11072 12:29:12.991300 <6>[ 20.025991] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11073 12:29:13.001471 <3>[ 20.032358] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11074 12:29:13.005000 <6>[ 20.044930] videodev: Linux video capture interface: v2.00
11075 12:29:13.008491 <6>[ 20.045710] Bluetooth: Core ver 2.22
11076 12:29:13.015010 <6>[ 20.045795] NET: Registered PF_BLUETOOTH protocol family
11077 12:29:13.021570 <6>[ 20.045799] Bluetooth: HCI device and connection manager initialized
11078 12:29:13.028493 <6>[ 20.045821] Bluetooth: HCI socket layer initialized
11079 12:29:13.031796 <6>[ 20.045828] Bluetooth: L2CAP socket layer initialized
11080 12:29:13.038718 <6>[ 20.045842] Bluetooth: SCO socket layer initialized
11081 12:29:13.042613 <6>[ 20.045960] usbcore: registered new interface driver cdc_ether
11082 12:29:13.049021 <6>[ 20.058990] usbcore: registered new interface driver r8153_ecm
11083 12:29:13.058915 <5>[ 20.060909] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11084 12:29:13.065884 <4>[ 20.063122] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11085 12:29:13.075762 <4>[ 20.063147] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11086 12:29:13.082322 <5>[ 20.073810] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11087 12:29:13.089411 <6>[ 20.107695] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11088 12:29:13.092954 <6>[ 20.107916] usbcore: registered new interface driver btusb
11089 12:29:13.106278 <4>[ 20.108759] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11090 12:29:13.109235 <3>[ 20.108779] Bluetooth: hci0: Failed to load firmware file (-2)
11091 12:29:13.115688 <3>[ 20.108782] Bluetooth: hci0: Failed to set up firmware (-2)
11092 12:29:13.125939 <4>[ 20.108787] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11093 12:29:13.135481 <4>[ 20.113155] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11094 12:29:13.149071 <6>[ 20.122295] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11095 12:29:13.152066 <6>[ 20.129086] cfg80211: failed to load regulatory.db
11096 12:29:13.158725 <6>[ 20.137540] usbcore: registered new interface driver uvcvideo
11097 12:29:13.165403 <6>[ 20.146255] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11098 12:29:13.168839 <6>[ 20.162916] r8152 2-1.3:1.0 eth0: v1.12.13
11099 12:29:13.175116 <6>[ 20.170878] remoteproc remoteproc0: powering up scp
11100 12:29:13.182205 <6>[ 20.185350] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
11101 12:29:13.191625 <4>[ 20.195123] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11102 12:29:13.198579 <3>[ 20.228527] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11103 12:29:13.208885 <3>[ 20.229099] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
11104 12:29:13.215509 <3>[ 20.236664] remoteproc remoteproc0: request_firmware failed: -2
11105 12:29:13.222019 <3>[ 20.240346] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11106 12:29:13.232071 <3>[ 20.241113] power_supply sbs-5-000b: driver failed to report `status' property: -6
11107 12:29:13.238689 <6>[ 20.249298] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11108 12:29:13.245010 <3>[ 20.251866] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11109 12:29:13.251920 <6>[ 20.258591] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11110 12:29:13.262063 <3>[ 20.278547] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11111 12:29:13.271693 <3>[ 20.279399] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
11112 12:29:13.274990 <6>[ 20.300523] mt7921e 0000:01:00.0: ASIC revision: 79610010
11113 12:29:13.285112 <3>[ 20.324220] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11114 12:29:13.295132 <4>[ 20.417945] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11115 12:29:13.305044 <3>[ 20.439491] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11116 12:29:13.311103 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11117 12:29:13.329355 <4>[ 20.554525] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11118 12:29:13.354196 <3>[ 20.582641] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11119 12:29:13.386983 <3>[ 20.615075] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11120 12:29:13.451998 <4>[ 20.677369] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11121 12:29:13.508209 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11122 12:29:13.523483 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11123 12:29:13.542287 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11124 12:29:13.572184 [[0;32m OK [0m] Reached target [0;1;39mSyst<4>[ 20.797096] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11125 12:29:13.575156 em Time Set[0m.
11126 12:29:13.592494 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11127 12:29:13.607743 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11128 12:29:13.623449 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11129 12:29:13.642534 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11130 12:29:13.655173 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11131 12:29:13.671195 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11132 12:29:13.692205 <4>[ 20.917019] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11133 12:29:13.701877 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11134 12:29:13.763929 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11135 12:29:13.789969 Starting [0;1;39mUser Login Management[0m...
11136 12:29:13.812966 <4>[ 21.038076] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11137 12:29:13.819523 Starting [0;1;39mPermit User Sessions[0m...
11138 12:29:13.838208 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11139 12:29:13.892380 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11140 12:29:13.910006 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11141 12:29:13.941268 [[0;32m OK [0m] Reached target [0;1;39mLogi<4>[ 21.165746] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11142 12:29:13.944235 n Prompts[0m.
11143 12:29:13.983670 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11144 12:29:14.000075 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11145 12:29:14.020978 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11146 12:29:14.027600 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11147 12:29:14.061919 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface<4>[ 21.285655] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11148 12:29:14.062074 [0m.
11149 12:29:14.127664 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11150 12:29:14.151656 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11151 12:29:14.181742 <4>[ 21.407066] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11152 12:29:14.181905
11153 12:29:14.182012
11154 12:29:14.188364 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11155 12:29:14.188447
11156 12:29:14.191922 debian-bullseye-arm64 login: root (automatic login)
11157 12:29:14.192025
11158 12:29:14.192121
11159 12:29:14.217381 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 12:15:37 UTC 2023 aarch64
11160 12:29:14.217518
11161 12:29:14.223792 The programs included with the Debian GNU/Linux system are free software;
11162 12:29:14.230401 the exact distribution terms for each program are described in the
11163 12:29:14.233869 individual files in /usr/share/doc/*/copyright.
11164 12:29:14.233978
11165 12:29:14.240480 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11166 12:29:14.243482 permitted by applicable law.
11167 12:29:14.243958 Matched prompt #10: / #
11169 12:29:14.244211 Setting prompt string to ['/ #']
11170 12:29:14.244314 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11172 12:29:14.244523 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11173 12:29:14.244613 start: 2.2.6 expect-shell-connection (timeout 00:02:03) [common]
11174 12:29:14.244693 Setting prompt string to ['/ #']
11175 12:29:14.244786 Forcing a shell prompt, looking for ['/ #']
11177 12:29:14.295047 / #
11178 12:29:14.295222 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11179 12:29:14.295343 Waiting using forced prompt support (timeout 00:02:30)
11180 12:29:14.308212 <4>[ 21.533259] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11181 12:29:14.308314
11182 12:29:14.313130 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11183 12:29:14.313269 start: 2.2.7 export-device-env (timeout 00:02:03) [common]
11184 12:29:14.313408 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11185 12:29:14.313541 end: 2.2 depthcharge-retry (duration 00:02:57) [common]
11186 12:29:14.313668 end: 2 depthcharge-action (duration 00:02:57) [common]
11187 12:29:14.313796 start: 3 lava-test-retry (timeout 00:05:00) [common]
11188 12:29:14.313919 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11189 12:29:14.314028 Using namespace: common
11191 12:29:14.414397 / # #
11192 12:29:14.414598 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11193 12:29:14.419559 #<3>[ 21.651036] mt7921e 0000:01:00.0: hardware init failed
11194 12:29:14.419679
11195 12:29:14.423175 Using /lava-10605776
11197 12:29:14.523541 / # export SHELL=/bin/sh
11198 12:29:14.528220 export SHELL=/bin/sh
11200 12:29:14.628786 / # . /lava-10605776/environment
11201 12:29:14.634001 . /lava-10605776/environment
11203 12:29:14.734538 / # /lava-10605776/bin/lava-test-runner /lava-10605776/0
11204 12:29:14.734748 Test shell timeout: 10s (minimum of the action and connection timeout)
11205 12:29:14.739784 /lava-10605776/bin/lava-test-runner /lava-10605776/0
11206 12:29:14.760428 + export TESTRUN_ID=0_sleep
11207 12:29:14.763842 + cd /lava-10605776/0/tests/0_sleep
11208 12:29:14.767371 + cat uuid
11209 12:29:14.767481 + UUID=10605776_1.5.2.3.1
11210 12:29:14.770248 + set +x
11211 12:29:14.773806 <LAVA_SIGNAL_STARTRUN 0_sleep 10605776_1.5.2.3.1>
11212 12:29:14.774068 Received signal: <STARTRUN> 0_sleep 10605776_1.5.2.3.1
11213 12:29:14.774145 Starting test lava.0_sleep (10605776_1.5.2.3.1)
11214 12:29:14.774232 Skipping test definition patterns.
11215 12:29:14.776730 + ./config/lava/sleep/sleep.sh mem freeze
11216 12:29:14.780504 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11218 12:29:14.783769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11219 12:29:14.786698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11220 12:29:14.786950 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11222 12:29:14.790280 rtcwake: assuming RTC uses UTC ...
11223 12:29:14.800215 rtcwake: wakeup from "mem" using rtc0 at Tue<6>[ 22.031523] PM: suspend entry (deep)
11224 12:29:14.803769 Jun 6 12:29:20<6>[ 22.035635] Filesystems sync: 0.000 seconds
11225 12:29:14.806737 2023
11226 12:29:14.810131 <6>[ 22.042990] Freezing user space processes
11227 12:29:14.820485 <6>[ 22.048842] Freezing user space processes completed (elapsed 0.001 seconds)
11228 12:29:14.823730 <6>[ 22.056081] OOM killer disabled.
11229 12:29:14.827169 <6>[ 22.059564] Freezing remaining freezable tasks
11230 12:29:14.837176 <6>[ 22.065457] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11231 12:29:14.843519 <6>[ 22.073120] printk: Suspending console(s) (use no_console_suspend to debug)
11232 12:29:18.156020 <3>[ 25.162826] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11233 12:29:18.166132 <3>[ 25.162868] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11234 12:29:18.175698 <3>[ 25.162895] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11235 12:29:18.182630 <3>[ 25.162915] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11236 12:29:18.189239 <3>[ 25.163269] PM: Some devices failed to suspend, or early wake event detected
11237 12:29:18.199001 <4>[ 25.179402] typec port0-partner: PM: parent port0 should not be sleeping
11238 12:29:18.202136 <6>[ 25.434791] OOM killer enabled.
11239 12:29:18.205644 <6>[ 25.438185] Restarting tasks ... done.
11240 12:29:18.212640 <5>[ 25.443812] random: crng reseeded on system resumption
11241 12:29:18.215598 <6>[ 25.450303] PM: suspend exit
11242 12:29:18.218625 rtcwake: write error
11243 12:29:18.226402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11244 12:29:18.226662 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11246 12:29:18.229330 rtcwake: assuming RTC uses UTC ...
11247 12:29:18.235982 rtcwake: wakeup from "mem" using rtc0 at Tue Jun 6 12:29:24 2023
11248 12:29:18.249017 <6>[ 25.481263] PM: suspend entry (deep)
11249 12:29:18.252602 <6>[ 25.485176] Filesystems sync: 0.000 seconds
11250 12:29:18.258983 <6>[ 25.490326] Freezing user space processes
11251 12:29:18.266009 <6>[ 25.496432] Freezing user space processes completed (elapsed 0.001 seconds)
11252 12:29:18.268895 <6>[ 25.503735] OOM killer disabled.
11253 12:29:18.275541 <6>[ 25.507225] Freezing remaining freezable tasks
11254 12:29:18.282465 <6>[ 25.513263] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11255 12:29:18.291946 <6>[ 25.520964] printk: Suspending console(s) (use no_console_suspend to debug)
11256 12:29:21.744328 <3>[ 28.746751] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11257 12:29:21.753980 <3>[ 28.746774] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11258 12:29:21.764013 <3>[ 28.746800] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11259 12:29:21.770817 <3>[ 28.746822] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11260 12:29:21.777139 <3>[ 28.747068] PM: Some devices failed to suspend, or early wake event detected
11261 12:29:21.783796 <6>[ 29.016358] OOM killer enabled.
11262 12:29:21.786699 <6>[ 29.019757] Restarting tasks ... done.
11263 12:29:21.793601 <5>[ 29.025284] random: crng reseeded on system resumption
11264 12:29:21.797008 <6>[ 29.031549] PM: suspend exit
11265 12:29:21.799840 rtcwake: write error
11266 12:29:21.807000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11267 12:29:21.807273 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11269 12:29:21.810504 rtcwake: assuming RTC uses UTC ...
11270 12:29:21.816991 rtcwake: wakeup from "mem" using rtc0 at Tue Jun 6 12:29:27 2023
11271 12:29:21.829299 <6>[ 29.062133] PM: suspend entry (deep)
11272 12:29:21.832754 <6>[ 29.066043] Filesystems sync: 0.000 seconds
11273 12:29:21.836319 <6>[ 29.071136] Freezing user space processes
11274 12:29:21.847786 <6>[ 29.077034] Freezing user space processes completed (elapsed 0.001 seconds)
11275 12:29:21.850975 <6>[ 29.084312] OOM killer disabled.
11276 12:29:21.854367 <6>[ 29.087801] Freezing remaining freezable tasks
11277 12:29:21.864325 <6>[ 29.093802] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11278 12:29:21.871225 <6>[ 29.101456] printk: Suspending console(s) (use no_console_suspend to debug)
11279 12:29:25.331473 <3>[ 32.330778] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11280 12:29:25.341505 <3>[ 32.330801] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11281 12:29:25.351989 <3>[ 32.330827] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11282 12:29:25.358364 <3>[ 32.330849] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11283 12:29:25.364828 <3>[ 32.331185] PM: Some devices failed to suspend, or early wake event detected
11284 12:29:25.368456 <6>[ 32.604405] OOM killer enabled.
11285 12:29:25.376637 <6>[ 32.607804] Restarting tasks ... done.
11286 12:29:25.379500 <5>[ 32.613495] random: crng reseeded on system resumption
11287 12:29:25.383684 <6>[ 32.620209] PM: suspend exit
11288 12:29:25.387188 rtcwake: write error
11289 12:29:25.395350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11290 12:29:25.395650 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11292 12:29:25.398833 rtcwake: assuming RTC uses UTC ...
11293 12:29:25.405157 rtcwake: wakeup from "mem" using rtc0 at Tue Jun 6 12:29:31 2023
11294 12:29:25.417982 <6>[ 32.651027] PM: suspend entry (deep)
11295 12:29:25.421359 <6>[ 32.654919] Filesystems sync: 0.000 seconds
11296 12:29:25.424605 <6>[ 32.659973] Freezing user space processes
11297 12:29:25.436254 <6>[ 32.666009] Freezing user space processes completed (elapsed 0.001 seconds)
11298 12:29:25.440074 <6>[ 32.673243] OOM killer disabled.
11299 12:29:25.443090 <6>[ 32.676725] Freezing remaining freezable tasks
11300 12:29:25.452815 <6>[ 32.682537] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11301 12:29:25.459264 <6>[ 32.690194] printk: Suspending console(s) (use no_console_suspend to debug)
11302 12:29:28.915105 <3>[ 35.914806] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11303 12:29:28.924979 <3>[ 35.914856] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11304 12:29:28.935180 <3>[ 35.914914] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11305 12:29:28.941717 <3>[ 35.914972] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11306 12:29:28.951725 <3>[ 35.915348] PM: Some devices failed to suspend, or early wake event detected
11307 12:29:28.955359 <6>[ 36.188539] OOM killer enabled.
11308 12:29:28.958217 <6>[ 36.191939] Restarting tasks ... done.
11309 12:29:28.964705 <5>[ 36.198074] random: crng reseeded on system resumption
11310 12:29:28.968287 <6>[ 36.204794] PM: suspend exit
11311 12:29:28.971724 rtcwake: write error
11312 12:29:28.979313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11313 12:29:28.979574 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11315 12:29:28.982910 rtcwake: assuming RTC uses UTC ...
11316 12:29:28.989459 rtcwake: wakeup from "mem" using rtc0 at Tue Jun 6 12:29:35 2023
11317 12:29:29.002431 <6>[ 36.235718] PM: suspend entry (deep)
11318 12:29:29.005780 <6>[ 36.239650] Filesystems sync: 0.000 seconds
11319 12:29:29.009230 <6>[ 36.244638] Freezing user space processes
11320 12:29:29.020889 <6>[ 36.250708] Freezing user space processes completed (elapsed 0.001 seconds)
11321 12:29:29.023847 <6>[ 36.257937] OOM killer disabled.
11322 12:29:29.027317 <6>[ 36.261420] Freezing remaining freezable tasks
11323 12:29:29.037291 <6>[ 36.267471] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11324 12:29:29.043830 <6>[ 36.275147] printk: Suspending console(s) (use no_console_suspend to debug)
11325 12:29:32.499047 <3>[ 39.498790] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11326 12:29:32.511926 <3>[ 39.498819] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11327 12:29:32.518900 <3>[ 39.498854] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11328 12:29:32.525433 <3>[ 39.498881] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11329 12:29:32.535171 <3>[ 39.499358] PM: Some devices failed to suspend, or early wake event detected
11330 12:29:32.538305 <6>[ 39.772485] OOM killer enabled.
11331 12:29:32.541877 <6>[ 39.775885] Restarting tasks ... done.
11332 12:29:32.548224 <5>[ 39.781521] random: crng reseeded on system resumption
11333 12:29:32.551679 <6>[ 39.788179] PM: suspend exit
11334 12:29:32.554704 rtcwake: write error
11335 12:29:32.562258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11336 12:29:32.562515 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11338 12:29:32.565142 rtcwake: assuming RTC uses UTC ...
11339 12:29:32.572219 rtcwake: wakeup from "mem" using rtc0 at Tue Jun 6 12:29:38 2023
11340 12:29:32.584838 <6>[ 39.818776] PM: suspend entry (deep)
11341 12:29:32.588325 <6>[ 39.822682] Filesystems sync: 0.000 seconds
11342 12:29:32.591834 <6>[ 39.827720] Freezing user space processes
11343 12:29:32.603052 <6>[ 39.833729] Freezing user space processes completed (elapsed 0.001 seconds)
11344 12:29:32.606597 <6>[ 39.841050] OOM killer disabled.
11345 12:29:32.609729 <6>[ 39.844537] Freezing remaining freezable tasks
11346 12:29:32.620126 <6>[ 39.850659] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11347 12:29:32.626549 <6>[ 39.858335] printk: Suspending console(s) (use no_console_suspend to debug)
11348 12:29:36.082379 <3>[ 43.082795] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11349 12:29:36.092154 <3>[ 43.082820] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11350 12:29:36.102441 <3>[ 43.082852] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11351 12:29:36.108951 <3>[ 43.082874] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11352 12:29:36.118892 <3>[ 43.083293] PM: Some devices failed to suspend, or early wake event detected
11353 12:29:36.121839 <6>[ 43.356482] OOM killer enabled.
11354 12:29:36.125101 <6>[ 43.359883] Restarting tasks ... done.
11355 12:29:36.132127 <5>[ 43.365689] random: crng reseeded on system resumption
11356 12:29:36.135592 <6>[ 43.372366] PM: suspend exit
11357 12:29:36.138346 rtcwake: write error
11358 12:29:36.146704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11359 12:29:36.147011 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11361 12:29:36.149632 rtcwake: assuming RTC uses UTC ...
11362 12:29:36.156079 rtcwake: wakeup from "mem" using rtc0 at Tue Jun 6 12:29:42 2023
11363 12:29:36.169427 <6>[ 43.403582] PM: suspend entry (deep)
11364 12:29:36.172878 <6>[ 43.407491] Filesystems sync: 0.000 seconds
11365 12:29:36.175905 <6>[ 43.412616] Freezing user space processes
11366 12:29:36.187775 <6>[ 43.418560] Freezing user space processes completed (elapsed 0.001 seconds)
11367 12:29:36.190857 <6>[ 43.425846] OOM killer disabled.
11368 12:29:36.194466 <6>[ 43.429337] Freezing remaining freezable tasks
11369 12:29:36.204617 <6>[ 43.435231] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11370 12:29:36.211088 <6>[ 43.442890] printk: Suspending console(s) (use no_console_suspend to debug)
11371 12:29:39.665824 <3>[ 46.666807] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11372 12:29:39.679393 <3>[ 46.666835] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11373 12:29:39.686115 <3>[ 46.666869] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11374 12:29:39.692317 <3>[ 46.666891] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11375 12:29:39.702378 <3>[ 46.667288] PM: Some devices failed to suspend, or early wake event detected
11376 12:29:39.705719 <6>[ 46.940506] OOM killer enabled.
11377 12:29:39.709242 <6>[ 46.943906] Restarting tasks ... done.
11378 12:29:39.715430 <5>[ 46.949599] random: crng reseeded on system resumption
11379 12:29:39.718709 <6>[ 46.956168] PM: suspend exit
11380 12:29:39.722092 rtcwake: write error
11381 12:29:39.729686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11382 12:29:39.729950 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11384 12:29:39.733289 rtcwake: assuming RTC uses UTC ...
11385 12:29:39.739702 rtcwake: wakeup from "mem" using rtc0 at Tue Jun 6 12:29:45 2023
11386 12:29:39.752874 <6>[ 46.987394] PM: suspend entry (deep)
11387 12:29:39.756334 <6>[ 46.991295] Filesystems sync: 0.000 seconds
11388 12:29:39.759301 <6>[ 46.996378] Freezing user space processes
11389 12:29:39.771093 <6>[ 47.002258] Freezing user space processes completed (elapsed 0.001 seconds)
11390 12:29:39.774526 <6>[ 47.009594] OOM killer disabled.
11391 12:29:39.777531 <6>[ 47.013079] Freezing remaining freezable tasks
11392 12:29:39.787875 <6>[ 47.018533] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11393 12:29:39.794102 <6>[ 47.026185] printk: Suspending console(s) (use no_console_suspend to debug)
11394 12:29:43.246369 <6>[ 48.202853] vpu: disabling
11395 12:29:43.249827 <6>[ 48.202953] vproc2: disabling
11396 12:29:43.253187 <6>[ 48.202992] vproc1: disabling
11397 12:29:43.256247 <6>[ 48.203031] vaud18: disabling
11398 12:29:43.259774 <6>[ 48.203215] vsram_others: disabling
11399 12:29:43.263321 <6>[ 48.203361] va09: disabling
11400 12:29:43.266134 <6>[ 48.203417] vsram_md: disabling
11401 12:29:43.269551 <6>[ 48.203513] Vgpu: disabling
11402 12:29:43.276452 <3>[ 50.250775] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11403 12:29:43.286201 <3>[ 50.250801] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11404 12:29:43.296017 <3>[ 50.250833] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11405 12:29:43.302488 <3>[ 50.250854] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11406 12:29:43.309095 <3>[ 50.251238] PM: Some devices failed to suspend, or early wake event detected
11407 12:29:43.315603 <6>[ 50.550652] OOM killer enabled.
11408 12:29:43.319096 <6>[ 50.554047] Restarting tasks ... done.
11409 12:29:43.325497 <5>[ 50.559622] random: crng reseeded on system resumption
11410 12:29:43.328843 <6>[ 50.565834] PM: suspend exit
11411 12:29:43.332243 rtcwake: write error
11412 12:29:43.338622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11413 12:29:43.338962 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11415 12:29:43.342184 rtcwake: assuming RTC uses UTC ...
11416 12:29:43.348485 rtcwake: wakeup from "mem" using rtc0 at Tue Jun 6 12:29:49 2023
11417 12:29:43.361697 <6>[ 50.596550] PM: suspend entry (deep)
11418 12:29:43.364963 <6>[ 50.600445] Filesystems sync: 0.000 seconds
11419 12:29:43.368478 <6>[ 50.605610] Freezing user space processes
11420 12:29:43.380249 <6>[ 50.611742] Freezing user space processes completed (elapsed 0.001 seconds)
11421 12:29:43.383356 <6>[ 50.618980] OOM killer disabled.
11422 12:29:43.386895 <6>[ 50.622458] Freezing remaining freezable tasks
11423 12:29:43.396576 <6>[ 50.628431] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11424 12:29:43.403166 <6>[ 50.636096] printk: Suspending console(s) (use no_console_suspend to debug)
11425 12:29:46.832981 <3>[ 53.834769] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11426 12:29:46.846516 <3>[ 53.834794] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11427 12:29:46.852866 <3>[ 53.834827] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11428 12:29:46.859426 <3>[ 53.834848] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11429 12:29:46.869380 <3>[ 53.835288] PM: Some devices failed to suspend, or early wake event detected
11430 12:29:46.872872 <6>[ 54.108488] OOM killer enabled.
11431 12:29:46.876157 <6>[ 54.111888] Restarting tasks ... done.
11432 12:29:46.883016 <5>[ 54.117721] random: crng reseeded on system resumption
11433 12:29:46.885977 <6>[ 54.124242] PM: suspend exit
11434 12:29:46.889281 rtcwake: write error
11435 12:29:46.897168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11436 12:29:46.897470 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11438 12:29:46.900462 rtcwake: assuming RTC uses UTC ...
11439 12:29:46.906762 rtcwake: wakeup from "mem" using rtc0 at Tue Jun 6 12:29:53 2023
11440 12:29:46.919740 <6>[ 54.155204] PM: suspend entry (deep)
11441 12:29:46.923305 <6>[ 54.159113] Filesystems sync: 0.000 seconds
11442 12:29:46.929827 <6>[ 54.164220] Freezing user space processes
11443 12:29:46.936240 <6>[ 54.170083] Freezing user space processes completed (elapsed 0.001 seconds)
11444 12:29:46.939680 <6>[ 54.177434] OOM killer disabled.
11445 12:29:46.946061 <6>[ 54.180927] Freezing remaining freezable tasks
11446 12:29:46.953117 <6>[ 54.186535] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11447 12:29:46.959135 <6>[ 54.194191] printk: Suspending console(s) (use no_console_suspend to debug)
11448 12:29:50.416077 <3>[ 57.418768] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11449 12:29:50.426166 <3>[ 57.418794] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11450 12:29:50.435974 <3>[ 57.418826] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11451 12:29:50.442930 <3>[ 57.418847] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11452 12:29:50.452538 <3>[ 57.419411] PM: Some devices failed to suspend, or early wake event detected
11453 12:29:50.456189 <6>[ 57.691975] OOM killer enabled.
11454 12:29:50.459183 <6>[ 57.695373] Restarting tasks ... done.
11455 12:29:50.466048 <5>[ 57.701016] random: crng reseeded on system resumption
11456 12:29:50.469246 <6>[ 57.707980] PM: suspend exit
11457 12:29:50.472301 rtcwake: write error
11458 12:29:50.480192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11459 12:29:50.480474 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11461 12:29:50.483340 rtcwake: assuming RTC uses UTC ...
11462 12:29:50.490010 rtcwake: wakeup from "freeze" using rtc0 at Tue Jun 6 12:29:56 2023
11463 12:29:50.503731 <6>[ 57.739655] PM: suspend entry (s2idle)
11464 12:29:50.507521 <6>[ 57.743723] Filesystems sync: 0.000 seconds
11465 12:29:50.513814 <6>[ 57.748868] Freezing user space processes
11466 12:29:50.520118 <6>[ 57.754681] Freezing user space processes completed (elapsed 0.001 seconds)
11467 12:29:50.523953 <6>[ 57.761903] OOM killer disabled.
11468 12:29:50.530259 <6>[ 57.765386] Freezing remaining freezable tasks
11469 12:29:50.536953 <6>[ 57.771309] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11470 12:29:50.546491 <6>[ 57.778964] printk: Suspending console(s) (use no_console_suspend to debug)
11471 12:29:54.000052 <3>[ 61.002789] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11472 12:29:54.010126 <3>[ 61.002842] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11473 12:29:54.019969 <3>[ 61.002904] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11474 12:29:54.026780 <3>[ 61.002981] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11475 12:29:54.036306 <3>[ 61.003263] PM: Some devices failed to suspend, or early wake event detected
11476 12:29:54.039686 <6>[ 61.276012] OOM killer enabled.
11477 12:29:54.042662 <6>[ 61.279414] Restarting tasks ... done.
11478 12:29:54.049373 <5>[ 61.285641] random: crng reseeded on system resumption
11479 12:29:54.052850 <6>[ 61.292334] PM: suspend exit
11480 12:29:54.056244 rtcwake: write error
11481 12:29:54.064843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11482 12:29:54.065136 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11484 12:29:54.067929 rtcwake: assuming RTC uses UTC ...
11485 12:29:54.074162 rtcwake: wakeup from "freeze" using rtc0 at Tue Jun 6 12:30:00 2023
11486 12:29:54.087300 <6>[ 61.323627] PM: suspend entry (s2idle)
11487 12:29:54.090779 <6>[ 61.327744] Filesystems sync: 0.000 seconds
11488 12:29:54.097532 <6>[ 61.332752] Freezing user space processes
11489 12:29:54.103825 <6>[ 61.338680] Freezing user space processes completed (elapsed 0.001 seconds)
11490 12:29:54.106986 <6>[ 61.345902] OOM killer disabled.
11491 12:29:54.113754 <6>[ 61.349385] Freezing remaining freezable tasks
11492 12:29:54.120646 <6>[ 61.355320] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11493 12:29:54.130392 <6>[ 61.362979] printk: Suspending console(s) (use no_console_suspend to debug)
11494 12:29:57.584065 <3>[ 64.586756] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11495 12:29:57.594005 <3>[ 64.586779] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11496 12:29:57.603840 <3>[ 64.586805] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11497 12:29:57.610160 <3>[ 64.586827] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11498 12:29:57.619962 <3>[ 64.587171] PM: Some devices failed to suspend, or early wake event detected
11499 12:29:57.623566 <6>[ 64.860430] OOM killer enabled.
11500 12:29:57.626595 <6>[ 64.863829] Restarting tasks ... done.
11501 12:29:57.633222 <5>[ 64.869558] random: crng reseeded on system resumption
11502 12:29:57.636896 <6>[ 64.876219] PM: suspend exit
11503 12:29:57.639912 rtcwake: write error
11504 12:29:57.647545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11505 12:29:57.647819 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11507 12:29:57.651056 rtcwake: assuming RTC uses UTC ...
11508 12:29:57.657912 rtcwake: wakeup from "freeze" using rtc0 at Tue Jun 6 12:30:03 2023
11509 12:29:57.670881 <6>[ 64.907330] PM: suspend entry (s2idle)
11510 12:29:57.674016 <6>[ 64.911409] Filesystems sync: 0.000 seconds
11511 12:29:57.680359 <6>[ 64.916420] Freezing user space processes
11512 12:29:57.686981 <6>[ 64.922371] Freezing user space processes completed (elapsed 0.001 seconds)
11513 12:29:57.690671 <6>[ 64.929649] OOM killer disabled.
11514 12:29:57.696983 <6>[ 64.933136] Freezing remaining freezable tasks
11515 12:29:57.703992 <6>[ 64.939070] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11516 12:29:57.713245 <6>[ 64.946732] printk: Suspending console(s) (use no_console_suspend to debug)
11517 12:30:01.159791 <3>[ 68.170820] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11518 12:30:01.169579 <3>[ 68.170851] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11519 12:30:01.179394 <3>[ 68.170893] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11520 12:30:01.186252 <3>[ 68.170930] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11521 12:30:01.192904 <3>[ 68.171438] PM: Some devices failed to suspend, or early wake event detected
11522 12:30:01.196054 <6>[ 68.436527] OOM killer enabled.
11523 12:30:01.205108 <6>[ 68.439928] Restarting tasks ... done.
11524 12:30:01.208198 <5>[ 68.446166] random: crng reseeded on system resumption
11525 12:30:01.212654 <6>[ 68.453069] PM: suspend exit
11526 12:30:01.216304 rtcwake: write error
11527 12:30:01.224189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11528 12:30:01.224463 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11530 12:30:01.227263 rtcwake: assuming RTC uses UTC ...
11531 12:30:01.233556 rtcwake: wakeup from "freeze" using rtc0 at Tue Jun 6 12:30:07 2023
11532 12:30:01.246676 <6>[ 68.483754] PM: suspend entry (s2idle)
11533 12:30:01.249765 <6>[ 68.487835] Filesystems sync: 0.000 seconds
11534 12:30:01.256659 <6>[ 68.492922] Freezing user space processes
11535 12:30:01.263487 <6>[ 68.498629] Freezing user space processes completed (elapsed 0.001 seconds)
11536 12:30:01.266424 <6>[ 68.505855] OOM killer disabled.
11537 12:30:01.273156 <6>[ 68.509337] Freezing remaining freezable tasks
11538 12:30:01.279961 <6>[ 68.515321] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11539 12:30:01.289799 <6>[ 68.522977] printk: Suspending console(s) (use no_console_suspend to debug)
11540 12:30:04.751293 <3>[ 71.754795] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11541 12:30:04.761228 <3>[ 71.754822] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11542 12:30:04.771907 <3>[ 71.754858] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11543 12:30:04.777440 <3>[ 71.754890] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11544 12:30:04.787537 <3>[ 71.755354] PM: Some devices failed to suspend, or early wake event detected
11545 12:30:04.790539 <6>[ 72.028401] OOM killer enabled.
11546 12:30:04.794304 <6>[ 72.031800] Restarting tasks ... done.
11547 12:30:04.800972 <5>[ 72.037499] random: crng reseeded on system resumption
11548 12:30:04.804089 <6>[ 72.043806] PM: suspend exit
11549 12:30:04.807105 rtcwake: write error
11550 12:30:04.814501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11551 12:30:04.814765 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11553 12:30:04.817788 rtcwake: assuming RTC uses UTC ...
11554 12:30:04.823984 rtcwake: wakeup from "freeze" using rtc0 at Tue Jun 6 12:30:10 2023
11555 12:30:04.836810 <6>[ 72.074424] PM: suspend entry (s2idle)
11556 12:30:04.840510 <6>[ 72.078522] Filesystems sync: 0.000 seconds
11557 12:30:04.846951 <6>[ 72.083483] Freezing user space processes
11558 12:30:04.853620 <6>[ 72.089390] Freezing user space processes completed (elapsed 0.001 seconds)
11559 12:30:04.856755 <6>[ 72.096740] OOM killer disabled.
11560 12:30:04.863475 <6>[ 72.100241] Freezing remaining freezable tasks
11561 12:30:04.870307 <6>[ 72.106251] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11562 12:30:04.879676 <6>[ 72.113907] printk: Suspending console(s) (use no_console_suspend to debug)
11563 12:30:08.326865 <3>[ 75.338795] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11564 12:30:08.336756 <3>[ 75.338822] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11565 12:30:08.346510 <3>[ 75.338858] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11566 12:30:08.353544 <3>[ 75.338884] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11567 12:30:08.363370 <3>[ 75.339334] PM: Some devices failed to suspend, or early wake event detected
11568 12:30:08.366508 <6>[ 75.604586] OOM killer enabled.
11569 12:30:08.369803 <6>[ 75.607987] Restarting tasks ... done.
11570 12:30:08.376179 <5>[ 75.614192] random: crng reseeded on system resumption
11571 12:30:08.379996 <6>[ 75.621516] PM: suspend exit
11572 12:30:08.383535 rtcwake: write error
11573 12:30:08.391723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11574 12:30:08.391987 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11576 12:30:08.394955 rtcwake: assuming RTC uses UTC ...
11577 12:30:08.401361 rtcwake: wakeup from "freeze" using rtc0 at Tue Jun 6 12:30:14 2023
11578 12:30:08.414520 <6>[ 75.652120] PM: suspend entry (s2idle)
11579 12:30:08.417578 <6>[ 75.656176] Filesystems sync: 0.000 seconds
11580 12:30:08.424232 <6>[ 75.661342] Freezing user space processes
11581 12:30:08.430834 <6>[ 75.667421] Freezing user space processes completed (elapsed 0.001 seconds)
11582 12:30:08.434451 <6>[ 75.674644] OOM killer disabled.
11583 12:30:08.440731 <6>[ 75.678121] Freezing remaining freezable tasks
11584 12:30:08.447336 <6>[ 75.684099] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11585 12:30:08.456984 <6>[ 75.691768] printk: Suspending console(s) (use no_console_suspend to debug)
11586 12:30:11.918446 <3>[ 78.922771] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11587 12:30:11.928485 <3>[ 78.922797] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11588 12:30:11.938481 <3>[ 78.922829] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11589 12:30:11.945210 <3>[ 78.922850] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11590 12:30:11.955066 <3>[ 78.923240] PM: Some devices failed to suspend, or early wake event detected
11591 12:30:11.958218 <6>[ 79.196596] OOM killer enabled.
11592 12:30:11.961346 <6>[ 79.199997] Restarting tasks ... done.
11593 12:30:11.968063 <5>[ 79.206293] random: crng reseeded on system resumption
11594 12:30:11.971277 <6>[ 79.212887] PM: suspend exit
11595 12:30:11.974384 rtcwake: write error
11596 12:30:11.983029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11597 12:30:11.983324 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11599 12:30:11.986297 rtcwake: assuming RTC uses UTC ...
11600 12:30:11.992425 rtcwake: wakeup from "freeze" using rtc0 at Tue Jun 6 12:30:18 2023
11601 12:30:12.004877 <6>[ 79.243373] PM: suspend entry (s2idle)
11602 12:30:12.008358 <6>[ 79.247441] Filesystems sync: 0.000 seconds
11603 12:30:12.015003 <6>[ 79.252577] Freezing user space processes
11604 12:30:12.021257 <6>[ 79.258606] Freezing user space processes completed (elapsed 0.001 seconds)
11605 12:30:12.025073 <6>[ 79.265830] OOM killer disabled.
11606 12:30:12.031841 <6>[ 79.269316] Freezing remaining freezable tasks
11607 12:30:12.037977 <6>[ 79.275253] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11608 12:30:12.048409 <6>[ 79.282925] printk: Suspending console(s) (use no_console_suspend to debug)
11609 12:30:15.501783 <3>[ 82.506772] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11610 12:30:15.511651 <3>[ 82.506797] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11611 12:30:15.521777 <3>[ 82.506830] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11612 12:30:15.528228 <3>[ 82.506852] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11613 12:30:15.538128 <3>[ 82.507288] PM: Some devices failed to suspend, or early wake event detected
11614 12:30:15.541229 <6>[ 82.780374] OOM killer enabled.
11615 12:30:15.545028 <6>[ 82.783774] Restarting tasks ... done.
11616 12:30:15.551229 <5>[ 82.789575] random: crng reseeded on system resumption
11617 12:30:15.554507 <6>[ 82.796662] PM: suspend exit
11618 12:30:15.558348 rtcwake: write error
11619 12:30:15.566082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11620 12:30:15.566376 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11622 12:30:15.569793 rtcwake: assuming RTC uses UTC ...
11623 12:30:15.575861 rtcwake: wakeup from "freeze" using rtc0 at Tue Jun 6 12:30:21 2023
11624 12:30:15.589245 <6>[ 82.827620] PM: suspend entry (s2idle)
11625 12:30:15.592290 <6>[ 82.831698] Filesystems sync: 0.000 seconds
11626 12:30:15.599101 <6>[ 82.836758] Freezing user space processes
11627 12:30:15.605276 <6>[ 82.842646] Freezing user space processes completed (elapsed 0.001 seconds)
11628 12:30:15.608839 <6>[ 82.849869] OOM killer disabled.
11629 12:30:15.615629 <6>[ 82.853359] Freezing remaining freezable tasks
11630 12:30:15.621828 <6>[ 82.859287] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11631 12:30:15.631990 <6>[ 82.866944] printk: Suspending console(s) (use no_console_suspend to debug)
11632 12:30:19.085032 <3>[ 86.090767] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11633 12:30:19.094824 <3>[ 86.090792] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11634 12:30:19.104845 <3>[ 86.090824] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11635 12:30:19.111705 <3>[ 86.090846] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11636 12:30:19.118060 <3>[ 86.091256] PM: Some devices failed to suspend, or early wake event detected
11637 12:30:19.121492 <6>[ 86.363894] OOM killer enabled.
11638 12:30:19.129894 <6>[ 86.367295] Restarting tasks ... done.
11639 12:30:19.133616 <5>[ 86.373301] random: crng reseeded on system resumption
11640 12:30:19.137826 <6>[ 86.380002] PM: suspend exit
11641 12:30:19.140998 rtcwake: write error
11642 12:30:19.148929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11643 12:30:19.149196 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11645 12:30:19.152608 rtcwake: assuming RTC uses UTC ...
11646 12:30:19.158913 rtcwake: wakeup from "freeze" using rtc0 at Tue Jun 6 12:30:25 2023
11647 12:30:19.171781 <6>[ 86.410874] PM: suspend entry (s2idle)
11648 12:30:19.175394 <6>[ 86.414931] Filesystems sync: 0.000 seconds
11649 12:30:19.181512 <6>[ 86.420043] Freezing user space processes
11650 12:30:19.188208 <6>[ 86.426222] Freezing user space processes completed (elapsed 0.001 seconds)
11651 12:30:19.191266 <6>[ 86.433491] OOM killer disabled.
11652 12:30:19.198630 <6>[ 86.436975] Freezing remaining freezable tasks
11653 12:30:19.204740 <6>[ 86.442565] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11654 12:30:19.214859 <6>[ 86.450224] printk: Suspending console(s) (use no_console_suspend to debug)
11655 12:30:22.669537 <3>[ 89.674775] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11656 12:30:22.679458 <3>[ 89.674798] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11657 12:30:22.689548 <3>[ 89.674824] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11658 12:30:22.695825 <3>[ 89.674847] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11659 12:30:22.706055 <3>[ 89.675246] PM: Some devices failed to suspend, or early wake event detected
11660 12:30:22.709089 <6>[ 89.948591] OOM killer enabled.
11661 12:30:22.712163 <6>[ 89.951991] Restarting tasks ... done.
11662 12:30:22.718644 <5>[ 89.958045] random: crng reseeded on system resumption
11663 12:30:22.722735 <6>[ 89.965525] PM: suspend exit
11664 12:30:22.725819 rtcwake: write error
11665 12:30:22.734844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11666 12:30:22.735139 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11668 12:30:22.737438 rtcwake: assuming RTC uses UTC ...
11669 12:30:22.743829 rtcwake: wakeup from "freeze" using rtc0 at Tue Jun 6 12:30:28 2023
11670 12:30:22.756941 <6>[ 89.996470] PM: suspend entry (s2idle)
11671 12:30:22.760515 <6>[ 90.000570] Filesystems sync: 0.000 seconds
11672 12:30:22.766716 <6>[ 90.005702] Freezing user space processes
11673 12:30:22.773808 <6>[ 90.011731] Freezing user space processes completed (elapsed 0.001 seconds)
11674 12:30:22.777011 <6>[ 90.018957] OOM killer disabled.
11675 12:30:22.783272 <6>[ 90.022434] Freezing remaining freezable tasks
11676 12:30:22.790215 <6>[ 90.028458] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11677 12:30:22.799742 <6>[ 90.036117] printk: Suspending console(s) (use no_console_suspend to debug)
11678 12:30:26.248843 <3>[ 93.258796] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11679 12:30:26.258585 <3>[ 93.258825] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11680 12:30:26.268717 <3>[ 93.258862] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11681 12:30:26.274981 <3>[ 93.258884] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11682 12:30:26.282028 <3>[ 93.259347] PM: Some devices failed to suspend, or early wake event detected
11683 12:30:26.284998 <6>[ 93.527982] OOM killer enabled.
11684 12:30:26.293466 <6>[ 93.531380] Restarting tasks ... done.
11685 12:30:26.296370 <5>[ 93.536959] random: crng reseeded on system resumption
11686 12:30:26.301328 <6>[ 93.543884] PM: suspend exit
11687 12:30:26.304262 rtcwake: write error
11688 12:30:26.312072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11689 12:30:26.312787 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11691 12:30:26.315774 + set +x
11692 12:30:26.318831 <LAVA_SIGNAL_ENDRUN 0_sleep 10605776_1.5.2.3.1>
11693 12:30:26.319427 <LAVA_TEST_RUNNER EXIT>
11694 12:30:26.320029 Received signal: <ENDRUN> 0_sleep 10605776_1.5.2.3.1
11695 12:30:26.320476 Ending use of test pattern.
11696 12:30:26.320792 Ending test lava.0_sleep (10605776_1.5.2.3.1), duration 71.55
11698 12:30:26.322687 ok: lava_test_shell seems to have completed
11699 12:30:26.323642 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11700 12:30:26.324116 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11701 12:30:26.324548 end: 3 lava-test-retry (duration 00:01:12) [common]
11702 12:30:26.324986 start: 4 finalize (timeout 00:05:17) [common]
11703 12:30:26.325416 start: 4.1 power-off (timeout 00:00:30) [common]
11704 12:30:26.326160 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11705 12:30:26.452260 >> Command sent successfully.
11706 12:30:26.454604 Returned 0 in 0 seconds
11707 12:30:26.555343 end: 4.1 power-off (duration 00:00:00) [common]
11709 12:30:26.556772 start: 4.2 read-feedback (timeout 00:05:17) [common]
11710 12:30:26.557946 Listened to connection for namespace 'common' for up to 1s
11711 12:30:26.558731 Listened to connection for namespace 'common' for up to 1s
11712 12:30:27.558412 Finalising connection for namespace 'common'
11713 12:30:27.558595 Disconnecting from shell: Finalise
11714 12:30:27.558702 / #
11715 12:30:27.659021 end: 4.2 read-feedback (duration 00:00:01) [common]
11716 12:30:27.659196 end: 4 finalize (duration 00:00:01) [common]
11717 12:30:27.659310 Cleaning after the job
11718 12:30:27.659406 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605776/tftp-deploy-yypd6nms/ramdisk
11719 12:30:27.668863 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605776/tftp-deploy-yypd6nms/kernel
11720 12:30:27.681461 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605776/tftp-deploy-yypd6nms/dtb
11721 12:30:27.681665 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605776/tftp-deploy-yypd6nms/modules
11722 12:30:27.683682 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605776
11723 12:30:27.819519 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605776
11724 12:30:27.819717 Job finished correctly