Boot log: qemu_arm64-virt-gicv3
- Errors: 0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 4
1 12:26:31.732713 lava-dispatcher, installed at version: 2023.01
2 12:26:31.732897 start: 0 validate
3 12:26:31.733006 Start time: 2023-06-06 12:26:31.733000+00:00 (UTC)
4 12:26:31.734051 Validating that http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig/gcc-10/kernel/Image exists
5 12:26:32.092104 Validating that http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz exists
6 12:26:32.271027 cmd: ['docker', 'pull', 'kernelci/qemu']
7 12:26:32.271206 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
8 12:26:32.420259 >> Using default tag: latest
9 12:26:33.526592 >> latest: Pulling from kernelci/qemu
10 12:26:33.558652 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
11 12:26:33.558857 >> Status: Image is up to date for kernelci/qemu:latest
12 12:26:33.591655 >> docker.io/kernelci/qemu:latest
13 12:26:33.594968 Returned 0 in 1 seconds
14 12:26:33.732888 cmd: ['docker', 'run', '--rm', '--init', 'kernelci/qemu', 'qemu-system-aarch64', '--version']
15 12:26:33.733380 Calling: 'nice' 'docker' 'run' '--rm' '--init' 'kernelci/qemu' 'qemu-system-aarch64' '--version'
16 12:26:37.723264 >> QEMU emulator version 7.2.2 (Debian 1:7.2+dfsg-7~bpo11+1)
17 12:26:37.723598 >> Copyright (c) 2003-2022 Fabrice Bellard and the QEMU Project developers
18 12:26:40.618086 Returned 0 in 6 seconds
19 12:26:40.719370 validate duration: 8.99
21 12:26:40.719938 start: 1 deployimages (timeout 00:03:00) [common]
22 12:26:40.720110 start: 1.1 lava-overlay (timeout 00:03:00) [common]
23 12:26:40.720579 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11
24 12:26:40.720838 makedir: /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin
25 12:26:40.721046 makedir: /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/tests
26 12:26:40.721246 makedir: /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/results
27 12:26:40.721447 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-add-keys
28 12:26:40.721733 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-add-sources
29 12:26:40.721979 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-background-process-start
30 12:26:40.722222 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-background-process-stop
31 12:26:40.722458 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-common-functions
32 12:26:40.722686 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-echo-ipv4
33 12:26:40.722920 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-install-packages
34 12:26:40.723152 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-installed-packages
35 12:26:40.723378 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-os-build
36 12:26:40.723606 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-probe-channel
37 12:26:40.723838 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-probe-ip
38 12:26:40.724068 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-target-ip
39 12:26:40.724295 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-target-mac
40 12:26:40.724522 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-target-storage
41 12:26:40.724752 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-test-case
42 12:26:40.724982 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-test-event
43 12:26:40.725211 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-test-feedback
44 12:26:40.725441 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-test-raise
45 12:26:40.725685 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-test-reference
46 12:26:40.725917 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-test-runner
47 12:26:40.726143 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-test-set
48 12:26:40.726370 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-test-shell
49 12:26:40.726605 Updating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-install-packages (oe)
50 12:26:40.726894 Updating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/bin/lava-installed-packages (oe)
51 12:26:40.727147 Creating /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/environment
52 12:26:40.727354 LAVA metadata
53 12:26:40.727493 - LAVA_JOB_ID=568933
54 12:26:40.727622 - LAVA_DISPATCHER_IP=172.27.0.2
55 12:26:40.727813 start: 1.1.1 lava-vland-overlay (timeout 00:03:00) [common]
56 12:26:40.727948 skipped lava-vland-overlay
57 12:26:40.728096 end: 1.1.1 lava-vland-overlay (duration 00:00:00) [common]
58 12:26:40.728255 start: 1.1.2 lava-multinode-overlay (timeout 00:03:00) [common]
59 12:26:40.728384 skipped lava-multinode-overlay
60 12:26:40.728527 end: 1.1.2 lava-multinode-overlay (duration 00:00:00) [common]
61 12:26:40.728681 start: 1.1.3 test-definition (timeout 00:03:00) [common]
62 12:26:40.728828 Loading test definitions
63 12:26:40.729004 start: 1.1.3.1 inline-repo-action (timeout 00:03:00) [common]
64 12:26:40.729146 Using /lava-568933 at stage 0
65 12:26:40.729741 uuid=568933_1.1.3.1 testdef=None
66 12:26:40.729919 end: 1.1.3.1 inline-repo-action (duration 00:00:00) [common]
67 12:26:40.730077 start: 1.1.3.2 test-overlay (timeout 00:03:00) [common]
68 12:26:40.730958 end: 1.1.3.2 test-overlay (duration 00:00:00) [common]
70 12:26:40.731426 start: 1.1.3.3 test-install-overlay (timeout 00:03:00) [common]
71 12:26:40.732525 end: 1.1.3.3 test-install-overlay (duration 00:00:00) [common]
73 12:26:40.733003 start: 1.1.3.4 test-runscript-overlay (timeout 00:03:00) [common]
74 12:26:40.734086 runner path: /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/0/tests/0_timesync-off test_uuid 568933_1.1.3.1
75 12:26:40.734367 end: 1.1.3.4 test-runscript-overlay (duration 00:00:00) [common]
77 12:26:40.734839 start: 1.1.3.5 git-repo-action (timeout 00:03:00) [common]
78 12:26:40.734978 Using /lava-568933 at stage 0
79 12:26:40.735167 Fetching tests from https://github.com/kernelci/test-definitions.git
80 12:26:40.735314 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/0/tests/1_kselftest-arm64_qemu'
81 12:26:44.858061 Running '/usr/bin/git checkout kernelci.org
82 12:26:45.023958 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/0/tests/1_kselftest-arm64_qemu/automated/linux/kselftest/kselftest.yaml
83 12:26:45.025091 uuid=568933_1.1.3.5 testdef=None
84 12:26:45.025333 end: 1.1.3.5 git-repo-action (duration 00:00:04) [common]
86 12:26:45.025819 start: 1.1.3.6 test-overlay (timeout 00:02:56) [common]
87 12:26:45.027376 end: 1.1.3.6 test-overlay (duration 00:00:00) [common]
89 12:26:45.027877 start: 1.1.3.7 test-install-overlay (timeout 00:02:56) [common]
90 12:26:45.030052 end: 1.1.3.7 test-install-overlay (duration 00:00:00) [common]
92 12:26:45.030555 start: 1.1.3.8 test-runscript-overlay (timeout 00:02:56) [common]
93 12:26:45.032596 runner path: /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/0/tests/1_kselftest-arm64_qemu test_uuid 568933_1.1.3.5
94 12:26:45.032770 BOARD='qemu_arm64-virt-gicv3'
95 12:26:45.032895 BRANCH='cip'
96 12:26:45.033011 SKIPFILE='/dev/null'
97 12:26:45.033127 SKIP_INSTALL='True'
98 12:26:45.033243 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig/gcc-10/kselftest.tar.xz'
99 12:26:45.033364 TST_CASENAME=''
100 12:26:45.033480 TST_CMDFILES='arm64'
101 12:26:45.033749 end: 1.1.3.8 test-runscript-overlay (duration 00:00:00) [common]
103 12:26:45.034207 Creating lava-test-runner.conf files
104 12:26:45.034333 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/568933/lava-overlay-fi1fdz11/lava-568933/0 for stage 0
105 12:26:45.034512 - 0_timesync-off
106 12:26:45.034648 - 1_kselftest-arm64_qemu
107 12:26:45.034824 end: 1.1.3 test-definition (duration 00:00:04) [common]
108 12:26:45.034990 start: 1.1.4 compress-overlay (timeout 00:02:56) [common]
109 12:26:53.763493 end: 1.1.4 compress-overlay (duration 00:00:09) [common]
110 12:26:53.763664 start: 1.1.5 persistent-nfs-overlay (timeout 00:02:47) [common]
111 12:26:53.763788 end: 1.1.5 persistent-nfs-overlay (duration 00:00:00) [common]
112 12:26:53.763908 end: 1.1 lava-overlay (duration 00:00:13) [common]
113 12:26:53.763999 start: 1.2 apply-overlay-guest (timeout 00:02:47) [common]
114 12:26:53.764078 Overlay: /var/lib/lava/dispatcher/tmp/568933/compress-overlay-2t5j1acu/overlay-1.1.4.tar.gz
115 12:27:08.813392 end: 1.2 apply-overlay-guest (duration 00:00:15) [common]
117 12:27:08.814286 start: 1.3 deploy-device-env (timeout 00:02:32) [common]
118 12:27:08.814493 end: 1.3 deploy-device-env (duration 00:00:00) [common]
119 12:27:08.814704 start: 1.4 download-retry (timeout 00:02:32) [common]
120 12:27:08.814917 start: 1.4.1 http-download (timeout 00:02:32) [common]
121 12:27:08.815272 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig/gcc-10/kernel/Image
122 12:27:08.815441 saving as /var/lib/lava/dispatcher/tmp/568933/deployimages-qs5w04wn/kernel/Image
123 12:27:08.815594 total size: 37358080 (35MB)
124 12:27:08.815743 No compression specified
125 12:27:09.172574 progress 0% (0MB)
126 12:27:10.235884 progress 5% (1MB)
127 12:27:10.611952 progress 10% (3MB)
128 12:27:10.628454 progress 15% (5MB)
129 12:27:10.798702 progress 20% (7MB)
130 12:27:10.978034 progress 25% (8MB)
131 12:27:11.157325 progress 30% (10MB)
132 12:27:11.336285 progress 35% (12MB)
133 12:27:11.673190 progress 40% (14MB)
134 12:27:11.858355 progress 45% (16MB)
135 12:27:12.036953 progress 50% (17MB)
136 12:27:12.215529 progress 55% (19MB)
137 12:27:12.393774 progress 60% (21MB)
138 12:27:12.571983 progress 65% (23MB)
139 12:27:12.750009 progress 70% (24MB)
140 12:27:12.927719 progress 75% (26MB)
141 12:27:13.105428 progress 80% (28MB)
142 12:27:13.282563 progress 85% (30MB)
143 12:27:13.459379 progress 90% (32MB)
144 12:27:13.636575 progress 95% (33MB)
145 12:27:13.812977 progress 100% (35MB)
146 12:27:13.813310 35MB downloaded in 5.00s (7.13MB/s)
147 12:27:13.813629 end: 1.4.1 http-download (duration 00:00:05) [common]
149 12:27:13.814223 end: 1.4 download-retry (duration 00:00:05) [common]
150 12:27:13.814413 start: 1.5 download-retry (timeout 00:02:27) [common]
151 12:27:13.814593 start: 1.5.1 http-download (timeout 00:02:27) [common]
152 12:27:13.814836 Not decompressing ramdisk as can be used compressed.
153 12:27:13.815021 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz
154 12:27:13.815163 saving as /var/lib/lava/dispatcher/tmp/568933/deployimages-qs5w04wn/ramdisk/rootfs.cpio.gz
155 12:27:13.815301 total size: 88976554 (84MB)
156 12:27:13.815436 No compression specified
157 12:27:13.994430 progress 0% (0MB)
158 12:27:14.383089 progress 5% (4MB)
159 12:27:14.913131 progress 10% (8MB)
160 12:27:15.448617 progress 15% (12MB)
161 12:27:15.982348 progress 20% (17MB)
162 12:27:16.514045 progress 25% (21MB)
163 12:27:17.045025 progress 30% (25MB)
164 12:27:17.574826 progress 35% (29MB)
165 12:27:18.103787 progress 40% (33MB)
166 12:27:18.607596 progress 45% (38MB)
167 12:27:19.008952 progress 50% (42MB)
168 12:27:19.541422 progress 55% (46MB)
169 12:27:20.069660 progress 60% (50MB)
170 12:27:20.557433 progress 65% (55MB)
171 12:27:20.969862 progress 70% (59MB)
172 12:27:21.494668 progress 75% (63MB)
173 12:27:22.013554 progress 80% (67MB)
174 12:27:22.392073 progress 85% (72MB)
175 12:27:22.916550 progress 90% (76MB)
176 12:27:23.438059 progress 95% (80MB)
177 12:27:23.928112 progress 100% (84MB)
178 12:27:23.928448 84MB downloaded in 10.11s (8.39MB/s)
179 12:27:23.928703 end: 1.5.1 http-download (duration 00:00:10) [common]
181 12:27:23.929174 end: 1.5 download-retry (duration 00:00:10) [common]
182 12:27:23.929331 end: 1 deployimages (duration 00:00:43) [common]
183 12:27:23.929490 start: 2 boot-image-retry (timeout 00:05:00) [common]
184 12:27:23.929657 start: 2.1 boot-qemu-image (timeout 00:05:00) [common]
185 12:27:23.929812 start: 2.1.1 execute-qemu (timeout 00:05:00) [common]
186 12:27:23.930160 Extending command line for qcow2 test overlay
187 12:27:23.930759 Pulling docker image
188 12:27:23.930920 cmd: ['docker', 'pull', 'kernelci/qemu']
189 12:27:23.931053 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
190 12:27:24.090584 >> Using default tag: latest
191 12:27:25.231035 >> latest: Pulling from kernelci/qemu
192 12:27:25.262731 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
193 12:27:25.262968 >> Status: Image is up to date for kernelci/qemu:latest
194 12:27:25.296203 >> docker.io/kernelci/qemu:latest
195 12:27:25.299911 Returned 0 in 1 seconds
196 12:27:25.437860 Boot command: docker run --network=host --cap-add=NET_ADMIN --interactive --tty --rm --init --name=lava-docker-qemu-568933-2.1.1-58qd14nm3e --mount=type=bind,source=/var/lib/lava/dispatcher/tmp,destination=/var/lib/lava/dispatcher/tmp kernelci/qemu qemu-system-aarch64 -cpu max,pauth-impdef=on -machine virt,gic-version=3,mte=on,accel=tcg -nographic -net nic,model=virtio,macaddr=52:54:00:12:34:58 -net user -m 1g -monitor none -kernel /var/lib/lava/dispatcher/tmp/568933/deployimages-qs5w04wn/kernel/Image -append "console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon" -initrd /var/lib/lava/dispatcher/tmp/568933/deployimages-qs5w04wn/ramdisk/rootfs.cpio.gz -drive format=qcow2,file=/var/lib/lava/dispatcher/tmp/568933/apply-overlay-guest-vpts5shr/lava-guest.qcow2,media=disk,if=virtio,id=lavatest
197 12:27:25.571852 started a shell command
198 12:27:25.572391 end: 2.1.1 execute-qemu (duration 00:00:02) [common]
199 12:27:25.572595 end: 2.1 boot-qemu-image (duration 00:00:02) [common]
200 12:27:25.572769 start: 2.2 auto-login-action (timeout 00:04:58) [common]
201 12:27:25.572947 Setting prompt string to ['Linux version [0-9]']
202 12:27:25.573089 auto-login-action: Wait for prompt ['Linux version [0-9]'] (timeout 00:05:00)
203 12:27:28.278644 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510]
204 12:27:28.279498 start: 2.2.1 login-action (timeout 00:04:56) [common]
205 12:27:28.279682 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
206 12:27:28.279873 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
207 12:27:28.280045 Using line separator: #'\n'#
208 12:27:28.280182 No login prompt set.
209 12:27:28.280327 Parsing kernel messages
210 12:27:28.280453 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
211 12:27:28.280697 [login-action] Waiting for messages, (timeout 00:04:56)
212 12:27:28.282036 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1615036-arm64-gcc-10-defconfig-kvxhb) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 12:10:19 UTC 2023
213 12:27:28.282204 [ 0.000000] random: crng init done
214 12:27:28.282335 [ 0.000000] Machine model: linux,dummy-virt
215 12:27:28.282468 [ 0.000000] efi: UEFI not found.
216 12:27:28.282593 [ 0.000000] earlycon: pl11 at MMIO 0x0000000009000000 (options '')
217 12:27:28.282717 [ 0.000000] printk: bootconsole [pl11] enabled
218 12:27:28.283048 [ 0.000000] NUMA: No NUMA configuration found
219 12:27:28.283392 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000007fffffff]
220 12:27:28.283760 [ 0.000000] NUMA: NODE_DATA [mem 0x7fdf2a00-0x7fdf4fff]
221 12:27:28.285891 [ 0.000000] Zone ranges:
222 12:27:28.286488 [ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff]
223 12:27:28.286997 [ 0.000000] DMA32 empty
224 12:27:28.287209 [ 0.000000] Normal empty
225 12:27:28.287399 [ 0.000000] Movable zone start for each node
226 12:27:28.287589 [ 0.000000] Early memory node ranges
227 12:27:28.287775 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff]
228 12:27:28.287997 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff]
229 12:27:28.301818 [ 0.000000] cma: Reserved 32 MiB at 0x000000007cc00000
230 12:27:28.302967 [ 0.000000] psci: probing for conduit method from DT.
231 12:27:28.303176 [ 0.000000] psci: PSCIv1.1 detected in firmware.
232 12:27:28.303332 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
233 12:27:28.303494 [ 0.000000] psci: Trusted OS migration not required
234 12:27:28.303621 [ 0.000000] psci: SMC Calling Convention v1.0
235 12:27:28.305827 [ 0.000000] percpu: Embedded 20 pages/cpu s44840 r8192 d28888 u81920
236 12:27:28.306271 [ 0.000000] pcpu-alloc: s44840 r8192 d28888 u81920 alloc=20*4096
237 12:27:28.306675 [ 0.000000] pcpu-alloc: [0] 0
238 12:27:28.308175 [ 0.000000] Detected PIPT I-cache on CPU0
239 12:27:28.313263 [ 0.000000] CPU features: detected: Address authentication (IMP DEF algorithm)
240 12:27:28.314007 [ 0.000000] CPU features: detected: GIC system register CPU interface
241 12:27:28.314207 [ 0.000000] CPU features: detected: Hardware dirty bit management
242 12:27:28.314398 [ 0.000000] CPU features: detected: Memory Tagging Extension
243 12:27:28.314530 [ 0.000000] CPU features: detected: Asymmetric MTE Tag Check Fault
244 12:27:28.314895 [ 0.000000] CPU features: detected: Spectre-v4
245 12:27:28.318484 [ 0.000000] alternatives: applying boot alternatives
246 12:27:28.321237 [ 0.000000] Fallback order for Node 0: 0
247 12:27:28.321561 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258048
248 12:27:28.321673 [ 0.000000] Policy zone: DMA
249 12:27:28.322274 [ 0.000000] Kernel command line: console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon
250 12:27:28.324725 <5>[ 0.000000] Unknown kernel command line parameters \"verbose\", will be passed to user space.
251 12:27:28.327220 <6>[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
252 12:27:28.327637 <6>[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
253 12:27:28.328057 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
254 12:27:28.337226 <6>[ 0.000000] Memory: 870672K/1048576K available (16192K kernel code, 3714K rwdata, 8860K rodata, 7552K init, 609K bss, 145136K reserved, 32768K cma-reserved)
255 12:27:28.343134 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
256 12:27:28.349568 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
257 12:27:28.350070 <6>[ 0.000000] rcu: RCU event tracing is enabled.
258 12:27:28.350260 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=1.
259 12:27:28.350464 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
260 12:27:28.350653 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
261 12:27:28.350791 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
262 12:27:28.350937 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
263 12:27:28.351709 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
264 12:27:28.358204 <6>[ 0.000000] GICv3: 224 SPIs implemented
265 12:27:28.358634 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
266 12:27:28.359900 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
267 12:27:28.360346 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
268 12:27:28.361035 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000
269 12:27:28.365309 <6>[ 0.000000] ITS [mem 0x08080000-0x0809ffff]
270 12:27:28.366146 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Devices @42830000 (indirect, esz 8, psz 64K, shr 1)
271 12:27:28.366396 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Interrupt Collections @42840000 (flat, esz 8, psz 64K, shr 1)
272 12:27:28.367176 <6>[ 0.000000] GICv3: using LPI property table @0x0000000042850000
273 12:27:28.367633 <6>[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000042860000
274 12:27:28.368987 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
275 12:27:28.377085 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 62.50MHz (virt).
276 12:27:28.377556 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x1cd42e208c, max_idle_ns: 881590405314 ns
277 12:27:28.377982 <6>[ 0.000076] sched_clock: 57 bits at 63MHz, resolution 16ns, wraps every 4398046511096ns
278 12:27:28.395055 <6>[ 0.014486] Console: colour dummy device 80x25
279 12:27:28.399103 <6>[ 0.020477] Calibrating delay loop (skipped), value calculated using timer frequency.. 125.00 BogoMIPS (lpj=250000)
280 12:27:28.399283 <6>[ 0.021387] pid_max: default: 32768 minimum: 301
281 12:27:28.400682 <6>[ 0.022761] LSM: Security Framework initializing
282 12:27:28.404913 <6>[ 0.026953] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
283 12:27:28.405041 <6>[ 0.027173] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
284 12:27:28.437214 <4>[ 0.059319] cacheinfo: Unable to detect cache hierarchy for CPU 0
285 12:27:28.443188 <6>[ 0.065385] cblist_init_generic: Setting adjustable number of callback queues.
286 12:27:28.443566 <6>[ 0.065684] cblist_init_generic: Setting shift to 0 and lim to 1.
287 12:27:28.444276 <6>[ 0.066314] cblist_init_generic: Setting shift to 0 and lim to 1.
288 12:27:28.445921 <6>[ 0.068168] rcu: Hierarchical SRCU implementation.
289 12:27:28.446410 <6>[ 0.068339] rcu: Max phase no-delay instances is 1000.
290 12:27:28.451061 <6>[ 0.073290] Platform MSI: its@8080000 domain created
291 12:27:28.452013 <6>[ 0.073906] PCI/MSI: /intc@8000000/its@8080000 domain created
292 12:27:28.452365 <6>[ 0.074586] fsl-mc MSI: its@8080000 domain created
293 12:27:28.456072 <6>[ 0.078129] EFI services will not be available.
294 12:27:28.457101 <6>[ 0.079162] smp: Bringing up secondary CPUs ...
295 12:27:28.457220 <6>[ 0.079368] smp: Brought up 1 node, 1 CPU
296 12:27:28.457328 <6>[ 0.079481] SMP: Total of 1 processors activated.
297 12:27:28.457924 <6>[ 0.079917] CPU features: detected: Branch Target Identification
298 12:27:28.458046 <6>[ 0.080172] CPU features: detected: 32-bit EL0 Support
299 12:27:28.458762 <6>[ 0.080808] CPU features: detected: 32-bit EL1 Support
300 12:27:28.458864 <6>[ 0.080940] CPU features: detected: ARMv8.4 Translation Table Level
301 12:27:28.459197 <6>[ 0.081161] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
302 12:27:28.459309 <6>[ 0.081472] CPU features: detected: Common not Private translations
303 12:27:28.459412 <6>[ 0.081638] CPU features: detected: CRC32 instructions
304 12:27:28.459744 <6>[ 0.081805] CPU features: detected: E0PD
305 12:27:28.459868 <6>[ 0.082033] CPU features: detected: Generic authentication (IMP DEF algorithm)
306 12:27:28.460195 <6>[ 0.082240] CPU features: detected: RCpc load-acquire (LDAPR)
307 12:27:28.460311 <6>[ 0.082439] CPU features: detected: LSE atomic instructions
308 12:27:28.460630 <6>[ 0.082611] CPU features: detected: Privileged Access Never
309 12:27:28.460732 <6>[ 0.082826] CPU features: detected: RAS Extension Support
310 12:27:28.460843 <6>[ 0.083000] CPU features: detected: Random Number Generator
311 12:27:28.461212 <6>[ 0.083203] CPU features: detected: Speculation barrier (SB)
312 12:27:28.461325 <6>[ 0.083396] CPU features: detected: Stage-2 Force Write-Back
313 12:27:28.461429 <6>[ 0.083571] CPU features: detected: TLB range maintenance instructions
314 12:27:28.461907 <6>[ 0.083854] CPU features: detected: Scalable Matrix Extension
315 12:27:28.462076 <6>[ 0.084077] CPU features: detected: FA64
316 12:27:28.462231 <6>[ 0.084216] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
317 12:27:28.462377 <6>[ 0.084573] CPU features: detected: Scalable Vector Extension
318 12:27:28.473658 <6>[ 0.093230] SVE: maximum available vector length 256 bytes per vector
319 12:27:28.474411 <6>[ 0.096433] SVE: default vector length 64 bytes per vector
320 12:27:28.476282 <6>[ 0.098272] SME: minimum available vector length 16 bytes per vector
321 12:27:28.476475 <6>[ 0.098481] SME: maximum available vector length 256 bytes per vector
322 12:27:28.476639 <6>[ 0.098642] SME: default vector length 32 bytes per vector
323 12:27:28.476851 <6>[ 0.099090] CPU: All CPU(s) started at EL1
324 12:27:28.477315 <6>[ 0.099475] alternatives: applying system-wide alternatives
325 12:27:28.529137 <6>[ 0.151220] devtmpfs: initialized
326 12:27:28.548785 <6>[ 0.170552] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
327 12:27:28.549091 <6>[ 0.171284] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
328 12:27:28.555095 <6>[ 0.177077] pinctrl core: initialized pinctrl subsystem
329 12:27:28.565968 <6>[ 0.187939] DMI not present or invalid.
330 12:27:28.574915 <6>[ 0.196850] NET: Registered PF_NETLINK/PF_ROUTE protocol family
331 12:27:28.586261 <6>[ 0.208059] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
332 12:27:28.586728 <6>[ 0.208880] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
333 12:27:28.587217 <6>[ 0.209340] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
334 12:27:28.587684 <6>[ 0.209840] audit: initializing netlink subsys (disabled)
335 12:27:28.592608 <5>[ 0.214530] audit: type=2000 audit(0.180:1): state=initialized audit_enabled=0 res=1
336 12:27:28.595515 <6>[ 0.217411] thermal_sys: Registered thermal governor 'step_wise'
337 12:27:28.596023 <6>[ 0.217483] thermal_sys: Registered thermal governor 'power_allocator'
338 12:27:28.596214 <6>[ 0.218123] cpuidle: using governor menu
339 12:27:28.597706 <6>[ 0.219718] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
340 12:27:28.598141 <6>[ 0.220281] ASID allocator initialised with 65536 entries
341 12:27:28.604129 <6>[ 0.226402] Serial: AMBA PL011 UART driver
342 12:27:28.654019 <6>[ 0.275921] 9000000.pl011: ttyAMA0 at MMIO 0x9000000 (irq = 13, base_baud = 0) is a PL011 rev1
343 12:27:28.655623 <6>[ 0.277498] printk: console [ttyAMA0] enabled
344 12:27:28.655736 <6>[ 0.277498] printk: console [ttyAMA0] enabled
345 12:27:28.655839 <6>[ 0.278042] printk: bootconsole [pl11] disabled
346 12:27:28.656148 <6>[ 0.278042] printk: bootconsole [pl11] disabled
347 12:27:28.666561 <6>[ 0.288827] KASLR enabled
348 12:27:28.697958 <6>[ 0.319925] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
349 12:27:28.698073 <6>[ 0.320138] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
350 12:27:28.698440 <6>[ 0.320373] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
351 12:27:28.698605 <6>[ 0.320576] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
352 12:27:28.698756 <6>[ 0.320788] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
353 12:27:28.699153 <6>[ 0.321050] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
354 12:27:28.699281 <6>[ 0.321312] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
355 12:27:28.699419 <6>[ 0.321540] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
356 12:27:28.711317 <6>[ 0.333506] ACPI: Interpreter disabled.
357 12:27:28.719997 <6>[ 0.342195] iommu: Default domain type: Translated
358 12:27:28.720384 <6>[ 0.342361] iommu: DMA domain TLB invalidation policy: strict mode
359 12:27:28.721994 <5>[ 0.344041] SCSI subsystem initialized
360 12:27:28.722928 <7>[ 0.344954] libata version 3.00 loaded.
361 12:27:28.724089 <6>[ 0.346310] usbcore: registered new interface driver usbfs
362 12:27:28.724745 <6>[ 0.346723] usbcore: registered new interface driver hub
363 12:27:28.725151 <6>[ 0.347101] usbcore: registered new device driver usb
364 12:27:28.728298 <6>[ 0.350164] pps_core: LinuxPPS API ver. 1 registered
365 12:27:28.728577 <6>[ 0.350331] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
366 12:27:28.728739 <6>[ 0.350781] PTP clock support registered
367 12:27:28.729196 <6>[ 0.351418] EDAC MC: Ver: 3.0.0
368 12:27:28.734991 <6>[ 0.356962] FPGA manager framework
369 12:27:28.735860 <6>[ 0.357832] Advanced Linux Sound Architecture Driver Initialized.
370 12:27:28.744636 <6>[ 0.366858] vgaarb: loaded
371 12:27:28.748835 <6>[ 0.370789] clocksource: Switched to clocksource arch_sys_counter
372 12:27:28.749788 <5>[ 0.372026] VFS: Disk quotas dquot_6.6.0
373 12:27:28.750244 <6>[ 0.372333] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
374 12:27:28.753480 <6>[ 0.375721] pnp: PnP ACPI: disabled
375 12:27:28.771243 <6>[ 0.393453] NET: Registered PF_INET protocol family
376 12:27:28.773763 <6>[ 0.395683] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
377 12:27:28.778586 <6>[ 0.400528] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
378 12:27:28.778802 <6>[ 0.400801] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
379 12:27:28.779001 <6>[ 0.401093] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
380 12:27:28.779438 <6>[ 0.401557] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear)
381 12:27:28.779898 <6>[ 0.402121] TCP: Hash tables configured (established 8192 bind 8192)
382 12:27:28.781562 <6>[ 0.403590] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
383 12:27:28.781770 <6>[ 0.403964] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
384 12:27:28.783033 <6>[ 0.405060] NET: Registered PF_UNIX/PF_LOCAL protocol family
385 12:27:28.785228 <6>[ 0.407275] RPC: Registered named UNIX socket transport module.
386 12:27:28.785387 <6>[ 0.407496] RPC: Registered udp transport module.
387 12:27:28.785504 <6>[ 0.407664] RPC: Registered tcp transport module.
388 12:27:28.785844 <6>[ 0.407831] RPC: Registered tcp NFSv4.1 backchannel transport module.
389 12:27:28.785938 <6>[ 0.408132] PCI: CLS 0 bytes, default 64
390 12:27:28.790474 <6>[ 0.412549] Unpacking initramfs...
391 12:27:28.796909 <6>[ 0.418956] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
392 12:27:28.797643 <6>[ 0.419716] kvm [1]: HYP mode not available
393 12:27:28.806556 <5>[ 0.428619] Initialise system trusted keyrings
394 12:27:28.813350 <6>[ 0.435401] workingset: timestamp_bits=42 max_order=18 bucket_order=0
395 12:27:28.848699 <6>[ 0.470726] squashfs: version 4.0 (2009/01/31) Phillip Lougher
396 12:27:28.853621 <5>[ 0.475832] NFS: Registering the id_resolver key type
397 12:27:28.854075 <5>[ 0.476212] Key type id_resolver registered
398 12:27:28.854267 <5>[ 0.476369] Key type id_legacy registered
399 12:27:28.854699 <6>[ 0.476841] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
400 12:27:28.855201 <6>[ 0.477120] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
401 12:27:28.856829 <6>[ 0.478808] 9p: Installing v9fs 9p2000 file system support
402 12:27:28.922328 <5>[ 0.544476] Key type asymmetric registered
403 12:27:28.922802 <5>[ 0.544701] Asymmetric key parser 'x509' registered
404 12:27:28.923368 <6>[ 0.545269] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
405 12:27:28.923544 <6>[ 0.545600] io scheduler mq-deadline registered
406 12:27:28.923703 <6>[ 0.545809] io scheduler kyber registered
407 12:27:28.988906 <6>[ 0.611006] pl061_gpio 9030000.pl061: PL061 GPIO chip registered
408 12:27:28.999477 <6>[ 0.621440] pci-host-generic 4010000000.pcie: host bridge /pcie@10000000 ranges:
409 12:27:29.008674 <6>[ 0.622477] pci-host-generic 4010000000.pcie: IO 0x003eff0000..0x003effffff -> 0x0000000000
410 12:27:29.009209 <6>[ 0.631285] pci-host-generic 4010000000.pcie: MEM 0x0010000000..0x003efeffff -> 0x0010000000
411 12:27:29.009513 <6>[ 0.631604] pci-host-generic 4010000000.pcie: MEM 0x8000000000..0xffffffffff -> 0x8000000000
412 12:27:29.010524 <4>[ 0.632474] pci-host-generic 4010000000.pcie: Memory resource size exceeds max for 32 bits
413 12:27:29.011383 <6>[ 0.633182] pci-host-generic 4010000000.pcie: ECAM at [mem 0x4010000000-0x401fffffff] for [bus 00-ff]
414 12:27:29.016790 <6>[ 0.638831] pci-host-generic 4010000000.pcie: PCI host bridge to bus 0000:00
415 12:27:29.017008 <6>[ 0.639253] pci_bus 0000:00: root bus resource [bus 00-ff]
416 12:27:29.017480 <6>[ 0.639469] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
417 12:27:29.017712 <6>[ 0.639712] pci_bus 0000:00: root bus resource [mem 0x10000000-0x3efeffff]
418 12:27:29.017876 <6>[ 0.639920] pci_bus 0000:00: root bus resource [mem 0x8000000000-0xffffffffff]
419 12:27:29.019442 <6>[ 0.641448] pci 0000:00:00.0: [1b36:0008] type 00 class 0x060000
420 12:27:29.026679 <6>[ 0.648838] pci 0000:00:01.0: [1af4:1000] type 00 class 0x020000
421 12:27:29.027081 <6>[ 0.649261] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x001f]
422 12:27:29.027443 <6>[ 0.649477] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x00000fff]
423 12:27:29.027955 <6>[ 0.649774] pci 0000:00:01.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
424 12:27:29.028142 <6>[ 0.650083] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
425 12:27:29.032632 <6>[ 0.654844] pci 0000:00:02.0: [1af4:1001] type 00 class 0x010000
426 12:27:29.033109 <6>[ 0.655015] pci 0000:00:02.0: reg 0x10: [io 0x0000-0x007f]
427 12:27:29.033278 <6>[ 0.655205] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x00000fff]
428 12:27:29.033464 <6>[ 0.655433] pci 0000:00:02.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
429 12:27:29.036224 <6>[ 0.658181] pci 0000:00:01.0: BAR 6: assigned [mem 0x10000000-0x1003ffff pref]
430 12:27:29.040822 <6>[ 0.662773] pci 0000:00:01.0: BAR 4: assigned [mem 0x8000000000-0x8000003fff 64bit pref]
431 12:27:29.041075 <6>[ 0.663117] pci 0000:00:02.0: BAR 4: assigned [mem 0x8000004000-0x8000007fff 64bit pref]
432 12:27:29.041340 <6>[ 0.663419] pci 0000:00:01.0: BAR 1: assigned [mem 0x10040000-0x10040fff]
433 12:27:29.041559 <6>[ 0.663675] pci 0000:00:02.0: BAR 1: assigned [mem 0x10041000-0x10041fff]
434 12:27:29.041766 <6>[ 0.663885] pci 0000:00:02.0: BAR 0: assigned [io 0x1000-0x107f]
435 12:27:29.041954 <6>[ 0.664092] pci 0000:00:01.0: BAR 0: assigned [io 0x1080-0x109f]
436 12:27:29.053601 <6>[ 0.675809] EINJ: ACPI disabled.
437 12:27:29.142060 <6>[ 0.764184] virtio-pci 0000:00:01.0: enabling device (0000 -> 0003)
438 12:27:29.149113 <6>[ 0.771129] virtio-pci 0000:00:02.0: enabling device (0000 -> 0003)
439 12:27:29.178253 <6>[ 0.800202] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
440 12:27:29.192839 <6>[ 0.815004] SuperH (H)SCI(F) driver initialized
441 12:27:29.194443 <6>[ 0.816445] msm_serial: driver initialized
442 12:27:29.203097 <4>[ 0.825065] cacheinfo: Unable to detect cache hierarchy for CPU 0
443 12:27:29.234495 <6>[ 0.856666] loop: module loaded
444 12:27:29.235651 <6>[ 0.857655] virtio_blk virtio1: 1/0/0 default/read/poll queues
445 12:27:29.252180 <5>[ 0.874090] virtio_blk virtio1: [vda] 1048576 512-byte logical blocks (537 MB/512 MiB)
446 12:27:29.282366 <6>[ 0.904558] megasas: 07.719.03.00-rc1
447 12:27:29.296689 <5>[ 0.918621] physmap-flash 0.flash: physmap platform flash device: [mem 0x00000000-0x03ffffff]
448 12:27:29.298282 <6>[ 0.920238] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
449 12:27:29.298790 <6>[ 0.920932] Intel/Sharp Extended Query Table at 0x0031
450 12:27:29.299717 <6>[ 0.921708] Using buffer write method
451 12:27:29.300018 <7>[ 0.922131] erase region 0: offset=0x0,size=0x40000,blocks=256
452 12:27:29.308635 <5>[ 0.930636] physmap-flash 0.flash: physmap platform flash device: [mem 0x04000000-0x07ffffff]
453 12:27:29.309438 <6>[ 0.931341] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
454 12:27:29.309557 <6>[ 0.931649] Intel/Sharp Extended Query Table at 0x0031
455 12:27:29.310402 <6>[ 0.932366] Using buffer write method
456 12:27:29.310589 <7>[ 0.932515] erase region 0: offset=0x0,size=0x40000,blocks=256
457 12:27:29.310779 <5>[ 0.932738] Concatenating MTD devices:
458 12:27:29.310919 <5>[ 0.932880] (0): \"0.flash\"
459 12:27:29.311039 <5>[ 0.932985] (1): \"0.flash\"
460 12:27:29.311179 <5>[ 0.933072] into device \"0.flash\"
461 12:27:34.038230 <6>[ 5.660250] Freeing initrd memory: 86888K
462 12:27:34.150692 <6>[ 5.772766] tun: Universal TUN/TAP device driver, 1.6
463 12:27:34.160692 <6>[ 5.782732] thunder_xcv, ver 1.0
464 12:27:34.161314 <6>[ 5.782960] thunder_bgx, ver 1.0
465 12:27:34.161519 <6>[ 5.783194] nicpf, ver 1.0
466 12:27:34.164596 <6>[ 5.786444] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
467 12:27:34.164791 <6>[ 5.786734] hns3: Copyright (c) 2017 Huawei Corporation.
468 12:27:34.165010 <6>[ 5.787109] hclge is initializing
469 12:27:34.165278 <6>[ 5.787328] e1000: Intel(R) PRO/1000 Network Driver
470 12:27:34.165492 <6>[ 5.787453] e1000: Copyright (c) 1999-2006 Intel Corporation.
471 12:27:34.165761 <6>[ 5.787694] e1000e: Intel(R) PRO/1000 Network Driver
472 12:27:34.166035 <6>[ 5.787826] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
473 12:27:34.166227 <6>[ 5.788077] igb: Intel(R) Gigabit Ethernet Network Driver
474 12:27:34.166416 <6>[ 5.788218] igb: Copyright (c) 2007-2014 Intel Corporation.
475 12:27:34.166583 <6>[ 5.788431] igbvf: Intel(R) Gigabit Virtual Function Network Driver
476 12:27:34.166711 <6>[ 5.788567] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
477 12:27:34.167326 <6>[ 5.789485] sky2: driver version 1.30
478 12:27:34.170444 <6>[ 5.792400] VFIO - User Level meta-driver version: 0.3
479 12:27:34.179471 <6>[ 5.801437] usbcore: registered new interface driver usb-storage
480 12:27:34.188466 <6>[ 5.810679] rtc-pl031 9010000.pl031: registered as rtc0
481 12:27:34.189687 <6>[ 5.811397] rtc-pl031 9010000.pl031: setting system clock to 2023-06-06T12:27:34 UTC (1686054454)
482 12:27:34.191452 <6>[ 5.813452] i2c_dev: i2c /dev entries driver
483 12:27:34.207158 <6>[ 5.829326] sdhci: Secure Digital Host Controller Interface driver
484 12:27:34.207593 <6>[ 5.829476] sdhci: Copyright(c) Pierre Ossman
485 12:27:34.209186 <6>[ 5.831384] Synopsys Designware Multimedia Card Interface Driver
486 12:27:34.211896 <6>[ 5.833945] sdhci-pltfm: SDHCI platform and OF driver helper
487 12:27:34.216717 <6>[ 5.838928] ledtrig-cpu: registered to indicate activity on CPUs
488 12:27:34.222372 <6>[ 5.844619] usbcore: registered new interface driver usbhid
489 12:27:34.222725 <6>[ 5.844755] usbhid: USB HID core driver
490 12:27:34.239131 <6>[ 5.861331] NET: Registered PF_PACKET protocol family
491 12:27:34.240216 <6>[ 5.862442] 9pnet: Installing 9P2000 support
492 12:27:34.240737 <5>[ 5.863013] Key type dns_resolver registered
493 12:27:34.242001 <6>[ 5.864281] registered taskstats version 1
494 12:27:34.242599 <5>[ 5.864636] Loading compiled-in X.509 certificates
495 12:27:34.263322 <6>[ 5.885260] input: gpio-keys as /devices/platform/gpio-keys/input/input0
496 12:27:34.270210 <6>[ 5.892447] ALSA device list:
497 12:27:34.270628 <6>[ 5.892596] No soundcards found.
498 12:27:34.273186 <6>[ 5.895246] uart-pl011 9000000.pl011: no DMA platform data
499 12:27:34.327123 <6>[ 5.949215] Freeing unused kernel memory: 7552K
500 12:27:34.327896 <6>[ 5.950137] Run /init as init process
501 12:27:34.328380 <7>[ 5.950277] with arguments:
502 12:27:34.328539 <7>[ 5.950380] /init
503 12:27:34.328670 <7>[ 5.950468] verbose
504 12:27:34.328791 <7>[ 5.950661] with environment:
505 12:27:34.328935 <7>[ 5.950763] HOME=/
506 12:27:34.329065 <7>[ 5.950831] TERM=linux
507 12:27:34.462568 <30>[ 6.084269] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
508 12:27:34.463396 <31>[ 6.085542] systemd[1]: No virtualization found in DMI
509 12:27:34.465029 <31>[ 6.086861] systemd[1]: UML virtualization not found in /proc/cpuinfo.
510 12:27:34.465241 <31>[ 6.087252] systemd[1]: No virtualization found in CPUID
511 12:27:34.465518 <31>[ 6.087607] systemd[1]: Virtualization XEN not found, /proc/xen does not exist
512 12:27:34.466902 <31>[ 6.088822] systemd[1]: Virtualization QEMU: \"fw-cfg\" present in /proc/device-tree/fw-cfg@9020000
513 12:27:34.467206 <31>[ 6.089199] systemd[1]: Found VM virtualization qemu
514 12:27:34.467357 <30>[ 6.089456] systemd[1]: Detected virtualization qemu.
515 12:27:34.467539 <30>[ 6.089758] systemd[1]: Detected architecture arm64.
516 12:27:34.468017 <31>[ 6.090136] systemd[1]: Detected initialized system, this is not the first boot.
517 12:27:34.472174
518 12:27:34.472621 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
519 12:27:34.472781
520 12:27:34.474781 <30>[ 6.096779] systemd[1]: Set hostname to <debian-bullseye-arm64>.
521 12:27:34.493949 <31>[ 6.115870] systemd[1]: Successfully added address 127.0.0.1 to loopback interface
522 12:27:34.495287 <31>[ 6.117201] systemd[1]: Failed to add address ::1 to loopback interface: Operation not supported
523 12:27:34.495508 <31>[ 6.117652] systemd[1]: Successfully brought loopback interface up
524 12:27:34.500053 <31>[ 6.122240] systemd[1]: Setting 'fs/file-max' to '9223372036854775807'.
525 12:27:34.512326 <31>[ 6.134282] systemd[1]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
526 12:27:34.512783 <31>[ 6.134828] systemd[1]: Unified cgroup hierarchy is located at /sys/fs/cgroup.
527 12:27:34.556158 <31>[ 6.177999] systemd[1]: Got EBADF when using BPF_F_ALLOW_MULTI, which indicates it is supported. Yay!
528 12:27:34.557543 <31>[ 6.179740] systemd[1]: Controller 'cpu' supported: yes
529 12:27:34.557906 <31>[ 6.179959] systemd[1]: Controller 'cpuacct' supported: no
530 12:27:34.558031 <31>[ 6.180193] systemd[1]: Controller 'cpuset' supported: yes
531 12:27:34.558392 <31>[ 6.180397] systemd[1]: Controller 'io' supported: yes
532 12:27:34.558597 <31>[ 6.180649] systemd[1]: Controller 'blkio' supported: no
533 12:27:34.558772 <31>[ 6.180898] systemd[1]: Controller 'memory' supported: yes
534 12:27:34.559167 <31>[ 6.181176] systemd[1]: Controller 'devices' supported: no
535 12:27:34.559332 <31>[ 6.181430] systemd[1]: Controller 'pids' supported: yes
536 12:27:34.559541 <31>[ 6.181670] systemd[1]: Controller 'bpf-firewall' supported: yes
537 12:27:34.559893 <31>[ 6.181978] systemd[1]: Controller 'bpf-devices' supported: yes
538 12:27:34.561497 <31>[ 6.183561] systemd[1]: Set up TFD_TIMER_CANCEL_ON_SET timerfd.
539 12:27:34.561916 <31>[ 6.184035] systemd[1]: Failed to stat /etc/localtime, ignoring: No such file or directory
540 12:27:34.562632 <31>[ 6.184656] systemd[1]: /etc/localtime doesn't exist yet, watching /etc instead.
541 12:27:34.570467 <31>[ 6.192320] systemd[1]: Enabling (yes) showing of status (commandline).
542 12:27:34.578297 <31>[ 6.200103] systemd[1]: Successfully forked off '(sd-executor)' as PID 94.
543 12:27:34.587802 <31>[ 6.209704] systemd[94]: Successfully forked off '(direxec)' as PID 95.
544 12:27:34.590656 <31>[ 6.212692] systemd[94]: Successfully forked off '(direxec)' as PID 96.
545 12:27:34.601035 <31>[ 6.223008] systemd[94]: Successfully forked off '(direxec)' as PID 97.
546 12:27:34.603120 <31>[ 6.225016] systemd[94]: Successfully forked off '(direxec)' as PID 98.
547 12:27:34.621468 <31>[ 6.243405] systemd[94]: Successfully forked off '(direxec)' as PID 99.
548 12:27:34.765858 <31>[ 6.387714] systemd-bless-boot-generator[95]: Skipping generator, not an EFI boot.
549 12:27:34.771541 <31>[ 6.393452] systemd-fstab-generator[96]: Parsing /etc/fstab...
550 12:27:34.781031 <31>[ 6.402911] systemd-getty-generator[97]: Automatically adding serial getty for /dev/ttyAMA0.
551 12:27:34.782610 <31>[ 6.404619] systemd-getty-generator[97]: SELinux enabled state cached to: disabled
552 12:27:34.786264 <31>[ 6.407983] systemd-fstab-generator[96]: Found entry what=/dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76 where=/ type=ext4 makefs=no growfs=no noauto=no nofail=no
553 12:27:34.797537 <31>[ 6.419535] systemd[94]: /usr/lib/systemd/system-generators/systemd-veritysetup-generator succeeded.
554 12:27:34.798646 <31>[ 6.420437] systemd-fstab-generator[96]: Checking was requested for /dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76, but fsck.ext4 does not exist.
555 12:27:34.802939 <31>[ 6.424941] systemd-fstab-generator[96]: SELinux enabled state cached to: disabled
556 12:27:34.808215 <31>[ 6.430182] systemd[94]: /usr/lib/systemd/system-generators/systemd-fstab-generator succeeded.
557 12:27:34.808762 <31>[ 6.430872] systemd[94]: /usr/lib/systemd/system-generators/systemd-run-generator succeeded.
558 12:27:34.809434 <31>[ 6.431293] systemd[94]: /usr/lib/systemd/system-generators/systemd-getty-generator succeeded.
559 12:27:34.809679 <31>[ 6.431650] systemd[94]: /usr/lib/systemd/system-generators/systemd-bless-boot-generator succeeded.
560 12:27:34.812222 <31>[ 6.434237] systemd[1]: (sd-executor) succeeded.
561 12:27:34.814268 <31>[ 6.436311] systemd[1]: Looking for unit files in (higher priority first):
562 12:27:34.814489 <31>[ 6.436554] systemd[1]: /etc/systemd/system.control
563 12:27:34.814683 <31>[ 6.436684] systemd[1]: /run/systemd/system.control
564 12:27:34.814931 <31>[ 6.436856] systemd[1]: /run/systemd/transient
565 12:27:34.815083 <31>[ 6.437023] systemd[1]: /run/systemd/generator.early
566 12:27:34.815264 <31>[ 6.437199] systemd[1]: /etc/systemd/system
567 12:27:34.815405 <31>[ 6.437358] systemd[1]: /etc/systemd/system.attached
568 12:27:34.815582 <31>[ 6.437534] systemd[1]: /run/systemd/system
569 12:27:34.815723 <31>[ 6.437669] systemd[1]: /run/systemd/system.attached
570 12:27:34.815899 <31>[ 6.437847] systemd[1]: /run/systemd/generator
571 12:27:34.816041 <31>[ 6.438012] systemd[1]: /usr/local/lib/systemd/system
572 12:27:34.816216 <31>[ 6.438165] systemd[1]: /lib/systemd/system
573 12:27:34.816378 <31>[ 6.438338] systemd[1]: /usr/lib/systemd/system
574 12:27:34.816832 <31>[ 6.438993] systemd[1]: /run/systemd/generator.late
575 12:27:34.853425 <31>[ 6.475381] systemd[1]: Modification times have changed, need to update cache.
576 12:27:34.855173 <31>[ 6.476982] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.network1.service → systemd-networkd.service
577 12:27:34.856056 <31>[ 6.478022] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.timesync1.service → systemd-timesyncd.service
578 12:27:34.857314 <31>[ 6.479270] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.resolve1.service → systemd-resolved.service
579 12:27:34.858317 <31>[ 6.480316] systemd[1]: unit_file_build_name_map: normal unit file: /run/systemd/generator/-.mount
580 12:27:34.859168 <31>[ 6.481100] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.service
581 12:27:34.859598 <31>[ 6.481436] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/console-getty.service
582 12:27:34.859719 <31>[ 6.481764] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.timer
583 12:27:34.860071 <31>[ 6.482092] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.path
584 12:27:34.860432 <31>[ 6.482415] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.service
585 12:27:34.861039 <31>[ 6.483101] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/poweroff.target
586 12:27:34.861398 <31>[ 6.483527] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-pre.target
587 12:27:34.862210 <31>[ 6.484242] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel4.target → multi-user.target
588 12:27:34.862609 <31>[ 6.484557] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend-then-hibernate.target
589 12:27:34.862963 <31>[ 6.484909] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network.target
590 12:27:34.863531 <31>[ 6.485532] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel5.target → graphical.target
591 12:27:34.863872 <31>[ 6.485864] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.service
592 12:27:34.864312 <31>[ 6.486207] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp-runlevel.service
593 12:27:34.864824 <31>[ 6.486901] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-fs.target
594 12:27:34.865387 <31>[ 6.487253] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/slices.target
595 12:27:34.866184 <31>[ 6.487987] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/kmod.service → systemd-modules-load.service
596 12:27:34.866375 <31>[ 6.488360] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp.service
597 12:27:34.866837 <31>[ 6.488970] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel1.target → rescue.target
598 12:27:34.867333 <31>[ 6.489290] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup-pre.target
599 12:27:34.867543 <31>[ 6.489660] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-pre.target
600 12:27:34.868036 <31>[ 6.489994] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/machine.slice
601 12:27:34.868374 <31>[ 6.490391] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs-pre.target
602 12:27:34.869138 <31>[ 6.491060] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.service
603 12:27:34.869935 <31>[ 6.491811] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel3.target → multi-user.target
604 12:27:34.870616 <31>[ 6.492489] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.timedate1.service → systemd-timedated.service
605 12:27:34.870745 <31>[ 6.492896] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.service
606 12:27:34.871084 <31>[ 6.493196] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/reboot.target
607 12:27:34.871675 <31>[ 6.493657] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-audit.socket
608 12:27:34.872056 <31>[ 6.494036] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty@.service
609 12:27:34.872409 <31>[ 6.494326] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kexec.target
610 12:27:34.872775 <31>[ 6.494901] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-systemd\x2dcryptsetup.slice
611 12:27:34.873154 <31>[ 6.495229] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timedated.service
612 12:27:34.873518 <31>[ 6.495523] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-device.target
613 12:27:34.873854 <31>[ 6.495844] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-parse-etc.service
614 12:27:34.874021 <31>[ 6.496170] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd.target
615 12:27:34.874459 <31>[ 6.496443] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.timer
616 12:27:34.874867 <31>[ 6.496757] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-binfmt.service
617 12:27:34.874968 <31>[ 6.497034] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs-pre.target
618 12:27:34.875327 <31>[ 6.497273] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.service
619 12:27:34.875664 <31>[ 6.497580] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/paths.target
620 12:27:34.875771 <31>[ 6.497900] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/modprobe@.service
621 12:27:34.876821 <31>[ 6.498803] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rc.service → /dev/null
622 12:27:34.877319 <31>[ 6.499239] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-static.service
623 12:27:34.877922 <31>[ 6.499968] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel2.target → multi-user.target
624 12:27:34.878344 <31>[ 6.500323] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-modules-load.service
625 12:27:34.878758 <31>[ 6.500837] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend.target
626 12:27:34.879148 <31>[ 6.501190] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-debug.mount
627 12:27:34.879580 <31>[ 6.501570] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysusers.service
628 12:27:34.880098 <31>[ 6.502206] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/default.target → graphical.target
629 12:27:34.880642 <31>[ 6.502712] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-poweroff.service
630 12:27:34.881123 <31>[ 6.503100] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.target
631 12:27:34.881309 <31>[ 6.503397] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysctl.service
632 12:27:34.881923 <31>[ 6.504054] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/procps.service → systemd-sysctl.service
633 12:27:34.882409 <31>[ 6.504323] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-time-wait-sync.service
634 12:27:34.882574 <31>[ 6.504591] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user@.service
635 12:27:34.882974 <31>[ 6.505102] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/udev.service → systemd-udevd.service
636 12:27:34.883364 <31>[ 6.505356] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-cleanup.service
637 12:27:34.883477 <31>[ 6.505631] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/nss-lookup.target
638 12:27:34.883829 <31>[ 6.505870] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/umount.target
639 12:27:34.884211 <31>[ 6.506131] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-udevadm-cleanup-db.service
640 12:27:34.884322 <31>[ 6.506391] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-tracing.mount
641 12:27:34.884904 <31>[ 6.506924] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.socket
642 12:27:34.885020 <31>[ 6.507191] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timesyncd.service
643 12:27:34.885368 <31>[ 6.507457] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.socket
644 12:27:34.885725 <31>[ 6.507705] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/printer.target
645 12:27:34.885834 <31>[ 6.507946] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-online.target
646 12:27:34.886189 <31>[ 6.508193] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/usb-gadget.target
647 12:27:34.886316 <31>[ 6.508432] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hybrid-sleep.service
648 12:27:34.886672 <31>[ 6.508777] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-reboot.service
649 12:27:34.887050 <31>[ 6.509057] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/quotaon.service
650 12:27:34.887665 <31>[ 6.509718] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/bluetooth.target
651 12:27:34.888029 <31>[ 6.510011] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rescue.service
652 12:27:34.888411 <31>[ 6.510352] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-backlight@.service
653 12:27:34.889360 <31>[ 6.511280] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks-early.service → /dev/null
654 12:27:34.889581 <31>[ 6.511673] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-hugepages.mount
655 12:27:34.890205 <31>[ 6.511977] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-cryptsetup.target
656 12:27:34.890392 <31>[ 6.512336] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-pstore.service
657 12:27:34.890890 <31>[ 6.512806] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/x11-common.service → /dev/null
658 12:27:34.891591 <31>[ 6.513465] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.locale1.service → systemd-localed.service
659 12:27:34.892110 <31>[ 6.513878] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/timers.target
660 12:27:34.892236 <31>[ 6.514218] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.automount
661 12:27:34.892960 <31>[ 6.514927] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.service
662 12:27:34.893384 <31>[ 6.515357] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.socket
663 12:27:34.893675 <31>[ 6.515737] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user.slice
664 12:27:34.893957 <31>[ 6.516027] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup.service
665 12:27:34.894440 <31>[ 6.516403] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-fsck-root.service
666 12:27:34.894959 <31>[ 6.516793] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-quotacheck.service
667 12:27:34.895160 <31>[ 6.517132] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-kexec.service
668 12:27:34.895344 <31>[ 6.517429] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/graphical.target
669 12:27:34.895600 <31>[ 6.517714] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.timer
670 12:27:34.896168 <31>[ 6.518055] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/exit.target
671 12:27:34.896375 <31>[ 6.518340] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-fs.target
672 12:27:34.896878 <31>[ 6.518901] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-system-token.service
673 12:27:34.897400 <31>[ 6.519397] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-varlink@.socket
674 12:27:34.897615 <31>[ 6.519673] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd.service
675 12:27:34.897837 <31>[ 6.519954] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rpcbind.target
676 12:27:34.898774 <31>[ 6.520693] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.hostname1.service → systemd-hostnamed.service
677 12:27:34.899011 <31>[ 6.521072] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/syslog.socket
678 12:27:34.899581 <31>[ 6.521376] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-user-sessions.service
679 12:27:34.899795 <31>[ 6.521760] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-volatile-root.service
680 12:27:34.900307 <31>[ 6.522196] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user-runtime-dir@.service
681 12:27:34.900898 <31>[ 6.522904] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kmod-static-nodes.service
682 12:27:34.901465 <31>[ 6.523309] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-logind.service
683 12:27:34.901998 <31>[ 6.523710] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-control.socket
684 12:27:34.902198 <31>[ 6.524021] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-bless-boot.service
685 12:27:34.902388 <31>[ 6.524326] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd.service
686 12:27:34.902586 <31>[ 6.524659] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journal-flush.service
687 12:27:34.903039 <31>[ 6.525001] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-pre.target
688 12:27:34.903163 <31>[ 6.525287] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty.target
689 12:27:34.903777 <31>[ 6.525604] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-network-generator.service
690 12:27:34.903910 <31>[ 6.525975] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update.target
691 12:27:34.904393 <31>[ 6.526342] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/multi-user.target
692 12:27:34.904634 <31>[ 6.526766] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend.service
693 12:27:34.905111 <31>[ 6.527078] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.service
694 12:27:34.905316 <31>[ 6.527406] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-cleanup.service
695 12:27:34.905819 <31>[ 6.527739] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/basic.target
696 12:27:34.906012 <31>[ 6.528062] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.target
697 12:27:34.906191 <31>[ 6.528335] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend-then-hibernate.service
698 12:27:34.906706 <31>[ 6.528613] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate-resume@.service
699 12:27:34.906895 <31>[ 6.528891] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-kernel.socket
700 12:27:34.907434 <31>[ 6.529230] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-dev-log.socket
701 12:27:34.907649 <31>[ 6.529602] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-machine-id-commit.service
702 12:27:34.907861 <31>[ 6.529904] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/serial-getty@.service
703 12:27:34.908333 <31>[ 6.530285] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.service
704 12:27:34.908583 <31>[ 6.530710] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_reap.service
705 12:27:34.909109 <31>[ 6.531048] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sockets.target
706 12:27:34.909641 <31>[ 6.531658] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks.service → /dev/null
707 12:27:34.910188 <31>[ 6.532093] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hybrid-sleep.target
708 12:27:34.910684 <31>[ 6.532767] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.login1.service → systemd-logind.service
709 12:27:34.911283 <31>[ 6.533123] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sleep.target
710 12:27:34.911456 <31>[ 6.533398] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate.service
711 12:27:34.911687 <31>[ 6.533698] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-halt.service
712 12:27:34.911914 <31>[ 6.533990] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/halt.target
713 12:27:34.912143 <31>[ 6.534255] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sigpwr.target
714 12:27:34.912555 <31>[ 6.534508] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup-dev.service
715 12:27:34.912952 <31>[ 6.535034] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sound.target
716 12:27:34.913186 <31>[ 6.535265] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-set.target
717 12:27:34.913849 <31>[ 6.535551] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-settle.service
718 12:27:34.914057 <31>[ 6.535976] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.socket
719 12:27:34.914583 <31>[ 6.536560] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/hwclock.service → /dev/null
720 12:27:34.915111 <31>[ 6.537057] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rcS.service → /dev/null
721 12:27:34.915554 <31>[ 6.537429] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hibernate.target
722 12:27:34.915673 <31>[ 6.537706] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-random-seed.service
723 12:27:34.916039 <31>[ 6.538031] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup.target
724 12:27:34.916420 <31>[ 6.538392] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/boot-complete.target
725 12:27:34.917098 <31>[ 6.538946] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/blockdev@.target
726 12:27:34.917511 <31>[ 6.539284] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd-wait-online.service
727 12:27:35.333632 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
728 12:27:35.340158 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
729 12:27:35.345874 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
730 12:27:35.350304 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
731 12:27:35.354500 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
732 12:27:35.356183 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
733 12:27:35.358720 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
734 12:27:35.359786 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
735 12:27:35.360861 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
736 12:27:35.361583 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
737 12:27:35.362388 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
738 12:27:35.366885 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
739 12:27:35.371491 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
740 12:27:35.374448 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
741 12:27:35.376941 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
742 12:27:35.379455 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
743 12:27:35.382460 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
744 12:27:35.384629 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
745 12:27:35.410626 Mounting [0;1;39mHuge Pages File System[0m...
746 12:27:35.446001 Mounting [0;1;39mPOSIX Message Queue File System[0m...
747 12:27:35.489887 Mounting [0;1;39mKernel Debug File System[0m...
748 12:27:35.530589 Starting [0;1;39mLoad Kernel Module configfs[0m...
749 12:27:35.570192 Starting [0;1;39mLoad Kernel Module drm[0m...
750 12:27:35.630195 Starting [0;1;39mJournal Service[0m...
751 12:27:35.662391 Starting [0;1;39mLoad Kernel Modules[0m...
752 12:27:35.694493 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
753 12:27:35.758045 Starting [0;1;39mColdplug All udev Devices[0m...
754 12:27:35.851285 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
755 12:27:35.870277 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
756 12:27:35.874570 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
757 12:27:35.929525 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
758 12:27:35.978836 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
759 12:27:36.007794 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
760 12:27:36.081982 Mounting [0;1;39mKernel Configuration File System[0m...
761 12:27:36.193904 Starting [0;1;39mApply Kernel Variables[0m...
762 12:27:36.271280 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
763 12:27:36.373531 <47>[ 7.995572] systemd-journald[105]: SELinux enabled state cached to: disabled
764 12:27:36.375328 <47>[ 7.997307] systemd-journald[105]: Auditing in kernel turned off.
765 12:27:36.405046 <47>[ 8.026913] systemd-journald[105]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
766 12:27:36.425444 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
767 12:27:36.429384 See 'systemctl status systemd-remount-fs.service' for details.
768 12:27:36.461397 <47>[ 8.083149] systemd-journald[105]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
769 12:27:36.464056 <47>[ 8.085837] systemd-journald[105]: Fixed min_use=3.8M max_use=19.4M max_size=2.4M min_size=512.0K keep_free=9.7M n_max_files=100
770 12:27:36.470167 <47>[ 8.092127] systemd-journald[105]: Reserving 333 entries in field hash table.
771 12:27:36.478632 Starting [0;1;39mLoad/Save Random Seed[0m...
772 12:27:36.504654 <47>[ 8.126442] systemd-journald[105]: Reserving 4437 entries in data hash table.
773 12:27:36.518666 <47>[ 8.140820] systemd-journald[105]: Vacuuming...
774 12:27:36.519466 <47>[ 8.141511] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
775 12:27:36.520122 <47>[ 8.142161] systemd-journald[105]: Flushing /dev/kmsg...
776 12:27:36.538630 Starting [0;1;39mCreate System Users[0m...
777 12:27:36.578821 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
778 12:27:36.697322 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
779 12:27:36.877567 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
780 12:27:36.922319 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
781 12:27:37.083501 <47>[ 8.705518] systemd-journald[105]: systemd-journald running as PID 105 for the system.
782 12:27:37.098145 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
783 12:27:37.112933 <47>[ 8.735045] systemd-journald[105]: Sent READY=1 notification.
784 12:27:37.113500 <47>[ 8.735576] systemd-journald[105]: Sent WATCHDOG=1 notification.
785 12:27:37.158302 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
786 12:27:37.161250 <47>[ 8.783165] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
787 12:27:37.178224 <47>[ 8.800035] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
788 12:27:37.197463 <47>[ 8.819195] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
789 12:27:37.199891 <47>[ 8.821929] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
790 12:27:37.207948 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
791 12:27:37.225761 <47>[ 8.847731] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
792 12:27:37.243084 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
793 12:27:37.244691 <47>[ 8.866469] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
794 12:27:37.249914 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
795 12:27:37.263073 <47>[ 8.884889] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
796 12:27:37.294906 <47>[ 8.916953] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
797 12:27:37.309533 <47>[ 8.931582] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
798 12:27:37.311604 <47>[ 8.933588] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
799 12:27:37.325913 <47>[ 8.947962] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
800 12:27:37.328049 <47>[ 8.950020] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
801 12:27:37.339746 <47>[ 8.961860] systemd-journald[105]: n/a: New incoming connection.
802 12:27:37.344845 <47>[ 8.966814] systemd-journald[105]: varlink-21: varlink: setting state idle-server
803 12:27:37.354821 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
804 12:27:37.370171 <47>[ 8.991960] systemd-journald[105]: varlink-21: New incoming message: {\"method\":\"io.systemd.Journal.FlushToVar\",\"parameters\":{}}
805 12:27:37.372132 <47>[ 8.993986] systemd-journald[105]: varlink-21: varlink: changing state idle-server → processing-method
806 12:27:37.372267 <46>[ 8.994348] systemd-journald[105]: Received client request to flush runtime journal.
807 12:27:37.382589 <47>[ 9.004358] systemd-journald[105]: Journal effective settings seal=yes keyed_hash=no compress=yes compress_threshold_bytes=512B
808 12:27:37.383208 <47>[ 9.005291] systemd-journald[105]: Vacuuming...
809 12:27:37.384030 <47>[ 9.005789] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
810 12:27:37.393783 <47>[ 9.015669] systemd-journald[105]: varlink-21: Sending message: {\"parameters\":{}}
811 12:27:37.394024 <47>[ 9.015994] systemd-journald[105]: varlink-21: varlink: changing state processing-method → processed-method
812 12:27:37.394440 <47>[ 9.016452] systemd-journald[105]: varlink-21: varlink: changing state processed-method → idle-server
813 12:27:37.410128 <47>[ 9.031823] systemd-journald[105]: varlink-21: varlink: changing state idle-server → pending-disconnect
814 12:27:37.410496 <47>[ 9.032235] systemd-journald[105]: varlink-21: varlink: changing state pending-disconnect → processing-disconnect
815 12:27:37.410682 <47>[ 9.032619] systemd-journald[105]: varlink-21: varlink: changing state processing-disconnect → disconnected
816 12:27:37.418570 <47>[ 9.040389] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
817 12:27:37.426916 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
818 12:27:37.438453 <47>[ 9.060216] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
819 12:27:37.446739 <47>[ 9.068593] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
820 12:27:37.487046 <47>[ 9.109100] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
821 12:27:37.490170 Starting [0;1;39mCreate Volatile Files and Directories[0m...
822 12:27:37.957069 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
823 12:27:38.046847 Starting [0;1;39mNetwork Service[0m...
824 12:27:38.076121 <47>[ 9.697876] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
825 12:27:38.081788 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
826 12:27:38.183903 Starting [0;1;39mNetwork Time Synchronization[0m...
827 12:27:38.203484 <47>[ 9.825269] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
828 12:27:38.250349 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
829 12:27:38.254444 <47>[ 9.876381] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
830 12:27:38.745807 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
831 12:27:40.006753 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
832 12:27:40.112993 <47>[ 11.714464] systemd-journald[105]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3329 of 4437 items, 2555904 file size, 767 bytes per hash table item), suggesting rotation.
833 12:27:40.113369 <47>[ 11.735276] systemd-journald[105]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
834 12:27:40.113596 <47>[ 11.735676] systemd-journald[105]: Rotating...
835 12:27:40.114621 <47>[ 11.736592] systemd-journald[105]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
836 12:27:40.116067 <47>[ 11.737946] systemd-journald[105]: Reserving 333 entries in field hash table.
837 12:27:40.143369 Starting [0;1;39mNetwork Name Resolution[0m...
838 12:27:40.180949 <47>[ 11.803048] systemd-journald[105]: Reserving 4437 entries in data hash table.
839 12:27:40.183978 <47>[ 11.806188] systemd-journald[105]: Vacuuming...
840 12:27:40.206367 <47>[ 11.828207] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
841 12:27:40.242775 <47>[ 11.864857] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
842 12:27:40.271101 <47>[ 11.892918] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
843 12:27:40.607541 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
844 12:27:40.610971 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
845 12:27:40.629970 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
846 12:27:41.795825 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
847 12:27:41.809321 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
848 12:27:41.834653 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
849 12:27:41.852753 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
850 12:27:41.859812 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
851 12:27:41.870989 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
852 12:27:41.899061 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
853 12:27:41.899774 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
854 12:27:41.911393 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
855 12:27:41.982836 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
856 12:27:42.001967 <47>[ 13.623762] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
857 12:27:42.173892 <47>[ 13.795890] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
858 12:27:42.175063 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
859 12:27:42.441582 Starting [0;1;39mUser Login Management[0m...
860 12:27:42.444044 <47>[ 14.065990] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
861 12:27:43.045077 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
862 12:27:43.047246 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
863 12:27:43.057942 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
864 12:27:43.130983 Starting [0;1;39mPermit User Sessions[0m...
865 12:27:43.159141 <47>[ 14.780934] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
866 12:27:43.266719 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
867 12:27:43.369822 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
868 12:27:43.483720 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
869 12:27:43.897815 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
870 12:27:46.155997 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyAMA0[0m.
871 12:27:46.242358 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyAMA0[0m.
872 12:27:46.274084 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
873 12:27:46.289431 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
874 12:27:46.303762 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
875 12:27:46.353581 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
876 12:27:46.363254 <47>[ 17.985175] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
877 12:27:46.560067 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
878 12:27:46.623477 <47>[ 18.245241] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
879 12:27:46.632916 <47>[ 18.254823] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
880 12:27:46.686209
881 12:27:46.686946 Debian GNU/Linux 11 debian-bullseye-arm64 ttyAMA0
882 12:27:46.687162
883 12:27:46.687388 debian-bullseye-arm64 login: root (automatic login)
884 12:27:46.687583
885 12:27:46.694906 <6>[ 18.317052] virtio_net virtio0 enp0s1: renamed from eth0
886 12:27:46.981657 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 12:10:19 UTC 2023 aarch64
887 12:27:46.982319
888 12:27:46.982694 The programs included with the Debian GNU/Linux system are free software;
889 12:27:46.982802 the exact distribution terms for each program are described in the
890 12:27:46.982890 individual files in /usr/share/doc/*/copyright.
891 12:27:46.982973
892 12:27:46.983067 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
893 12:27:46.983151 permitted by applicable law.
894 12:27:47.531911 <47>[ 19.153712] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
895 12:27:47.604430 <47>[ 19.226176] systemd-journald[105]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.1 (3330 of 4437 items, 2555904 file size, 767 bytes per hash table item), suggesting rotation.
896 12:27:47.616846 <47>[ 19.238718] systemd-journald[105]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
897 12:27:47.617093 <47>[ 19.239179] systemd-journald[105]: Rotating...
898 12:27:47.618732 <47>[ 19.240716] systemd-journald[105]: Reserving 333 entries in field hash table.
899 12:27:47.643502 <47>[ 19.265645] systemd-journald[105]: Reserving 4437 entries in data hash table.
900 12:27:47.654942 <47>[ 19.277145] systemd-journald[105]: Vacuuming...
901 12:27:47.656311 <47>[ 19.278305] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
902 12:27:47.851485 <47>[ 19.473566] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
903 12:27:49.616811 <47>[ 21.238855] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
904 12:27:49.936862 Matched prompt #10: / #
906 12:27:49.937420 Setting prompt string to ['/ #']
907 12:27:49.937602 end: 2.2.1 login-action (duration 00:00:22) [common]
909 12:27:49.938057 end: 2.2 auto-login-action (duration 00:00:24) [common]
910 12:27:49.938237 start: 2.3 expect-shell-connection (timeout 00:04:34) [common]
911 12:27:49.938388 Setting prompt string to ['/ #']
912 12:27:49.938524 Forcing a shell prompt, looking for ['/ #']
914 12:27:49.989072 / #
915 12:27:49.989267 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
916 12:27:49.989424 Waiting using forced prompt support (timeout 00:02:30)
917 12:27:49.991085
918 12:27:49.999536 end: 2.3 expect-shell-connection (duration 00:00:00) [common]
919 12:27:49.999653 start: 2.4 export-device-env (timeout 00:04:34) [common]
920 12:27:49.999748 end: 2.4 export-device-env (duration 00:00:00) [common]
921 12:27:49.999837 end: 2 boot-image-retry (duration 00:00:26) [common]
922 12:27:49.999928 start: 3 lava-test-retry (timeout 00:08:51) [common]
923 12:27:50.000010 start: 3.1 lava-test-shell (timeout 00:08:51) [common]
924 12:27:50.000085 Using namespace: common
926 12:27:50.100785 / # #
927 12:27:50.100947 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
928 12:27:50.101567 #
930 12:27:50.210701 / # mkdir /lava-568933
931 12:27:50.211745 mkdir /lava-568933
933 12:27:50.343162 / # mount /dev/disk/by-uuid/85525b52-42ec-46dd-b796-92508e7731e1 -t ext2 /lava-568933
934 12:27:50.344056 mount /dev/disk/by-uuid/85525b52-42ec-46dd-b796-92508e7731e1 -t ext2 /lava-568933
935 12:27:50.384927 <4>[ 22.006570] ext2 filesystem being mounted at /lava-568933 supports timestamps until 2038 (0x7fffffff)
937 12:27:50.526502 / # ls -la /lava-568933/bin/lava-test-runner
938 12:27:50.527608 ls -la /lava-568933/bin/lava-test-runner
939 12:27:50.571264 -rwxr-xr-x 1 root root 1039 Jun 6 12:26 /lava-568933/bin/lava-test-runner
940 12:27:50.583984 Using /lava-568933
942 12:27:50.685016 / # export SHELL=/bin/sh
943 12:27:50.686044 export SHELL=/bin/sh
945 12:27:50.795725 / # . /lava-568933/environment
946 12:27:50.796680 . /lava-568933/environment
948 12:27:50.909039 / # /lava-568933/bin/lava-test-runner /lava-568933/0
949 12:27:50.909361 Test shell timeout: 10s (minimum of the action and connection timeout)
950 12:27:50.910220 /lava-568933/bin/lava-test-runner /lava-568933/0
951 12:27:51.077222 + export TESTRUN_ID=0_timesync-off
952 12:27:51.077445 + cd /lava-568933/0/tests/0_timesync-off
953 12:27:51.079556 + cat uuid
954 12:27:51.088041 + UUID=568933_1.1.3.1
955 12:27:51.088325 + set +x
956 12:27:51.088945 Received signal: <STARTRUN> 0_timesync-off 568933_1.1.3.1
957 12:27:51.089045 Starting test lava.0_timesync-off (568933_1.1.3.1)
958 12:27:51.089165 Skipping test definition patterns.
959 12:27:51.089309 <LAVA_SIGNAL_STARTRUN 0_timesync-off 568933_1.1.3.1>
960 12:27:51.089405 + systemctl stop systemd-timesyncd
961 12:27:51.369680 + set +x
962 12:27:51.369903 <LAVA_SIGNAL_ENDRUN 0_timesync-off 568933_1.1.3.1>
963 12:27:51.370181 Received signal: <ENDRUN> 0_timesync-off 568933_1.1.3.1
964 12:27:51.370299 Ending use of test pattern.
965 12:27:51.370385 Ending test lava.0_timesync-off (568933_1.1.3.1), duration 0.28
967 12:27:51.419592 + export TESTRUN_ID=1_kselftest-arm64_qemu
968 12:27:51.419950 + cd /lava-568933/0/tests/1_kselftest-arm64_qemu
969 12:27:51.422367 + cat uuid
970 12:27:51.431076 + UUID=568933_1.1.3.5
971 12:27:51.431337 + set +x
972 12:27:51.431587 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64_qemu 568933_1.1.3.5>
973 12:27:51.431902 Received signal: <STARTRUN> 1_kselftest-arm64_qemu 568933_1.1.3.5
974 12:27:51.432018 Starting test lava.1_kselftest-arm64_qemu (568933_1.1.3.5)
975 12:27:51.432149 Skipping test definition patterns.
976 12:27:51.432317 + cd ./automated/linux/kselftest/
977 12:27:51.437942 + ./kselftest.sh -c arm64 -T -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig/gcc-10/kselftest.tar.xz -L -S /dev/null -b qemu_arm64-virt-gicv3 -g cip -e -p /opt/kselftests/mainline/ -n 1 -i 1
978 12:27:51.580654 INFO: install_deps skipped
979 12:27:51.616844 --2023-06-06 12:27:51-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1320-gc38e4a9845945/arm64/defconfig/gcc-10/kselftest.tar.xz
980 12:27:51.714953 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
981 12:27:51.925227 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
982 12:27:52.120229 HTTP request sent, awaiting response... 200 OK
983 12:27:52.123135 Length: 2860984 (2.7M) [application/octet-stream]
984 12:27:52.124605 Saving to: 'kselftest.tar.xz'
985 12:27:52.125907
986 12:27:53.406213 kselftest.tar.xz 0%[ ] 0 --.-KB/s kselftest.tar.xz 1%[ ] 50.15K 151KB/s kselftest.tar.xz 7%[> ] 219.84K 323KB/s kselftest.tar.xz 32%[=====> ] 898.59K 871KB/s kselftest.tar.xz 89%[================> ] 2.43M 1.97MB/s kselftest.tar.xz 100%[===================>] 2.73M 2.20MB/s in 1.2s
987 12:27:53.406605
988 12:27:53.409751 2023-06-06 12:27:53 (2.20 MB/s) - 'kselftest.tar.xz' saved [2860984/2860984]
989 12:27:53.410143
990 12:27:56.483448 skiplist:
991 12:27:56.483705 ========================================
992 12:27:56.484793 ========================================
993 12:27:56.538309 arm64:tags_test
994 12:27:56.538567 arm64:run_tags_test.sh
995 12:27:56.538664 arm64:fake_sigreturn_bad_magic
996 12:27:56.538962 arm64:fake_sigreturn_bad_size
997 12:27:56.539075 arm64:fake_sigreturn_bad_size_for_magic0
998 12:27:56.539167 arm64:fake_sigreturn_duplicated_fpsimd
999 12:27:56.539256 arm64:fake_sigreturn_misaligned_sp
1000 12:27:56.539344 arm64:fake_sigreturn_missing_fpsimd
1001 12:27:56.539432 arm64:fake_sigreturn_sme_change_vl
1002 12:27:56.539521 arm64:fake_sigreturn_sve_change_vl
1003 12:27:56.539626 arm64:mangle_pstate_invalid_compat_toggle
1004 12:27:56.539714 arm64:mangle_pstate_invalid_daif_bits
1005 12:27:56.539801 arm64:mangle_pstate_invalid_mode_el1h
1006 12:27:56.539889 arm64:mangle_pstate_invalid_mode_el1t
1007 12:27:56.539978 arm64:mangle_pstate_invalid_mode_el2h
1008 12:27:56.540068 arm64:mangle_pstate_invalid_mode_el2t
1009 12:27:56.540178 arm64:mangle_pstate_invalid_mode_el3h
1010 12:27:56.540272 arm64:mangle_pstate_invalid_mode_el3t
1011 12:27:56.540363 arm64:sme_trap_no_sm
1012 12:27:56.540452 arm64:sme_trap_non_streaming
1013 12:27:56.540542 arm64:sme_trap_za
1014 12:27:56.540633 arm64:sme_vl
1015 12:27:56.540742 arm64:ssve_regs
1016 12:27:56.540835 arm64:sve_regs
1017 12:27:56.540927 arm64:sve_vl
1018 12:27:56.541016 arm64:za_no_regs
1019 12:27:56.541107 arm64:za_regs
1020 12:27:56.541193 arm64:pac
1021 12:27:56.541279 arm64:fp-stress
1022 12:27:56.541366 arm64:sve-ptrace
1023 12:27:56.541451 arm64:sve-probe-vls
1024 12:27:56.541556 arm64:vec-syscfg
1025 12:27:56.541665 arm64:za-fork
1026 12:27:56.541754 arm64:za-ptrace
1027 12:27:56.541840 arm64:check_buffer_fill
1028 12:27:56.541927 arm64:check_child_memory
1029 12:27:56.542012 arm64:check_gcr_el1_cswitch
1030 12:27:56.542103 arm64:check_ksm_options
1031 12:27:56.542188 arm64:check_mmap_options
1032 12:27:56.542273 arm64:check_prctl
1033 12:27:56.542382 arm64:check_tags_inclusion
1034 12:27:56.542471 arm64:check_user_mem
1035 12:27:56.542557 arm64:btitest
1036 12:27:56.542643 arm64:nobtitest
1037 12:27:56.542728 arm64:hwcap
1038 12:27:56.542812 arm64:ptrace
1039 12:27:56.542898 arm64:syscall-abi
1040 12:27:56.542979 arm64:tpidr2
1041 12:27:56.554112 ============== Tests to run ===============
1042 12:27:56.558252 arm64:tags_test
1043 12:27:56.558560 arm64:run_tags_test.sh
1044 12:27:56.558662 arm64:fake_sigreturn_bad_magic
1045 12:27:56.558758 arm64:fake_sigreturn_bad_size
1046 12:27:56.558867 arm64:fake_sigreturn_bad_size_for_magic0
1047 12:27:56.558958 arm64:fake_sigreturn_duplicated_fpsimd
1048 12:27:56.559046 arm64:fake_sigreturn_misaligned_sp
1049 12:27:56.559150 arm64:fake_sigreturn_missing_fpsimd
1050 12:27:56.559242 arm64:fake_sigreturn_sme_change_vl
1051 12:27:56.559332 arm64:fake_sigreturn_sve_change_vl
1052 12:27:56.559438 arm64:mangle_pstate_invalid_compat_toggle
1053 12:27:56.559527 arm64:mangle_pstate_invalid_daif_bits
1054 12:27:56.559632 arm64:mangle_pstate_invalid_mode_el1h
1055 12:27:56.559723 arm64:mangle_pstate_invalid_mode_el1t
1056 12:27:56.559810 arm64:mangle_pstate_invalid_mode_el2h
1057 12:27:56.559910 arm64:mangle_pstate_invalid_mode_el2t
1058 12:27:56.560014 arm64:mangle_pstate_invalid_mode_el3h
1059 12:27:56.560101 arm64:mangle_pstate_invalid_mode_el3t
1060 12:27:56.560188 arm64:sme_trap_no_sm
1061 12:27:56.560288 arm64:sme_trap_non_streaming
1062 12:27:56.560378 arm64:sme_trap_za
1063 12:27:56.560463 arm64:sme_vl
1064 12:27:56.560547 arm64:ssve_regs
1065 12:27:56.560629 arm64:sve_regs
1066 12:27:56.560732 arm64:sve_vl
1067 12:27:56.560824 arm64:za_no_regs
1068 12:27:56.560911 arm64:za_regs
1069 12:27:56.560996 arm64:pac
1070 12:27:56.561082 arm64:fp-stress
1071 12:27:56.561168 arm64:sve-ptrace
1072 12:27:56.561253 arm64:sve-probe-vls
1073 12:27:56.561340 arm64:vec-syscfg
1074 12:27:56.561428 arm64:za-fork
1075 12:27:56.561513 arm64:za-ptrace
1076 12:27:56.561598 arm64:check_buffer_fill
1077 12:27:56.561964 arm64:check_child_memory
1078 12:27:56.562080 arm64:check_gcr_el1_cswitch
1079 12:27:56.562172 arm64:check_ksm_options
1080 12:27:56.562258 arm64:check_mmap_options
1081 12:27:56.562343 arm64:check_prctl
1082 12:27:56.562426 arm64:check_tags_inclusion
1083 12:27:56.562510 arm64:check_user_mem
1084 12:27:56.562595 arm64:btitest
1085 12:27:56.562681 arm64:nobtitest
1086 12:27:56.562767 arm64:hwcap
1087 12:27:56.562853 arm64:ptrace
1088 12:27:56.562939 arm64:syscall-abi
1089 12:27:56.563026 arm64:tpidr2
1090 12:27:56.563135 ===========End Tests to run ===============
1091 12:27:57.494638 <12>[ 29.116734] kselftest: Running tests in arm64
1092 12:27:57.522963 TAP version 13
1093 12:27:57.540447 1..48
1094 12:27:57.588207 # selftests: arm64: tags_test
1095 12:27:57.643189 ok 1 selftests: arm64: tags_test
1096 12:27:57.687675 # selftests: arm64: run_tags_test.sh
1097 12:27:57.738794 # --------------------
1098 12:27:57.739073 # running tags test
1099 12:27:57.739210 # --------------------
1100 12:27:57.739551 # [PASS]
1101 12:27:57.744646 ok 2 selftests: arm64: run_tags_test.sh
1102 12:27:57.791315 # selftests: arm64: fake_sigreturn_bad_magic
1103 12:27:57.847558 # Registered handlers for all signals.
1104 12:27:57.847800 # Detected MINSTKSIGSZ:10000
1105 12:27:57.847900 # Testcase initialized.
1106 12:27:57.847995 # uc context validated.
1107 12:27:57.848087 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1108 12:27:57.848177 # Handled SIG_COPYCTX
1109 12:27:57.848288 # Available space:3536
1110 12:27:57.848381 # Using badly built context - ERR: BAD MAGIC !
1111 12:27:57.848470 # SIG_OK -- SP:0xFFFFE49D52A0 si_addr@:0xffffe49d52a0 si_code:2 token@:0xffffe49d4040 offset:-4704
1112 12:27:57.848561 # ==>> completed. PASS(1)
1113 12:27:57.848650 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
1114 12:27:57.848737 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE49D4040
1115 12:27:57.856332 ok 3 selftests: arm64: fake_sigreturn_bad_magic
1116 12:27:57.904774 # selftests: arm64: fake_sigreturn_bad_size
1117 12:27:57.955422 # Registered handlers for all signals.
1118 12:27:57.956055 # Detected MINSTKSIGSZ:10000
1119 12:27:57.956274 # Testcase initialized.
1120 12:27:57.956497 # uc context validated.
1121 12:27:57.956675 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1122 12:27:57.956831 # Handled SIG_COPYCTX
1123 12:27:57.956981 # Available space:3536
1124 12:27:57.957126 # uc context validated.
1125 12:27:57.957269 # Using badly built context - ERR: Bad size for esr_context
1126 12:27:57.957457 # SIG_OK -- SP:0xFFFFEE405C20 si_addr@:0xffffee405c20 si_code:2 token@:0xffffee4049c0 offset:-4704
1127 12:27:57.957595 # ==>> completed. PASS(1)
1128 12:27:57.957753 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
1129 12:27:57.957899 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEE4049C0
1130 12:27:57.964548 ok 4 selftests: arm64: fake_sigreturn_bad_size
1131 12:27:58.009792 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
1132 12:27:58.059763 # Registered handlers for all signals.
1133 12:27:58.060083 # Detected MINSTKSIGSZ:10000
1134 12:27:58.060273 # Testcase initialized.
1135 12:27:58.060422 # uc context validated.
1136 12:27:58.060843 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1137 12:27:58.061046 # Handled SIG_COPYCTX
1138 12:27:58.061211 # Available space:3536
1139 12:27:58.061335 # Using badly built context - ERR: Bad size for terminator
1140 12:27:58.061490 # SIG_OK -- SP:0xFFFFF040DB70 si_addr@:0xfffff040db70 si_code:2 token@:0xfffff040c910 offset:-4704
1141 12:27:58.062064 # ==>> completed. PASS(1)
1142 12:27:58.062584 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
1143 12:27:58.062762 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF040C910
1144 12:27:58.069305 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
1145 12:27:58.115301 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
1146 12:27:58.165915 # Registered handlers for all signals.
1147 12:27:58.166186 # Detected MINSTKSIGSZ:10000
1148 12:27:58.168233 # Testcase initialized.
1149 12:27:58.168360 # uc context validated.
1150 12:27:58.168454 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1151 12:27:58.168544 # Handled SIG_COPYCTX
1152 12:27:58.168629 # Available space:3536
1153 12:27:58.168712 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
1154 12:27:58.168999 # SIG_OK -- SP:0xFFFFF8476F90 si_addr@:0xfffff8476f90 si_code:2 token@:0xfffff8475d30 offset:-4704
1155 12:27:58.169104 # ==>> completed. PASS(1)
1156 12:27:58.169196 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
1157 12:27:58.169302 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF8475D30
1158 12:27:58.177474 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
1159 12:27:58.226294 # selftests: arm64: fake_sigreturn_misaligned_sp
1160 12:27:58.275210 # Registered handlers for all signals.
1161 12:27:58.275443 # Detected MINSTKSIGSZ:10000
1162 12:27:58.277229 # Testcase initialized.
1163 12:27:58.277673 # uc context validated.
1164 12:27:58.277892 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1165 12:27:58.278085 # Handled SIG_COPYCTX
1166 12:27:58.278287 # SIG_OK -- SP:0xFFFFE0A44B23 si_addr@:0xffffe0a44b23 si_code:2 token@:0xffffe0a44b23 offset:0
1167 12:27:58.278429 # ==>> completed. PASS(1)
1168 12:27:58.278548 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
1169 12:27:58.278666 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE0A44B23
1170 12:27:58.285259 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
1171 12:27:58.334550 # selftests: arm64: fake_sigreturn_missing_fpsimd
1172 12:27:58.387801 # Registered handlers for all signals.
1173 12:27:58.388054 # Detected MINSTKSIGSZ:10000
1174 12:27:58.388368 # Testcase initialized.
1175 12:27:58.388478 # uc context validated.
1176 12:27:58.388573 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1177 12:27:58.388665 # Handled SIG_COPYCTX
1178 12:27:58.388756 # Mangling template header. Spare space:4096
1179 12:27:58.388846 # Using badly built context - ERR: Missing FPSIMD
1180 12:27:58.388952 # SIG_OK -- SP:0xFFFFE58D2E70 si_addr@:0xffffe58d2e70 si_code:2 token@:0xffffe58d1c10 offset:-4704
1181 12:27:58.389044 # ==>> completed. PASS(1)
1182 12:27:58.389132 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
1183 12:27:58.390719 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE58D1C10
1184 12:27:58.398136 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
1185 12:27:58.447891 # selftests: arm64: fake_sigreturn_sme_change_vl
1186 12:27:58.501251 # Registered handlers for all signals.
1187 12:27:58.501441 # Detected MINSTKSIGSZ:10000
1188 12:27:58.501535 # Required Features: [ SME ] supported
1189 12:27:58.501623 # Incompatible Features: [] absent
1190 12:27:58.501742 # Testcase initialized.
1191 12:27:58.501832 # uc context validated.
1192 12:27:58.501921 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1193 12:27:58.502012 # Handled SIG_COPYCTX
1194 12:27:58.502105 # Attempting to change VL from 16 to 256
1195 12:27:58.502212 # SIG_OK -- SP:0xFFFFCAF39420 si_addr@:0xffffcaf39420 si_code:2 token@:0xffffcaf381c0 offset:-4704
1196 12:27:58.502305 # ==>> completed. PASS(1)
1197 12:27:58.502394 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
1198 12:27:58.509653 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCAF381C0
1199 12:27:58.509967 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl
1200 12:27:58.559632 # selftests: arm64: fake_sigreturn_sve_change_vl
1201 12:27:58.612512 # Registered handlers for all signals.
1202 12:27:58.612787 # Detected MINSTKSIGSZ:10000
1203 12:27:58.613247 # Required Features: [ SVE ] supported
1204 12:27:58.613404 # Incompatible Features: [] absent
1205 12:27:58.613558 # Testcase initialized.
1206 12:27:58.613732 # uc context validated.
1207 12:27:58.613880 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1208 12:27:58.614026 # Handled SIG_COPYCTX
1209 12:27:58.614169 # Attempting to change VL from 16 to 256
1210 12:27:58.614388 # SIG_OK -- SP:0xFFFFFD8323D0 si_addr@:0xfffffd8323d0 si_code:2 token@:0xfffffd831170 offset:-4704
1211 12:27:58.614550 # ==>> completed. PASS(1)
1212 12:27:58.614698 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
1213 12:27:58.614839 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFD831170
1214 12:27:58.621754 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl
1215 12:27:58.669356 # selftests: arm64: mangle_pstate_invalid_compat_toggle
1216 12:27:58.721712 # Registered handlers for all signals.
1217 12:27:58.722042 # Detected MINSTKSIGSZ:10000
1218 12:27:58.722469 # Testcase initialized.
1219 12:27:58.722668 # uc context validated.
1220 12:27:58.722821 # Handled SIG_TRIG
1221 12:27:58.722945 # SIG_OK -- SP:0xFFFFE548A040 si_addr@:0xffffe548a040 si_code:2 token@:(nil) offset:-281474528485440
1222 12:27:58.723066 # ==>> completed. PASS(1)
1223 12:27:58.723182 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
1224 12:27:58.734555 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
1225 12:27:58.796484 # selftests: arm64: mangle_pstate_invalid_daif_bits
1226 12:27:58.855546 # Registered handlers for all signals.
1227 12:27:58.855891 # Detected MINSTKSIGSZ:10000
1228 12:27:58.856084 # Testcase initialized.
1229 12:27:58.856466 # uc context validated.
1230 12:27:58.856608 # Handled SIG_TRIG
1231 12:27:58.856755 # SIG_OK -- SP:0xFFFFC02FE3C0 si_addr@:0xffffc02fe3c0 si_code:2 token@:(nil) offset:-281473906107328
1232 12:27:58.856916 # ==>> completed. PASS(1)
1233 12:27:58.857065 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
1234 12:27:58.868474 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
1235 12:27:58.922923 # selftests: arm64: mangle_pstate_invalid_mode_el1h
1236 12:27:58.974623 # Registered handlers for all signals.
1237 12:27:58.974969 # Detected MINSTKSIGSZ:10000
1238 12:27:58.975139 # Testcase initialized.
1239 12:27:58.975493 # uc context validated.
1240 12:27:58.975625 # Handled SIG_TRIG
1241 12:27:58.975747 # SIG_OK -- SP:0xFFFFC2EEF9B0 si_addr@:0xffffc2eef9b0 si_code:2 token@:(nil) offset:-281473952184752
1242 12:27:58.975869 # ==>> completed. PASS(1)
1243 12:27:58.975988 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
1244 12:27:58.982789 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
1245 12:27:59.027784 # selftests: arm64: mangle_pstate_invalid_mode_el1t
1246 12:27:59.075845 # Registered handlers for all signals.
1247 12:27:59.076136 # Detected MINSTKSIGSZ:10000
1248 12:27:59.076522 # Testcase initialized.
1249 12:27:59.076689 # uc context validated.
1250 12:27:59.076820 # Handled SIG_TRIG
1251 12:27:59.076946 # SIG_OK -- SP:0xFFFFDB58E3F0 si_addr@:0xffffdb58e3f0 si_code:2 token@:(nil) offset:-281474361779184
1252 12:27:59.077076 # ==>> completed. PASS(1)
1253 12:27:59.077202 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
1254 12:27:59.082667 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
1255 12:27:59.136536 # selftests: arm64: mangle_pstate_invalid_mode_el2h
1256 12:27:59.186809 # Registered handlers for all signals.
1257 12:27:59.187106 # Detected MINSTKSIGSZ:10000
1258 12:27:59.187468 # Testcase initialized.
1259 12:27:59.188938 # uc context validated.
1260 12:27:59.189208 # Handled SIG_TRIG
1261 12:27:59.189565 # SIG_OK -- SP:0xFFFFC73CEE40 si_addr@:0xffffc73cee40 si_code:2 token@:(nil) offset:-281474024402496
1262 12:27:59.189714 # ==>> completed. PASS(1)
1263 12:27:59.189836 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
1264 12:27:59.195917 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
1265 12:27:59.243357 # selftests: arm64: mangle_pstate_invalid_mode_el2t
1266 12:27:59.295683 # Registered handlers for all signals.
1267 12:27:59.296290 # Detected MINSTKSIGSZ:10000
1268 12:27:59.296460 # Testcase initialized.
1269 12:27:59.296634 # uc context validated.
1270 12:27:59.296781 # Handled SIG_TRIG
1271 12:27:59.296923 # SIG_OK -- SP:0xFFFFC6F6F8E0 si_addr@:0xffffc6f6f8e0 si_code:2 token@:(nil) offset:-281474019817696
1272 12:27:59.297069 # ==>> completed. PASS(1)
1273 12:27:59.298284 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
1274 12:27:59.305076 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
1275 12:27:59.352164 # selftests: arm64: mangle_pstate_invalid_mode_el3h
1276 12:27:59.401983 # Registered handlers for all signals.
1277 12:27:59.402293 # Detected MINSTKSIGSZ:10000
1278 12:27:59.402693 # Testcase initialized.
1279 12:27:59.402824 # uc context validated.
1280 12:27:59.402941 # Handled SIG_TRIG
1281 12:27:59.403055 # SIG_OK -- SP:0xFFFFC858E250 si_addr@:0xffffc858e250 si_code:2 token@:(nil) offset:-281474043011664
1282 12:27:59.403171 # ==>> completed. PASS(1)
1283 12:27:59.403284 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
1284 12:27:59.410375 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
1285 12:27:59.457471 # selftests: arm64: mangle_pstate_invalid_mode_el3t
1286 12:27:59.510450 # Registered handlers for all signals.
1287 12:27:59.510822 # Detected MINSTKSIGSZ:10000
1288 12:27:59.510957 # Testcase initialized.
1289 12:27:59.511299 # uc context validated.
1290 12:27:59.511428 # Handled SIG_TRIG
1291 12:27:59.512890 # SIG_OK -- SP:0xFFFFD44F8CA0 si_addr@:0xffffd44f8ca0 si_code:2 token@:(nil) offset:-281474243726496
1292 12:27:59.513155 # ==>> completed. PASS(1)
1293 12:27:59.513520 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
1294 12:27:59.518894 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
1295 12:27:59.569727 # selftests: arm64: sme_trap_no_sm
1296 12:27:59.695601 # Registered handlers for all signals.
1297 12:27:59.696021 # Detected MINSTKSIGSZ:10000
1298 12:27:59.696124 # Required Features: [ SME ] supported
1299 12:27:59.696216 # Incompatible Features: [] absent
1300 12:27:59.696305 # Testcase initialized.
1301 12:27:59.696409 # SIG_OK -- SP:0xFFFFE77BEC60 si_addr@:0xaaaae9ab2514 si_code:1 token@:(nil) offset:-187651041469716
1302 12:27:59.696501 # ==>> completed. PASS(1)
1303 12:27:59.696588 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
1304 12:27:59.713945 ok 19 selftests: arm64: sme_trap_no_sm
1305 12:27:59.810838 # selftests: arm64: sme_trap_non_streaming
1306 12:27:59.878822 # Registered handlers for all signals.
1307 12:27:59.879051 # Detected MINSTKSIGSZ:10000
1308 12:27:59.879155 # Required Features: [] NOT supported
1309 12:27:59.879270 # Incompatible Features: [] supported
1310 12:27:59.879367 # ==>> completed. SKIP.
1311 12:27:59.882204 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
1312 12:27:59.894133 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
1313 12:27:59.948487 # selftests: arm64: sme_trap_za
1314 12:28:00.003207 # Registered handlers for all signals.
1315 12:28:00.003651 # Detected MINSTKSIGSZ:10000
1316 12:28:00.003779 # Testcase initialized.
1317 12:28:00.003877 # SIG_OK -- SP:0xFFFFCBC2BCD0 si_addr@:0xaaaab6ee2510 si_code:1 token@:(nil) offset:-187650190222608
1318 12:28:00.003974 # ==>> completed. PASS(1)
1319 12:28:00.004081 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
1320 12:28:00.012466 ok 21 selftests: arm64: sme_trap_za
1321 12:28:00.065729 # selftests: arm64: sme_vl
1322 12:28:00.121056 # Registered handlers for all signals.
1323 12:28:00.121288 # Detected MINSTKSIGSZ:10000
1324 12:28:00.121596 # Required Features: [ SME ] supported
1325 12:28:00.121704 # Incompatible Features: [] absent
1326 12:28:00.121793 # Testcase initialized.
1327 12:28:00.121880 # uc context validated.
1328 12:28:00.121965 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1329 12:28:00.122049 # Handled SIG_COPYCTX
1330 12:28:00.122134 # got expected VL 32
1331 12:28:00.122216 # ==>> completed. PASS(1)
1332 12:28:00.123486 # # SME VL :: Check that we get the right SME VL reported
1333 12:28:00.130693 ok 22 selftests: arm64: sme_vl
1334 12:28:00.182166 # selftests: arm64: ssve_regs
1335 12:28:00.409049 # Registered handlers for all signals.
1336 12:28:00.409261 # Detected MINSTKSIGSZ:10000
1337 12:28:00.409372 # Required Features: [ SME FA64 ] supported
1338 12:28:00.409678 # Incompatible Features: [] absent
1339 12:28:00.409768 # Testcase initialized.
1340 12:28:00.409883 # Testing VL 256
1341 12:28:00.409986 # Validating EXTRA...
1342 12:28:00.410076 # uc context validated.
1343 12:28:00.410154 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1344 12:28:00.410229 # Handled SIG_COPYCTX
1345 12:28:00.410303 # Got expected size 8752 and VL 256
1346 12:28:00.410399 # Testing VL 128
1347 12:28:00.410469 # Validating EXTRA...
1348 12:28:00.410543 # uc context validated.
1349 12:28:00.410617 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1350 12:28:00.410691 # Handled SIG_COPYCTX
1351 12:28:00.410764 # Got expected size 4384 and VL 128
1352 12:28:00.410838 # Testing VL 64
1353 12:28:00.410911 # uc context validated.
1354 12:28:00.410984 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1355 12:28:00.411058 # Handled SIG_COPYCTX
1356 12:28:00.411131 # Got expected size 2208 and VL 64
1357 12:28:00.411205 # Testing VL 32
1358 12:28:00.411277 # uc context validated.
1359 12:28:00.411371 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1360 12:28:00.411441 # Handled SIG_COPYCTX
1361 12:28:00.411514 # Got expected size 1120 and VL 32
1362 12:28:00.411587 # Testing VL 16
1363 12:28:00.411659 # uc context validated.
1364 12:28:00.411731 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1365 12:28:00.411804 # Handled SIG_COPYCTX
1366 12:28:00.411877 # Got expected size 576 and VL 16
1367 12:28:00.411949 # ==>> completed. PASS(1)
1368 12:28:00.412022 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
1369 12:28:00.420364 ok 23 selftests: arm64: ssve_regs
1370 12:28:00.468013 # selftests: arm64: sve_regs
1371 12:28:00.926242 # Registered handlers for all signals.
1372 12:28:00.926685 # Detected MINSTKSIGSZ:10000
1373 12:28:00.926899 # Required Features: [ SVE ] supported
1374 12:28:00.927096 # Incompatible Features: [] absent
1375 12:28:00.927244 # Testcase initialized.
1376 12:28:00.927419 # Testing VL 256
1377 12:28:00.927612 # Validating EXTRA...
1378 12:28:00.927807 # uc context validated.
1379 12:28:00.928031 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1380 12:28:00.928206 # Handled SIG_COPYCTX
1381 12:28:00.928373 # Got expected size 8752 and VL 256
1382 12:28:00.928542 # Testing VL 240
1383 12:28:00.928708 # Validating EXTRA...
1384 12:28:00.928878 # uc context validated.
1385 12:28:00.929056 # 8816 byte GOOD CONTEXT grabbed from sig_copyctx handler
1386 12:28:00.929234 # Handled SIG_COPYCTX
1387 12:28:00.929407 # Got expected size 8208 and VL 240
1388 12:28:00.929577 # Testing VL 224
1389 12:28:00.930307 # Validating EXTRA...
1390 12:28:00.930493 # uc context validated.
1391 12:28:00.930666 # 8272 byte GOOD CONTEXT grabbed from sig_copyctx handler
1392 12:28:00.930813 # Handled SIG_COPYCTX
1393 12:28:00.930956 # Got expected size 7664 and VL 224
1394 12:28:00.931098 # Testing VL 208
1395 12:28:00.931270 # Validating EXTRA...
1396 12:28:00.931445 # uc context validated.
1397 12:28:00.931660 # 7728 byte GOOD CONTEXT grabbed from sig_copyctx handler
1398 12:28:00.931818 # Handled SIG_COPYCTX
1399 12:28:00.931966 # Got expected size 7120 and VL 208
1400 12:28:00.932111 # Testing VL 192
1401 12:28:00.932302 # Validating EXTRA...
1402 12:28:00.932486 # uc context validated.
1403 12:28:00.932642 # 7184 byte GOOD CONTEXT grabbed from sig_copyctx handler
1404 12:28:00.932797 # Handled SIG_COPYCTX
1405 12:28:00.932972 # Got expected size 6576 and VL 192
1406 12:28:00.933128 # Testing VL 176
1407 12:28:00.933294 # Validating EXTRA...
1408 12:28:00.933474 # uc context validated.
1409 12:28:00.933631 # 6640 byte GOOD CONTEXT grabbed from sig_copyctx handler
1410 12:28:00.934050 # Handled SIG_COPYCTX
1411 12:28:00.934207 # Got expected size 6032 and VL 176
1412 12:28:00.941643 # Testing VL 160
1413 12:28:00.941890 # Validating EXTRA...
1414 12:28:00.942036 # uc context validated.
1415 12:28:00.942379 # 6096 byte GOOD CONTEXT grabbed from sig_copyctx handler
1416 12:28:00.942500 # Handled SIG_COPYCTX
1417 12:28:00.942635 # Got expected size 5488 and VL 160
1418 12:28:00.942791 # Testing VL 144
1419 12:28:00.942958 # Validating EXTRA...
1420 12:28:00.943092 # uc context validated.
1421 12:28:00.943242 # 5552 byte GOOD CONTEXT grabbed from sig_copyctx handler
1422 12:28:00.943371 # Handled SIG_COPYCTX
1423 12:28:00.943528 # Got expected size 4944 and VL 144
1424 12:28:00.943685 # Testing VL 128
1425 12:28:00.943783 # Validating EXTRA...
1426 12:28:00.943873 # uc context validated.
1427 12:28:00.943962 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1428 12:28:00.944053 # Handled SIG_COPYCTX
1429 12:28:00.944192 # Got expected size 4384 and VL 128
1430 12:28:00.944287 # Testing VL 112
1431 12:28:00.944376 # Validating EXTRA...
1432 12:28:00.944464 # uc context validated.
1433 12:28:00.944569 # 4448 byte GOOD CONTEXT grabbed from sig_copyctx handler
1434 12:28:00.944676 # Handled SIG_COPYCTX
1435 12:28:00.944766 # Got expected size 3840 and VL 112
1436 12:28:00.944855 # Testing VL 96
1437 12:28:00.944946 # uc context validated.
1438 12:28:00.945092 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1439 12:28:00.945189 # Handled SIG_COPYCTX
1440 12:28:00.945277 # Got expected size 3296 and VL 96
1441 12:28:00.945365 # Testing VL 80
1442 12:28:00.945479 # uc context validated.
1443 12:28:00.945601 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1444 12:28:00.945729 # Handled SIG_COPYCTX
1445 12:28:00.945819 # Got expected size 2752 and VL 80
1446 12:28:00.945908 # Testing VL 64
1447 12:28:00.945995 # uc context validated.
1448 12:28:00.946113 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1449 12:28:00.946206 # Handled SIG_COPYCTX
1450 12:28:00.946316 # Got expected size 2208 and VL 64
1451 12:28:00.946425 # Testing VL 48
1452 12:28:00.946532 # uc context validated.
1453 12:28:00.946622 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1454 12:28:00.946726 # Handled SIG_COPYCTX
1455 12:28:00.946830 # Got expected size 1664 and VL 48
1456 12:28:00.946919 # Testing VL 32
1457 12:28:00.947006 # uc context validated.
1458 12:28:00.947093 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1459 12:28:00.947217 # Handled SIG_COPYCTX
1460 12:28:00.947316 # Got expected size 1120 and VL 32
1461 12:28:00.947405 # Testing VL 16
1462 12:28:00.947494 # uc context validated.
1463 12:28:00.950367 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1464 12:28:00.950493 # Handled SIG_COPYCTX
1465 12:28:00.950587 # Got expected size 576 and VL 16
1466 12:28:00.950875 # ==>> completed. PASS(1)
1467 12:28:00.950982 # # SVE registers :: Check that we get the right SVE registers reported
1468 12:28:00.951117 ok 24 selftests: arm64: sve_regs
1469 12:28:00.998333 # selftests: arm64: sve_vl
1470 12:28:01.051548 # Registered handlers for all signals.
1471 12:28:01.051883 # Detected MINSTKSIGSZ:10000
1472 12:28:01.052127 # Required Features: [ SVE ] supported
1473 12:28:01.052501 # Incompatible Features: [] absent
1474 12:28:01.052609 # Testcase initialized.
1475 12:28:01.052702 # uc context validated.
1476 12:28:01.052793 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1477 12:28:01.052881 # Handled SIG_COPYCTX
1478 12:28:01.052968 # got expected VL 64
1479 12:28:01.053055 # ==>> completed. PASS(1)
1480 12:28:01.053140 # # SVE VL :: Check that we get the right SVE VL reported
1481 12:28:01.062526 ok 25 selftests: arm64: sve_vl
1482 12:28:01.112241 # selftests: arm64: za_no_regs
1483 12:28:01.229427 # Registered handlers for all signals.
1484 12:28:01.229698 # Detected MINSTKSIGSZ:10000
1485 12:28:01.229791 # Required Features: [ SME ] supported
1486 12:28:01.230087 # Incompatible Features: [] absent
1487 12:28:01.230178 # Testcase initialized.
1488 12:28:01.230254 # Testing VL 256
1489 12:28:01.230348 # uc context validated.
1490 12:28:01.230435 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1491 12:28:01.230510 # Handled SIG_COPYCTX
1492 12:28:01.230576 # Got expected size 16 and VL 256
1493 12:28:01.230644 # Testing VL 128
1494 12:28:01.230729 # uc context validated.
1495 12:28:01.230842 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1496 12:28:01.230942 # Handled SIG_COPYCTX
1497 12:28:01.231018 # Got expected size 16 and VL 128
1498 12:28:01.231085 # Testing VL 64
1499 12:28:01.231165 # uc context validated.
1500 12:28:01.231241 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1501 12:28:01.231345 # Handled SIG_COPYCTX
1502 12:28:01.231436 # Got expected size 16 and VL 64
1503 12:28:01.231522 # Testing VL 32
1504 12:28:01.231602 # uc context validated.
1505 12:28:01.231674 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1506 12:28:01.231744 # Handled SIG_COPYCTX
1507 12:28:01.231847 # Got expected size 16 and VL 32
1508 12:28:01.231937 # Testing VL 16
1509 12:28:01.232015 # uc context validated.
1510 12:28:01.232093 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1511 12:28:01.232158 # Handled SIG_COPYCTX
1512 12:28:01.232220 # Got expected size 16 and VL 16
1513 12:28:01.232280 # ==>> completed. PASS(1)
1514 12:28:01.232364 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
1515 12:28:01.255415 ok 26 selftests: arm64: za_no_regs
1516 12:28:01.304217 # selftests: arm64: za_regs
1517 12:28:01.483256 # Registered handlers for all signals.
1518 12:28:01.483550 # Detected MINSTKSIGSZ:10000
1519 12:28:01.483946 # Required Features: [ SME ] supported
1520 12:28:01.484054 # Incompatible Features: [] absent
1521 12:28:01.484146 # Testcase initialized.
1522 12:28:01.484231 # Testing VL 256
1523 12:28:01.484315 # Validating EXTRA...
1524 12:28:01.484401 # uc context validated.
1525 12:28:01.484488 # 66160 byte GOOD CONTEXT grabbed from sig_copyctx handler
1526 12:28:01.484575 # Handled SIG_COPYCTX
1527 12:28:01.484678 # Got expected size 65552 and VL 256
1528 12:28:01.484764 # Testing VL 128
1529 12:28:01.484848 # Validating EXTRA...
1530 12:28:01.484933 # uc context validated.
1531 12:28:01.485017 # 17008 byte GOOD CONTEXT grabbed from sig_copyctx handler
1532 12:28:01.485102 # Handled SIG_COPYCTX
1533 12:28:01.485187 # Got expected size 16400 and VL 128
1534 12:28:01.485271 # Testing VL 64
1535 12:28:01.485371 # Validating EXTRA...
1536 12:28:01.485464 # uc context validated.
1537 12:28:01.485549 # 4720 byte GOOD CONTEXT grabbed from sig_copyctx handler
1538 12:28:01.485633 # Handled SIG_COPYCTX
1539 12:28:01.485733 # Got expected size 4112 and VL 64
1540 12:28:01.485817 # Testing VL 32
1541 12:28:01.485916 # uc context validated.
1542 12:28:01.486003 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1543 12:28:01.486087 # Handled SIG_COPYCTX
1544 12:28:01.486171 # Got expected size 1040 and VL 32
1545 12:28:01.486254 # Testing VL 16
1546 12:28:01.486336 # uc context validated.
1547 12:28:01.486437 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1548 12:28:01.486538 # Handled SIG_COPYCTX
1549 12:28:01.486642 # Got expected size 272 and VL 16
1550 12:28:01.486728 # ==>> completed. PASS(1)
1551 12:28:01.486815 # # ZA register :: Check that we get the right ZA registers reported
1552 12:28:01.495363 ok 27 selftests: arm64: za_regs
1553 12:28:01.542280 # selftests: arm64: pac
1554 12:28:01.695337 # TAP version 13
1555 12:28:01.695585 # 1..7
1556 12:28:01.695678 # # Starting 7 tests from 1 test cases.
1557 12:28:01.695976 # # RUN global.corrupt_pac ...
1558 12:28:01.696082 # # OK global.corrupt_pac
1559 12:28:01.696176 # ok 1 global.corrupt_pac
1560 12:28:01.696262 # # RUN global.pac_instructions_not_nop ...
1561 12:28:01.696337 # # OK global.pac_instructions_not_nop
1562 12:28:01.696425 # ok 2 global.pac_instructions_not_nop
1563 12:28:01.696506 # # RUN global.pac_instructions_not_nop_generic ...
1564 12:28:01.696594 # # OK global.pac_instructions_not_nop_generic
1565 12:28:01.696696 # ok 3 global.pac_instructions_not_nop_generic
1566 12:28:01.696787 # # RUN global.single_thread_different_keys ...
1567 12:28:01.703970 # # OK global.single_thread_different_keys
1568 12:28:01.704267 # ok 4 global.single_thread_different_keys
1569 12:28:01.704367 # # RUN global.exec_changed_keys ...
1570 12:28:01.704467 # # OK global.exec_changed_keys
1571 12:28:01.704578 # ok 5 global.exec_changed_keys
1572 12:28:01.704671 # # RUN global.context_switch_keep_keys ...
1573 12:28:01.704761 # # OK global.context_switch_keep_keys
1574 12:28:01.704857 # ok 6 global.context_switch_keep_keys
1575 12:28:01.705719 # # RUN global.context_switch_keep_keys_generic ...
1576 12:28:01.705981 # # OK global.context_switch_keep_keys_generic
1577 12:28:01.706068 # ok 7 global.context_switch_keep_keys_generic
1578 12:28:01.706138 # # PASSED: 7 / 7 tests passed.
1579 12:28:01.706215 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
1580 12:28:01.706467 ok 28 selftests: arm64: pac
1581 12:28:01.753859 # selftests: arm64: fp-stress
1582 12:28:18.172230 # TAP version 13
1583 12:28:18.172825 # 1..27
1584 12:28:18.173043 # # 1 CPUs, 16 SVE VLs, 5 SME VLs
1585 12:28:18.173263 # # Will run for 10s
1586 12:28:18.173666 # # Started FPSIMD-0-0
1587 12:28:18.173865 # # Started SVE-VL-256-0
1588 12:28:18.174049 # # Started SVE-VL-240-0
1589 12:28:18.174210 # # Started SVE-VL-224-0
1590 12:28:18.174444 # # Started SVE-VL-208-0
1591 12:28:18.174649 # # Started SVE-VL-192-0
1592 12:28:18.174784 # # Started SVE-VL-176-0
1593 12:28:18.174899 # # Started SVE-VL-160-0
1594 12:28:18.175061 # # Started SVE-VL-144-0
1595 12:28:18.175192 # # Started SVE-VL-128-0
1596 12:28:18.175307 # # Started SVE-VL-112-0
1597 12:28:18.175420 # # Started SVE-VL-96-0
1598 12:28:18.175533 # # Started SVE-VL-80-0
1599 12:28:18.175646 # # Started SVE-VL-64-0
1600 12:28:18.175759 # # Started SVE-VL-48-0
1601 12:28:18.175871 # # Started SVE-VL-32-0
1602 12:28:18.175982 # # Started SVE-VL-16-0
1603 12:28:18.176095 # # Started SSVE-VL-256-0
1604 12:28:18.176206 # # Started ZA-VL-256-0
1605 12:28:18.176319 # # Started SSVE-VL-128-0
1606 12:28:18.176433 # # Started ZA-VL-128-0
1607 12:28:18.176545 # # Started SSVE-VL-64-0
1608 12:28:18.176656 # # Started ZA-VL-64-0
1609 12:28:18.176804 # # Started SSVE-VL-32-0
1610 12:28:18.176927 # # Started ZA-VL-32-0
1611 12:28:18.178656 # # Started SSVE-VL-16-0
1612 12:28:18.180012 # # Started ZA-VL-16-0
1613 12:28:18.180789 # # FPSIMD-0-0: Vector length: 128 bits
1614 12:28:18.181004 # # FPSIMD-0-0: PID: 907
1615 12:28:18.181233 # # SVE-VL-256-0: Vector length: 2048 bits
1616 12:28:18.181415 # # SVE-VL-256-0: PID: 908
1617 12:28:18.181624 # # SVE-VL-192-0: Vector length: 1536 bits
1618 12:28:18.181864 # # SVE-VL-192-0: PID: 912
1619 12:28:18.182037 # # SVE-VL-208-0: Vector length: 1664 bits
1620 12:28:18.182209 # # SVE-VL-208-0: PID: 911
1621 12:28:18.182404 # # SVE-VL-224-0: Vector length: 1792 bits
1622 12:28:18.182569 # # SVE-VL-224-0: PID: 910
1623 12:28:18.182736 # # SVE-VL-176-0: Vector length: 1408 bits
1624 12:28:18.182906 # # SVE-VL-176-0: PID: 913
1625 12:28:18.188267 # # SVE-VL-160-0: Vector length: 1280 bits
1626 12:28:18.188841 # # SVE-VL-160-0: PID: 914
1627 12:28:18.189014 # # SVE-VL-16-0: Vector length: 128 bits
1628 12:28:18.189168 # # SVE-VL-16-0: PID: 923
1629 12:28:18.189316 # # SVE-VL-128-0: Vector length: 1024 bits
1630 12:28:18.189462 # # SVE-VL-128-0: PID: 916
1631 12:28:18.189608 # # SVE-VL-48-0: Vector length: 384 bits
1632 12:28:18.189816 # # SVE-VL-240-0: Vector length: 1920 bits
1633 12:28:18.190001 # # SVE-VL-240-0: PID: 909
1634 12:28:18.190236 # # SVE-VL-48-0: PID: 921
1635 12:28:18.190450 # # SVE-VL-112-0: Vector length: 896 bits
1636 12:28:18.190623 # # SVE-VL-112-0: PID: 917
1637 12:28:18.190748 # # SSVE-VL-256-0: Streaming mode Vector length: 2048 bits
1638 12:28:18.190864 # # SSVE-VL-256-0: PID: 924
1639 12:28:18.190980 # # SVE-VL-96-0: Vector length: 768 bits
1640 12:28:18.191125 # # SVE-VL-96-0: PID: 918
1641 12:28:18.191255 # # SVE-VL-144-0: Vector length: 1152 bits
1642 12:28:18.191380 # # SVE-VL-144-0: PID: 915
1643 12:28:18.191496 # # ZA-VL-128-0: Streaming mode vector length: 1024 bits
1644 12:28:18.191655 # # ZA-VL-128-0: PID: 927
1645 12:28:18.191792 # # SVE-VL-64-0: Vector length: 512 bits
1646 12:28:18.191941 # # SVE-VL-64-0: PID: 920
1647 12:28:18.192074 # # SSVE-VL-32-0: Streaming mode Vector length: 256 bits
1648 12:28:18.192206 # # SSVE-VL-32-0: PID: 930
1649 12:28:18.192359 # # SSVE-VL-64-0: Streaming mode Vector length: 512 bits
1650 12:28:18.192516 # # SSVE-VL-64-0: PID: 928
1651 12:28:18.192691 # # ZA-VL-64-0: Streaming mode vector length: 512 bits
1652 12:28:18.192844 # # ZA-VL-64-0: PID: 929
1653 12:28:18.192976 # # SVE-VL-80-0: Vector length: 640 bits
1654 12:28:18.193104 # # SVE-VL-80-0: PID: 919
1655 12:28:18.193255 # # SSVE-VL-16-0: Streaming mode Vector length: 128 bits
1656 12:28:18.193417 # # SSVE-VL-16-0: PID: 932
1657 12:28:18.193551 # # SSVE-VL-128-0: Streaming mode Vector length: 1024 bits
1658 12:28:18.194516 # # SSVE-VL-128-0: PID: 926
1659 12:28:18.194663 # # ZA-VL-256-0: Streaming mode vector length: 2048 bits
1660 12:28:18.194819 # # ZA-VL-256-0: PID: 925
1661 12:28:18.194944 # # ZA-VL-32-0: Streaming mode vector length: 256 bits
1662 12:28:18.195063 # # SVE-VL-32-0: Vector length: 256 bits
1663 12:28:18.195184 # # SVE-VL-32-0: PID: 922
1664 12:28:18.195301 # # ZA-VL-32-0: PID: 931
1665 12:28:18.195419 # # ZA-VL-16-0: Streaming mode vector length: 128 bits
1666 12:28:18.195538 # # ZA-VL-16-0: PID: 933
1667 12:28:18.195654 # # Finishing up...
1668 12:28:18.195770 # # SVE-VL-224-0: Terminated by signal 15, no error, iterations=2780, signals=9
1669 12:28:18.196121 # ok 1 FPSIMD-0-0
1670 12:28:18.196240 # ok 2 SVE-VL-256-0
1671 12:28:18.196350 # ok 3 SVE-VL-240-0
1672 12:28:18.196441 # ok 4 SVE-VL-224-0
1673 12:28:18.196545 # ok 5 SVE-VL-208-0
1674 12:28:18.196635 # ok 6 SVE-VL-192-0
1675 12:28:18.196722 # ok 7 SVE-VL-176-0
1676 12:28:18.196811 # ok 8 SVE-VL-160-0
1677 12:28:18.196914 # ok 9 SVE-VL-144-0
1678 12:28:18.197002 # ok 10 SVE-VL-128-0
1679 12:28:18.197088 # ok 11 SVE-VL-112-0
1680 12:28:18.197178 # ok 12 SVE-VL-96-0
1681 12:28:18.197265 # ok 13 SVE-VL-80-0
1682 12:28:18.197353 # ok 14 SVE-VL-64-0
1683 12:28:18.197458 # ok 15 SVE-VL-48-0
1684 12:28:18.197551 # ok 16 SVE-VL-32-0
1685 12:28:18.197645 # ok 17 SVE-VL-16-0
1686 12:28:18.197744 # ok 18 SSVE-VL-256-0
1687 12:28:18.197832 # ok 19 ZA-VL-256-0
1688 12:28:18.197939 # ok 20 SSVE-VL-128-0
1689 12:28:18.198034 # ok 21 ZA-VL-128-0
1690 12:28:18.198128 # ok 22 SSVE-VL-64-0
1691 12:28:18.198217 # ok 23 ZA-VL-64-0
1692 12:28:18.198304 # ok 24 SSVE-VL-32-0
1693 12:28:18.198387 # ok 25 ZA-VL-32-0
1694 12:28:18.198490 # ok 26 SSVE-VL-16-0
1695 12:28:18.198579 # ok 27 ZA-VL-16-0
1696 12:28:18.198665 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=3263, signals=9
1697 12:28:18.198753 # # ZA-VL-256-0: Terminated by signal 15, no error, iterations=221, signals=9
1698 12:28:18.198841 # # SVE-VL-144-0: Terminated by signal 15, no error, iterations=3551, signals=9
1699 12:28:18.215250 # # SVE-VL-176-0: Terminated by signal 15, no error, iterations=3293, signals=9
1700 12:28:18.215886 # # SVE-VL-192-0: Terminated by signal 15, no error, iterations=3067, signals=9
1701 12:28:18.216063 # # SSVE-VL-256-0: Terminated by signal 15, no error, iterations=2607, signals=9
1702 12:28:18.216194 # # SVE-VL-128-0: Terminated by signal 15, no error, iterations=4153, signals=9
1703 12:28:18.216336 # # SVE-VL-16-0: Terminated by signal 15, no error, iterations=14010, signals=9
1704 12:28:18.298587 # # ZA-VL-32-0: Terminated by signal 15, no error, iterations=1421, signals=9
1705 12:28:18.299121 # # SSVE-VL-32-0: Terminated by signal 15, no error, iterations=9053, signals=9
1706 12:28:18.327759 # # ZA-VL-16-0: Terminated by signal 15, no error, iterations=1233, signals=9
1707 12:28:18.328217 # # ZA-VL-64-0: Terminated by signal 15, no error, iterations=984, signals=9
1708 12:28:18.328326 # # SVE-VL-48-0: Terminated by signal 15, no error, iterations=8005, signals=9
1709 12:28:18.328414 # # ZA-VL-128-0: Terminated by signal 15, no error, iterations=721, signals=9
1710 12:28:18.328511 # # SVE-VL-96-0: Terminated by signal 15, no error, iterations=5265, signals=9
1711 12:28:18.328607 # # SSVE-VL-128-0: Terminated by signal 15, no error, iterations=3901, signals=9
1712 12:28:18.328900 # # SSVE-VL-16-0: Terminated by signal 15, no error, iterations=11702, signals=9
1713 12:28:18.329033 # # SVE-VL-112-0: Terminated by signal 15, no error, iterations=4685, signals=9
1714 12:28:18.329347 # # SVE-VL-32-0: Terminated by signal 15, no error, iterations=7463, signals=9
1715 12:28:18.329468 # # SVE-VL-240-0: Terminated by signal 15, no error, iterations=2474, signals=9
1716 12:28:18.329807 # # SVE-VL-64-0: Terminated by signal 15, no error, iterations=6621, signals=9
1717 12:28:18.329993 # # SVE-VL-80-0: Terminated by signal 15, no error, iterations=5388, signals=9
1718 12:28:18.330194 # # SVE-VL-256-0: Terminated by signal 15, no error, iterations=2551, signals=9
1719 12:28:18.330362 # # SSVE-VL-64-0: Terminated by signal 15, no error, iterations=6787, signals=9
1720 12:28:18.330550 # # SVE-VL-208-0: Terminated by signal 15, no error, iterations=3072, signals=9
1721 12:28:18.330681 # # SVE-VL-160-0: Terminated by signal 15, no error, iterations=3736, signals=9
1722 12:28:18.330819 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:0 error:0
1723 12:28:18.335826 ok 29 selftests: arm64: fp-stress
1724 12:28:18.478273 # selftests: arm64: sve-ptrace
1725 12:28:18.618036 # TAP version 13
1726 12:28:18.618379 # 1..4104
1727 12:28:18.618573 # # Parent is 950, child is 951
1728 12:28:18.619088 # ok 1 SVE FPSIMD set via SVE: 0
1729 12:28:18.619259 # ok 2 SVE get_fpsimd() gave same state
1730 12:28:18.619478 # ok 3 SVE SVE_PT_VL_INHERIT set
1731 12:28:18.619728 # ok 4 SVE SVE_PT_VL_INHERIT cleared
1732 12:28:18.619904 # ok 5 Set SVE VL 16
1733 12:28:18.620059 # ok 6 Set and get SVE data for VL 16
1734 12:28:18.620206 # ok 7 Set and get FPSIMD data for SVE VL 16
1735 12:28:18.620351 # ok 8 Set FPSIMD, read via SVE for SVE VL 16
1736 12:28:18.620496 # ok 9 Set SVE VL 32
1737 12:28:18.620639 # ok 10 Set and get SVE data for VL 32
1738 12:28:18.620783 # ok 11 Set and get FPSIMD data for SVE VL 32
1739 12:28:18.620989 # ok 12 Set FPSIMD, read via SVE for SVE VL 32
1740 12:28:18.621129 # ok 13 Set SVE VL 48
1741 12:28:18.621275 # ok 14 Set and get SVE data for VL 48
1742 12:28:18.621420 # ok 15 Set and get FPSIMD data for SVE VL 48
1743 12:28:18.621564 # ok 16 Set FPSIMD, read via SVE for SVE VL 48
1744 12:28:18.621726 # ok 17 Set SVE VL 64
1745 12:28:18.621873 # ok 18 Set and get SVE data for VL 64
1746 12:28:18.622020 # ok 19 Set and get FPSIMD data for SVE VL 64
1747 12:28:18.622161 # ok 20 Set FPSIMD, read via SVE for SVE VL 64
1748 12:28:18.622305 # ok 21 Set SVE VL 80
1749 12:28:18.622449 # ok 22 Set and get SVE data for VL 80
1750 12:28:18.622593 # ok 23 Set and get FPSIMD data for SVE VL 80
1751 12:28:18.622738 # ok 24 Set FPSIMD, read via SVE for SVE VL 80
1752 12:28:18.622881 # ok 25 Set SVE VL 96
1753 12:28:18.623025 # ok 26 Set and get SVE data for VL 96
1754 12:28:18.623167 # ok 27 Set and get FPSIMD data for SVE VL 96
1755 12:28:18.623308 # ok 28 Set FPSIMD, read via SVE for SVE VL 96
1756 12:28:18.623450 # ok 29 Set SVE VL 112
1757 12:28:18.623654 # ok 30 Set and get SVE data for VL 112
1758 12:28:18.623829 # ok 31 Set and get FPSIMD data for SVE VL 112
1759 12:28:18.623979 # ok 32 Set FPSIMD, read via SVE for SVE VL 112
1760 12:28:18.624125 # ok 33 Set SVE VL 128
1761 12:28:18.624268 # ok 34 Set and get SVE data for VL 128
1762 12:28:18.624410 # ok 35 Set and get FPSIMD data for SVE VL 128
1763 12:28:18.624552 # ok 36 Set FPSIMD, read via SVE for SVE VL 128
1764 12:28:18.624695 # ok 37 Set SVE VL 144
1765 12:28:18.624837 # ok 38 Set and get SVE data for VL 144
1766 12:28:18.624980 # ok 39 Set and get FPSIMD data for SVE VL 144
1767 12:28:18.625121 # ok 40 Set FPSIMD, read via SVE for SVE VL 144
1768 12:28:18.625263 # ok 41 Set SVE VL 160
1769 12:28:18.625405 # ok 42 Set and get SVE data for VL 160
1770 12:28:18.625546 # ok 43 Set and get FPSIMD data for SVE VL 160
1771 12:28:18.625701 # ok 44 Set FPSIMD, read via SVE for SVE VL 160
1772 12:28:18.625847 # ok 45 Set SVE VL 176
1773 12:28:18.625990 # ok 46 Set and get SVE data for VL 176
1774 12:28:18.626131 # ok 47 Set and get FPSIMD data for SVE VL 176
1775 12:28:18.626271 # ok 48 Set FPSIMD, read via SVE for SVE VL 176
1776 12:28:18.626415 # ok 49 Set SVE VL 192
1777 12:28:18.626917 # ok 50 Set and get SVE data for VL 192
1778 12:28:18.627080 # ok 51 Set and get FPSIMD data for SVE VL 192
1779 12:28:18.627840 # ok 52 Set FPSIMD, read via SVE for SVE VL 192
1780 12:28:18.628178 # ok 53 Set SVE VL 208
1781 12:28:18.628460 # ok 54 Set and get SVE data for VL 208
1782 12:28:18.628983 # ok 55 Set and get FPSIMD data for SVE VL 208
1783 12:28:18.629255 # ok 56 Set FPSIMD, read via SVE for SVE VL 208
1784 12:28:18.629356 # ok 57 Set SVE VL 224
1785 12:28:18.629569 # ok 58 Set and get SVE data for VL 224
1786 12:28:18.629764 # ok 59 Set and get FPSIMD data for SVE VL 224
1787 12:28:18.629856 # ok 60 Set FPSIMD, read via SVE for SVE VL 224
1788 12:28:18.629944 # ok 61 Set SVE VL 240
1789 12:28:18.630148 # ok 62 Set and get SVE data for VL 240
1790 12:28:18.630241 # ok 63 Set and get FPSIMD data for SVE VL 240
1791 12:28:18.630326 # ok 64 Set FPSIMD, read via SVE for SVE VL 240
1792 12:28:18.630412 # ok 65 Set SVE VL 256
1793 12:28:18.630497 # ok 66 Set and get SVE data for VL 256
1794 12:28:18.630583 # ok 67 Set and get FPSIMD data for SVE VL 256
1795 12:28:18.630670 # ok 68 Set FPSIMD, read via SVE for SVE VL 256
1796 12:28:18.630759 # ok 69 Set SVE VL 272
1797 12:28:18.630877 # ok 70 # SKIP SVE set SVE get SVE for VL 272
1798 12:28:18.630965 # ok 71 # SKIP SVE set SVE get FPSIMD for VL 272
1799 12:28:18.631054 # ok 72 # SKIP SVE set FPSIMD get SVE for VL 272
1800 12:28:18.631143 # ok 73 Set SVE VL 288
1801 12:28:18.631231 # ok 74 # SKIP SVE set SVE get SVE for VL 288
1802 12:28:18.631320 # ok 75 # SKIP SVE set SVE get FPSIMD for VL 288
1803 12:28:18.631409 # ok 76 # SKIP SVE set FPSIMD get SVE for VL 288
1804 12:28:18.631495 # ok 77 Set SVE VL 304
1805 12:28:18.631580 # ok 78 # SKIP SVE set SVE get SVE for VL 304
1806 12:28:18.631669 # ok 79 # SKIP SVE set SVE get FPSIMD for VL 304
1807 12:28:18.631758 # ok 80 # SKIP SVE set FPSIMD get SVE for VL 304
1808 12:28:18.631846 # ok 81 Set SVE VL 320
1809 12:28:18.631934 # ok 82 # SKIP SVE set SVE get SVE for VL 320
1810 12:28:18.632021 # ok 83 # SKIP SVE set SVE get FPSIMD for VL 320
1811 12:28:18.632102 # ok 84 # SKIP SVE set FPSIMD get SVE for VL 320
1812 12:28:18.632190 # ok 85 Set SVE VL 336
1813 12:28:18.632272 # ok 86 # SKIP SVE set SVE get SVE for VL 336
1814 12:28:18.632354 # ok 87 # SKIP SVE set SVE get FPSIMD for VL 336
1815 12:28:18.632436 # ok 88 # SKIP SVE set FPSIMD get SVE for VL 336
1816 12:28:18.632519 # ok 89 Set SVE VL 352
1817 12:28:18.632620 # ok 90 # SKIP SVE set SVE get SVE for VL 352
1818 12:28:18.632704 # ok 91 # SKIP SVE set SVE get FPSIMD for VL 352
1819 12:28:18.632787 # ok 92 # SKIP SVE set FPSIMD get SVE for VL 352
1820 12:28:18.632871 # ok 93 Set SVE VL 368
1821 12:28:18.632957 # ok 94 # SKIP SVE set SVE get SVE for VL 368
1822 12:28:18.637891 # ok 95 # SKIP SVE set SVE get FPSIMD for VL 368
1823 12:28:18.638163 # ok 96 # SKIP SVE set FPSIMD get SVE for VL 368
1824 12:28:18.638291 # ok 97 Set SVE VL 384
1825 12:28:18.638646 # ok 98 # SKIP SVE set SVE get SVE for VL 384
1826 12:28:18.638805 # ok 99 # SKIP SVE set SVE get FPSIMD for VL 384
1827 12:28:18.638928 # ok 100 # SKIP SVE set FPSIMD get SVE for VL 384
1828 12:28:18.639045 # ok 101 Set SVE VL 400
1829 12:28:18.640033 # ok 102 # SKIP SVE set SVE get SVE for VL 400
1830 12:28:18.640499 # ok 103 # SKIP SVE set SVE get FPSIMD for VL 400
1831 12:28:18.641777 # ok 104 # SKIP SVE set FPSIMD get SVE for VL 400
1832 12:28:18.641889 # ok 105 Set SVE VL 416
1833 12:28:18.641982 # ok 106 # SKIP SVE set SVE get SVE for VL 416
1834 12:28:18.642070 # ok 107 # SKIP SVE set SVE get FPSIMD for VL 416
1835 12:28:18.642156 # ok 108 # SKIP SVE set FPSIMD get SVE for VL 416
1836 12:28:18.642243 # ok 109 Set SVE VL 432
1837 12:28:18.642326 # ok 110 # SKIP SVE set SVE get SVE for VL 432
1838 12:28:18.642411 # ok 111 # SKIP SVE set SVE get FPSIMD for VL 432
1839 12:28:18.642503 # ok 112 # SKIP SVE set FPSIMD get SVE for VL 432
1840 12:28:18.642591 # ok 113 Set SVE VL 448
1841 12:28:18.642673 # ok 114 # SKIP SVE set SVE get SVE for VL 448
1842 12:28:18.642756 # ok 115 # SKIP SVE set SVE get FPSIMD for VL 448
1843 12:28:18.642842 # ok 116 # SKIP SVE set FPSIMD get SVE for VL 448
1844 12:28:18.642924 # ok 117 Set SVE VL 464
1845 12:28:18.643012 # ok 118 # SKIP SVE set SVE get SVE for VL 464
1846 12:28:18.643296 # ok 119 # SKIP SVE set SVE get FPSIMD for VL 464
1847 12:28:18.643397 # ok 120 # SKIP SVE set FPSIMD get SVE for VL 464
1848 12:28:18.643474 # ok 121 Set SVE VL 480
1849 12:28:18.643551 # ok 122 # SKIP SVE set SVE get SVE for VL 480
1850 12:28:18.643626 # ok 123 # SKIP SVE set SVE get FPSIMD for VL 480
1851 12:28:18.643700 # ok 124 # SKIP SVE set FPSIMD get SVE for VL 480
1852 12:28:18.643776 # ok 125 Set SVE VL 496
1853 12:28:18.643851 # ok 126 # SKIP SVE set SVE get SVE for VL 496
1854 12:28:18.643931 # ok 127 # SKIP SVE set SVE get FPSIMD for VL 496
1855 12:28:18.652962 # ok 128 # SKIP SVE set FPSIMD get SVE for VL 496
1856 12:28:18.653210 # ok 129 Set SVE VL 512
1857 12:28:18.653513 # ok 130 # SKIP SVE set SVE get SVE for VL 512
1858 12:28:18.653610 # ok 131 # SKIP SVE set SVE get FPSIMD for VL 512
1859 12:28:18.653707 # ok 132 # SKIP SVE set FPSIMD get SVE for VL 512
1860 12:28:18.653795 # ok 133 Set SVE VL 528
1861 12:28:18.653882 # ok 134 # SKIP SVE set SVE get SVE for VL 528
1862 12:28:18.653983 # ok 135 # SKIP SVE set SVE get FPSIMD for VL 528
1863 12:28:18.654072 # ok 136 # SKIP SVE set FPSIMD get SVE for VL 528
1864 12:28:18.654160 # ok 137 Set SVE VL 544
1865 12:28:18.654248 # ok 138 # SKIP SVE set SVE get SVE for VL 544
1866 12:28:18.654350 # ok 139 # SKIP SVE set SVE get FPSIMD for VL 544
1867 12:28:18.654439 # ok 140 # SKIP SVE set FPSIMD get SVE for VL 544
1868 12:28:18.654524 # ok 141 Set SVE VL 560
1869 12:28:18.654626 # ok 142 # SKIP SVE set SVE get SVE for VL 560
1870 12:28:18.654729 # ok 143 # SKIP SVE set SVE get FPSIMD for VL 560
1871 12:28:18.654845 # ok 144 # SKIP SVE set FPSIMD get SVE for VL 560
1872 12:28:18.654952 # ok 145 Set SVE VL 576
1873 12:28:18.655549 # ok 146 # SKIP SVE set SVE get SVE for VL 576
1874 12:28:18.655858 # ok 147 # SKIP SVE set SVE get FPSIMD for VL 576
1875 12:28:18.655953 # ok 148 # SKIP SVE set FPSIMD get SVE for VL 576
1876 12:28:18.656049 # ok 149 Set SVE VL 592
1877 12:28:18.656149 # ok 150 # SKIP SVE set SVE get SVE for VL 592
1878 12:28:18.656242 # ok 151 # SKIP SVE set SVE get FPSIMD for VL 592
1879 12:28:18.656343 # ok 152 # SKIP SVE set FPSIMD get SVE for VL 592
1880 12:28:18.656434 # ok 153 Set SVE VL 608
1881 12:28:18.656534 # ok 154 # SKIP SVE set SVE get SVE for VL 608
1882 12:28:18.656648 # ok 155 # SKIP SVE set SVE get FPSIMD for VL 608
1883 12:28:18.656939 # ok 156 # SKIP SVE set FPSIMD get SVE for VL 608
1884 12:28:18.657033 # ok 157 Set SVE VL 624
1885 12:28:18.657134 # ok 158 # SKIP SVE set SVE get SVE for VL 624
1886 12:28:18.657409 # ok 159 # SKIP SVE set SVE get FPSIMD for VL 624
1887 12:28:18.657514 # ok 160 # SKIP SVE set FPSIMD get SVE for VL 624
1888 12:28:18.657599 # ok 161 Set SVE VL 640
1889 12:28:18.657703 # ok 162 # SKIP SVE set SVE get SVE for VL 640
1890 12:28:18.657804 # ok 163 # SKIP SVE set SVE get FPSIMD for VL 640
1891 12:28:18.657891 # ok 164 # SKIP SVE set FPSIMD get SVE for VL 640
1892 12:28:18.657990 # ok 165 Set SVE VL 656
1893 12:28:18.658082 # ok 166 # SKIP SVE set SVE get SVE for VL 656
1894 12:28:18.658180 # ok 167 # SKIP SVE set SVE get FPSIMD for VL 656
1895 12:28:18.658281 # ok 168 # SKIP SVE set FPSIMD get SVE for VL 656
1896 12:28:18.658567 # ok 169 Set SVE VL 672
1897 12:28:18.658660 # ok 170 # SKIP SVE set SVE get SVE for VL 672
1898 12:28:18.658765 # ok 171 # SKIP SVE set SVE get FPSIMD for VL 672
1899 12:28:18.658856 # ok 172 # SKIP SVE set FPSIMD get SVE for VL 672
1900 12:28:18.658960 # ok 173 Set SVE VL 688
1901 12:28:18.659066 # ok 174 # SKIP SVE set SVE get SVE for VL 688
1902 12:28:18.668094 # ok 175 # SKIP SVE set SVE get FPSIMD for VL 688
1903 12:28:18.668336 # ok 176 # SKIP SVE set FPSIMD get SVE for VL 688
1904 12:28:18.668655 # ok 177 Set SVE VL 704
1905 12:28:18.668762 # ok 178 # SKIP SVE set SVE get SVE for VL 704
1906 12:28:18.668853 # ok 179 # SKIP SVE set SVE get FPSIMD for VL 704
1907 12:28:18.668943 # ok 180 # SKIP SVE set FPSIMD get SVE for VL 704
1908 12:28:18.669030 # ok 181 Set SVE VL 720
1909 12:28:18.669136 # ok 182 # SKIP SVE set SVE get SVE for VL 720
1910 12:28:18.669225 # ok 183 # SKIP SVE set SVE get FPSIMD for VL 720
1911 12:28:18.669309 # ok 184 # SKIP SVE set FPSIMD get SVE for VL 720
1912 12:28:18.669395 # ok 185 Set SVE VL 736
1913 12:28:18.669738 # ok 186 # SKIP SVE set SVE get SVE for VL 736
1914 12:28:18.669843 # ok 187 # SKIP SVE set SVE get FPSIMD for VL 736
1915 12:28:18.669935 # ok 188 # SKIP SVE set FPSIMD get SVE for VL 736
1916 12:28:18.670038 # ok 189 Set SVE VL 752
1917 12:28:18.670130 # ok 190 # SKIP SVE set SVE get SVE for VL 752
1918 12:28:18.670235 # ok 191 # SKIP SVE set SVE get FPSIMD for VL 752
1919 12:28:18.670321 # ok 192 # SKIP SVE set FPSIMD get SVE for VL 752
1920 12:28:18.670425 # ok 193 Set SVE VL 768
1921 12:28:18.670513 # ok 194 # SKIP SVE set SVE get SVE for VL 768
1922 12:28:18.670849 # ok 195 # SKIP SVE set SVE get FPSIMD for VL 768
1923 12:28:18.670988 # ok 196 # SKIP SVE set FPSIMD get SVE for VL 768
1924 12:28:18.671070 # ok 197 Set SVE VL 784
1925 12:28:18.675931 # ok 198 # SKIP SVE set SVE get SVE for VL 784
1926 12:28:18.676146 # ok 199 # SKIP SVE set SVE get FPSIMD for VL 784
1927 12:28:18.676250 # ok 200 # SKIP SVE set FPSIMD get SVE for VL 784
1928 12:28:18.676343 # ok 201 Set SVE VL 800
1929 12:28:18.676444 # ok 202 # SKIP SVE set SVE get SVE for VL 800
1930 12:28:18.676556 # ok 203 # SKIP SVE set SVE get FPSIMD for VL 800
1931 12:28:18.676651 # ok 204 # SKIP SVE set FPSIMD get SVE for VL 800
1932 12:28:18.676756 # ok 205 Set SVE VL 816
1933 12:28:18.677084 # ok 206 # SKIP SVE set SVE get SVE for VL 816
1934 12:28:18.677314 # ok 207 # SKIP SVE set SVE get FPSIMD for VL 816
1935 12:28:18.677576 # ok 208 # SKIP SVE set FPSIMD get SVE for VL 816
1936 12:28:18.677811 # ok 209 Set SVE VL 832
1937 12:28:18.678011 # ok 210 # SKIP SVE set SVE get SVE for VL 832
1938 12:28:18.678215 # ok 211 # SKIP SVE set SVE get FPSIMD for VL 832
1939 12:28:18.678466 # ok 212 # SKIP SVE set FPSIMD get SVE for VL 832
1940 12:28:18.678669 # ok 213 Set SVE VL 848
1941 12:28:18.678857 # ok 214 # SKIP SVE set SVE get SVE for VL 848
1942 12:28:18.679064 # ok 215 # SKIP SVE set SVE get FPSIMD for VL 848
1943 12:28:18.679245 # ok 216 # SKIP SVE set FPSIMD get SVE for VL 848
1944 12:28:18.679413 # ok 217 Set SVE VL 864
1945 12:28:18.679547 # ok 218 # SKIP SVE set SVE get SVE for VL 864
1946 12:28:18.679666 # ok 219 # SKIP SVE set SVE get FPSIMD for VL 864
1947 12:28:18.679783 # ok 220 # SKIP SVE set FPSIMD get SVE for VL 864
1948 12:28:18.679902 # ok 221 Set SVE VL 880
1949 12:28:18.680017 # ok 222 # SKIP SVE set SVE get SVE for VL 880
1950 12:28:18.680133 # ok 223 # SKIP SVE set SVE get FPSIMD for VL 880
1951 12:28:18.680249 # ok 224 # SKIP SVE set FPSIMD get SVE for VL 880
1952 12:28:18.680365 # ok 225 Set SVE VL 896
1953 12:28:18.680479 # ok 226 # SKIP SVE set SVE get SVE for VL 896
1954 12:28:18.680594 # ok 227 # SKIP SVE set SVE get FPSIMD for VL 896
1955 12:28:18.680709 # ok 228 # SKIP SVE set FPSIMD get SVE for VL 896
1956 12:28:18.685348 # ok 229 Set SVE VL 912
1957 12:28:18.685785 # ok 230 # SKIP SVE set SVE get SVE for VL 912
1958 12:28:18.685896 # ok 231 # SKIP SVE set SVE get FPSIMD for VL 912
1959 12:28:18.685986 # ok 232 # SKIP SVE set FPSIMD get SVE for VL 912
1960 12:28:18.686087 # ok 233 Set SVE VL 928
1961 12:28:18.686175 # ok 234 # SKIP SVE set SVE get SVE for VL 928
1962 12:28:18.686276 # ok 235 # SKIP SVE set SVE get FPSIMD for VL 928
1963 12:28:18.686639 # ok 236 # SKIP SVE set FPSIMD get SVE for VL 928
1964 12:28:18.686749 # ok 237 Set SVE VL 944
1965 12:28:18.686842 # ok 238 # SKIP SVE set SVE get SVE for VL 944
1966 12:28:18.687134 # ok 239 # SKIP SVE set SVE get FPSIMD for VL 944
1967 12:28:18.687239 # ok 240 # SKIP SVE set FPSIMD get SVE for VL 944
1968 12:28:18.687327 # ok 241 Set SVE VL 960
1969 12:28:18.693956 # ok 242 # SKIP SVE set SVE get SVE for VL 960
1970 12:28:18.694173 # ok 243 # SKIP SVE set SVE get FPSIMD for VL 960
1971 12:28:18.694303 # ok 244 # SKIP SVE set FPSIMD get SVE for VL 960
1972 12:28:18.694423 # ok 245 Set SVE VL 976
1973 12:28:18.694542 # ok 246 # SKIP SVE set SVE get SVE for VL 976
1974 12:28:18.694660 # ok 247 # SKIP SVE set SVE get FPSIMD for VL 976
1975 12:28:18.694778 # ok 248 # SKIP SVE set FPSIMD get SVE for VL 976
1976 12:28:18.694909 # ok 249 Set SVE VL 992
1977 12:28:18.695065 # ok 250 # SKIP SVE set SVE get SVE for VL 992
1978 12:28:18.695184 # ok 251 # SKIP SVE set SVE get FPSIMD for VL 992
1979 12:28:18.695316 # ok 252 # SKIP SVE set FPSIMD get SVE for VL 992
1980 12:28:18.695434 # ok 253 Set SVE VL 1008
1981 12:28:18.695550 # ok 254 # SKIP SVE set SVE get SVE for VL 1008
1982 12:28:18.695667 # ok 255 # SKIP SVE set SVE get FPSIMD for VL 1008
1983 12:28:18.695784 # ok 256 # SKIP SVE set FPSIMD get SVE for VL 1008
1984 12:28:18.695900 # ok 257 Set SVE VL 1024
1985 12:28:18.696014 # ok 258 # SKIP SVE set SVE get SVE for VL 1024
1986 12:28:18.696133 # ok 259 # SKIP SVE set SVE get FPSIMD for VL 1024
1987 12:28:18.696250 # ok 260 # SKIP SVE set FPSIMD get SVE for VL 1024
1988 12:28:18.696366 # ok 261 Set SVE VL 1040
1989 12:28:18.696483 # ok 262 # SKIP SVE set SVE get SVE for VL 1040
1990 12:28:18.696599 # ok 263 # SKIP SVE set SVE get FPSIMD for VL 1040
1991 12:28:18.696716 # ok 264 # SKIP SVE set FPSIMD get SVE for VL 1040
1992 12:28:18.696833 # ok 265 Set SVE VL 1056
1993 12:28:18.696949 # ok 266 # SKIP SVE set SVE get SVE for VL 1056
1994 12:28:18.697065 # ok 267 # SKIP SVE set SVE get FPSIMD for VL 1056
1995 12:28:18.697182 # ok 268 # SKIP SVE set FPSIMD get SVE for VL 1056
1996 12:28:18.697299 # ok 269 Set SVE VL 1072
1997 12:28:18.697416 # ok 270 # SKIP SVE set SVE get SVE for VL 1072
1998 12:28:18.697531 # ok 271 # SKIP SVE set SVE get FPSIMD for VL 1072
1999 12:28:18.697661 # ok 272 # SKIP SVE set FPSIMD get SVE for VL 1072
2000 12:28:18.697785 # ok 273 Set SVE VL 1088
2001 12:28:18.697902 # ok 274 # SKIP SVE set SVE get SVE for VL 1088
2002 12:28:18.698018 # ok 275 # SKIP SVE set SVE get FPSIMD for VL 1088
2003 12:28:18.698135 # ok 276 # SKIP SVE set FPSIMD get SVE for VL 1088
2004 12:28:18.698250 # ok 277 Set SVE VL 1104
2005 12:28:18.698365 # ok 278 # SKIP SVE set SVE get SVE for VL 1104
2006 12:28:18.698481 # ok 279 # SKIP SVE set SVE get FPSIMD for VL 1104
2007 12:28:18.698597 # ok 280 # SKIP SVE set FPSIMD get SVE for VL 1104
2008 12:28:18.698713 # ok 281 Set SVE VL 1120
2009 12:28:18.698829 # ok 282 # SKIP SVE set SVE get SVE for VL 1120
2010 12:28:18.698957 # ok 283 # SKIP SVE set SVE get FPSIMD for VL 1120
2011 12:28:18.699074 # ok 284 # SKIP SVE set FPSIMD get SVE for VL 1120
2012 12:28:18.699191 # ok 285 Set SVE VL 1136
2013 12:28:18.703379 # ok 286 # SKIP SVE set SVE get SVE for VL 1136
2014 12:28:18.703826 # ok 287 # SKIP SVE set SVE get FPSIMD for VL 1136
2015 12:28:18.703933 # ok 288 # SKIP SVE set FPSIMD get SVE for VL 1136
2016 12:28:18.704025 # ok 289 Set SVE VL 1152
2017 12:28:18.704106 # ok 290 # SKIP SVE set SVE get SVE for VL 1152
2018 12:28:18.704200 # ok 291 # SKIP SVE set SVE get FPSIMD for VL 1152
2019 12:28:18.704281 # ok 292 # SKIP SVE set FPSIMD get SVE for VL 1152
2020 12:28:18.706333 # ok 293 Set SVE VL 1168
2021 12:28:18.706680 # ok 294 # SKIP SVE set SVE get SVE for VL 1168
2022 12:28:18.706784 # ok 295 # SKIP SVE set SVE get FPSIMD for VL 1168
2023 12:28:18.706888 # ok 296 # SKIP SVE set FPSIMD get SVE for VL 1168
2024 12:28:18.706974 # ok 297 Set SVE VL 1184
2025 12:28:18.707073 # ok 298 # SKIP SVE set SVE get SVE for VL 1184
2026 12:28:18.707636 # ok 299 # SKIP SVE set SVE get FPSIMD for VL 1184
2027 12:28:18.707930 # ok 300 # SKIP SVE set FPSIMD get SVE for VL 1184
2028 12:28:18.708022 # ok 301 Set SVE VL 1200
2029 12:28:18.708124 # ok 302 # SKIP SVE set SVE get SVE for VL 1200
2030 12:28:18.708215 # ok 303 # SKIP SVE set SVE get FPSIMD for VL 1200
2031 12:28:18.708315 # ok 304 # SKIP SVE set FPSIMD get SVE for VL 1200
2032 12:28:18.708415 # ok 305 Set SVE VL 1216
2033 12:28:18.708516 # ok 306 # SKIP SVE set SVE get SVE for VL 1216
2034 12:28:18.708614 # ok 307 # SKIP SVE set SVE get FPSIMD for VL 1216
2035 12:28:18.708725 # ok 308 # SKIP SVE set FPSIMD get SVE for VL 1216
2036 12:28:18.708826 # ok 309 Set SVE VL 1232
2037 12:28:18.709113 # ok 310 # SKIP SVE set SVE get SVE for VL 1232
2038 12:28:18.709208 # ok 311 # SKIP SVE set SVE get FPSIMD for VL 1232
2039 12:28:18.709307 # ok 312 # SKIP SVE set FPSIMD get SVE for VL 1232
2040 12:28:18.709394 # ok 313 Set SVE VL 1248
2041 12:28:18.709492 # ok 314 # SKIP SVE set SVE get SVE for VL 1248
2042 12:28:18.709591 # ok 315 # SKIP SVE set SVE get FPSIMD for VL 1248
2043 12:28:18.709886 # ok 316 # SKIP SVE set FPSIMD get SVE for VL 1248
2044 12:28:18.709977 # ok 317 Set SVE VL 1264
2045 12:28:18.710075 # ok 318 # SKIP SVE set SVE get SVE for VL 1264
2046 12:28:18.710175 # ok 319 # SKIP SVE set SVE get FPSIMD for VL 1264
2047 12:28:18.710275 # ok 320 # SKIP SVE set FPSIMD get SVE for VL 1264
2048 12:28:18.710548 # ok 321 Set SVE VL 1280
2049 12:28:18.710651 # ok 322 # SKIP SVE set SVE get SVE for VL 1280
2050 12:28:18.710738 # ok 323 # SKIP SVE set SVE get FPSIMD for VL 1280
2051 12:28:18.710837 # ok 324 # SKIP SVE set FPSIMD get SVE for VL 1280
2052 12:28:18.711117 # ok 325 Set SVE VL 1296
2053 12:28:18.711198 # ok 326 # SKIP SVE set SVE get SVE for VL 1296
2054 12:28:18.715737 # ok 327 # SKIP SVE set SVE get FPSIMD for VL 1296
2055 12:28:18.715929 # ok 328 # SKIP SVE set FPSIMD get SVE for VL 1296
2056 12:28:18.716239 # ok 329 Set SVE VL 1312
2057 12:28:18.716342 # ok 330 # SKIP SVE set SVE get SVE for VL 1312
2058 12:28:18.716440 # ok 331 # SKIP SVE set SVE get FPSIMD for VL 1312
2059 12:28:18.716539 # ok 332 # SKIP SVE set FPSIMD get SVE for VL 1312
2060 12:28:18.716638 # ok 333 Set SVE VL 1328
2061 12:28:18.716720 # ok 334 # SKIP SVE set SVE get SVE for VL 1328
2062 12:28:18.716792 # ok 335 # SKIP SVE set SVE get FPSIMD for VL 1328
2063 12:28:18.716881 # ok 336 # SKIP SVE set FPSIMD get SVE for VL 1328
2064 12:28:18.716944 # ok 337 Set SVE VL 1344
2065 12:28:18.717002 # ok 338 # SKIP SVE set SVE get SVE for VL 1344
2066 12:28:18.717070 # ok 339 # SKIP SVE set SVE get FPSIMD for VL 1344
2067 12:28:18.717130 # ok 340 # SKIP SVE set FPSIMD get SVE for VL 1344
2068 12:28:18.717384 # ok 341 Set SVE VL 1360
2069 12:28:18.717470 # ok 342 # SKIP SVE set SVE get SVE for VL 1360
2070 12:28:18.717568 # ok 343 # SKIP SVE set SVE get FPSIMD for VL 1360
2071 12:28:18.717688 # ok 344 # SKIP SVE set FPSIMD get SVE for VL 1360
2072 12:28:18.717780 # ok 345 Set SVE VL 1376
2073 12:28:18.717883 # ok 346 # SKIP SVE set SVE get SVE for VL 1376
2074 12:28:18.717992 # ok 347 # SKIP SVE set SVE get FPSIMD for VL 1376
2075 12:28:18.718085 # ok 348 # SKIP SVE set FPSIMD get SVE for VL 1376
2076 12:28:18.718243 # ok 349 Set SVE VL 1392
2077 12:28:18.718429 # ok 350 # SKIP SVE set SVE get SVE for VL 1392
2078 12:28:18.718662 # ok 351 # SKIP SVE set SVE get FPSIMD for VL 1392
2079 12:28:18.718876 # ok 352 # SKIP SVE set FPSIMD get SVE for VL 1392
2080 12:28:18.719068 # ok 353 Set SVE VL 1408
2081 12:28:18.719230 # ok 354 # SKIP SVE set SVE get SVE for VL 1408
2082 12:28:18.719386 # ok 355 # SKIP SVE set SVE get FPSIMD for VL 1408
2083 12:28:18.719509 # ok 356 # SKIP SVE set FPSIMD get SVE for VL 1408
2084 12:28:18.719623 # ok 357 Set SVE VL 1424
2085 12:28:18.727519 # ok 358 # SKIP SVE set SVE get SVE for VL 1424
2086 12:28:18.727759 # ok 359 # SKIP SVE set SVE get FPSIMD for VL 1424
2087 12:28:18.728051 # ok 360 # SKIP SVE set FPSIMD get SVE for VL 1424
2088 12:28:18.728157 # ok 361 Set SVE VL 1440
2089 12:28:18.728249 # ok 362 # SKIP SVE set SVE get SVE for VL 1440
2090 12:28:18.728331 # ok 363 # SKIP SVE set SVE get FPSIMD for VL 1440
2091 12:28:18.728420 # ok 364 # SKIP SVE set FPSIMD get SVE for VL 1440
2092 12:28:18.728504 # ok 365 Set SVE VL 1456
2093 12:28:18.728613 # ok 366 # SKIP SVE set SVE get SVE for VL 1456
2094 12:28:18.728702 # ok 367 # SKIP SVE set SVE get FPSIMD for VL 1456
2095 12:28:18.728787 # ok 368 # SKIP SVE set FPSIMD get SVE for VL 1456
2096 12:28:18.728872 # ok 369 Set SVE VL 1472
2097 12:28:18.728957 # ok 370 # SKIP SVE set SVE get SVE for VL 1472
2098 12:28:18.729041 # ok 371 # SKIP SVE set SVE get FPSIMD for VL 1472
2099 12:28:18.729143 # ok 372 # SKIP SVE set FPSIMD get SVE for VL 1472
2100 12:28:18.729233 # ok 373 Set SVE VL 1488
2101 12:28:18.729313 # ok 374 # SKIP SVE set SVE get SVE for VL 1488
2102 12:28:18.729394 # ok 375 # SKIP SVE set SVE get FPSIMD for VL 1488
2103 12:28:18.729487 # ok 376 # SKIP SVE set FPSIMD get SVE for VL 1488
2104 12:28:18.729572 # ok 377 Set SVE VL 1504
2105 12:28:18.729664 # ok 378 # SKIP SVE set SVE get SVE for VL 1504
2106 12:28:18.729760 # ok 379 # SKIP SVE set SVE get FPSIMD for VL 1504
2107 12:28:18.730108 # ok 380 # SKIP SVE set FPSIMD get SVE for VL 1504
2108 12:28:18.730217 # ok 381 Set SVE VL 1520
2109 12:28:18.730325 # ok 382 # SKIP SVE set SVE get SVE for VL 1520
2110 12:28:18.730421 # ok 383 # SKIP SVE set SVE get FPSIMD for VL 1520
2111 12:28:18.730529 # ok 384 # SKIP SVE set FPSIMD get SVE for VL 1520
2112 12:28:18.730624 # ok 385 Set SVE VL 1536
2113 12:28:18.730715 # ok 386 # SKIP SVE set SVE get SVE for VL 1536
2114 12:28:18.730805 # ok 387 # SKIP SVE set SVE get FPSIMD for VL 1536
2115 12:28:18.730912 # ok 388 # SKIP SVE set FPSIMD get SVE for VL 1536
2116 12:28:18.731006 # ok 389 Set SVE VL 1552
2117 12:28:18.731094 # ok 390 # SKIP SVE set SVE get SVE for VL 1552
2118 12:28:18.731197 # ok 391 # SKIP SVE set SVE get FPSIMD for VL 1552
2119 12:28:18.731563 # ok 392 # SKIP SVE set FPSIMD get SVE for VL 1552
2120 12:28:18.732085 # ok 393 Set SVE VL 1568
2121 12:28:18.732278 # ok 394 # SKIP SVE set SVE get SVE for VL 1568
2122 12:28:18.732450 # ok 395 # SKIP SVE set SVE get FPSIMD for VL 1568
2123 12:28:18.732644 # ok 396 # SKIP SVE set FPSIMD get SVE for VL 1568
2124 12:28:18.732823 # ok 397 Set SVE VL 1584
2125 12:28:18.733026 # ok 398 # SKIP SVE set SVE get SVE for VL 1584
2126 12:28:18.733203 # ok 399 # SKIP SVE set SVE get FPSIMD for VL 1584
2127 12:28:18.733349 # ok 400 # SKIP SVE set FPSIMD get SVE for VL 1584
2128 12:28:18.733494 # ok 401 Set SVE VL 1600
2129 12:28:18.733675 # ok 402 # SKIP SVE set SVE get SVE for VL 1600
2130 12:28:18.733863 # ok 403 # SKIP SVE set SVE get FPSIMD for VL 1600
2131 12:28:18.734038 # ok 404 # SKIP SVE set FPSIMD get SVE for VL 1600
2132 12:28:18.734268 # ok 405 Set SVE VL 1616
2133 12:28:18.734467 # ok 406 # SKIP SVE set SVE get SVE for VL 1616
2134 12:28:18.734647 # ok 407 # SKIP SVE set SVE get FPSIMD for VL 1616
2135 12:28:18.734822 # ok 408 # SKIP SVE set FPSIMD get SVE for VL 1616
2136 12:28:18.735013 # ok 409 Set SVE VL 1632
2137 12:28:18.735223 # ok 410 # SKIP SVE set SVE get SVE for VL 1632
2138 12:28:18.735365 # ok 411 # SKIP SVE set SVE get FPSIMD for VL 1632
2139 12:28:18.735488 # ok 412 # SKIP SVE set FPSIMD get SVE for VL 1632
2140 12:28:18.735606 # ok 413 Set SVE VL 1648
2141 12:28:18.735724 # ok 414 # SKIP SVE set SVE get SVE for VL 1648
2142 12:28:18.735872 # ok 415 # SKIP SVE set SVE get FPSIMD for VL 1648
2143 12:28:18.735997 # ok 416 # SKIP SVE set FPSIMD get SVE for VL 1648
2144 12:28:18.736114 # ok 417 Set SVE VL 1664
2145 12:28:18.736233 # ok 418 # SKIP SVE set SVE get SVE for VL 1664
2146 12:28:18.736353 # ok 419 # SKIP SVE set SVE get FPSIMD for VL 1664
2147 12:28:18.736470 # ok 420 # SKIP SVE set FPSIMD get SVE for VL 1664
2148 12:28:18.736587 # ok 421 Set SVE VL 1680
2149 12:28:18.739603 # ok 422 # SKIP SVE set SVE get SVE for VL 1680
2150 12:28:18.739950 # ok 423 # SKIP SVE set SVE get FPSIMD for VL 1680
2151 12:28:18.740064 # ok 424 # SKIP SVE set FPSIMD get SVE for VL 1680
2152 12:28:18.740154 # ok 425 Set SVE VL 1696
2153 12:28:18.740263 # ok 426 # SKIP SVE set SVE get SVE for VL 1696
2154 12:28:18.740353 # ok 427 # SKIP SVE set SVE get FPSIMD for VL 1696
2155 12:28:18.740439 # ok 428 # SKIP SVE set FPSIMD get SVE for VL 1696
2156 12:28:18.740543 # ok 429 Set SVE VL 1712
2157 12:28:18.740634 # ok 430 # SKIP SVE set SVE get SVE for VL 1712
2158 12:28:18.740735 # ok 431 # SKIP SVE set SVE get FPSIMD for VL 1712
2159 12:28:18.740821 # ok 432 # SKIP SVE set FPSIMD get SVE for VL 1712
2160 12:28:18.740917 # ok 433 Set SVE VL 1728
2161 12:28:18.741017 # ok 434 # SKIP SVE set SVE get SVE for VL 1728
2162 12:28:18.741316 # ok 435 # SKIP SVE set SVE get FPSIMD for VL 1728
2163 12:28:18.741422 # ok 436 # SKIP SVE set FPSIMD get SVE for VL 1728
2164 12:28:18.741514 # ok 437 Set SVE VL 1744
2165 12:28:18.741622 # ok 438 # SKIP SVE set SVE get SVE for VL 1744
2166 12:28:18.741725 # ok 439 # SKIP SVE set SVE get FPSIMD for VL 1744
2167 12:28:18.741816 # ok 440 # SKIP SVE set FPSIMD get SVE for VL 1744
2168 12:28:18.741924 # ok 441 Set SVE VL 1760
2169 12:28:18.742016 # ok 442 # SKIP SVE set SVE get SVE for VL 1760
2170 12:28:18.742107 # ok 443 # SKIP SVE set SVE get FPSIMD for VL 1760
2171 12:28:18.742214 # ok 444 # SKIP SVE set FPSIMD get SVE for VL 1760
2172 12:28:18.742306 # ok 445 Set SVE VL 1776
2173 12:28:18.742395 # ok 446 # SKIP SVE set SVE get SVE for VL 1776
2174 12:28:18.742500 # ok 447 # SKIP SVE set SVE get FPSIMD for VL 1776
2175 12:28:18.742609 # ok 448 # SKIP SVE set FPSIMD get SVE for VL 1776
2176 12:28:18.742708 # ok 449 Set SVE VL 1792
2177 12:28:18.743005 # ok 450 # SKIP SVE set SVE get SVE for VL 1792
2178 12:28:18.743110 # ok 451 # SKIP SVE set SVE get FPSIMD for VL 1792
2179 12:28:18.747543 # ok 452 # SKIP SVE set FPSIMD get SVE for VL 1792
2180 12:28:18.747931 # ok 453 Set SVE VL 1808
2181 12:28:18.748041 # ok 454 # SKIP SVE set SVE get SVE for VL 1808
2182 12:28:18.748135 # ok 455 # SKIP SVE set SVE get FPSIMD for VL 1808
2183 12:28:18.748240 # ok 456 # SKIP SVE set FPSIMD get SVE for VL 1808
2184 12:28:18.748325 # ok 457 Set SVE VL 1824
2185 12:28:18.748407 # ok 458 # SKIP SVE set SVE get SVE for VL 1824
2186 12:28:18.748507 # ok 459 # SKIP SVE set SVE get FPSIMD for VL 1824
2187 12:28:18.748593 # ok 460 # SKIP SVE set FPSIMD get SVE for VL 1824
2188 12:28:18.748678 # ok 461 Set SVE VL 1840
2189 12:28:18.748778 # ok 462 # SKIP SVE set SVE get SVE for VL 1840
2190 12:28:18.748864 # ok 463 # SKIP SVE set SVE get FPSIMD for VL 1840
2191 12:28:18.748960 # ok 464 # SKIP SVE set FPSIMD get SVE for VL 1840
2192 12:28:18.749045 # ok 465 Set SVE VL 1856
2193 12:28:18.749127 # ok 466 # SKIP SVE set SVE get SVE for VL 1856
2194 12:28:18.749226 # ok 467 # SKIP SVE set SVE get FPSIMD for VL 1856
2195 12:28:18.749328 # ok 468 # SKIP SVE set FPSIMD get SVE for VL 1856
2196 12:28:18.749429 # ok 469 Set SVE VL 1872
2197 12:28:18.749534 # ok 470 # SKIP SVE set SVE get SVE for VL 1872
2198 12:28:18.749624 # ok 471 # SKIP SVE set SVE get FPSIMD for VL 1872
2199 12:28:18.749738 # ok 472 # SKIP SVE set FPSIMD get SVE for VL 1872
2200 12:28:18.749845 # ok 473 Set SVE VL 1888
2201 12:28:18.749951 # ok 474 # SKIP SVE set SVE get SVE for VL 1888
2202 12:28:18.750057 # ok 475 # SKIP SVE set SVE get FPSIMD for VL 1888
2203 12:28:18.750181 # ok 476 # SKIP SVE set FPSIMD get SVE for VL 1888
2204 12:28:18.750293 # ok 477 Set SVE VL 1904
2205 12:28:18.750642 # ok 478 # SKIP SVE set SVE get SVE for VL 1904
2206 12:28:18.750806 # ok 479 # SKIP SVE set SVE get FPSIMD for VL 1904
2207 12:28:18.769028 # ok 480 # SKIP SVE set FPSIMD get SVE for VL 1904
2208 12:28:18.769343 # ok 481 Set SVE VL 1920
2209 12:28:18.769735 # ok 482 # SKIP SVE set SVE get SVE for VL 1920
2210 12:28:18.769906 # ok 483 # SKIP SVE set SVE get FPSIMD for VL 1920
2211 12:28:18.770033 # ok 484 # SKIP SVE set FPSIMD get SVE for VL 1920
2212 12:28:18.770157 # ok 485 Set SVE VL 1936
2213 12:28:18.770307 # ok 486 # SKIP SVE set SVE get SVE for VL 1936
2214 12:28:18.770487 # ok 487 # SKIP SVE set SVE get FPSIMD for VL 1936
2215 12:28:18.770650 # ok 488 # SKIP SVE set FPSIMD get SVE for VL 1936
2216 12:28:18.770807 # ok 489 Set SVE VL 1952
2217 12:28:18.770952 # ok 490 # SKIP SVE set SVE get SVE for VL 1952
2218 12:28:18.771091 # ok 491 # SKIP SVE set SVE get FPSIMD for VL 1952
2219 12:28:18.771274 # ok 492 # SKIP SVE set FPSIMD get SVE for VL 1952
2220 12:28:18.771408 # ok 493 Set SVE VL 1968
2221 12:28:18.771523 # ok 494 # SKIP SVE set SVE get SVE for VL 1968
2222 12:28:18.771639 # ok 495 # SKIP SVE set SVE get FPSIMD for VL 1968
2223 12:28:18.771752 # ok 496 # SKIP SVE set FPSIMD get SVE for VL 1968
2224 12:28:18.771868 # ok 497 Set SVE VL 1984
2225 12:28:18.771983 # ok 498 # SKIP SVE set SVE get SVE for VL 1984
2226 12:28:18.775563 # ok 499 # SKIP SVE set SVE get FPSIMD for VL 1984
2227 12:28:18.776041 # ok 500 # SKIP SVE set FPSIMD get SVE for VL 1984
2228 12:28:18.776206 # ok 501 Set SVE VL 2000
2229 12:28:18.776384 # ok 502 # SKIP SVE set SVE get SVE for VL 2000
2230 12:28:18.776564 # ok 503 # SKIP SVE set SVE get FPSIMD for VL 2000
2231 12:28:18.776748 # ok 504 # SKIP SVE set FPSIMD get SVE for VL 2000
2232 12:28:18.776916 # ok 505 Set SVE VL 2016
2233 12:28:18.777059 # ok 506 # SKIP SVE set SVE get SVE for VL 2016
2234 12:28:18.777219 # ok 507 # SKIP SVE set SVE get FPSIMD for VL 2016
2235 12:28:18.777357 # ok 508 # SKIP SVE set FPSIMD get SVE for VL 2016
2236 12:28:18.777491 # ok 509 Set SVE VL 2032
2237 12:28:18.777659 # ok 510 # SKIP SVE set SVE get SVE for VL 2032
2238 12:28:18.777847 # ok 511 # SKIP SVE set SVE get FPSIMD for VL 2032
2239 12:28:18.778042 # ok 512 # SKIP SVE set FPSIMD get SVE for VL 2032
2240 12:28:18.778227 # ok 513 Set SVE VL 2048
2241 12:28:18.778421 # ok 514 # SKIP SVE set SVE get SVE for VL 2048
2242 12:28:18.778619 # ok 515 # SKIP SVE set SVE get FPSIMD for VL 2048
2243 12:28:18.778840 # ok 516 # SKIP SVE set FPSIMD get SVE for VL 2048
2244 12:28:18.779059 # ok 517 Set SVE VL 2064
2245 12:28:18.779277 # ok 518 # SKIP SVE set SVE get SVE for VL 2064
2246 12:28:18.779420 # ok 519 # SKIP SVE set SVE get FPSIMD for VL 2064
2247 12:28:18.779542 # ok 520 # SKIP SVE set FPSIMD get SVE for VL 2064
2248 12:28:18.779662 # ok 521 Set SVE VL 2080
2249 12:28:18.779779 # ok 522 # SKIP SVE set SVE get SVE for VL 2080
2250 12:28:18.779898 # ok 523 # SKIP SVE set SVE get FPSIMD for VL 2080
2251 12:28:18.780015 # ok 524 # SKIP SVE set FPSIMD get SVE for VL 2080
2252 12:28:18.780132 # ok 525 Set SVE VL 2096
2253 12:28:18.780251 # ok 526 # SKIP SVE set SVE get SVE for VL 2096
2254 12:28:18.782770 # ok 527 # SKIP SVE set SVE get FPSIMD for VL 2096
2255 12:28:18.782911 # ok 528 # SKIP SVE set FPSIMD get SVE for VL 2096
2256 12:28:18.783007 # ok 529 Set SVE VL 2112
2257 12:28:18.783109 # ok 530 # SKIP SVE set SVE get SVE for VL 2112
2258 12:28:18.783603 # ok 531 # SKIP SVE set SVE get FPSIMD for VL 2112
2259 12:28:18.783909 # ok 532 # SKIP SVE set FPSIMD get SVE for VL 2112
2260 12:28:18.784019 # ok 533 Set SVE VL 2128
2261 12:28:18.784123 # ok 534 # SKIP SVE set SVE get SVE for VL 2128
2262 12:28:18.784215 # ok 535 # SKIP SVE set SVE get FPSIMD for VL 2128
2263 12:28:18.784316 # ok 536 # SKIP SVE set FPSIMD get SVE for VL 2128
2264 12:28:18.784405 # ok 537 Set SVE VL 2144
2265 12:28:18.784502 # ok 538 # SKIP SVE set SVE get SVE for VL 2144
2266 12:28:18.784612 # ok 539 # SKIP SVE set SVE get FPSIMD for VL 2144
2267 12:28:18.784915 # ok 540 # SKIP SVE set FPSIMD get SVE for VL 2144
2268 12:28:18.785029 # ok 541 Set SVE VL 2160
2269 12:28:18.785115 # ok 542 # SKIP SVE set SVE get SVE for VL 2160
2270 12:28:18.785214 # ok 543 # SKIP SVE set SVE get FPSIMD for VL 2160
2271 12:28:18.785313 # ok 544 # SKIP SVE set FPSIMD get SVE for VL 2160
2272 12:28:18.785408 # ok 545 Set SVE VL 2176
2273 12:28:18.785714 # ok 546 # SKIP SVE set SVE get SVE for VL 2176
2274 12:28:18.786009 # ok 547 # SKIP SVE set SVE get FPSIMD for VL 2176
2275 12:28:18.786110 # ok 548 # SKIP SVE set FPSIMD get SVE for VL 2176
2276 12:28:18.786195 # ok 549 Set SVE VL 2192
2277 12:28:18.786277 # ok 550 # SKIP SVE set SVE get SVE for VL 2192
2278 12:28:18.786379 # ok 551 # SKIP SVE set SVE get FPSIMD for VL 2192
2279 12:28:18.786469 # ok 552 # SKIP SVE set FPSIMD get SVE for VL 2192
2280 12:28:18.786554 # ok 553 Set SVE VL 2208
2281 12:28:18.786655 # ok 554 # SKIP SVE set SVE get SVE for VL 2208
2282 12:28:18.786758 # ok 555 # SKIP SVE set SVE get FPSIMD for VL 2208
2283 12:28:18.786844 # ok 556 # SKIP SVE set FPSIMD get SVE for VL 2208
2284 12:28:18.786946 # ok 557 Set SVE VL 2224
2285 12:28:18.787273 # ok 558 # SKIP SVE set SVE get SVE for VL 2224
2286 12:28:18.787472 # ok 559 # SKIP SVE set SVE get FPSIMD for VL 2224
2287 12:28:18.787635 # ok 560 # SKIP SVE set FPSIMD get SVE for VL 2224
2288 12:28:18.787767 # ok 561 Set SVE VL 2240
2289 12:28:18.787894 # ok 562 # SKIP SVE set SVE get SVE for VL 2240
2290 12:28:18.788053 # ok 563 # SKIP SVE set SVE get FPSIMD for VL 2240
2291 12:28:18.788211 # ok 564 # SKIP SVE set FPSIMD get SVE for VL 2240
2292 12:28:18.788357 # ok 565 Set SVE VL 2256
2293 12:28:18.788555 # ok 566 # SKIP SVE set SVE get SVE for VL 2256
2294 12:28:18.788695 # ok 567 # SKIP SVE set SVE get FPSIMD for VL 2256
2295 12:28:18.788861 # ok 568 # SKIP SVE set FPSIMD get SVE for VL 2256
2296 12:28:18.789015 # ok 569 Set SVE VL 2272
2297 12:28:18.789259 # ok 570 # SKIP SVE set SVE get SVE for VL 2272
2298 12:28:18.789501 # ok 571 # SKIP SVE set SVE get FPSIMD for VL 2272
2299 12:28:18.789693 # ok 572 # SKIP SVE set FPSIMD get SVE for VL 2272
2300 12:28:18.789862 # ok 573 Set SVE VL 2288
2301 12:28:18.790044 # ok 574 # SKIP SVE set SVE get SVE for VL 2288
2302 12:28:18.790258 # ok 575 # SKIP SVE set SVE get FPSIMD for VL 2288
2303 12:28:18.790486 # ok 576 # SKIP SVE set FPSIMD get SVE for VL 2288
2304 12:28:18.790671 # ok 577 Set SVE VL 2304
2305 12:28:18.790880 # ok 578 # SKIP SVE set SVE get SVE for VL 2304
2306 12:28:18.791059 # ok 579 # SKIP SVE set SVE get FPSIMD for VL 2304
2307 12:28:18.791199 # ok 580 # SKIP SVE set FPSIMD get SVE for VL 2304
2308 12:28:18.791322 # ok 581 Set SVE VL 2320
2309 12:28:18.791487 # ok 582 # SKIP SVE set SVE get SVE for VL 2320
2310 12:28:18.791617 # ok 583 # SKIP SVE set SVE get FPSIMD for VL 2320
2311 12:28:18.791739 # ok 584 # SKIP SVE set FPSIMD get SVE for VL 2320
2312 12:28:18.791860 # ok 585 Set SVE VL 2336
2313 12:28:18.791980 # ok 586 # SKIP SVE set SVE get SVE for VL 2336
2314 12:28:18.792101 # ok 587 # SKIP SVE set SVE get FPSIMD for VL 2336
2315 12:28:18.792224 # ok 588 # SKIP SVE set FPSIMD get SVE for VL 2336
2316 12:28:18.792347 # ok 589 Set SVE VL 2352
2317 12:28:18.792469 # ok 590 # SKIP SVE set SVE get SVE for VL 2352
2318 12:28:18.792593 # ok 591 # SKIP SVE set SVE get FPSIMD for VL 2352
2319 12:28:18.792715 # ok 592 # SKIP SVE set FPSIMD get SVE for VL 2352
2320 12:28:18.792865 # ok 593 Set SVE VL 2368
2321 12:28:18.792989 # ok 594 # SKIP SVE set SVE get SVE for VL 2368
2322 12:28:18.793112 # ok 595 # SKIP SVE set SVE get FPSIMD for VL 2368
2323 12:28:18.793241 # ok 596 # SKIP SVE set FPSIMD get SVE for VL 2368
2324 12:28:18.793360 # ok 597 Set SVE VL 2384
2325 12:28:18.793474 # ok 598 # SKIP SVE set SVE get SVE for VL 2384
2326 12:28:18.793587 # ok 599 # SKIP SVE set SVE get FPSIMD for VL 2384
2327 12:28:18.793786 # ok 600 # SKIP SVE set FPSIMD get SVE for VL 2384
2328 12:28:18.794241 # ok 601 Set SVE VL 2400
2329 12:28:18.794434 # ok 602 # SKIP SVE set SVE get SVE for VL 2400
2330 12:28:18.794639 # ok 603 # SKIP SVE set SVE get FPSIMD for VL 2400
2331 12:28:18.794867 # ok 604 # SKIP SVE set FPSIMD get SVE for VL 2400
2332 12:28:18.795082 # ok 605 Set SVE VL 2416
2333 12:28:18.795304 # ok 606 # SKIP SVE set SVE get SVE for VL 2416
2334 12:28:18.795502 # ok 607 # SKIP SVE set SVE get FPSIMD for VL 2416
2335 12:28:18.795689 # ok 608 # SKIP SVE set FPSIMD get SVE for VL 2416
2336 12:28:18.795906 # ok 609 Set SVE VL 2432
2337 12:28:18.796093 # ok 610 # SKIP SVE set SVE get SVE for VL 2432
2338 12:28:18.796303 # ok 611 # SKIP SVE set SVE get FPSIMD for VL 2432
2339 12:28:18.796488 # ok 612 # SKIP SVE set FPSIMD get SVE for VL 2432
2340 12:28:18.796680 # ok 613 Set SVE VL 2448
2341 12:28:18.796891 # ok 614 # SKIP SVE set SVE get SVE for VL 2448
2342 12:28:18.797147 # ok 615 # SKIP SVE set SVE get FPSIMD for VL 2448
2343 12:28:18.797362 # ok 616 # SKIP SVE set FPSIMD get SVE for VL 2448
2344 12:28:18.797548 # ok 617 Set SVE VL 2464
2345 12:28:18.797738 # ok 618 # SKIP SVE set SVE get SVE for VL 2464
2346 12:28:18.797944 # ok 619 # SKIP SVE set SVE get FPSIMD for VL 2464
2347 12:28:18.798126 # ok 620 # SKIP SVE set FPSIMD get SVE for VL 2464
2348 12:28:18.798304 # ok 621 Set SVE VL 2480
2349 12:28:18.798513 # ok 622 # SKIP SVE set SVE get SVE for VL 2480
2350 12:28:18.798719 # ok 623 # SKIP SVE set SVE get FPSIMD for VL 2480
2351 12:28:18.798905 # ok 624 # SKIP SVE set FPSIMD get SVE for VL 2480
2352 12:28:18.799132 # ok 625 Set SVE VL 2496
2353 12:28:18.799355 # ok 626 # SKIP SVE set SVE get SVE for VL 2496
2354 12:28:18.799542 # ok 627 # SKIP SVE set SVE get FPSIMD for VL 2496
2355 12:28:18.799718 # ok 628 # SKIP SVE set FPSIMD get SVE for VL 2496
2356 12:28:18.799895 # ok 629 Set SVE VL 2512
2357 12:28:18.800099 # ok 630 # SKIP SVE set SVE get SVE for VL 2512
2358 12:28:18.800282 # ok 631 # SKIP SVE set SVE get FPSIMD for VL 2512
2359 12:28:18.800459 # ok 632 # SKIP SVE set FPSIMD get SVE for VL 2512
2360 12:28:18.800646 # ok 633 Set SVE VL 2528
2361 12:28:18.800904 # ok 634 # SKIP SVE set SVE get SVE for VL 2528
2362 12:28:18.801118 # ok 635 # SKIP SVE set SVE get FPSIMD for VL 2528
2363 12:28:18.801339 # ok 636 # SKIP SVE set FPSIMD get SVE for VL 2528
2364 12:28:18.801553 # ok 637 Set SVE VL 2544
2365 12:28:18.801710 # ok 638 # SKIP SVE set SVE get SVE for VL 2544
2366 12:28:18.801832 # ok 639 # SKIP SVE set SVE get FPSIMD for VL 2544
2367 12:28:18.801952 # ok 640 # SKIP SVE set FPSIMD get SVE for VL 2544
2368 12:28:18.802071 # ok 641 Set SVE VL 2560
2369 12:28:18.802187 # ok 642 # SKIP SVE set SVE get SVE for VL 2560
2370 12:28:18.802306 # ok 643 # SKIP SVE set SVE get FPSIMD for VL 2560
2371 12:28:18.802423 # ok 644 # SKIP SVE set FPSIMD get SVE for VL 2560
2372 12:28:18.802769 # ok 645 Set SVE VL 2576
2373 12:28:18.802900 # ok 646 # SKIP SVE set SVE get SVE for VL 2576
2374 12:28:18.803020 # ok 647 # SKIP SVE set SVE get FPSIMD for VL 2576
2375 12:28:18.803140 # ok 648 # SKIP SVE set FPSIMD get SVE for VL 2576
2376 12:28:18.803259 # ok 649 Set SVE VL 2592
2377 12:28:18.803385 # ok 650 # SKIP SVE set SVE get SVE for VL 2592
2378 12:28:18.803503 # ok 651 # SKIP SVE set SVE get FPSIMD for VL 2592
2379 12:28:18.803623 # ok 652 # SKIP SVE set FPSIMD get SVE for VL 2592
2380 12:28:18.803742 # ok 653 Set SVE VL 2608
2381 12:28:18.803858 # ok 654 # SKIP SVE set SVE get SVE for VL 2608
2382 12:28:18.803977 # ok 655 # SKIP SVE set SVE get FPSIMD for VL 2608
2383 12:28:18.804094 # ok 656 # SKIP SVE set FPSIMD get SVE for VL 2608
2384 12:28:18.804210 # ok 657 Set SVE VL 2624
2385 12:28:18.804329 # ok 658 # SKIP SVE set SVE get SVE for VL 2624
2386 12:28:18.804446 # ok 659 # SKIP SVE set SVE get FPSIMD for VL 2624
2387 12:28:18.804562 # ok 660 # SKIP SVE set FPSIMD get SVE for VL 2624
2388 12:28:18.804678 # ok 661 Set SVE VL 2640
2389 12:28:18.804794 # ok 662 # SKIP SVE set SVE get SVE for VL 2640
2390 12:28:18.804911 # ok 663 # SKIP SVE set SVE get FPSIMD for VL 2640
2391 12:28:18.805028 # ok 664 # SKIP SVE set FPSIMD get SVE for VL 2640
2392 12:28:18.805146 # ok 665 Set SVE VL 2656
2393 12:28:18.805263 # ok 666 # SKIP SVE set SVE get SVE for VL 2656
2394 12:28:18.810711 # ok 667 # SKIP SVE set SVE get FPSIMD for VL 2656
2395 12:28:18.811235 # ok 668 # SKIP SVE set FPSIMD get SVE for VL 2656
2396 12:28:18.811398 # ok 669 Set SVE VL 2672
2397 12:28:18.811525 # ok 670 # SKIP SVE set SVE get SVE for VL 2672
2398 12:28:18.811716 # ok 671 # SKIP SVE set SVE get FPSIMD for VL 2672
2399 12:28:18.811921 # ok 672 # SKIP SVE set FPSIMD get SVE for VL 2672
2400 12:28:18.812128 # ok 673 Set SVE VL 2688
2401 12:28:18.812306 # ok 674 # SKIP SVE set SVE get SVE for VL 2688
2402 12:28:18.812510 # ok 675 # SKIP SVE set SVE get FPSIMD for VL 2688
2403 12:28:18.812705 # ok 676 # SKIP SVE set FPSIMD get SVE for VL 2688
2404 12:28:18.812898 # ok 677 Set SVE VL 2704
2405 12:28:18.813098 # ok 678 # SKIP SVE set SVE get SVE for VL 2704
2406 12:28:18.813295 # ok 679 # SKIP SVE set SVE get FPSIMD for VL 2704
2407 12:28:18.813480 # ok 680 # SKIP SVE set FPSIMD get SVE for VL 2704
2408 12:28:18.813752 # ok 681 Set SVE VL 2720
2409 12:28:18.814014 # ok 682 # SKIP SVE set SVE get SVE for VL 2720
2410 12:28:18.814234 # ok 683 # SKIP SVE set SVE get FPSIMD for VL 2720
2411 12:28:18.814444 # ok 684 # SKIP SVE set FPSIMD get SVE for VL 2720
2412 12:28:18.814652 # ok 685 Set SVE VL 2736
2413 12:28:18.814880 # ok 686 # SKIP SVE set SVE get SVE for VL 2736
2414 12:28:18.815119 # ok 687 # SKIP SVE set SVE get FPSIMD for VL 2736
2415 12:28:18.815332 # ok 688 # SKIP SVE set FPSIMD get SVE for VL 2736
2416 12:28:18.815581 # ok 689 Set SVE VL 2752
2417 12:28:18.815818 # ok 690 # SKIP SVE set SVE get SVE for VL 2752
2418 12:28:18.816062 # ok 691 # SKIP SVE set SVE get FPSIMD for VL 2752
2419 12:28:18.816264 # ok 692 # SKIP SVE set FPSIMD get SVE for VL 2752
2420 12:28:18.816446 # ok 693 Set SVE VL 2768
2421 12:28:18.816610 # ok 694 # SKIP SVE set SVE get SVE for VL 2768
2422 12:28:18.816775 # ok 695 # SKIP SVE set SVE get FPSIMD for VL 2768
2423 12:28:18.816936 # ok 696 # SKIP SVE set FPSIMD get SVE for VL 2768
2424 12:28:18.817149 # ok 697 Set SVE VL 2784
2425 12:28:18.817346 # ok 698 # SKIP SVE set SVE get SVE for VL 2784
2426 12:28:18.817515 # ok 699 # SKIP SVE set SVE get FPSIMD for VL 2784
2427 12:28:18.817693 # ok 700 # SKIP SVE set FPSIMD get SVE for VL 2784
2428 12:28:18.817895 # ok 701 Set SVE VL 2800
2429 12:28:18.818099 # ok 702 # SKIP SVE set SVE get SVE for VL 2800
2430 12:28:18.818306 # ok 703 # SKIP SVE set SVE get FPSIMD for VL 2800
2431 12:28:18.818517 # ok 704 # SKIP SVE set FPSIMD get SVE for VL 2800
2432 12:28:18.818739 # ok 705 Set SVE VL 2816
2433 12:28:18.818967 # ok 706 # SKIP SVE set SVE get SVE for VL 2816
2434 12:28:18.819196 # ok 707 # SKIP SVE set SVE get FPSIMD for VL 2816
2435 12:28:18.819424 # ok 708 # SKIP SVE set FPSIMD get SVE for VL 2816
2436 12:28:18.819574 # ok 709 Set SVE VL 2832
2437 12:28:18.819695 # ok 710 # SKIP SVE set SVE get SVE for VL 2832
2438 12:28:18.819813 # ok 711 # SKIP SVE set SVE get FPSIMD for VL 2832
2439 12:28:18.820174 # ok 712 # SKIP SVE set FPSIMD get SVE for VL 2832
2440 12:28:18.820305 # ok 713 Set SVE VL 2848
2441 12:28:18.820424 # ok 714 # SKIP SVE set SVE get SVE for VL 2848
2442 12:28:18.820541 # ok 715 # SKIP SVE set SVE get FPSIMD for VL 2848
2443 12:28:18.820658 # ok 716 # SKIP SVE set FPSIMD get SVE for VL 2848
2444 12:28:18.820775 # ok 717 Set SVE VL 2864
2445 12:28:18.820891 # ok 718 # SKIP SVE set SVE get SVE for VL 2864
2446 12:28:18.821007 # ok 719 # SKIP SVE set SVE get FPSIMD for VL 2864
2447 12:28:18.821123 # ok 720 # SKIP SVE set FPSIMD get SVE for VL 2864
2448 12:28:18.821239 # ok 721 Set SVE VL 2880
2449 12:28:18.821359 # ok 722 # SKIP SVE set SVE get SVE for VL 2880
2450 12:28:18.821476 # ok 723 # SKIP SVE set SVE get FPSIMD for VL 2880
2451 12:28:18.821591 # ok 724 # SKIP SVE set FPSIMD get SVE for VL 2880
2452 12:28:18.821747 # ok 725 Set SVE VL 2896
2453 12:28:18.821952 # ok 726 # SKIP SVE set SVE get SVE for VL 2896
2454 12:28:18.822159 # ok 727 # SKIP SVE set SVE get FPSIMD for VL 2896
2455 12:28:18.822333 # ok 728 # SKIP SVE set FPSIMD get SVE for VL 2896
2456 12:28:18.822549 # ok 729 Set SVE VL 2912
2457 12:28:18.822752 # ok 730 # SKIP SVE set SVE get SVE for VL 2912
2458 12:28:18.822963 # ok 731 # SKIP SVE set SVE get FPSIMD for VL 2912
2459 12:28:18.823178 # ok 732 # SKIP SVE set FPSIMD get SVE for VL 2912
2460 12:28:18.823362 # ok 733 Set SVE VL 2928
2461 12:28:18.823541 # ok 734 # SKIP SVE set SVE get SVE for VL 2928
2462 12:28:18.823730 # ok 735 # SKIP SVE set SVE get FPSIMD for VL 2928
2463 12:28:18.823917 # ok 736 # SKIP SVE set FPSIMD get SVE for VL 2928
2464 12:28:18.824125 # ok 737 Set SVE VL 2944
2465 12:28:18.824333 # ok 738 # SKIP SVE set SVE get SVE for VL 2944
2466 12:28:18.824536 # ok 739 # SKIP SVE set SVE get FPSIMD for VL 2944
2467 12:28:18.824724 # ok 740 # SKIP SVE set FPSIMD get SVE for VL 2944
2468 12:28:18.824934 # ok 741 Set SVE VL 2960
2469 12:28:18.825113 # ok 742 # SKIP SVE set SVE get SVE for VL 2960
2470 12:28:18.825299 # ok 743 # SKIP SVE set SVE get FPSIMD for VL 2960
2471 12:28:18.825487 # ok 744 # SKIP SVE set FPSIMD get SVE for VL 2960
2472 12:28:18.826289 # ok 745 Set SVE VL 2976
2473 12:28:18.826490 # ok 746 # SKIP SVE set SVE get SVE for VL 2976
2474 12:28:18.826732 # ok 747 # SKIP SVE set SVE get FPSIMD for VL 2976
2475 12:28:18.826958 # ok 748 # SKIP SVE set FPSIMD get SVE for VL 2976
2476 12:28:18.827167 # ok 749 Set SVE VL 2992
2477 12:28:18.827375 # ok 750 # SKIP SVE set SVE get SVE for VL 2992
2478 12:28:18.827558 # ok 751 # SKIP SVE set SVE get FPSIMD for VL 2992
2479 12:28:18.827725 # ok 752 # SKIP SVE set FPSIMD get SVE for VL 2992
2480 12:28:18.827886 # ok 753 Set SVE VL 3008
2481 12:28:18.828048 # ok 754 # SKIP SVE set SVE get SVE for VL 3008
2482 12:28:18.828218 # ok 755 # SKIP SVE set SVE get FPSIMD for VL 3008
2483 12:28:18.828634 # ok 756 # SKIP SVE set FPSIMD get SVE for VL 3008
2484 12:28:18.828735 # ok 757 Set SVE VL 3024
2485 12:28:18.828819 # ok 758 # SKIP SVE set SVE get SVE for VL 3024
2486 12:28:18.828903 # ok 759 # SKIP SVE set SVE get FPSIMD for VL 3024
2487 12:28:18.828985 # ok 760 # SKIP SVE set FPSIMD get SVE for VL 3024
2488 12:28:18.829066 # ok 761 Set SVE VL 3040
2489 12:28:18.829145 # ok 762 # SKIP SVE set SVE get SVE for VL 3040
2490 12:28:18.829215 # ok 763 # SKIP SVE set SVE get FPSIMD for VL 3040
2491 12:28:18.829284 # ok 764 # SKIP SVE set FPSIMD get SVE for VL 3040
2492 12:28:18.829356 # ok 765 Set SVE VL 3056
2493 12:28:18.829430 # ok 766 # SKIP SVE set SVE get SVE for VL 3056
2494 12:28:18.829509 # ok 767 # SKIP SVE set SVE get FPSIMD for VL 3056
2495 12:28:18.829580 # ok 768 # SKIP SVE set FPSIMD get SVE for VL 3056
2496 12:28:18.829664 # ok 769 Set SVE VL 3072
2497 12:28:18.829740 # ok 770 # SKIP SVE set SVE get SVE for VL 3072
2498 12:28:18.829820 # ok 771 # SKIP SVE set SVE get FPSIMD for VL 3072
2499 12:28:18.829901 # ok 772 # SKIP SVE set FPSIMD get SVE for VL 3072
2500 12:28:18.829982 # ok 773 Set SVE VL 3088
2501 12:28:18.830060 # ok 774 # SKIP SVE set SVE get SVE for VL 3088
2502 12:28:18.830141 # ok 775 # SKIP SVE set SVE get FPSIMD for VL 3088
2503 12:28:18.830221 # ok 776 # SKIP SVE set FPSIMD get SVE for VL 3088
2504 12:28:18.830301 # ok 777 Set SVE VL 3104
2505 12:28:18.830379 # ok 778 # SKIP SVE set SVE get SVE for VL 3104
2506 12:28:18.830460 # ok 779 # SKIP SVE set SVE get FPSIMD for VL 3104
2507 12:28:18.830541 # ok 780 # SKIP SVE set FPSIMD get SVE for VL 3104
2508 12:28:18.830622 # ok 781 Set SVE VL 3120
2509 12:28:18.830702 # ok 782 # SKIP SVE set SVE get SVE for VL 3120
2510 12:28:18.830782 # ok 783 # SKIP SVE set SVE get FPSIMD for VL 3120
2511 12:28:18.830861 # ok 784 # SKIP SVE set FPSIMD get SVE for VL 3120
2512 12:28:18.830940 # ok 785 Set SVE VL 3136
2513 12:28:18.831026 # ok 786 # SKIP SVE set SVE get SVE for VL 3136
2514 12:28:18.831108 # ok 787 # SKIP SVE set SVE get FPSIMD for VL 3136
2515 12:28:18.831188 # ok 788 # SKIP SVE set FPSIMD get SVE for VL 3136
2516 12:28:18.831268 # ok 789 Set SVE VL 3152
2517 12:28:18.831350 # ok 790 # SKIP SVE set SVE get SVE for VL 3152
2518 12:28:18.831434 # ok 791 # SKIP SVE set SVE get FPSIMD for VL 3152
2519 12:28:18.831517 # ok 792 # SKIP SVE set FPSIMD get SVE for VL 3152
2520 12:28:18.831598 # ok 793 Set SVE VL 3168
2521 12:28:18.831677 # ok 794 # SKIP SVE set SVE get SVE for VL 3168
2522 12:28:18.831757 # ok 795 # SKIP SVE set SVE get FPSIMD for VL 3168
2523 12:28:18.831836 # ok 796 # SKIP SVE set FPSIMD get SVE for VL 3168
2524 12:28:18.831917 # ok 797 Set SVE VL 3184
2525 12:28:18.831998 # ok 798 # SKIP SVE set SVE get SVE for VL 3184
2526 12:28:18.832298 # ok 799 # SKIP SVE set SVE get FPSIMD for VL 3184
2527 12:28:18.832390 # ok 800 # SKIP SVE set FPSIMD get SVE for VL 3184
2528 12:28:18.832472 # ok 801 Set SVE VL 3200
2529 12:28:18.832544 # ok 802 # SKIP SVE set SVE get SVE for VL 3200
2530 12:28:18.832614 # ok 803 # SKIP SVE set SVE get FPSIMD for VL 3200
2531 12:28:18.832690 # ok 804 # SKIP SVE set FPSIMD get SVE for VL 3200
2532 12:28:18.832766 # ok 805 Set SVE VL 3216
2533 12:28:18.832837 # ok 806 # SKIP SVE set SVE get SVE for VL 3216
2534 12:28:18.832907 # ok 807 # SKIP SVE set SVE get FPSIMD for VL 3216
2535 12:28:18.832983 # ok 808 # SKIP SVE set FPSIMD get SVE for VL 3216
2536 12:28:18.833057 # ok 809 Set SVE VL 3232
2537 12:28:18.833131 # ok 810 # SKIP SVE set SVE get SVE for VL 3232
2538 12:28:18.833204 # ok 811 # SKIP SVE set SVE get FPSIMD for VL 3232
2539 12:28:18.833286 # ok 812 # SKIP SVE set FPSIMD get SVE for VL 3232
2540 12:28:18.833369 # ok 813 Set SVE VL 3248
2541 12:28:18.833452 # ok 814 # SKIP SVE set SVE get SVE for VL 3248
2542 12:28:18.833535 # ok 815 # SKIP SVE set SVE get FPSIMD for VL 3248
2543 12:28:18.833618 # ok 816 # SKIP SVE set FPSIMD get SVE for VL 3248
2544 12:28:18.833715 # ok 817 Set SVE VL 3264
2545 12:28:18.833800 # ok 818 # SKIP SVE set SVE get SVE for VL 3264
2546 12:28:18.833885 # ok 819 # SKIP SVE set SVE get FPSIMD for VL 3264
2547 12:28:18.833966 # ok 820 # SKIP SVE set FPSIMD get SVE for VL 3264
2548 12:28:18.834048 # ok 821 Set SVE VL 3280
2549 12:28:18.834128 # ok 822 # SKIP SVE set SVE get SVE for VL 3280
2550 12:28:18.834200 # ok 823 # SKIP SVE set SVE get FPSIMD for VL 3280
2551 12:28:18.834276 # ok 824 # SKIP SVE set FPSIMD get SVE for VL 3280
2552 12:28:18.834360 # ok 825 Set SVE VL 3296
2553 12:28:18.834444 # ok 826 # SKIP SVE set SVE get SVE for VL 3296
2554 12:28:18.834525 # ok 827 # SKIP SVE set SVE get FPSIMD for VL 3296
2555 12:28:18.834599 # ok 828 # SKIP SVE set FPSIMD get SVE for VL 3296
2556 12:28:18.834671 # ok 829 Set SVE VL 3312
2557 12:28:18.834742 # ok 830 # SKIP SVE set SVE get SVE for VL 3312
2558 12:28:18.834817 # ok 831 # SKIP SVE set SVE get FPSIMD for VL 3312
2559 12:28:18.834905 # ok 832 # SKIP SVE set FPSIMD get SVE for VL 3312
2560 12:28:18.834991 # ok 833 Set SVE VL 3328
2561 12:28:18.835066 # ok 834 # SKIP SVE set SVE get SVE for VL 3328
2562 12:28:18.835145 # ok 835 # SKIP SVE set SVE get FPSIMD for VL 3328
2563 12:28:18.835229 # ok 836 # SKIP SVE set FPSIMD get SVE for VL 3328
2564 12:28:18.835311 # ok 837 Set SVE VL 3344
2565 12:28:18.835388 # ok 838 # SKIP SVE set SVE get SVE for VL 3344
2566 12:28:18.835473 # ok 839 # SKIP SVE set SVE get FPSIMD for VL 3344
2567 12:28:18.835555 # ok 840 # SKIP SVE set FPSIMD get SVE for VL 3344
2568 12:28:18.835638 # ok 841 Set SVE VL 3360
2569 12:28:18.835721 # ok 842 # SKIP SVE set SVE get SVE for VL 3360
2570 12:28:18.836047 # ok 843 # SKIP SVE set SVE get FPSIMD for VL 3360
2571 12:28:18.836157 # ok 844 # SKIP SVE set FPSIMD get SVE for VL 3360
2572 12:28:18.836250 # ok 845 Set SVE VL 3376
2573 12:28:18.836334 # ok 846 # SKIP SVE set SVE get SVE for VL 3376
2574 12:28:18.836418 # ok 847 # SKIP SVE set SVE get FPSIMD for VL 3376
2575 12:28:18.836501 # ok 848 # SKIP SVE set FPSIMD get SVE for VL 3376
2576 12:28:18.836587 # ok 849 Set SVE VL 3392
2577 12:28:18.836673 # ok 850 # SKIP SVE set SVE get SVE for VL 3392
2578 12:28:18.836758 # ok 851 # SKIP SVE set SVE get FPSIMD for VL 3392
2579 12:28:18.836847 # ok 852 # SKIP SVE set FPSIMD get SVE for VL 3392
2580 12:28:18.836932 # ok 853 Set SVE VL 3408
2581 12:28:18.837016 # ok 854 # SKIP SVE set SVE get SVE for VL 3408
2582 12:28:18.837096 # ok 855 # SKIP SVE set SVE get FPSIMD for VL 3408
2583 12:28:18.837176 # ok 856 # SKIP SVE set FPSIMD get SVE for VL 3408
2584 12:28:18.837258 # ok 857 Set SVE VL 3424
2585 12:28:18.837365 # ok 858 # SKIP SVE set SVE get SVE for VL 3424
2586 12:28:18.837456 # ok 859 # SKIP SVE set SVE get FPSIMD for VL 3424
2587 12:28:18.837539 # ok 860 # SKIP SVE set FPSIMD get SVE for VL 3424
2588 12:28:18.841823 # ok 861 Set SVE VL 3440
2589 12:28:18.841943 # ok 862 # SKIP SVE set SVE get SVE for VL 3440
2590 12:28:18.842029 # ok 863 # SKIP SVE set SVE get FPSIMD for VL 3440
2591 12:28:18.842112 # ok 864 # SKIP SVE set FPSIMD get SVE for VL 3440
2592 12:28:18.842195 # ok 865 Set SVE VL 3456
2593 12:28:18.842277 # ok 866 # SKIP SVE set SVE get SVE for VL 3456
2594 12:28:18.842361 # ok 867 # SKIP SVE set SVE get FPSIMD for VL 3456
2595 12:28:18.842449 # ok 868 # SKIP SVE set FPSIMD get SVE for VL 3456
2596 12:28:18.842530 # ok 869 Set SVE VL 3472
2597 12:28:18.842651 # ok 870 # SKIP SVE set SVE get SVE for VL 3472
2598 12:28:18.842737 # ok 871 # SKIP SVE set SVE get FPSIMD for VL 3472
2599 12:28:18.842821 # ok 872 # SKIP SVE set FPSIMD get SVE for VL 3472
2600 12:28:18.842904 # ok 873 Set SVE VL 3488
2601 12:28:18.842987 # ok 874 # SKIP SVE set SVE get SVE for VL 3488
2602 12:28:18.843070 # ok 875 # SKIP SVE set SVE get FPSIMD for VL 3488
2603 12:28:18.843152 # ok 876 # SKIP SVE set FPSIMD get SVE for VL 3488
2604 12:28:18.843235 # ok 877 Set SVE VL 3504
2605 12:28:18.843317 # ok 878 # SKIP SVE set SVE get SVE for VL 3504
2606 12:28:18.843404 # ok 879 # SKIP SVE set SVE get FPSIMD for VL 3504
2607 12:28:18.843486 # ok 880 # SKIP SVE set FPSIMD get SVE for VL 3504
2608 12:28:18.843609 # ok 881 Set SVE VL 3520
2609 12:28:18.843700 # ok 882 # SKIP SVE set SVE get SVE for VL 3520
2610 12:28:18.843783 # ok 883 # SKIP SVE set SVE get FPSIMD for VL 3520
2611 12:28:18.843866 # ok 884 # SKIP SVE set FPSIMD get SVE for VL 3520
2612 12:28:18.843948 # ok 885 Set SVE VL 3536
2613 12:28:18.844030 # ok 886 # SKIP SVE set SVE get SVE for VL 3536
2614 12:28:18.849478 # ok 887 # SKIP SVE set SVE get FPSIMD for VL 3536
2615 12:28:18.849704 # ok 888 # SKIP SVE set FPSIMD get SVE for VL 3536
2616 12:28:18.849799 # ok 889 Set SVE VL 3552
2617 12:28:18.849883 # ok 890 # SKIP SVE set SVE get SVE for VL 3552
2618 12:28:18.849966 # ok 891 # SKIP SVE set SVE get FPSIMD for VL 3552
2619 12:28:18.850051 # ok 892 # SKIP SVE set FPSIMD get SVE for VL 3552
2620 12:28:18.850136 # ok 893 Set SVE VL 3568
2621 12:28:18.850219 # ok 894 # SKIP SVE set SVE get SVE for VL 3568
2622 12:28:18.850302 # ok 895 # SKIP SVE set SVE get FPSIMD for VL 3568
2623 12:28:18.850384 # ok 896 # SKIP SVE set FPSIMD get SVE for VL 3568
2624 12:28:18.850466 # ok 897 Set SVE VL 3584
2625 12:28:18.850546 # ok 898 # SKIP SVE set SVE get SVE for VL 3584
2626 12:28:18.850628 # ok 899 # SKIP SVE set SVE get FPSIMD for VL 3584
2627 12:28:18.850711 # ok 900 # SKIP SVE set FPSIMD get SVE for VL 3584
2628 12:28:18.850795 # ok 901 Set SVE VL 3600
2629 12:28:18.850879 # ok 902 # SKIP SVE set SVE get SVE for VL 3600
2630 12:28:18.850963 # ok 903 # SKIP SVE set SVE get FPSIMD for VL 3600
2631 12:28:18.851048 # ok 904 # SKIP SVE set FPSIMD get SVE for VL 3600
2632 12:28:18.851130 # ok 905 Set SVE VL 3616
2633 12:28:18.851215 # ok 906 # SKIP SVE set SVE get SVE for VL 3616
2634 12:28:18.851301 # ok 907 # SKIP SVE set SVE get FPSIMD for VL 3616
2635 12:28:18.851387 # ok 908 # SKIP SVE set FPSIMD get SVE for VL 3616
2636 12:28:18.851475 # ok 909 Set SVE VL 3632
2637 12:28:18.851563 # ok 910 # SKIP SVE set SVE get SVE for VL 3632
2638 12:28:18.851651 # ok 911 # SKIP SVE set SVE get FPSIMD for VL 3632
2639 12:28:18.851738 # ok 912 # SKIP SVE set FPSIMD get SVE for VL 3632
2640 12:28:18.851824 # ok 913 Set SVE VL 3648
2641 12:28:18.851910 # ok 914 # SKIP SVE set SVE get SVE for VL 3648
2642 12:28:18.851996 # ok 915 # SKIP SVE set SVE get FPSIMD for VL 3648
2643 12:28:18.852083 # ok 916 # SKIP SVE set FPSIMD get SVE for VL 3648
2644 12:28:18.852170 # ok 917 Set SVE VL 3664
2645 12:28:18.852253 # ok 918 # SKIP SVE set SVE get SVE for VL 3664
2646 12:28:18.852337 # ok 919 # SKIP SVE set SVE get FPSIMD for VL 3664
2647 12:28:18.852416 # ok 920 # SKIP SVE set FPSIMD get SVE for VL 3664
2648 12:28:18.852499 # ok 921 Set SVE VL 3680
2649 12:28:18.852582 # ok 922 # SKIP SVE set SVE get SVE for VL 3680
2650 12:28:18.852666 # ok 923 # SKIP SVE set SVE get FPSIMD for VL 3680
2651 12:28:18.852749 # ok 924 # SKIP SVE set FPSIMD get SVE for VL 3680
2652 12:28:18.852836 # ok 925 Set SVE VL 3696
2653 12:28:18.852921 # ok 926 # SKIP SVE set SVE get SVE for VL 3696
2654 12:28:18.853004 # ok 927 # SKIP SVE set SVE get FPSIMD for VL 3696
2655 12:28:18.853087 # ok 928 # SKIP SVE set FPSIMD get SVE for VL 3696
2656 12:28:18.853168 # ok 929 Set SVE VL 3712
2657 12:28:18.853250 # ok 930 # SKIP SVE set SVE get SVE for VL 3712
2658 12:28:18.853693 # ok 931 # SKIP SVE set SVE get FPSIMD for VL 3712
2659 12:28:18.853889 # ok 932 # SKIP SVE set FPSIMD get SVE for VL 3712
2660 12:28:18.854045 # ok 933 Set SVE VL 3728
2661 12:28:18.854189 # ok 934 # SKIP SVE set SVE get SVE for VL 3728
2662 12:28:18.854333 # ok 935 # SKIP SVE set SVE get FPSIMD for VL 3728
2663 12:28:18.854454 # ok 936 # SKIP SVE set FPSIMD get SVE for VL 3728
2664 12:28:18.854564 # ok 937 Set SVE VL 3744
2665 12:28:18.854675 # ok 938 # SKIP SVE set SVE get SVE for VL 3744
2666 12:28:18.854789 # ok 939 # SKIP SVE set SVE get FPSIMD for VL 3744
2667 12:28:18.854902 # ok 940 # SKIP SVE set FPSIMD get SVE for VL 3744
2668 12:28:18.855013 # ok 941 Set SVE VL 3760
2669 12:28:18.855132 # ok 942 # SKIP SVE set SVE get SVE for VL 3760
2670 12:28:18.855243 # ok 943 # SKIP SVE set SVE get FPSIMD for VL 3760
2671 12:28:18.855354 # ok 944 # SKIP SVE set FPSIMD get SVE for VL 3760
2672 12:28:18.855465 # ok 945 Set SVE VL 3776
2673 12:28:18.855575 # ok 946 # SKIP SVE set SVE get SVE for VL 3776
2674 12:28:18.855685 # ok 947 # SKIP SVE set SVE get FPSIMD for VL 3776
2675 12:28:18.855796 # ok 948 # SKIP SVE set FPSIMD get SVE for VL 3776
2676 12:28:18.855907 # ok 949 Set SVE VL 3792
2677 12:28:18.856023 # ok 950 # SKIP SVE set SVE get SVE for VL 3792
2678 12:28:18.856233 # ok 951 # SKIP SVE set SVE get FPSIMD for VL 3792
2679 12:28:18.856385 # ok 952 # SKIP SVE set FPSIMD get SVE for VL 3792
2680 12:28:18.856518 # ok 953 Set SVE VL 3808
2681 12:28:18.856604 # ok 954 # SKIP SVE set SVE get SVE for VL 3808
2682 12:28:18.856683 # ok 955 # SKIP SVE set SVE get FPSIMD for VL 3808
2683 12:28:18.856763 # ok 956 # SKIP SVE set FPSIMD get SVE for VL 3808
2684 12:28:18.856845 # ok 957 Set SVE VL 3824
2685 12:28:18.856925 # ok 958 # SKIP SVE set SVE get SVE for VL 3824
2686 12:28:18.857007 # ok 959 # SKIP SVE set SVE get FPSIMD for VL 3824
2687 12:28:18.857110 # ok 960 # SKIP SVE set FPSIMD get SVE for VL 3824
2688 12:28:18.857200 # ok 961 Set SVE VL 3840
2689 12:28:18.857287 # ok 962 # SKIP SVE set SVE get SVE for VL 3840
2690 12:28:18.857371 # ok 963 # SKIP SVE set SVE get FPSIMD for VL 3840
2691 12:28:18.857456 # ok 964 # SKIP SVE set FPSIMD get SVE for VL 3840
2692 12:28:18.857537 # ok 965 Set SVE VL 3856
2693 12:28:18.857618 # ok 966 # SKIP SVE set SVE get SVE for VL 3856
2694 12:28:18.857712 # ok 967 # SKIP SVE set SVE get FPSIMD for VL 3856
2695 12:28:18.857797 # ok 968 # SKIP SVE set FPSIMD get SVE for VL 3856
2696 12:28:18.857874 # ok 969 Set SVE VL 3872
2697 12:28:18.857935 # ok 970 # SKIP SVE set SVE get SVE for VL 3872
2698 12:28:18.858007 # ok 971 # SKIP SVE set SVE get FPSIMD for VL 3872
2699 12:28:18.858086 # ok 972 # SKIP SVE set FPSIMD get SVE for VL 3872
2700 12:28:18.858168 # ok 973 Set SVE VL 3888
2701 12:28:18.858473 # ok 974 # SKIP SVE set SVE get SVE for VL 3888
2702 12:28:18.858572 # ok 975 # SKIP SVE set SVE get FPSIMD for VL 3888
2703 12:28:18.858660 # ok 976 # SKIP SVE set FPSIMD get SVE for VL 3888
2704 12:28:18.858744 # ok 977 Set SVE VL 3904
2705 12:28:18.858826 # ok 978 # SKIP SVE set SVE get SVE for VL 3904
2706 12:28:18.858912 # ok 979 # SKIP SVE set SVE get FPSIMD for VL 3904
2707 12:28:18.859000 # ok 980 # SKIP SVE set FPSIMD get SVE for VL 3904
2708 12:28:18.859091 # ok 981 Set SVE VL 3920
2709 12:28:18.859180 # ok 982 # SKIP SVE set SVE get SVE for VL 3920
2710 12:28:18.859269 # ok 983 # SKIP SVE set SVE get FPSIMD for VL 3920
2711 12:28:18.859354 # ok 984 # SKIP SVE set FPSIMD get SVE for VL 3920
2712 12:28:18.859443 # ok 985 Set SVE VL 3936
2713 12:28:18.859531 # ok 986 # SKIP SVE set SVE get SVE for VL 3936
2714 12:28:18.859616 # ok 987 # SKIP SVE set SVE get FPSIMD for VL 3936
2715 12:28:18.859702 # ok 988 # SKIP SVE set FPSIMD get SVE for VL 3936
2716 12:28:18.859788 # ok 989 Set SVE VL 3952
2717 12:28:18.859872 # ok 990 # SKIP SVE set SVE get SVE for VL 3952
2718 12:28:18.859937 # ok 991 # SKIP SVE set SVE get FPSIMD for VL 3952
2719 12:28:18.859998 # ok 992 # SKIP SVE set FPSIMD get SVE for VL 3952
2720 12:28:18.860057 # ok 993 Set SVE VL 3968
2721 12:28:18.860116 # ok 994 # SKIP SVE set SVE get SVE for VL 3968
2722 12:28:18.860178 # ok 995 # SKIP SVE set SVE get FPSIMD for VL 3968
2723 12:28:18.860263 # ok 996 # SKIP SVE set FPSIMD get SVE for VL 3968
2724 12:28:18.860336 # ok 997 Set SVE VL 3984
2725 12:28:18.860399 # ok 998 # SKIP SVE set SVE get SVE for VL 3984
2726 12:28:18.860464 # ok 999 # SKIP SVE set SVE get FPSIMD for VL 3984
2727 12:28:18.860523 # ok 1000 # SKIP SVE set FPSIMD get SVE for VL 3984
2728 12:28:18.860582 # ok 1001 Set SVE VL 4000
2729 12:28:18.860640 # ok 1002 # SKIP SVE set SVE get SVE for VL 4000
2730 12:28:18.860699 # ok 1003 # SKIP SVE set SVE get FPSIMD for VL 4000
2731 12:28:18.860758 # ok 1004 # SKIP SVE set FPSIMD get SVE for VL 4000
2732 12:28:18.860816 # ok 1005 Set SVE VL 4016
2733 12:28:18.860875 # ok 1006 # SKIP SVE set SVE get SVE for VL 4016
2734 12:28:18.860933 # ok 1007 # SKIP SVE set SVE get FPSIMD for VL 4016
2735 12:28:18.860992 # ok 1008 # SKIP SVE set FPSIMD get SVE for VL 4016
2736 12:28:18.861064 # ok 1009 Set SVE VL 4032
2737 12:28:18.861153 # ok 1010 # SKIP SVE set SVE get SVE for VL 4032
2738 12:28:18.861224 # ok 1011 # SKIP SVE set SVE get FPSIMD for VL 4032
2739 12:28:18.861295 # ok 1012 # SKIP SVE set FPSIMD get SVE for VL 4032
2740 12:28:18.861367 # ok 1013 Set SVE VL 4048
2741 12:28:18.861446 # ok 1014 # SKIP SVE set SVE get SVE for VL 4048
2742 12:28:18.861524 # ok 1015 # SKIP SVE set SVE get FPSIMD for VL 4048
2743 12:28:18.861614 # ok 1016 # SKIP SVE set FPSIMD get SVE for VL 4048
2744 12:28:18.861731 # ok 1017 Set SVE VL 4064
2745 12:28:18.862060 # ok 1018 # SKIP SVE set SVE get SVE for VL 4064
2746 12:28:18.862157 # ok 1019 # SKIP SVE set SVE get FPSIMD for VL 4064
2747 12:28:18.862235 # ok 1020 # SKIP SVE set FPSIMD get SVE for VL 4064
2748 12:28:18.862307 # ok 1021 Set SVE VL 4080
2749 12:28:18.862380 # ok 1022 # SKIP SVE set SVE get SVE for VL 4080
2750 12:28:18.862452 # ok 1023 # SKIP SVE set SVE get FPSIMD for VL 4080
2751 12:28:18.862525 # ok 1024 # SKIP SVE set FPSIMD get SVE for VL 4080
2752 12:28:18.862597 # ok 1025 Set SVE VL 4096
2753 12:28:18.862667 # ok 1026 # SKIP SVE set SVE get SVE for VL 4096
2754 12:28:18.862737 # ok 1027 # SKIP SVE set SVE get FPSIMD for VL 4096
2755 12:28:18.862813 # ok 1028 # SKIP SVE set FPSIMD get SVE for VL 4096
2756 12:28:18.862887 # ok 1029 Set SVE VL 4112
2757 12:28:18.862959 # ok 1030 # SKIP SVE set SVE get SVE for VL 4112
2758 12:28:18.863029 # ok 1031 # SKIP SVE set SVE get FPSIMD for VL 4112
2759 12:28:18.863186 # ok 1032 # SKIP SVE set FPSIMD get SVE for VL 4112
2760 12:28:18.863268 # ok 1033 Set SVE VL 4128
2761 12:28:18.863343 # ok 1034 # SKIP SVE set SVE get SVE for VL 4128
2762 12:28:18.863417 # ok 1035 # SKIP SVE set SVE get FPSIMD for VL 4128
2763 12:28:18.863498 # ok 1036 # SKIP SVE set FPSIMD get SVE for VL 4128
2764 12:28:18.863573 # ok 1037 Set SVE VL 4144
2765 12:28:18.863653 # ok 1038 # SKIP SVE set SVE get SVE for VL 4144
2766 12:28:18.863727 # ok 1039 # SKIP SVE set SVE get FPSIMD for VL 4144
2767 12:28:18.863800 # ok 1040 # SKIP SVE set FPSIMD get SVE for VL 4144
2768 12:28:18.863877 # ok 1041 Set SVE VL 4160
2769 12:28:18.863955 # ok 1042 # SKIP SVE set SVE get SVE for VL 4160
2770 12:28:18.864034 # ok 1043 # SKIP SVE set SVE get FPSIMD for VL 4160
2771 12:28:18.864114 # ok 1044 # SKIP SVE set FPSIMD get SVE for VL 4160
2772 12:28:18.864195 # ok 1045 Set SVE VL 4176
2773 12:28:18.864275 # ok 1046 # SKIP SVE set SVE get SVE for VL 4176
2774 12:28:18.864350 # ok 1047 # SKIP SVE set SVE get FPSIMD for VL 4176
2775 12:28:18.864453 # ok 1048 # SKIP SVE set FPSIMD get SVE for VL 4176
2776 12:28:18.864525 # ok 1049 Set SVE VL 4192
2777 12:28:18.864599 # ok 1050 # SKIP SVE set SVE get SVE for VL 4192
2778 12:28:18.864668 # ok 1051 # SKIP SVE set SVE get FPSIMD for VL 4192
2779 12:28:18.864739 # ok 1052 # SKIP SVE set FPSIMD get SVE for VL 4192
2780 12:28:18.864809 # ok 1053 Set SVE VL 4208
2781 12:28:18.864882 # ok 1054 # SKIP SVE set SVE get SVE for VL 4208
2782 12:28:18.864960 # ok 1055 # SKIP SVE set SVE get FPSIMD for VL 4208
2783 12:28:18.865041 # ok 1056 # SKIP SVE set FPSIMD get SVE for VL 4208
2784 12:28:18.865121 # ok 1057 Set SVE VL 4224
2785 12:28:18.865201 # ok 1058 # SKIP SVE set SVE get SVE for VL 4224
2786 12:28:18.865282 # ok 1059 # SKIP SVE set SVE get FPSIMD for VL 4224
2787 12:28:18.865579 # ok 1060 # SKIP SVE set FPSIMD get SVE for VL 4224
2788 12:28:18.865687 # ok 1061 Set SVE VL 4240
2789 12:28:18.865765 # ok 1062 # SKIP SVE set SVE get SVE for VL 4240
2790 12:28:18.865838 # ok 1063 # SKIP SVE set SVE get FPSIMD for VL 4240
2791 12:28:18.865909 # ok 1064 # SKIP SVE set FPSIMD get SVE for VL 4240
2792 12:28:18.865979 # ok 1065 Set SVE VL 4256
2793 12:28:18.866050 # ok 1066 # SKIP SVE set SVE get SVE for VL 4256
2794 12:28:18.866120 # ok 1067 # SKIP SVE set SVE get FPSIMD for VL 4256
2795 12:28:18.866192 # ok 1068 # SKIP SVE set FPSIMD get SVE for VL 4256
2796 12:28:18.866269 # ok 1069 Set SVE VL 4272
2797 12:28:18.866352 # ok 1070 # SKIP SVE set SVE get SVE for VL 4272
2798 12:28:18.866436 # ok 1071 # SKIP SVE set SVE get FPSIMD for VL 4272
2799 12:28:18.866508 # ok 1072 # SKIP SVE set FPSIMD get SVE for VL 4272
2800 12:28:18.866579 # ok 1073 Set SVE VL 4288
2801 12:28:18.866650 # ok 1074 # SKIP SVE set SVE get SVE for VL 4288
2802 12:28:18.866725 # ok 1075 # SKIP SVE set SVE get FPSIMD for VL 4288
2803 12:28:18.866798 # ok 1076 # SKIP SVE set FPSIMD get SVE for VL 4288
2804 12:28:18.866868 # ok 1077 Set SVE VL 4304
2805 12:28:18.866958 # ok 1078 # SKIP SVE set SVE get SVE for VL 4304
2806 12:28:18.867032 # ok 1079 # SKIP SVE set SVE get FPSIMD for VL 4304
2807 12:28:18.867102 # ok 1080 # SKIP SVE set FPSIMD get SVE for VL 4304
2808 12:28:18.867172 # ok 1081 Set SVE VL 4320
2809 12:28:18.867245 # ok 1082 # SKIP SVE set SVE get SVE for VL 4320
2810 12:28:18.867325 # ok 1083 # SKIP SVE set SVE get FPSIMD for VL 4320
2811 12:28:18.867402 # ok 1084 # SKIP SVE set FPSIMD get SVE for VL 4320
2812 12:28:18.867475 # ok 1085 Set SVE VL 4336
2813 12:28:18.867548 # ok 1086 # SKIP SVE set SVE get SVE for VL 4336
2814 12:28:18.867642 # ok 1087 # SKIP SVE set SVE get FPSIMD for VL 4336
2815 12:28:18.867724 # ok 1088 # SKIP SVE set FPSIMD get SVE for VL 4336
2816 12:28:18.867804 # ok 1089 Set SVE VL 4352
2817 12:28:18.867881 # ok 1090 # SKIP SVE set SVE get SVE for VL 4352
2818 12:28:18.867953 # ok 1091 # SKIP SVE set SVE get FPSIMD for VL 4352
2819 12:28:18.868035 # ok 1092 # SKIP SVE set FPSIMD get SVE for VL 4352
2820 12:28:18.868111 # ok 1093 Set SVE VL 4368
2821 12:28:18.868180 # ok 1094 # SKIP SVE set SVE get SVE for VL 4368
2822 12:28:18.868267 # ok 1095 # SKIP SVE set SVE get FPSIMD for VL 4368
2823 12:28:18.868340 # ok 1096 # SKIP SVE set FPSIMD get SVE for VL 4368
2824 12:28:18.868418 # ok 1097 Set SVE VL 4384
2825 12:28:18.868498 # ok 1098 # SKIP SVE set SVE get SVE for VL 4384
2826 12:28:18.868578 # ok 1099 # SKIP SVE set SVE get FPSIMD for VL 4384
2827 12:28:18.868658 # ok 1100 # SKIP SVE set FPSIMD get SVE for VL 4384
2828 12:28:18.868739 # ok 1101 Set SVE VL 4400
2829 12:28:18.868835 # ok 1102 # SKIP SVE set SVE get SVE for VL 4400
2830 12:28:18.869148 # ok 1103 # SKIP SVE set SVE get FPSIMD for VL 4400
2831 12:28:18.869251 # ok 1104 # SKIP SVE set FPSIMD get SVE for VL 4400
2832 12:28:18.869348 # ok 1105 Set SVE VL 4416
2833 12:28:18.869444 # ok 1106 # SKIP SVE set SVE get SVE for VL 4416
2834 12:28:18.869530 # ok 1107 # SKIP SVE set SVE get FPSIMD for VL 4416
2835 12:28:18.869660 # ok 1108 # SKIP SVE set FPSIMD get SVE for VL 4416
2836 12:28:18.869759 # ok 1109 Set SVE VL 4432
2837 12:28:18.869843 # ok 1110 # SKIP SVE set SVE get SVE for VL 4432
2838 12:28:18.869926 # ok 1111 # SKIP SVE set SVE get FPSIMD for VL 4432
2839 12:28:18.870011 # ok 1112 # SKIP SVE set FPSIMD get SVE for VL 4432
2840 12:28:18.870114 # ok 1113 Set SVE VL 4448
2841 12:28:18.870202 # ok 1114 # SKIP SVE set SVE get SVE for VL 4448
2842 12:28:18.870285 # ok 1115 # SKIP SVE set SVE get FPSIMD for VL 4448
2843 12:28:18.870369 # ok 1116 # SKIP SVE set FPSIMD get SVE for VL 4448
2844 12:28:18.870468 # ok 1117 Set SVE VL 4464
2845 12:28:18.870540 # ok 1118 # SKIP SVE set SVE get SVE for VL 4464
2846 12:28:18.870606 # ok 1119 # SKIP SVE set SVE get FPSIMD for VL 4464
2847 12:28:18.870700 # ok 1120 # SKIP SVE set FPSIMD get SVE for VL 4464
2848 12:28:18.870765 # ok 1121 Set SVE VL 4480
2849 12:28:18.870846 # ok 1122 # SKIP SVE set SVE get SVE for VL 4480
2850 12:28:18.870926 # ok 1123 # SKIP SVE set SVE get FPSIMD for VL 4480
2851 12:28:18.871014 # ok 1124 # SKIP SVE set FPSIMD get SVE for VL 4480
2852 12:28:18.871118 # ok 1125 Set SVE VL 4496
2853 12:28:18.871224 # ok 1126 # SKIP SVE set SVE get SVE for VL 4496
2854 12:28:18.872489 # ok 1127 # SKIP SVE set SVE get FPSIMD for VL 4496
2855 12:28:18.872767 # ok 1128 # SKIP SVE set FPSIMD get SVE for VL 4496
2856 12:28:18.872864 # ok 1129 Set SVE VL 4512
2857 12:28:18.872957 # ok 1130 # SKIP SVE set SVE get SVE for VL 4512
2858 12:28:18.873033 # ok 1131 # SKIP SVE set SVE get FPSIMD for VL 4512
2859 12:28:18.873356 # ok 1132 # SKIP SVE set FPSIMD get SVE for VL 4512
2860 12:28:18.873469 # ok 1133 Set SVE VL 4528
2861 12:28:18.873542 # ok 1134 # SKIP SVE set SVE get SVE for VL 4528
2862 12:28:18.873633 # ok 1135 # SKIP SVE set SVE get FPSIMD for VL 4528
2863 12:28:18.873742 # ok 1136 # SKIP SVE set FPSIMD get SVE for VL 4528
2864 12:28:18.873826 # ok 1137 Set SVE VL 4544
2865 12:28:18.873901 # ok 1138 # SKIP SVE set SVE get SVE for VL 4544
2866 12:28:18.873975 # ok 1139 # SKIP SVE set SVE get FPSIMD for VL 4544
2867 12:28:18.874216 # ok 1140 # SKIP SVE set FPSIMD get SVE for VL 4544
2868 12:28:18.874301 # ok 1141 Set SVE VL 4560
2869 12:28:18.874377 # ok 1142 # SKIP SVE set SVE get SVE for VL 4560
2870 12:28:18.874446 # ok 1143 # SKIP SVE set SVE get FPSIMD for VL 4560
2871 12:28:18.874717 # ok 1144 # SKIP SVE set FPSIMD get SVE for VL 4560
2872 12:28:18.874893 # ok 1145 Set SVE VL 4576
2873 12:28:18.875124 # ok 1146 # SKIP SVE set SVE get SVE for VL 4576
2874 12:28:18.875235 # ok 1147 # SKIP SVE set SVE get FPSIMD for VL 4576
2875 12:28:18.875310 # ok 1148 # SKIP SVE set FPSIMD get SVE for VL 4576
2876 12:28:18.875373 # ok 1149 Set SVE VL 4592
2877 12:28:18.875433 # ok 1150 # SKIP SVE set SVE get SVE for VL 4592
2878 12:28:18.875698 # ok 1151 # SKIP SVE set SVE get FPSIMD for VL 4592
2879 12:28:18.875820 # ok 1152 # SKIP SVE set FPSIMD get SVE for VL 4592
2880 12:28:18.875922 # ok 1153 Set SVE VL 4608
2881 12:28:18.876037 # ok 1154 # SKIP SVE set SVE get SVE for VL 4608
2882 12:28:18.876366 # ok 1155 # SKIP SVE set SVE get FPSIMD for VL 4608
2883 12:28:18.876504 # ok 1156 # SKIP SVE set FPSIMD get SVE for VL 4608
2884 12:28:18.876593 # ok 1157 Set SVE VL 4624
2885 12:28:18.876693 # ok 1158 # SKIP SVE set SVE get SVE for VL 4624
2886 12:28:18.876796 # ok 1159 # SKIP SVE set SVE get FPSIMD for VL 4624
2887 12:28:18.876900 # ok 1160 # SKIP SVE set FPSIMD get SVE for VL 4624
2888 12:28:18.877001 # ok 1161 Set SVE VL 4640
2889 12:28:18.877121 # ok 1162 # SKIP SVE set SVE get SVE for VL 4640
2890 12:28:18.877218 # ok 1163 # SKIP SVE set SVE get FPSIMD for VL 4640
2891 12:28:18.877516 # ok 1164 # SKIP SVE set FPSIMD get SVE for VL 4640
2892 12:28:18.877618 # ok 1165 Set SVE VL 4656
2893 12:28:18.877722 # ok 1166 # SKIP SVE set SVE get SVE for VL 4656
2894 12:28:18.877808 # ok 1167 # SKIP SVE set SVE get FPSIMD for VL 4656
2895 12:28:18.877876 # ok 1168 # SKIP SVE set FPSIMD get SVE for VL 4656
2896 12:28:18.877945 # ok 1169 Set SVE VL 4672
2897 12:28:18.878042 # ok 1170 # SKIP SVE set SVE get SVE for VL 4672
2898 12:28:18.878119 # ok 1171 # SKIP SVE set SVE get FPSIMD for VL 4672
2899 12:28:18.878194 # ok 1172 # SKIP SVE set FPSIMD get SVE for VL 4672
2900 12:28:18.878268 # ok 1173 Set SVE VL 4688
2901 12:28:18.878359 # ok 1174 # SKIP SVE set SVE get SVE for VL 4688
2902 12:28:18.878437 # ok 1175 # SKIP SVE set SVE get FPSIMD for VL 4688
2903 12:28:18.878511 # ok 1176 # SKIP SVE set FPSIMD get SVE for VL 4688
2904 12:28:18.878583 # ok 1177 Set SVE VL 4704
2905 12:28:18.878676 # ok 1178 # SKIP SVE set SVE get SVE for VL 4704
2906 12:28:18.878760 # ok 1179 # SKIP SVE set SVE get FPSIMD for VL 4704
2907 12:28:18.878876 # ok 1180 # SKIP SVE set FPSIMD get SVE for VL 4704
2908 12:28:18.878966 # ok 1181 Set SVE VL 4720
2909 12:28:18.879056 # ok 1182 # SKIP SVE set SVE get SVE for VL 4720
2910 12:28:18.879129 # ok 1183 # SKIP SVE set SVE get FPSIMD for VL 4720
2911 12:28:18.879404 # ok 1184 # SKIP SVE set FPSIMD get SVE for VL 4720
2912 12:28:18.879522 # ok 1185 Set SVE VL 4736
2913 12:28:18.879610 # ok 1186 # SKIP SVE set SVE get SVE for VL 4736
2914 12:28:18.879709 # ok 1187 # SKIP SVE set SVE get FPSIMD for VL 4736
2915 12:28:18.879806 # ok 1188 # SKIP SVE set FPSIMD get SVE for VL 4736
2916 12:28:18.879904 # ok 1189 Set SVE VL 4752
2917 12:28:18.880246 # ok 1190 # SKIP SVE set SVE get SVE for VL 4752
2918 12:28:18.880343 # ok 1191 # SKIP SVE set SVE get FPSIMD for VL 4752
2919 12:28:18.880441 # ok 1192 # SKIP SVE set FPSIMD get SVE for VL 4752
2920 12:28:18.880523 # ok 1193 Set SVE VL 4768
2921 12:28:18.880616 # ok 1194 # SKIP SVE set SVE get SVE for VL 4768
2922 12:28:18.880710 # ok 1195 # SKIP SVE set SVE get FPSIMD for VL 4768
2923 12:28:18.880846 # ok 1196 # SKIP SVE set FPSIMD get SVE for VL 4768
2924 12:28:18.880958 # ok 1197 Set SVE VL 4784
2925 12:28:18.881040 # ok 1198 # SKIP SVE set SVE get SVE for VL 4784
2926 12:28:18.881127 # ok 1199 # SKIP SVE set SVE get FPSIMD for VL 4784
2927 12:28:18.881201 # ok 1200 # SKIP SVE set FPSIMD get SVE for VL 4784
2928 12:28:18.881282 # ok 1201 Set SVE VL 4800
2929 12:28:18.881364 # ok 1202 # SKIP SVE set SVE get SVE for VL 4800
2930 12:28:18.881462 # ok 1203 # SKIP SVE set SVE get FPSIMD for VL 4800
2931 12:28:18.881561 # ok 1204 # SKIP SVE set FPSIMD get SVE for VL 4800
2932 12:28:18.881666 # ok 1205 Set SVE VL 4816
2933 12:28:18.881757 # ok 1206 # SKIP SVE set SVE get SVE for VL 4816
2934 12:28:18.882034 # ok 1207 # SKIP SVE set SVE get FPSIMD for VL 4816
2935 12:28:18.882115 # ok 1208 # SKIP SVE set FPSIMD get SVE for VL 4816
2936 12:28:18.882203 # ok 1209 Set SVE VL 4832
2937 12:28:18.882299 # ok 1210 # SKIP SVE set SVE get SVE for VL 4832
2938 12:28:18.882398 # ok 1211 # SKIP SVE set SVE get FPSIMD for VL 4832
2939 12:28:18.882498 # ok 1212 # SKIP SVE set FPSIMD get SVE for VL 4832
2940 12:28:18.882601 # ok 1213 Set SVE VL 4848
2941 12:28:18.882700 # ok 1214 # SKIP SVE set SVE get SVE for VL 4848
2942 12:28:18.882982 # ok 1215 # SKIP SVE set SVE get FPSIMD for VL 4848
2943 12:28:18.883080 # ok 1216 # SKIP SVE set FPSIMD get SVE for VL 4848
2944 12:28:18.883166 # ok 1217 Set SVE VL 4864
2945 12:28:18.883264 # ok 1218 # SKIP SVE set SVE get SVE for VL 4864
2946 12:28:18.883364 # ok 1219 # SKIP SVE set SVE get FPSIMD for VL 4864
2947 12:28:18.883458 # ok 1220 # SKIP SVE set FPSIMD get SVE for VL 4864
2948 12:28:18.883543 # ok 1221 Set SVE VL 4880
2949 12:28:18.883817 # ok 1222 # SKIP SVE set SVE get SVE for VL 4880
2950 12:28:18.883904 # ok 1223 # SKIP SVE set SVE get FPSIMD for VL 4880
2951 12:28:18.892624 # ok 1224 # SKIP SVE set FPSIMD get SVE for VL 4880
2952 12:28:18.892792 # ok 1225 Set SVE VL 4896
2953 12:28:18.892873 # ok 1226 # SKIP SVE set SVE get SVE for VL 4896
2954 12:28:18.892953 # ok 1227 # SKIP SVE set SVE get FPSIMD for VL 4896
2955 12:28:18.893211 # ok 1228 # SKIP SVE set FPSIMD get SVE for VL 4896
2956 12:28:18.893283 # ok 1229 Set SVE VL 4912
2957 12:28:18.893360 # ok 1230 # SKIP SVE set SVE get SVE for VL 4912
2958 12:28:18.893444 # ok 1231 # SKIP SVE set SVE get FPSIMD for VL 4912
2959 12:28:18.893701 # ok 1232 # SKIP SVE set FPSIMD get SVE for VL 4912
2960 12:28:18.893785 # ok 1233 Set SVE VL 4928
2961 12:28:18.893861 # ok 1234 # SKIP SVE set SVE get SVE for VL 4928
2962 12:28:18.894118 # ok 1235 # SKIP SVE set SVE get FPSIMD for VL 4928
2963 12:28:18.894216 # ok 1236 # SKIP SVE set FPSIMD get SVE for VL 4928
2964 12:28:18.894301 # ok 1237 Set SVE VL 4944
2965 12:28:18.894367 # ok 1238 # SKIP SVE set SVE get SVE for VL 4944
2966 12:28:18.894446 # ok 1239 # SKIP SVE set SVE get FPSIMD for VL 4944
2967 12:28:18.894522 # ok 1240 # SKIP SVE set FPSIMD get SVE for VL 4944
2968 12:28:18.894776 # ok 1241 Set SVE VL 4960
2969 12:28:18.894848 # ok 1242 # SKIP SVE set SVE get SVE for VL 4960
2970 12:28:18.894923 # ok 1243 # SKIP SVE set SVE get FPSIMD for VL 4960
2971 12:28:18.894998 # ok 1244 # SKIP SVE set FPSIMD get SVE for VL 4960
2972 12:28:18.895085 # ok 1245 Set SVE VL 4976
2973 12:28:18.896615 # ok 1246 # SKIP SVE set SVE get SVE for VL 4976
2974 12:28:18.896871 # ok 1247 # SKIP SVE set SVE get FPSIMD for VL 4976
2975 12:28:18.897140 # ok 1248 # SKIP SVE set FPSIMD get SVE for VL 4976
2976 12:28:18.897215 # ok 1249 Set SVE VL 4992
2977 12:28:18.897276 # ok 1250 # SKIP SVE set SVE get SVE for VL 4992
2978 12:28:18.897355 # ok 1251 # SKIP SVE set SVE get FPSIMD for VL 4992
2979 12:28:18.897605 # ok 1252 # SKIP SVE set FPSIMD get SVE for VL 4992
2980 12:28:18.897698 # ok 1253 Set SVE VL 5008
2981 12:28:18.897777 # ok 1254 # SKIP SVE set SVE get SVE for VL 5008
2982 12:28:18.897841 # ok 1255 # SKIP SVE set SVE get FPSIMD for VL 5008
2983 12:28:18.897913 # ok 1256 # SKIP SVE set FPSIMD get SVE for VL 5008
2984 12:28:18.898164 # ok 1257 Set SVE VL 5024
2985 12:28:18.898244 # ok 1258 # SKIP SVE set SVE get SVE for VL 5024
2986 12:28:18.898317 # ok 1259 # SKIP SVE set SVE get FPSIMD for VL 5024
2987 12:28:18.898572 # ok 1260 # SKIP SVE set FPSIMD get SVE for VL 5024
2988 12:28:18.898655 # ok 1261 Set SVE VL 5040
2989 12:28:18.898731 # ok 1262 # SKIP SVE set SVE get SVE for VL 5040
2990 12:28:18.898806 # ok 1263 # SKIP SVE set SVE get FPSIMD for VL 5040
2991 12:28:18.898882 # ok 1264 # SKIP SVE set FPSIMD get SVE for VL 5040
2992 12:28:18.899115 # ok 1265 Set SVE VL 5056
2993 12:28:18.899205 # ok 1266 # SKIP SVE set SVE get SVE for VL 5056
2994 12:28:18.899926 # ok 1267 # SKIP SVE set SVE get FPSIMD for VL 5056
2995 12:28:18.900197 # ok 1268 # SKIP SVE set FPSIMD get SVE for VL 5056
2996 12:28:18.900282 # ok 1269 Set SVE VL 5072
2997 12:28:18.900385 # ok 1270 # SKIP SVE set SVE get SVE for VL 5072
2998 12:28:18.900464 # ok 1271 # SKIP SVE set SVE get FPSIMD for VL 5072
2999 12:28:18.900542 # ok 1272 # SKIP SVE set FPSIMD get SVE for VL 5072
3000 12:28:18.900796 # ok 1273 Set SVE VL 5088
3001 12:28:18.900865 # ok 1274 # SKIP SVE set SVE get SVE for VL 5088
3002 12:28:18.900940 # ok 1275 # SKIP SVE set SVE get FPSIMD for VL 5088
3003 12:28:18.901015 # ok 1276 # SKIP SVE set FPSIMD get SVE for VL 5088
3004 12:28:18.901267 # ok 1277 Set SVE VL 5104
3005 12:28:18.901336 # ok 1278 # SKIP SVE set SVE get SVE for VL 5104
3006 12:28:18.901608 # ok 1279 # SKIP SVE set SVE get FPSIMD for VL 5104
3007 12:28:18.901698 # ok 1280 # SKIP SVE set FPSIMD get SVE for VL 5104
3008 12:28:18.901763 # ok 1281 Set SVE VL 5120
3009 12:28:18.901836 # ok 1282 # SKIP SVE set SVE get SVE for VL 5120
3010 12:28:18.901897 # ok 1283 # SKIP SVE set SVE get FPSIMD for VL 5120
3011 12:28:18.901967 # ok 1284 # SKIP SVE set FPSIMD get SVE for VL 5120
3012 12:28:18.902041 # ok 1285 Set SVE VL 5136
3013 12:28:18.902302 # ok 1286 # SKIP SVE set SVE get SVE for VL 5136
3014 12:28:18.902383 # ok 1287 # SKIP SVE set SVE get FPSIMD for VL 5136
3015 12:28:18.902464 # ok 1288 # SKIP SVE set FPSIMD get SVE for VL 5136
3016 12:28:18.902708 # ok 1289 Set SVE VL 5152
3017 12:28:18.902790 # ok 1290 # SKIP SVE set SVE get SVE for VL 5152
3018 12:28:18.902864 # ok 1291 # SKIP SVE set SVE get FPSIMD for VL 5152
3019 12:28:18.902941 # ok 1292 # SKIP SVE set FPSIMD get SVE for VL 5152
3020 12:28:18.903197 # ok 1293 Set SVE VL 5168
3021 12:28:18.903279 # ok 1294 # SKIP SVE set SVE get SVE for VL 5168
3022 12:28:18.903530 # ok 1295 # SKIP SVE set SVE get FPSIMD for VL 5168
3023 12:28:18.903608 # ok 1296 # SKIP SVE set FPSIMD get SVE for VL 5168
3024 12:28:18.903684 # ok 1297 Set SVE VL 5184
3025 12:28:18.903935 # ok 1298 # SKIP SVE set SVE get SVE for VL 5184
3026 12:28:18.904016 # ok 1299 # SKIP SVE set SVE get FPSIMD for VL 5184
3027 12:28:18.904093 # ok 1300 # SKIP SVE set FPSIMD get SVE for VL 5184
3028 12:28:18.904169 # ok 1301 Set SVE VL 5200
3029 12:28:18.904272 # ok 1302 # SKIP SVE set SVE get SVE for VL 5200
3030 12:28:18.904561 # ok 1303 # SKIP SVE set SVE get FPSIMD for VL 5200
3031 12:28:18.904650 # ok 1304 # SKIP SVE set FPSIMD get SVE for VL 5200
3032 12:28:18.904723 # ok 1305 Set SVE VL 5216
3033 12:28:18.904800 # ok 1306 # SKIP SVE set SVE get SVE for VL 5216
3034 12:28:18.905048 # ok 1307 # SKIP SVE set SVE get FPSIMD for VL 5216
3035 12:28:18.905119 # ok 1308 # SKIP SVE set FPSIMD get SVE for VL 5216
3036 12:28:18.905195 # ok 1309 Set SVE VL 5232
3037 12:28:18.905260 # ok 1310 # SKIP SVE set SVE get SVE for VL 5232
3038 12:28:18.905340 # ok 1311 # SKIP SVE set SVE get FPSIMD for VL 5232
3039 12:28:18.905614 # ok 1312 # SKIP SVE set FPSIMD get SVE for VL 5232
3040 12:28:18.905708 # ok 1313 Set SVE VL 5248
3041 12:28:18.905781 # ok 1314 # SKIP SVE set SVE get SVE for VL 5248
3042 12:28:18.906018 # ok 1315 # SKIP SVE set SVE get FPSIMD for VL 5248
3043 12:28:18.906100 # ok 1316 # SKIP SVE set FPSIMD get SVE for VL 5248
3044 12:28:18.906203 # ok 1317 Set SVE VL 5264
3045 12:28:18.906457 # ok 1318 # SKIP SVE set SVE get SVE for VL 5264
3046 12:28:18.906525 # ok 1319 # SKIP SVE set SVE get FPSIMD for VL 5264
3047 12:28:18.906589 # ok 1320 # SKIP SVE set FPSIMD get SVE for VL 5264
3048 12:28:18.906665 # ok 1321 Set SVE VL 5280
3049 12:28:18.906910 # ok 1322 # SKIP SVE set SVE get SVE for VL 5280
3050 12:28:18.906980 # ok 1323 # SKIP SVE set SVE get FPSIMD for VL 5280
3051 12:28:18.907055 # ok 1324 # SKIP SVE set FPSIMD get SVE for VL 5280
3052 12:28:18.907140 # ok 1325 Set SVE VL 5296
3053 12:28:18.907244 # ok 1326 # SKIP SVE set SVE get SVE for VL 5296
3054 12:28:18.907558 # ok 1327 # SKIP SVE set SVE get FPSIMD for VL 5296
3055 12:28:18.907637 # ok 1328 # SKIP SVE set FPSIMD get SVE for VL 5296
3056 12:28:18.907883 # ok 1329 Set SVE VL 5312
3057 12:28:18.907953 # ok 1330 # SKIP SVE set SVE get SVE for VL 5312
3058 12:28:18.908019 # ok 1331 # SKIP SVE set SVE get FPSIMD for VL 5312
3059 12:28:18.908093 # ok 1332 # SKIP SVE set FPSIMD get SVE for VL 5312
3060 12:28:18.908158 # ok 1333 Set SVE VL 5328
3061 12:28:18.908258 # ok 1334 # SKIP SVE set SVE get SVE for VL 5328
3062 12:28:18.908335 # ok 1335 # SKIP SVE set SVE get FPSIMD for VL 5328
3063 12:28:18.908439 # ok 1336 # SKIP SVE set FPSIMD get SVE for VL 5328
3064 12:28:18.908525 # ok 1337 Set SVE VL 5344
3065 12:28:18.908773 # ok 1338 # SKIP SVE set SVE get SVE for VL 5344
3066 12:28:18.908853 # ok 1339 # SKIP SVE set SVE get FPSIMD for VL 5344
3067 12:28:18.908929 # ok 1340 # SKIP SVE set FPSIMD get SVE for VL 5344
3068 12:28:18.909176 # ok 1341 Set SVE VL 5360
3069 12:28:18.909244 # ok 1342 # SKIP SVE set SVE get SVE for VL 5360
3070 12:28:18.909318 # ok 1343 # SKIP SVE set SVE get FPSIMD for VL 5360
3071 12:28:18.909574 # ok 1344 # SKIP SVE set FPSIMD get SVE for VL 5360
3072 12:28:18.909685 # ok 1345 Set SVE VL 5376
3073 12:28:18.909771 # ok 1346 # SKIP SVE set SVE get SVE for VL 5376
3074 12:28:18.910029 # ok 1347 # SKIP SVE set SVE get FPSIMD for VL 5376
3075 12:28:18.910111 # ok 1348 # SKIP SVE set FPSIMD get SVE for VL 5376
3076 12:28:18.910175 # ok 1349 Set SVE VL 5392
3077 12:28:18.910249 # ok 1350 # SKIP SVE set SVE get SVE for VL 5392
3078 12:28:18.910324 # ok 1351 # SKIP SVE set SVE get FPSIMD for VL 5392
3079 12:28:18.910576 # ok 1352 # SKIP SVE set FPSIMD get SVE for VL 5392
3080 12:28:18.910645 # ok 1353 Set SVE VL 5408
3081 12:28:18.910720 # ok 1354 # SKIP SVE set SVE get SVE for VL 5408
3082 12:28:18.910785 # ok 1355 # SKIP SVE set SVE get FPSIMD for VL 5408
3083 12:28:18.911027 # ok 1356 # SKIP SVE set FPSIMD get SVE for VL 5408
3084 12:28:18.911104 # ok 1357 Set SVE VL 5424
3085 12:28:18.911204 # ok 1358 # SKIP SVE set SVE get SVE for VL 5424
3086 12:28:18.911468 # ok 1359 # SKIP SVE set SVE get FPSIMD for VL 5424
3087 12:28:18.911568 # ok 1360 # SKIP SVE set FPSIMD get SVE for VL 5424
3088 12:28:18.911650 # ok 1361 Set SVE VL 5440
3089 12:28:18.911726 # ok 1362 # SKIP SVE set SVE get SVE for VL 5440
3090 12:28:18.911973 # ok 1363 # SKIP SVE set SVE get FPSIMD for VL 5440
3091 12:28:18.912053 # ok 1364 # SKIP SVE set FPSIMD get SVE for VL 5440
3092 12:28:18.912313 # ok 1365 Set SVE VL 5456
3093 12:28:18.912402 # ok 1366 # SKIP SVE set SVE get SVE for VL 5456
3094 12:28:18.912500 # ok 1367 # SKIP SVE set SVE get FPSIMD for VL 5456
3095 12:28:18.912582 # ok 1368 # SKIP SVE set FPSIMD get SVE for VL 5456
3096 12:28:18.912664 # ok 1369 Set SVE VL 5472
3097 12:28:18.912997 # ok 1370 # SKIP SVE set SVE get SVE for VL 5472
3098 12:28:18.913145 # ok 1371 # SKIP SVE set SVE get FPSIMD for VL 5472
3099 12:28:18.913307 # ok 1372 # SKIP SVE set FPSIMD get SVE for VL 5472
3100 12:28:18.913402 # ok 1373 Set SVE VL 5488
3101 12:28:18.913508 # ok 1374 # SKIP SVE set SVE get SVE for VL 5488
3102 12:28:18.913597 # ok 1375 # SKIP SVE set SVE get FPSIMD for VL 5488
3103 12:28:18.913719 # ok 1376 # SKIP SVE set FPSIMD get SVE for VL 5488
3104 12:28:18.913825 # ok 1377 Set SVE VL 5504
3105 12:28:18.913906 # ok 1378 # SKIP SVE set SVE get SVE for VL 5504
3106 12:28:18.914204 # ok 1379 # SKIP SVE set SVE get FPSIMD for VL 5504
3107 12:28:18.914309 # ok 1380 # SKIP SVE set FPSIMD get SVE for VL 5504
3108 12:28:18.914421 # ok 1381 Set SVE VL 5520
3109 12:28:18.914505 # ok 1382 # SKIP SVE set SVE get SVE for VL 5520
3110 12:28:18.914593 # ok 1383 # SKIP SVE set SVE get FPSIMD for VL 5520
3111 12:28:18.914693 # ok 1384 # SKIP SVE set FPSIMD get SVE for VL 5520
3112 12:28:18.914778 # ok 1385 Set SVE VL 5536
3113 12:28:18.914877 # ok 1386 # SKIP SVE set SVE get SVE for VL 5536
3114 12:28:18.914961 # ok 1387 # SKIP SVE set SVE get FPSIMD for VL 5536
3115 12:28:18.915059 # ok 1388 # SKIP SVE set FPSIMD get SVE for VL 5536
3116 12:28:18.915147 # ok 1389 Set SVE VL 5552
3117 12:28:18.915244 # ok 1390 # SKIP SVE set SVE get SVE for VL 5552
3118 12:28:18.915356 # ok 1391 # SKIP SVE set SVE get FPSIMD for VL 5552
3119 12:28:18.915657 # ok 1392 # SKIP SVE set FPSIMD get SVE for VL 5552
3120 12:28:18.915969 # ok 1393 Set SVE VL 5568
3121 12:28:18.916075 # ok 1394 # SKIP SVE set SVE get SVE for VL 5568
3122 12:28:18.916164 # ok 1395 # SKIP SVE set SVE get FPSIMD for VL 5568
3123 12:28:18.916263 # ok 1396 # SKIP SVE set FPSIMD get SVE for VL 5568
3124 12:28:18.916346 # ok 1397 Set SVE VL 5584
3125 12:28:18.916428 # ok 1398 # SKIP SVE set SVE get SVE for VL 5584
3126 12:28:18.916526 # ok 1399 # SKIP SVE set SVE get FPSIMD for VL 5584
3127 12:28:18.916612 # ok 1400 # SKIP SVE set FPSIMD get SVE for VL 5584
3128 12:28:18.916710 # ok 1401 Set SVE VL 5600
3129 12:28:18.916796 # ok 1402 # SKIP SVE set SVE get SVE for VL 5600
3130 12:28:18.916893 # ok 1403 # SKIP SVE set SVE get FPSIMD for VL 5600
3131 12:28:18.917202 # ok 1404 # SKIP SVE set FPSIMD get SVE for VL 5600
3132 12:28:18.917359 # ok 1405 Set SVE VL 5616
3133 12:28:18.917476 # ok 1406 # SKIP SVE set SVE get SVE for VL 5616
3134 12:28:18.945932 # ok 1407 # SKIP SVE set SVE get FPSIMD for VL 5616
3135 12:28:18.946182 # ok 1408 # SKIP SVE set FPSIMD get SVE for VL 5616
3136 12:28:18.946277 # ok 1409 Set SVE VL 5632
3137 12:28:18.946373 # ok 1410 # SKIP SVE set SVE get SVE for VL 5632
3138 12:28:18.946450 # ok 1411 # SKIP SVE set SVE get FPSIMD for VL 5632
3139 12:28:18.946527 # ok 1412 # SKIP SVE set FPSIMD get SVE for VL 5632
3140 12:28:18.946607 # ok 1413 Set SVE VL 5648
3141 12:28:18.946703 # ok 1414 # SKIP SVE set SVE get SVE for VL 5648
3142 12:28:18.946788 # ok 1415 # SKIP SVE set SVE get FPSIMD for VL 5648
3143 12:28:18.946870 # ok 1416 # SKIP SVE set FPSIMD get SVE for VL 5648
3144 12:28:18.946966 # ok 1417 Set SVE VL 5664
3145 12:28:18.947040 # ok 1418 # SKIP SVE set SVE get SVE for VL 5664
3146 12:28:18.947129 # ok 1419 # SKIP SVE set SVE get FPSIMD for VL 5664
3147 12:28:18.947218 # ok 1420 # SKIP SVE set FPSIMD get SVE for VL 5664
3148 12:28:18.947294 # ok 1421 Set SVE VL 5680
3149 12:28:18.948525 # ok 1422 # SKIP SVE set SVE get SVE for VL 5680
3150 12:28:18.948843 # ok 1423 # SKIP SVE set SVE get FPSIMD for VL 5680
3151 12:28:18.948949 # ok 1424 # SKIP SVE set FPSIMD get SVE for VL 5680
3152 12:28:18.949038 # ok 1425 Set SVE VL 5696
3153 12:28:18.949138 # ok 1426 # SKIP SVE set SVE get SVE for VL 5696
3154 12:28:18.949239 # ok 1427 # SKIP SVE set SVE get FPSIMD for VL 5696
3155 12:28:18.949342 # ok 1428 # SKIP SVE set FPSIMD get SVE for VL 5696
3156 12:28:18.949446 # ok 1429 Set SVE VL 5712
3157 12:28:18.949549 # ok 1430 # SKIP SVE set SVE get SVE for VL 5712
3158 12:28:18.949722 # ok 1431 # SKIP SVE set SVE get FPSIMD for VL 5712
3159 12:28:18.949828 # ok 1432 # SKIP SVE set FPSIMD get SVE for VL 5712
3160 12:28:18.949925 # ok 1433 Set SVE VL 5728
3161 12:28:18.950020 # ok 1434 # SKIP SVE set SVE get SVE for VL 5728
3162 12:28:18.950121 # ok 1435 # SKIP SVE set SVE get FPSIMD for VL 5728
3163 12:28:18.950224 # ok 1436 # SKIP SVE set FPSIMD get SVE for VL 5728
3164 12:28:18.950310 # ok 1437 Set SVE VL 5744
3165 12:28:18.950408 # ok 1438 # SKIP SVE set SVE get SVE for VL 5744
3166 12:28:18.950508 # ok 1439 # SKIP SVE set SVE get FPSIMD for VL 5744
3167 12:28:18.950609 # ok 1440 # SKIP SVE set FPSIMD get SVE for VL 5744
3168 12:28:18.950696 # ok 1441 Set SVE VL 5760
3169 12:28:18.950795 # ok 1442 # SKIP SVE set SVE get SVE for VL 5760
3170 12:28:18.951137 # ok 1443 # SKIP SVE set SVE get FPSIMD for VL 5760
3171 12:28:18.951246 # ok 1444 # SKIP SVE set FPSIMD get SVE for VL 5760
3172 12:28:18.951334 # ok 1445 Set SVE VL 5776
3173 12:28:18.951439 # ok 1446 # SKIP SVE set SVE get SVE for VL 5776
3174 12:28:18.952050 # ok 1447 # SKIP SVE set SVE get FPSIMD for VL 5776
3175 12:28:18.952360 # ok 1448 # SKIP SVE set FPSIMD get SVE for VL 5776
3176 12:28:18.952467 # ok 1449 Set SVE VL 5792
3177 12:28:18.952553 # ok 1450 # SKIP SVE set SVE get SVE for VL 5792
3178 12:28:18.952657 # ok 1451 # SKIP SVE set SVE get FPSIMD for VL 5792
3179 12:28:18.952745 # ok 1452 # SKIP SVE set FPSIMD get SVE for VL 5792
3180 12:28:18.952827 # ok 1453 Set SVE VL 5808
3181 12:28:18.952925 # ok 1454 # SKIP SVE set SVE get SVE for VL 5808
3182 12:28:18.953027 # ok 1455 # SKIP SVE set SVE get FPSIMD for VL 5808
3183 12:28:18.953312 # ok 1456 # SKIP SVE set FPSIMD get SVE for VL 5808
3184 12:28:18.953433 # ok 1457 Set SVE VL 5824
3185 12:28:18.953514 # ok 1458 # SKIP SVE set SVE get SVE for VL 5824
3186 12:28:18.953604 # ok 1459 # SKIP SVE set SVE get FPSIMD for VL 5824
3187 12:28:18.953703 # ok 1460 # SKIP SVE set FPSIMD get SVE for VL 5824
3188 12:28:18.953793 # ok 1461 Set SVE VL 5840
3189 12:28:18.953886 # ok 1462 # SKIP SVE set SVE get SVE for VL 5840
3190 12:28:18.954166 # ok 1463 # SKIP SVE set SVE get FPSIMD for VL 5840
3191 12:28:18.954273 # ok 1464 # SKIP SVE set FPSIMD get SVE for VL 5840
3192 12:28:18.954363 # ok 1465 Set SVE VL 5856
3193 12:28:18.954633 # ok 1466 # SKIP SVE set SVE get SVE for VL 5856
3194 12:28:18.954722 # ok 1467 # SKIP SVE set SVE get FPSIMD for VL 5856
3195 12:28:18.955606 # ok 1468 # SKIP SVE set FPSIMD get SVE for VL 5856
3196 12:28:18.955706 # ok 1469 Set SVE VL 5872
3197 12:28:18.955797 # ok 1470 # SKIP SVE set SVE get SVE for VL 5872
3198 12:28:18.955873 # ok 1471 # SKIP SVE set SVE get FPSIMD for VL 5872
3199 12:28:18.955948 # ok 1472 # SKIP SVE set FPSIMD get SVE for VL 5872
3200 12:28:18.956022 # ok 1473 Set SVE VL 5888
3201 12:28:18.956635 # ok 1474 # SKIP SVE set SVE get SVE for VL 5888
3202 12:28:18.956896 # ok 1475 # SKIP SVE set SVE get FPSIMD for VL 5888
3203 12:28:18.957224 # ok 1476 # SKIP SVE set FPSIMD get SVE for VL 5888
3204 12:28:18.957326 # ok 1477 Set SVE VL 5904
3205 12:28:18.957429 # ok 1478 # SKIP SVE set SVE get SVE for VL 5904
3206 12:28:18.957526 # ok 1479 # SKIP SVE set SVE get FPSIMD for VL 5904
3207 12:28:18.957606 # ok 1480 # SKIP SVE set FPSIMD get SVE for VL 5904
3208 12:28:18.957721 # ok 1481 Set SVE VL 5920
3209 12:28:18.957819 # ok 1482 # SKIP SVE set SVE get SVE for VL 5920
3210 12:28:18.957927 # ok 1483 # SKIP SVE set SVE get FPSIMD for VL 5920
3211 12:28:18.958000 # ok 1484 # SKIP SVE set FPSIMD get SVE for VL 5920
3212 12:28:18.958276 # ok 1485 Set SVE VL 5936
3213 12:28:18.958368 # ok 1486 # SKIP SVE set SVE get SVE for VL 5936
3214 12:28:18.958456 # ok 1487 # SKIP SVE set SVE get FPSIMD for VL 5936
3215 12:28:18.958553 # ok 1488 # SKIP SVE set FPSIMD get SVE for VL 5936
3216 12:28:18.958663 # ok 1489 Set SVE VL 5952
3217 12:28:18.958746 # ok 1490 # SKIP SVE set SVE get SVE for VL 5952
3218 12:28:18.958838 # ok 1491 # SKIP SVE set SVE get FPSIMD for VL 5952
3219 12:28:18.958925 # ok 1492 # SKIP SVE set FPSIMD get SVE for VL 5952
3220 12:28:18.959202 # ok 1493 Set SVE VL 5968
3221 12:28:18.959295 # ok 1494 # SKIP SVE set SVE get SVE for VL 5968
3222 12:28:18.960353 # ok 1495 # SKIP SVE set SVE get FPSIMD for VL 5968
3223 12:28:18.960618 # ok 1496 # SKIP SVE set FPSIMD get SVE for VL 5968
3224 12:28:18.960687 # ok 1497 Set SVE VL 5984
3225 12:28:18.960760 # ok 1498 # SKIP SVE set SVE get SVE for VL 5984
3226 12:28:18.961171 # ok 1499 # SKIP SVE set SVE get FPSIMD for VL 5984
3227 12:28:18.961268 # ok 1500 # SKIP SVE set FPSIMD get SVE for VL 5984
3228 12:28:18.961355 # ok 1501 Set SVE VL 6000
3229 12:28:18.961679 # ok 1502 # SKIP SVE set SVE get SVE for VL 6000
3230 12:28:18.961782 # ok 1503 # SKIP SVE set SVE get FPSIMD for VL 6000
3231 12:28:18.961869 # ok 1504 # SKIP SVE set FPSIMD get SVE for VL 6000
3232 12:28:18.961953 # ok 1505 Set SVE VL 6016
3233 12:28:18.962034 # ok 1506 # SKIP SVE set SVE get SVE for VL 6016
3234 12:28:18.962315 # ok 1507 # SKIP SVE set SVE get FPSIMD for VL 6016
3235 12:28:18.962417 # ok 1508 # SKIP SVE set FPSIMD get SVE for VL 6016
3236 12:28:18.962510 # ok 1509 Set SVE VL 6032
3237 12:28:18.962593 # ok 1510 # SKIP SVE set SVE get SVE for VL 6032
3238 12:28:18.962674 # ok 1511 # SKIP SVE set SVE get FPSIMD for VL 6032
3239 12:28:18.962768 # ok 1512 # SKIP SVE set FPSIMD get SVE for VL 6032
3240 12:28:18.965734 # ok 1513 Set SVE VL 6048
3241 12:28:18.965889 # ok 1514 # SKIP SVE set SVE get SVE for VL 6048
3242 12:28:18.966210 # ok 1515 # SKIP SVE set SVE get FPSIMD for VL 6048
3243 12:28:18.966331 # ok 1516 # SKIP SVE set FPSIMD get SVE for VL 6048
3244 12:28:18.966412 # ok 1517 Set SVE VL 6064
3245 12:28:18.966483 # ok 1518 # SKIP SVE set SVE get SVE for VL 6064
3246 12:28:18.966557 # ok 1519 # SKIP SVE set SVE get FPSIMD for VL 6064
3247 12:28:18.966632 # ok 1520 # SKIP SVE set FPSIMD get SVE for VL 6064
3248 12:28:18.966703 # ok 1521 Set SVE VL 6080
3249 12:28:18.966774 # ok 1522 # SKIP SVE set SVE get SVE for VL 6080
3250 12:28:18.966845 # ok 1523 # SKIP SVE set SVE get FPSIMD for VL 6080
3251 12:28:18.966916 # ok 1524 # SKIP SVE set FPSIMD get SVE for VL 6080
3252 12:28:18.966985 # ok 1525 Set SVE VL 6096
3253 12:28:18.967056 # ok 1526 # SKIP SVE set SVE get SVE for VL 6096
3254 12:28:18.967370 # ok 1527 # SKIP SVE set SVE get FPSIMD for VL 6096
3255 12:28:18.967476 # ok 1528 # SKIP SVE set FPSIMD get SVE for VL 6096
3256 12:28:18.967567 # ok 1529 Set SVE VL 6112
3257 12:28:18.967646 # ok 1530 # SKIP SVE set SVE get SVE for VL 6112
3258 12:28:18.967719 # ok 1531 # SKIP SVE set SVE get FPSIMD for VL 6112
3259 12:28:18.967788 # ok 1532 # SKIP SVE set FPSIMD get SVE for VL 6112
3260 12:28:18.967860 # ok 1533 Set SVE VL 6128
3261 12:28:18.967929 # ok 1534 # SKIP SVE set SVE get SVE for VL 6128
3262 12:28:18.968018 # ok 1535 # SKIP SVE set SVE get FPSIMD for VL 6128
3263 12:28:18.968094 # ok 1536 # SKIP SVE set FPSIMD get SVE for VL 6128
3264 12:28:18.968166 # ok 1537 Set SVE VL 6144
3265 12:28:18.968445 # ok 1538 # SKIP SVE set SVE get SVE for VL 6144
3266 12:28:18.968528 # ok 1539 # SKIP SVE set SVE get FPSIMD for VL 6144
3267 12:28:18.968606 # ok 1540 # SKIP SVE set FPSIMD get SVE for VL 6144
3268 12:28:18.968684 # ok 1541 Set SVE VL 6160
3269 12:28:18.968756 # ok 1542 # SKIP SVE set SVE get SVE for VL 6160
3270 12:28:18.968825 # ok 1543 # SKIP SVE set SVE get FPSIMD for VL 6160
3271 12:28:18.968892 # ok 1544 # SKIP SVE set FPSIMD get SVE for VL 6160
3272 12:28:18.968962 # ok 1545 Set SVE VL 6176
3273 12:28:18.969041 # ok 1546 # SKIP SVE set SVE get SVE for VL 6176
3274 12:28:18.969142 # ok 1547 # SKIP SVE set SVE get FPSIMD for VL 6176
3275 12:28:18.969218 # ok 1548 # SKIP SVE set FPSIMD get SVE for VL 6176
3276 12:28:18.969297 # ok 1549 Set SVE VL 6192
3277 12:28:18.969371 # ok 1550 # SKIP SVE set SVE get SVE for VL 6192
3278 12:28:18.969448 # ok 1551 # SKIP SVE set SVE get FPSIMD for VL 6192
3279 12:28:18.969522 # ok 1552 # SKIP SVE set FPSIMD get SVE for VL 6192
3280 12:28:18.969600 # ok 1553 Set SVE VL 6208
3281 12:28:18.969687 # ok 1554 # SKIP SVE set SVE get SVE for VL 6208
3282 12:28:18.969760 # ok 1555 # SKIP SVE set SVE get FPSIMD for VL 6208
3283 12:28:18.969832 # ok 1556 # SKIP SVE set FPSIMD get SVE for VL 6208
3284 12:28:18.970193 # ok 1557 Set SVE VL 6224
3285 12:28:18.970301 # ok 1558 # SKIP SVE set SVE get SVE for VL 6224
3286 12:28:18.970430 # ok 1559 # SKIP SVE set SVE get FPSIMD for VL 6224
3287 12:28:18.970555 # ok 1560 # SKIP SVE set FPSIMD get SVE for VL 6224
3288 12:28:18.970671 # ok 1561 Set SVE VL 6240
3289 12:28:18.970751 # ok 1562 # SKIP SVE set SVE get SVE for VL 6240
3290 12:28:18.970826 # ok 1563 # SKIP SVE set SVE get FPSIMD for VL 6240
3291 12:28:18.970899 # ok 1564 # SKIP SVE set FPSIMD get SVE for VL 6240
3292 12:28:18.970973 # ok 1565 Set SVE VL 6256
3293 12:28:18.971046 # ok 1566 # SKIP SVE set SVE get SVE for VL 6256
3294 12:28:18.971119 # ok 1567 # SKIP SVE set SVE get FPSIMD for VL 6256
3295 12:28:18.971236 # ok 1568 # SKIP SVE set FPSIMD get SVE for VL 6256
3296 12:28:18.971326 # ok 1569 Set SVE VL 6272
3297 12:28:18.971414 # ok 1570 # SKIP SVE set SVE get SVE for VL 6272
3298 12:28:18.971489 # ok 1571 # SKIP SVE set SVE get FPSIMD for VL 6272
3299 12:28:18.971563 # ok 1572 # SKIP SVE set FPSIMD get SVE for VL 6272
3300 12:28:18.971635 # ok 1573 Set SVE VL 6288
3301 12:28:18.971708 # ok 1574 # SKIP SVE set SVE get SVE for VL 6288
3302 12:28:18.971781 # ok 1575 # SKIP SVE set SVE get FPSIMD for VL 6288
3303 12:28:18.971873 # ok 1576 # SKIP SVE set FPSIMD get SVE for VL 6288
3304 12:28:18.971944 # ok 1577 Set SVE VL 6304
3305 12:28:18.972018 # ok 1578 # SKIP SVE set SVE get SVE for VL 6304
3306 12:28:18.972092 # ok 1579 # SKIP SVE set SVE get FPSIMD for VL 6304
3307 12:28:18.972166 # ok 1580 # SKIP SVE set FPSIMD get SVE for VL 6304
3308 12:28:18.972304 # ok 1581 Set SVE VL 6320
3309 12:28:18.972394 # ok 1582 # SKIP SVE set SVE get SVE for VL 6320
3310 12:28:18.972501 # ok 1583 # SKIP SVE set SVE get FPSIMD for VL 6320
3311 12:28:18.972573 # ok 1584 # SKIP SVE set FPSIMD get SVE for VL 6320
3312 12:28:18.972648 # ok 1585 Set SVE VL 6336
3313 12:28:18.972722 # ok 1586 # SKIP SVE set SVE get SVE for VL 6336
3314 12:28:18.972811 # ok 1587 # SKIP SVE set SVE get FPSIMD for VL 6336
3315 12:28:18.972881 # ok 1588 # SKIP SVE set FPSIMD get SVE for VL 6336
3316 12:28:18.972955 # ok 1589 Set SVE VL 6352
3317 12:28:18.975663 # ok 1590 # SKIP SVE set SVE get SVE for VL 6352
3318 12:28:18.975998 # ok 1591 # SKIP SVE set SVE get FPSIMD for VL 6352
3319 12:28:18.976095 # ok 1592 # SKIP SVE set FPSIMD get SVE for VL 6352
3320 12:28:18.976193 # ok 1593 Set SVE VL 6368
3321 12:28:18.976291 # ok 1594 # SKIP SVE set SVE get SVE for VL 6368
3322 12:28:18.976357 # ok 1595 # SKIP SVE set SVE get FPSIMD for VL 6368
3323 12:28:18.976446 # ok 1596 # SKIP SVE set FPSIMD get SVE for VL 6368
3324 12:28:18.976540 # ok 1597 Set SVE VL 6384
3325 12:28:18.976638 # ok 1598 # SKIP SVE set SVE get SVE for VL 6384
3326 12:28:18.976730 # ok 1599 # SKIP SVE set SVE get FPSIMD for VL 6384
3327 12:28:18.977024 # ok 1600 # SKIP SVE set FPSIMD get SVE for VL 6384
3328 12:28:18.977123 # ok 1601 Set SVE VL 6400
3329 12:28:18.977228 # ok 1602 # SKIP SVE set SVE get SVE for VL 6400
3330 12:28:18.977353 # ok 1603 # SKIP SVE set SVE get FPSIMD for VL 6400
3331 12:28:18.977454 # ok 1604 # SKIP SVE set FPSIMD get SVE for VL 6400
3332 12:28:18.977552 # ok 1605 Set SVE VL 6416
3333 12:28:18.977728 # ok 1606 # SKIP SVE set SVE get SVE for VL 6416
3334 12:28:18.977828 # ok 1607 # SKIP SVE set SVE get FPSIMD for VL 6416
3335 12:28:18.977924 # ok 1608 # SKIP SVE set FPSIMD get SVE for VL 6416
3336 12:28:18.978020 # ok 1609 Set SVE VL 6432
3337 12:28:18.978129 # ok 1610 # SKIP SVE set SVE get SVE for VL 6432
3338 12:28:18.978202 # ok 1611 # SKIP SVE set SVE get FPSIMD for VL 6432
3339 12:28:18.978302 # ok 1612 # SKIP SVE set FPSIMD get SVE for VL 6432
3340 12:28:18.978379 # ok 1613 Set SVE VL 6448
3341 12:28:18.978444 # ok 1614 # SKIP SVE set SVE get SVE for VL 6448
3342 12:28:18.978721 # ok 1615 # SKIP SVE set SVE get FPSIMD for VL 6448
3343 12:28:18.978820 # ok 1616 # SKIP SVE set FPSIMD get SVE for VL 6448
3344 12:28:18.978895 # ok 1617 Set SVE VL 6464
3345 12:28:18.978987 # ok 1618 # SKIP SVE set SVE get SVE for VL 6464
3346 12:28:18.979073 # ok 1619 # SKIP SVE set SVE get FPSIMD for VL 6464
3347 12:28:18.979172 # ok 1620 # SKIP SVE set FPSIMD get SVE for VL 6464
3348 12:28:18.979262 # ok 1621 Set SVE VL 6480
3349 12:28:18.979370 # ok 1622 # SKIP SVE set SVE get SVE for VL 6480
3350 12:28:18.979451 # ok 1623 # SKIP SVE set SVE get FPSIMD for VL 6480
3351 12:28:18.979739 # ok 1624 # SKIP SVE set FPSIMD get SVE for VL 6480
3352 12:28:18.979852 # ok 1625 Set SVE VL 6496
3353 12:28:18.979972 # ok 1626 # SKIP SVE set SVE get SVE for VL 6496
3354 12:28:18.980085 # ok 1627 # SKIP SVE set SVE get FPSIMD for VL 6496
3355 12:28:18.980186 # ok 1628 # SKIP SVE set FPSIMD get SVE for VL 6496
3356 12:28:18.980290 # ok 1629 Set SVE VL 6512
3357 12:28:18.980388 # ok 1630 # SKIP SVE set SVE get SVE for VL 6512
3358 12:28:18.980481 # ok 1631 # SKIP SVE set SVE get FPSIMD for VL 6512
3359 12:28:18.980781 # ok 1632 # SKIP SVE set FPSIMD get SVE for VL 6512
3360 12:28:18.980882 # ok 1633 Set SVE VL 6528
3361 12:28:18.980970 # ok 1634 # SKIP SVE set SVE get SVE for VL 6528
3362 12:28:18.981934 # ok 1635 # SKIP SVE set SVE get FPSIMD for VL 6528
3363 12:28:18.982035 # ok 1636 # SKIP SVE set FPSIMD get SVE for VL 6528
3364 12:28:18.982112 # ok 1637 Set SVE VL 6544
3365 12:28:18.982188 # ok 1638 # SKIP SVE set SVE get SVE for VL 6544
3366 12:28:18.982264 # ok 1639 # SKIP SVE set SVE get FPSIMD for VL 6544
3367 12:28:18.982337 # ok 1640 # SKIP SVE set FPSIMD get SVE for VL 6544
3368 12:28:18.982416 # ok 1641 Set SVE VL 6560
3369 12:28:18.982495 # ok 1642 # SKIP SVE set SVE get SVE for VL 6560
3370 12:28:18.982577 # ok 1643 # SKIP SVE set SVE get FPSIMD for VL 6560
3371 12:28:18.982663 # ok 1644 # SKIP SVE set FPSIMD get SVE for VL 6560
3372 12:28:18.982744 # ok 1645 Set SVE VL 6576
3373 12:28:18.982816 # ok 1646 # SKIP SVE set SVE get SVE for VL 6576
3374 12:28:18.982896 # ok 1647 # SKIP SVE set SVE get FPSIMD for VL 6576
3375 12:28:18.982978 # ok 1648 # SKIP SVE set FPSIMD get SVE for VL 6576
3376 12:28:18.983260 # ok 1649 Set SVE VL 6592
3377 12:28:18.983426 # ok 1650 # SKIP SVE set SVE get SVE for VL 6592
3378 12:28:18.983530 # ok 1651 # SKIP SVE set SVE get FPSIMD for VL 6592
3379 12:28:18.983636 # ok 1652 # SKIP SVE set FPSIMD get SVE for VL 6592
3380 12:28:18.983720 # ok 1653 Set SVE VL 6608
3381 12:28:18.983806 # ok 1654 # SKIP SVE set SVE get SVE for VL 6608
3382 12:28:18.983890 # ok 1655 # SKIP SVE set SVE get FPSIMD for VL 6608
3383 12:28:18.983992 # ok 1656 # SKIP SVE set FPSIMD get SVE for VL 6608
3384 12:28:18.984093 # ok 1657 Set SVE VL 6624
3385 12:28:18.984186 # ok 1658 # SKIP SVE set SVE get SVE for VL 6624
3386 12:28:18.984287 # ok 1659 # SKIP SVE set SVE get FPSIMD for VL 6624
3387 12:28:18.984397 # ok 1660 # SKIP SVE set FPSIMD get SVE for VL 6624
3388 12:28:18.984480 # ok 1661 Set SVE VL 6640
3389 12:28:18.984571 # ok 1662 # SKIP SVE set SVE get SVE for VL 6640
3390 12:28:18.984673 # ok 1663 # SKIP SVE set SVE get FPSIMD for VL 6640
3391 12:28:18.984762 # ok 1664 # SKIP SVE set FPSIMD get SVE for VL 6640
3392 12:28:18.984858 # ok 1665 Set SVE VL 6656
3393 12:28:18.984943 # ok 1666 # SKIP SVE set SVE get SVE for VL 6656
3394 12:28:18.985018 # ok 1667 # SKIP SVE set SVE get FPSIMD for VL 6656
3395 12:28:18.985119 # ok 1668 # SKIP SVE set FPSIMD get SVE for VL 6656
3396 12:28:18.985199 # ok 1669 Set SVE VL 6672
3397 12:28:18.985264 # ok 1670 # SKIP SVE set SVE get SVE for VL 6672
3398 12:28:18.985328 # ok 1671 # SKIP SVE set SVE get FPSIMD for VL 6672
3399 12:28:18.985390 # ok 1672 # SKIP SVE set FPSIMD get SVE for VL 6672
3400 12:28:18.985450 # ok 1673 Set SVE VL 6688
3401 12:28:18.985512 # ok 1674 # SKIP SVE set SVE get SVE for VL 6688
3402 12:28:18.985590 # ok 1675 # SKIP SVE set SVE get FPSIMD for VL 6688
3403 12:28:18.985704 # ok 1676 # SKIP SVE set FPSIMD get SVE for VL 6688
3404 12:28:18.985776 # ok 1677 Set SVE VL 6704
3405 12:28:18.985869 # ok 1678 # SKIP SVE set SVE get SVE for VL 6704
3406 12:28:18.985943 # ok 1679 # SKIP SVE set SVE get FPSIMD for VL 6704
3407 12:28:18.986006 # ok 1680 # SKIP SVE set FPSIMD get SVE for VL 6704
3408 12:28:18.986085 # ok 1681 Set SVE VL 6720
3409 12:28:18.986153 # ok 1682 # SKIP SVE set SVE get SVE for VL 6720
3410 12:28:18.986216 # ok 1683 # SKIP SVE set SVE get FPSIMD for VL 6720
3411 12:28:18.986290 # ok 1684 # SKIP SVE set FPSIMD get SVE for VL 6720
3412 12:28:18.986355 # ok 1685 Set SVE VL 6736
3413 12:28:18.986430 # ok 1686 # SKIP SVE set SVE get SVE for VL 6736
3414 12:28:18.986710 # ok 1687 # SKIP SVE set SVE get FPSIMD for VL 6736
3415 12:28:18.986826 # ok 1688 # SKIP SVE set FPSIMD get SVE for VL 6736
3416 12:28:18.987135 # ok 1689 Set SVE VL 6752
3417 12:28:18.987307 # ok 1690 # SKIP SVE set SVE get SVE for VL 6752
3418 12:28:18.987414 # ok 1691 # SKIP SVE set SVE get FPSIMD for VL 6752
3419 12:28:18.987511 # ok 1692 # SKIP SVE set FPSIMD get SVE for VL 6752
3420 12:28:18.987613 # ok 1693 Set SVE VL 6768
3421 12:28:18.987721 # ok 1694 # SKIP SVE set SVE get SVE for VL 6768
3422 12:28:18.987807 # ok 1695 # SKIP SVE set SVE get FPSIMD for VL 6768
3423 12:28:18.987891 # ok 1696 # SKIP SVE set FPSIMD get SVE for VL 6768
3424 12:28:18.987976 # ok 1697 Set SVE VL 6784
3425 12:28:18.988068 # ok 1698 # SKIP SVE set SVE get SVE for VL 6784
3426 12:28:18.988149 # ok 1699 # SKIP SVE set SVE get FPSIMD for VL 6784
3427 12:28:18.988226 # ok 1700 # SKIP SVE set FPSIMD get SVE for VL 6784
3428 12:28:18.988302 # ok 1701 Set SVE VL 6800
3429 12:28:18.988394 # ok 1702 # SKIP SVE set SVE get SVE for VL 6800
3430 12:28:18.988490 # ok 1703 # SKIP SVE set SVE get FPSIMD for VL 6800
3431 12:28:18.988573 # ok 1704 # SKIP SVE set FPSIMD get SVE for VL 6800
3432 12:28:18.988657 # ok 1705 Set SVE VL 6816
3433 12:28:18.988780 # ok 1706 # SKIP SVE set SVE get SVE for VL 6816
3434 12:28:18.988922 # ok 1707 # SKIP SVE set SVE get FPSIMD for VL 6816
3435 12:28:18.989039 # ok 1708 # SKIP SVE set FPSIMD get SVE for VL 6816
3436 12:28:18.989161 # ok 1709 Set SVE VL 6832
3437 12:28:18.989265 # ok 1710 # SKIP SVE set SVE get SVE for VL 6832
3438 12:28:18.989390 # ok 1711 # SKIP SVE set SVE get FPSIMD for VL 6832
3439 12:28:18.989485 # ok 1712 # SKIP SVE set FPSIMD get SVE for VL 6832
3440 12:28:18.989574 # ok 1713 Set SVE VL 6848
3441 12:28:18.989730 # ok 1714 # SKIP SVE set SVE get SVE for VL 6848
3442 12:28:18.989830 # ok 1715 # SKIP SVE set SVE get FPSIMD for VL 6848
3443 12:28:18.989941 # ok 1716 # SKIP SVE set FPSIMD get SVE for VL 6848
3444 12:28:18.990031 # ok 1717 Set SVE VL 6864
3445 12:28:18.990125 # ok 1718 # SKIP SVE set SVE get SVE for VL 6864
3446 12:28:18.990207 # ok 1719 # SKIP SVE set SVE get FPSIMD for VL 6864
3447 12:28:18.990302 # ok 1720 # SKIP SVE set FPSIMD get SVE for VL 6864
3448 12:28:18.990383 # ok 1721 Set SVE VL 6880
3449 12:28:18.990737 # ok 1722 # SKIP SVE set SVE get SVE for VL 6880
3450 12:28:18.990914 # ok 1723 # SKIP SVE set SVE get FPSIMD for VL 6880
3451 12:28:18.991027 # ok 1724 # SKIP SVE set FPSIMD get SVE for VL 6880
3452 12:28:18.991107 # ok 1725 Set SVE VL 6896
3453 12:28:18.991179 # ok 1726 # SKIP SVE set SVE get SVE for VL 6896
3454 12:28:18.991255 # ok 1727 # SKIP SVE set SVE get FPSIMD for VL 6896
3455 12:28:18.991344 # ok 1728 # SKIP SVE set FPSIMD get SVE for VL 6896
3456 12:28:18.991424 # ok 1729 Set SVE VL 6912
3457 12:28:18.991765 # ok 1730 # SKIP SVE set SVE get SVE for VL 6912
3458 12:28:18.991870 # ok 1731 # SKIP SVE set SVE get FPSIMD for VL 6912
3459 12:28:18.991972 # ok 1732 # SKIP SVE set FPSIMD get SVE for VL 6912
3460 12:28:18.992082 # ok 1733 Set SVE VL 6928
3461 12:28:18.992171 # ok 1734 # SKIP SVE set SVE get SVE for VL 6928
3462 12:28:18.992461 # ok 1735 # SKIP SVE set SVE get FPSIMD for VL 6928
3463 12:28:18.992565 # ok 1736 # SKIP SVE set FPSIMD get SVE for VL 6928
3464 12:28:18.992669 # ok 1737 Set SVE VL 6944
3465 12:28:18.992775 # ok 1738 # SKIP SVE set SVE get SVE for VL 6944
3466 12:28:18.992873 # ok 1739 # SKIP SVE set SVE get FPSIMD for VL 6944
3467 12:28:18.992995 # ok 1740 # SKIP SVE set FPSIMD get SVE for VL 6944
3468 12:28:18.993111 # ok 1741 Set SVE VL 6960
3469 12:28:18.993209 # ok 1742 # SKIP SVE set SVE get SVE for VL 6960
3470 12:28:18.993302 # ok 1743 # SKIP SVE set SVE get FPSIMD for VL 6960
3471 12:28:18.993406 # ok 1744 # SKIP SVE set FPSIMD get SVE for VL 6960
3472 12:28:18.993489 # ok 1745 Set SVE VL 6976
3473 12:28:18.993571 # ok 1746 # SKIP SVE set SVE get SVE for VL 6976
3474 12:28:18.993683 # ok 1747 # SKIP SVE set SVE get FPSIMD for VL 6976
3475 12:28:18.993786 # ok 1748 # SKIP SVE set FPSIMD get SVE for VL 6976
3476 12:28:18.993904 # ok 1749 Set SVE VL 6992
3477 12:28:18.994005 # ok 1750 # SKIP SVE set SVE get SVE for VL 6992
3478 12:28:18.994129 # ok 1751 # SKIP SVE set SVE get FPSIMD for VL 6992
3479 12:28:18.994232 # ok 1752 # SKIP SVE set FPSIMD get SVE for VL 6992
3480 12:28:18.994309 # ok 1753 Set SVE VL 7008
3481 12:28:18.994595 # ok 1754 # SKIP SVE set SVE get SVE for VL 7008
3482 12:28:18.994697 # ok 1755 # SKIP SVE set SVE get FPSIMD for VL 7008
3483 12:28:18.994780 # ok 1756 # SKIP SVE set FPSIMD get SVE for VL 7008
3484 12:28:18.994878 # ok 1757 Set SVE VL 7024
3485 12:28:18.994963 # ok 1758 # SKIP SVE set SVE get SVE for VL 7024
3486 12:28:18.995065 # ok 1759 # SKIP SVE set SVE get FPSIMD for VL 7024
3487 12:28:18.995354 # ok 1760 # SKIP SVE set FPSIMD get SVE for VL 7024
3488 12:28:18.995513 # ok 1761 Set SVE VL 7040
3489 12:28:18.995613 # ok 1762 # SKIP SVE set SVE get SVE for VL 7040
3490 12:28:18.995711 # ok 1763 # SKIP SVE set SVE get FPSIMD for VL 7040
3491 12:28:18.995795 # ok 1764 # SKIP SVE set FPSIMD get SVE for VL 7040
3492 12:28:18.995892 # ok 1765 Set SVE VL 7056
3493 12:28:18.995976 # ok 1766 # SKIP SVE set SVE get SVE for VL 7056
3494 12:28:18.996057 # ok 1767 # SKIP SVE set SVE get FPSIMD for VL 7056
3495 12:28:18.996247 # ok 1768 # SKIP SVE set FPSIMD get SVE for VL 7056
3496 12:28:18.996370 # ok 1769 Set SVE VL 7072
3497 12:28:18.996472 # ok 1770 # SKIP SVE set SVE get SVE for VL 7072
3498 12:28:18.996556 # ok 1771 # SKIP SVE set SVE get FPSIMD for VL 7072
3499 12:28:18.996621 # ok 1772 # SKIP SVE set FPSIMD get SVE for VL 7072
3500 12:28:18.999017 # ok 1773 Set SVE VL 7088
3501 12:28:18.999171 # ok 1774 # SKIP SVE set SVE get SVE for VL 7088
3502 12:28:18.999287 # ok 1775 # SKIP SVE set SVE get FPSIMD for VL 7088
3503 12:28:18.999844 # ok 1776 # SKIP SVE set FPSIMD get SVE for VL 7088
3504 12:28:19.000224 # ok 1777 Set SVE VL 7104
3505 12:28:19.000344 # ok 1778 # SKIP SVE set SVE get SVE for VL 7104
3506 12:28:19.000471 # ok 1779 # SKIP SVE set SVE get FPSIMD for VL 7104
3507 12:28:19.000579 # ok 1780 # SKIP SVE set FPSIMD get SVE for VL 7104
3508 12:28:19.000686 # ok 1781 Set SVE VL 7120
3509 12:28:19.000810 # ok 1782 # SKIP SVE set SVE get SVE for VL 7120
3510 12:28:19.000900 # ok 1783 # SKIP SVE set SVE get FPSIMD for VL 7120
3511 12:28:19.000982 # ok 1784 # SKIP SVE set FPSIMD get SVE for VL 7120
3512 12:28:19.001066 # ok 1785 Set SVE VL 7136
3513 12:28:19.001179 # ok 1786 # SKIP SVE set SVE get SVE for VL 7136
3514 12:28:19.001292 # ok 1787 # SKIP SVE set SVE get FPSIMD for VL 7136
3515 12:28:19.001595 # ok 1788 # SKIP SVE set FPSIMD get SVE for VL 7136
3516 12:28:19.001706 # ok 1789 Set SVE VL 7152
3517 12:28:19.001786 # ok 1790 # SKIP SVE set SVE get SVE for VL 7152
3518 12:28:19.001872 # ok 1791 # SKIP SVE set SVE get FPSIMD for VL 7152
3519 12:28:19.001962 # ok 1792 # SKIP SVE set FPSIMD get SVE for VL 7152
3520 12:28:19.002047 # ok 1793 Set SVE VL 7168
3521 12:28:19.002386 # ok 1794 # SKIP SVE set SVE get SVE for VL 7168
3522 12:28:19.002491 # ok 1795 # SKIP SVE set SVE get FPSIMD for VL 7168
3523 12:28:19.002583 # ok 1796 # SKIP SVE set FPSIMD get SVE for VL 7168
3524 12:28:19.002699 # ok 1797 Set SVE VL 7184
3525 12:28:19.002811 # ok 1798 # SKIP SVE set SVE get SVE for VL 7184
3526 12:28:19.002932 # ok 1799 # SKIP SVE set SVE get FPSIMD for VL 7184
3527 12:28:19.003033 # ok 1800 # SKIP SVE set FPSIMD get SVE for VL 7184
3528 12:28:19.003122 # ok 1801 Set SVE VL 7200
3529 12:28:19.003234 # ok 1802 # SKIP SVE set SVE get SVE for VL 7200
3530 12:28:19.003324 # ok 1803 # SKIP SVE set SVE get FPSIMD for VL 7200
3531 12:28:19.003667 # ok 1804 # SKIP SVE set FPSIMD get SVE for VL 7200
3532 12:28:19.004052 # ok 1805 Set SVE VL 7216
3533 12:28:19.004207 # ok 1806 # SKIP SVE set SVE get SVE for VL 7216
3534 12:28:19.004352 # ok 1807 # SKIP SVE set SVE get FPSIMD for VL 7216
3535 12:28:19.004510 # ok 1808 # SKIP SVE set FPSIMD get SVE for VL 7216
3536 12:28:19.004786 # ok 1809 Set SVE VL 7232
3537 12:28:19.004880 # ok 1810 # SKIP SVE set SVE get SVE for VL 7232
3538 12:28:19.004960 # ok 1811 # SKIP SVE set SVE get FPSIMD for VL 7232
3539 12:28:19.005040 # ok 1812 # SKIP SVE set FPSIMD get SVE for VL 7232
3540 12:28:19.005120 # ok 1813 Set SVE VL 7248
3541 12:28:19.005206 # ok 1814 # SKIP SVE set SVE get SVE for VL 7248
3542 12:28:19.005319 # ok 1815 # SKIP SVE set SVE get FPSIMD for VL 7248
3543 12:28:19.005404 # ok 1816 # SKIP SVE set FPSIMD get SVE for VL 7248
3544 12:28:19.005487 # ok 1817 Set SVE VL 7264
3545 12:28:19.005598 # ok 1818 # SKIP SVE set SVE get SVE for VL 7264
3546 12:28:19.005730 # ok 1819 # SKIP SVE set SVE get FPSIMD for VL 7264
3547 12:28:19.005835 # ok 1820 # SKIP SVE set FPSIMD get SVE for VL 7264
3548 12:28:19.005942 # ok 1821 Set SVE VL 7280
3549 12:28:19.006040 # ok 1822 # SKIP SVE set SVE get SVE for VL 7280
3550 12:28:19.006147 # ok 1823 # SKIP SVE set SVE get FPSIMD for VL 7280
3551 12:28:19.006225 # ok 1824 # SKIP SVE set FPSIMD get SVE for VL 7280
3552 12:28:19.006301 # ok 1825 Set SVE VL 7296
3553 12:28:19.006412 # ok 1826 # SKIP SVE set SVE get SVE for VL 7296
3554 12:28:19.006504 # ok 1827 # SKIP SVE set SVE get FPSIMD for VL 7296
3555 12:28:19.006582 # ok 1828 # SKIP SVE set FPSIMD get SVE for VL 7296
3556 12:28:19.006685 # ok 1829 Set SVE VL 7312
3557 12:28:19.006771 # ok 1830 # SKIP SVE set SVE get SVE for VL 7312
3558 12:28:19.006864 # ok 1831 # SKIP SVE set SVE get FPSIMD for VL 7312
3559 12:28:19.006961 # ok 1832 # SKIP SVE set FPSIMD get SVE for VL 7312
3560 12:28:19.007039 # ok 1833 Set SVE VL 7328
3561 12:28:19.007128 # ok 1834 # SKIP SVE set SVE get SVE for VL 7328
3562 12:28:19.007224 # ok 1835 # SKIP SVE set SVE get FPSIMD for VL 7328
3563 12:28:19.007784 # ok 1836 # SKIP SVE set FPSIMD get SVE for VL 7328
3564 12:28:19.007886 # ok 1837 Set SVE VL 7344
3565 12:28:19.007997 # ok 1838 # SKIP SVE set SVE get SVE for VL 7344
3566 12:28:19.008110 # ok 1839 # SKIP SVE set SVE get FPSIMD for VL 7344
3567 12:28:19.008211 # ok 1840 # SKIP SVE set FPSIMD get SVE for VL 7344
3568 12:28:19.008338 # ok 1841 Set SVE VL 7360
3569 12:28:19.008447 # ok 1842 # SKIP SVE set SVE get SVE for VL 7360
3570 12:28:19.008542 # ok 1843 # SKIP SVE set SVE get FPSIMD for VL 7360
3571 12:28:19.008647 # ok 1844 # SKIP SVE set FPSIMD get SVE for VL 7360
3572 12:28:19.008749 # ok 1845 Set SVE VL 7376
3573 12:28:19.008864 # ok 1846 # SKIP SVE set SVE get SVE for VL 7376
3574 12:28:19.008960 # ok 1847 # SKIP SVE set SVE get FPSIMD for VL 7376
3575 12:28:19.009068 # ok 1848 # SKIP SVE set FPSIMD get SVE for VL 7376
3576 12:28:19.009161 # ok 1849 Set SVE VL 7392
3577 12:28:19.009284 # ok 1850 # SKIP SVE set SVE get SVE for VL 7392
3578 12:28:19.009378 # ok 1851 # SKIP SVE set SVE get FPSIMD for VL 7392
3579 12:28:19.009479 # ok 1852 # SKIP SVE set FPSIMD get SVE for VL 7392
3580 12:28:19.009581 # ok 1853 Set SVE VL 7408
3581 12:28:19.009680 # ok 1854 # SKIP SVE set SVE get SVE for VL 7408
3582 12:28:19.009799 # ok 1855 # SKIP SVE set SVE get FPSIMD for VL 7408
3583 12:28:19.009901 # ok 1856 # SKIP SVE set FPSIMD get SVE for VL 7408
3584 12:28:19.009998 # ok 1857 Set SVE VL 7424
3585 12:28:19.010101 # ok 1858 # SKIP SVE set SVE get SVE for VL 7424
3586 12:28:19.010198 # ok 1859 # SKIP SVE set SVE get FPSIMD for VL 7424
3587 12:28:19.010302 # ok 1860 # SKIP SVE set FPSIMD get SVE for VL 7424
3588 12:28:19.010420 # ok 1861 Set SVE VL 7440
3589 12:28:19.010523 # ok 1862 # SKIP SVE set SVE get SVE for VL 7440
3590 12:28:19.010656 # ok 1863 # SKIP SVE set SVE get FPSIMD for VL 7440
3591 12:28:19.010765 # ok 1864 # SKIP SVE set FPSIMD get SVE for VL 7440
3592 12:28:19.010865 # ok 1865 Set SVE VL 7456
3593 12:28:19.010986 # ok 1866 # SKIP SVE set SVE get SVE for VL 7456
3594 12:28:19.011080 # ok 1867 # SKIP SVE set SVE get FPSIMD for VL 7456
3595 12:28:19.011168 # ok 1868 # SKIP SVE set FPSIMD get SVE for VL 7456
3596 12:28:19.011276 # ok 1869 Set SVE VL 7472
3597 12:28:19.011363 # ok 1870 # SKIP SVE set SVE get SVE for VL 7472
3598 12:28:19.011460 # ok 1871 # SKIP SVE set SVE get FPSIMD for VL 7472
3599 12:28:19.011552 # ok 1872 # SKIP SVE set FPSIMD get SVE for VL 7472
3600 12:28:19.020984 # ok 1873 Set SVE VL 7488
3601 12:28:19.021181 # ok 1874 # SKIP SVE set SVE get SVE for VL 7488
3602 12:28:19.021248 # ok 1875 # SKIP SVE set SVE get FPSIMD for VL 7488
3603 12:28:19.021309 # ok 1876 # SKIP SVE set FPSIMD get SVE for VL 7488
3604 12:28:19.021370 # ok 1877 Set SVE VL 7504
3605 12:28:19.021429 # ok 1878 # SKIP SVE set SVE get SVE for VL 7504
3606 12:28:19.021488 # ok 1879 # SKIP SVE set SVE get FPSIMD for VL 7504
3607 12:28:19.021547 # ok 1880 # SKIP SVE set FPSIMD get SVE for VL 7504
3608 12:28:19.021631 # ok 1881 Set SVE VL 7520
3609 12:28:19.021711 # ok 1882 # SKIP SVE set SVE get SVE for VL 7520
3610 12:28:19.021771 # ok 1883 # SKIP SVE set SVE get FPSIMD for VL 7520
3611 12:28:19.021831 # ok 1884 # SKIP SVE set FPSIMD get SVE for VL 7520
3612 12:28:19.021889 # ok 1885 Set SVE VL 7536
3613 12:28:19.021949 # ok 1886 # SKIP SVE set SVE get SVE for VL 7536
3614 12:28:19.022007 # ok 1887 # SKIP SVE set SVE get FPSIMD for VL 7536
3615 12:28:19.022066 # ok 1888 # SKIP SVE set FPSIMD get SVE for VL 7536
3616 12:28:19.022125 # ok 1889 Set SVE VL 7552
3617 12:28:19.022185 # ok 1890 # SKIP SVE set SVE get SVE for VL 7552
3618 12:28:19.022243 # ok 1891 # SKIP SVE set SVE get FPSIMD for VL 7552
3619 12:28:19.022302 # ok 1892 # SKIP SVE set FPSIMD get SVE for VL 7552
3620 12:28:19.022366 # ok 1893 Set SVE VL 7568
3621 12:28:19.022427 # ok 1894 # SKIP SVE set SVE get SVE for VL 7568
3622 12:28:19.022485 # ok 1895 # SKIP SVE set SVE get FPSIMD for VL 7568
3623 12:28:19.022544 # ok 1896 # SKIP SVE set FPSIMD get SVE for VL 7568
3624 12:28:19.022606 # ok 1897 Set SVE VL 7584
3625 12:28:19.022673 # ok 1898 # SKIP SVE set SVE get SVE for VL 7584
3626 12:28:19.022746 # ok 1899 # SKIP SVE set SVE get FPSIMD for VL 7584
3627 12:28:19.022821 # ok 1900 # SKIP SVE set FPSIMD get SVE for VL 7584
3628 12:28:19.022893 # ok 1901 Set SVE VL 7600
3629 12:28:19.022985 # ok 1902 # SKIP SVE set SVE get SVE for VL 7600
3630 12:28:19.023068 # ok 1903 # SKIP SVE set SVE get FPSIMD for VL 7600
3631 12:28:19.023143 # ok 1904 # SKIP SVE set FPSIMD get SVE for VL 7600
3632 12:28:19.023235 # ok 1905 Set SVE VL 7616
3633 12:28:19.023338 # ok 1906 # SKIP SVE set SVE get SVE for VL 7616
3634 12:28:19.023437 # ok 1907 # SKIP SVE set SVE get FPSIMD for VL 7616
3635 12:28:19.023514 # ok 1908 # SKIP SVE set FPSIMD get SVE for VL 7616
3636 12:28:19.023578 # ok 1909 Set SVE VL 7632
3637 12:28:19.023637 # ok 1910 # SKIP SVE set SVE get SVE for VL 7632
3638 12:28:19.023695 # ok 1911 # SKIP SVE set SVE get FPSIMD for VL 7632
3639 12:28:19.023780 # ok 1912 # SKIP SVE set FPSIMD get SVE for VL 7632
3640 12:28:19.023881 # ok 1913 Set SVE VL 7648
3641 12:28:19.023977 # ok 1914 # SKIP SVE set SVE get SVE for VL 7648
3642 12:28:19.024059 # ok 1915 # SKIP SVE set SVE get FPSIMD for VL 7648
3643 12:28:19.024399 # ok 1916 # SKIP SVE set FPSIMD get SVE for VL 7648
3644 12:28:19.024489 # ok 1917 Set SVE VL 7664
3645 12:28:19.024585 # ok 1918 # SKIP SVE set SVE get SVE for VL 7664
3646 12:28:19.024681 # ok 1919 # SKIP SVE set SVE get FPSIMD for VL 7664
3647 12:28:19.024760 # ok 1920 # SKIP SVE set FPSIMD get SVE for VL 7664
3648 12:28:19.024838 # ok 1921 Set SVE VL 7680
3649 12:28:19.024921 # ok 1922 # SKIP SVE set SVE get SVE for VL 7680
3650 12:28:19.025008 # ok 1923 # SKIP SVE set SVE get FPSIMD for VL 7680
3651 12:28:19.025086 # ok 1924 # SKIP SVE set FPSIMD get SVE for VL 7680
3652 12:28:19.025163 # ok 1925 Set SVE VL 7696
3653 12:28:19.025249 # ok 1926 # SKIP SVE set SVE get SVE for VL 7696
3654 12:28:19.025325 # ok 1927 # SKIP SVE set SVE get FPSIMD for VL 7696
3655 12:28:19.025403 # ok 1928 # SKIP SVE set FPSIMD get SVE for VL 7696
3656 12:28:19.025480 # ok 1929 Set SVE VL 7712
3657 12:28:19.025564 # ok 1930 # SKIP SVE set SVE get SVE for VL 7712
3658 12:28:19.025670 # ok 1931 # SKIP SVE set SVE get FPSIMD for VL 7712
3659 12:28:19.025795 # ok 1932 # SKIP SVE set FPSIMD get SVE for VL 7712
3660 12:28:19.025907 # ok 1933 Set SVE VL 7728
3661 12:28:19.026029 # ok 1934 # SKIP SVE set SVE get SVE for VL 7728
3662 12:28:19.026122 # ok 1935 # SKIP SVE set SVE get FPSIMD for VL 7728
3663 12:28:19.026202 # ok 1936 # SKIP SVE set FPSIMD get SVE for VL 7728
3664 12:28:19.026282 # ok 1937 Set SVE VL 7744
3665 12:28:19.026365 # ok 1938 # SKIP SVE set SVE get SVE for VL 7744
3666 12:28:19.026448 # ok 1939 # SKIP SVE set SVE get FPSIMD for VL 7744
3667 12:28:19.026536 # ok 1940 # SKIP SVE set FPSIMD get SVE for VL 7744
3668 12:28:19.026628 # ok 1941 Set SVE VL 7760
3669 12:28:19.026744 # ok 1942 # SKIP SVE set SVE get SVE for VL 7760
3670 12:28:19.026848 # ok 1943 # SKIP SVE set SVE get FPSIMD for VL 7760
3671 12:28:19.026969 # ok 1944 # SKIP SVE set FPSIMD get SVE for VL 7760
3672 12:28:19.027079 # ok 1945 Set SVE VL 7776
3673 12:28:19.027195 # ok 1946 # SKIP SVE set SVE get SVE for VL 7776
3674 12:28:19.027303 # ok 1947 # SKIP SVE set SVE get FPSIMD for VL 7776
3675 12:28:19.027391 # ok 1948 # SKIP SVE set FPSIMD get SVE for VL 7776
3676 12:28:19.027477 # ok 1949 Set SVE VL 7792
3677 12:28:19.027560 # ok 1950 # SKIP SVE set SVE get SVE for VL 7792
3678 12:28:19.027635 # ok 1951 # SKIP SVE set SVE get FPSIMD for VL 7792
3679 12:28:19.027721 # ok 1952 # SKIP SVE set FPSIMD get SVE for VL 7792
3680 12:28:19.027799 # ok 1953 Set SVE VL 7808
3681 12:28:19.027897 # ok 1954 # SKIP SVE set SVE get SVE for VL 7808
3682 12:28:19.027994 # ok 1955 # SKIP SVE set SVE get FPSIMD for VL 7808
3683 12:28:19.028088 # ok 1956 # SKIP SVE set FPSIMD get SVE for VL 7808
3684 12:28:19.028174 # ok 1957 Set SVE VL 7824
3685 12:28:19.028249 # ok 1958 # SKIP SVE set SVE get SVE for VL 7824
3686 12:28:19.028539 # ok 1959 # SKIP SVE set SVE get FPSIMD for VL 7824
3687 12:28:19.028636 # ok 1960 # SKIP SVE set FPSIMD get SVE for VL 7824
3688 12:28:19.028723 # ok 1961 Set SVE VL 7840
3689 12:28:19.028798 # ok 1962 # SKIP SVE set SVE get SVE for VL 7840
3690 12:28:19.028878 # ok 1963 # SKIP SVE set SVE get FPSIMD for VL 7840
3691 12:28:19.028959 # ok 1964 # SKIP SVE set FPSIMD get SVE for VL 7840
3692 12:28:19.029053 # ok 1965 Set SVE VL 7856
3693 12:28:19.029135 # ok 1966 # SKIP SVE set SVE get SVE for VL 7856
3694 12:28:19.029219 # ok 1967 # SKIP SVE set SVE get FPSIMD for VL 7856
3695 12:28:19.029300 # ok 1968 # SKIP SVE set FPSIMD get SVE for VL 7856
3696 12:28:19.029382 # ok 1969 Set SVE VL 7872
3697 12:28:19.029458 # ok 1970 # SKIP SVE set SVE get SVE for VL 7872
3698 12:28:19.029540 # ok 1971 # SKIP SVE set SVE get FPSIMD for VL 7872
3699 12:28:19.029620 # ok 1972 # SKIP SVE set FPSIMD get SVE for VL 7872
3700 12:28:19.029714 # ok 1973 Set SVE VL 7888
3701 12:28:19.029798 # ok 1974 # SKIP SVE set SVE get SVE for VL 7888
3702 12:28:19.029898 # ok 1975 # SKIP SVE set SVE get FPSIMD for VL 7888
3703 12:28:19.029993 # ok 1976 # SKIP SVE set FPSIMD get SVE for VL 7888
3704 12:28:19.030096 # ok 1977 Set SVE VL 7904
3705 12:28:19.030183 # ok 1978 # SKIP SVE set SVE get SVE for VL 7904
3706 12:28:19.030261 # ok 1979 # SKIP SVE set SVE get FPSIMD for VL 7904
3707 12:28:19.030353 # ok 1980 # SKIP SVE set FPSIMD get SVE for VL 7904
3708 12:28:19.030441 # ok 1981 Set SVE VL 7920
3709 12:28:19.030523 # ok 1982 # SKIP SVE set SVE get SVE for VL 7920
3710 12:28:19.030634 # ok 1983 # SKIP SVE set SVE get FPSIMD for VL 7920
3711 12:28:19.030737 # ok 1984 # SKIP SVE set FPSIMD get SVE for VL 7920
3712 12:28:19.030833 # ok 1985 Set SVE VL 7936
3713 12:28:19.030921 # ok 1986 # SKIP SVE set SVE get SVE for VL 7936
3714 12:28:19.030993 # ok 1987 # SKIP SVE set SVE get FPSIMD for VL 7936
3715 12:28:19.031071 # ok 1988 # SKIP SVE set FPSIMD get SVE for VL 7936
3716 12:28:19.031157 # ok 1989 Set SVE VL 7952
3717 12:28:19.031261 # ok 1990 # SKIP SVE set SVE get SVE for VL 7952
3718 12:28:19.031358 # ok 1991 # SKIP SVE set SVE get FPSIMD for VL 7952
3719 12:28:19.031448 # ok 1992 # SKIP SVE set FPSIMD get SVE for VL 7952
3720 12:28:19.031523 # ok 1993 Set SVE VL 7968
3721 12:28:19.031625 # ok 1994 # SKIP SVE set SVE get SVE for VL 7968
3722 12:28:19.031729 # ok 1995 # SKIP SVE set SVE get FPSIMD for VL 7968
3723 12:28:19.031823 # ok 1996 # SKIP SVE set FPSIMD get SVE for VL 7968
3724 12:28:19.031925 # ok 1997 Set SVE VL 7984
3725 12:28:19.032013 # ok 1998 # SKIP SVE set SVE get SVE for VL 7984
3726 12:28:19.032106 # ok 1999 # SKIP SVE set SVE get FPSIMD for VL 7984
3727 12:28:19.032201 # ok 2000 # SKIP SVE set FPSIMD get SVE for VL 7984
3728 12:28:19.032289 # ok 2001 Set SVE VL 8000
3729 12:28:19.032571 # ok 2002 # SKIP SVE set SVE get SVE for VL 8000
3730 12:28:19.032675 # ok 2003 # SKIP SVE set SVE get FPSIMD for VL 8000
3731 12:28:19.032783 # ok 2004 # SKIP SVE set FPSIMD get SVE for VL 8000
3732 12:28:19.032880 # ok 2005 Set SVE VL 8016
3733 12:28:19.032975 # ok 2006 # SKIP SVE set SVE get SVE for VL 8016
3734 12:28:19.033084 # ok 2007 # SKIP SVE set SVE get FPSIMD for VL 8016
3735 12:28:19.033191 # ok 2008 # SKIP SVE set FPSIMD get SVE for VL 8016
3736 12:28:19.033309 # ok 2009 Set SVE VL 8032
3737 12:28:19.033418 # ok 2010 # SKIP SVE set SVE get SVE for VL 8032
3738 12:28:19.033535 # ok 2011 # SKIP SVE set SVE get FPSIMD for VL 8032
3739 12:28:19.033662 # ok 2012 # SKIP SVE set FPSIMD get SVE for VL 8032
3740 12:28:19.033773 # ok 2013 Set SVE VL 8048
3741 12:28:19.033907 # ok 2014 # SKIP SVE set SVE get SVE for VL 8048
3742 12:28:19.034023 # ok 2015 # SKIP SVE set SVE get FPSIMD for VL 8048
3743 12:28:19.034122 # ok 2016 # SKIP SVE set FPSIMD get SVE for VL 8048
3744 12:28:19.034230 # ok 2017 Set SVE VL 8064
3745 12:28:19.034332 # ok 2018 # SKIP SVE set SVE get SVE for VL 8064
3746 12:28:19.034436 # ok 2019 # SKIP SVE set SVE get FPSIMD for VL 8064
3747 12:28:19.034537 # ok 2020 # SKIP SVE set FPSIMD get SVE for VL 8064
3748 12:28:19.034633 # ok 2021 Set SVE VL 8080
3749 12:28:19.034746 # ok 2022 # SKIP SVE set SVE get SVE for VL 8080
3750 12:28:19.034840 # ok 2023 # SKIP SVE set SVE get FPSIMD for VL 8080
3751 12:28:19.034944 # ok 2024 # SKIP SVE set FPSIMD get SVE for VL 8080
3752 12:28:19.035033 # ok 2025 Set SVE VL 8096
3753 12:28:19.035148 # ok 2026 # SKIP SVE set SVE get SVE for VL 8096
3754 12:28:19.035261 # ok 2027 # SKIP SVE set SVE get FPSIMD for VL 8096
3755 12:28:19.035367 # ok 2028 # SKIP SVE set FPSIMD get SVE for VL 8096
3756 12:28:19.035463 # ok 2029 Set SVE VL 8112
3757 12:28:19.035560 # ok 2030 # SKIP SVE set SVE get SVE for VL 8112
3758 12:28:19.035666 # ok 2031 # SKIP SVE set SVE get FPSIMD for VL 8112
3759 12:28:19.035764 # ok 2032 # SKIP SVE set FPSIMD get SVE for VL 8112
3760 12:28:19.035869 # ok 2033 Set SVE VL 8128
3761 12:28:19.035954 # ok 2034 # SKIP SVE set SVE get SVE for VL 8128
3762 12:28:19.036034 # ok 2035 # SKIP SVE set SVE get FPSIMD for VL 8128
3763 12:28:19.036144 # ok 2036 # SKIP SVE set FPSIMD get SVE for VL 8128
3764 12:28:19.036246 # ok 2037 Set SVE VL 8144
3765 12:28:19.036351 # ok 2038 # SKIP SVE set SVE get SVE for VL 8144
3766 12:28:19.036454 # ok 2039 # SKIP SVE set SVE get FPSIMD for VL 8144
3767 12:28:19.036556 # ok 2040 # SKIP SVE set FPSIMD get SVE for VL 8144
3768 12:28:19.036647 # ok 2041 Set SVE VL 8160
3769 12:28:19.036753 # ok 2042 # SKIP SVE set SVE get SVE for VL 8160
3770 12:28:19.036856 # ok 2043 # SKIP SVE set SVE get FPSIMD for VL 8160
3771 12:28:19.037410 # ok 2044 # SKIP SVE set FPSIMD get SVE for VL 8160
3772 12:28:19.037519 # ok 2045 Set SVE VL 8176
3773 12:28:19.037622 # ok 2046 # SKIP SVE set SVE get SVE for VL 8176
3774 12:28:19.037868 # ok 2047 # SKIP SVE set SVE get FPSIMD for VL 8176
3775 12:28:19.037956 # ok 2048 # SKIP SVE set FPSIMD get SVE for VL 8176
3776 12:28:19.038038 # ok 2049 Set SVE VL 8192
3777 12:28:19.038116 # ok 2050 # SKIP SVE set SVE get SVE for VL 8192
3778 12:28:19.038218 # ok 2051 # SKIP SVE set SVE get FPSIMD for VL 8192
3779 12:28:19.038327 # ok 2052 # SKIP SVE set FPSIMD get SVE for VL 8192
3780 12:28:19.038437 # ok 2053 Streaming SVE FPSIMD set via SVE: 0
3781 12:28:19.038533 # ok 2054 Streaming SVE get_fpsimd() gave same state
3782 12:28:19.038630 # ok 2055 Streaming SVE SVE_PT_VL_INHERIT set
3783 12:28:19.038728 # ok 2056 Streaming SVE SVE_PT_VL_INHERIT cleared
3784 12:28:19.038819 # ok 2057 Set Streaming SVE VL 16
3785 12:28:19.038904 # ok 2058 Set and get Streaming SVE data for VL 16
3786 12:28:19.038989 # ok 2059 Set and get FPSIMD data for Streaming SVE VL 16
3787 12:28:19.039091 # ok 2060 Set FPSIMD, read via SVE for Streaming SVE VL 16
3788 12:28:19.039196 # ok 2061 Set Streaming SVE VL 32
3789 12:28:19.039301 # ok 2062 Set and get Streaming SVE data for VL 32
3790 12:28:19.039395 # ok 2063 Set and get FPSIMD data for Streaming SVE VL 32
3791 12:28:19.039493 # ok 2064 Set FPSIMD, read via SVE for Streaming SVE VL 32
3792 12:28:19.039590 # ok 2065 Set Streaming SVE VL 48
3793 12:28:19.039686 # ok 2066 # SKIP Streaming SVE set SVE get SVE for VL 48
3794 12:28:19.039800 # ok 2067 # SKIP Streaming SVE set SVE get FPSIMD for VL 48
3795 12:28:19.039917 # ok 2068 # SKIP Streaming SVE set FPSIMD get SVE for VL 48
3796 12:28:19.040015 # ok 2069 Set Streaming SVE VL 64
3797 12:28:19.040134 # ok 2070 Set and get Streaming SVE data for VL 64
3798 12:28:19.040224 # ok 2071 Set and get FPSIMD data for Streaming SVE VL 64
3799 12:28:19.040310 # ok 2072 Set FPSIMD, read via SVE for Streaming SVE VL 64
3800 12:28:19.040394 # ok 2073 Set Streaming SVE VL 80
3801 12:28:19.040471 # ok 2074 # SKIP Streaming SVE set SVE get SVE for VL 80
3802 12:28:19.040546 # ok 2075 # SKIP Streaming SVE set SVE get FPSIMD for VL 80
3803 12:28:19.040625 # ok 2076 # SKIP Streaming SVE set FPSIMD get SVE for VL 80
3804 12:28:19.040704 # ok 2077 Set Streaming SVE VL 96
3805 12:28:19.040780 # ok 2078 # SKIP Streaming SVE set SVE get SVE for VL 96
3806 12:28:19.040857 # ok 2079 # SKIP Streaming SVE set SVE get FPSIMD for VL 96
3807 12:28:19.040937 # ok 2080 # SKIP Streaming SVE set FPSIMD get SVE for VL 96
3808 12:28:19.041016 # ok 2081 Set Streaming SVE VL 112
3809 12:28:19.041094 # ok 2082 # SKIP Streaming SVE set SVE get SVE for VL 112
3810 12:28:19.041381 # ok 2083 # SKIP Streaming SVE set SVE get FPSIMD for VL 112
3811 12:28:19.041476 # ok 2084 # SKIP Streaming SVE set FPSIMD get SVE for VL 112
3812 12:28:19.041560 # ok 2085 Set Streaming SVE VL 128
3813 12:28:19.041642 # ok 2086 Set and get Streaming SVE data for VL 128
3814 12:28:19.041747 # ok 2087 Set and get FPSIMD data for Streaming SVE VL 128
3815 12:28:19.041823 # ok 2088 Set FPSIMD, read via SVE for Streaming SVE VL 128
3816 12:28:19.041905 # ok 2089 Set Streaming SVE VL 144
3817 12:28:19.041989 # ok 2090 # SKIP Streaming SVE set SVE get SVE for VL 144
3818 12:28:19.042070 # ok 2091 # SKIP Streaming SVE set SVE get FPSIMD for VL 144
3819 12:28:19.042150 # ok 2092 # SKIP Streaming SVE set FPSIMD get SVE for VL 144
3820 12:28:19.042231 # ok 2093 Set Streaming SVE VL 160
3821 12:28:19.042314 # ok 2094 # SKIP Streaming SVE set SVE get SVE for VL 160
3822 12:28:19.042395 # ok 2095 # SKIP Streaming SVE set SVE get FPSIMD for VL 160
3823 12:28:19.042498 # ok 2096 # SKIP Streaming SVE set FPSIMD get SVE for VL 160
3824 12:28:19.042581 # ok 2097 Set Streaming SVE VL 176
3825 12:28:19.042662 # ok 2098 # SKIP Streaming SVE set SVE get SVE for VL 176
3826 12:28:19.042745 # ok 2099 # SKIP Streaming SVE set SVE get FPSIMD for VL 176
3827 12:28:19.042834 # ok 2100 # SKIP Streaming SVE set FPSIMD get SVE for VL 176
3828 12:28:19.042916 # ok 2101 Set Streaming SVE VL 192
3829 12:28:19.043000 # ok 2102 # SKIP Streaming SVE set SVE get SVE for VL 192
3830 12:28:19.043297 # ok 2103 # SKIP Streaming SVE set SVE get FPSIMD for VL 192
3831 12:28:19.043391 # ok 2104 # SKIP Streaming SVE set FPSIMD get SVE for VL 192
3832 12:28:19.043474 # ok 2105 Set Streaming SVE VL 208
3833 12:28:19.043547 # ok 2106 # SKIP Streaming SVE set SVE get SVE for VL 208
3834 12:28:19.043628 # ok 2107 # SKIP Streaming SVE set SVE get FPSIMD for VL 208
3835 12:28:19.043729 # ok 2108 # SKIP Streaming SVE set FPSIMD get SVE for VL 208
3836 12:28:19.043808 # ok 2109 Set Streaming SVE VL 224
3837 12:28:19.043932 # ok 2110 # SKIP Streaming SVE set SVE get SVE for VL 224
3838 12:28:19.044039 # ok 2111 # SKIP Streaming SVE set SVE get FPSIMD for VL 224
3839 12:28:19.044238 # ok 2112 # SKIP Streaming SVE set FPSIMD get SVE for VL 224
3840 12:28:19.044364 # ok 2113 Set Streaming SVE VL 240
3841 12:28:19.044459 # ok 2114 # SKIP Streaming SVE set SVE get SVE for VL 240
3842 12:28:19.044578 # ok 2115 # SKIP Streaming SVE set SVE get FPSIMD for VL 240
3843 12:28:19.044720 # ok 2116 # SKIP Streaming SVE set FPSIMD get SVE for VL 240
3844 12:28:19.044902 # ok 2117 Set Streaming SVE VL 256
3845 12:28:19.045166 # ok 2118 Set and get Streaming SVE data for VL 256
3846 12:28:19.045262 # ok 2119 Set and get FPSIMD data for Streaming SVE VL 256
3847 12:28:19.045390 # ok 2120 Set FPSIMD, read via SVE for Streaming SVE VL 256
3848 12:28:19.045499 # ok 2121 Set Streaming SVE VL 272
3849 12:28:19.045624 # ok 2122 # SKIP Streaming SVE set SVE get SVE for VL 272
3850 12:28:19.045765 # ok 2123 # SKIP Streaming SVE set SVE get FPSIMD for VL 272
3851 12:28:19.045891 # ok 2124 # SKIP Streaming SVE set FPSIMD get SVE for VL 272
3852 12:28:19.046009 # ok 2125 Set Streaming SVE VL 288
3853 12:28:19.049658 # ok 2126 # SKIP Streaming SVE set SVE get SVE for VL 288
3854 12:28:19.049854 # ok 2127 # SKIP Streaming SVE set SVE get FPSIMD for VL 288
3855 12:28:19.049938 # ok 2128 # SKIP Streaming SVE set FPSIMD get SVE for VL 288
3856 12:28:19.050028 # ok 2129 Set Streaming SVE VL 304
3857 12:28:19.050117 # ok 2130 # SKIP Streaming SVE set SVE get SVE for VL 304
3858 12:28:19.050531 # ok 2131 # SKIP Streaming SVE set SVE get FPSIMD for VL 304
3859 12:28:19.050636 # ok 2132 # SKIP Streaming SVE set FPSIMD get SVE for VL 304
3860 12:28:19.050772 # ok 2133 Set Streaming SVE VL 320
3861 12:28:19.050898 # ok 2134 # SKIP Streaming SVE set SVE get SVE for VL 320
3862 12:28:19.051027 # ok 2135 # SKIP Streaming SVE set SVE get FPSIMD for VL 320
3863 12:28:19.051327 # ok 2136 # SKIP Streaming SVE set FPSIMD get SVE for VL 320
3864 12:28:19.051404 # ok 2137 Set Streaming SVE VL 336
3865 12:28:19.051738 # ok 2138 # SKIP Streaming SVE set SVE get SVE for VL 336
3866 12:28:19.052050 # ok 2139 # SKIP Streaming SVE set SVE get FPSIMD for VL 336
3867 12:28:19.052165 # ok 2140 # SKIP Streaming SVE set FPSIMD get SVE for VL 336
3868 12:28:19.052288 # ok 2141 Set Streaming SVE VL 352
3869 12:28:19.052401 # ok 2142 # SKIP Streaming SVE set SVE get SVE for VL 352
3870 12:28:19.052513 # ok 2143 # SKIP Streaming SVE set SVE get FPSIMD for VL 352
3871 12:28:19.052788 # ok 2144 # SKIP Streaming SVE set FPSIMD get SVE for VL 352
3872 12:28:19.052881 # ok 2145 Set Streaming SVE VL 368
3873 12:28:19.052975 # ok 2146 # SKIP Streaming SVE set SVE get SVE for VL 368
3874 12:28:19.053071 # ok 2147 # SKIP Streaming SVE set SVE get FPSIMD for VL 368
3875 12:28:19.053388 # ok 2148 # SKIP Streaming SVE set FPSIMD get SVE for VL 368
3876 12:28:19.053529 # ok 2149 Set Streaming SVE VL 384
3877 12:28:19.053843 # ok 2150 # SKIP Streaming SVE set SVE get SVE for VL 384
3878 12:28:19.053939 # ok 2151 # SKIP Streaming SVE set SVE get FPSIMD for VL 384
3879 12:28:19.054025 # ok 2152 # SKIP Streaming SVE set FPSIMD get SVE for VL 384
3880 12:28:19.054111 # ok 2153 Set Streaming SVE VL 400
3881 12:28:19.054208 # ok 2154 # SKIP Streaming SVE set SVE get SVE for VL 400
3882 12:28:19.054499 # ok 2155 # SKIP Streaming SVE set SVE get FPSIMD for VL 400
3883 12:28:19.054619 # ok 2156 # SKIP Streaming SVE set FPSIMD get SVE for VL 400
3884 12:28:19.054716 # ok 2157 Set Streaming SVE VL 416
3885 12:28:19.054822 # ok 2158 # SKIP Streaming SVE set SVE get SVE for VL 416
3886 12:28:19.055119 # ok 2159 # SKIP Streaming SVE set SVE get FPSIMD for VL 416
3887 12:28:19.055225 # ok 2160 # SKIP Streaming SVE set FPSIMD get SVE for VL 416
3888 12:28:19.055337 # ok 2161 Set Streaming SVE VL 432
3889 12:28:19.055654 # ok 2162 # SKIP Streaming SVE set SVE get SVE for VL 432
3890 12:28:19.056003 # ok 2163 # SKIP Streaming SVE set SVE get FPSIMD for VL 432
3891 12:28:19.056102 # ok 2164 # SKIP Streaming SVE set FPSIMD get SVE for VL 432
3892 12:28:19.056193 # ok 2165 Set Streaming SVE VL 448
3893 12:28:19.056281 # ok 2166 # SKIP Streaming SVE set SVE get SVE for VL 448
3894 12:28:19.056569 # ok 2167 # SKIP Streaming SVE set SVE get FPSIMD for VL 448
3895 12:28:19.056664 # ok 2168 # SKIP Streaming SVE set FPSIMD get SVE for VL 448
3896 12:28:19.056760 # ok 2169 Set Streaming SVE VL 464
3897 12:28:19.056861 # ok 2170 # SKIP Streaming SVE set SVE get SVE for VL 464
3898 12:28:19.057170 # ok 2171 # SKIP Streaming SVE set SVE get FPSIMD for VL 464
3899 12:28:19.057301 # ok 2172 # SKIP Streaming SVE set FPSIMD get SVE for VL 464
3900 12:28:19.057411 # ok 2173 Set Streaming SVE VL 480
3901 12:28:19.057509 # ok 2174 # SKIP Streaming SVE set SVE get SVE for VL 480
3902 12:28:19.061715 # ok 2175 # SKIP Streaming SVE set SVE get FPSIMD for VL 480
3903 12:28:19.061993 # ok 2176 # SKIP Streaming SVE set FPSIMD get SVE for VL 480
3904 12:28:19.062110 # ok 2177 Set Streaming SVE VL 496
3905 12:28:19.062224 # ok 2178 # SKIP Streaming SVE set SVE get SVE for VL 496
3906 12:28:19.062353 # ok 2179 # SKIP Streaming SVE set SVE get FPSIMD for VL 496
3907 12:28:19.062478 # ok 2180 # SKIP Streaming SVE set FPSIMD get SVE for VL 496
3908 12:28:19.062587 # ok 2181 Set Streaming SVE VL 512
3909 12:28:19.062690 # ok 2182 # SKIP Streaming SVE set SVE get SVE for VL 512
3910 12:28:19.062808 # ok 2183 # SKIP Streaming SVE set SVE get FPSIMD for VL 512
3911 12:28:19.062923 # ok 2184 # SKIP Streaming SVE set FPSIMD get SVE for VL 512
3912 12:28:19.063029 # ok 2185 Set Streaming SVE VL 528
3913 12:28:19.063130 # ok 2186 # SKIP Streaming SVE set SVE get SVE for VL 528
3914 12:28:19.063208 # ok 2187 # SKIP Streaming SVE set SVE get FPSIMD for VL 528
3915 12:28:19.063285 # ok 2188 # SKIP Streaming SVE set FPSIMD get SVE for VL 528
3916 12:28:19.063356 # ok 2189 Set Streaming SVE VL 544
3917 12:28:19.063417 # ok 2190 # SKIP Streaming SVE set SVE get SVE for VL 544
3918 12:28:19.063477 # ok 2191 # SKIP Streaming SVE set SVE get FPSIMD for VL 544
3919 12:28:19.063537 # ok 2192 # SKIP Streaming SVE set FPSIMD get SVE for VL 544
3920 12:28:19.063600 # ok 2193 Set Streaming SVE VL 560
3921 12:28:19.063680 # ok 2194 # SKIP Streaming SVE set SVE get SVE for VL 560
3922 12:28:19.063756 # ok 2195 # SKIP Streaming SVE set SVE get FPSIMD for VL 560
3923 12:28:19.063825 # ok 2196 # SKIP Streaming SVE set FPSIMD get SVE for VL 560
3924 12:28:19.063942 # ok 2197 Set Streaming SVE VL 576
3925 12:28:19.064053 # ok 2198 # SKIP Streaming SVE set SVE get SVE for VL 576
3926 12:28:19.064162 # ok 2199 # SKIP Streaming SVE set SVE get FPSIMD for VL 576
3927 12:28:19.064257 # ok 2200 # SKIP Streaming SVE set FPSIMD get SVE for VL 576
3928 12:28:19.064346 # ok 2201 Set Streaming SVE VL 592
3929 12:28:19.064472 # ok 2202 # SKIP Streaming SVE set SVE get SVE for VL 592
3930 12:28:19.064551 # ok 2203 # SKIP Streaming SVE set SVE get FPSIMD for VL 592
3931 12:28:19.064625 # ok 2204 # SKIP Streaming SVE set FPSIMD get SVE for VL 592
3932 12:28:19.064698 # ok 2205 Set Streaming SVE VL 608
3933 12:28:19.064765 # ok 2206 # SKIP Streaming SVE set SVE get SVE for VL 608
3934 12:28:19.064825 # ok 2207 # SKIP Streaming SVE set SVE get FPSIMD for VL 608
3935 12:28:19.064889 # ok 2208 # SKIP Streaming SVE set FPSIMD get SVE for VL 608
3936 12:28:19.064965 # ok 2209 Set Streaming SVE VL 624
3937 12:28:19.065043 # ok 2210 # SKIP Streaming SVE set SVE get SVE for VL 624
3938 12:28:19.065338 # ok 2211 # SKIP Streaming SVE set SVE get FPSIMD for VL 624
3939 12:28:19.065440 # ok 2212 # SKIP Streaming SVE set FPSIMD get SVE for VL 624
3940 12:28:19.065515 # ok 2213 Set Streaming SVE VL 640
3941 12:28:19.065595 # ok 2214 # SKIP Streaming SVE set SVE get SVE for VL 640
3942 12:28:19.065688 # ok 2215 # SKIP Streaming SVE set SVE get FPSIMD for VL 640
3943 12:28:19.065775 # ok 2216 # SKIP Streaming SVE set FPSIMD get SVE for VL 640
3944 12:28:19.065859 # ok 2217 Set Streaming SVE VL 656
3945 12:28:19.065938 # ok 2218 # SKIP Streaming SVE set SVE get SVE for VL 656
3946 12:28:19.066018 # ok 2219 # SKIP Streaming SVE set SVE get FPSIMD for VL 656
3947 12:28:19.066100 # ok 2220 # SKIP Streaming SVE set FPSIMD get SVE for VL 656
3948 12:28:19.066181 # ok 2221 Set Streaming SVE VL 672
3949 12:28:19.066244 # ok 2222 # SKIP Streaming SVE set SVE get SVE for VL 672
3950 12:28:19.066318 # ok 2223 # SKIP Streaming SVE set SVE get FPSIMD for VL 672
3951 12:28:19.066397 # ok 2224 # SKIP Streaming SVE set FPSIMD get SVE for VL 672
3952 12:28:19.066498 # ok 2225 Set Streaming SVE VL 688
3953 12:28:19.066584 # ok 2226 # SKIP Streaming SVE set SVE get SVE for VL 688
3954 12:28:19.066659 # ok 2227 # SKIP Streaming SVE set SVE get FPSIMD for VL 688
3955 12:28:19.066726 # ok 2228 # SKIP Streaming SVE set FPSIMD get SVE for VL 688
3956 12:28:19.066804 # ok 2229 Set Streaming SVE VL 704
3957 12:28:19.066884 # ok 2230 # SKIP Streaming SVE set SVE get SVE for VL 704
3958 12:28:19.066960 # ok 2231 # SKIP Streaming SVE set SVE get FPSIMD for VL 704
3959 12:28:19.067033 # ok 2232 # SKIP Streaming SVE set FPSIMD get SVE for VL 704
3960 12:28:19.067111 # ok 2233 Set Streaming SVE VL 720
3961 12:28:19.067215 # ok 2234 # SKIP Streaming SVE set SVE get SVE for VL 720
3962 12:28:19.067311 # ok 2235 # SKIP Streaming SVE set SVE get FPSIMD for VL 720
3963 12:28:19.067383 # ok 2236 # SKIP Streaming SVE set FPSIMD get SVE for VL 720
3964 12:28:19.067445 # ok 2237 Set Streaming SVE VL 736
3965 12:28:19.067504 # ok 2238 # SKIP Streaming SVE set SVE get SVE for VL 736
3966 12:28:19.067562 # ok 2239 # SKIP Streaming SVE set SVE get FPSIMD for VL 736
3967 12:28:19.067692 # ok 2240 # SKIP Streaming SVE set FPSIMD get SVE for VL 736
3968 12:28:19.067812 # ok 2241 Set Streaming SVE VL 752
3969 12:28:19.067901 # ok 2242 # SKIP Streaming SVE set SVE get SVE for VL 752
3970 12:28:19.068195 # ok 2243 # SKIP Streaming SVE set SVE get FPSIMD for VL 752
3971 12:28:19.068320 # ok 2244 # SKIP Streaming SVE set FPSIMD get SVE for VL 752
3972 12:28:19.068401 # ok 2245 Set Streaming SVE VL 768
3973 12:28:19.068488 # ok 2246 # SKIP Streaming SVE set SVE get SVE for VL 768
3974 12:28:19.068780 # ok 2247 # SKIP Streaming SVE set SVE get FPSIMD for VL 768
3975 12:28:19.068873 # ok 2248 # SKIP Streaming SVE set FPSIMD get SVE for VL 768
3976 12:28:19.068949 # ok 2249 Set Streaming SVE VL 784
3977 12:28:19.069021 # ok 2250 # SKIP Streaming SVE set SVE get SVE for VL 784
3978 12:28:19.069291 # ok 2251 # SKIP Streaming SVE set SVE get FPSIMD for VL 784
3979 12:28:19.069380 # ok 2252 # SKIP Streaming SVE set FPSIMD get SVE for VL 784
3980 12:28:19.069457 # ok 2253 Set Streaming SVE VL 800
3981 12:28:19.069680 # ok 2254 # SKIP Streaming SVE set SVE get SVE for VL 800
3982 12:28:19.069756 # ok 2255 # SKIP Streaming SVE set SVE get FPSIMD for VL 800
3983 12:28:19.070775 # ok 2256 # SKIP Streaming SVE set FPSIMD get SVE for VL 800
3984 12:28:19.070901 # ok 2257 Set Streaming SVE VL 816
3985 12:28:19.071011 # ok 2258 # SKIP Streaming SVE set SVE get SVE for VL 816
3986 12:28:19.071096 # ok 2259 # SKIP Streaming SVE set SVE get FPSIMD for VL 816
3987 12:28:19.071184 # ok 2260 # SKIP Streaming SVE set FPSIMD get SVE for VL 816
3988 12:28:19.071280 # ok 2261 Set Streaming SVE VL 832
3989 12:28:19.071368 # ok 2262 # SKIP Streaming SVE set SVE get SVE for VL 832
3990 12:28:19.071467 # ok 2263 # SKIP Streaming SVE set SVE get FPSIMD for VL 832
3991 12:28:19.071533 # ok 2264 # SKIP Streaming SVE set FPSIMD get SVE for VL 832
3992 12:28:19.071593 # ok 2265 Set Streaming SVE VL 848
3993 12:28:19.071652 # ok 2266 # SKIP Streaming SVE set SVE get SVE for VL 848
3994 12:28:19.071722 # ok 2267 # SKIP Streaming SVE set SVE get FPSIMD for VL 848
3995 12:28:19.071995 # ok 2268 # SKIP Streaming SVE set FPSIMD get SVE for VL 848
3996 12:28:19.072093 # ok 2269 Set Streaming SVE VL 864
3997 12:28:19.072192 # ok 2270 # SKIP Streaming SVE set SVE get SVE for VL 864
3998 12:28:19.072295 # ok 2271 # SKIP Streaming SVE set SVE get FPSIMD for VL 864
3999 12:28:19.072655 # ok 2272 # SKIP Streaming SVE set FPSIMD get SVE for VL 864
4000 12:28:19.072762 # ok 2273 Set Streaming SVE VL 880
4001 12:28:19.073052 # ok 2274 # SKIP Streaming SVE set SVE get SVE for VL 880
4002 12:28:19.073148 # ok 2275 # SKIP Streaming SVE set SVE get FPSIMD for VL 880
4003 12:28:19.073234 # ok 2276 # SKIP Streaming SVE set FPSIMD get SVE for VL 880
4004 12:28:19.073337 # ok 2277 Set Streaming SVE VL 896
4005 12:28:19.073440 # ok 2278 # SKIP Streaming SVE set SVE get SVE for VL 896
4006 12:28:19.077457 # ok 2279 # SKIP Streaming SVE set SVE get FPSIMD for VL 896
4007 12:28:19.077713 # ok 2280 # SKIP Streaming SVE set FPSIMD get SVE for VL 896
4008 12:28:19.077827 # ok 2281 Set Streaming SVE VL 912
4009 12:28:19.077920 # ok 2282 # SKIP Streaming SVE set SVE get SVE for VL 912
4010 12:28:19.078011 # ok 2283 # SKIP Streaming SVE set SVE get FPSIMD for VL 912
4011 12:28:19.078108 # ok 2284 # SKIP Streaming SVE set FPSIMD get SVE for VL 912
4012 12:28:19.078189 # ok 2285 Set Streaming SVE VL 928
4013 12:28:19.078282 # ok 2286 # SKIP Streaming SVE set SVE get SVE for VL 928
4014 12:28:19.078564 # ok 2287 # SKIP Streaming SVE set SVE get FPSIMD for VL 928
4015 12:28:19.078688 # ok 2288 # SKIP Streaming SVE set FPSIMD get SVE for VL 928
4016 12:28:19.078787 # ok 2289 Set Streaming SVE VL 944
4017 12:28:19.078885 # ok 2290 # SKIP Streaming SVE set SVE get SVE for VL 944
4018 12:28:19.079004 # ok 2291 # SKIP Streaming SVE set SVE get FPSIMD for VL 944
4019 12:28:19.079325 # ok 2292 # SKIP Streaming SVE set FPSIMD get SVE for VL 944
4020 12:28:19.079423 # ok 2293 Set Streaming SVE VL 960
4021 12:28:19.080168 # ok 2294 # SKIP Streaming SVE set SVE get SVE for VL 960
4022 12:28:19.080470 # ok 2295 # SKIP Streaming SVE set SVE get FPSIMD for VL 960
4023 12:28:19.080561 # ok 2296 # SKIP Streaming SVE set FPSIMD get SVE for VL 960
4024 12:28:19.080637 # ok 2297 Set Streaming SVE VL 976
4025 12:28:19.080892 # ok 2298 # SKIP Streaming SVE set SVE get SVE for VL 976
4026 12:28:19.080960 # ok 2299 # SKIP Streaming SVE set SVE get FPSIMD for VL 976
4027 12:28:19.081030 # ok 2300 # SKIP Streaming SVE set FPSIMD get SVE for VL 976
4028 12:28:19.081115 # ok 2301 Set Streaming SVE VL 992
4029 12:28:19.081360 # ok 2302 # SKIP Streaming SVE set SVE get SVE for VL 992
4030 12:28:19.081433 # ok 2303 # SKIP Streaming SVE set SVE get FPSIMD for VL 992
4031 12:28:19.081678 # ok 2304 # SKIP Streaming SVE set FPSIMD get SVE for VL 992
4032 12:28:19.081754 # ok 2305 Set Streaming SVE VL 1008
4033 12:28:19.081998 # ok 2306 # SKIP Streaming SVE set SVE get SVE for VL 1008
4034 12:28:19.082061 # ok 2307 # SKIP Streaming SVE set SVE get FPSIMD for VL 1008
4035 12:28:19.082303 # ok 2308 # SKIP Streaming SVE set FPSIMD get SVE for VL 1008
4036 12:28:19.082366 # ok 2309 Set Streaming SVE VL 1024
4037 12:28:19.082434 # ok 2310 # SKIP Streaming SVE set SVE get SVE for VL 1024
4038 12:28:19.082676 # ok 2311 # SKIP Streaming SVE set SVE get FPSIMD for VL 1024
4039 12:28:19.082777 # ok 2312 # SKIP Streaming SVE set FPSIMD get SVE for VL 1024
4040 12:28:19.083084 # ok 2313 Set Streaming SVE VL 1040
4041 12:28:19.083180 # ok 2314 # SKIP Streaming SVE set SVE get SVE for VL 1040
4042 12:28:19.083259 # ok 2315 # SKIP Streaming SVE set SVE get FPSIMD for VL 1040
4043 12:28:19.083581 # ok 2316 # SKIP Streaming SVE set FPSIMD get SVE for VL 1040
4044 12:28:19.083879 # ok 2317 Set Streaming SVE VL 1056
4045 12:28:19.083984 # ok 2318 # SKIP Streaming SVE set SVE get SVE for VL 1056
4046 12:28:19.084116 # ok 2319 # SKIP Streaming SVE set SVE get FPSIMD for VL 1056
4047 12:28:19.084211 # ok 2320 # SKIP Streaming SVE set FPSIMD get SVE for VL 1056
4048 12:28:19.084314 # ok 2321 Set Streaming SVE VL 1072
4049 12:28:19.084413 # ok 2322 # SKIP Streaming SVE set SVE get SVE for VL 1072
4050 12:28:19.084508 # ok 2323 # SKIP Streaming SVE set SVE get FPSIMD for VL 1072
4051 12:28:19.084795 # ok 2324 # SKIP Streaming SVE set FPSIMD get SVE for VL 1072
4052 12:28:19.084896 # ok 2325 Set Streaming SVE VL 1088
4053 12:28:19.084996 # ok 2326 # SKIP Streaming SVE set SVE get SVE for VL 1088
4054 12:28:19.085098 # ok 2327 # SKIP Streaming SVE set SVE get FPSIMD for VL 1088
4055 12:28:19.085214 # ok 2328 # SKIP Streaming SVE set FPSIMD get SVE for VL 1088
4056 12:28:19.085320 # ok 2329 Set Streaming SVE VL 1104
4057 12:28:19.085600 # ok 2330 # SKIP Streaming SVE set SVE get SVE for VL 1104
4058 12:28:19.085713 # ok 2331 # SKIP Streaming SVE set SVE get FPSIMD for VL 1104
4059 12:28:19.086012 # ok 2332 # SKIP Streaming SVE set FPSIMD get SVE for VL 1104
4060 12:28:19.086117 # ok 2333 Set Streaming SVE VL 1120
4061 12:28:19.086223 # ok 2334 # SKIP Streaming SVE set SVE get SVE for VL 1120
4062 12:28:19.086522 # ok 2335 # SKIP Streaming SVE set SVE get FPSIMD for VL 1120
4063 12:28:19.086618 # ok 2336 # SKIP Streaming SVE set FPSIMD get SVE for VL 1120
4064 12:28:19.086722 # ok 2337 Set Streaming SVE VL 1136
4065 12:28:19.086821 # ok 2338 # SKIP Streaming SVE set SVE get SVE for VL 1136
4066 12:28:19.087108 # ok 2339 # SKIP Streaming SVE set SVE get FPSIMD for VL 1136
4067 12:28:19.087220 # ok 2340 # SKIP Streaming SVE set FPSIMD get SVE for VL 1136
4068 12:28:19.087313 # ok 2341 Set Streaming SVE VL 1152
4069 12:28:19.087637 # ok 2342 # SKIP Streaming SVE set SVE get SVE for VL 1152
4070 12:28:19.087986 # ok 2343 # SKIP Streaming SVE set SVE get FPSIMD for VL 1152
4071 12:28:19.088087 # ok 2344 # SKIP Streaming SVE set FPSIMD get SVE for VL 1152
4072 12:28:19.088190 # ok 2345 Set Streaming SVE VL 1168
4073 12:28:19.088295 # ok 2346 # SKIP Streaming SVE set SVE get SVE for VL 1168
4074 12:28:19.088606 # ok 2347 # SKIP Streaming SVE set SVE get FPSIMD for VL 1168
4075 12:28:19.088917 # ok 2348 # SKIP Streaming SVE set FPSIMD get SVE for VL 1168
4076 12:28:19.089042 # ok 2349 Set Streaming SVE VL 1184
4077 12:28:19.089144 # ok 2350 # SKIP Streaming SVE set SVE get SVE for VL 1184
4078 12:28:19.089247 # ok 2351 # SKIP Streaming SVE set SVE get FPSIMD for VL 1184
4079 12:28:19.089341 # ok 2352 # SKIP Streaming SVE set FPSIMD get SVE for VL 1184
4080 12:28:19.089437 # ok 2353 Set Streaming SVE VL 1200
4081 12:28:19.089545 # ok 2354 # SKIP Streaming SVE set SVE get SVE for VL 1200
4082 12:28:19.089675 # ok 2355 # SKIP Streaming SVE set SVE get FPSIMD for VL 1200
4083 12:28:19.089975 # ok 2356 # SKIP Streaming SVE set FPSIMD get SVE for VL 1200
4084 12:28:19.090065 # ok 2357 Set Streaming SVE VL 1216
4085 12:28:19.090159 # ok 2358 # SKIP Streaming SVE set SVE get SVE for VL 1216
4086 12:28:19.090416 # ok 2359 # SKIP Streaming SVE set SVE get FPSIMD for VL 1216
4087 12:28:19.090504 # ok 2360 # SKIP Streaming SVE set FPSIMD get SVE for VL 1216
4088 12:28:19.090581 # ok 2361 Set Streaming SVE VL 1232
4089 12:28:19.090848 # ok 2362 # SKIP Streaming SVE set SVE get SVE for VL 1232
4090 12:28:19.090942 # ok 2363 # SKIP Streaming SVE set SVE get FPSIMD for VL 1232
4091 12:28:19.091033 # ok 2364 # SKIP Streaming SVE set FPSIMD get SVE for VL 1232
4092 12:28:19.091138 # ok 2365 Set Streaming SVE VL 1248
4093 12:28:19.091234 # ok 2366 # SKIP Streaming SVE set SVE get SVE for VL 1248
4094 12:28:19.091700 # ok 2367 # SKIP Streaming SVE set SVE get FPSIMD for VL 1248
4095 12:28:19.091792 # ok 2368 # SKIP Streaming SVE set FPSIMD get SVE for VL 1248
4096 12:28:19.091885 # ok 2369 Set Streaming SVE VL 1264
4097 12:28:19.092142 # ok 2370 # SKIP Streaming SVE set SVE get SVE for VL 1264
4098 12:28:19.092421 # ok 2371 # SKIP Streaming SVE set SVE get FPSIMD for VL 1264
4099 12:28:19.092491 # ok 2372 # SKIP Streaming SVE set FPSIMD get SVE for VL 1264
4100 12:28:19.092736 # ok 2373 Set Streaming SVE VL 1280
4101 12:28:19.092803 # ok 2374 # SKIP Streaming SVE set SVE get SVE for VL 1280
4102 12:28:19.092887 # ok 2375 # SKIP Streaming SVE set SVE get FPSIMD for VL 1280
4103 12:28:19.092974 # ok 2376 # SKIP Streaming SVE set FPSIMD get SVE for VL 1280
4104 12:28:19.093284 # ok 2377 Set Streaming SVE VL 1296
4105 12:28:19.093374 # ok 2378 # SKIP Streaming SVE set SVE get SVE for VL 1296
4106 12:28:19.093461 # ok 2379 # SKIP Streaming SVE set SVE get FPSIMD for VL 1296
4107 12:28:19.093675 # ok 2380 # SKIP Streaming SVE set FPSIMD get SVE for VL 1296
4108 12:28:19.093750 # ok 2381 Set Streaming SVE VL 1312
4109 12:28:19.093987 # ok 2382 # SKIP Streaming SVE set SVE get SVE for VL 1312
4110 12:28:19.094226 # ok 2383 # SKIP Streaming SVE set SVE get FPSIMD for VL 1312
4111 12:28:19.094288 # ok 2384 # SKIP Streaming SVE set FPSIMD get SVE for VL 1312
4112 12:28:19.094356 # ok 2385 Set Streaming SVE VL 1328
4113 12:28:19.139778 # ok 2386 # SKIP Streaming SVE set SVE get SVE for VL 1328
4114 12:28:19.139992 # ok 2387 # SKIP Streaming SVE set SVE get FPSIMD for VL 1328
4115 12:28:19.140071 # ok 2388 # SKIP Streaming SVE set FPSIMD get SVE for VL 1328
4116 12:28:19.140143 # ok 2389 Set Streaming SVE VL 1344
4117 12:28:19.140232 # ok 2390 # SKIP Streaming SVE set SVE get SVE for VL 1344
4118 12:28:19.140302 # ok 2391 # SKIP Streaming SVE set SVE get FPSIMD for VL 1344
4119 12:28:19.140370 # ok 2392 # SKIP Streaming SVE set FPSIMD get SVE for VL 1344
4120 12:28:19.140431 # ok 2393 Set Streaming SVE VL 1360
4121 12:28:19.140489 # ok 2394 # SKIP Streaming SVE set SVE get SVE for VL 1360
4122 12:28:19.140548 # ok 2395 # SKIP Streaming SVE set SVE get FPSIMD for VL 1360
4123 12:28:19.140607 # ok 2396 # SKIP Streaming SVE set FPSIMD get SVE for VL 1360
4124 12:28:19.140666 # ok 2397 Set Streaming SVE VL 1376
4125 12:28:19.140725 # ok 2398 # SKIP Streaming SVE set SVE get SVE for VL 1376
4126 12:28:19.140783 # ok 2399 # SKIP Streaming SVE set SVE get FPSIMD for VL 1376
4127 12:28:19.140841 # ok 2400 # SKIP Streaming SVE set FPSIMD get SVE for VL 1376
4128 12:28:19.140900 # ok 2401 Set Streaming SVE VL 1392
4129 12:28:19.140958 # ok 2402 # SKIP Streaming SVE set SVE get SVE for VL 1392
4130 12:28:19.141017 # ok 2403 # SKIP Streaming SVE set SVE get FPSIMD for VL 1392
4131 12:28:19.141075 # ok 2404 # SKIP Streaming SVE set FPSIMD get SVE for VL 1392
4132 12:28:19.141134 # ok 2405 Set Streaming SVE VL 1408
4133 12:28:19.141193 # ok 2406 # SKIP Streaming SVE set SVE get SVE for VL 1408
4134 12:28:19.141251 # ok 2407 # SKIP Streaming SVE set SVE get FPSIMD for VL 1408
4135 12:28:19.141309 # ok 2408 # SKIP Streaming SVE set FPSIMD get SVE for VL 1408
4136 12:28:19.141367 # ok 2409 Set Streaming SVE VL 1424
4137 12:28:19.141426 # ok 2410 # SKIP Streaming SVE set SVE get SVE for VL 1424
4138 12:28:19.141484 # ok 2411 # SKIP Streaming SVE set SVE get FPSIMD for VL 1424
4139 12:28:19.141543 # ok 2412 # SKIP Streaming SVE set FPSIMD get SVE for VL 1424
4140 12:28:19.141601 # ok 2413 Set Streaming SVE VL 1440
4141 12:28:19.141667 # ok 2414 # SKIP Streaming SVE set SVE get SVE for VL 1440
4142 12:28:19.141727 # ok 2415 # SKIP Streaming SVE set SVE get FPSIMD for VL 1440
4143 12:28:19.141785 # ok 2416 # SKIP Streaming SVE set FPSIMD get SVE for VL 1440
4144 12:28:19.141843 # ok 2417 Set Streaming SVE VL 1456
4145 12:28:19.141902 # ok 2418 # SKIP Streaming SVE set SVE get SVE for VL 1456
4146 12:28:19.142173 # ok 2419 # SKIP Streaming SVE set SVE get FPSIMD for VL 1456
4147 12:28:19.142260 # ok 2420 # SKIP Streaming SVE set FPSIMD get SVE for VL 1456
4148 12:28:19.142332 # ok 2421 Set Streaming SVE VL 1472
4149 12:28:19.142408 # ok 2422 # SKIP Streaming SVE set SVE get SVE for VL 1472
4150 12:28:19.142484 # ok 2423 # SKIP Streaming SVE set SVE get FPSIMD for VL 1472
4151 12:28:19.142576 # ok 2424 # SKIP Streaming SVE set FPSIMD get SVE for VL 1472
4152 12:28:19.142659 # ok 2425 Set Streaming SVE VL 1488
4153 12:28:19.142737 # ok 2426 # SKIP Streaming SVE set SVE get SVE for VL 1488
4154 12:28:19.142811 # ok 2427 # SKIP Streaming SVE set SVE get FPSIMD for VL 1488
4155 12:28:19.142888 # ok 2428 # SKIP Streaming SVE set FPSIMD get SVE for VL 1488
4156 12:28:19.142961 # ok 2429 Set Streaming SVE VL 1504
4157 12:28:19.143031 # ok 2430 # SKIP Streaming SVE set SVE get SVE for VL 1504
4158 12:28:19.143108 # ok 2431 # SKIP Streaming SVE set SVE get FPSIMD for VL 1504
4159 12:28:19.143177 # ok 2432 # SKIP Streaming SVE set FPSIMD get SVE for VL 1504
4160 12:28:19.143238 # ok 2433 Set Streaming SVE VL 1520
4161 12:28:19.143298 # ok 2434 # SKIP Streaming SVE set SVE get SVE for VL 1520
4162 12:28:19.143362 # ok 2435 # SKIP Streaming SVE set SVE get FPSIMD for VL 1520
4163 12:28:19.143422 # ok 2436 # SKIP Streaming SVE set FPSIMD get SVE for VL 1520
4164 12:28:19.143483 # ok 2437 Set Streaming SVE VL 1536
4165 12:28:19.143543 # ok 2438 # SKIP Streaming SVE set SVE get SVE for VL 1536
4166 12:28:19.143609 # ok 2439 # SKIP Streaming SVE set SVE get FPSIMD for VL 1536
4167 12:28:19.143675 # ok 2440 # SKIP Streaming SVE set FPSIMD get SVE for VL 1536
4168 12:28:19.143739 # ok 2441 Set Streaming SVE VL 1552
4169 12:28:19.143811 # ok 2442 # SKIP Streaming SVE set SVE get SVE for VL 1552
4170 12:28:19.143889 # ok 2443 # SKIP Streaming SVE set SVE get FPSIMD for VL 1552
4171 12:28:19.143970 # ok 2444 # SKIP Streaming SVE set FPSIMD get SVE for VL 1552
4172 12:28:19.144044 # ok 2445 Set Streaming SVE VL 1568
4173 12:28:19.144111 # ok 2446 # SKIP Streaming SVE set SVE get SVE for VL 1568
4174 12:28:19.144184 # ok 2447 # SKIP Streaming SVE set SVE get FPSIMD for VL 1568
4175 12:28:19.144274 # ok 2448 # SKIP Streaming SVE set FPSIMD get SVE for VL 1568
4176 12:28:19.144349 # ok 2449 Set Streaming SVE VL 1584
4177 12:28:19.144410 # ok 2450 # SKIP Streaming SVE set SVE get SVE for VL 1584
4178 12:28:19.144468 # ok 2451 # SKIP Streaming SVE set SVE get FPSIMD for VL 1584
4179 12:28:19.144536 # ok 2452 # SKIP Streaming SVE set FPSIMD get SVE for VL 1584
4180 12:28:19.144595 # ok 2453 Set Streaming SVE VL 1600
4181 12:28:19.144845 # ok 2454 # SKIP Streaming SVE set SVE get SVE for VL 1600
4182 12:28:19.144913 # ok 2455 # SKIP Streaming SVE set SVE get FPSIMD for VL 1600
4183 12:28:19.144994 # ok 2456 # SKIP Streaming SVE set FPSIMD get SVE for VL 1600
4184 12:28:19.145069 # ok 2457 Set Streaming SVE VL 1616
4185 12:28:19.145148 # ok 2458 # SKIP Streaming SVE set SVE get SVE for VL 1616
4186 12:28:19.145245 # ok 2459 # SKIP Streaming SVE set SVE get FPSIMD for VL 1616
4187 12:28:19.145318 # ok 2460 # SKIP Streaming SVE set FPSIMD get SVE for VL 1616
4188 12:28:19.145382 # ok 2461 Set Streaming SVE VL 1632
4189 12:28:19.145444 # ok 2462 # SKIP Streaming SVE set SVE get SVE for VL 1632
4190 12:28:19.145503 # ok 2463 # SKIP Streaming SVE set SVE get FPSIMD for VL 1632
4191 12:28:19.145581 # ok 2464 # SKIP Streaming SVE set FPSIMD get SVE for VL 1632
4192 12:28:19.145663 # ok 2465 Set Streaming SVE VL 1648
4193 12:28:19.145738 # ok 2466 # SKIP Streaming SVE set SVE get SVE for VL 1648
4194 12:28:19.145810 # ok 2467 # SKIP Streaming SVE set SVE get FPSIMD for VL 1648
4195 12:28:19.145874 # ok 2468 # SKIP Streaming SVE set FPSIMD get SVE for VL 1648
4196 12:28:19.145948 # ok 2469 Set Streaming SVE VL 1664
4197 12:28:19.146026 # ok 2470 # SKIP Streaming SVE set SVE get SVE for VL 1664
4198 12:28:19.146108 # ok 2471 # SKIP Streaming SVE set SVE get FPSIMD for VL 1664
4199 12:28:19.146206 # ok 2472 # SKIP Streaming SVE set FPSIMD get SVE for VL 1664
4200 12:28:19.146291 # ok 2473 Set Streaming SVE VL 1680
4201 12:28:19.146371 # ok 2474 # SKIP Streaming SVE set SVE get SVE for VL 1680
4202 12:28:19.146451 # ok 2475 # SKIP Streaming SVE set SVE get FPSIMD for VL 1680
4203 12:28:19.146527 # ok 2476 # SKIP Streaming SVE set FPSIMD get SVE for VL 1680
4204 12:28:19.146600 # ok 2477 Set Streaming SVE VL 1696
4205 12:28:19.146669 # ok 2478 # SKIP Streaming SVE set SVE get SVE for VL 1696
4206 12:28:19.146736 # ok 2479 # SKIP Streaming SVE set SVE get FPSIMD for VL 1696
4207 12:28:19.146814 # ok 2480 # SKIP Streaming SVE set FPSIMD get SVE for VL 1696
4208 12:28:19.146889 # ok 2481 Set Streaming SVE VL 1712
4209 12:28:19.146973 # ok 2482 # SKIP Streaming SVE set SVE get SVE for VL 1712
4210 12:28:19.147043 # ok 2483 # SKIP Streaming SVE set SVE get FPSIMD for VL 1712
4211 12:28:19.147125 # ok 2484 # SKIP Streaming SVE set FPSIMD get SVE for VL 1712
4212 12:28:19.147206 # ok 2485 Set Streaming SVE VL 1728
4213 12:28:19.147285 # ok 2486 # SKIP Streaming SVE set SVE get SVE for VL 1728
4214 12:28:19.147361 # ok 2487 # SKIP Streaming SVE set SVE get FPSIMD for VL 1728
4215 12:28:19.147430 # ok 2488 # SKIP Streaming SVE set FPSIMD get SVE for VL 1728
4216 12:28:19.147713 # ok 2489 Set Streaming SVE VL 1744
4217 12:28:19.147828 # ok 2490 # SKIP Streaming SVE set SVE get SVE for VL 1744
4218 12:28:19.147930 # ok 2491 # SKIP Streaming SVE set SVE get FPSIMD for VL 1744
4219 12:28:19.148021 # ok 2492 # SKIP Streaming SVE set FPSIMD get SVE for VL 1744
4220 12:28:19.148115 # ok 2493 Set Streaming SVE VL 1760
4221 12:28:19.148209 # ok 2494 # SKIP Streaming SVE set SVE get SVE for VL 1760
4222 12:28:19.148307 # ok 2495 # SKIP Streaming SVE set SVE get FPSIMD for VL 1760
4223 12:28:19.148411 # ok 2496 # SKIP Streaming SVE set FPSIMD get SVE for VL 1760
4224 12:28:19.148496 # ok 2497 Set Streaming SVE VL 1776
4225 12:28:19.148573 # ok 2498 # SKIP Streaming SVE set SVE get SVE for VL 1776
4226 12:28:19.148638 # ok 2499 # SKIP Streaming SVE set SVE get FPSIMD for VL 1776
4227 12:28:19.148714 # ok 2500 # SKIP Streaming SVE set FPSIMD get SVE for VL 1776
4228 12:28:19.148790 # ok 2501 Set Streaming SVE VL 1792
4229 12:28:19.148867 # ok 2502 # SKIP Streaming SVE set SVE get SVE for VL 1792
4230 12:28:19.148949 # ok 2503 # SKIP Streaming SVE set SVE get FPSIMD for VL 1792
4231 12:28:19.149023 # ok 2504 # SKIP Streaming SVE set FPSIMD get SVE for VL 1792
4232 12:28:19.149087 # ok 2505 Set Streaming SVE VL 1808
4233 12:28:19.149165 # ok 2506 # SKIP Streaming SVE set SVE get SVE for VL 1808
4234 12:28:19.149240 # ok 2507 # SKIP Streaming SVE set SVE get FPSIMD for VL 1808
4235 12:28:19.149308 # ok 2508 # SKIP Streaming SVE set FPSIMD get SVE for VL 1808
4236 12:28:19.149373 # ok 2509 Set Streaming SVE VL 1824
4237 12:28:19.149438 # ok 2510 # SKIP Streaming SVE set SVE get SVE for VL 1824
4238 12:28:19.149502 # ok 2511 # SKIP Streaming SVE set SVE get FPSIMD for VL 1824
4239 12:28:19.149568 # ok 2512 # SKIP Streaming SVE set FPSIMD get SVE for VL 1824
4240 12:28:19.149627 # ok 2513 Set Streaming SVE VL 1840
4241 12:28:19.149696 # ok 2514 # SKIP Streaming SVE set SVE get SVE for VL 1840
4242 12:28:19.149755 # ok 2515 # SKIP Streaming SVE set SVE get FPSIMD for VL 1840
4243 12:28:19.149813 # ok 2516 # SKIP Streaming SVE set FPSIMD get SVE for VL 1840
4244 12:28:19.149871 # ok 2517 Set Streaming SVE VL 1856
4245 12:28:19.149931 # ok 2518 # SKIP Streaming SVE set SVE get SVE for VL 1856
4246 12:28:19.149990 # ok 2519 # SKIP Streaming SVE set SVE get FPSIMD for VL 1856
4247 12:28:19.150048 # ok 2520 # SKIP Streaming SVE set FPSIMD get SVE for VL 1856
4248 12:28:19.150106 # ok 2521 Set Streaming SVE VL 1872
4249 12:28:19.150164 # ok 2522 # SKIP Streaming SVE set SVE get SVE for VL 1872
4250 12:28:19.150222 # ok 2523 # SKIP Streaming SVE set SVE get FPSIMD for VL 1872
4251 12:28:19.150470 # ok 2524 # SKIP Streaming SVE set FPSIMD get SVE for VL 1872
4252 12:28:19.150535 # ok 2525 Set Streaming SVE VL 1888
4253 12:28:19.150594 # ok 2526 # SKIP Streaming SVE set SVE get SVE for VL 1888
4254 12:28:19.150652 # ok 2527 # SKIP Streaming SVE set SVE get FPSIMD for VL 1888
4255 12:28:19.150710 # ok 2528 # SKIP Streaming SVE set FPSIMD get SVE for VL 1888
4256 12:28:19.150768 # ok 2529 Set Streaming SVE VL 1904
4257 12:28:19.150826 # ok 2530 # SKIP Streaming SVE set SVE get SVE for VL 1904
4258 12:28:19.150884 # ok 2531 # SKIP Streaming SVE set SVE get FPSIMD for VL 1904
4259 12:28:19.150941 # ok 2532 # SKIP Streaming SVE set FPSIMD get SVE for VL 1904
4260 12:28:19.151004 # ok 2533 Set Streaming SVE VL 1920
4261 12:28:19.151094 # ok 2534 # SKIP Streaming SVE set SVE get SVE for VL 1920
4262 12:28:19.151162 # ok 2535 # SKIP Streaming SVE set SVE get FPSIMD for VL 1920
4263 12:28:19.151221 # ok 2536 # SKIP Streaming SVE set FPSIMD get SVE for VL 1920
4264 12:28:19.151278 # ok 2537 Set Streaming SVE VL 1936
4265 12:28:19.151336 # ok 2538 # SKIP Streaming SVE set SVE get SVE for VL 1936
4266 12:28:19.151394 # ok 2539 # SKIP Streaming SVE set SVE get FPSIMD for VL 1936
4267 12:28:19.151452 # ok 2540 # SKIP Streaming SVE set FPSIMD get SVE for VL 1936
4268 12:28:19.151509 # ok 2541 Set Streaming SVE VL 1952
4269 12:28:19.151567 # ok 2542 # SKIP Streaming SVE set SVE get SVE for VL 1952
4270 12:28:19.151624 # ok 2543 # SKIP Streaming SVE set SVE get FPSIMD for VL 1952
4271 12:28:19.151681 # ok 2544 # SKIP Streaming SVE set FPSIMD get SVE for VL 1952
4272 12:28:19.151739 # ok 2545 Set Streaming SVE VL 1968
4273 12:28:19.151795 # ok 2546 # SKIP Streaming SVE set SVE get SVE for VL 1968
4274 12:28:19.151852 # ok 2547 # SKIP Streaming SVE set SVE get FPSIMD for VL 1968
4275 12:28:19.151912 # ok 2548 # SKIP Streaming SVE set FPSIMD get SVE for VL 1968
4276 12:28:19.151973 # ok 2549 Set Streaming SVE VL 1984
4277 12:28:19.152047 # ok 2550 # SKIP Streaming SVE set SVE get SVE for VL 1984
4278 12:28:19.152128 # ok 2551 # SKIP Streaming SVE set SVE get FPSIMD for VL 1984
4279 12:28:19.152228 # ok 2552 # SKIP Streaming SVE set FPSIMD get SVE for VL 1984
4280 12:28:19.152298 # ok 2553 Set Streaming SVE VL 2000
4281 12:28:19.152361 # ok 2554 # SKIP Streaming SVE set SVE get SVE for VL 2000
4282 12:28:19.152432 # ok 2555 # SKIP Streaming SVE set SVE get FPSIMD for VL 2000
4283 12:28:19.152506 # ok 2556 # SKIP Streaming SVE set FPSIMD get SVE for VL 2000
4284 12:28:19.152605 # ok 2557 Set Streaming SVE VL 2016
4285 12:28:19.152696 # ok 2558 # SKIP Streaming SVE set SVE get SVE for VL 2016
4286 12:28:19.152776 # ok 2559 # SKIP Streaming SVE set SVE get FPSIMD for VL 2016
4287 12:28:19.153071 # ok 2560 # SKIP Streaming SVE set FPSIMD get SVE for VL 2016
4288 12:28:19.153163 # ok 2561 Set Streaming SVE VL 2032
4289 12:28:19.153242 # ok 2562 # SKIP Streaming SVE set SVE get SVE for VL 2032
4290 12:28:19.153321 # ok 2563 # SKIP Streaming SVE set SVE get FPSIMD for VL 2032
4291 12:28:19.153400 # ok 2564 # SKIP Streaming SVE set FPSIMD get SVE for VL 2032
4292 12:28:19.153479 # ok 2565 Set Streaming SVE VL 2048
4293 12:28:19.153558 # ok 2566 # SKIP Streaming SVE set SVE get SVE for VL 2048
4294 12:28:19.153659 # ok 2567 # SKIP Streaming SVE set SVE get FPSIMD for VL 2048
4295 12:28:19.153748 # ok 2568 # SKIP Streaming SVE set FPSIMD get SVE for VL 2048
4296 12:28:19.153838 # ok 2569 Set Streaming SVE VL 2064
4297 12:28:19.153928 # ok 2570 # SKIP Streaming SVE set SVE get SVE for VL 2064
4298 12:28:19.154031 # ok 2571 # SKIP Streaming SVE set SVE get FPSIMD for VL 2064
4299 12:28:19.154122 # ok 2572 # SKIP Streaming SVE set FPSIMD get SVE for VL 2064
4300 12:28:19.154218 # ok 2573 Set Streaming SVE VL 2080
4301 12:28:19.154304 # ok 2574 # SKIP Streaming SVE set SVE get SVE for VL 2080
4302 12:28:19.154386 # ok 2575 # SKIP Streaming SVE set SVE get FPSIMD for VL 2080
4303 12:28:19.154467 # ok 2576 # SKIP Streaming SVE set FPSIMD get SVE for VL 2080
4304 12:28:19.154548 # ok 2577 Set Streaming SVE VL 2096
4305 12:28:19.154629 # ok 2578 # SKIP Streaming SVE set SVE get SVE for VL 2096
4306 12:28:19.154712 # ok 2579 # SKIP Streaming SVE set SVE get FPSIMD for VL 2096
4307 12:28:19.154794 # ok 2580 # SKIP Streaming SVE set FPSIMD get SVE for VL 2096
4308 12:28:19.154873 # ok 2581 Set Streaming SVE VL 2112
4309 12:28:19.154956 # ok 2582 # SKIP Streaming SVE set SVE get SVE for VL 2112
4310 12:28:19.155035 # ok 2583 # SKIP Streaming SVE set SVE get FPSIMD for VL 2112
4311 12:28:19.155120 # ok 2584 # SKIP Streaming SVE set FPSIMD get SVE for VL 2112
4312 12:28:19.155204 # ok 2585 Set Streaming SVE VL 2128
4313 12:28:19.155284 # ok 2586 # SKIP Streaming SVE set SVE get SVE for VL 2128
4314 12:28:19.155362 # ok 2587 # SKIP Streaming SVE set SVE get FPSIMD for VL 2128
4315 12:28:19.155447 # ok 2588 # SKIP Streaming SVE set FPSIMD get SVE for VL 2128
4316 12:28:19.155529 # ok 2589 Set Streaming SVE VL 2144
4317 12:28:19.155610 # ok 2590 # SKIP Streaming SVE set SVE get SVE for VL 2144
4318 12:28:19.155692 # ok 2591 # SKIP Streaming SVE set SVE get FPSIMD for VL 2144
4319 12:28:19.155777 # ok 2592 # SKIP Streaming SVE set FPSIMD get SVE for VL 2144
4320 12:28:19.155867 # ok 2593 Set Streaming SVE VL 2160
4321 12:28:19.155971 # ok 2594 # SKIP Streaming SVE set SVE get SVE for VL 2160
4322 12:28:19.156304 # ok 2595 # SKIP Streaming SVE set SVE get FPSIMD for VL 2160
4323 12:28:19.156412 # ok 2596 # SKIP Streaming SVE set FPSIMD get SVE for VL 2160
4324 12:28:19.156516 # ok 2597 Set Streaming SVE VL 2176
4325 12:28:19.156609 # ok 2598 # SKIP Streaming SVE set SVE get SVE for VL 2176
4326 12:28:19.156708 # ok 2599 # SKIP Streaming SVE set SVE get FPSIMD for VL 2176
4327 12:28:19.156821 # ok 2600 # SKIP Streaming SVE set FPSIMD get SVE for VL 2176
4328 12:28:19.156929 # ok 2601 Set Streaming SVE VL 2192
4329 12:28:19.157037 # ok 2602 # SKIP Streaming SVE set SVE get SVE for VL 2192
4330 12:28:19.157134 # ok 2603 # SKIP Streaming SVE set SVE get FPSIMD for VL 2192
4331 12:28:19.157235 # ok 2604 # SKIP Streaming SVE set FPSIMD get SVE for VL 2192
4332 12:28:19.157346 # ok 2605 Set Streaming SVE VL 2208
4333 12:28:19.157457 # ok 2606 # SKIP Streaming SVE set SVE get SVE for VL 2208
4334 12:28:19.157559 # ok 2607 # SKIP Streaming SVE set SVE get FPSIMD for VL 2208
4335 12:28:19.157661 # ok 2608 # SKIP Streaming SVE set FPSIMD get SVE for VL 2208
4336 12:28:19.157756 # ok 2609 Set Streaming SVE VL 2224
4337 12:28:19.157846 # ok 2610 # SKIP Streaming SVE set SVE get SVE for VL 2224
4338 12:28:19.157940 # ok 2611 # SKIP Streaming SVE set SVE get FPSIMD for VL 2224
4339 12:28:19.158045 # ok 2612 # SKIP Streaming SVE set FPSIMD get SVE for VL 2224
4340 12:28:19.158134 # ok 2613 Set Streaming SVE VL 2240
4341 12:28:19.158239 # ok 2614 # SKIP Streaming SVE set SVE get SVE for VL 2240
4342 12:28:19.158348 # ok 2615 # SKIP Streaming SVE set SVE get FPSIMD for VL 2240
4343 12:28:19.158454 # ok 2616 # SKIP Streaming SVE set FPSIMD get SVE for VL 2240
4344 12:28:19.158545 # ok 2617 Set Streaming SVE VL 2256
4345 12:28:19.158633 # ok 2618 # SKIP Streaming SVE set SVE get SVE for VL 2256
4346 12:28:19.158716 # ok 2619 # SKIP Streaming SVE set SVE get FPSIMD for VL 2256
4347 12:28:19.158814 # ok 2620 # SKIP Streaming SVE set FPSIMD get SVE for VL 2256
4348 12:28:19.158903 # ok 2621 Set Streaming SVE VL 2272
4349 12:28:19.158989 # ok 2622 # SKIP Streaming SVE set SVE get SVE for VL 2272
4350 12:28:19.159069 # ok 2623 # SKIP Streaming SVE set SVE get FPSIMD for VL 2272
4351 12:28:19.159153 # ok 2624 # SKIP Streaming SVE set FPSIMD get SVE for VL 2272
4352 12:28:19.159235 # ok 2625 Set Streaming SVE VL 2288
4353 12:28:19.159320 # ok 2626 # SKIP Streaming SVE set SVE get SVE for VL 2288
4354 12:28:19.159403 # ok 2627 # SKIP Streaming SVE set SVE get FPSIMD for VL 2288
4355 12:28:19.159484 # ok 2628 # SKIP Streaming SVE set FPSIMD get SVE for VL 2288
4356 12:28:19.159563 # ok 2629 Set Streaming SVE VL 2304
4357 12:28:19.160112 # ok 2630 # SKIP Streaming SVE set SVE get SVE for VL 2304
4358 12:28:19.160239 # ok 2631 # SKIP Streaming SVE set SVE get FPSIMD for VL 2304
4359 12:28:19.160339 # ok 2632 # SKIP Streaming SVE set FPSIMD get SVE for VL 2304
4360 12:28:19.160440 # ok 2633 Set Streaming SVE VL 2320
4361 12:28:19.160530 # ok 2634 # SKIP Streaming SVE set SVE get SVE for VL 2320
4362 12:28:19.160636 # ok 2635 # SKIP Streaming SVE set SVE get FPSIMD for VL 2320
4363 12:28:19.160721 # ok 2636 # SKIP Streaming SVE set FPSIMD get SVE for VL 2320
4364 12:28:19.160809 # ok 2637 Set Streaming SVE VL 2336
4365 12:28:19.160890 # ok 2638 # SKIP Streaming SVE set SVE get SVE for VL 2336
4366 12:28:19.160977 # ok 2639 # SKIP Streaming SVE set SVE get FPSIMD for VL 2336
4367 12:28:19.161057 # ok 2640 # SKIP Streaming SVE set FPSIMD get SVE for VL 2336
4368 12:28:19.161138 # ok 2641 Set Streaming SVE VL 2352
4369 12:28:19.161219 # ok 2642 # SKIP Streaming SVE set SVE get SVE for VL 2352
4370 12:28:19.161316 # ok 2643 # SKIP Streaming SVE set SVE get FPSIMD for VL 2352
4371 12:28:19.161428 # ok 2644 # SKIP Streaming SVE set FPSIMD get SVE for VL 2352
4372 12:28:19.161550 # ok 2645 Set Streaming SVE VL 2368
4373 12:28:19.161678 # ok 2646 # SKIP Streaming SVE set SVE get SVE for VL 2368
4374 12:28:19.161770 # ok 2647 # SKIP Streaming SVE set SVE get FPSIMD for VL 2368
4375 12:28:19.161855 # ok 2648 # SKIP Streaming SVE set FPSIMD get SVE for VL 2368
4376 12:28:19.161944 # ok 2649 Set Streaming SVE VL 2384
4377 12:28:19.162029 # ok 2650 # SKIP Streaming SVE set SVE get SVE for VL 2384
4378 12:28:19.162117 # ok 2651 # SKIP Streaming SVE set SVE get FPSIMD for VL 2384
4379 12:28:19.162206 # ok 2652 # SKIP Streaming SVE set FPSIMD get SVE for VL 2384
4380 12:28:19.162293 # ok 2653 Set Streaming SVE VL 2400
4381 12:28:19.162375 # ok 2654 # SKIP Streaming SVE set SVE get SVE for VL 2400
4382 12:28:19.162456 # ok 2655 # SKIP Streaming SVE set SVE get FPSIMD for VL 2400
4383 12:28:19.162535 # ok 2656 # SKIP Streaming SVE set FPSIMD get SVE for VL 2400
4384 12:28:19.162614 # ok 2657 Set Streaming SVE VL 2416
4385 12:28:19.162696 # ok 2658 # SKIP Streaming SVE set SVE get SVE for VL 2416
4386 12:28:19.162780 # ok 2659 # SKIP Streaming SVE set SVE get FPSIMD for VL 2416
4387 12:28:19.162859 # ok 2660 # SKIP Streaming SVE set FPSIMD get SVE for VL 2416
4388 12:28:19.162961 # ok 2661 Set Streaming SVE VL 2432
4389 12:28:19.163078 # ok 2662 # SKIP Streaming SVE set SVE get SVE for VL 2432
4390 12:28:19.163167 # ok 2663 # SKIP Streaming SVE set SVE get FPSIMD for VL 2432
4391 12:28:19.163252 # ok 2664 # SKIP Streaming SVE set FPSIMD get SVE for VL 2432
4392 12:28:19.163332 # ok 2665 Set Streaming SVE VL 2448
4393 12:28:19.163724 # ok 2666 # SKIP Streaming SVE set SVE get SVE for VL 2448
4394 12:28:19.163830 # ok 2667 # SKIP Streaming SVE set SVE get FPSIMD for VL 2448
4395 12:28:19.163920 # ok 2668 # SKIP Streaming SVE set FPSIMD get SVE for VL 2448
4396 12:28:19.164002 # ok 2669 Set Streaming SVE VL 2464
4397 12:28:19.164081 # ok 2670 # SKIP Streaming SVE set SVE get SVE for VL 2464
4398 12:28:19.164179 # ok 2671 # SKIP Streaming SVE set SVE get FPSIMD for VL 2464
4399 12:28:19.164283 # ok 2672 # SKIP Streaming SVE set FPSIMD get SVE for VL 2464
4400 12:28:19.164381 # ok 2673 Set Streaming SVE VL 2480
4401 12:28:19.164488 # ok 2674 # SKIP Streaming SVE set SVE get SVE for VL 2480
4402 12:28:19.164580 # ok 2675 # SKIP Streaming SVE set SVE get FPSIMD for VL 2480
4403 12:28:19.164670 # ok 2676 # SKIP Streaming SVE set FPSIMD get SVE for VL 2480
4404 12:28:19.164754 # ok 2677 Set Streaming SVE VL 2496
4405 12:28:19.164837 # ok 2678 # SKIP Streaming SVE set SVE get SVE for VL 2496
4406 12:28:19.164918 # ok 2679 # SKIP Streaming SVE set SVE get FPSIMD for VL 2496
4407 12:28:19.165001 # ok 2680 # SKIP Streaming SVE set FPSIMD get SVE for VL 2496
4408 12:28:19.165083 # ok 2681 Set Streaming SVE VL 2512
4409 12:28:19.165171 # ok 2682 # SKIP Streaming SVE set SVE get SVE for VL 2512
4410 12:28:19.165262 # ok 2683 # SKIP Streaming SVE set SVE get FPSIMD for VL 2512
4411 12:28:19.165362 # ok 2684 # SKIP Streaming SVE set FPSIMD get SVE for VL 2512
4412 12:28:19.165477 # ok 2685 Set Streaming SVE VL 2528
4413 12:28:19.165589 # ok 2686 # SKIP Streaming SVE set SVE get SVE for VL 2528
4414 12:28:19.165700 # ok 2687 # SKIP Streaming SVE set SVE get FPSIMD for VL 2528
4415 12:28:19.165787 # ok 2688 # SKIP Streaming SVE set FPSIMD get SVE for VL 2528
4416 12:28:19.165874 # ok 2689 Set Streaming SVE VL 2544
4417 12:28:19.165963 # ok 2690 # SKIP Streaming SVE set SVE get SVE for VL 2544
4418 12:28:19.166053 # ok 2691 # SKIP Streaming SVE set SVE get FPSIMD for VL 2544
4419 12:28:19.166143 # ok 2692 # SKIP Streaming SVE set FPSIMD get SVE for VL 2544
4420 12:28:19.166240 # ok 2693 Set Streaming SVE VL 2560
4421 12:28:19.166349 # ok 2694 # SKIP Streaming SVE set SVE get SVE for VL 2560
4422 12:28:19.166464 # ok 2695 # SKIP Streaming SVE set SVE get FPSIMD for VL 2560
4423 12:28:19.166573 # ok 2696 # SKIP Streaming SVE set FPSIMD get SVE for VL 2560
4424 12:28:19.166680 # ok 2697 Set Streaming SVE VL 2576
4425 12:28:19.166790 # ok 2698 # SKIP Streaming SVE set SVE get SVE for VL 2576
4426 12:28:19.166900 # ok 2699 # SKIP Streaming SVE set SVE get FPSIMD for VL 2576
4427 12:28:19.167006 # ok 2700 # SKIP Streaming SVE set FPSIMD get SVE for VL 2576
4428 12:28:19.167328 # ok 2701 Set Streaming SVE VL 2592
4429 12:28:19.167424 # ok 2702 # SKIP Streaming SVE set SVE get SVE for VL 2592
4430 12:28:19.167491 # ok 2703 # SKIP Streaming SVE set SVE get FPSIMD for VL 2592
4431 12:28:19.167636 # ok 2704 # SKIP Streaming SVE set FPSIMD get SVE for VL 2592
4432 12:28:19.167810 # ok 2705 Set Streaming SVE VL 2608
4433 12:28:19.167887 # ok 2706 # SKIP Streaming SVE set SVE get SVE for VL 2608
4434 12:28:19.167956 # ok 2707 # SKIP Streaming SVE set SVE get FPSIMD for VL 2608
4435 12:28:19.168019 # ok 2708 # SKIP Streaming SVE set FPSIMD get SVE for VL 2608
4436 12:28:19.168085 # ok 2709 Set Streaming SVE VL 2624
4437 12:28:19.168147 # ok 2710 # SKIP Streaming SVE set SVE get SVE for VL 2624
4438 12:28:19.168210 # ok 2711 # SKIP Streaming SVE set SVE get FPSIMD for VL 2624
4439 12:28:19.168277 # ok 2712 # SKIP Streaming SVE set FPSIMD get SVE for VL 2624
4440 12:28:19.168346 # ok 2713 Set Streaming SVE VL 2640
4441 12:28:19.168405 # ok 2714 # SKIP Streaming SVE set SVE get SVE for VL 2640
4442 12:28:19.168471 # ok 2715 # SKIP Streaming SVE set SVE get FPSIMD for VL 2640
4443 12:28:19.168530 # ok 2716 # SKIP Streaming SVE set FPSIMD get SVE for VL 2640
4444 12:28:19.168593 # ok 2717 Set Streaming SVE VL 2656
4445 12:28:19.168654 # ok 2718 # SKIP Streaming SVE set SVE get SVE for VL 2656
4446 12:28:19.168719 # ok 2719 # SKIP Streaming SVE set SVE get FPSIMD for VL 2656
4447 12:28:19.168780 # ok 2720 # SKIP Streaming SVE set FPSIMD get SVE for VL 2656
4448 12:28:19.168839 # ok 2721 Set Streaming SVE VL 2672
4449 12:28:19.168896 # ok 2722 # SKIP Streaming SVE set SVE get SVE for VL 2672
4450 12:28:19.168970 # ok 2723 # SKIP Streaming SVE set SVE get FPSIMD for VL 2672
4451 12:28:19.169035 # ok 2724 # SKIP Streaming SVE set FPSIMD get SVE for VL 2672
4452 12:28:19.169095 # ok 2725 Set Streaming SVE VL 2688
4453 12:28:19.169154 # ok 2726 # SKIP Streaming SVE set SVE get SVE for VL 2688
4454 12:28:19.169223 # ok 2727 # SKIP Streaming SVE set SVE get FPSIMD for VL 2688
4455 12:28:19.169291 # ok 2728 # SKIP Streaming SVE set FPSIMD get SVE for VL 2688
4456 12:28:19.169352 # ok 2729 Set Streaming SVE VL 2704
4457 12:28:19.169410 # ok 2730 # SKIP Streaming SVE set SVE get SVE for VL 2704
4458 12:28:19.169477 # ok 2731 # SKIP Streaming SVE set SVE get FPSIMD for VL 2704
4459 12:28:19.169540 # ok 2732 # SKIP Streaming SVE set FPSIMD get SVE for VL 2704
4460 12:28:19.169602 # ok 2733 Set Streaming SVE VL 2720
4461 12:28:19.169681 # ok 2734 # SKIP Streaming SVE set SVE get SVE for VL 2720
4462 12:28:19.169759 # ok 2735 # SKIP Streaming SVE set SVE get FPSIMD for VL 2720
4463 12:28:19.170256 # ok 2736 # SKIP Streaming SVE set FPSIMD get SVE for VL 2720
4464 12:28:19.170344 # ok 2737 Set Streaming SVE VL 2736
4465 12:28:19.170434 # ok 2738 # SKIP Streaming SVE set SVE get SVE for VL 2736
4466 12:28:19.170527 # ok 2739 # SKIP Streaming SVE set SVE get FPSIMD for VL 2736
4467 12:28:19.170618 # ok 2740 # SKIP Streaming SVE set FPSIMD get SVE for VL 2736
4468 12:28:19.170694 # ok 2741 Set Streaming SVE VL 2752
4469 12:28:19.170768 # ok 2742 # SKIP Streaming SVE set SVE get SVE for VL 2752
4470 12:28:19.170842 # ok 2743 # SKIP Streaming SVE set SVE get FPSIMD for VL 2752
4471 12:28:19.170916 # ok 2744 # SKIP Streaming SVE set FPSIMD get SVE for VL 2752
4472 12:28:19.170991 # ok 2745 Set Streaming SVE VL 2768
4473 12:28:19.171065 # ok 2746 # SKIP Streaming SVE set SVE get SVE for VL 2768
4474 12:28:19.171139 # ok 2747 # SKIP Streaming SVE set SVE get FPSIMD for VL 2768
4475 12:28:19.171212 # ok 2748 # SKIP Streaming SVE set FPSIMD get SVE for VL 2768
4476 12:28:19.171288 # ok 2749 Set Streaming SVE VL 2784
4477 12:28:19.171367 # ok 2750 # SKIP Streaming SVE set SVE get SVE for VL 2784
4478 12:28:19.171441 # ok 2751 # SKIP Streaming SVE set SVE get FPSIMD for VL 2784
4479 12:28:19.171516 # ok 2752 # SKIP Streaming SVE set FPSIMD get SVE for VL 2784
4480 12:28:19.171589 # ok 2753 Set Streaming SVE VL 2800
4481 12:28:19.171661 # ok 2754 # SKIP Streaming SVE set SVE get SVE for VL 2800
4482 12:28:19.171735 # ok 2755 # SKIP Streaming SVE set SVE get FPSIMD for VL 2800
4483 12:28:19.171809 # ok 2756 # SKIP Streaming SVE set FPSIMD get SVE for VL 2800
4484 12:28:19.171882 # ok 2757 Set Streaming SVE VL 2816
4485 12:28:19.171956 # ok 2758 # SKIP Streaming SVE set SVE get SVE for VL 2816
4486 12:28:19.172030 # ok 2759 # SKIP Streaming SVE set SVE get FPSIMD for VL 2816
4487 12:28:19.172104 # ok 2760 # SKIP Streaming SVE set FPSIMD get SVE for VL 2816
4488 12:28:19.172178 # ok 2761 Set Streaming SVE VL 2832
4489 12:28:19.172252 # ok 2762 # SKIP Streaming SVE set SVE get SVE for VL 2832
4490 12:28:19.172325 # ok 2763 # SKIP Streaming SVE set SVE get FPSIMD for VL 2832
4491 12:28:19.172399 # ok 2764 # SKIP Streaming SVE set FPSIMD get SVE for VL 2832
4492 12:28:19.172473 # ok 2765 Set Streaming SVE VL 2848
4493 12:28:19.172547 # ok 2766 # SKIP Streaming SVE set SVE get SVE for VL 2848
4494 12:28:19.172620 # ok 2767 # SKIP Streaming SVE set SVE get FPSIMD for VL 2848
4495 12:28:19.172694 # ok 2768 # SKIP Streaming SVE set FPSIMD get SVE for VL 2848
4496 12:28:19.172768 # ok 2769 Set Streaming SVE VL 2864
4497 12:28:19.172842 # ok 2770 # SKIP Streaming SVE set SVE get SVE for VL 2864
4498 12:28:19.173126 # ok 2771 # SKIP Streaming SVE set SVE get FPSIMD for VL 2864
4499 12:28:19.173227 # ok 2772 # SKIP Streaming SVE set FPSIMD get SVE for VL 2864
4500 12:28:19.173329 # ok 2773 Set Streaming SVE VL 2880
4501 12:28:19.173432 # ok 2774 # SKIP Streaming SVE set SVE get SVE for VL 2880
4502 12:28:19.173537 # ok 2775 # SKIP Streaming SVE set SVE get FPSIMD for VL 2880
4503 12:28:19.173644 # ok 2776 # SKIP Streaming SVE set FPSIMD get SVE for VL 2880
4504 12:28:19.173770 # ok 2777 Set Streaming SVE VL 2896
4505 12:28:19.173873 # ok 2778 # SKIP Streaming SVE set SVE get SVE for VL 2896
4506 12:28:19.173973 # ok 2779 # SKIP Streaming SVE set SVE get FPSIMD for VL 2896
4507 12:28:19.174080 # ok 2780 # SKIP Streaming SVE set FPSIMD get SVE for VL 2896
4508 12:28:19.174193 # ok 2781 Set Streaming SVE VL 2912
4509 12:28:19.174296 # ok 2782 # SKIP Streaming SVE set SVE get SVE for VL 2912
4510 12:28:19.174393 # ok 2783 # SKIP Streaming SVE set SVE get FPSIMD for VL 2912
4511 12:28:19.174495 # ok 2784 # SKIP Streaming SVE set FPSIMD get SVE for VL 2912
4512 12:28:19.174595 # ok 2785 Set Streaming SVE VL 2928
4513 12:28:19.174705 # ok 2786 # SKIP Streaming SVE set SVE get SVE for VL 2928
4514 12:28:19.174806 # ok 2787 # SKIP Streaming SVE set SVE get FPSIMD for VL 2928
4515 12:28:19.174911 # ok 2788 # SKIP Streaming SVE set FPSIMD get SVE for VL 2928
4516 12:28:19.175017 # ok 2789 Set Streaming SVE VL 2944
4517 12:28:19.175129 # ok 2790 # SKIP Streaming SVE set SVE get SVE for VL 2944
4518 12:28:19.175221 # ok 2791 # SKIP Streaming SVE set SVE get FPSIMD for VL 2944
4519 12:28:19.175290 # ok 2792 # SKIP Streaming SVE set FPSIMD get SVE for VL 2944
4520 12:28:19.175351 # ok 2793 Set Streaming SVE VL 2960
4521 12:28:19.175412 # ok 2794 # SKIP Streaming SVE set SVE get SVE for VL 2960
4522 12:28:19.175475 # ok 2795 # SKIP Streaming SVE set SVE get FPSIMD for VL 2960
4523 12:28:19.175543 # ok 2796 # SKIP Streaming SVE set FPSIMD get SVE for VL 2960
4524 12:28:19.175617 # ok 2797 Set Streaming SVE VL 2976
4525 12:28:19.175691 # ok 2798 # SKIP Streaming SVE set SVE get SVE for VL 2976
4526 12:28:19.175762 # ok 2799 # SKIP Streaming SVE set SVE get FPSIMD for VL 2976
4527 12:28:19.175830 # ok 2800 # SKIP Streaming SVE set FPSIMD get SVE for VL 2976
4528 12:28:19.175900 # ok 2801 Set Streaming SVE VL 2992
4529 12:28:19.175971 # ok 2802 # SKIP Streaming SVE set SVE get SVE for VL 2992
4530 12:28:19.176038 # ok 2803 # SKIP Streaming SVE set SVE get FPSIMD for VL 2992
4531 12:28:19.176100 # ok 2804 # SKIP Streaming SVE set FPSIMD get SVE for VL 2992
4532 12:28:19.176167 # ok 2805 Set Streaming SVE VL 3008
4533 12:28:19.176439 # ok 2806 # SKIP Streaming SVE set SVE get SVE for VL 3008
4534 12:28:19.176525 # ok 2807 # SKIP Streaming SVE set SVE get FPSIMD for VL 3008
4535 12:28:19.176597 # ok 2808 # SKIP Streaming SVE set FPSIMD get SVE for VL 3008
4536 12:28:19.176666 # ok 2809 Set Streaming SVE VL 3024
4537 12:28:19.176732 # ok 2810 # SKIP Streaming SVE set SVE get SVE for VL 3024
4538 12:28:19.176794 # ok 2811 # SKIP Streaming SVE set SVE get FPSIMD for VL 3024
4539 12:28:19.176856 # ok 2812 # SKIP Streaming SVE set FPSIMD get SVE for VL 3024
4540 12:28:19.176916 # ok 2813 Set Streaming SVE VL 3040
4541 12:28:19.176977 # ok 2814 # SKIP Streaming SVE set SVE get SVE for VL 3040
4542 12:28:19.177042 # ok 2815 # SKIP Streaming SVE set SVE get FPSIMD for VL 3040
4543 12:28:19.177110 # ok 2816 # SKIP Streaming SVE set FPSIMD get SVE for VL 3040
4544 12:28:19.177175 # ok 2817 Set Streaming SVE VL 3056
4545 12:28:19.177245 # ok 2818 # SKIP Streaming SVE set SVE get SVE for VL 3056
4546 12:28:19.177323 # ok 2819 # SKIP Streaming SVE set SVE get FPSIMD for VL 3056
4547 12:28:19.177403 # ok 2820 # SKIP Streaming SVE set FPSIMD get SVE for VL 3056
4548 12:28:19.177502 # ok 2821 Set Streaming SVE VL 3072
4549 12:28:19.177582 # ok 2822 # SKIP Streaming SVE set SVE get SVE for VL 3072
4550 12:28:19.177672 # ok 2823 # SKIP Streaming SVE set SVE get FPSIMD for VL 3072
4551 12:28:19.177749 # ok 2824 # SKIP Streaming SVE set FPSIMD get SVE for VL 3072
4552 12:28:19.177845 # ok 2825 Set Streaming SVE VL 3088
4553 12:28:19.177930 # ok 2826 # SKIP Streaming SVE set SVE get SVE for VL 3088
4554 12:28:19.178003 # ok 2827 # SKIP Streaming SVE set SVE get FPSIMD for VL 3088
4555 12:28:19.178081 # ok 2828 # SKIP Streaming SVE set FPSIMD get SVE for VL 3088
4556 12:28:19.178162 # ok 2829 Set Streaming SVE VL 3104
4557 12:28:19.178230 # ok 2830 # SKIP Streaming SVE set SVE get SVE for VL 3104
4558 12:28:19.178291 # ok 2831 # SKIP Streaming SVE set SVE get FPSIMD for VL 3104
4559 12:28:19.178351 # ok 2832 # SKIP Streaming SVE set FPSIMD get SVE for VL 3104
4560 12:28:19.178411 # ok 2833 Set Streaming SVE VL 3120
4561 12:28:19.178470 # ok 2834 # SKIP Streaming SVE set SVE get SVE for VL 3120
4562 12:28:19.178529 # ok 2835 # SKIP Streaming SVE set SVE get FPSIMD for VL 3120
4563 12:28:19.178592 # ok 2836 # SKIP Streaming SVE set FPSIMD get SVE for VL 3120
4564 12:28:19.178661 # ok 2837 Set Streaming SVE VL 3136
4565 12:28:19.178721 # ok 2838 # SKIP Streaming SVE set SVE get SVE for VL 3136
4566 12:28:19.178780 # ok 2839 # SKIP Streaming SVE set SVE get FPSIMD for VL 3136
4567 12:28:19.178839 # ok 2840 # SKIP Streaming SVE set FPSIMD get SVE for VL 3136
4568 12:28:19.178897 # ok 2841 Set Streaming SVE VL 3152
4569 12:28:19.179158 # ok 2842 # SKIP Streaming SVE set SVE get SVE for VL 3152
4570 12:28:19.179248 # ok 2843 # SKIP Streaming SVE set SVE get FPSIMD for VL 3152
4571 12:28:19.179332 # ok 2844 # SKIP Streaming SVE set FPSIMD get SVE for VL 3152
4572 12:28:19.179412 # ok 2845 Set Streaming SVE VL 3168
4573 12:28:19.179493 # ok 2846 # SKIP Streaming SVE set SVE get SVE for VL 3168
4574 12:28:19.179573 # ok 2847 # SKIP Streaming SVE set SVE get FPSIMD for VL 3168
4575 12:28:19.179657 # ok 2848 # SKIP Streaming SVE set FPSIMD get SVE for VL 3168
4576 12:28:19.179742 # ok 2849 Set Streaming SVE VL 3184
4577 12:28:19.179830 # ok 2850 # SKIP Streaming SVE set SVE get SVE for VL 3184
4578 12:28:19.179912 # ok 2851 # SKIP Streaming SVE set SVE get FPSIMD for VL 3184
4579 12:28:19.180010 # ok 2852 # SKIP Streaming SVE set FPSIMD get SVE for VL 3184
4580 12:28:19.180120 # ok 2853 Set Streaming SVE VL 3200
4581 12:28:19.180233 # ok 2854 # SKIP Streaming SVE set SVE get SVE for VL 3200
4582 12:28:19.180340 # ok 2855 # SKIP Streaming SVE set SVE get FPSIMD for VL 3200
4583 12:28:19.180451 # ok 2856 # SKIP Streaming SVE set FPSIMD get SVE for VL 3200
4584 12:28:19.180580 # ok 2857 Set Streaming SVE VL 3216
4585 12:28:19.180687 # ok 2858 # SKIP Streaming SVE set SVE get SVE for VL 3216
4586 12:28:19.180803 # ok 2859 # SKIP Streaming SVE set SVE get FPSIMD for VL 3216
4587 12:28:19.180922 # ok 2860 # SKIP Streaming SVE set FPSIMD get SVE for VL 3216
4588 12:28:19.181020 # ok 2861 Set Streaming SVE VL 3232
4589 12:28:19.181107 # ok 2862 # SKIP Streaming SVE set SVE get SVE for VL 3232
4590 12:28:19.181188 # ok 2863 # SKIP Streaming SVE set SVE get FPSIMD for VL 3232
4591 12:28:19.181269 # ok 2864 # SKIP Streaming SVE set FPSIMD get SVE for VL 3232
4592 12:28:19.181353 # ok 2865 Set Streaming SVE VL 3248
4593 12:28:19.181437 # ok 2866 # SKIP Streaming SVE set SVE get SVE for VL 3248
4594 12:28:19.181521 # ok 2867 # SKIP Streaming SVE set SVE get FPSIMD for VL 3248
4595 12:28:19.181599 # ok 2868 # SKIP Streaming SVE set FPSIMD get SVE for VL 3248
4596 12:28:19.181687 # ok 2869 Set Streaming SVE VL 3264
4597 12:28:19.181748 # ok 2870 # SKIP Streaming SVE set SVE get SVE for VL 3264
4598 12:28:19.181807 # ok 2871 # SKIP Streaming SVE set SVE get FPSIMD for VL 3264
4599 12:28:19.181866 # ok 2872 # SKIP Streaming SVE set FPSIMD get SVE for VL 3264
4600 12:28:19.181924 # ok 2873 Set Streaming SVE VL 3280
4601 12:28:19.181983 # ok 2874 # SKIP Streaming SVE set SVE get SVE for VL 3280
4602 12:28:19.182045 # ok 2875 # SKIP Streaming SVE set SVE get FPSIMD for VL 3280
4603 12:28:19.182106 # ok 2876 # SKIP Streaming SVE set FPSIMD get SVE for VL 3280
4604 12:28:19.182366 # ok 2877 Set Streaming SVE VL 3296
4605 12:28:19.185571 # ok 2878 # SKIP Streaming SVE set SVE get SVE for VL 3296
4606 12:28:19.185790 # ok 2879 # SKIP Streaming SVE set SVE get FPSIMD for VL 3296
4607 12:28:19.185920 # ok 2880 # SKIP Streaming SVE set FPSIMD get SVE for VL 3296
4608 12:28:19.186033 # ok 2881 Set Streaming SVE VL 3312
4609 12:28:19.186159 # ok 2882 # SKIP Streaming SVE set SVE get SVE for VL 3312
4610 12:28:19.186339 # ok 2883 # SKIP Streaming SVE set SVE get FPSIMD for VL 3312
4611 12:28:19.186441 # ok 2884 # SKIP Streaming SVE set FPSIMD get SVE for VL 3312
4612 12:28:19.186707 # ok 2885 Set Streaming SVE VL 3328
4613 12:28:19.186808 # ok 2886 # SKIP Streaming SVE set SVE get SVE for VL 3328
4614 12:28:19.187043 # ok 2887 # SKIP Streaming SVE set SVE get FPSIMD for VL 3328
4615 12:28:19.187177 # ok 2888 # SKIP Streaming SVE set FPSIMD get SVE for VL 3328
4616 12:28:19.187297 # ok 2889 Set Streaming SVE VL 3344
4617 12:28:19.195554 # ok 2890 # SKIP Streaming SVE set SVE get SVE for VL 3344
4618 12:28:19.196815 # ok 2891 # SKIP Streaming SVE set SVE get FPSIMD for VL 3344
4619 12:28:19.196959 # ok 2892 # SKIP Streaming SVE set FPSIMD get SVE for VL 3344
4620 12:28:19.197218 # ok 2893 Set Streaming SVE VL 3360
4621 12:28:19.197330 # ok 2894 # SKIP Streaming SVE set SVE get SVE for VL 3360
4622 12:28:19.197451 # ok 2895 # SKIP Streaming SVE set SVE get FPSIMD for VL 3360
4623 12:28:19.197755 # ok 2896 # SKIP Streaming SVE set FPSIMD get SVE for VL 3360
4624 12:28:19.197871 # ok 2897 Set Streaming SVE VL 3376
4625 12:28:19.198182 # ok 2898 # SKIP Streaming SVE set SVE get SVE for VL 3376
4626 12:28:19.198319 # ok 2899 # SKIP Streaming SVE set SVE get FPSIMD for VL 3376
4627 12:28:19.198426 # ok 2900 # SKIP Streaming SVE set FPSIMD get SVE for VL 3376
4628 12:28:19.198558 # ok 2901 Set Streaming SVE VL 3392
4629 12:28:19.198650 # ok 2902 # SKIP Streaming SVE set SVE get SVE for VL 3392
4630 12:28:19.198990 # ok 2903 # SKIP Streaming SVE set SVE get FPSIMD for VL 3392
4631 12:28:19.199111 # ok 2904 # SKIP Streaming SVE set FPSIMD get SVE for VL 3392
4632 12:28:19.199198 # ok 2905 Set Streaming SVE VL 3408
4633 12:28:19.199463 # ok 2906 # SKIP Streaming SVE set SVE get SVE for VL 3408
4634 12:28:19.199571 # ok 2907 # SKIP Streaming SVE set SVE get FPSIMD for VL 3408
4635 12:28:19.209134 # ok 2908 # SKIP Streaming SVE set FPSIMD get SVE for VL 3408
4636 12:28:19.209384 # ok 2909 Set Streaming SVE VL 3424
4637 12:28:19.209752 # ok 2910 # SKIP Streaming SVE set SVE get SVE for VL 3424
4638 12:28:19.209863 # ok 2911 # SKIP Streaming SVE set SVE get FPSIMD for VL 3424
4639 12:28:19.209955 # ok 2912 # SKIP Streaming SVE set FPSIMD get SVE for VL 3424
4640 12:28:19.210044 # ok 2913 Set Streaming SVE VL 3440
4641 12:28:19.210131 # ok 2914 # SKIP Streaming SVE set SVE get SVE for VL 3440
4642 12:28:19.210226 # ok 2915 # SKIP Streaming SVE set SVE get FPSIMD for VL 3440
4643 12:28:19.210317 # ok 2916 # SKIP Streaming SVE set FPSIMD get SVE for VL 3440
4644 12:28:19.210619 # ok 2917 Set Streaming SVE VL 3456
4645 12:28:19.210735 # ok 2918 # SKIP Streaming SVE set SVE get SVE for VL 3456
4646 12:28:19.211050 # ok 2919 # SKIP Streaming SVE set SVE get FPSIMD for VL 3456
4647 12:28:19.211167 # ok 2920 # SKIP Streaming SVE set FPSIMD get SVE for VL 3456
4648 12:28:19.211256 # ok 2921 Set Streaming SVE VL 3472
4649 12:28:19.211554 # ok 2922 # SKIP Streaming SVE set SVE get SVE for VL 3472
4650 12:28:19.224918 # ok 2923 # SKIP Streaming SVE set SVE get FPSIMD for VL 3472
4651 12:28:19.225180 # ok 2924 # SKIP Streaming SVE set FPSIMD get SVE for VL 3472
4652 12:28:19.225492 # ok 2925 Set Streaming SVE VL 3488
4653 12:28:19.225592 # ok 2926 # SKIP Streaming SVE set SVE get SVE for VL 3488
4654 12:28:19.225700 # ok 2927 # SKIP Streaming SVE set SVE get FPSIMD for VL 3488
4655 12:28:19.225810 # ok 2928 # SKIP Streaming SVE set FPSIMD get SVE for VL 3488
4656 12:28:19.225906 # ok 2929 Set Streaming SVE VL 3504
4657 12:28:19.226014 # ok 2930 # SKIP Streaming SVE set SVE get SVE for VL 3504
4658 12:28:19.226140 # ok 2931 # SKIP Streaming SVE set SVE get FPSIMD for VL 3504
4659 12:28:19.226439 # ok 2932 # SKIP Streaming SVE set FPSIMD get SVE for VL 3504
4660 12:28:19.226552 # ok 2933 Set Streaming SVE VL 3520
4661 12:28:19.226849 # ok 2934 # SKIP Streaming SVE set SVE get SVE for VL 3520
4662 12:28:19.226961 # ok 2935 # SKIP Streaming SVE set SVE get FPSIMD for VL 3520
4663 12:28:19.229709 # ok 2936 # SKIP Streaming SVE set FPSIMD get SVE for VL 3520
4664 12:28:19.229882 # ok 2937 Set Streaming SVE VL 3536
4665 12:28:19.229971 # ok 2938 # SKIP Streaming SVE set SVE get SVE for VL 3536
4666 12:28:19.230061 # ok 2939 # SKIP Streaming SVE set SVE get FPSIMD for VL 3536
4667 12:28:19.237094 # ok 2940 # SKIP Streaming SVE set FPSIMD get SVE for VL 3536
4668 12:28:19.237564 # ok 2941 Set Streaming SVE VL 3552
4669 12:28:19.237691 # ok 2942 # SKIP Streaming SVE set SVE get SVE for VL 3552
4670 12:28:19.237807 # ok 2943 # SKIP Streaming SVE set SVE get FPSIMD for VL 3552
4671 12:28:19.237920 # ok 2944 # SKIP Streaming SVE set FPSIMD get SVE for VL 3552
4672 12:28:19.238011 # ok 2945 Set Streaming SVE VL 3568
4673 12:28:19.238113 # ok 2946 # SKIP Streaming SVE set SVE get SVE for VL 3568
4674 12:28:19.238208 # ok 2947 # SKIP Streaming SVE set SVE get FPSIMD for VL 3568
4675 12:28:19.238508 # ok 2948 # SKIP Streaming SVE set FPSIMD get SVE for VL 3568
4676 12:28:19.238618 # ok 2949 Set Streaming SVE VL 3584
4677 12:28:19.238732 # ok 2950 # SKIP Streaming SVE set SVE get SVE for VL 3584
4678 12:28:19.239020 # ok 2951 # SKIP Streaming SVE set SVE get FPSIMD for VL 3584
4679 12:28:19.239352 # ok 2952 # SKIP Streaming SVE set FPSIMD get SVE for VL 3584
4680 12:28:19.239471 # ok 2953 Set Streaming SVE VL 3600
4681 12:28:19.239553 # ok 2954 # SKIP Streaming SVE set SVE get SVE for VL 3600
4682 12:28:19.245342 # ok 2955 # SKIP Streaming SVE set SVE get FPSIMD for VL 3600
4683 12:28:19.245553 # ok 2956 # SKIP Streaming SVE set FPSIMD get SVE for VL 3600
4684 12:28:19.245678 # ok 2957 Set Streaming SVE VL 3616
4685 12:28:19.245772 # ok 2958 # SKIP Streaming SVE set SVE get SVE for VL 3616
4686 12:28:19.245874 # ok 2959 # SKIP Streaming SVE set SVE get FPSIMD for VL 3616
4687 12:28:19.245964 # ok 2960 # SKIP Streaming SVE set FPSIMD get SVE for VL 3616
4688 12:28:19.246067 # ok 2961 Set Streaming SVE VL 3632
4689 12:28:19.246167 # ok 2962 # SKIP Streaming SVE set SVE get SVE for VL 3632
4690 12:28:19.246263 # ok 2963 # SKIP Streaming SVE set SVE get FPSIMD for VL 3632
4691 12:28:19.246553 # ok 2964 # SKIP Streaming SVE set FPSIMD get SVE for VL 3632
4692 12:28:19.246667 # ok 2965 Set Streaming SVE VL 3648
4693 12:28:19.246758 # ok 2966 # SKIP Streaming SVE set SVE get SVE for VL 3648
4694 12:28:19.247032 # ok 2967 # SKIP Streaming SVE set SVE get FPSIMD for VL 3648
4695 12:28:19.247145 # ok 2968 # SKIP Streaming SVE set FPSIMD get SVE for VL 3648
4696 12:28:19.247291 # ok 2969 Set Streaming SVE VL 3664
4697 12:28:19.247400 # ok 2970 # SKIP Streaming SVE set SVE get SVE for VL 3664
4698 12:28:19.247492 # ok 2971 # SKIP Streaming SVE set SVE get FPSIMD for VL 3664
4699 12:28:19.248440 # ok 2972 # SKIP Streaming SVE set FPSIMD get SVE for VL 3664
4700 12:28:19.248543 # ok 2973 Set Streaming SVE VL 3680
4701 12:28:19.248864 # ok 2974 # SKIP Streaming SVE set SVE get SVE for VL 3680
4702 12:28:19.248964 # ok 2975 # SKIP Streaming SVE set SVE get FPSIMD for VL 3680
4703 12:28:19.249107 # ok 2976 # SKIP Streaming SVE set FPSIMD get SVE for VL 3680
4704 12:28:19.249192 # ok 2977 Set Streaming SVE VL 3696
4705 12:28:19.249277 # ok 2978 # SKIP Streaming SVE set SVE get SVE for VL 3696
4706 12:28:19.249383 # ok 2979 # SKIP Streaming SVE set SVE get FPSIMD for VL 3696
4707 12:28:19.249514 # ok 2980 # SKIP Streaming SVE set FPSIMD get SVE for VL 3696
4708 12:28:19.249610 # ok 2981 Set Streaming SVE VL 3712
4709 12:28:19.249734 # ok 2982 # SKIP Streaming SVE set SVE get SVE for VL 3712
4710 12:28:19.249842 # ok 2983 # SKIP Streaming SVE set SVE get FPSIMD for VL 3712
4711 12:28:19.249974 # ok 2984 # SKIP Streaming SVE set FPSIMD get SVE for VL 3712
4712 12:28:19.250088 # ok 2985 Set Streaming SVE VL 3728
4713 12:28:19.250236 # ok 2986 # SKIP Streaming SVE set SVE get SVE for VL 3728
4714 12:28:19.250367 # ok 2987 # SKIP Streaming SVE set SVE get FPSIMD for VL 3728
4715 12:28:19.250468 # ok 2988 # SKIP Streaming SVE set FPSIMD get SVE for VL 3728
4716 12:28:19.250592 # ok 2989 Set Streaming SVE VL 3744
4717 12:28:19.251083 # ok 2990 # SKIP Streaming SVE set SVE get SVE for VL 3744
4718 12:28:19.251210 # ok 2991 # SKIP Streaming SVE set SVE get FPSIMD for VL 3744
4719 12:28:19.251318 # ok 2992 # SKIP Streaming SVE set FPSIMD get SVE for VL 3744
4720 12:28:19.251412 # ok 2993 Set Streaming SVE VL 3760
4721 12:28:19.251488 # ok 2994 # SKIP Streaming SVE set SVE get SVE for VL 3760
4722 12:28:19.251750 # ok 2995 # SKIP Streaming SVE set SVE get FPSIMD for VL 3760
4723 12:28:19.251835 # ok 2996 # SKIP Streaming SVE set FPSIMD get SVE for VL 3760
4724 12:28:19.251925 # ok 2997 Set Streaming SVE VL 3776
4725 12:28:19.252001 # ok 2998 # SKIP Streaming SVE set SVE get SVE for VL 3776
4726 12:28:19.256461 # ok 2999 # SKIP Streaming SVE set SVE get FPSIMD for VL 3776
4727 12:28:19.256860 # ok 3000 # SKIP Streaming SVE set FPSIMD get SVE for VL 3776
4728 12:28:19.256973 # ok 3001 Set Streaming SVE VL 3792
4729 12:28:19.257085 # ok 3002 # SKIP Streaming SVE set SVE get SVE for VL 3792
4730 12:28:19.257186 # ok 3003 # SKIP Streaming SVE set SVE get FPSIMD for VL 3792
4731 12:28:19.257278 # ok 3004 # SKIP Streaming SVE set FPSIMD get SVE for VL 3792
4732 12:28:19.257373 # ok 3005 Set Streaming SVE VL 3808
4733 12:28:19.257450 # ok 3006 # SKIP Streaming SVE set SVE get SVE for VL 3808
4734 12:28:19.257537 # ok 3007 # SKIP Streaming SVE set SVE get FPSIMD for VL 3808
4735 12:28:19.257615 # ok 3008 # SKIP Streaming SVE set FPSIMD get SVE for VL 3808
4736 12:28:19.257717 # ok 3009 Set Streaming SVE VL 3824
4737 12:28:19.257799 # ok 3010 # SKIP Streaming SVE set SVE get SVE for VL 3824
4738 12:28:19.257880 # ok 3011 # SKIP Streaming SVE set SVE get FPSIMD for VL 3824
4739 12:28:19.258170 # ok 3012 # SKIP Streaming SVE set FPSIMD get SVE for VL 3824
4740 12:28:19.258266 # ok 3013 Set Streaming SVE VL 3840
4741 12:28:19.258362 # ok 3014 # SKIP Streaming SVE set SVE get SVE for VL 3840
4742 12:28:19.258460 # ok 3015 # SKIP Streaming SVE set SVE get FPSIMD for VL 3840
4743 12:28:19.258587 # ok 3016 # SKIP Streaming SVE set FPSIMD get SVE for VL 3840
4744 12:28:19.258709 # ok 3017 Set Streaming SVE VL 3856
4745 12:28:19.259069 # ok 3018 # SKIP Streaming SVE set SVE get SVE for VL 3856
4746 12:28:19.259282 # ok 3019 # SKIP Streaming SVE set SVE get FPSIMD for VL 3856
4747 12:28:19.259445 # ok 3020 # SKIP Streaming SVE set FPSIMD get SVE for VL 3856
4748 12:28:19.259582 # ok 3021 Set Streaming SVE VL 3872
4749 12:28:19.259728 # ok 3022 # SKIP Streaming SVE set SVE get SVE for VL 3872
4750 12:28:19.259850 # ok 3023 # SKIP Streaming SVE set SVE get FPSIMD for VL 3872
4751 12:28:19.259968 # ok 3024 # SKIP Streaming SVE set FPSIMD get SVE for VL 3872
4752 12:28:19.266723 # ok 3025 Set Streaming SVE VL 3888
4753 12:28:19.267183 # ok 3026 # SKIP Streaming SVE set SVE get SVE for VL 3888
4754 12:28:19.267482 # ok 3027 # SKIP Streaming SVE set SVE get FPSIMD for VL 3888
4755 12:28:19.272528 # ok 3028 # SKIP Streaming SVE set FPSIMD get SVE for VL 3888
4756 12:28:19.272785 # ok 3029 Set Streaming SVE VL 3904
4757 12:28:19.273132 # ok 3030 # SKIP Streaming SVE set SVE get SVE for VL 3904
4758 12:28:19.273278 # ok 3031 # SKIP Streaming SVE set SVE get FPSIMD for VL 3904
4759 12:28:19.273456 # ok 3032 # SKIP Streaming SVE set FPSIMD get SVE for VL 3904
4760 12:28:19.273553 # ok 3033 Set Streaming SVE VL 3920
4761 12:28:19.273643 # ok 3034 # SKIP Streaming SVE set SVE get SVE for VL 3920
4762 12:28:19.273741 # ok 3035 # SKIP Streaming SVE set SVE get FPSIMD for VL 3920
4763 12:28:19.273850 # ok 3036 # SKIP Streaming SVE set FPSIMD get SVE for VL 3920
4764 12:28:19.273942 # ok 3037 Set Streaming SVE VL 3936
4765 12:28:19.274031 # ok 3038 # SKIP Streaming SVE set SVE get SVE for VL 3936
4766 12:28:19.274121 # ok 3039 # SKIP Streaming SVE set SVE get FPSIMD for VL 3936
4767 12:28:19.274230 # ok 3040 # SKIP Streaming SVE set FPSIMD get SVE for VL 3936
4768 12:28:19.274321 # ok 3041 Set Streaming SVE VL 3952
4769 12:28:19.274409 # ok 3042 # SKIP Streaming SVE set SVE get SVE for VL 3952
4770 12:28:19.274498 # ok 3043 # SKIP Streaming SVE set SVE get FPSIMD for VL 3952
4771 12:28:19.274606 # ok 3044 # SKIP Streaming SVE set FPSIMD get SVE for VL 3952
4772 12:28:19.274698 # ok 3045 Set Streaming SVE VL 3968
4773 12:28:19.274787 # ok 3046 # SKIP Streaming SVE set SVE get SVE for VL 3968
4774 12:28:19.274875 # ok 3047 # SKIP Streaming SVE set SVE get FPSIMD for VL 3968
4775 12:28:19.274961 # ok 3048 # SKIP Streaming SVE set FPSIMD get SVE for VL 3968
4776 12:28:19.275067 # ok 3049 Set Streaming SVE VL 3984
4777 12:28:19.275159 # ok 3050 # SKIP Streaming SVE set SVE get SVE for VL 3984
4778 12:28:19.275251 # ok 3051 # SKIP Streaming SVE set SVE get FPSIMD for VL 3984
4779 12:28:19.275338 # ok 3052 # SKIP Streaming SVE set FPSIMD get SVE for VL 3984
4780 12:28:19.275875 # ok 3053 Set Streaming SVE VL 4000
4781 12:28:19.275974 # ok 3054 # SKIP Streaming SVE set SVE get SVE for VL 4000
4782 12:28:19.276065 # ok 3055 # SKIP Streaming SVE set SVE get FPSIMD for VL 4000
4783 12:28:19.276155 # ok 3056 # SKIP Streaming SVE set FPSIMD get SVE for VL 4000
4784 12:28:19.280680 # ok 3057 Set Streaming SVE VL 4016
4785 12:28:19.280919 # ok 3058 # SKIP Streaming SVE set SVE get SVE for VL 4016
4786 12:28:19.281236 # ok 3059 # SKIP Streaming SVE set SVE get FPSIMD for VL 4016
4787 12:28:19.281356 # ok 3060 # SKIP Streaming SVE set FPSIMD get SVE for VL 4016
4788 12:28:19.281464 # ok 3061 Set Streaming SVE VL 4032
4789 12:28:19.281548 # ok 3062 # SKIP Streaming SVE set SVE get SVE for VL 4032
4790 12:28:19.281630 # ok 3063 # SKIP Streaming SVE set SVE get FPSIMD for VL 4032
4791 12:28:19.281742 # ok 3064 # SKIP Streaming SVE set FPSIMD get SVE for VL 4032
4792 12:28:19.281826 # ok 3065 Set Streaming SVE VL 4048
4793 12:28:19.281912 # ok 3066 # SKIP Streaming SVE set SVE get SVE for VL 4048
4794 12:28:19.281996 # ok 3067 # SKIP Streaming SVE set SVE get FPSIMD for VL 4048
4795 12:28:19.282099 # ok 3068 # SKIP Streaming SVE set FPSIMD get SVE for VL 4048
4796 12:28:19.282188 # ok 3069 Set Streaming SVE VL 4064
4797 12:28:19.282295 # ok 3070 # SKIP Streaming SVE set SVE get SVE for VL 4064
4798 12:28:19.282398 # ok 3071 # SKIP Streaming SVE set SVE get FPSIMD for VL 4064
4799 12:28:19.282758 # ok 3072 # SKIP Streaming SVE set FPSIMD get SVE for VL 4064
4800 12:28:19.282865 # ok 3073 Set Streaming SVE VL 4080
4801 12:28:19.282957 # ok 3074 # SKIP Streaming SVE set SVE get SVE for VL 4080
4802 12:28:19.283331 # ok 3075 # SKIP Streaming SVE set SVE get FPSIMD for VL 4080
4803 12:28:19.283438 # ok 3076 # SKIP Streaming SVE set FPSIMD get SVE for VL 4080
4804 12:28:19.283526 # ok 3077 Set Streaming SVE VL 4096
4805 12:28:19.283612 # ok 3078 # SKIP Streaming SVE set SVE get SVE for VL 4096
4806 12:28:19.283697 # ok 3079 # SKIP Streaming SVE set SVE get FPSIMD for VL 4096
4807 12:28:19.283782 # ok 3080 # SKIP Streaming SVE set FPSIMD get SVE for VL 4096
4808 12:28:19.283870 # ok 3081 Set Streaming SVE VL 4112
4809 12:28:19.283977 # ok 3082 # SKIP Streaming SVE set SVE get SVE for VL 4112
4810 12:28:19.284064 # ok 3083 # SKIP Streaming SVE set SVE get FPSIMD for VL 4112
4811 12:28:19.284149 # ok 3084 # SKIP Streaming SVE set FPSIMD get SVE for VL 4112
4812 12:28:19.288600 # ok 3085 Set Streaming SVE VL 4128
4813 12:28:19.289028 # ok 3086 # SKIP Streaming SVE set SVE get SVE for VL 4128
4814 12:28:19.289139 # ok 3087 # SKIP Streaming SVE set SVE get FPSIMD for VL 4128
4815 12:28:19.289234 # ok 3088 # SKIP Streaming SVE set FPSIMD get SVE for VL 4128
4816 12:28:19.289324 # ok 3089 Set Streaming SVE VL 4144
4817 12:28:19.289414 # ok 3090 # SKIP Streaming SVE set SVE get SVE for VL 4144
4818 12:28:19.289518 # ok 3091 # SKIP Streaming SVE set SVE get FPSIMD for VL 4144
4819 12:28:19.289613 # ok 3092 # SKIP Streaming SVE set FPSIMD get SVE for VL 4144
4820 12:28:19.289711 # ok 3093 Set Streaming SVE VL 4160
4821 12:28:19.289815 # ok 3094 # SKIP Streaming SVE set SVE get SVE for VL 4160
4822 12:28:19.289903 # ok 3095 # SKIP Streaming SVE set SVE get FPSIMD for VL 4160
4823 12:28:19.289990 # ok 3096 # SKIP Streaming SVE set FPSIMD get SVE for VL 4160
4824 12:28:19.290088 # ok 3097 Set Streaming SVE VL 4176
4825 12:28:19.290175 # ok 3098 # SKIP Streaming SVE set SVE get SVE for VL 4176
4826 12:28:19.290274 # ok 3099 # SKIP Streaming SVE set SVE get FPSIMD for VL 4176
4827 12:28:19.290370 # ok 3100 # SKIP Streaming SVE set FPSIMD get SVE for VL 4176
4828 12:28:19.290463 # ok 3101 Set Streaming SVE VL 4192
4829 12:28:19.290758 # ok 3102 # SKIP Streaming SVE set SVE get SVE for VL 4192
4830 12:28:19.294172 # ok 3103 # SKIP Streaming SVE set SVE get FPSIMD for VL 4192
4831 12:28:19.294380 # ok 3104 # SKIP Streaming SVE set FPSIMD get SVE for VL 4192
4832 12:28:19.294476 # ok 3105 Set Streaming SVE VL 4208
4833 12:28:19.294565 # ok 3106 # SKIP Streaming SVE set SVE get SVE for VL 4208
4834 12:28:19.294653 # ok 3107 # SKIP Streaming SVE set SVE get FPSIMD for VL 4208
4835 12:28:19.294740 # ok 3108 # SKIP Streaming SVE set FPSIMD get SVE for VL 4208
4836 12:28:19.294828 # ok 3109 Set Streaming SVE VL 4224
4837 12:28:19.294915 # ok 3110 # SKIP Streaming SVE set SVE get SVE for VL 4224
4838 12:28:19.295571 # ok 3111 # SKIP Streaming SVE set SVE get FPSIMD for VL 4224
4839 12:28:19.296624 # ok 3112 # SKIP Streaming SVE set FPSIMD get SVE for VL 4224
4840 12:28:19.296938 # ok 3113 Set Streaming SVE VL 4240
4841 12:28:19.297030 # ok 3114 # SKIP Streaming SVE set SVE get SVE for VL 4240
4842 12:28:19.297099 # ok 3115 # SKIP Streaming SVE set SVE get FPSIMD for VL 4240
4843 12:28:19.297186 # ok 3116 # SKIP Streaming SVE set FPSIMD get SVE for VL 4240
4844 12:28:19.297255 # ok 3117 Set Streaming SVE VL 4256
4845 12:28:19.297360 # ok 3118 # SKIP Streaming SVE set SVE get SVE for VL 4256
4846 12:28:19.297678 # ok 3119 # SKIP Streaming SVE set SVE get FPSIMD for VL 4256
4847 12:28:19.297785 # ok 3120 # SKIP Streaming SVE set FPSIMD get SVE for VL 4256
4848 12:28:19.297894 # ok 3121 Set Streaming SVE VL 4272
4849 12:28:19.298004 # ok 3122 # SKIP Streaming SVE set SVE get SVE for VL 4272
4850 12:28:19.298110 # ok 3123 # SKIP Streaming SVE set SVE get FPSIMD for VL 4272
4851 12:28:19.298211 # ok 3124 # SKIP Streaming SVE set FPSIMD get SVE for VL 4272
4852 12:28:19.298312 # ok 3125 Set Streaming SVE VL 4288
4853 12:28:19.298552 # ok 3126 # SKIP Streaming SVE set SVE get SVE for VL 4288
4854 12:28:19.298661 # ok 3127 # SKIP Streaming SVE set SVE get FPSIMD for VL 4288
4855 12:28:19.298767 # ok 3128 # SKIP Streaming SVE set FPSIMD get SVE for VL 4288
4856 12:28:19.298858 # ok 3129 Set Streaming SVE VL 4304
4857 12:28:19.298963 # ok 3130 # SKIP Streaming SVE set SVE get SVE for VL 4304
4858 12:28:19.299070 # ok 3131 # SKIP Streaming SVE set SVE get FPSIMD for VL 4304
4859 12:28:19.299372 # ok 3132 # SKIP Streaming SVE set FPSIMD get SVE for VL 4304
4860 12:28:19.299506 # ok 3133 Set Streaming SVE VL 4320
4861 12:28:19.299616 # ok 3134 # SKIP Streaming SVE set SVE get SVE for VL 4320
4862 12:28:19.302391 # ok 3135 # SKIP Streaming SVE set SVE get FPSIMD for VL 4320
4863 12:28:19.302883 # ok 3136 # SKIP Streaming SVE set FPSIMD get SVE for VL 4320
4864 12:28:19.303038 # ok 3137 Set Streaming SVE VL 4336
4865 12:28:19.303130 # ok 3138 # SKIP Streaming SVE set SVE get SVE for VL 4336
4866 12:28:19.303216 # ok 3139 # SKIP Streaming SVE set SVE get FPSIMD for VL 4336
4867 12:28:19.303320 # ok 3140 # SKIP Streaming SVE set FPSIMD get SVE for VL 4336
4868 12:28:19.303412 # ok 3141 Set Streaming SVE VL 4352
4869 12:28:19.303499 # ok 3142 # SKIP Streaming SVE set SVE get SVE for VL 4352
4870 12:28:19.303584 # ok 3143 # SKIP Streaming SVE set SVE get FPSIMD for VL 4352
4871 12:28:19.303687 # ok 3144 # SKIP Streaming SVE set FPSIMD get SVE for VL 4352
4872 12:28:19.303774 # ok 3145 Set Streaming SVE VL 4368
4873 12:28:19.307355 # ok 3146 # SKIP Streaming SVE set SVE get SVE for VL 4368
4874 12:28:19.307685 # ok 3147 # SKIP Streaming SVE set SVE get FPSIMD for VL 4368
4875 12:28:19.307866 # ok 3148 # SKIP Streaming SVE set FPSIMD get SVE for VL 4368
4876 12:28:19.308040 # ok 3149 Set Streaming SVE VL 4384
4877 12:28:19.308201 # ok 3150 # SKIP Streaming SVE set SVE get SVE for VL 4384
4878 12:28:19.308411 # ok 3151 # SKIP Streaming SVE set SVE get FPSIMD for VL 4384
4879 12:28:19.308588 # ok 3152 # SKIP Streaming SVE set FPSIMD get SVE for VL 4384
4880 12:28:19.308758 # ok 3153 Set Streaming SVE VL 4400
4881 12:28:19.308906 # ok 3154 # SKIP Streaming SVE set SVE get SVE for VL 4400
4882 12:28:19.309168 # ok 3155 # SKIP Streaming SVE set SVE get FPSIMD for VL 4400
4883 12:28:19.309369 # ok 3156 # SKIP Streaming SVE set FPSIMD get SVE for VL 4400
4884 12:28:19.309586 # ok 3157 Set Streaming SVE VL 4416
4885 12:28:19.309827 # ok 3158 # SKIP Streaming SVE set SVE get SVE for VL 4416
4886 12:28:19.310030 # ok 3159 # SKIP Streaming SVE set SVE get FPSIMD for VL 4416
4887 12:28:19.310199 # ok 3160 # SKIP Streaming SVE set FPSIMD get SVE for VL 4416
4888 12:28:19.310352 # ok 3161 Set Streaming SVE VL 4432
4889 12:28:19.310509 # ok 3162 # SKIP Streaming SVE set SVE get SVE for VL 4432
4890 12:28:19.310703 # ok 3163 # SKIP Streaming SVE set SVE get FPSIMD for VL 4432
4891 12:28:19.310856 # ok 3164 # SKIP Streaming SVE set FPSIMD get SVE for VL 4432
4892 12:28:19.310990 # ok 3165 Set Streaming SVE VL 4448
4893 12:28:19.311110 # ok 3166 # SKIP Streaming SVE set SVE get SVE for VL 4448
4894 12:28:19.311229 # ok 3167 # SKIP Streaming SVE set SVE get FPSIMD for VL 4448
4895 12:28:19.311347 # ok 3168 # SKIP Streaming SVE set FPSIMD get SVE for VL 4448
4896 12:28:19.311464 # ok 3169 Set Streaming SVE VL 4464
4897 12:28:19.311591 # ok 3170 # SKIP Streaming SVE set SVE get SVE for VL 4464
4898 12:28:19.311740 # ok 3171 # SKIP Streaming SVE set SVE get FPSIMD for VL 4464
4899 12:28:19.311876 # ok 3172 # SKIP Streaming SVE set FPSIMD get SVE for VL 4464
4900 12:28:19.312014 # ok 3173 Set Streaming SVE VL 4480
4901 12:28:19.312161 # ok 3174 # SKIP Streaming SVE set SVE get SVE for VL 4480
4902 12:28:19.312351 # ok 3175 # SKIP Streaming SVE set SVE get FPSIMD for VL 4480
4903 12:28:19.312521 # ok 3176 # SKIP Streaming SVE set FPSIMD get SVE for VL 4480
4904 12:28:19.312690 # ok 3177 Set Streaming SVE VL 4496
4905 12:28:19.312849 # ok 3178 # SKIP Streaming SVE set SVE get SVE for VL 4496
4906 12:28:19.313016 # ok 3179 # SKIP Streaming SVE set SVE get FPSIMD for VL 4496
4907 12:28:19.313181 # ok 3180 # SKIP Streaming SVE set FPSIMD get SVE for VL 4496
4908 12:28:19.313349 # ok 3181 Set Streaming SVE VL 4512
4909 12:28:19.313841 # ok 3182 # SKIP Streaming SVE set SVE get SVE for VL 4512
4910 12:28:19.314009 # ok 3183 # SKIP Streaming SVE set SVE get FPSIMD for VL 4512
4911 12:28:19.314184 # ok 3184 # SKIP Streaming SVE set FPSIMD get SVE for VL 4512
4912 12:28:19.314336 # ok 3185 Set Streaming SVE VL 4528
4913 12:28:19.314480 # ok 3186 # SKIP Streaming SVE set SVE get SVE for VL 4528
4914 12:28:19.314622 # ok 3187 # SKIP Streaming SVE set SVE get FPSIMD for VL 4528
4915 12:28:19.314765 # ok 3188 # SKIP Streaming SVE set FPSIMD get SVE for VL 4528
4916 12:28:19.314906 # ok 3189 Set Streaming SVE VL 4544
4917 12:28:19.315048 # ok 3190 # SKIP Streaming SVE set SVE get SVE for VL 4544
4918 12:28:19.315190 # ok 3191 # SKIP Streaming SVE set SVE get FPSIMD for VL 4544
4919 12:28:19.315335 # ok 3192 # SKIP Streaming SVE set FPSIMD get SVE for VL 4544
4920 12:28:19.315478 # ok 3193 Set Streaming SVE VL 4560
4921 12:28:19.328484 # ok 3194 # SKIP Streaming SVE set SVE get SVE for VL 4560
4922 12:28:19.328761 # ok 3195 # SKIP Streaming SVE set SVE get FPSIMD for VL 4560
4923 12:28:19.329063 # ok 3196 # SKIP Streaming SVE set FPSIMD get SVE for VL 4560
4924 12:28:19.329157 # ok 3197 Set Streaming SVE VL 4576
4925 12:28:19.329243 # ok 3198 # SKIP Streaming SVE set SVE get SVE for VL 4576
4926 12:28:19.329330 # ok 3199 # SKIP Streaming SVE set SVE get FPSIMD for VL 4576
4927 12:28:19.329415 # ok 3200 # SKIP Streaming SVE set FPSIMD get SVE for VL 4576
4928 12:28:19.329515 # ok 3201 Set Streaming SVE VL 4592
4929 12:28:19.329692 # ok 3202 # SKIP Streaming SVE set SVE get SVE for VL 4592
4930 12:28:19.329778 # ok 3203 # SKIP Streaming SVE set SVE get FPSIMD for VL 4592
4931 12:28:19.329888 # ok 3204 # SKIP Streaming SVE set FPSIMD get SVE for VL 4592
4932 12:28:19.329965 # ok 3205 Set Streaming SVE VL 4608
4933 12:28:19.330040 # ok 3206 # SKIP Streaming SVE set SVE get SVE for VL 4608
4934 12:28:19.330127 # ok 3207 # SKIP Streaming SVE set SVE get FPSIMD for VL 4608
4935 12:28:19.330413 # ok 3208 # SKIP Streaming SVE set FPSIMD get SVE for VL 4608
4936 12:28:19.330510 # ok 3209 Set Streaming SVE VL 4624
4937 12:28:19.330602 # ok 3210 # SKIP Streaming SVE set SVE get SVE for VL 4624
4938 12:28:19.330679 # ok 3211 # SKIP Streaming SVE set SVE get FPSIMD for VL 4624
4939 12:28:19.330763 # ok 3212 # SKIP Streaming SVE set FPSIMD get SVE for VL 4624
4940 12:28:19.330853 # ok 3213 Set Streaming SVE VL 4640
4941 12:28:19.331215 # ok 3214 # SKIP Streaming SVE set SVE get SVE for VL 4640
4942 12:28:19.331420 # ok 3215 # SKIP Streaming SVE set SVE get FPSIMD for VL 4640
4943 12:28:19.331632 # ok 3216 # SKIP Streaming SVE set FPSIMD get SVE for VL 4640
4944 12:28:19.331769 # ok 3217 Set Streaming SVE VL 4656
4945 12:28:19.331889 # ok 3218 # SKIP Streaming SVE set SVE get SVE for VL 4656
4946 12:28:19.344483 # ok 3219 # SKIP Streaming SVE set SVE get FPSIMD for VL 4656
4947 12:28:19.345041 # ok 3220 # SKIP Streaming SVE set FPSIMD get SVE for VL 4656
4948 12:28:19.345150 # ok 3221 Set Streaming SVE VL 4672
4949 12:28:19.345243 # ok 3222 # SKIP Streaming SVE set SVE get SVE for VL 4672
4950 12:28:19.345327 # ok 3223 # SKIP Streaming SVE set SVE get FPSIMD for VL 4672
4951 12:28:19.345420 # ok 3224 # SKIP Streaming SVE set FPSIMD get SVE for VL 4672
4952 12:28:19.345504 # ok 3225 Set Streaming SVE VL 4688
4953 12:28:19.345731 # ok 3226 # SKIP Streaming SVE set SVE get SVE for VL 4688
4954 12:28:19.345812 # ok 3227 # SKIP Streaming SVE set SVE get FPSIMD for VL 4688
4955 12:28:19.345902 # ok 3228 # SKIP Streaming SVE set FPSIMD get SVE for VL 4688
4956 12:28:19.345978 # ok 3229 Set Streaming SVE VL 4704
4957 12:28:19.346052 # ok 3230 # SKIP Streaming SVE set SVE get SVE for VL 4704
4958 12:28:19.346144 # ok 3231 # SKIP Streaming SVE set SVE get FPSIMD for VL 4704
4959 12:28:19.346221 # ok 3232 # SKIP Streaming SVE set FPSIMD get SVE for VL 4704
4960 12:28:19.346344 # ok 3233 Set Streaming SVE VL 4720
4961 12:28:19.346426 # ok 3234 # SKIP Streaming SVE set SVE get SVE for VL 4720
4962 12:28:19.346516 # ok 3235 # SKIP Streaming SVE set SVE get FPSIMD for VL 4720
4963 12:28:19.346594 # ok 3236 # SKIP Streaming SVE set FPSIMD get SVE for VL 4720
4964 12:28:19.346670 # ok 3237 Set Streaming SVE VL 4736
4965 12:28:19.346755 # ok 3238 # SKIP Streaming SVE set SVE get SVE for VL 4736
4966 12:28:19.346844 # ok 3239 # SKIP Streaming SVE set SVE get FPSIMD for VL 4736
4967 12:28:19.346954 # ok 3240 # SKIP Streaming SVE set FPSIMD get SVE for VL 4736
4968 12:28:19.347047 # ok 3241 Set Streaming SVE VL 4752
4969 12:28:19.347148 # ok 3242 # SKIP Streaming SVE set SVE get SVE for VL 4752
4970 12:28:19.347241 # ok 3243 # SKIP Streaming SVE set SVE get FPSIMD for VL 4752
4971 12:28:19.347564 # ok 3244 # SKIP Streaming SVE set FPSIMD get SVE for VL 4752
4972 12:28:19.347737 # ok 3245 Set Streaming SVE VL 4768
4973 12:28:19.360739 # ok 3246 # SKIP Streaming SVE set SVE get SVE for VL 4768
4974 12:28:19.361066 # ok 3247 # SKIP Streaming SVE set SVE get FPSIMD for VL 4768
4975 12:28:19.361462 # ok 3248 # SKIP Streaming SVE set FPSIMD get SVE for VL 4768
4976 12:28:19.361579 # ok 3249 Set Streaming SVE VL 4784
4977 12:28:19.361682 # ok 3250 # SKIP Streaming SVE set SVE get SVE for VL 4784
4978 12:28:19.361771 # ok 3251 # SKIP Streaming SVE set SVE get FPSIMD for VL 4784
4979 12:28:19.361858 # ok 3252 # SKIP Streaming SVE set FPSIMD get SVE for VL 4784
4980 12:28:19.361946 # ok 3253 Set Streaming SVE VL 4800
4981 12:28:19.362053 # ok 3254 # SKIP Streaming SVE set SVE get SVE for VL 4800
4982 12:28:19.362145 # ok 3255 # SKIP Streaming SVE set SVE get FPSIMD for VL 4800
4983 12:28:19.362234 # ok 3256 # SKIP Streaming SVE set FPSIMD get SVE for VL 4800
4984 12:28:19.362346 # ok 3257 Set Streaming SVE VL 4816
4985 12:28:19.362437 # ok 3258 # SKIP Streaming SVE set SVE get SVE for VL 4816
4986 12:28:19.362525 # ok 3259 # SKIP Streaming SVE set SVE get FPSIMD for VL 4816
4987 12:28:19.362614 # ok 3260 # SKIP Streaming SVE set FPSIMD get SVE for VL 4816
4988 12:28:19.362697 # ok 3261 Set Streaming SVE VL 4832
4989 12:28:19.362799 # ok 3262 # SKIP Streaming SVE set SVE get SVE for VL 4832
4990 12:28:19.362884 # ok 3263 # SKIP Streaming SVE set SVE get FPSIMD for VL 4832
4991 12:28:19.362967 # ok 3264 # SKIP Streaming SVE set FPSIMD get SVE for VL 4832
4992 12:28:19.363067 # ok 3265 Set Streaming SVE VL 4848
4993 12:28:19.363170 # ok 3266 # SKIP Streaming SVE set SVE get SVE for VL 4848
4994 12:28:19.363256 # ok 3267 # SKIP Streaming SVE set SVE get FPSIMD for VL 4848
4995 12:28:19.363359 # ok 3268 # SKIP Streaming SVE set FPSIMD get SVE for VL 4848
4996 12:28:19.363881 # ok 3269 Set Streaming SVE VL 4864
4997 12:28:19.364006 # ok 3270 # SKIP Streaming SVE set SVE get SVE for VL 4864
4998 12:28:19.372951 # ok 3271 # SKIP Streaming SVE set SVE get FPSIMD for VL 4864
4999 12:28:19.373529 # ok 3272 # SKIP Streaming SVE set FPSIMD get SVE for VL 4864
5000 12:28:19.373729 # ok 3273 Set Streaming SVE VL 4880
5001 12:28:19.373876 # ok 3274 # SKIP Streaming SVE set SVE get SVE for VL 4880
5002 12:28:19.374024 # ok 3275 # SKIP Streaming SVE set SVE get FPSIMD for VL 4880
5003 12:28:19.374173 # ok 3276 # SKIP Streaming SVE set FPSIMD get SVE for VL 4880
5004 12:28:19.374373 # ok 3277 Set Streaming SVE VL 4896
5005 12:28:19.374530 # ok 3278 # SKIP Streaming SVE set SVE get SVE for VL 4896
5006 12:28:19.374661 # ok 3279 # SKIP Streaming SVE set SVE get FPSIMD for VL 4896
5007 12:28:19.374800 # ok 3280 # SKIP Streaming SVE set FPSIMD get SVE for VL 4896
5008 12:28:19.374954 # ok 3281 Set Streaming SVE VL 4912
5009 12:28:19.375118 # ok 3282 # SKIP Streaming SVE set SVE get SVE for VL 4912
5010 12:28:19.375310 # ok 3283 # SKIP Streaming SVE set SVE get FPSIMD for VL 4912
5011 12:28:19.375464 # ok 3284 # SKIP Streaming SVE set FPSIMD get SVE for VL 4912
5012 12:28:19.375627 # ok 3285 Set Streaming SVE VL 4928
5013 12:28:19.375759 # ok 3286 # SKIP Streaming SVE set SVE get SVE for VL 4928
5014 12:28:19.375879 # ok 3287 # SKIP Streaming SVE set SVE get FPSIMD for VL 4928
5015 12:28:19.375995 # ok 3288 # SKIP Streaming SVE set FPSIMD get SVE for VL 4928
5016 12:28:19.376112 # ok 3289 Set Streaming SVE VL 4944
5017 12:28:19.376258 # ok 3290 # SKIP Streaming SVE set SVE get SVE for VL 4944
5018 12:28:19.376381 # ok 3291 # SKIP Streaming SVE set SVE get FPSIMD for VL 4944
5019 12:28:19.381261 # ok 3292 # SKIP Streaming SVE set FPSIMD get SVE for VL 4944
5020 12:28:19.381593 # ok 3293 Set Streaming SVE VL 4960
5021 12:28:19.381998 # ok 3294 # SKIP Streaming SVE set SVE get SVE for VL 4960
5022 12:28:19.382096 # ok 3295 # SKIP Streaming SVE set SVE get FPSIMD for VL 4960
5023 12:28:19.382176 # ok 3296 # SKIP Streaming SVE set FPSIMD get SVE for VL 4960
5024 12:28:19.382249 # ok 3297 Set Streaming SVE VL 4976
5025 12:28:19.382323 # ok 3298 # SKIP Streaming SVE set SVE get SVE for VL 4976
5026 12:28:19.382394 # ok 3299 # SKIP Streaming SVE set SVE get FPSIMD for VL 4976
5027 12:28:19.382480 # ok 3300 # SKIP Streaming SVE set FPSIMD get SVE for VL 4976
5028 12:28:19.382558 # ok 3301 Set Streaming SVE VL 4992
5029 12:28:19.382636 # ok 3302 # SKIP Streaming SVE set SVE get SVE for VL 4992
5030 12:28:19.382710 # ok 3303 # SKIP Streaming SVE set SVE get FPSIMD for VL 4992
5031 12:28:19.382800 # ok 3304 # SKIP Streaming SVE set FPSIMD get SVE for VL 4992
5032 12:28:19.382876 # ok 3305 Set Streaming SVE VL 5008
5033 12:28:19.382950 # ok 3306 # SKIP Streaming SVE set SVE get SVE for VL 5008
5034 12:28:19.383043 # ok 3307 # SKIP Streaming SVE set SVE get FPSIMD for VL 5008
5035 12:28:19.383122 # ok 3308 # SKIP Streaming SVE set FPSIMD get SVE for VL 5008
5036 12:28:19.383196 # ok 3309 Set Streaming SVE VL 5024
5037 12:28:19.383293 # ok 3310 # SKIP Streaming SVE set SVE get SVE for VL 5024
5038 12:28:19.383387 # ok 3311 # SKIP Streaming SVE set SVE get FPSIMD for VL 5024
5039 12:28:19.383879 # ok 3312 # SKIP Streaming SVE set FPSIMD get SVE for VL 5024
5040 12:28:19.383986 # ok 3313 Set Streaming SVE VL 5040
5041 12:28:19.384077 # ok 3314 # SKIP Streaming SVE set SVE get SVE for VL 5040
5042 12:28:19.392672 # ok 3315 # SKIP Streaming SVE set SVE get FPSIMD for VL 5040
5043 12:28:19.393150 # ok 3316 # SKIP Streaming SVE set FPSIMD get SVE for VL 5040
5044 12:28:19.393258 # ok 3317 Set Streaming SVE VL 5056
5045 12:28:19.393349 # ok 3318 # SKIP Streaming SVE set SVE get SVE for VL 5056
5046 12:28:19.393455 # ok 3319 # SKIP Streaming SVE set SVE get FPSIMD for VL 5056
5047 12:28:19.393543 # ok 3320 # SKIP Streaming SVE set FPSIMD get SVE for VL 5056
5048 12:28:19.393627 # ok 3321 Set Streaming SVE VL 5072
5049 12:28:19.393729 # ok 3322 # SKIP Streaming SVE set SVE get SVE for VL 5072
5050 12:28:19.393805 # ok 3323 # SKIP Streaming SVE set SVE get FPSIMD for VL 5072
5051 12:28:19.393890 # ok 3324 # SKIP Streaming SVE set FPSIMD get SVE for VL 5072
5052 12:28:19.393963 # ok 3325 Set Streaming SVE VL 5088
5053 12:28:19.394047 # ok 3326 # SKIP Streaming SVE set SVE get SVE for VL 5088
5054 12:28:19.394753 # ok 3327 # SKIP Streaming SVE set SVE get FPSIMD for VL 5088
5055 12:28:19.395204 # ok 3328 # SKIP Streaming SVE set FPSIMD get SVE for VL 5088
5056 12:28:19.395410 # ok 3329 Set Streaming SVE VL 5104
5057 12:28:19.395618 # ok 3330 # SKIP Streaming SVE set SVE get SVE for VL 5104
5058 12:28:19.395800 # ok 3331 # SKIP Streaming SVE set SVE get FPSIMD for VL 5104
5059 12:28:19.395965 # ok 3332 # SKIP Streaming SVE set FPSIMD get SVE for VL 5104
5060 12:28:19.396094 # ok 3333 Set Streaming SVE VL 5120
5061 12:28:19.400709 # ok 3334 # SKIP Streaming SVE set SVE get SVE for VL 5120
5062 12:28:19.401158 # ok 3335 # SKIP Streaming SVE set SVE get FPSIMD for VL 5120
5063 12:28:19.401320 # ok 3336 # SKIP Streaming SVE set FPSIMD get SVE for VL 5120
5064 12:28:19.401492 # ok 3337 Set Streaming SVE VL 5136
5065 12:28:19.401733 # ok 3338 # SKIP Streaming SVE set SVE get SVE for VL 5136
5066 12:28:19.401926 # ok 3339 # SKIP Streaming SVE set SVE get FPSIMD for VL 5136
5067 12:28:19.402089 # ok 3340 # SKIP Streaming SVE set FPSIMD get SVE for VL 5136
5068 12:28:19.402251 # ok 3341 Set Streaming SVE VL 5152
5069 12:28:19.402523 # ok 3342 # SKIP Streaming SVE set SVE get SVE for VL 5152
5070 12:28:19.402730 # ok 3343 # SKIP Streaming SVE set SVE get FPSIMD for VL 5152
5071 12:28:19.402969 # ok 3344 # SKIP Streaming SVE set FPSIMD get SVE for VL 5152
5072 12:28:19.403194 # ok 3345 Set Streaming SVE VL 5168
5073 12:28:19.403404 # ok 3346 # SKIP Streaming SVE set SVE get SVE for VL 5168
5074 12:28:19.403612 # ok 3347 # SKIP Streaming SVE set SVE get FPSIMD for VL 5168
5075 12:28:19.403807 # ok 3348 # SKIP Streaming SVE set FPSIMD get SVE for VL 5168
5076 12:28:19.404001 # ok 3349 Set Streaming SVE VL 5184
5077 12:28:19.404142 # ok 3350 # SKIP Streaming SVE set SVE get SVE for VL 5184
5078 12:28:19.404261 # ok 3351 # SKIP Streaming SVE set SVE get FPSIMD for VL 5184
5079 12:28:19.404380 # ok 3352 # SKIP Streaming SVE set FPSIMD get SVE for VL 5184
5080 12:28:19.404496 # ok 3353 Set Streaming SVE VL 5200
5081 12:28:19.404612 # ok 3354 # SKIP Streaming SVE set SVE get SVE for VL 5200
5082 12:28:19.404727 # ok 3355 # SKIP Streaming SVE set SVE get FPSIMD for VL 5200
5083 12:28:19.404841 # ok 3356 # SKIP Streaming SVE set FPSIMD get SVE for VL 5200
5084 12:28:19.404957 # ok 3357 Set Streaming SVE VL 5216
5085 12:28:19.408700 # ok 3358 # SKIP Streaming SVE set SVE get SVE for VL 5216
5086 12:28:19.408890 # ok 3359 # SKIP Streaming SVE set SVE get FPSIMD for VL 5216
5087 12:28:19.409179 # ok 3360 # SKIP Streaming SVE set FPSIMD get SVE for VL 5216
5088 12:28:19.409280 # ok 3361 Set Streaming SVE VL 5232
5089 12:28:19.409369 # ok 3362 # SKIP Streaming SVE set SVE get SVE for VL 5232
5090 12:28:19.409473 # ok 3363 # SKIP Streaming SVE set SVE get FPSIMD for VL 5232
5091 12:28:19.409690 # ok 3364 # SKIP Streaming SVE set FPSIMD get SVE for VL 5232
5092 12:28:19.409891 # ok 3365 Set Streaming SVE VL 5248
5093 12:28:19.410090 # ok 3366 # SKIP Streaming SVE set SVE get SVE for VL 5248
5094 12:28:19.410254 # ok 3367 # SKIP Streaming SVE set SVE get FPSIMD for VL 5248
5095 12:28:19.410454 # ok 3368 # SKIP Streaming SVE set FPSIMD get SVE for VL 5248
5096 12:28:19.410661 # ok 3369 Set Streaming SVE VL 5264
5097 12:28:19.410847 # ok 3370 # SKIP Streaming SVE set SVE get SVE for VL 5264
5098 12:28:19.411005 # ok 3371 # SKIP Streaming SVE set SVE get FPSIMD for VL 5264
5099 12:28:19.411178 # ok 3372 # SKIP Streaming SVE set FPSIMD get SVE for VL 5264
5100 12:28:19.411406 # ok 3373 Set Streaming SVE VL 5280
5101 12:28:19.411594 # ok 3374 # SKIP Streaming SVE set SVE get SVE for VL 5280
5102 12:28:19.411770 # ok 3375 # SKIP Streaming SVE set SVE get FPSIMD for VL 5280
5103 12:28:19.411894 # ok 3376 # SKIP Streaming SVE set FPSIMD get SVE for VL 5280
5104 12:28:19.412056 # ok 3377 Set Streaming SVE VL 5296
5105 12:28:19.412206 # ok 3378 # SKIP Streaming SVE set SVE get SVE for VL 5296
5106 12:28:19.412329 # ok 3379 # SKIP Streaming SVE set SVE get FPSIMD for VL 5296
5107 12:28:19.414833 # ok 3380 # SKIP Streaming SVE set FPSIMD get SVE for VL 5296
5108 12:28:19.415308 # ok 3381 Set Streaming SVE VL 5312
5109 12:28:19.415413 # ok 3382 # SKIP Streaming SVE set SVE get SVE for VL 5312
5110 12:28:19.415507 # ok 3383 # SKIP Streaming SVE set SVE get FPSIMD for VL 5312
5111 12:28:19.415610 # ok 3384 # SKIP Streaming SVE set FPSIMD get SVE for VL 5312
5112 12:28:19.415698 # ok 3385 Set Streaming SVE VL 5328
5113 12:28:19.415784 # ok 3386 # SKIP Streaming SVE set SVE get SVE for VL 5328
5114 12:28:19.415871 # ok 3387 # SKIP Streaming SVE set SVE get FPSIMD for VL 5328
5115 12:28:19.418660 # ok 3388 # SKIP Streaming SVE set FPSIMD get SVE for VL 5328
5116 12:28:19.419046 # ok 3389 Set Streaming SVE VL 5344
5117 12:28:19.419150 # ok 3390 # SKIP Streaming SVE set SVE get SVE for VL 5344
5118 12:28:19.419241 # ok 3391 # SKIP Streaming SVE set SVE get FPSIMD for VL 5344
5119 12:28:19.419344 # ok 3392 # SKIP Streaming SVE set FPSIMD get SVE for VL 5344
5120 12:28:19.419436 # ok 3393 Set Streaming SVE VL 5360
5121 12:28:19.419538 # ok 3394 # SKIP Streaming SVE set SVE get SVE for VL 5360
5122 12:28:19.419641 # ok 3395 # SKIP Streaming SVE set SVE get FPSIMD for VL 5360
5123 12:28:19.423393 # ok 3396 # SKIP Streaming SVE set FPSIMD get SVE for VL 5360
5124 12:28:19.423694 # ok 3397 Set Streaming SVE VL 5376
5125 12:28:19.424077 # ok 3398 # SKIP Streaming SVE set SVE get SVE for VL 5376
5126 12:28:19.424467 # ok 3399 # SKIP Streaming SVE set SVE get FPSIMD for VL 5376
5127 12:28:19.424726 # ok 3400 # SKIP Streaming SVE set FPSIMD get SVE for VL 5376
5128 12:28:19.424928 # ok 3401 Set Streaming SVE VL 5392
5129 12:28:19.425104 # ok 3402 # SKIP Streaming SVE set SVE get SVE for VL 5392
5130 12:28:19.425308 # ok 3403 # SKIP Streaming SVE set SVE get FPSIMD for VL 5392
5131 12:28:19.425513 # ok 3404 # SKIP Streaming SVE set FPSIMD get SVE for VL 5392
5132 12:28:19.425744 # ok 3405 Set Streaming SVE VL 5408
5133 12:28:19.425950 # ok 3406 # SKIP Streaming SVE set SVE get SVE for VL 5408
5134 12:28:19.426170 # ok 3407 # SKIP Streaming SVE set SVE get FPSIMD for VL 5408
5135 12:28:19.426356 # ok 3408 # SKIP Streaming SVE set FPSIMD get SVE for VL 5408
5136 12:28:19.426548 # ok 3409 Set Streaming SVE VL 5424
5137 12:28:19.426757 # ok 3410 # SKIP Streaming SVE set SVE get SVE for VL 5424
5138 12:28:19.426982 # ok 3411 # SKIP Streaming SVE set SVE get FPSIMD for VL 5424
5139 12:28:19.427177 # ok 3412 # SKIP Streaming SVE set FPSIMD get SVE for VL 5424
5140 12:28:19.427360 # ok 3413 Set Streaming SVE VL 5440
5141 12:28:19.427608 # ok 3414 # SKIP Streaming SVE set SVE get SVE for VL 5440
5142 12:28:19.427770 # ok 3415 # SKIP Streaming SVE set SVE get FPSIMD for VL 5440
5143 12:28:19.427896 # ok 3416 # SKIP Streaming SVE set FPSIMD get SVE for VL 5440
5144 12:28:19.428015 # ok 3417 Set Streaming SVE VL 5456
5145 12:28:19.428130 # ok 3418 # SKIP Streaming SVE set SVE get SVE for VL 5456
5146 12:28:19.428245 # ok 3419 # SKIP Streaming SVE set SVE get FPSIMD for VL 5456
5147 12:28:19.428360 # ok 3420 # SKIP Streaming SVE set FPSIMD get SVE for VL 5456
5148 12:28:19.428475 # ok 3421 Set Streaming SVE VL 5472
5149 12:28:19.428596 # ok 3422 # SKIP Streaming SVE set SVE get SVE for VL 5472
5150 12:28:19.428739 # ok 3423 # SKIP Streaming SVE set SVE get FPSIMD for VL 5472
5151 12:28:19.428861 # ok 3424 # SKIP Streaming SVE set FPSIMD get SVE for VL 5472
5152 12:28:19.430480 # ok 3425 Set Streaming SVE VL 5488
5153 12:28:19.430864 # ok 3426 # SKIP Streaming SVE set SVE get SVE for VL 5488
5154 12:28:19.430978 # ok 3427 # SKIP Streaming SVE set SVE get FPSIMD for VL 5488
5155 12:28:19.431068 # ok 3428 # SKIP Streaming SVE set FPSIMD get SVE for VL 5488
5156 12:28:19.431164 # ok 3429 Set Streaming SVE VL 5504
5157 12:28:19.431244 # ok 3430 # SKIP Streaming SVE set SVE get SVE for VL 5504
5158 12:28:19.431346 # ok 3431 # SKIP Streaming SVE set SVE get FPSIMD for VL 5504
5159 12:28:19.431640 # ok 3432 # SKIP Streaming SVE set FPSIMD get SVE for VL 5504
5160 12:28:19.431816 # ok 3433 Set Streaming SVE VL 5520
5161 12:28:19.436642 # ok 3434 # SKIP Streaming SVE set SVE get SVE for VL 5520
5162 12:28:19.437004 # ok 3435 # SKIP Streaming SVE set SVE get FPSIMD for VL 5520
5163 12:28:19.437494 # ok 3436 # SKIP Streaming SVE set FPSIMD get SVE for VL 5520
5164 12:28:19.437703 # ok 3437 Set Streaming SVE VL 5536
5165 12:28:19.437858 # ok 3438 # SKIP Streaming SVE set SVE get SVE for VL 5536
5166 12:28:19.438073 # ok 3439 # SKIP Streaming SVE set SVE get FPSIMD for VL 5536
5167 12:28:19.438254 # ok 3440 # SKIP Streaming SVE set FPSIMD get SVE for VL 5536
5168 12:28:19.438409 # ok 3441 Set Streaming SVE VL 5552
5169 12:28:19.438570 # ok 3442 # SKIP Streaming SVE set SVE get SVE for VL 5552
5170 12:28:19.438812 # ok 3443 # SKIP Streaming SVE set SVE get FPSIMD for VL 5552
5171 12:28:19.438996 # ok 3444 # SKIP Streaming SVE set FPSIMD get SVE for VL 5552
5172 12:28:19.439152 # ok 3445 Set Streaming SVE VL 5568
5173 12:28:19.439298 # ok 3446 # SKIP Streaming SVE set SVE get SVE for VL 5568
5174 12:28:19.439493 # ok 3447 # SKIP Streaming SVE set SVE get FPSIMD for VL 5568
5175 12:28:19.439672 # ok 3448 # SKIP Streaming SVE set FPSIMD get SVE for VL 5568
5176 12:28:19.439826 # ok 3449 Set Streaming SVE VL 5584
5177 12:28:19.439947 # ok 3450 # SKIP Streaming SVE set SVE get SVE for VL 5584
5178 12:28:19.440063 # ok 3451 # SKIP Streaming SVE set SVE get FPSIMD for VL 5584
5179 12:28:19.440210 # ok 3452 # SKIP Streaming SVE set FPSIMD get SVE for VL 5584
5180 12:28:19.440334 # ok 3453 Set Streaming SVE VL 5600
5181 12:28:19.440451 # ok 3454 # SKIP Streaming SVE set SVE get SVE for VL 5600
5182 12:28:19.440568 # ok 3455 # SKIP Streaming SVE set SVE get FPSIMD for VL 5600
5183 12:28:19.440683 # ok 3456 # SKIP Streaming SVE set FPSIMD get SVE for VL 5600
5184 12:28:19.440796 # ok 3457 Set Streaming SVE VL 5616
5185 12:28:19.440911 # ok 3458 # SKIP Streaming SVE set SVE get SVE for VL 5616
5186 12:28:19.444933 # ok 3459 # SKIP Streaming SVE set SVE get FPSIMD for VL 5616
5187 12:28:19.445373 # ok 3460 # SKIP Streaming SVE set FPSIMD get SVE for VL 5616
5188 12:28:19.445480 # ok 3461 Set Streaming SVE VL 5632
5189 12:28:19.445639 # ok 3462 # SKIP Streaming SVE set SVE get SVE for VL 5632
5190 12:28:19.445744 # ok 3463 # SKIP Streaming SVE set SVE get FPSIMD for VL 5632
5191 12:28:19.445850 # ok 3464 # SKIP Streaming SVE set FPSIMD get SVE for VL 5632
5192 12:28:19.445940 # ok 3465 Set Streaming SVE VL 5648
5193 12:28:19.446029 # ok 3466 # SKIP Streaming SVE set SVE get SVE for VL 5648
5194 12:28:19.446133 # ok 3467 # SKIP Streaming SVE set SVE get FPSIMD for VL 5648
5195 12:28:19.446223 # ok 3468 # SKIP Streaming SVE set FPSIMD get SVE for VL 5648
5196 12:28:19.446531 # ok 3469 Set Streaming SVE VL 5664
5197 12:28:19.446638 # ok 3470 # SKIP Streaming SVE set SVE get SVE for VL 5664
5198 12:28:19.446729 # ok 3471 # SKIP Streaming SVE set SVE get FPSIMD for VL 5664
5199 12:28:19.446818 # ok 3472 # SKIP Streaming SVE set FPSIMD get SVE for VL 5664
5200 12:28:19.446922 # ok 3473 Set Streaming SVE VL 5680
5201 12:28:19.447008 # ok 3474 # SKIP Streaming SVE set SVE get SVE for VL 5680
5202 12:28:19.447091 # ok 3475 # SKIP Streaming SVE set SVE get FPSIMD for VL 5680
5203 12:28:19.447786 # ok 3476 # SKIP Streaming SVE set FPSIMD get SVE for VL 5680
5204 12:28:19.456772 # ok 3477 Set Streaming SVE VL 5696
5205 12:28:19.457307 # ok 3478 # SKIP Streaming SVE set SVE get SVE for VL 5696
5206 12:28:19.457422 # ok 3479 # SKIP Streaming SVE set SVE get FPSIMD for VL 5696
5207 12:28:19.457510 # ok 3480 # SKIP Streaming SVE set FPSIMD get SVE for VL 5696
5208 12:28:19.457596 # ok 3481 Set Streaming SVE VL 5712
5209 12:28:19.457695 # ok 3482 # SKIP Streaming SVE set SVE get SVE for VL 5712
5210 12:28:19.457797 # ok 3483 # SKIP Streaming SVE set SVE get FPSIMD for VL 5712
5211 12:28:19.457882 # ok 3484 # SKIP Streaming SVE set FPSIMD get SVE for VL 5712
5212 12:28:19.457962 # ok 3485 Set Streaming SVE VL 5728
5213 12:28:19.458057 # ok 3486 # SKIP Streaming SVE set SVE get SVE for VL 5728
5214 12:28:19.458141 # ok 3487 # SKIP Streaming SVE set SVE get FPSIMD for VL 5728
5215 12:28:19.458222 # ok 3488 # SKIP Streaming SVE set FPSIMD get SVE for VL 5728
5216 12:28:19.458318 # ok 3489 Set Streaming SVE VL 5744
5217 12:28:19.458401 # ok 3490 # SKIP Streaming SVE set SVE get SVE for VL 5744
5218 12:28:19.458498 # ok 3491 # SKIP Streaming SVE set SVE get FPSIMD for VL 5744
5219 12:28:19.458599 # ok 3492 # SKIP Streaming SVE set FPSIMD get SVE for VL 5744
5220 12:28:19.458696 # ok 3493 Set Streaming SVE VL 5760
5221 12:28:19.459116 # ok 3494 # SKIP Streaming SVE set SVE get SVE for VL 5760
5222 12:28:19.459372 # ok 3495 # SKIP Streaming SVE set SVE get FPSIMD for VL 5760
5223 12:28:19.459564 # ok 3496 # SKIP Streaming SVE set FPSIMD get SVE for VL 5760
5224 12:28:19.459711 # ok 3497 Set Streaming SVE VL 5776
5225 12:28:19.459857 # ok 3498 # SKIP Streaming SVE set SVE get SVE for VL 5776
5226 12:28:19.459981 # ok 3499 # SKIP Streaming SVE set SVE get FPSIMD for VL 5776
5227 12:28:19.460097 # ok 3500 # SKIP Streaming SVE set FPSIMD get SVE for VL 5776
5228 12:28:19.465548 # ok 3501 Set Streaming SVE VL 5792
5229 12:28:19.465790 # ok 3502 # SKIP Streaming SVE set SVE get SVE for VL 5792
5230 12:28:19.466082 # ok 3503 # SKIP Streaming SVE set SVE get FPSIMD for VL 5792
5231 12:28:19.466180 # ok 3504 # SKIP Streaming SVE set FPSIMD get SVE for VL 5792
5232 12:28:19.466259 # ok 3505 Set Streaming SVE VL 5808
5233 12:28:19.466348 # ok 3506 # SKIP Streaming SVE set SVE get SVE for VL 5808
5234 12:28:19.466425 # ok 3507 # SKIP Streaming SVE set SVE get FPSIMD for VL 5808
5235 12:28:19.466509 # ok 3508 # SKIP Streaming SVE set FPSIMD get SVE for VL 5808
5236 12:28:19.466584 # ok 3509 Set Streaming SVE VL 5824
5237 12:28:19.466679 # ok 3510 # SKIP Streaming SVE set SVE get SVE for VL 5824
5238 12:28:19.466770 # ok 3511 # SKIP Streaming SVE set SVE get FPSIMD for VL 5824
5239 12:28:19.466869 # ok 3512 # SKIP Streaming SVE set FPSIMD get SVE for VL 5824
5240 12:28:19.466964 # ok 3513 Set Streaming SVE VL 5840
5241 12:28:19.467261 # ok 3514 # SKIP Streaming SVE set SVE get SVE for VL 5840
5242 12:28:19.467358 # ok 3515 # SKIP Streaming SVE set SVE get FPSIMD for VL 5840
5243 12:28:19.467450 # ok 3516 # SKIP Streaming SVE set FPSIMD get SVE for VL 5840
5244 12:28:19.467539 # ok 3517 Set Streaming SVE VL 5856
5245 12:28:19.476355 # ok 3518 # SKIP Streaming SVE set SVE get SVE for VL 5856
5246 12:28:19.476820 # ok 3519 # SKIP Streaming SVE set SVE get FPSIMD for VL 5856
5247 12:28:19.476924 # ok 3520 # SKIP Streaming SVE set FPSIMD get SVE for VL 5856
5248 12:28:19.477006 # ok 3521 Set Streaming SVE VL 5872
5249 12:28:19.477082 # ok 3522 # SKIP Streaming SVE set SVE get SVE for VL 5872
5250 12:28:19.477173 # ok 3523 # SKIP Streaming SVE set SVE get FPSIMD for VL 5872
5251 12:28:19.477250 # ok 3524 # SKIP Streaming SVE set FPSIMD get SVE for VL 5872
5252 12:28:19.477322 # ok 3525 Set Streaming SVE VL 5888
5253 12:28:19.477407 # ok 3526 # SKIP Streaming SVE set SVE get SVE for VL 5888
5254 12:28:19.477495 # ok 3527 # SKIP Streaming SVE set SVE get FPSIMD for VL 5888
5255 12:28:19.477769 # ok 3528 # SKIP Streaming SVE set FPSIMD get SVE for VL 5888
5256 12:28:19.477865 # ok 3529 Set Streaming SVE VL 5904
5257 12:28:19.477955 # ok 3530 # SKIP Streaming SVE set SVE get SVE for VL 5904
5258 12:28:19.478044 # ok 3531 # SKIP Streaming SVE set SVE get FPSIMD for VL 5904
5259 12:28:19.478333 # ok 3532 # SKIP Streaming SVE set FPSIMD get SVE for VL 5904
5260 12:28:19.478429 # ok 3533 Set Streaming SVE VL 5920
5261 12:28:19.478507 # ok 3534 # SKIP Streaming SVE set SVE get SVE for VL 5920
5262 12:28:19.478597 # ok 3535 # SKIP Streaming SVE set SVE get FPSIMD for VL 5920
5263 12:28:19.478674 # ok 3536 # SKIP Streaming SVE set FPSIMD get SVE for VL 5920
5264 12:28:19.478761 # ok 3537 Set Streaming SVE VL 5936
5265 12:28:19.478848 # ok 3538 # SKIP Streaming SVE set SVE get SVE for VL 5936
5266 12:28:19.479151 # ok 3539 # SKIP Streaming SVE set SVE get FPSIMD for VL 5936
5267 12:28:19.479255 # ok 3540 # SKIP Streaming SVE set FPSIMD get SVE for VL 5936
5268 12:28:19.479345 # ok 3541 Set Streaming SVE VL 5952
5269 12:28:19.479449 # ok 3542 # SKIP Streaming SVE set SVE get SVE for VL 5952
5270 12:28:19.479541 # ok 3543 # SKIP Streaming SVE set SVE get FPSIMD for VL 5952
5271 12:28:19.479642 # ok 3544 # SKIP Streaming SVE set FPSIMD get SVE for VL 5952
5272 12:28:19.479731 # ok 3545 Set Streaming SVE VL 5968
5273 12:28:19.492655 # ok 3546 # SKIP Streaming SVE set SVE get SVE for VL 5968
5274 12:28:19.493202 # ok 3547 # SKIP Streaming SVE set SVE get FPSIMD for VL 5968
5275 12:28:19.493387 # ok 3548 # SKIP Streaming SVE set FPSIMD get SVE for VL 5968
5276 12:28:19.493558 # ok 3549 Set Streaming SVE VL 5984
5277 12:28:19.493731 # ok 3550 # SKIP Streaming SVE set SVE get SVE for VL 5984
5278 12:28:19.493928 # ok 3551 # SKIP Streaming SVE set SVE get FPSIMD for VL 5984
5279 12:28:19.494098 # ok 3552 # SKIP Streaming SVE set FPSIMD get SVE for VL 5984
5280 12:28:19.494257 # ok 3553 Set Streaming SVE VL 6000
5281 12:28:19.494410 # ok 3554 # SKIP Streaming SVE set SVE get SVE for VL 6000
5282 12:28:19.494564 # ok 3555 # SKIP Streaming SVE set SVE get FPSIMD for VL 6000
5283 12:28:19.494762 # ok 3556 # SKIP Streaming SVE set FPSIMD get SVE for VL 6000
5284 12:28:19.494926 # ok 3557 Set Streaming SVE VL 6016
5285 12:28:19.495080 # ok 3558 # SKIP Streaming SVE set SVE get SVE for VL 6016
5286 12:28:19.495230 # ok 3559 # SKIP Streaming SVE set SVE get FPSIMD for VL 6016
5287 12:28:19.495385 # ok 3560 # SKIP Streaming SVE set FPSIMD get SVE for VL 6016
5288 12:28:19.495514 # ok 3561 Set Streaming SVE VL 6032
5289 12:28:19.495641 # ok 3562 # SKIP Streaming SVE set SVE get SVE for VL 6032
5290 12:28:19.495796 # ok 3563 # SKIP Streaming SVE set SVE get FPSIMD for VL 6032
5291 12:28:19.495924 # ok 3564 # SKIP Streaming SVE set FPSIMD get SVE for VL 6032
5292 12:28:19.496042 # ok 3565 Set Streaming SVE VL 6048
5293 12:28:19.496156 # ok 3566 # SKIP Streaming SVE set SVE get SVE for VL 6048
5294 12:28:19.496269 # ok 3567 # SKIP Streaming SVE set SVE get FPSIMD for VL 6048
5295 12:28:19.496381 # ok 3568 # SKIP Streaming SVE set FPSIMD get SVE for VL 6048
5296 12:28:19.496493 # ok 3569 Set Streaming SVE VL 6064
5297 12:28:19.496604 # ok 3570 # SKIP Streaming SVE set SVE get SVE for VL 6064
5298 12:28:19.504508 # ok 3571 # SKIP Streaming SVE set SVE get FPSIMD for VL 6064
5299 12:28:19.504870 # ok 3572 # SKIP Streaming SVE set FPSIMD get SVE for VL 6064
5300 12:28:19.505316 # ok 3573 Set Streaming SVE VL 6080
5301 12:28:19.505457 # ok 3574 # SKIP Streaming SVE set SVE get SVE for VL 6080
5302 12:28:19.505670 # ok 3575 # SKIP Streaming SVE set SVE get FPSIMD for VL 6080
5303 12:28:19.505756 # ok 3576 # SKIP Streaming SVE set FPSIMD get SVE for VL 6080
5304 12:28:19.505831 # ok 3577 Set Streaming SVE VL 6096
5305 12:28:19.505906 # ok 3578 # SKIP Streaming SVE set SVE get SVE for VL 6096
5306 12:28:19.505994 # ok 3579 # SKIP Streaming SVE set SVE get FPSIMD for VL 6096
5307 12:28:19.506069 # ok 3580 # SKIP Streaming SVE set FPSIMD get SVE for VL 6096
5308 12:28:19.506155 # ok 3581 Set Streaming SVE VL 6112
5309 12:28:19.506229 # ok 3582 # SKIP Streaming SVE set SVE get SVE for VL 6112
5310 12:28:19.506422 # ok 3583 # SKIP Streaming SVE set SVE get FPSIMD for VL 6112
5311 12:28:19.506509 # ok 3584 # SKIP Streaming SVE set FPSIMD get SVE for VL 6112
5312 12:28:19.506598 # ok 3585 Set Streaming SVE VL 6128
5313 12:28:19.506675 # ok 3586 # SKIP Streaming SVE set SVE get SVE for VL 6128
5314 12:28:19.506746 # ok 3587 # SKIP Streaming SVE set SVE get FPSIMD for VL 6128
5315 12:28:19.506835 # ok 3588 # SKIP Streaming SVE set FPSIMD get SVE for VL 6128
5316 12:28:19.506924 # ok 3589 Set Streaming SVE VL 6144
5317 12:28:19.507209 # ok 3590 # SKIP Streaming SVE set SVE get SVE for VL 6144
5318 12:28:19.507304 # ok 3591 # SKIP Streaming SVE set SVE get FPSIMD for VL 6144
5319 12:28:19.507398 # ok 3592 # SKIP Streaming SVE set FPSIMD get SVE for VL 6144
5320 12:28:19.507552 # ok 3593 Set Streaming SVE VL 6160
5321 12:28:19.507815 # ok 3594 # SKIP Streaming SVE set SVE get SVE for VL 6160
5322 12:28:19.512625 # ok 3595 # SKIP Streaming SVE set SVE get FPSIMD for VL 6160
5323 12:28:19.513064 # ok 3596 # SKIP Streaming SVE set FPSIMD get SVE for VL 6160
5324 12:28:19.513154 # ok 3597 Set Streaming SVE VL 6176
5325 12:28:19.513253 # ok 3598 # SKIP Streaming SVE set SVE get SVE for VL 6176
5326 12:28:19.513352 # ok 3599 # SKIP Streaming SVE set SVE get FPSIMD for VL 6176
5327 12:28:19.513452 # ok 3600 # SKIP Streaming SVE set FPSIMD get SVE for VL 6176
5328 12:28:19.513682 # ok 3601 Set Streaming SVE VL 6192
5329 12:28:19.513771 # ok 3602 # SKIP Streaming SVE set SVE get SVE for VL 6192
5330 12:28:19.513858 # ok 3603 # SKIP Streaming SVE set SVE get FPSIMD for VL 6192
5331 12:28:19.514137 # ok 3604 # SKIP Streaming SVE set FPSIMD get SVE for VL 6192
5332 12:28:19.514219 # ok 3605 Set Streaming SVE VL 6208
5333 12:28:19.514352 # ok 3606 # SKIP Streaming SVE set SVE get SVE for VL 6208
5334 12:28:19.514633 # ok 3607 # SKIP Streaming SVE set SVE get FPSIMD for VL 6208
5335 12:28:19.514742 # ok 3608 # SKIP Streaming SVE set FPSIMD get SVE for VL 6208
5336 12:28:19.515017 # ok 3609 Set Streaming SVE VL 6224
5337 12:28:19.515114 # ok 3610 # SKIP Streaming SVE set SVE get SVE for VL 6224
5338 12:28:19.515208 # ok 3611 # SKIP Streaming SVE set SVE get FPSIMD for VL 6224
5339 12:28:19.515487 # ok 3612 # SKIP Streaming SVE set FPSIMD get SVE for VL 6224
5340 12:28:19.515574 # ok 3613 Set Streaming SVE VL 6240
5341 12:28:19.515763 # ok 3614 # SKIP Streaming SVE set SVE get SVE for VL 6240
5342 12:28:19.520648 # ok 3615 # SKIP Streaming SVE set SVE get FPSIMD for VL 6240
5343 12:28:19.521115 # ok 3616 # SKIP Streaming SVE set FPSIMD get SVE for VL 6240
5344 12:28:19.521315 # ok 3617 Set Streaming SVE VL 6256
5345 12:28:19.521487 # ok 3618 # SKIP Streaming SVE set SVE get SVE for VL 6256
5346 12:28:19.521698 # ok 3619 # SKIP Streaming SVE set SVE get FPSIMD for VL 6256
5347 12:28:19.521956 # ok 3620 # SKIP Streaming SVE set FPSIMD get SVE for VL 6256
5348 12:28:19.522183 # ok 3621 Set Streaming SVE VL 6272
5349 12:28:19.522396 # ok 3622 # SKIP Streaming SVE set SVE get SVE for VL 6272
5350 12:28:19.522551 # ok 3623 # SKIP Streaming SVE set SVE get FPSIMD for VL 6272
5351 12:28:19.522702 # ok 3624 # SKIP Streaming SVE set FPSIMD get SVE for VL 6272
5352 12:28:19.522865 # ok 3625 Set Streaming SVE VL 6288
5353 12:28:19.523484 # ok 3626 # SKIP Streaming SVE set SVE get SVE for VL 6288
5354 12:28:19.523687 # ok 3627 # SKIP Streaming SVE set SVE get FPSIMD for VL 6288
5355 12:28:19.531593 # ok 3628 # SKIP Streaming SVE set FPSIMD get SVE for VL 6288
5356 12:28:19.533062 # ok 3629 Set Streaming SVE VL 6304
5357 12:28:19.533401 # ok 3630 # SKIP Streaming SVE set SVE get SVE for VL 6304
5358 12:28:19.533572 # ok 3631 # SKIP Streaming SVE set SVE get FPSIMD for VL 6304
5359 12:28:19.533686 # ok 3632 # SKIP Streaming SVE set FPSIMD get SVE for VL 6304
5360 12:28:19.534049 # ok 3633 Set Streaming SVE VL 6320
5361 12:28:19.534146 # ok 3634 # SKIP Streaming SVE set SVE get SVE for VL 6320
5362 12:28:19.534308 # ok 3635 # SKIP Streaming SVE set SVE get FPSIMD for VL 6320
5363 12:28:19.534420 # ok 3636 # SKIP Streaming SVE set FPSIMD get SVE for VL 6320
5364 12:28:19.534500 # ok 3637 Set Streaming SVE VL 6336
5365 12:28:19.534585 # ok 3638 # SKIP Streaming SVE set SVE get SVE for VL 6336
5366 12:28:19.534857 # ok 3639 # SKIP Streaming SVE set SVE get FPSIMD for VL 6336
5367 12:28:19.534956 # ok 3640 # SKIP Streaming SVE set FPSIMD get SVE for VL 6336
5368 12:28:19.535107 # ok 3641 Set Streaming SVE VL 6352
5369 12:28:19.535218 # ok 3642 # SKIP Streaming SVE set SVE get SVE for VL 6352
5370 12:28:19.535304 # ok 3643 # SKIP Streaming SVE set SVE get FPSIMD for VL 6352
5371 12:28:19.535611 # ok 3644 # SKIP Streaming SVE set FPSIMD get SVE for VL 6352
5372 12:28:19.535711 # ok 3645 Set Streaming SVE VL 6368
5373 12:28:19.535802 # ok 3646 # SKIP Streaming SVE set SVE get SVE for VL 6368
5374 12:28:19.535892 # ok 3647 # SKIP Streaming SVE set SVE get FPSIMD for VL 6368
5375 12:28:19.542520 # ok 3648 # SKIP Streaming SVE set FPSIMD get SVE for VL 6368
5376 12:28:19.542948 # ok 3649 Set Streaming SVE VL 6384
5377 12:28:19.543144 # ok 3650 # SKIP Streaming SVE set SVE get SVE for VL 6384
5378 12:28:19.543331 # ok 3651 # SKIP Streaming SVE set SVE get FPSIMD for VL 6384
5379 12:28:19.543732 # ok 3652 # SKIP Streaming SVE set FPSIMD get SVE for VL 6384
5380 12:28:19.549549 # ok 3653 Set Streaming SVE VL 6400
5381 12:28:19.550162 # ok 3654 # SKIP Streaming SVE set SVE get SVE for VL 6400
5382 12:28:19.550467 # ok 3655 # SKIP Streaming SVE set SVE get FPSIMD for VL 6400
5383 12:28:19.550562 # ok 3656 # SKIP Streaming SVE set FPSIMD get SVE for VL 6400
5384 12:28:19.550657 # ok 3657 Set Streaming SVE VL 6416
5385 12:28:19.550952 # ok 3658 # SKIP Streaming SVE set SVE get SVE for VL 6416
5386 12:28:19.551176 # ok 3659 # SKIP Streaming SVE set SVE get FPSIMD for VL 6416
5387 12:28:19.551321 # ok 3660 # SKIP Streaming SVE set FPSIMD get SVE for VL 6416
5388 12:28:19.551440 # ok 3661 Set Streaming SVE VL 6432
5389 12:28:19.551579 # ok 3662 # SKIP Streaming SVE set SVE get SVE for VL 6432
5390 12:28:19.558091 # ok 3663 # SKIP Streaming SVE set SVE get FPSIMD for VL 6432
5391 12:28:19.558634 # ok 3664 # SKIP Streaming SVE set FPSIMD get SVE for VL 6432
5392 12:28:19.558814 # ok 3665 Set Streaming SVE VL 6448
5393 12:28:19.558980 # ok 3666 # SKIP Streaming SVE set SVE get SVE for VL 6448
5394 12:28:19.559190 # ok 3667 # SKIP Streaming SVE set SVE get FPSIMD for VL 6448
5395 12:28:19.559366 # ok 3668 # SKIP Streaming SVE set FPSIMD get SVE for VL 6448
5396 12:28:19.559542 # ok 3669 Set Streaming SVE VL 6464
5397 12:28:19.559705 # ok 3670 # SKIP Streaming SVE set SVE get SVE for VL 6464
5398 12:28:19.559862 # ok 3671 # SKIP Streaming SVE set SVE get FPSIMD for VL 6464
5399 12:28:19.559984 # ok 3672 # SKIP Streaming SVE set FPSIMD get SVE for VL 6464
5400 12:28:19.560100 # ok 3673 Set Streaming SVE VL 6480
5401 12:28:19.560215 # ok 3674 # SKIP Streaming SVE set SVE get SVE for VL 6480
5402 12:28:19.565067 # ok 3675 # SKIP Streaming SVE set SVE get FPSIMD for VL 6480
5403 12:28:19.565664 # ok 3676 # SKIP Streaming SVE set FPSIMD get SVE for VL 6480
5404 12:28:19.565998 # ok 3677 Set Streaming SVE VL 6496
5405 12:28:19.566112 # ok 3678 # SKIP Streaming SVE set SVE get SVE for VL 6496
5406 12:28:19.566207 # ok 3679 # SKIP Streaming SVE set SVE get FPSIMD for VL 6496
5407 12:28:19.566311 # ok 3680 # SKIP Streaming SVE set FPSIMD get SVE for VL 6496
5408 12:28:19.566398 # ok 3681 Set Streaming SVE VL 6512
5409 12:28:19.566620 # ok 3682 # SKIP Streaming SVE set SVE get SVE for VL 6512
5410 12:28:19.566716 # ok 3683 # SKIP Streaming SVE set SVE get FPSIMD for VL 6512
5411 12:28:19.566818 # ok 3684 # SKIP Streaming SVE set FPSIMD get SVE for VL 6512
5412 12:28:19.566906 # ok 3685 Set Streaming SVE VL 6528
5413 12:28:19.567202 # ok 3686 # SKIP Streaming SVE set SVE get SVE for VL 6528
5414 12:28:19.567289 # ok 3687 # SKIP Streaming SVE set SVE get FPSIMD for VL 6528
5415 12:28:19.567361 # ok 3688 # SKIP Streaming SVE set FPSIMD get SVE for VL 6528
5416 12:28:19.567468 # ok 3689 Set Streaming SVE VL 6544
5417 12:28:19.567541 # ok 3690 # SKIP Streaming SVE set SVE get SVE for VL 6544
5418 12:28:19.567620 # ok 3691 # SKIP Streaming SVE set SVE get FPSIMD for VL 6544
5419 12:28:19.567721 # ok 3692 # SKIP Streaming SVE set FPSIMD get SVE for VL 6544
5420 12:28:19.567818 # ok 3693 Set Streaming SVE VL 6560
5421 12:28:19.575869 # ok 3694 # SKIP Streaming SVE set SVE get SVE for VL 6560
5422 12:28:19.577305 # ok 3695 # SKIP Streaming SVE set SVE get FPSIMD for VL 6560
5423 12:28:19.577453 # ok 3696 # SKIP Streaming SVE set FPSIMD get SVE for VL 6560
5424 12:28:19.577541 # ok 3697 Set Streaming SVE VL 6576
5425 12:28:19.577641 # ok 3698 # SKIP Streaming SVE set SVE get SVE for VL 6576
5426 12:28:19.577737 # ok 3699 # SKIP Streaming SVE set SVE get FPSIMD for VL 6576
5427 12:28:19.578524 # ok 3700 # SKIP Streaming SVE set FPSIMD get SVE for VL 6576
5428 12:28:19.578866 # ok 3701 Set Streaming SVE VL 6592
5429 12:28:19.578971 # ok 3702 # SKIP Streaming SVE set SVE get SVE for VL 6592
5430 12:28:19.579079 # ok 3703 # SKIP Streaming SVE set SVE get FPSIMD for VL 6592
5431 12:28:19.579169 # ok 3704 # SKIP Streaming SVE set FPSIMD get SVE for VL 6592
5432 12:28:19.579275 # ok 3705 Set Streaming SVE VL 6608
5433 12:28:19.579382 # ok 3706 # SKIP Streaming SVE set SVE get SVE for VL 6608
5434 12:28:19.579488 # ok 3707 # SKIP Streaming SVE set SVE get FPSIMD for VL 6608
5435 12:28:19.579594 # ok 3708 # SKIP Streaming SVE set FPSIMD get SVE for VL 6608
5436 12:28:19.579908 # ok 3709 Set Streaming SVE VL 6624
5437 12:28:19.584677 # ok 3710 # SKIP Streaming SVE set SVE get SVE for VL 6624
5438 12:28:19.585163 # ok 3711 # SKIP Streaming SVE set SVE get FPSIMD for VL 6624
5439 12:28:19.585487 # ok 3712 # SKIP Streaming SVE set FPSIMD get SVE for VL 6624
5440 12:28:19.585599 # ok 3713 Set Streaming SVE VL 6640
5441 12:28:19.585687 # ok 3714 # SKIP Streaming SVE set SVE get SVE for VL 6640
5442 12:28:19.585967 # ok 3715 # SKIP Streaming SVE set SVE get FPSIMD for VL 6640
5443 12:28:19.586062 # ok 3716 # SKIP Streaming SVE set FPSIMD get SVE for VL 6640
5444 12:28:19.586151 # ok 3717 Set Streaming SVE VL 6656
5445 12:28:19.586240 # ok 3718 # SKIP Streaming SVE set SVE get SVE for VL 6656
5446 12:28:19.586337 # ok 3719 # SKIP Streaming SVE set SVE get FPSIMD for VL 6656
5447 12:28:19.586626 # ok 3720 # SKIP Streaming SVE set FPSIMD get SVE for VL 6656
5448 12:28:19.586722 # ok 3721 Set Streaming SVE VL 6672
5449 12:28:19.586811 # ok 3722 # SKIP Streaming SVE set SVE get SVE for VL 6672
5450 12:28:19.586909 # ok 3723 # SKIP Streaming SVE set SVE get FPSIMD for VL 6672
5451 12:28:19.586997 # ok 3724 # SKIP Streaming SVE set FPSIMD get SVE for VL 6672
5452 12:28:19.587090 # ok 3725 Set Streaming SVE VL 6688
5453 12:28:19.587377 # ok 3726 # SKIP Streaming SVE set SVE get SVE for VL 6688
5454 12:28:19.587475 # ok 3727 # SKIP Streaming SVE set SVE get FPSIMD for VL 6688
5455 12:28:19.587575 # ok 3728 # SKIP Streaming SVE set FPSIMD get SVE for VL 6688
5456 12:28:19.587673 # ok 3729 Set Streaming SVE VL 6704
5457 12:28:19.587773 # ok 3730 # SKIP Streaming SVE set SVE get SVE for VL 6704
5458 12:28:19.597006 # ok 3731 # SKIP Streaming SVE set SVE get FPSIMD for VL 6704
5459 12:28:19.597468 # ok 3732 # SKIP Streaming SVE set FPSIMD get SVE for VL 6704
5460 12:28:19.597577 # ok 3733 Set Streaming SVE VL 6720
5461 12:28:19.597678 # ok 3734 # SKIP Streaming SVE set SVE get SVE for VL 6720
5462 12:28:19.597768 # ok 3735 # SKIP Streaming SVE set SVE get FPSIMD for VL 6720
5463 12:28:19.597877 # ok 3736 # SKIP Streaming SVE set FPSIMD get SVE for VL 6720
5464 12:28:19.597969 # ok 3737 Set Streaming SVE VL 6736
5465 12:28:19.598258 # ok 3738 # SKIP Streaming SVE set SVE get SVE for VL 6736
5466 12:28:19.598546 # ok 3739 # SKIP Streaming SVE set SVE get FPSIMD for VL 6736
5467 12:28:19.598647 # ok 3740 # SKIP Streaming SVE set FPSIMD get SVE for VL 6736
5468 12:28:19.598751 # ok 3741 Set Streaming SVE VL 6752
5469 12:28:19.598842 # ok 3742 # SKIP Streaming SVE set SVE get SVE for VL 6752
5470 12:28:19.598947 # ok 3743 # SKIP Streaming SVE set SVE get FPSIMD for VL 6752
5471 12:28:19.599054 # ok 3744 # SKIP Streaming SVE set FPSIMD get SVE for VL 6752
5472 12:28:19.599388 # ok 3745 Set Streaming SVE VL 6768
5473 12:28:19.599530 # ok 3746 # SKIP Streaming SVE set SVE get SVE for VL 6768
5474 12:28:19.599675 # ok 3747 # SKIP Streaming SVE set SVE get FPSIMD for VL 6768
5475 12:28:19.600020 # ok 3748 # SKIP Streaming SVE set FPSIMD get SVE for VL 6768
5476 12:28:19.600162 # ok 3749 Set Streaming SVE VL 6784
5477 12:28:19.605524 # ok 3750 # SKIP Streaming SVE set SVE get SVE for VL 6784
5478 12:28:19.605946 # ok 3751 # SKIP Streaming SVE set SVE get FPSIMD for VL 6784
5479 12:28:19.606038 # ok 3752 # SKIP Streaming SVE set FPSIMD get SVE for VL 6784
5480 12:28:19.606143 # ok 3753 Set Streaming SVE VL 6800
5481 12:28:19.606253 # ok 3754 # SKIP Streaming SVE set SVE get SVE for VL 6800
5482 12:28:19.606394 # ok 3755 # SKIP Streaming SVE set SVE get FPSIMD for VL 6800
5483 12:28:19.606501 # ok 3756 # SKIP Streaming SVE set FPSIMD get SVE for VL 6800
5484 12:28:19.606633 # ok 3757 Set Streaming SVE VL 6816
5485 12:28:19.606729 # ok 3758 # SKIP Streaming SVE set SVE get SVE for VL 6816
5486 12:28:19.606840 # ok 3759 # SKIP Streaming SVE set SVE get FPSIMD for VL 6816
5487 12:28:19.606934 # ok 3760 # SKIP Streaming SVE set FPSIMD get SVE for VL 6816
5488 12:28:19.607032 # ok 3761 Set Streaming SVE VL 6832
5489 12:28:19.607183 # ok 3762 # SKIP Streaming SVE set SVE get SVE for VL 6832
5490 12:28:19.607316 # ok 3763 # SKIP Streaming SVE set SVE get FPSIMD for VL 6832
5491 12:28:19.607639 # ok 3764 # SKIP Streaming SVE set FPSIMD get SVE for VL 6832
5492 12:28:19.607770 # ok 3765 Set Streaming SVE VL 6848
5493 12:28:19.607864 # ok 3766 # SKIP Streaming SVE set SVE get SVE for VL 6848
5494 12:28:19.607961 # ok 3767 # SKIP Streaming SVE set SVE get FPSIMD for VL 6848
5495 12:28:19.609260 # ok 3768 # SKIP Streaming SVE set FPSIMD get SVE for VL 6848
5496 12:28:19.609466 # ok 3769 Set Streaming SVE VL 6864
5497 12:28:19.609774 # ok 3770 # SKIP Streaming SVE set SVE get SVE for VL 6864
5498 12:28:19.609991 # ok 3771 # SKIP Streaming SVE set SVE get FPSIMD for VL 6864
5499 12:28:19.610132 # ok 3772 # SKIP Streaming SVE set FPSIMD get SVE for VL 6864
5500 12:28:19.610252 # ok 3773 Set Streaming SVE VL 6880
5501 12:28:19.610393 # ok 3774 # SKIP Streaming SVE set SVE get SVE for VL 6880
5502 12:28:19.623775 # ok 3775 # SKIP Streaming SVE set SVE get FPSIMD for VL 6880
5503 12:28:19.624326 # ok 3776 # SKIP Streaming SVE set FPSIMD get SVE for VL 6880
5504 12:28:19.624485 # ok 3777 Set Streaming SVE VL 6896
5505 12:28:19.632282 # ok 3778 # SKIP Streaming SVE set SVE get SVE for VL 6896
5506 12:28:19.632942 # ok 3779 # SKIP Streaming SVE set SVE get FPSIMD for VL 6896
5507 12:28:19.633247 # ok 3780 # SKIP Streaming SVE set FPSIMD get SVE for VL 6896
5508 12:28:19.633445 # ok 3781 Set Streaming SVE VL 6912
5509 12:28:19.633677 # ok 3782 # SKIP Streaming SVE set SVE get SVE for VL 6912
5510 12:28:19.633948 # ok 3783 # SKIP Streaming SVE set SVE get FPSIMD for VL 6912
5511 12:28:19.634159 # ok 3784 # SKIP Streaming SVE set FPSIMD get SVE for VL 6912
5512 12:28:19.634377 # ok 3785 Set Streaming SVE VL 6928
5513 12:28:19.634564 # ok 3786 # SKIP Streaming SVE set SVE get SVE for VL 6928
5514 12:28:19.634805 # ok 3787 # SKIP Streaming SVE set SVE get FPSIMD for VL 6928
5515 12:28:19.634982 # ok 3788 # SKIP Streaming SVE set FPSIMD get SVE for VL 6928
5516 12:28:19.635199 # ok 3789 Set Streaming SVE VL 6944
5517 12:28:19.635423 # ok 3790 # SKIP Streaming SVE set SVE get SVE for VL 6944
5518 12:28:19.635659 # ok 3791 # SKIP Streaming SVE set SVE get FPSIMD for VL 6944
5519 12:28:19.635872 # ok 3792 # SKIP Streaming SVE set FPSIMD get SVE for VL 6944
5520 12:28:19.636083 # ok 3793 Set Streaming SVE VL 6960
5521 12:28:19.636219 # ok 3794 # SKIP Streaming SVE set SVE get SVE for VL 6960
5522 12:28:19.636337 # ok 3795 # SKIP Streaming SVE set SVE get FPSIMD for VL 6960
5523 12:28:19.636453 # ok 3796 # SKIP Streaming SVE set FPSIMD get SVE for VL 6960
5524 12:28:19.636568 # ok 3797 Set Streaming SVE VL 6976
5525 12:28:19.636682 # ok 3798 # SKIP Streaming SVE set SVE get SVE for VL 6976
5526 12:28:19.636796 # ok 3799 # SKIP Streaming SVE set SVE get FPSIMD for VL 6976
5527 12:28:19.636914 # ok 3800 # SKIP Streaming SVE set FPSIMD get SVE for VL 6976
5528 12:28:19.637027 # ok 3801 Set Streaming SVE VL 6992
5529 12:28:19.637142 # ok 3802 # SKIP Streaming SVE set SVE get SVE for VL 6992
5530 12:28:19.637257 # ok 3803 # SKIP Streaming SVE set SVE get FPSIMD for VL 6992
5531 12:28:19.637372 # ok 3804 # SKIP Streaming SVE set FPSIMD get SVE for VL 6992
5532 12:28:19.637486 # ok 3805 Set Streaming SVE VL 7008
5533 12:28:19.637599 # ok 3806 # SKIP Streaming SVE set SVE get SVE for VL 7008
5534 12:28:19.637813 # ok 3807 # SKIP Streaming SVE set SVE get FPSIMD for VL 7008
5535 12:28:19.639058 # ok 3808 # SKIP Streaming SVE set FPSIMD get SVE for VL 7008
5536 12:28:19.639474 # ok 3809 Set Streaming SVE VL 7024
5537 12:28:19.639652 # ok 3810 # SKIP Streaming SVE set SVE get SVE for VL 7024
5538 12:28:19.639870 # ok 3811 # SKIP Streaming SVE set SVE get FPSIMD for VL 7024
5539 12:28:19.640047 # ok 3812 # SKIP Streaming SVE set FPSIMD get SVE for VL 7024
5540 12:28:19.640174 # ok 3813 Set Streaming SVE VL 7040
5541 12:28:19.640292 # ok 3814 # SKIP Streaming SVE set SVE get SVE for VL 7040
5542 12:28:19.648738 # ok 3815 # SKIP Streaming SVE set SVE get FPSIMD for VL 7040
5543 12:28:19.649039 # ok 3816 # SKIP Streaming SVE set FPSIMD get SVE for VL 7040
5544 12:28:19.649239 # ok 3817 Set Streaming SVE VL 7056
5545 12:28:19.649671 # ok 3818 # SKIP Streaming SVE set SVE get SVE for VL 7056
5546 12:28:19.649853 # ok 3819 # SKIP Streaming SVE set SVE get FPSIMD for VL 7056
5547 12:28:19.650060 # ok 3820 # SKIP Streaming SVE set FPSIMD get SVE for VL 7056
5548 12:28:19.650232 # ok 3821 Set Streaming SVE VL 7072
5549 12:28:19.650390 # ok 3822 # SKIP Streaming SVE set SVE get SVE for VL 7072
5550 12:28:19.650548 # ok 3823 # SKIP Streaming SVE set SVE get FPSIMD for VL 7072
5551 12:28:19.650747 # ok 3824 # SKIP Streaming SVE set FPSIMD get SVE for VL 7072
5552 12:28:19.650906 # ok 3825 Set Streaming SVE VL 7088
5553 12:28:19.651034 # ok 3826 # SKIP Streaming SVE set SVE get SVE for VL 7088
5554 12:28:19.651173 # ok 3827 # SKIP Streaming SVE set SVE get FPSIMD for VL 7088
5555 12:28:19.651321 # ok 3828 # SKIP Streaming SVE set FPSIMD get SVE for VL 7088
5556 12:28:19.651460 # ok 3829 Set Streaming SVE VL 7104
5557 12:28:19.651592 # ok 3830 # SKIP Streaming SVE set SVE get SVE for VL 7104
5558 12:28:19.651746 # ok 3831 # SKIP Streaming SVE set SVE get FPSIMD for VL 7104
5559 12:28:19.651907 # ok 3832 # SKIP Streaming SVE set FPSIMD get SVE for VL 7104
5560 12:28:19.652033 # ok 3833 Set Streaming SVE VL 7120
5561 12:28:19.652148 # ok 3834 # SKIP Streaming SVE set SVE get SVE for VL 7120
5562 12:28:19.652263 # ok 3835 # SKIP Streaming SVE set SVE get FPSIMD for VL 7120
5563 12:28:19.652377 # ok 3836 # SKIP Streaming SVE set FPSIMD get SVE for VL 7120
5564 12:28:19.652492 # ok 3837 Set Streaming SVE VL 7136
5565 12:28:19.652606 # ok 3838 # SKIP Streaming SVE set SVE get SVE for VL 7136
5566 12:28:19.663663 # ok 3839 # SKIP Streaming SVE set SVE get FPSIMD for VL 7136
5567 12:28:19.664261 # ok 3840 # SKIP Streaming SVE set FPSIMD get SVE for VL 7136
5568 12:28:19.664404 # ok 3841 Set Streaming SVE VL 7152
5569 12:28:19.673938 # ok 3842 # SKIP Streaming SVE set SVE get SVE for VL 7152
5570 12:28:19.674267 # ok 3843 # SKIP Streaming SVE set SVE get FPSIMD for VL 7152
5571 12:28:19.674451 # ok 3844 # SKIP Streaming SVE set FPSIMD get SVE for VL 7152
5572 12:28:19.674903 # ok 3845 Set Streaming SVE VL 7168
5573 12:28:19.675101 # ok 3846 # SKIP Streaming SVE set SVE get SVE for VL 7168
5574 12:28:19.675268 # ok 3847 # SKIP Streaming SVE set SVE get FPSIMD for VL 7168
5575 12:28:19.675428 # ok 3848 # SKIP Streaming SVE set FPSIMD get SVE for VL 7168
5576 12:28:19.675585 # ok 3849 Set Streaming SVE VL 7184
5577 12:28:19.675747 # ok 3850 # SKIP Streaming SVE set SVE get SVE for VL 7184
5578 12:28:19.675900 # ok 3851 # SKIP Streaming SVE set SVE get FPSIMD for VL 7184
5579 12:28:19.676019 # ok 3852 # SKIP Streaming SVE set FPSIMD get SVE for VL 7184
5580 12:28:19.676163 # ok 3853 Set Streaming SVE VL 7200
5581 12:28:19.676284 # ok 3854 # SKIP Streaming SVE set SVE get SVE for VL 7200
5582 12:28:19.676400 # ok 3855 # SKIP Streaming SVE set SVE get FPSIMD for VL 7200
5583 12:28:19.676514 # ok 3856 # SKIP Streaming SVE set FPSIMD get SVE for VL 7200
5584 12:28:19.676628 # ok 3857 Set Streaming SVE VL 7216
5585 12:28:19.676739 # ok 3858 # SKIP Streaming SVE set SVE get SVE for VL 7216
5586 12:28:19.676853 # ok 3859 # SKIP Streaming SVE set SVE get FPSIMD for VL 7216
5587 12:28:19.676967 # ok 3860 # SKIP Streaming SVE set FPSIMD get SVE for VL 7216
5588 12:28:19.677082 # ok 3861 Set Streaming SVE VL 7232
5589 12:28:19.680502 # ok 3862 # SKIP Streaming SVE set SVE get SVE for VL 7232
5590 12:28:19.681090 # ok 3863 # SKIP Streaming SVE set SVE get FPSIMD for VL 7232
5591 12:28:19.681293 # ok 3864 # SKIP Streaming SVE set FPSIMD get SVE for VL 7232
5592 12:28:19.681458 # ok 3865 Set Streaming SVE VL 7248
5593 12:28:19.681623 # ok 3866 # SKIP Streaming SVE set SVE get SVE for VL 7248
5594 12:28:19.681792 # ok 3867 # SKIP Streaming SVE set SVE get FPSIMD for VL 7248
5595 12:28:19.681984 # ok 3868 # SKIP Streaming SVE set FPSIMD get SVE for VL 7248
5596 12:28:19.682147 # ok 3869 Set Streaming SVE VL 7264
5597 12:28:19.682302 # ok 3870 # SKIP Streaming SVE set SVE get SVE for VL 7264
5598 12:28:19.682457 # ok 3871 # SKIP Streaming SVE set SVE get FPSIMD for VL 7264
5599 12:28:19.682612 # ok 3872 # SKIP Streaming SVE set FPSIMD get SVE for VL 7264
5600 12:28:19.682769 # ok 3873 Set Streaming SVE VL 7280
5601 12:28:19.682923 # ok 3874 # SKIP Streaming SVE set SVE get SVE for VL 7280
5602 12:28:19.683118 # ok 3875 # SKIP Streaming SVE set SVE get FPSIMD for VL 7280
5603 12:28:19.683279 # ok 3876 # SKIP Streaming SVE set FPSIMD get SVE for VL 7280
5604 12:28:19.683434 # ok 3877 Set Streaming SVE VL 7296
5605 12:28:19.683590 # ok 3878 # SKIP Streaming SVE set SVE get SVE for VL 7296
5606 12:28:19.683752 # ok 3879 # SKIP Streaming SVE set SVE get FPSIMD for VL 7296
5607 12:28:19.683908 # ok 3880 # SKIP Streaming SVE set FPSIMD get SVE for VL 7296
5608 12:28:19.684061 # ok 3881 Set Streaming SVE VL 7312
5609 12:28:19.684217 # ok 3882 # SKIP Streaming SVE set SVE get SVE for VL 7312
5610 12:28:19.684372 # ok 3883 # SKIP Streaming SVE set SVE get FPSIMD for VL 7312
5611 12:28:19.684528 # ok 3884 # SKIP Streaming SVE set FPSIMD get SVE for VL 7312
5612 12:28:19.684717 # ok 3885 Set Streaming SVE VL 7328
5613 12:28:19.684877 # ok 3886 # SKIP Streaming SVE set SVE get SVE for VL 7328
5614 12:28:19.685034 # ok 3887 # SKIP Streaming SVE set SVE get FPSIMD for VL 7328
5615 12:28:19.685188 # ok 3888 # SKIP Streaming SVE set FPSIMD get SVE for VL 7328
5616 12:28:19.685343 # ok 3889 Set Streaming SVE VL 7344
5617 12:28:19.692274 # ok 3890 # SKIP Streaming SVE set SVE get SVE for VL 7344
5618 12:28:19.692894 # ok 3891 # SKIP Streaming SVE set SVE get FPSIMD for VL 7344
5619 12:28:19.693085 # ok 3892 # SKIP Streaming SVE set FPSIMD get SVE for VL 7344
5620 12:28:19.693228 # ok 3893 Set Streaming SVE VL 7360
5621 12:28:19.693377 # ok 3894 # SKIP Streaming SVE set SVE get SVE for VL 7360
5622 12:28:19.693587 # ok 3895 # SKIP Streaming SVE set SVE get FPSIMD for VL 7360
5623 12:28:19.693795 # ok 3896 # SKIP Streaming SVE set FPSIMD get SVE for VL 7360
5624 12:28:19.693972 # ok 3897 Set Streaming SVE VL 7376
5625 12:28:19.694151 # ok 3898 # SKIP Streaming SVE set SVE get SVE for VL 7376
5626 12:28:19.694333 # ok 3899 # SKIP Streaming SVE set SVE get FPSIMD for VL 7376
5627 12:28:19.694542 # ok 3900 # SKIP Streaming SVE set FPSIMD get SVE for VL 7376
5628 12:28:19.694725 # ok 3901 Set Streaming SVE VL 7392
5629 12:28:19.694890 # ok 3902 # SKIP Streaming SVE set SVE get SVE for VL 7392
5630 12:28:19.695048 # ok 3903 # SKIP Streaming SVE set SVE get FPSIMD for VL 7392
5631 12:28:19.695194 # ok 3904 # SKIP Streaming SVE set FPSIMD get SVE for VL 7392
5632 12:28:19.695344 # ok 3905 Set Streaming SVE VL 7408
5633 12:28:19.695526 # ok 3906 # SKIP Streaming SVE set SVE get SVE for VL 7408
5634 12:28:19.695664 # ok 3907 # SKIP Streaming SVE set SVE get FPSIMD for VL 7408
5635 12:28:19.695801 # ok 3908 # SKIP Streaming SVE set FPSIMD get SVE for VL 7408
5636 12:28:19.695921 # ok 3909 Set Streaming SVE VL 7424
5637 12:28:19.696038 # ok 3910 # SKIP Streaming SVE set SVE get SVE for VL 7424
5638 12:28:19.696153 # ok 3911 # SKIP Streaming SVE set SVE get FPSIMD for VL 7424
5639 12:28:19.696272 # ok 3912 # SKIP Streaming SVE set FPSIMD get SVE for VL 7424
5640 12:28:19.696414 # ok 3913 Set Streaming SVE VL 7440
5641 12:28:19.696532 # ok 3914 # SKIP Streaming SVE set SVE get SVE for VL 7440
5642 12:28:19.700970 # ok 3915 # SKIP Streaming SVE set SVE get FPSIMD for VL 7440
5643 12:28:19.701273 # ok 3916 # SKIP Streaming SVE set FPSIMD get SVE for VL 7440
5644 12:28:19.701467 # ok 3917 Set Streaming SVE VL 7456
5645 12:28:19.702039 # ok 3918 # SKIP Streaming SVE set SVE get SVE for VL 7456
5646 12:28:19.702210 # ok 3919 # SKIP Streaming SVE set SVE get FPSIMD for VL 7456
5647 12:28:19.702357 # ok 3920 # SKIP Streaming SVE set FPSIMD get SVE for VL 7456
5648 12:28:19.702477 # ok 3921 Set Streaming SVE VL 7472
5649 12:28:19.702593 # ok 3922 # SKIP Streaming SVE set SVE get SVE for VL 7472
5650 12:28:19.702708 # ok 3923 # SKIP Streaming SVE set SVE get FPSIMD for VL 7472
5651 12:28:19.702887 # ok 3924 # SKIP Streaming SVE set FPSIMD get SVE for VL 7472
5652 12:28:19.703091 # ok 3925 Set Streaming SVE VL 7488
5653 12:28:19.703267 # ok 3926 # SKIP Streaming SVE set SVE get SVE for VL 7488
5654 12:28:19.703509 # ok 3927 # SKIP Streaming SVE set SVE get FPSIMD for VL 7488
5655 12:28:19.703710 # ok 3928 # SKIP Streaming SVE set FPSIMD get SVE for VL 7488
5656 12:28:19.703958 # ok 3929 Set Streaming SVE VL 7504
5657 12:28:19.704121 # ok 3930 # SKIP Streaming SVE set SVE get SVE for VL 7504
5658 12:28:19.704246 # ok 3931 # SKIP Streaming SVE set SVE get FPSIMD for VL 7504
5659 12:28:19.708532 # ok 3932 # SKIP Streaming SVE set FPSIMD get SVE for VL 7504
5660 12:28:19.708930 # ok 3933 Set Streaming SVE VL 7520
5661 12:28:19.709399 # ok 3934 # SKIP Streaming SVE set SVE get SVE for VL 7520
5662 12:28:19.709715 # ok 3935 # SKIP Streaming SVE set SVE get FPSIMD for VL 7520
5663 12:28:19.709920 # ok 3936 # SKIP Streaming SVE set FPSIMD get SVE for VL 7520
5664 12:28:19.710258 # ok 3937 Set Streaming SVE VL 7536
5665 12:28:19.710517 # ok 3938 # SKIP Streaming SVE set SVE get SVE for VL 7536
5666 12:28:19.710850 # ok 3939 # SKIP Streaming SVE set SVE get FPSIMD for VL 7536
5667 12:28:19.711082 # ok 3940 # SKIP Streaming SVE set FPSIMD get SVE for VL 7536
5668 12:28:19.711339 # ok 3941 Set Streaming SVE VL 7552
5669 12:28:19.711675 # ok 3942 # SKIP Streaming SVE set SVE get SVE for VL 7552
5670 12:28:19.711974 # ok 3943 # SKIP Streaming SVE set SVE get FPSIMD for VL 7552
5671 12:28:19.712155 # ok 3944 # SKIP Streaming SVE set FPSIMD get SVE for VL 7552
5672 12:28:19.712282 # ok 3945 Set Streaming SVE VL 7568
5673 12:28:19.712433 # ok 3946 # SKIP Streaming SVE set SVE get SVE for VL 7568
5674 12:28:19.712583 # ok 3947 # SKIP Streaming SVE set SVE get FPSIMD for VL 7568
5675 12:28:19.712732 # ok 3948 # SKIP Streaming SVE set FPSIMD get SVE for VL 7568
5676 12:28:19.712921 # ok 3949 Set Streaming SVE VL 7584
5677 12:28:19.713050 # ok 3950 # SKIP Streaming SVE set SVE get SVE for VL 7584
5678 12:28:19.713202 # ok 3951 # SKIP Streaming SVE set SVE get FPSIMD for VL 7584
5679 12:28:19.713371 # ok 3952 # SKIP Streaming SVE set FPSIMD get SVE for VL 7584
5680 12:28:19.713552 # ok 3953 Set Streaming SVE VL 7600
5681 12:28:19.713802 # ok 3954 # SKIP Streaming SVE set SVE get SVE for VL 7600
5682 12:28:19.714025 # ok 3955 # SKIP Streaming SVE set SVE get FPSIMD for VL 7600
5683 12:28:19.716976 # ok 3956 # SKIP Streaming SVE set FPSIMD get SVE for VL 7600
5684 12:28:19.717266 # ok 3957 Set Streaming SVE VL 7616
5685 12:28:19.717742 # ok 3958 # SKIP Streaming SVE set SVE get SVE for VL 7616
5686 12:28:19.717928 # ok 3959 # SKIP Streaming SVE set SVE get FPSIMD for VL 7616
5687 12:28:19.718094 # ok 3960 # SKIP Streaming SVE set FPSIMD get SVE for VL 7616
5688 12:28:19.718250 # ok 3961 Set Streaming SVE VL 7632
5689 12:28:19.718395 # ok 3962 # SKIP Streaming SVE set SVE get SVE for VL 7632
5690 12:28:19.718590 # ok 3963 # SKIP Streaming SVE set SVE get FPSIMD for VL 7632
5691 12:28:19.718740 # ok 3964 # SKIP Streaming SVE set FPSIMD get SVE for VL 7632
5692 12:28:19.718908 # ok 3965 Set Streaming SVE VL 7648
5693 12:28:19.719053 # ok 3966 # SKIP Streaming SVE set SVE get SVE for VL 7648
5694 12:28:19.719211 # ok 3967 # SKIP Streaming SVE set SVE get FPSIMD for VL 7648
5695 12:28:19.719399 # ok 3968 # SKIP Streaming SVE set FPSIMD get SVE for VL 7648
5696 12:28:19.719557 # ok 3969 Set Streaming SVE VL 7664
5697 12:28:19.719716 # ok 3970 # SKIP Streaming SVE set SVE get SVE for VL 7664
5698 12:28:19.719859 # ok 3971 # SKIP Streaming SVE set SVE get FPSIMD for VL 7664
5699 12:28:19.720024 # ok 3972 # SKIP Streaming SVE set FPSIMD get SVE for VL 7664
5700 12:28:19.720168 # ok 3973 Set Streaming SVE VL 7680
5701 12:28:19.720358 # ok 3974 # SKIP Streaming SVE set SVE get SVE for VL 7680
5702 12:28:19.720513 # ok 3975 # SKIP Streaming SVE set SVE get FPSIMD for VL 7680
5703 12:28:19.720666 # ok 3976 # SKIP Streaming SVE set FPSIMD get SVE for VL 7680
5704 12:28:19.720858 # ok 3977 Set Streaming SVE VL 7696
5705 12:28:19.721074 # ok 3978 # SKIP Streaming SVE set SVE get SVE for VL 7696
5706 12:28:19.721246 # ok 3979 # SKIP Streaming SVE set SVE get FPSIMD for VL 7696
5707 12:28:19.721412 # ok 3980 # SKIP Streaming SVE set FPSIMD get SVE for VL 7696
5708 12:28:19.721571 # ok 3981 Set Streaming SVE VL 7712
5709 12:28:19.721749 # ok 3982 # SKIP Streaming SVE set SVE get SVE for VL 7712
5710 12:28:19.721955 # ok 3983 # SKIP Streaming SVE set SVE get FPSIMD for VL 7712
5711 12:28:19.722153 # ok 3984 # SKIP Streaming SVE set FPSIMD get SVE for VL 7712
5712 12:28:19.722348 # ok 3985 Set Streaming SVE VL 7728
5713 12:28:19.722521 # ok 3986 # SKIP Streaming SVE set SVE get SVE for VL 7728
5714 12:28:19.722684 # ok 3987 # SKIP Streaming SVE set SVE get FPSIMD for VL 7728
5715 12:28:19.722852 # ok 3988 # SKIP Streaming SVE set FPSIMD get SVE for VL 7728
5716 12:28:19.723048 # ok 3989 Set Streaming SVE VL 7744
5717 12:28:19.723214 # ok 3990 # SKIP Streaming SVE set SVE get SVE for VL 7744
5718 12:28:19.723368 # ok 3991 # SKIP Streaming SVE set SVE get FPSIMD for VL 7744
5719 12:28:19.723524 # ok 3992 # SKIP Streaming SVE set FPSIMD get SVE for VL 7744
5720 12:28:19.723939 # ok 3993 Set Streaming SVE VL 7760
5721 12:28:19.724114 # ok 3994 # SKIP Streaming SVE set SVE get SVE for VL 7760
5722 12:28:19.724259 # ok 3995 # SKIP Streaming SVE set SVE get FPSIMD for VL 7760
5723 12:28:19.724425 # ok 3996 # SKIP Streaming SVE set FPSIMD get SVE for VL 7760
5724 12:28:19.724569 # ok 3997 Set Streaming SVE VL 7776
5725 12:28:19.724727 # ok 3998 # SKIP Streaming SVE set SVE get SVE for VL 7776
5726 12:28:19.724880 # ok 3999 # SKIP Streaming SVE set SVE get FPSIMD for VL 7776
5727 12:28:19.725023 # ok 4000 # SKIP Streaming SVE set FPSIMD get SVE for VL 7776
5728 12:28:19.725186 # ok 4001 Set Streaming SVE VL 7792
5729 12:28:19.725326 # ok 4002 # SKIP Streaming SVE set SVE get SVE for VL 7792
5730 12:28:19.728616 # ok 4003 # SKIP Streaming SVE set SVE get FPSIMD for VL 7792
5731 12:28:19.728927 # ok 4004 # SKIP Streaming SVE set FPSIMD get SVE for VL 7792
5732 12:28:19.729180 # ok 4005 Set Streaming SVE VL 7808
5733 12:28:19.729375 # ok 4006 # SKIP Streaming SVE set SVE get SVE for VL 7808
5734 12:28:19.729600 # ok 4007 # SKIP Streaming SVE set SVE get FPSIMD for VL 7808
5735 12:28:19.729827 # ok 4008 # SKIP Streaming SVE set FPSIMD get SVE for VL 7808
5736 12:28:19.730087 # ok 4009 Set Streaming SVE VL 7824
5737 12:28:19.730310 # ok 4010 # SKIP Streaming SVE set SVE get SVE for VL 7824
5738 12:28:19.730526 # ok 4011 # SKIP Streaming SVE set SVE get FPSIMD for VL 7824
5739 12:28:19.730749 # ok 4012 # SKIP Streaming SVE set FPSIMD get SVE for VL 7824
5740 12:28:19.730965 # ok 4013 Set Streaming SVE VL 7840
5741 12:28:19.731228 # ok 4014 # SKIP Streaming SVE set SVE get SVE for VL 7840
5742 12:28:19.731486 # ok 4015 # SKIP Streaming SVE set SVE get FPSIMD for VL 7840
5743 12:28:19.731681 # ok 4016 # SKIP Streaming SVE set FPSIMD get SVE for VL 7840
5744 12:28:19.731911 # ok 4017 Set Streaming SVE VL 7856
5745 12:28:19.732070 # ok 4018 # SKIP Streaming SVE set SVE get SVE for VL 7856
5746 12:28:19.732194 # ok 4019 # SKIP Streaming SVE set SVE get FPSIMD for VL 7856
5747 12:28:19.732309 # ok 4020 # SKIP Streaming SVE set FPSIMD get SVE for VL 7856
5748 12:28:19.732424 # ok 4021 Set Streaming SVE VL 7872
5749 12:28:19.732538 # ok 4022 # SKIP Streaming SVE set SVE get SVE for VL 7872
5750 12:28:19.732652 # ok 4023 # SKIP Streaming SVE set SVE get FPSIMD for VL 7872
5751 12:28:19.732795 # ok 4024 # SKIP Streaming SVE set FPSIMD get SVE for VL 7872
5752 12:28:19.732918 # ok 4025 Set Streaming SVE VL 7888
5753 12:28:19.736379 # ok 4026 # SKIP Streaming SVE set SVE get SVE for VL 7888
5754 12:28:19.737197 # ok 4027 # SKIP Streaming SVE set SVE get FPSIMD for VL 7888
5755 12:28:19.737455 # ok 4028 # SKIP Streaming SVE set FPSIMD get SVE for VL 7888
5756 12:28:19.737684 # ok 4029 Set Streaming SVE VL 7904
5757 12:28:19.737909 # ok 4030 # SKIP Streaming SVE set SVE get SVE for VL 7904
5758 12:28:19.738056 # ok 4031 # SKIP Streaming SVE set SVE get FPSIMD for VL 7904
5759 12:28:19.738216 # ok 4032 # SKIP Streaming SVE set FPSIMD get SVE for VL 7904
5760 12:28:19.738377 # ok 4033 Set Streaming SVE VL 7920
5761 12:28:19.738518 # ok 4034 # SKIP Streaming SVE set SVE get SVE for VL 7920
5762 12:28:19.738617 # ok 4035 # SKIP Streaming SVE set SVE get FPSIMD for VL 7920
5763 12:28:19.738749 # ok 4036 # SKIP Streaming SVE set FPSIMD get SVE for VL 7920
5764 12:28:19.738920 # ok 4037 Set Streaming SVE VL 7936
5765 12:28:19.739067 # ok 4038 # SKIP Streaming SVE set SVE get SVE for VL 7936
5766 12:28:19.739176 # ok 4039 # SKIP Streaming SVE set SVE get FPSIMD for VL 7936
5767 12:28:19.739317 # ok 4040 # SKIP Streaming SVE set FPSIMD get SVE for VL 7936
5768 12:28:19.739451 # ok 4041 Set Streaming SVE VL 7952
5769 12:28:19.739588 # ok 4042 # SKIP Streaming SVE set SVE get SVE for VL 7952
5770 12:28:19.739716 # ok 4043 # SKIP Streaming SVE set SVE get FPSIMD for VL 7952
5771 12:28:19.739841 # ok 4044 # SKIP Streaming SVE set FPSIMD get SVE for VL 7952
5772 12:28:19.739968 # ok 4045 Set Streaming SVE VL 7968
5773 12:28:19.740112 # ok 4046 # SKIP Streaming SVE set SVE get SVE for VL 7968
5774 12:28:19.740205 # ok 4047 # SKIP Streaming SVE set SVE get FPSIMD for VL 7968
5775 12:28:19.744764 # ok 4048 # SKIP Streaming SVE set FPSIMD get SVE for VL 7968
5776 12:28:19.745318 # ok 4049 Set Streaming SVE VL 7984
5777 12:28:19.745424 # ok 4050 # SKIP Streaming SVE set SVE get SVE for VL 7984
5778 12:28:19.745516 # ok 4051 # SKIP Streaming SVE set SVE get FPSIMD for VL 7984
5779 12:28:19.745624 # ok 4052 # SKIP Streaming SVE set FPSIMD get SVE for VL 7984
5780 12:28:19.745720 # ok 4053 Set Streaming SVE VL 8000
5781 12:28:19.745810 # ok 4054 # SKIP Streaming SVE set SVE get SVE for VL 8000
5782 12:28:19.745917 # ok 4055 # SKIP Streaming SVE set SVE get FPSIMD for VL 8000
5783 12:28:19.746008 # ok 4056 # SKIP Streaming SVE set FPSIMD get SVE for VL 8000
5784 12:28:19.746123 # ok 4057 Set Streaming SVE VL 8016
5785 12:28:19.746253 # ok 4058 # SKIP Streaming SVE set SVE get SVE for VL 8016
5786 12:28:19.746572 # ok 4059 # SKIP Streaming SVE set SVE get FPSIMD for VL 8016
5787 12:28:19.746674 # ok 4060 # SKIP Streaming SVE set FPSIMD get SVE for VL 8016
5788 12:28:19.746786 # ok 4061 Set Streaming SVE VL 8032
5789 12:28:19.746896 # ok 4062 # SKIP Streaming SVE set SVE get SVE for VL 8032
5790 12:28:19.747008 # ok 4063 # SKIP Streaming SVE set SVE get FPSIMD for VL 8032
5791 12:28:19.747301 # ok 4064 # SKIP Streaming SVE set FPSIMD get SVE for VL 8032
5792 12:28:19.747400 # ok 4065 Set Streaming SVE VL 8048
5793 12:28:19.747510 # ok 4066 # SKIP Streaming SVE set SVE get SVE for VL 8048
5794 12:28:19.747912 # ok 4067 # SKIP Streaming SVE set SVE get FPSIMD for VL 8048
5795 12:28:19.748018 # ok 4068 # SKIP Streaming SVE set FPSIMD get SVE for VL 8048
5796 12:28:19.753337 # ok 4069 Set Streaming SVE VL 8064
5797 12:28:19.753513 # ok 4070 # SKIP Streaming SVE set SVE get SVE for VL 8064
5798 12:28:19.753799 # ok 4071 # SKIP Streaming SVE set SVE get FPSIMD for VL 8064
5799 12:28:19.753894 # ok 4072 # SKIP Streaming SVE set FPSIMD get SVE for VL 8064
5800 12:28:19.753980 # ok 4073 Set Streaming SVE VL 8080
5801 12:28:19.754065 # ok 4074 # SKIP Streaming SVE set SVE get SVE for VL 8080
5802 12:28:19.754932 # ok 4075 # SKIP Streaming SVE set SVE get FPSIMD for VL 8080
5803 12:28:19.755244 # ok 4076 # SKIP Streaming SVE set FPSIMD get SVE for VL 8080
5804 12:28:19.755350 # ok 4077 Set Streaming SVE VL 8096
5805 12:28:19.755455 # ok 4078 # SKIP Streaming SVE set SVE get SVE for VL 8096
5806 12:28:19.755558 # ok 4079 # SKIP Streaming SVE set SVE get FPSIMD for VL 8096
5807 12:28:19.755839 # ok 4080 # SKIP Streaming SVE set FPSIMD get SVE for VL 8096
5808 12:28:19.755931 # ok 4081 Set Streaming SVE VL 8112
5809 12:28:19.756029 # ok 4082 # SKIP Streaming SVE set SVE get SVE for VL 8112
5810 12:28:19.760303 # ok 4083 # SKIP Streaming SVE set SVE get FPSIMD for VL 8112
5811 12:28:19.760696 # ok 4084 # SKIP Streaming SVE set FPSIMD get SVE for VL 8112
5812 12:28:19.760790 # ok 4085 Set Streaming SVE VL 8128
5813 12:28:19.760878 # ok 4086 # SKIP Streaming SVE set SVE get SVE for VL 8128
5814 12:28:19.760964 # ok 4087 # SKIP Streaming SVE set SVE get FPSIMD for VL 8128
5815 12:28:19.761067 # ok 4088 # SKIP Streaming SVE set FPSIMD get SVE for VL 8128
5816 12:28:19.761158 # ok 4089 Set Streaming SVE VL 8144
5817 12:28:19.761244 # ok 4090 # SKIP Streaming SVE set SVE get SVE for VL 8144
5818 12:28:19.761346 # ok 4091 # SKIP Streaming SVE set SVE get FPSIMD for VL 8144
5819 12:28:19.761435 # ok 4092 # SKIP Streaming SVE set FPSIMD get SVE for VL 8144
5820 12:28:19.761519 # ok 4093 Set Streaming SVE VL 8160
5821 12:28:19.761619 # ok 4094 # SKIP Streaming SVE set SVE get SVE for VL 8160
5822 12:28:19.761714 # ok 4095 # SKIP Streaming SVE set SVE get FPSIMD for VL 8160
5823 12:28:19.761813 # ok 4096 # SKIP Streaming SVE set FPSIMD get SVE for VL 8160
5824 12:28:19.761901 # ok 4097 Set Streaming SVE VL 8176
5825 12:28:19.762000 # ok 4098 # SKIP Streaming SVE set SVE get SVE for VL 8176
5826 12:28:19.762101 # ok 4099 # SKIP Streaming SVE set SVE get FPSIMD for VL 8176
5827 12:28:19.762401 # ok 4100 # SKIP Streaming SVE set FPSIMD get SVE for VL 8176
5828 12:28:19.762494 # ok 4101 Set Streaming SVE VL 8192
5829 12:28:19.762580 # ok 4102 # SKIP Streaming SVE set SVE get SVE for VL 8192
5830 12:28:19.762679 # ok 4103 # SKIP Streaming SVE set SVE get FPSIMD for VL 8192
5831 12:28:19.762780 # ok 4104 # SKIP Streaming SVE set FPSIMD get SVE for VL 8192
5832 12:28:19.762869 # # Totals: pass:1095 fail:0 xfail:0 xpass:0 skip:3009 error:0
5833 12:28:19.763378 ok 30 selftests: arm64: sve-ptrace
5834 12:28:19.763471 # selftests: arm64: sve-probe-vls
5835 12:28:19.763559 # TAP version 13
5836 12:28:19.763643 # 1..2
5837 12:28:19.763726 # ok 1 Enumerated 16 vector lengths
5838 12:28:19.763813 # ok 2 All vector lengths valid
5839 12:28:19.763898 # # 16
5840 12:28:19.763984 # # 32
5841 12:28:19.764072 # # 48
5842 12:28:19.764165 # # 64
5843 12:28:19.764255 # # 80
5844 12:28:19.764347 # # 96
5845 12:28:19.764622 # # 112
5846 12:28:19.764714 # # 128
5847 12:28:19.764798 # # 144
5848 12:28:19.764879 # # 160
5849 12:28:19.764962 # # 176
5850 12:28:19.765043 # # 192
5851 12:28:19.765126 # # 208
5852 12:28:19.765206 # # 224
5853 12:28:19.765290 # # 240
5854 12:28:19.765372 # # 256
5855 12:28:19.765456 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
5856 12:28:19.765539 ok 31 selftests: arm64: sve-probe-vls
5857 12:28:19.874377 # selftests: arm64: vec-syscfg
5858 12:28:21.018956 # TAP version 13
5859 12:28:21.019287 # 1..20
5860 12:28:21.019704 # ok 1 SVE default vector length 64
5861 12:28:21.019906 # ok 2 SVE minimum vector length 16
5862 12:28:21.020005 # ok 3 SVE maximum vector length 256
5863 12:28:21.020092 # ok 4 SVE current VL is 64
5864 12:28:21.020179 # ok 5 SVE set VL 64 and have VL 64
5865 12:28:21.020266 # ok 6 SVE prctl() set min/max
5866 12:28:21.020352 # ok 7 SVE vector length used default
5867 12:28:21.020438 # ok 8 SVE vector length was inherited
5868 12:28:21.020542 # ok 9 SVE vector length set on exec
5869 12:28:21.020632 # ok 10 SVE prctl() set all VLs, 0 errors
5870 12:28:21.020952 # ok 11 SME default vector length 32
5871 12:28:21.021118 # ok 12 SME minimum vector length 16
5872 12:28:21.021255 # ok 13 SME maximum vector length 256
5873 12:28:21.021390 # ok 14 SME current VL is 32
5874 12:28:21.021594 # ok 15 SME set VL 32 and have VL 32
5875 12:28:21.021782 # ok 16 SME prctl() set min/max
5876 12:28:21.021931 # ok 17 SME vector length used default
5877 12:28:21.023836 # ok 18 SME vector length was inherited
5878 12:28:21.024252 # ok 19 SME vector length set on exec
5879 12:28:21.024407 # ok 20 SME prctl() set all VLs, 0 errors
5880 12:28:21.024562 # # Totals: pass:20 fail:0 xfail:0 xpass:0 skip:0 error:0
5881 12:28:21.047719 ok 32 selftests: arm64: vec-syscfg
5882 12:28:21.162184 # selftests: arm64: za-fork
5883 12:28:21.343197 # TAP version 13
5884 12:28:21.343666 # 1..1
5885 12:28:21.343775 # # PID: 1014
5886 12:28:21.343860 # ok 1 fork_test
5887 12:28:21.343934 # # Totals: pass:1 fail:0 xfail:0 xpass:0 skip:0 error:0
5888 12:28:21.371382 ok 33 selftests: arm64: za-fork
5889 12:28:21.552928 # selftests: arm64: za-ptrace
5890 12:28:21.765274 # TAP version 13
5891 12:28:21.765519 # 1..1536
5892 12:28:21.765802 # # Parent is 1032, child is 1033
5893 12:28:21.767608 # ok 1 Set VL 16
5894 12:28:21.767755 # ok 2 Disabled ZA for VL 16
5895 12:28:21.768188 # ok 3 Data match for VL 16
5896 12:28:21.768389 # ok 4 Set VL 32
5897 12:28:21.768561 # ok 5 Disabled ZA for VL 32
5898 12:28:21.768710 # ok 6 Data match for VL 32
5899 12:28:21.768894 # ok 7 Set VL 48
5900 12:28:21.769034 # ok 8 # SKIP Disabled ZA for VL 48
5901 12:28:21.769220 # ok 9 # SKIP Get and set data for VL 48
5902 12:28:21.769360 # ok 10 Set VL 64
5903 12:28:21.769481 # ok 11 Disabled ZA for VL 64
5904 12:28:21.769599 # ok 12 Data match for VL 64
5905 12:28:21.769789 # ok 13 Set VL 80
5906 12:28:21.769990 # ok 14 # SKIP Disabled ZA for VL 80
5907 12:28:21.770164 # ok 15 # SKIP Get and set data for VL 80
5908 12:28:21.770337 # ok 16 Set VL 96
5909 12:28:21.770513 # ok 17 # SKIP Disabled ZA for VL 96
5910 12:28:21.770666 # ok 18 # SKIP Get and set data for VL 96
5911 12:28:21.770810 # ok 19 Set VL 112
5912 12:28:21.770962 # ok 20 # SKIP Disabled ZA for VL 112
5913 12:28:21.771141 # ok 21 # SKIP Get and set data for VL 112
5914 12:28:21.771286 # ok 22 Set VL 128
5915 12:28:21.771427 # ok 23 Disabled ZA for VL 128
5916 12:28:21.771573 # ok 24 Data match for VL 128
5917 12:28:21.771715 # ok 25 Set VL 144
5918 12:28:21.771848 # ok 26 # SKIP Disabled ZA for VL 144
5919 12:28:21.771976 # ok 27 # SKIP Get and set data for VL 144
5920 12:28:21.772101 # ok 28 Set VL 160
5921 12:28:21.772224 # ok 29 # SKIP Disabled ZA for VL 160
5922 12:28:21.772373 # ok 30 # SKIP Get and set data for VL 160
5923 12:28:21.772516 # ok 31 Set VL 176
5924 12:28:21.772691 # ok 32 # SKIP Disabled ZA for VL 176
5925 12:28:21.772820 # ok 33 # SKIP Get and set data for VL 176
5926 12:28:21.772946 # ok 34 Set VL 192
5927 12:28:21.773083 # ok 35 # SKIP Disabled ZA for VL 192
5928 12:28:21.773231 # ok 36 # SKIP Get and set data for VL 192
5929 12:28:21.773398 # ok 37 Set VL 208
5930 12:28:21.773531 # ok 38 # SKIP Disabled ZA for VL 208
5931 12:28:21.773674 # ok 39 # SKIP Get and set data for VL 208
5932 12:28:21.773797 # ok 40 Set VL 224
5933 12:28:21.773912 # ok 41 # SKIP Disabled ZA for VL 224
5934 12:28:21.774027 # ok 42 # SKIP Get and set data for VL 224
5935 12:28:21.774140 # ok 43 Set VL 240
5936 12:28:21.774265 # ok 44 # SKIP Disabled ZA for VL 240
5937 12:28:21.774442 # ok 45 # SKIP Get and set data for VL 240
5938 12:28:21.774627 # ok 46 Set VL 256
5939 12:28:21.774764 # ok 47 Disabled ZA for VL 256
5940 12:28:21.774907 # ok 48 Data match for VL 256
5941 12:28:21.775050 # ok 49 Set VL 272
5942 12:28:21.775192 # ok 50 # SKIP Disabled ZA for VL 272
5943 12:28:21.782237 # ok 51 # SKIP Get and set data for VL 272
5944 12:28:21.782706 # ok 52 Set VL 288
5945 12:28:21.783166 # ok 53 # SKIP Disabled ZA for VL 288
5946 12:28:21.783355 # ok 54 # SKIP Get and set data for VL 288
5947 12:28:21.783536 # ok 55 Set VL 304
5948 12:28:21.783701 # ok 56 # SKIP Disabled ZA for VL 304
5949 12:28:21.783960 # ok 57 # SKIP Get and set data for VL 304
5950 12:28:21.784147 # ok 58 Set VL 320
5951 12:28:21.784324 # ok 59 # SKIP Disabled ZA for VL 320
5952 12:28:21.784526 # ok 60 # SKIP Get and set data for VL 320
5953 12:28:21.784737 # ok 61 Set VL 336
5954 12:28:21.784968 # ok 62 # SKIP Disabled ZA for VL 336
5955 12:28:21.785143 # ok 63 # SKIP Get and set data for VL 336
5956 12:28:21.785312 # ok 64 Set VL 352
5957 12:28:21.785439 # ok 65 # SKIP Disabled ZA for VL 352
5958 12:28:21.785552 # ok 66 # SKIP Get and set data for VL 352
5959 12:28:21.785676 # ok 67 Set VL 368
5960 12:28:21.785790 # ok 68 # SKIP Disabled ZA for VL 368
5961 12:28:21.785906 # ok 69 # SKIP Get and set data for VL 368
5962 12:28:21.786025 # ok 70 Set VL 384
5963 12:28:21.786140 # ok 71 # SKIP Disabled ZA for VL 384
5964 12:28:21.786254 # ok 72 # SKIP Get and set data for VL 384
5965 12:28:21.786368 # ok 73 Set VL 400
5966 12:28:21.786482 # ok 74 # SKIP Disabled ZA for VL 400
5967 12:28:21.786595 # ok 75 # SKIP Get and set data for VL 400
5968 12:28:21.786709 # ok 76 Set VL 416
5969 12:28:21.786824 # ok 77 # SKIP Disabled ZA for VL 416
5970 12:28:21.786937 # ok 78 # SKIP Get and set data for VL 416
5971 12:28:21.787052 # ok 79 Set VL 432
5972 12:28:21.787194 # ok 80 # SKIP Disabled ZA for VL 432
5973 12:28:21.787315 # ok 81 # SKIP Get and set data for VL 432
5974 12:28:21.787430 # ok 82 Set VL 448
5975 12:28:21.787544 # ok 83 # SKIP Disabled ZA for VL 448
5976 12:28:21.790811 # ok 84 # SKIP Get and set data for VL 448
5977 12:28:21.791045 # ok 85 Set VL 464
5978 12:28:21.791509 # ok 86 # SKIP Disabled ZA for VL 464
5979 12:28:21.791732 # ok 87 # SKIP Get and set data for VL 464
5980 12:28:21.791961 # ok 88 Set VL 480
5981 12:28:21.792176 # ok 89 # SKIP Disabled ZA for VL 480
5982 12:28:21.792449 # ok 90 # SKIP Get and set data for VL 480
5983 12:28:21.792679 # ok 91 Set VL 496
5984 12:28:21.792869 # ok 92 # SKIP Disabled ZA for VL 496
5985 12:28:21.793041 # ok 93 # SKIP Get and set data for VL 496
5986 12:28:21.793205 # ok 94 Set VL 512
5987 12:28:21.793352 # ok 95 # SKIP Disabled ZA for VL 512
5988 12:28:21.793473 # ok 96 # SKIP Get and set data for VL 512
5989 12:28:21.793587 # ok 97 Set VL 528
5990 12:28:21.793764 # ok 98 # SKIP Disabled ZA for VL 528
5991 12:28:21.793961 # ok 99 # SKIP Get and set data for VL 528
5992 12:28:21.794148 # ok 100 Set VL 544
5993 12:28:21.794292 # ok 101 # SKIP Disabled ZA for VL 544
5994 12:28:21.794437 # ok 102 # SKIP Get and set data for VL 544
5995 12:28:21.794579 # ok 103 Set VL 560
5996 12:28:21.794765 # ok 104 # SKIP Disabled ZA for VL 560
5997 12:28:21.794901 # ok 105 # SKIP Get and set data for VL 560
5998 12:28:21.795044 # ok 106 Set VL 576
5999 12:28:21.795188 # ok 107 # SKIP Disabled ZA for VL 576
6000 12:28:21.795331 # ok 108 # SKIP Get and set data for VL 576
6001 12:28:21.795475 # ok 109 Set VL 592
6002 12:28:21.795617 # ok 110 # SKIP Disabled ZA for VL 592
6003 12:28:21.795758 # ok 111 # SKIP Get and set data for VL 592
6004 12:28:21.795900 # ok 112 Set VL 608
6005 12:28:21.796047 # ok 113 # SKIP Disabled ZA for VL 608
6006 12:28:21.796189 # ok 114 # SKIP Get and set data for VL 608
6007 12:28:21.798848 # ok 115 Set VL 624
6008 12:28:21.799026 # ok 116 # SKIP Disabled ZA for VL 624
6009 12:28:21.799354 # ok 117 # SKIP Get and set data for VL 624
6010 12:28:21.799465 # ok 118 Set VL 640
6011 12:28:21.799561 # ok 119 # SKIP Disabled ZA for VL 640
6012 12:28:21.799654 # ok 120 # SKIP Get and set data for VL 640
6013 12:28:21.799745 # ok 121 Set VL 656
6014 12:28:21.799850 # ok 122 # SKIP Disabled ZA for VL 656
6015 12:28:21.799946 # ok 123 # SKIP Get and set data for VL 656
6016 12:28:21.800042 # ok 124 Set VL 672
6017 12:28:21.813092 # ok 125 # SKIP Disabled ZA for VL 672
6018 12:28:21.813554 # ok 126 # SKIP Get and set data for VL 672
6019 12:28:21.813672 # ok 127 Set VL 688
6020 12:28:21.813769 # ok 128 # SKIP Disabled ZA for VL 688
6021 12:28:21.813861 # ok 129 # SKIP Get and set data for VL 688
6022 12:28:21.818761 # ok 130 Set VL 704
6023 12:28:21.819153 # ok 131 # SKIP Disabled ZA for VL 704
6024 12:28:21.819252 # ok 132 # SKIP Get and set data for VL 704
6025 12:28:21.819342 # ok 133 Set VL 720
6026 12:28:21.819433 # ok 134 # SKIP Disabled ZA for VL 720
6027 12:28:21.819520 # ok 135 # SKIP Get and set data for VL 720
6028 12:28:21.819621 # ok 136 Set VL 736
6029 12:28:21.819710 # ok 137 # SKIP Disabled ZA for VL 736
6030 12:28:21.819797 # ok 138 # SKIP Get and set data for VL 736
6031 12:28:21.819884 # ok 139 Set VL 752
6032 12:28:21.819985 # ok 140 # SKIP Disabled ZA for VL 752
6033 12:28:21.820072 # ok 141 # SKIP Get and set data for VL 752
6034 12:28:21.820175 # ok 142 Set VL 768
6035 12:28:21.820262 # ok 143 # SKIP Disabled ZA for VL 768
6036 12:28:21.820364 # ok 144 # SKIP Get and set data for VL 768
6037 12:28:21.820452 # ok 145 Set VL 784
6038 12:28:21.820554 # ok 146 # SKIP Disabled ZA for VL 784
6039 12:28:21.820642 # ok 147 # SKIP Get and set data for VL 784
6040 12:28:21.820741 # ok 148 Set VL 800
6041 12:28:21.820842 # ok 149 # SKIP Disabled ZA for VL 800
6042 12:28:21.820944 # ok 150 # SKIP Get and set data for VL 800
6043 12:28:21.821033 # ok 151 Set VL 816
6044 12:28:21.821304 # ok 152 # SKIP Disabled ZA for VL 816
6045 12:28:21.821398 # ok 153 # SKIP Get and set data for VL 816
6046 12:28:21.821465 # ok 154 Set VL 832
6047 12:28:21.830642 # ok 155 # SKIP Disabled ZA for VL 832
6048 12:28:21.830940 # ok 156 # SKIP Get and set data for VL 832
6049 12:28:21.831297 # ok 157 Set VL 848
6050 12:28:21.831438 # ok 158 # SKIP Disabled ZA for VL 848
6051 12:28:21.831600 # ok 159 # SKIP Get and set data for VL 848
6052 12:28:21.831725 # ok 160 Set VL 864
6053 12:28:21.831859 # ok 161 # SKIP Disabled ZA for VL 864
6054 12:28:21.832003 # ok 162 # SKIP Get and set data for VL 864
6055 12:28:21.832124 # ok 163 Set VL 880
6056 12:28:21.832270 # ok 164 # SKIP Disabled ZA for VL 880
6057 12:28:21.832414 # ok 165 # SKIP Get and set data for VL 880
6058 12:28:21.832570 # ok 166 Set VL 896
6059 12:28:21.832727 # ok 167 # SKIP Disabled ZA for VL 896
6060 12:28:21.832848 # ok 168 # SKIP Get and set data for VL 896
6061 12:28:21.832978 # ok 169 Set VL 912
6062 12:28:21.833126 # ok 170 # SKIP Disabled ZA for VL 912
6063 12:28:21.833246 # ok 171 # SKIP Get and set data for VL 912
6064 12:28:21.833402 # ok 172 Set VL 928
6065 12:28:21.833524 # ok 173 # SKIP Disabled ZA for VL 928
6066 12:28:21.833662 # ok 174 # SKIP Get and set data for VL 928
6067 12:28:21.833823 # ok 175 Set VL 944
6068 12:28:21.833945 # ok 176 # SKIP Disabled ZA for VL 944
6069 12:28:21.834081 # ok 177 # SKIP Get and set data for VL 944
6070 12:28:21.834221 # ok 178 Set VL 960
6071 12:28:21.834337 # ok 179 # SKIP Disabled ZA for VL 960
6072 12:28:21.834483 # ok 180 # SKIP Get and set data for VL 960
6073 12:28:21.834612 # ok 181 Set VL 976
6074 12:28:21.834748 # ok 182 # SKIP Disabled ZA for VL 976
6075 12:28:21.834913 # ok 183 # SKIP Get and set data for VL 976
6076 12:28:21.835043 # ok 184 Set VL 992
6077 12:28:21.835194 # ok 185 # SKIP Disabled ZA for VL 992
6078 12:28:21.835359 # ok 186 # SKIP Get and set data for VL 992
6079 12:28:21.835492 # ok 187 Set VL 1008
6080 12:28:21.835614 # ok 188 # SKIP Disabled ZA for VL 1008
6081 12:28:21.835767 # ok 189 # SKIP Get and set data for VL 1008
6082 12:28:21.835887 # ok 190 Set VL 1024
6083 12:28:21.836019 # ok 191 # SKIP Disabled ZA for VL 1024
6084 12:28:21.836157 # ok 192 # SKIP Get and set data for VL 1024
6085 12:28:21.836275 # ok 193 Set VL 1040
6086 12:28:21.836428 # ok 194 # SKIP Disabled ZA for VL 1040
6087 12:28:21.839023 # ok 195 # SKIP Get and set data for VL 1040
6088 12:28:21.839287 # ok 196 Set VL 1056
6089 12:28:21.839442 # ok 197 # SKIP Disabled ZA for VL 1056
6090 12:28:21.839784 # ok 198 # SKIP Get and set data for VL 1056
6091 12:28:21.839921 # ok 199 Set VL 1072
6092 12:28:21.840060 # ok 200 # SKIP Disabled ZA for VL 1072
6093 12:28:21.840203 # ok 201 # SKIP Get and set data for VL 1072
6094 12:28:21.840321 # ok 202 Set VL 1088
6095 12:28:21.840477 # ok 203 # SKIP Disabled ZA for VL 1088
6096 12:28:21.840612 # ok 204 # SKIP Get and set data for VL 1088
6097 12:28:21.840763 # ok 205 Set VL 1104
6098 12:28:21.840921 # ok 206 # SKIP Disabled ZA for VL 1104
6099 12:28:21.841044 # ok 207 # SKIP Get and set data for VL 1104
6100 12:28:21.841183 # ok 208 Set VL 1120
6101 12:28:21.841325 # ok 209 # SKIP Disabled ZA for VL 1120
6102 12:28:21.841511 # ok 210 # SKIP Get and set data for VL 1120
6103 12:28:21.841693 # ok 211 Set VL 1136
6104 12:28:21.841817 # ok 212 # SKIP Disabled ZA for VL 1136
6105 12:28:21.841966 # ok 213 # SKIP Get and set data for VL 1136
6106 12:28:21.842108 # ok 214 Set VL 1152
6107 12:28:21.842224 # ok 215 # SKIP Disabled ZA for VL 1152
6108 12:28:21.842377 # ok 216 # SKIP Get and set data for VL 1152
6109 12:28:21.842498 # ok 217 Set VL 1168
6110 12:28:21.842620 # ok 218 # SKIP Disabled ZA for VL 1168
6111 12:28:21.842774 # ok 219 # SKIP Get and set data for VL 1168
6112 12:28:21.842904 # ok 220 Set VL 1184
6113 12:28:21.843019 # ok 221 # SKIP Disabled ZA for VL 1184
6114 12:28:21.843181 # ok 222 # SKIP Get and set data for VL 1184
6115 12:28:21.843333 # ok 223 Set VL 1200
6116 12:28:21.843469 # ok 224 # SKIP Disabled ZA for VL 1200
6117 12:28:21.843623 # ok 225 # SKIP Get and set data for VL 1200
6118 12:28:21.843762 # ok 226 Set VL 1216
6119 12:28:21.843879 # ok 227 # SKIP Disabled ZA for VL 1216
6120 12:28:21.844029 # ok 228 # SKIP Get and set data for VL 1216
6121 12:28:21.844155 # ok 229 Set VL 1232
6122 12:28:21.844280 # ok 230 # SKIP Disabled ZA for VL 1232
6123 12:28:21.847007 # ok 231 # SKIP Get and set data for VL 1232
6124 12:28:21.847267 # ok 232 Set VL 1248
6125 12:28:21.847484 # ok 233 # SKIP Disabled ZA for VL 1248
6126 12:28:21.847940 # ok 234 # SKIP Get and set data for VL 1248
6127 12:28:21.848147 # ok 235 Set VL 1264
6128 12:28:21.848362 # ok 236 # SKIP Disabled ZA for VL 1264
6129 12:28:21.848580 # ok 237 # SKIP Get and set data for VL 1264
6130 12:28:21.848779 # ok 238 Set VL 1280
6131 12:28:21.848947 # ok 239 # SKIP Disabled ZA for VL 1280
6132 12:28:21.849120 # ok 240 # SKIP Get and set data for VL 1280
6133 12:28:21.849308 # ok 241 Set VL 1296
6134 12:28:21.849491 # ok 242 # SKIP Disabled ZA for VL 1296
6135 12:28:21.849731 # ok 243 # SKIP Get and set data for VL 1296
6136 12:28:21.849876 # ok 244 Set VL 1312
6137 12:28:21.850039 # ok 245 # SKIP Disabled ZA for VL 1312
6138 12:28:21.850174 # ok 246 # SKIP Get and set data for VL 1312
6139 12:28:21.850305 # ok 247 Set VL 1328
6140 12:28:21.850450 # ok 248 # SKIP Disabled ZA for VL 1328
6141 12:28:21.850570 # ok 249 # SKIP Get and set data for VL 1328
6142 12:28:21.850732 # ok 250 Set VL 1344
6143 12:28:21.850869 # ok 251 # SKIP Disabled ZA for VL 1344
6144 12:28:21.850993 # ok 252 # SKIP Get and set data for VL 1344
6145 12:28:21.851113 # ok 253 Set VL 1360
6146 12:28:21.851228 # ok 254 # SKIP Disabled ZA for VL 1360
6147 12:28:21.851357 # ok 255 # SKIP Get and set data for VL 1360
6148 12:28:21.851508 # ok 256 Set VL 1376
6149 12:28:21.851630 # ok 257 # SKIP Disabled ZA for VL 1376
6150 12:28:21.857069 # ok 258 # SKIP Get and set data for VL 1376
6151 12:28:21.857483 # ok 259 Set VL 1392
6152 12:28:21.857846 # ok 260 # SKIP Disabled ZA for VL 1392
6153 12:28:21.857980 # ok 261 # SKIP Get and set data for VL 1392
6154 12:28:21.858099 # ok 262 Set VL 1408
6155 12:28:21.860884 # ok 263 # SKIP Disabled ZA for VL 1408
6156 12:28:21.861404 # ok 264 # SKIP Get and set data for VL 1408
6157 12:28:21.861565 # ok 265 Set VL 1424
6158 12:28:21.861705 # ok 266 # SKIP Disabled ZA for VL 1424
6159 12:28:21.861828 # ok 267 # SKIP Get and set data for VL 1424
6160 12:28:21.882975 # ok 268 Set VL 1440
6161 12:28:21.883228 # ok 269 # SKIP Disabled ZA for VL 1440
6162 12:28:21.883562 # ok 270 # SKIP Get and set data for VL 1440
6163 12:28:21.883671 # ok 271 Set VL 1456
6164 12:28:21.883761 # ok 272 # SKIP Disabled ZA for VL 1456
6165 12:28:21.883847 # ok 273 # SKIP Get and set data for VL 1456
6166 12:28:21.883933 # ok 274 Set VL 1472
6167 12:28:21.884033 # ok 275 # SKIP Disabled ZA for VL 1472
6168 12:28:21.884123 # ok 276 # SKIP Get and set data for VL 1472
6169 12:28:21.884229 # ok 277 Set VL 1488
6170 12:28:21.884319 # ok 278 # SKIP Disabled ZA for VL 1488
6171 12:28:21.884612 # ok 279 # SKIP Get and set data for VL 1488
6172 12:28:21.884718 # ok 280 Set VL 1504
6173 12:28:21.884806 # ok 281 # SKIP Disabled ZA for VL 1504
6174 12:28:21.884908 # ok 282 # SKIP Get and set data for VL 1504
6175 12:28:21.884996 # ok 283 Set VL 1520
6176 12:28:21.885082 # ok 284 # SKIP Disabled ZA for VL 1520
6177 12:28:21.885415 # ok 285 # SKIP Get and set data for VL 1520
6178 12:28:21.885574 # ok 286 Set VL 1536
6179 12:28:21.885723 # ok 287 # SKIP Disabled ZA for VL 1536
6180 12:28:21.885899 # ok 288 # SKIP Get and set data for VL 1536
6181 12:28:21.924380 # ok 289 Set VL 1552
6182 12:28:21.924744 # ok 290 # SKIP Disabled ZA for VL 1552
6183 12:28:21.924967 # ok 291 # SKIP Get and set data for VL 1552
6184 12:28:21.925399 # ok 292 Set VL 1568
6185 12:28:21.925603 # ok 293 # SKIP Disabled ZA for VL 1568
6186 12:28:21.925754 # ok 294 # SKIP Get and set data for VL 1568
6187 12:28:21.925908 # ok 295 Set VL 1584
6188 12:28:21.926034 # ok 296 # SKIP Disabled ZA for VL 1584
6189 12:28:21.926179 # ok 297 # SKIP Get and set data for VL 1584
6190 12:28:21.926313 # ok 298 Set VL 1600
6191 12:28:21.926439 # ok 299 # SKIP Disabled ZA for VL 1600
6192 12:28:21.944673 # ok 300 # SKIP Get and set data for VL 1600
6193 12:28:21.945025 # ok 301 Set VL 1616
6194 12:28:21.945461 # ok 302 # SKIP Disabled ZA for VL 1616
6195 12:28:21.945661 # ok 303 # SKIP Get and set data for VL 1616
6196 12:28:21.945837 # ok 304 Set VL 1632
6197 12:28:21.945984 # ok 305 # SKIP Disabled ZA for VL 1632
6198 12:28:21.946132 # ok 306 # SKIP Get and set data for VL 1632
6199 12:28:21.946276 # ok 307 Set VL 1648
6200 12:28:21.946421 # ok 308 # SKIP Disabled ZA for VL 1648
6201 12:28:21.946565 # ok 309 # SKIP Get and set data for VL 1648
6202 12:28:21.953062 # ok 310 Set VL 1664
6203 12:28:21.953686 # ok 311 # SKIP Disabled ZA for VL 1664
6204 12:28:21.953855 # ok 312 # SKIP Get and set data for VL 1664
6205 12:28:21.953981 # ok 313 Set VL 1680
6206 12:28:21.954099 # ok 314 # SKIP Disabled ZA for VL 1680
6207 12:28:21.960452 # ok 315 # SKIP Get and set data for VL 1680
6208 12:28:21.960690 # ok 316 Set VL 1696
6209 12:28:21.960788 # ok 317 # SKIP Disabled ZA for VL 1696
6210 12:28:21.960896 # ok 318 # SKIP Get and set data for VL 1696
6211 12:28:21.960990 # ok 319 Set VL 1712
6212 12:28:21.961081 # ok 320 # SKIP Disabled ZA for VL 1712
6213 12:28:21.961167 # ok 321 # SKIP Get and set data for VL 1712
6214 12:28:21.961273 # ok 322 Set VL 1728
6215 12:28:21.961362 # ok 323 # SKIP Disabled ZA for VL 1728
6216 12:28:21.961448 # ok 324 # SKIP Get and set data for VL 1728
6217 12:28:21.961554 # ok 325 Set VL 1744
6218 12:28:21.968214 # ok 326 # SKIP Disabled ZA for VL 1744
6219 12:28:21.968776 # ok 327 # SKIP Get and set data for VL 1744
6220 12:28:21.968890 # ok 328 Set VL 1760
6221 12:28:21.968981 # ok 329 # SKIP Disabled ZA for VL 1760
6222 12:28:21.969261 # ok 330 # SKIP Get and set data for VL 1760
6223 12:28:21.969358 # ok 331 Set VL 1776
6224 12:28:21.969446 # ok 332 # SKIP Disabled ZA for VL 1776
6225 12:28:21.969538 # ok 333 # SKIP Get and set data for VL 1776
6226 12:28:21.969615 # ok 334 Set VL 1792
6227 12:28:21.969701 # ok 335 # SKIP Disabled ZA for VL 1792
6228 12:28:21.969772 # ok 336 # SKIP Get and set data for VL 1792
6229 12:28:21.969844 # ok 337 Set VL 1808
6230 12:28:21.976815 # ok 338 # SKIP Disabled ZA for VL 1808
6231 12:28:21.977070 # ok 339 # SKIP Get and set data for VL 1808
6232 12:28:21.977380 # ok 340 Set VL 1824
6233 12:28:21.977482 # ok 341 # SKIP Disabled ZA for VL 1824
6234 12:28:21.977561 # ok 342 # SKIP Get and set data for VL 1824
6235 12:28:21.977637 # ok 343 Set VL 1840
6236 12:28:21.977720 # ok 344 # SKIP Disabled ZA for VL 1840
6237 12:28:21.977807 # ok 345 # SKIP Get and set data for VL 1840
6238 12:28:21.985409 # ok 346 Set VL 1856
6239 12:28:21.985723 # ok 347 # SKIP Disabled ZA for VL 1856
6240 12:28:21.986139 # ok 348 # SKIP Get and set data for VL 1856
6241 12:28:21.986286 # ok 349 Set VL 1872
6242 12:28:21.987237 # ok 350 # SKIP Disabled ZA for VL 1872
6243 12:28:21.987468 # ok 351 # SKIP Get and set data for VL 1872
6244 12:28:21.987697 # ok 352 Set VL 1888
6245 12:28:21.987941 # ok 353 # SKIP Disabled ZA for VL 1888
6246 12:28:21.988111 # ok 354 # SKIP Get and set data for VL 1888
6247 12:28:21.988298 # ok 355 Set VL 1904
6248 12:28:21.988490 # ok 356 # SKIP Disabled ZA for VL 1904
6249 12:28:21.988697 # ok 357 # SKIP Get and set data for VL 1904
6250 12:28:21.988843 # ok 358 Set VL 1920
6251 12:28:21.989428 # ok 359 # SKIP Disabled ZA for VL 1920
6252 12:28:21.989594 # ok 360 # SKIP Get and set data for VL 1920
6253 12:28:21.995048 # ok 361 Set VL 1936
6254 12:28:21.995534 # ok 362 # SKIP Disabled ZA for VL 1936
6255 12:28:21.995683 # ok 363 # SKIP Get and set data for VL 1936
6256 12:28:21.995817 # ok 364 Set VL 1952
6257 12:28:21.995948 # ok 365 # SKIP Disabled ZA for VL 1952
6258 12:28:21.996079 # ok 366 # SKIP Get and set data for VL 1952
6259 12:28:21.996253 # ok 367 Set VL 1968
6260 12:28:21.996451 # ok 368 # SKIP Disabled ZA for VL 1968
6261 12:28:21.996607 # ok 369 # SKIP Get and set data for VL 1968
6262 12:28:21.996736 # ok 370 Set VL 1984
6263 12:28:21.996953 # ok 371 # SKIP Disabled ZA for VL 1984
6264 12:28:21.997156 # ok 372 # SKIP Get and set data for VL 1984
6265 12:28:21.997332 # ok 373 Set VL 2000
6266 12:28:21.997527 # ok 374 # SKIP Disabled ZA for VL 2000
6267 12:28:21.997706 # ok 375 # SKIP Get and set data for VL 2000
6268 12:28:21.997839 # ok 376 Set VL 2016
6269 12:28:21.997960 # ok 377 # SKIP Disabled ZA for VL 2016
6270 12:28:21.998080 # ok 378 # SKIP Get and set data for VL 2016
6271 12:28:21.998224 # ok 379 Set VL 2032
6272 12:28:21.998350 # ok 380 # SKIP Disabled ZA for VL 2032
6273 12:28:21.998475 # ok 381 # SKIP Get and set data for VL 2032
6274 12:28:21.998592 # ok 382 Set VL 2048
6275 12:28:21.998709 # ok 383 # SKIP Disabled ZA for VL 2048
6276 12:28:22.003331 # ok 384 # SKIP Get and set data for VL 2048
6277 12:28:22.003668 # ok 385 Set VL 2064
6278 12:28:22.004108 # ok 386 # SKIP Disabled ZA for VL 2064
6279 12:28:22.004313 # ok 387 # SKIP Get and set data for VL 2064
6280 12:28:22.004490 # ok 388 Set VL 2080
6281 12:28:22.004658 # ok 389 # SKIP Disabled ZA for VL 2080
6282 12:28:22.004836 # ok 390 # SKIP Get and set data for VL 2080
6283 12:28:22.004998 # ok 391 Set VL 2096
6284 12:28:22.005152 # ok 392 # SKIP Disabled ZA for VL 2096
6285 12:28:22.005338 # ok 393 # SKIP Get and set data for VL 2096
6286 12:28:22.005495 # ok 394 Set VL 2112
6287 12:28:22.005614 # ok 395 # SKIP Disabled ZA for VL 2112
6288 12:28:22.005807 # ok 396 # SKIP Get and set data for VL 2112
6289 12:28:22.006003 # ok 397 Set VL 2128
6290 12:28:22.006163 # ok 398 # SKIP Disabled ZA for VL 2128
6291 12:28:22.006308 # ok 399 # SKIP Get and set data for VL 2128
6292 12:28:22.006456 # ok 400 Set VL 2144
6293 12:28:22.006639 # ok 401 # SKIP Disabled ZA for VL 2144
6294 12:28:22.006778 # ok 402 # SKIP Get and set data for VL 2144
6295 12:28:22.006924 # ok 403 Set VL 2160
6296 12:28:22.007066 # ok 404 # SKIP Disabled ZA for VL 2160
6297 12:28:22.007210 # ok 405 # SKIP Get and set data for VL 2160
6298 12:28:22.011505 # ok 406 Set VL 2176
6299 12:28:22.012347 # ok 407 # SKIP Disabled ZA for VL 2176
6300 12:28:22.012554 # ok 408 # SKIP Get and set data for VL 2176
6301 12:28:22.012742 # ok 409 Set VL 2192
6302 12:28:22.012908 # ok 410 # SKIP Disabled ZA for VL 2192
6303 12:28:22.013071 # ok 411 # SKIP Get and set data for VL 2192
6304 12:28:22.013235 # ok 412 Set VL 2208
6305 12:28:22.013444 # ok 413 # SKIP Disabled ZA for VL 2208
6306 12:28:22.013579 # ok 414 # SKIP Get and set data for VL 2208
6307 12:28:22.013758 # ok 415 Set VL 2224
6308 12:28:22.013890 # ok 416 # SKIP Disabled ZA for VL 2224
6309 12:28:22.014008 # ok 417 # SKIP Get and set data for VL 2224
6310 12:28:22.014122 # ok 418 Set VL 2240
6311 12:28:22.014266 # ok 419 # SKIP Disabled ZA for VL 2240
6312 12:28:22.014452 # ok 420 # SKIP Get and set data for VL 2240
6313 12:28:22.014618 # ok 421 Set VL 2256
6314 12:28:22.014778 # ok 422 # SKIP Disabled ZA for VL 2256
6315 12:28:22.014942 # ok 423 # SKIP Get and set data for VL 2256
6316 12:28:22.015101 # ok 424 Set VL 2272
6317 12:28:22.015253 # ok 425 # SKIP Disabled ZA for VL 2272
6318 12:28:22.015454 # ok 426 # SKIP Get and set data for VL 2272
6319 12:28:22.015631 # ok 427 Set VL 2288
6320 12:28:22.015806 # ok 428 # SKIP Disabled ZA for VL 2288
6321 12:28:22.015981 # ok 429 # SKIP Get and set data for VL 2288
6322 12:28:22.016205 # ok 430 Set VL 2304
6323 12:28:22.016392 # ok 431 # SKIP Disabled ZA for VL 2304
6324 12:28:22.016568 # ok 432 # SKIP Get and set data for VL 2304
6325 12:28:22.016788 # ok 433 Set VL 2320
6326 12:28:22.016994 # ok 434 # SKIP Disabled ZA for VL 2320
6327 12:28:22.017201 # ok 435 # SKIP Get and set data for VL 2320
6328 12:28:22.017419 # ok 436 Set VL 2336
6329 12:28:22.017622 # ok 437 # SKIP Disabled ZA for VL 2336
6330 12:28:22.017768 # ok 438 # SKIP Get and set data for VL 2336
6331 12:28:22.017886 # ok 439 Set VL 2352
6332 12:28:22.018001 # ok 440 # SKIP Disabled ZA for VL 2352
6333 12:28:22.018115 # ok 441 # SKIP Get and set data for VL 2352
6334 12:28:22.018227 # ok 442 Set VL 2368
6335 12:28:22.018340 # ok 443 # SKIP Disabled ZA for VL 2368
6336 12:28:22.018453 # ok 444 # SKIP Get and set data for VL 2368
6337 12:28:22.018564 # ok 445 Set VL 2384
6338 12:28:22.018675 # ok 446 # SKIP Disabled ZA for VL 2384
6339 12:28:22.018788 # ok 447 # SKIP Get and set data for VL 2384
6340 12:28:22.018899 # ok 448 Set VL 2400
6341 12:28:22.019011 # ok 449 # SKIP Disabled ZA for VL 2400
6342 12:28:22.019124 # ok 450 # SKIP Get and set data for VL 2400
6343 12:28:22.019237 # ok 451 Set VL 2416
6344 12:28:22.019350 # ok 452 # SKIP Disabled ZA for VL 2416
6345 12:28:22.019463 # ok 453 # SKIP Get and set data for VL 2416
6346 12:28:22.019576 # ok 454 Set VL 2432
6347 12:28:22.019688 # ok 455 # SKIP Disabled ZA for VL 2432
6348 12:28:22.019800 # ok 456 # SKIP Get and set data for VL 2432
6349 12:28:22.019913 # ok 457 Set VL 2448
6350 12:28:22.020025 # ok 458 # SKIP Disabled ZA for VL 2448
6351 12:28:22.020138 # ok 459 # SKIP Get and set data for VL 2448
6352 12:28:22.020250 # ok 460 Set VL 2464
6353 12:28:22.020590 # ok 461 # SKIP Disabled ZA for VL 2464
6354 12:28:22.020715 # ok 462 # SKIP Get and set data for VL 2464
6355 12:28:22.027259 # ok 463 Set VL 2480
6356 12:28:22.027810 # ok 464 # SKIP Disabled ZA for VL 2480
6357 12:28:22.027926 # ok 465 # SKIP Get and set data for VL 2480
6358 12:28:22.028023 # ok 466 Set VL 2496
6359 12:28:22.028113 # ok 467 # SKIP Disabled ZA for VL 2496
6360 12:28:22.028204 # ok 468 # SKIP Get and set data for VL 2496
6361 12:28:22.028292 # ok 469 Set VL 2512
6362 12:28:22.028381 # ok 470 # SKIP Disabled ZA for VL 2512
6363 12:28:22.028497 # ok 471 # SKIP Get and set data for VL 2512
6364 12:28:22.028588 # ok 472 Set VL 2528
6365 12:28:22.028675 # ok 473 # SKIP Disabled ZA for VL 2528
6366 12:28:22.028762 # ok 474 # SKIP Get and set data for VL 2528
6367 12:28:22.028852 # ok 475 Set VL 2544
6368 12:28:22.028941 # ok 476 # SKIP Disabled ZA for VL 2544
6369 12:28:22.029048 # ok 477 # SKIP Get and set data for VL 2544
6370 12:28:22.029137 # ok 478 Set VL 2560
6371 12:28:22.029225 # ok 479 # SKIP Disabled ZA for VL 2560
6372 12:28:22.029311 # ok 480 # SKIP Get and set data for VL 2560
6373 12:28:22.029399 # ok 481 Set VL 2576
6374 12:28:22.029491 # ok 482 # SKIP Disabled ZA for VL 2576
6375 12:28:22.029576 # ok 483 # SKIP Get and set data for VL 2576
6376 12:28:22.029688 # ok 484 Set VL 2592
6377 12:28:22.029777 # ok 485 # SKIP Disabled ZA for VL 2592
6378 12:28:22.029866 # ok 486 # SKIP Get and set data for VL 2592
6379 12:28:22.029956 # ok 487 Set VL 2608
6380 12:28:22.035662 # ok 488 # SKIP Disabled ZA for VL 2608
6381 12:28:22.035897 # ok 489 # SKIP Get and set data for VL 2608
6382 12:28:22.035995 # ok 490 Set VL 2624
6383 12:28:22.036296 # ok 491 # SKIP Disabled ZA for VL 2624
6384 12:28:22.036408 # ok 492 # SKIP Get and set data for VL 2624
6385 12:28:22.036505 # ok 493 Set VL 2640
6386 12:28:22.036598 # ok 494 # SKIP Disabled ZA for VL 2640
6387 12:28:22.036686 # ok 495 # SKIP Get and set data for VL 2640
6388 12:28:22.036774 # ok 496 Set VL 2656
6389 12:28:22.036861 # ok 497 # SKIP Disabled ZA for VL 2656
6390 12:28:22.036967 # ok 498 # SKIP Get and set data for VL 2656
6391 12:28:22.037059 # ok 499 Set VL 2672
6392 12:28:22.037145 # ok 500 # SKIP Disabled ZA for VL 2672
6393 12:28:22.037231 # ok 501 # SKIP Get and set data for VL 2672
6394 12:28:22.037316 # ok 502 Set VL 2688
6395 12:28:22.037403 # ok 503 # SKIP Disabled ZA for VL 2688
6396 12:28:22.037501 # ok 504 # SKIP Get and set data for VL 2688
6397 12:28:22.037589 # ok 505 Set VL 2704
6398 12:28:22.037701 # ok 506 # SKIP Disabled ZA for VL 2704
6399 12:28:22.037793 # ok 507 # SKIP Get and set data for VL 2704
6400 12:28:22.037881 # ok 508 Set VL 2720
6401 12:28:22.037971 # ok 509 # SKIP Disabled ZA for VL 2720
6402 12:28:22.048099 # ok 510 # SKIP Get and set data for VL 2720
6403 12:28:22.048337 # ok 511 Set VL 2736
6404 12:28:22.048432 # ok 512 # SKIP Disabled ZA for VL 2736
6405 12:28:22.048548 # ok 513 # SKIP Get and set data for VL 2736
6406 12:28:22.048642 # ok 514 Set VL 2752
6407 12:28:22.048730 # ok 515 # SKIP Disabled ZA for VL 2752
6408 12:28:22.048816 # ok 516 # SKIP Get and set data for VL 2752
6409 12:28:22.048907 # ok 517 Set VL 2768
6410 12:28:22.049016 # ok 518 # SKIP Disabled ZA for VL 2768
6411 12:28:22.049127 # ok 519 # SKIP Get and set data for VL 2768
6412 12:28:22.049222 # ok 520 Set VL 2784
6413 12:28:22.049309 # ok 521 # SKIP Disabled ZA for VL 2784
6414 12:28:22.049393 # ok 522 # SKIP Get and set data for VL 2784
6415 12:28:22.049503 # ok 523 Set VL 2800
6416 12:28:22.049594 # ok 524 # SKIP Disabled ZA for VL 2800
6417 12:28:22.049686 # ok 525 # SKIP Get and set data for VL 2800
6418 12:28:22.055473 # ok 526 Set VL 2816
6419 12:28:22.055728 # ok 527 # SKIP Disabled ZA for VL 2816
6420 12:28:22.056046 # ok 528 # SKIP Get and set data for VL 2816
6421 12:28:22.056155 # ok 529 Set VL 2832
6422 12:28:22.056246 # ok 530 # SKIP Disabled ZA for VL 2832
6423 12:28:22.056338 # ok 531 # SKIP Get and set data for VL 2832
6424 12:28:22.056427 # ok 532 Set VL 2848
6425 12:28:22.056534 # ok 533 # SKIP Disabled ZA for VL 2848
6426 12:28:22.056624 # ok 534 # SKIP Get and set data for VL 2848
6427 12:28:22.056710 # ok 535 Set VL 2864
6428 12:28:22.056795 # ok 536 # SKIP Disabled ZA for VL 2864
6429 12:28:22.056897 # ok 537 # SKIP Get and set data for VL 2864
6430 12:28:22.056988 # ok 538 Set VL 2880
6431 12:28:22.057076 # ok 539 # SKIP Disabled ZA for VL 2880
6432 12:28:22.057177 # ok 540 # SKIP Get and set data for VL 2880
6433 12:28:22.057265 # ok 541 Set VL 2896
6434 12:28:22.057351 # ok 542 # SKIP Disabled ZA for VL 2896
6435 12:28:22.057455 # ok 543 # SKIP Get and set data for VL 2896
6436 12:28:22.057544 # ok 544 Set VL 2912
6437 12:28:22.057631 # ok 545 # SKIP Disabled ZA for VL 2912
6438 12:28:22.063186 # ok 546 # SKIP Get and set data for VL 2912
6439 12:28:22.063425 # ok 547 Set VL 2928
6440 12:28:22.063739 # ok 548 # SKIP Disabled ZA for VL 2928
6441 12:28:22.063851 # ok 549 # SKIP Get and set data for VL 2928
6442 12:28:22.063942 # ok 550 Set VL 2944
6443 12:28:22.064030 # ok 551 # SKIP Disabled ZA for VL 2944
6444 12:28:22.064116 # ok 552 # SKIP Get and set data for VL 2944
6445 12:28:22.064208 # ok 553 Set VL 2960
6446 12:28:22.064314 # ok 554 # SKIP Disabled ZA for VL 2960
6447 12:28:22.064403 # ok 555 # SKIP Get and set data for VL 2960
6448 12:28:22.064492 # ok 556 Set VL 2976
6449 12:28:22.064581 # ok 557 # SKIP Disabled ZA for VL 2976
6450 12:28:22.064669 # ok 558 # SKIP Get and set data for VL 2976
6451 12:28:22.064758 # ok 559 Set VL 2992
6452 12:28:22.064862 # ok 560 # SKIP Disabled ZA for VL 2992
6453 12:28:22.064950 # ok 561 # SKIP Get and set data for VL 2992
6454 12:28:22.065036 # ok 562 Set VL 3008
6455 12:28:22.065124 # ok 563 # SKIP Disabled ZA for VL 3008
6456 12:28:22.065214 # ok 564 # SKIP Get and set data for VL 3008
6457 12:28:22.065300 # ok 565 Set VL 3024
6458 12:28:22.065404 # ok 566 # SKIP Disabled ZA for VL 3024
6459 12:28:22.065494 # ok 567 # SKIP Get and set data for VL 3024
6460 12:28:22.065580 # ok 568 Set VL 3040
6461 12:28:22.065672 # ok 569 # SKIP Disabled ZA for VL 3040
6462 12:28:22.065771 # ok 570 # SKIP Get and set data for VL 3040
6463 12:28:22.071493 # ok 571 Set VL 3056
6464 12:28:22.071739 # ok 572 # SKIP Disabled ZA for VL 3056
6465 12:28:22.072049 # ok 573 # SKIP Get and set data for VL 3056
6466 12:28:22.072158 # ok 574 Set VL 3072
6467 12:28:22.072250 # ok 575 # SKIP Disabled ZA for VL 3072
6468 12:28:22.072338 # ok 576 # SKIP Get and set data for VL 3072
6469 12:28:22.072424 # ok 577 Set VL 3088
6470 12:28:22.072514 # ok 578 # SKIP Disabled ZA for VL 3088
6471 12:28:22.072624 # ok 579 # SKIP Get and set data for VL 3088
6472 12:28:22.072713 # ok 580 Set VL 3104
6473 12:28:22.072799 # ok 581 # SKIP Disabled ZA for VL 3104
6474 12:28:22.072885 # ok 582 # SKIP Get and set data for VL 3104
6475 12:28:22.072974 # ok 583 Set VL 3120
6476 12:28:22.073065 # ok 584 # SKIP Disabled ZA for VL 3120
6477 12:28:22.073170 # ok 585 # SKIP Get and set data for VL 3120
6478 12:28:22.073260 # ok 586 Set VL 3136
6479 12:28:22.073347 # ok 587 # SKIP Disabled ZA for VL 3136
6480 12:28:22.073433 # ok 588 # SKIP Get and set data for VL 3136
6481 12:28:22.073523 # ok 589 Set VL 3152
6482 12:28:22.080592 # ok 590 # SKIP Disabled ZA for VL 3152
6483 12:28:22.081063 # ok 591 # SKIP Get and set data for VL 3152
6484 12:28:22.081174 # ok 592 Set VL 3168
6485 12:28:22.081269 # ok 593 # SKIP Disabled ZA for VL 3168
6486 12:28:22.081359 # ok 594 # SKIP Get and set data for VL 3168
6487 12:28:22.081448 # ok 595 Set VL 3184
6488 12:28:22.081556 # ok 596 # SKIP Disabled ZA for VL 3184
6489 12:28:22.081653 # ok 597 # SKIP Get and set data for VL 3184
6490 12:28:22.081745 # ok 598 Set VL 3200
6491 12:28:22.087456 # ok 599 # SKIP Disabled ZA for VL 3200
6492 12:28:22.088028 # ok 600 # SKIP Get and set data for VL 3200
6493 12:28:22.088136 # ok 601 Set VL 3216
6494 12:28:22.088224 # ok 602 # SKIP Disabled ZA for VL 3216
6495 12:28:22.088307 # ok 603 # SKIP Get and set data for VL 3216
6496 12:28:22.088405 # ok 604 Set VL 3232
6497 12:28:22.088490 # ok 605 # SKIP Disabled ZA for VL 3232
6498 12:28:22.088575 # ok 606 # SKIP Get and set data for VL 3232
6499 12:28:22.088716 # ok 607 Set VL 3248
6500 12:28:22.088810 # ok 608 # SKIP Disabled ZA for VL 3248
6501 12:28:22.088910 # ok 609 # SKIP Get and set data for VL 3248
6502 12:28:22.088996 # ok 610 Set VL 3264
6503 12:28:22.089092 # ok 611 # SKIP Disabled ZA for VL 3264
6504 12:28:22.089194 # ok 612 # SKIP Get and set data for VL 3264
6505 12:28:22.089290 # ok 613 Set VL 3280
6506 12:28:22.089394 # ok 614 # SKIP Disabled ZA for VL 3280
6507 12:28:22.089495 # ok 615 # SKIP Get and set data for VL 3280
6508 12:28:22.089597 # ok 616 Set VL 3296
6509 12:28:22.092222 # ok 617 # SKIP Disabled ZA for VL 3296
6510 12:28:22.092653 # ok 618 # SKIP Get and set data for VL 3296
6511 12:28:22.092763 # ok 619 Set VL 3312
6512 12:28:22.092853 # ok 620 # SKIP Disabled ZA for VL 3312
6513 12:28:22.092941 # ok 621 # SKIP Get and set data for VL 3312
6514 12:28:22.093030 # ok 622 Set VL 3328
6515 12:28:22.093137 # ok 623 # SKIP Disabled ZA for VL 3328
6516 12:28:22.093229 # ok 624 # SKIP Get and set data for VL 3328
6517 12:28:22.093317 # ok 625 Set VL 3344
6518 12:28:22.093404 # ok 626 # SKIP Disabled ZA for VL 3344
6519 12:28:22.093514 # ok 627 # SKIP Get and set data for VL 3344
6520 12:28:22.093602 # ok 628 Set VL 3360
6521 12:28:22.093699 # ok 629 # SKIP Disabled ZA for VL 3360
6522 12:28:22.093785 # ok 630 # SKIP Get and set data for VL 3360
6523 12:28:22.097435 # ok 631 Set VL 3376
6524 12:28:22.097684 # ok 632 # SKIP Disabled ZA for VL 3376
6525 12:28:22.104669 # ok 633 # SKIP Get and set data for VL 3376
6526 12:28:22.104928 # ok 634 Set VL 3392
6527 12:28:22.105246 # ok 635 # SKIP Disabled ZA for VL 3392
6528 12:28:22.105355 # ok 636 # SKIP Get and set data for VL 3392
6529 12:28:22.105449 # ok 637 Set VL 3408
6530 12:28:22.105542 # ok 638 # SKIP Disabled ZA for VL 3408
6531 12:28:22.105638 # ok 639 # SKIP Get and set data for VL 3408
6532 12:28:22.105734 # ok 640 Set VL 3424
6533 12:28:22.105836 # ok 641 # SKIP Disabled ZA for VL 3424
6534 12:28:22.105930 # ok 642 # SKIP Get and set data for VL 3424
6535 12:28:22.107459 # ok 643 Set VL 3440
6536 12:28:22.107931 # ok 644 # SKIP Disabled ZA for VL 3440
6537 12:28:22.108139 # ok 645 # SKIP Get and set data for VL 3440
6538 12:28:22.108346 # ok 646 Set VL 3456
6539 12:28:22.108565 # ok 647 # SKIP Disabled ZA for VL 3456
6540 12:28:22.108811 # ok 648 # SKIP Get and set data for VL 3456
6541 12:28:22.109030 # ok 649 Set VL 3472
6542 12:28:22.109251 # ok 650 # SKIP Disabled ZA for VL 3472
6543 12:28:22.109473 # ok 651 # SKIP Get and set data for VL 3472
6544 12:28:22.109638 # ok 652 Set VL 3488
6545 12:28:22.109785 # ok 653 # SKIP Disabled ZA for VL 3488
6546 12:28:22.109902 # ok 654 # SKIP Get and set data for VL 3488
6547 12:28:22.110051 # ok 655 Set VL 3504
6548 12:28:22.110182 # ok 656 # SKIP Disabled ZA for VL 3504
6549 12:28:22.110299 # ok 657 # SKIP Get and set data for VL 3504
6550 12:28:22.110414 # ok 658 Set VL 3520
6551 12:28:22.110557 # ok 659 # SKIP Disabled ZA for VL 3520
6552 12:28:22.110682 # ok 660 # SKIP Get and set data for VL 3520
6553 12:28:22.110798 # ok 661 Set VL 3536
6554 12:28:22.110911 # ok 662 # SKIP Disabled ZA for VL 3536
6555 12:28:22.111025 # ok 663 # SKIP Get and set data for VL 3536
6556 12:28:22.111138 # ok 664 Set VL 3552
6557 12:28:22.111252 # ok 665 # SKIP Disabled ZA for VL 3552
6558 12:28:22.111365 # ok 666 # SKIP Get and set data for VL 3552
6559 12:28:22.123097 # ok 667 Set VL 3568
6560 12:28:22.123645 # ok 668 # SKIP Disabled ZA for VL 3568
6561 12:28:22.124056 # ok 669 # SKIP Get and set data for VL 3568
6562 12:28:22.124258 # ok 670 Set VL 3584
6563 12:28:22.124436 # ok 671 # SKIP Disabled ZA for VL 3584
6564 12:28:22.124610 # ok 672 # SKIP Get and set data for VL 3584
6565 12:28:22.124814 # ok 673 Set VL 3600
6566 12:28:22.125036 # ok 674 # SKIP Disabled ZA for VL 3600
6567 12:28:22.125251 # ok 675 # SKIP Get and set data for VL 3600
6568 12:28:22.125456 # ok 676 Set VL 3616
6569 12:28:22.125685 # ok 677 # SKIP Disabled ZA for VL 3616
6570 12:28:22.125896 # ok 678 # SKIP Get and set data for VL 3616
6571 12:28:22.126080 # ok 679 Set VL 3632
6572 12:28:22.126226 # ok 680 # SKIP Disabled ZA for VL 3632
6573 12:28:22.126371 # ok 681 # SKIP Get and set data for VL 3632
6574 12:28:22.126514 # ok 682 Set VL 3648
6575 12:28:22.126656 # ok 683 # SKIP Disabled ZA for VL 3648
6576 12:28:22.126801 # ok 684 # SKIP Get and set data for VL 3648
6577 12:28:22.126944 # ok 685 Set VL 3664
6578 12:28:22.127085 # ok 686 # SKIP Disabled ZA for VL 3664
6579 12:28:22.127226 # ok 687 # SKIP Get and set data for VL 3664
6580 12:28:22.127367 # ok 688 Set VL 3680
6581 12:28:22.127508 # ok 689 # SKIP Disabled ZA for VL 3680
6582 12:28:22.131319 # ok 690 # SKIP Get and set data for VL 3680
6583 12:28:22.131565 # ok 691 Set VL 3696
6584 12:28:22.131806 # ok 692 # SKIP Disabled ZA for VL 3696
6585 12:28:22.132009 # ok 693 # SKIP Get and set data for VL 3696
6586 12:28:22.132230 # ok 694 Set VL 3712
6587 12:28:22.132424 # ok 695 # SKIP Disabled ZA for VL 3712
6588 12:28:22.132665 # ok 696 # SKIP Get and set data for VL 3712
6589 12:28:22.132881 # ok 697 Set VL 3728
6590 12:28:22.133104 # ok 698 # SKIP Disabled ZA for VL 3728
6591 12:28:22.133360 # ok 699 # SKIP Get and set data for VL 3728
6592 12:28:22.133573 # ok 700 Set VL 3744
6593 12:28:22.133758 # ok 701 # SKIP Disabled ZA for VL 3744
6594 12:28:22.133889 # ok 702 # SKIP Get and set data for VL 3744
6595 12:28:22.134036 # ok 703 Set VL 3760
6596 12:28:22.134157 # ok 704 # SKIP Disabled ZA for VL 3760
6597 12:28:22.134272 # ok 705 # SKIP Get and set data for VL 3760
6598 12:28:22.134387 # ok 706 Set VL 3776
6599 12:28:22.134501 # ok 707 # SKIP Disabled ZA for VL 3776
6600 12:28:22.134614 # ok 708 # SKIP Get and set data for VL 3776
6601 12:28:22.134728 # ok 709 Set VL 3792
6602 12:28:22.140838 # ok 710 # SKIP Disabled ZA for VL 3792
6603 12:28:22.141422 # ok 711 # SKIP Get and set data for VL 3792
6604 12:28:22.141581 # ok 712 Set VL 3808
6605 12:28:22.141766 # ok 713 # SKIP Disabled ZA for VL 3808
6606 12:28:22.141900 # ok 714 # SKIP Get and set data for VL 3808
6607 12:28:22.142016 # ok 715 Set VL 3824
6608 12:28:22.142129 # ok 716 # SKIP Disabled ZA for VL 3824
6609 12:28:22.151879 # ok 717 # SKIP Get and set data for VL 3824
6610 12:28:22.152161 # ok 718 Set VL 3840
6611 12:28:22.152535 # ok 719 # SKIP Disabled ZA for VL 3840
6612 12:28:22.153080 # ok 720 # SKIP Get and set data for VL 3840
6613 12:28:22.153275 # ok 721 Set VL 3856
6614 12:28:22.153437 # ok 722 # SKIP Disabled ZA for VL 3856
6615 12:28:22.153603 # ok 723 # SKIP Get and set data for VL 3856
6616 12:28:22.153789 # ok 724 Set VL 3872
6617 12:28:22.153957 # ok 725 # SKIP Disabled ZA for VL 3872
6618 12:28:22.154123 # ok 726 # SKIP Get and set data for VL 3872
6619 12:28:22.154287 # ok 727 Set VL 3888
6620 12:28:22.154451 # ok 728 # SKIP Disabled ZA for VL 3888
6621 12:28:22.154618 # ok 729 # SKIP Get and set data for VL 3888
6622 12:28:22.154791 # ok 730 Set VL 3904
6623 12:28:22.154951 # ok 731 # SKIP Disabled ZA for VL 3904
6624 12:28:22.155116 # ok 732 # SKIP Get and set data for VL 3904
6625 12:28:22.155252 # ok 733 Set VL 3920
6626 12:28:22.155404 # ok 734 # SKIP Disabled ZA for VL 3920
6627 12:28:22.163647 # ok 735 # SKIP Get and set data for VL 3920
6628 12:28:22.163930 # ok 736 Set VL 3936
6629 12:28:22.164060 # ok 737 # SKIP Disabled ZA for VL 3936
6630 12:28:22.164211 # ok 738 # SKIP Get and set data for VL 3936
6631 12:28:22.164339 # ok 739 Set VL 3952
6632 12:28:22.164465 # ok 740 # SKIP Disabled ZA for VL 3952
6633 12:28:22.164589 # ok 741 # SKIP Get and set data for VL 3952
6634 12:28:22.164715 # ok 742 Set VL 3968
6635 12:28:22.164839 # ok 743 # SKIP Disabled ZA for VL 3968
6636 12:28:22.164987 # ok 744 # SKIP Get and set data for VL 3968
6637 12:28:22.165116 # ok 745 Set VL 3984
6638 12:28:22.165238 # ok 746 # SKIP Disabled ZA for VL 3984
6639 12:28:22.165358 # ok 747 # SKIP Get and set data for VL 3984
6640 12:28:22.165478 # ok 748 Set VL 4000
6641 12:28:22.165597 # ok 749 # SKIP Disabled ZA for VL 4000
6642 12:28:22.165735 # ok 750 # SKIP Get and set data for VL 4000
6643 12:28:22.165826 # ok 751 Set VL 4016
6644 12:28:22.165913 # ok 752 # SKIP Disabled ZA for VL 4016
6645 12:28:22.165998 # ok 753 # SKIP Get and set data for VL 4016
6646 12:28:22.166083 # ok 754 Set VL 4032
6647 12:28:22.175298 # ok 755 # SKIP Disabled ZA for VL 4032
6648 12:28:22.175838 # ok 756 # SKIP Get and set data for VL 4032
6649 12:28:22.176063 # ok 757 Set VL 4048
6650 12:28:22.176241 # ok 758 # SKIP Disabled ZA for VL 4048
6651 12:28:22.176407 # ok 759 # SKIP Get and set data for VL 4048
6652 12:28:22.176580 # ok 760 Set VL 4064
6653 12:28:22.176788 # ok 761 # SKIP Disabled ZA for VL 4064
6654 12:28:22.176969 # ok 762 # SKIP Get and set data for VL 4064
6655 12:28:22.177146 # ok 763 Set VL 4080
6656 12:28:22.177330 # ok 764 # SKIP Disabled ZA for VL 4080
6657 12:28:22.177505 # ok 765 # SKIP Get and set data for VL 4080
6658 12:28:22.177686 # ok 766 Set VL 4096
6659 12:28:22.177861 # ok 767 # SKIP Disabled ZA for VL 4096
6660 12:28:22.178036 # ok 768 # SKIP Get and set data for VL 4096
6661 12:28:22.178246 # ok 769 Set VL 4112
6662 12:28:22.178423 # ok 770 # SKIP Disabled ZA for VL 4112
6663 12:28:22.178595 # ok 771 # SKIP Get and set data for VL 4112
6664 12:28:22.178771 # ok 772 Set VL 4128
6665 12:28:22.178945 # ok 773 # SKIP Disabled ZA for VL 4128
6666 12:28:22.179118 # ok 774 # SKIP Get and set data for VL 4128
6667 12:28:22.179290 # ok 775 Set VL 4144
6668 12:28:22.191805 # ok 776 # SKIP Disabled ZA for VL 4144
6669 12:28:22.192141 # ok 777 # SKIP Get and set data for VL 4144
6670 12:28:22.192358 # ok 778 Set VL 4160
6671 12:28:22.192538 # ok 779 # SKIP Disabled ZA for VL 4160
6672 12:28:22.192716 # ok 780 # SKIP Get and set data for VL 4160
6673 12:28:22.192890 # ok 781 Set VL 4176
6674 12:28:22.193047 # ok 782 # SKIP Disabled ZA for VL 4176
6675 12:28:22.193214 # ok 783 # SKIP Get and set data for VL 4176
6676 12:28:22.193424 # ok 784 Set VL 4192
6677 12:28:22.193602 # ok 785 # SKIP Disabled ZA for VL 4192
6678 12:28:22.193795 # ok 786 # SKIP Get and set data for VL 4192
6679 12:28:22.193971 # ok 787 Set VL 4208
6680 12:28:22.194145 # ok 788 # SKIP Disabled ZA for VL 4208
6681 12:28:22.194319 # ok 789 # SKIP Get and set data for VL 4208
6682 12:28:22.194489 # ok 790 Set VL 4224
6683 12:28:22.194662 # ok 791 # SKIP Disabled ZA for VL 4224
6684 12:28:22.194840 # ok 792 # SKIP Get and set data for VL 4224
6685 12:28:22.195050 # ok 793 Set VL 4240
6686 12:28:22.208916 # ok 794 # SKIP Disabled ZA for VL 4240
6687 12:28:22.209306 # ok 795 # SKIP Get and set data for VL 4240
6688 12:28:22.209489 # ok 796 Set VL 4256
6689 12:28:22.209931 # ok 797 # SKIP Disabled ZA for VL 4256
6690 12:28:22.210126 # ok 798 # SKIP Get and set data for VL 4256
6691 12:28:22.210304 # ok 799 Set VL 4272
6692 12:28:22.210483 # ok 800 # SKIP Disabled ZA for VL 4272
6693 12:28:22.210655 # ok 801 # SKIP Get and set data for VL 4272
6694 12:28:22.210834 # ok 802 Set VL 4288
6695 12:28:22.211010 # ok 803 # SKIP Disabled ZA for VL 4288
6696 12:28:22.220303 # ok 804 # SKIP Get and set data for VL 4288
6697 12:28:22.220657 # ok 805 Set VL 4304
6698 12:28:22.220985 # ok 806 # SKIP Disabled ZA for VL 4304
6699 12:28:22.221085 # ok 807 # SKIP Get and set data for VL 4304
6700 12:28:22.221176 # ok 808 Set VL 4320
6701 12:28:22.221267 # ok 809 # SKIP Disabled ZA for VL 4320
6702 12:28:22.221358 # ok 810 # SKIP Get and set data for VL 4320
6703 12:28:22.221445 # ok 811 Set VL 4336
6704 12:28:22.221531 # ok 812 # SKIP Disabled ZA for VL 4336
6705 12:28:22.221616 # ok 813 # SKIP Get and set data for VL 4336
6706 12:28:22.221740 # ok 814 Set VL 4352
6707 12:28:22.221835 # ok 815 # SKIP Disabled ZA for VL 4352
6708 12:28:22.221922 # ok 816 # SKIP Get and set data for VL 4352
6709 12:28:22.222008 # ok 817 Set VL 4368
6710 12:28:22.222094 # ok 818 # SKIP Disabled ZA for VL 4368
6711 12:28:22.222180 # ok 819 # SKIP Get and set data for VL 4368
6712 12:28:22.227577 # ok 820 Set VL 4384
6713 12:28:22.228035 # ok 821 # SKIP Disabled ZA for VL 4384
6714 12:28:22.228785 # ok 822 # SKIP Get and set data for VL 4384
6715 12:28:22.229116 # ok 823 Set VL 4400
6716 12:28:22.229228 # ok 824 # SKIP Disabled ZA for VL 4400
6717 12:28:22.229344 # ok 825 # SKIP Get and set data for VL 4400
6718 12:28:22.229436 # ok 826 Set VL 4416
6719 12:28:22.229549 # ok 827 # SKIP Disabled ZA for VL 4416
6720 12:28:22.229641 # ok 828 # SKIP Get and set data for VL 4416
6721 12:28:22.229743 # ok 829 Set VL 4432
6722 12:28:22.232135 # ok 830 # SKIP Disabled ZA for VL 4432
6723 12:28:22.251371 # ok 831 # SKIP Get and set data for VL 4432
6724 12:28:22.251794 # ok 832 Set VL 4448
6725 12:28:22.251912 # ok 833 # SKIP Disabled ZA for VL 4448
6726 12:28:22.252004 # ok 834 # SKIP Get and set data for VL 4448
6727 12:28:22.252090 # ok 835 Set VL 4464
6728 12:28:22.252178 # ok 836 # SKIP Disabled ZA for VL 4464
6729 12:28:22.252281 # ok 837 # SKIP Get and set data for VL 4464
6730 12:28:22.252367 # ok 838 Set VL 4480
6731 12:28:22.252449 # ok 839 # SKIP Disabled ZA for VL 4480
6732 12:28:22.252534 # ok 840 # SKIP Get and set data for VL 4480
6733 12:28:22.252620 # ok 841 Set VL 4496
6734 12:28:22.252722 # ok 842 # SKIP Disabled ZA for VL 4496
6735 12:28:22.252810 # ok 843 # SKIP Get and set data for VL 4496
6736 12:28:22.252899 # ok 844 Set VL 4512
6737 12:28:22.252998 # ok 845 # SKIP Disabled ZA for VL 4512
6738 12:28:22.253084 # ok 846 # SKIP Get and set data for VL 4512
6739 12:28:22.253371 # ok 847 Set VL 4528
6740 12:28:22.253458 # ok 848 # SKIP Disabled ZA for VL 4528
6741 12:28:22.253539 # ok 849 # SKIP Get and set data for VL 4528
6742 12:28:22.253606 # ok 850 Set VL 4544
6743 12:28:22.253696 # ok 851 # SKIP Disabled ZA for VL 4544
6744 12:28:22.267002 # ok 852 # SKIP Get and set data for VL 4544
6745 12:28:22.267248 # ok 853 Set VL 4560
6746 12:28:22.267545 # ok 854 # SKIP Disabled ZA for VL 4560
6747 12:28:22.267653 # ok 855 # SKIP Get and set data for VL 4560
6748 12:28:22.267771 # ok 856 Set VL 4576
6749 12:28:22.267879 # ok 857 # SKIP Disabled ZA for VL 4576
6750 12:28:22.267980 # ok 858 # SKIP Get and set data for VL 4576
6751 12:28:22.268081 # ok 859 Set VL 4592
6752 12:28:22.268206 # ok 860 # SKIP Disabled ZA for VL 4592
6753 12:28:22.268294 # ok 861 # SKIP Get and set data for VL 4592
6754 12:28:22.268376 # ok 862 Set VL 4608
6755 12:28:22.268453 # ok 863 # SKIP Disabled ZA for VL 4608
6756 12:28:22.268517 # ok 864 # SKIP Get and set data for VL 4608
6757 12:28:22.268579 # ok 865 Set VL 4624
6758 12:28:22.268641 # ok 866 # SKIP Disabled ZA for VL 4624
6759 12:28:22.268749 # ok 867 # SKIP Get and set data for VL 4624
6760 12:28:22.268827 # ok 868 Set VL 4640
6761 12:28:22.268921 # ok 869 # SKIP Disabled ZA for VL 4640
6762 12:28:22.269016 # ok 870 # SKIP Get and set data for VL 4640
6763 12:28:22.269108 # ok 871 Set VL 4656
6764 12:28:22.269199 # ok 872 # SKIP Disabled ZA for VL 4656
6765 12:28:22.269267 # ok 873 # SKIP Get and set data for VL 4656
6766 12:28:22.269332 # ok 874 Set VL 4672
6767 12:28:22.269394 # ok 875 # SKIP Disabled ZA for VL 4672
6768 12:28:22.269456 # ok 876 # SKIP Get and set data for VL 4672
6769 12:28:22.269531 # ok 877 Set VL 4688
6770 12:28:22.269595 # ok 878 # SKIP Disabled ZA for VL 4688
6771 12:28:22.269677 # ok 879 # SKIP Get and set data for VL 4688
6772 12:28:22.269783 # ok 880 Set VL 4704
6773 12:28:22.269899 # ok 881 # SKIP Disabled ZA for VL 4704
6774 12:28:22.269997 # ok 882 # SKIP Get and set data for VL 4704
6775 12:28:22.280489 # ok 883 Set VL 4720
6776 12:28:22.280714 # ok 884 # SKIP Disabled ZA for VL 4720
6777 12:28:22.280815 # ok 885 # SKIP Get and set data for VL 4720
6778 12:28:22.280927 # ok 886 Set VL 4736
6779 12:28:22.281067 # ok 887 # SKIP Disabled ZA for VL 4736
6780 12:28:22.281216 # ok 888 # SKIP Get and set data for VL 4736
6781 12:28:22.281398 # ok 889 Set VL 4752
6782 12:28:22.281532 # ok 890 # SKIP Disabled ZA for VL 4752
6783 12:28:22.281642 # ok 891 # SKIP Get and set data for VL 4752
6784 12:28:22.281748 # ok 892 Set VL 4768
6785 12:28:22.281836 # ok 893 # SKIP Disabled ZA for VL 4768
6786 12:28:22.281925 # ok 894 # SKIP Get and set data for VL 4768
6787 12:28:22.282011 # ok 895 Set VL 4784
6788 12:28:22.282114 # ok 896 # SKIP Disabled ZA for VL 4784
6789 12:28:22.282204 # ok 897 # SKIP Get and set data for VL 4784
6790 12:28:22.293283 # ok 898 Set VL 4800
6791 12:28:22.293623 # ok 899 # SKIP Disabled ZA for VL 4800
6792 12:28:22.293795 # ok 900 # SKIP Get and set data for VL 4800
6793 12:28:22.294187 # ok 901 Set VL 4816
6794 12:28:22.294324 # ok 902 # SKIP Disabled ZA for VL 4816
6795 12:28:22.294444 # ok 903 # SKIP Get and set data for VL 4816
6796 12:28:22.294563 # ok 904 Set VL 4832
6797 12:28:22.296491 # ok 905 # SKIP Disabled ZA for VL 4832
6798 12:28:22.296645 # ok 906 # SKIP Get and set data for VL 4832
6799 12:28:22.296944 # ok 907 Set VL 4848
6800 12:28:22.297054 # ok 908 # SKIP Disabled ZA for VL 4848
6801 12:28:22.297143 # ok 909 # SKIP Get and set data for VL 4848
6802 12:28:22.297228 # ok 910 Set VL 4864
6803 12:28:22.297326 # ok 911 # SKIP Disabled ZA for VL 4864
6804 12:28:22.297413 # ok 912 # SKIP Get and set data for VL 4864
6805 12:28:22.297499 # ok 913 Set VL 4880
6806 12:28:22.297581 # ok 914 # SKIP Disabled ZA for VL 4880
6807 12:28:22.297691 # ok 915 # SKIP Get and set data for VL 4880
6808 12:28:22.297769 # ok 916 Set VL 4896
6809 12:28:22.303357 # ok 917 # SKIP Disabled ZA for VL 4896
6810 12:28:22.303785 # ok 918 # SKIP Get and set data for VL 4896
6811 12:28:22.303896 # ok 919 Set VL 4912
6812 12:28:22.303983 # ok 920 # SKIP Disabled ZA for VL 4912
6813 12:28:22.304067 # ok 921 # SKIP Get and set data for VL 4912
6814 12:28:22.304150 # ok 922 Set VL 4928
6815 12:28:22.304401 # ok 923 # SKIP Disabled ZA for VL 4928
6816 12:28:22.304497 # ok 924 # SKIP Get and set data for VL 4928
6817 12:28:22.304581 # ok 925 Set VL 4944
6818 12:28:22.304668 # ok 926 # SKIP Disabled ZA for VL 4944
6819 12:28:22.304769 # ok 927 # SKIP Get and set data for VL 4944
6820 12:28:22.304854 # ok 928 Set VL 4960
6821 12:28:22.304937 # ok 929 # SKIP Disabled ZA for VL 4960
6822 12:28:22.305043 # ok 930 # SKIP Get and set data for VL 4960
6823 12:28:22.305127 # ok 931 Set VL 4976
6824 12:28:22.305226 # ok 932 # SKIP Disabled ZA for VL 4976
6825 12:28:22.305312 # ok 933 # SKIP Get and set data for VL 4976
6826 12:28:22.305411 # ok 934 Set VL 4992
6827 12:28:22.305510 # ok 935 # SKIP Disabled ZA for VL 4992
6828 12:28:22.305609 # ok 936 # SKIP Get and set data for VL 4992
6829 12:28:22.309267 # ok 937 Set VL 5008
6830 12:28:22.309761 # ok 938 # SKIP Disabled ZA for VL 5008
6831 12:28:22.309876 # ok 939 # SKIP Get and set data for VL 5008
6832 12:28:22.309971 # ok 940 Set VL 5024
6833 12:28:22.310064 # ok 941 # SKIP Disabled ZA for VL 5024
6834 12:28:22.316382 # ok 942 # SKIP Get and set data for VL 5024
6835 12:28:22.316634 # ok 943 Set VL 5040
6836 12:28:22.316995 # ok 944 # SKIP Disabled ZA for VL 5040
6837 12:28:22.317220 # ok 945 # SKIP Get and set data for VL 5040
6838 12:28:22.317414 # ok 946 Set VL 5056
6839 12:28:22.317622 # ok 947 # SKIP Disabled ZA for VL 5056
6840 12:28:22.317847 # ok 948 # SKIP Get and set data for VL 5056
6841 12:28:22.318001 # ok 949 Set VL 5072
6842 12:28:22.318184 # ok 950 # SKIP Disabled ZA for VL 5072
6843 12:28:22.318323 # ok 951 # SKIP Get and set data for VL 5072
6844 12:28:22.318468 # ok 952 Set VL 5088
6845 12:28:22.318610 # ok 953 # SKIP Disabled ZA for VL 5088
6846 12:28:22.318753 # ok 954 # SKIP Get and set data for VL 5088
6847 12:28:22.318896 # ok 955 Set VL 5104
6848 12:28:22.319041 # ok 956 # SKIP Disabled ZA for VL 5104
6849 12:28:22.325249 # ok 957 # SKIP Get and set data for VL 5104
6850 12:28:22.325594 # ok 958 Set VL 5120
6851 12:28:22.325914 # ok 959 # SKIP Disabled ZA for VL 5120
6852 12:28:22.326028 # ok 960 # SKIP Get and set data for VL 5120
6853 12:28:22.326123 # ok 961 Set VL 5136
6854 12:28:22.327128 # ok 962 # SKIP Disabled ZA for VL 5136
6855 12:28:22.327456 # ok 963 # SKIP Get and set data for VL 5136
6856 12:28:22.327568 # ok 964 Set VL 5152
6857 12:28:22.327676 # ok 965 # SKIP Disabled ZA for VL 5152
6858 12:28:22.327766 # ok 966 # SKIP Get and set data for VL 5152
6859 12:28:22.327868 # ok 967 Set VL 5168
6860 12:28:22.327977 # ok 968 # SKIP Disabled ZA for VL 5168
6861 12:28:22.328083 # ok 969 # SKIP Get and set data for VL 5168
6862 12:28:22.328192 # ok 970 Set VL 5184
6863 12:28:22.328482 # ok 971 # SKIP Disabled ZA for VL 5184
6864 12:28:22.328591 # ok 972 # SKIP Get and set data for VL 5184
6865 12:28:22.328682 # ok 973 Set VL 5200
6866 12:28:22.328785 # ok 974 # SKIP Disabled ZA for VL 5200
6867 12:28:22.328888 # ok 975 # SKIP Get and set data for VL 5200
6868 12:28:22.328976 # ok 976 Set VL 5216
6869 12:28:22.329080 # ok 977 # SKIP Disabled ZA for VL 5216
6870 12:28:22.329170 # ok 978 # SKIP Get and set data for VL 5216
6871 12:28:22.329255 # ok 979 Set VL 5232
6872 12:28:22.329359 # ok 980 # SKIP Disabled ZA for VL 5232
6873 12:28:22.329447 # ok 981 # SKIP Get and set data for VL 5232
6874 12:28:22.329533 # ok 982 Set VL 5248
6875 12:28:22.329624 # ok 983 # SKIP Disabled ZA for VL 5248
6876 12:28:22.335180 # ok 984 # SKIP Get and set data for VL 5248
6877 12:28:22.335709 # ok 985 Set VL 5264
6878 12:28:22.335815 # ok 986 # SKIP Disabled ZA for VL 5264
6879 12:28:22.335906 # ok 987 # SKIP Get and set data for VL 5264
6880 12:28:22.335992 # ok 988 Set VL 5280
6881 12:28:22.336082 # ok 989 # SKIP Disabled ZA for VL 5280
6882 12:28:22.336162 # ok 990 # SKIP Get and set data for VL 5280
6883 12:28:22.336431 # ok 991 Set VL 5296
6884 12:28:22.336543 # ok 992 # SKIP Disabled ZA for VL 5296
6885 12:28:22.336632 # ok 993 # SKIP Get and set data for VL 5296
6886 12:28:22.336719 # ok 994 Set VL 5312
6887 12:28:22.336805 # ok 995 # SKIP Disabled ZA for VL 5312
6888 12:28:22.336889 # ok 996 # SKIP Get and set data for VL 5312
6889 12:28:22.336973 # ok 997 Set VL 5328
6890 12:28:22.337076 # ok 998 # SKIP Disabled ZA for VL 5328
6891 12:28:22.337162 # ok 999 # SKIP Get and set data for VL 5328
6892 12:28:22.337246 # ok 1000 Set VL 5344
6893 12:28:22.337344 # ok 1001 # SKIP Disabled ZA for VL 5344
6894 12:28:22.337428 # ok 1002 # SKIP Get and set data for VL 5344
6895 12:28:22.337511 # ok 1003 Set VL 5360
6896 12:28:22.337603 # ok 1004 # SKIP Disabled ZA for VL 5360
6897 12:28:22.337688 # ok 1005 # SKIP Get and set data for VL 5360
6898 12:28:22.343439 # ok 1006 Set VL 5376
6899 12:28:22.344062 # ok 1007 # SKIP Disabled ZA for VL 5376
6900 12:28:22.344295 # ok 1008 # SKIP Get and set data for VL 5376
6901 12:28:22.344480 # ok 1009 Set VL 5392
6902 12:28:22.344671 # ok 1010 # SKIP Disabled ZA for VL 5392
6903 12:28:22.344877 # ok 1011 # SKIP Get and set data for VL 5392
6904 12:28:22.345065 # ok 1012 Set VL 5408
6905 12:28:22.345307 # ok 1013 # SKIP Disabled ZA for VL 5408
6906 12:28:22.345509 # ok 1014 # SKIP Get and set data for VL 5408
6907 12:28:22.345697 # ok 1015 Set VL 5424
6908 12:28:22.345848 # ok 1016 # SKIP Disabled ZA for VL 5424
6909 12:28:22.345967 # ok 1017 # SKIP Get and set data for VL 5424
6910 12:28:22.346085 # ok 1018 Set VL 5440
6911 12:28:22.346198 # ok 1019 # SKIP Disabled ZA for VL 5440
6912 12:28:22.346312 # ok 1020 # SKIP Get and set data for VL 5440
6913 12:28:22.346424 # ok 1021 Set VL 5456
6914 12:28:22.346538 # ok 1022 # SKIP Disabled ZA for VL 5456
6915 12:28:22.346652 # ok 1023 # SKIP Get and set data for VL 5456
6916 12:28:22.346766 # ok 1024 Set VL 5472
6917 12:28:22.346908 # ok 1025 # SKIP Disabled ZA for VL 5472
6918 12:28:22.347029 # ok 1026 # SKIP Get and set data for VL 5472
6919 12:28:22.347144 # ok 1027 Set VL 5488
6920 12:28:22.347257 # ok 1028 # SKIP Disabled ZA for VL 5488
6921 12:28:22.351732 # ok 1029 # SKIP Get and set data for VL 5488
6922 12:28:22.351955 # ok 1030 Set VL 5504
6923 12:28:22.352256 # ok 1031 # SKIP Disabled ZA for VL 5504
6924 12:28:22.352361 # ok 1032 # SKIP Get and set data for VL 5504
6925 12:28:22.352448 # ok 1033 Set VL 5520
6926 12:28:22.352532 # ok 1034 # SKIP Disabled ZA for VL 5520
6927 12:28:22.352619 # ok 1035 # SKIP Get and set data for VL 5520
6928 12:28:22.352721 # ok 1036 Set VL 5536
6929 12:28:22.352809 # ok 1037 # SKIP Disabled ZA for VL 5536
6930 12:28:22.352895 # ok 1038 # SKIP Get and set data for VL 5536
6931 12:28:22.352980 # ok 1039 Set VL 5552
6932 12:28:22.353080 # ok 1040 # SKIP Disabled ZA for VL 5552
6933 12:28:22.353166 # ok 1041 # SKIP Get and set data for VL 5552
6934 12:28:22.353250 # ok 1042 Set VL 5568
6935 12:28:22.353348 # ok 1043 # SKIP Disabled ZA for VL 5568
6936 12:28:22.353431 # ok 1044 # SKIP Get and set data for VL 5568
6937 12:28:22.353527 # ok 1045 Set VL 5584
6938 12:28:22.353625 # ok 1046 # SKIP Disabled ZA for VL 5584
6939 12:28:22.359322 # ok 1047 # SKIP Get and set data for VL 5584
6940 12:28:22.359574 # ok 1048 Set VL 5600
6941 12:28:22.359880 # ok 1049 # SKIP Disabled ZA for VL 5600
6942 12:28:22.359983 # ok 1050 # SKIP Get and set data for VL 5600
6943 12:28:22.360083 # ok 1051 Set VL 5616
6944 12:28:22.360179 # ok 1052 # SKIP Disabled ZA for VL 5616
6945 12:28:22.361361 # ok 1053 # SKIP Get and set data for VL 5616
6946 12:28:22.361572 # ok 1054 Set VL 5632
6947 12:28:22.361752 # ok 1055 # SKIP Disabled ZA for VL 5632
6948 12:28:22.361928 # ok 1056 # SKIP Get and set data for VL 5632
6949 12:28:22.362052 # ok 1057 Set VL 5648
6950 12:28:22.367702 # ok 1058 # SKIP Disabled ZA for VL 5648
6951 12:28:22.368189 # ok 1059 # SKIP Get and set data for VL 5648
6952 12:28:22.368396 # ok 1060 Set VL 5664
6953 12:28:22.368592 # ok 1061 # SKIP Disabled ZA for VL 5664
6954 12:28:22.368770 # ok 1062 # SKIP Get and set data for VL 5664
6955 12:28:22.368933 # ok 1063 Set VL 5680
6956 12:28:22.369126 # ok 1064 # SKIP Disabled ZA for VL 5680
6957 12:28:22.369310 # ok 1065 # SKIP Get and set data for VL 5680
6958 12:28:22.369512 # ok 1066 Set VL 5696
6959 12:28:22.369716 # ok 1067 # SKIP Disabled ZA for VL 5696
6960 12:28:22.369850 # ok 1068 # SKIP Get and set data for VL 5696
6961 12:28:22.369963 # ok 1069 Set VL 5712
6962 12:28:22.370076 # ok 1070 # SKIP Disabled ZA for VL 5712
6963 12:28:22.370188 # ok 1071 # SKIP Get and set data for VL 5712
6964 12:28:22.370326 # ok 1072 Set VL 5728
6965 12:28:22.370443 # ok 1073 # SKIP Disabled ZA for VL 5728
6966 12:28:22.370557 # ok 1074 # SKIP Get and set data for VL 5728
6967 12:28:22.370668 # ok 1075 Set VL 5744
6968 12:28:22.375174 # ok 1076 # SKIP Disabled ZA for VL 5744
6969 12:28:22.375653 # ok 1077 # SKIP Get and set data for VL 5744
6970 12:28:22.375764 # ok 1078 Set VL 5760
6971 12:28:22.375871 # ok 1079 # SKIP Disabled ZA for VL 5760
6972 12:28:22.375974 # ok 1080 # SKIP Get and set data for VL 5760
6973 12:28:22.376079 # ok 1081 Set VL 5776
6974 12:28:22.376195 # ok 1082 # SKIP Disabled ZA for VL 5776
6975 12:28:22.376308 # ok 1083 # SKIP Get and set data for VL 5776
6976 12:28:22.376397 # ok 1084 Set VL 5792
6977 12:28:22.376509 # ok 1085 # SKIP Disabled ZA for VL 5792
6978 12:28:22.376628 # ok 1086 # SKIP Get and set data for VL 5792
6979 12:28:22.376729 # ok 1087 Set VL 5808
6980 12:28:22.376817 # ok 1088 # SKIP Disabled ZA for VL 5808
6981 12:28:22.376914 # ok 1089 # SKIP Get and set data for VL 5808
6982 12:28:22.376998 # ok 1090 Set VL 5824
6983 12:28:22.377080 # ok 1091 # SKIP Disabled ZA for VL 5824
6984 12:28:22.377177 # ok 1092 # SKIP Get and set data for VL 5824
6985 12:28:22.377264 # ok 1093 Set VL 5840
6986 12:28:22.377349 # ok 1094 # SKIP Disabled ZA for VL 5840
6987 12:28:22.377470 # ok 1095 # SKIP Get and set data for VL 5840
6988 12:28:22.377580 # ok 1096 Set VL 5856
6989 12:28:22.377675 # ok 1097 # SKIP Disabled ZA for VL 5856
6990 12:28:22.377744 # ok 1098 # SKIP Get and set data for VL 5856
6991 12:28:22.377821 # ok 1099 Set VL 5872
6992 12:28:22.377904 # ok 1100 # SKIP Disabled ZA for VL 5872
6993 12:28:22.379629 # ok 1101 # SKIP Get and set data for VL 5872
6994 12:28:22.379774 # ok 1102 Set VL 5888
6995 12:28:22.379880 # ok 1103 # SKIP Disabled ZA for VL 5888
6996 12:28:22.379970 # ok 1104 # SKIP Get and set data for VL 5888
6997 12:28:22.380070 # ok 1105 Set VL 5904
6998 12:28:22.380378 # ok 1106 # SKIP Disabled ZA for VL 5904
6999 12:28:22.380481 # ok 1107 # SKIP Get and set data for VL 5904
7000 12:28:22.380571 # ok 1108 Set VL 5920
7001 12:28:22.380673 # ok 1109 # SKIP Disabled ZA for VL 5920
7002 12:28:22.380776 # ok 1110 # SKIP Get and set data for VL 5920
7003 12:28:22.380875 # ok 1111 Set VL 5936
7004 12:28:22.380974 # ok 1112 # SKIP Disabled ZA for VL 5936
7005 12:28:22.381314 # ok 1113 # SKIP Get and set data for VL 5936
7006 12:28:22.381452 # ok 1114 Set VL 5952
7007 12:28:22.381566 # ok 1115 # SKIP Disabled ZA for VL 5952
7008 12:28:22.381667 # ok 1116 # SKIP Get and set data for VL 5952
7009 12:28:22.381776 # ok 1117 Set VL 5968
7010 12:28:22.388690 # ok 1118 # SKIP Disabled ZA for VL 5968
7011 12:28:22.389155 # ok 1119 # SKIP Get and set data for VL 5968
7012 12:28:22.389425 # ok 1120 Set VL 5984
7013 12:28:22.389859 # ok 1121 # SKIP Disabled ZA for VL 5984
7014 12:28:22.389956 # ok 1122 # SKIP Get and set data for VL 5984
7015 12:28:22.390034 # ok 1123 Set VL 6000
7016 12:28:22.390110 # ok 1124 # SKIP Disabled ZA for VL 6000
7017 12:28:22.390186 # ok 1125 # SKIP Get and set data for VL 6000
7018 12:28:22.390260 # ok 1126 Set VL 6016
7019 12:28:22.390335 # ok 1127 # SKIP Disabled ZA for VL 6016
7020 12:28:22.390409 # ok 1128 # SKIP Get and set data for VL 6016
7021 12:28:22.390484 # ok 1129 Set VL 6032
7022 12:28:22.390557 # ok 1130 # SKIP Disabled ZA for VL 6032
7023 12:28:22.393695 # ok 1131 # SKIP Get and set data for VL 6032
7024 12:28:22.393880 # ok 1132 Set VL 6048
7025 12:28:22.395544 # ok 1133 # SKIP Disabled ZA for VL 6048
7026 12:28:22.395680 # ok 1134 # SKIP Get and set data for VL 6048
7027 12:28:22.395772 # ok 1135 Set VL 6064
7028 12:28:22.395873 # ok 1136 # SKIP Disabled ZA for VL 6064
7029 12:28:22.395961 # ok 1137 # SKIP Get and set data for VL 6064
7030 12:28:22.396048 # ok 1138 Set VL 6080
7031 12:28:22.396148 # ok 1139 # SKIP Disabled ZA for VL 6080
7032 12:28:22.396248 # ok 1140 # SKIP Get and set data for VL 6080
7033 12:28:22.396348 # ok 1141 Set VL 6096
7034 12:28:22.396444 # ok 1142 # SKIP Disabled ZA for VL 6096
7035 12:28:22.396746 # ok 1143 # SKIP Get and set data for VL 6096
7036 12:28:22.396852 # ok 1144 Set VL 6112
7037 12:28:22.397111 # ok 1145 # SKIP Disabled ZA for VL 6112
7038 12:28:22.397216 # ok 1146 # SKIP Get and set data for VL 6112
7039 12:28:22.397304 # ok 1147 Set VL 6128
7040 12:28:22.397387 # ok 1148 # SKIP Disabled ZA for VL 6128
7041 12:28:22.397484 # ok 1149 # SKIP Get and set data for VL 6128
7042 12:28:22.397565 # ok 1150 Set VL 6144
7043 12:28:22.397689 # ok 1151 # SKIP Disabled ZA for VL 6144
7044 12:28:22.402966 # ok 1152 # SKIP Get and set data for VL 6144
7045 12:28:22.403421 # ok 1153 Set VL 6160
7046 12:28:22.403528 # ok 1154 # SKIP Disabled ZA for VL 6160
7047 12:28:22.403616 # ok 1155 # SKIP Get and set data for VL 6160
7048 12:28:22.403700 # ok 1156 Set VL 6176
7049 12:28:22.403783 # ok 1157 # SKIP Disabled ZA for VL 6176
7050 12:28:22.403882 # ok 1158 # SKIP Get and set data for VL 6176
7051 12:28:22.403970 # ok 1159 Set VL 6192
7052 12:28:22.404073 # ok 1160 # SKIP Disabled ZA for VL 6192
7053 12:28:22.404161 # ok 1161 # SKIP Get and set data for VL 6192
7054 12:28:22.404244 # ok 1162 Set VL 6208
7055 12:28:22.404338 # ok 1163 # SKIP Disabled ZA for VL 6208
7056 12:28:22.404425 # ok 1164 # SKIP Get and set data for VL 6208
7057 12:28:22.404709 # ok 1165 Set VL 6224
7058 12:28:22.404815 # ok 1166 # SKIP Disabled ZA for VL 6224
7059 12:28:22.404917 # ok 1167 # SKIP Get and set data for VL 6224
7060 12:28:22.405006 # ok 1168 Set VL 6240
7061 12:28:22.405104 # ok 1169 # SKIP Disabled ZA for VL 6240
7062 12:28:22.405209 # ok 1170 # SKIP Get and set data for VL 6240
7063 12:28:22.405494 # ok 1171 Set VL 6256
7064 12:28:22.405599 # ok 1172 # SKIP Disabled ZA for VL 6256
7065 12:28:22.405706 # ok 1173 # SKIP Get and set data for VL 6256
7066 12:28:22.405804 # ok 1174 Set VL 6272
7067 12:28:22.414583 # ok 1175 # SKIP Disabled ZA for VL 6272
7068 12:28:22.415084 # ok 1176 # SKIP Get and set data for VL 6272
7069 12:28:22.415193 # ok 1177 Set VL 6288
7070 12:28:22.415283 # ok 1178 # SKIP Disabled ZA for VL 6288
7071 12:28:22.415372 # ok 1179 # SKIP Get and set data for VL 6288
7072 12:28:22.415459 # ok 1180 Set VL 6304
7073 12:28:22.415559 # ok 1181 # SKIP Disabled ZA for VL 6304
7074 12:28:22.415647 # ok 1182 # SKIP Get and set data for VL 6304
7075 12:28:22.415734 # ok 1183 Set VL 6320
7076 12:28:22.415834 # ok 1184 # SKIP Disabled ZA for VL 6320
7077 12:28:22.415919 # ok 1185 # SKIP Get and set data for VL 6320
7078 12:28:22.416003 # ok 1186 Set VL 6336
7079 12:28:22.416102 # ok 1187 # SKIP Disabled ZA for VL 6336
7080 12:28:22.416195 # ok 1188 # SKIP Get and set data for VL 6336
7081 12:28:22.416298 # ok 1189 Set VL 6352
7082 12:28:22.416384 # ok 1190 # SKIP Disabled ZA for VL 6352
7083 12:28:22.416485 # ok 1191 # SKIP Get and set data for VL 6352
7084 12:28:22.416586 # ok 1192 Set VL 6368
7085 12:28:22.416686 # ok 1193 # SKIP Disabled ZA for VL 6368
7086 12:28:22.416794 # ok 1194 # SKIP Get and set data for VL 6368
7087 12:28:22.416894 # ok 1195 Set VL 6384
7088 12:28:22.417200 # ok 1196 # SKIP Disabled ZA for VL 6384
7089 12:28:22.417535 # ok 1197 # SKIP Get and set data for VL 6384
7090 12:28:22.417652 # ok 1198 Set VL 6400
7091 12:28:22.417747 # ok 1199 # SKIP Disabled ZA for VL 6400
7092 12:28:22.417853 # ok 1200 # SKIP Get and set data for VL 6400
7093 12:28:22.417944 # ok 1201 Set VL 6416
7094 12:28:22.424035 # ok 1202 # SKIP Disabled ZA for VL 6416
7095 12:28:22.424289 # ok 1203 # SKIP Get and set data for VL 6416
7096 12:28:22.424603 # ok 1204 Set VL 6432
7097 12:28:22.424709 # ok 1205 # SKIP Disabled ZA for VL 6432
7098 12:28:22.424798 # ok 1206 # SKIP Get and set data for VL 6432
7099 12:28:22.424884 # ok 1207 Set VL 6448
7100 12:28:22.424970 # ok 1208 # SKIP Disabled ZA for VL 6448
7101 12:28:22.425055 # ok 1209 # SKIP Get and set data for VL 6448
7102 12:28:22.425156 # ok 1210 Set VL 6464
7103 12:28:22.425242 # ok 1211 # SKIP Disabled ZA for VL 6464
7104 12:28:22.425328 # ok 1212 # SKIP Get and set data for VL 6464
7105 12:28:22.425412 # ok 1213 Set VL 6480
7106 12:28:22.425510 # ok 1214 # SKIP Disabled ZA for VL 6480
7107 12:28:22.425595 # ok 1215 # SKIP Get and set data for VL 6480
7108 12:28:22.425686 # ok 1216 Set VL 6496
7109 12:28:22.425778 # ok 1217 # SKIP Disabled ZA for VL 6496
7110 12:28:22.433001 # ok 1218 # SKIP Get and set data for VL 6496
7111 12:28:22.433329 # ok 1219 Set VL 6512
7112 12:28:22.433708 # ok 1220 # SKIP Disabled ZA for VL 6512
7113 12:28:22.433851 # ok 1221 # SKIP Get and set data for VL 6512
7114 12:28:22.434010 # ok 1222 Set VL 6528
7115 12:28:22.434134 # ok 1223 # SKIP Disabled ZA for VL 6528
7116 12:28:22.434287 # ok 1224 # SKIP Get and set data for VL 6528
7117 12:28:22.434414 # ok 1225 Set VL 6544
7118 12:28:22.434539 # ok 1226 # SKIP Disabled ZA for VL 6544
7119 12:28:22.434732 # ok 1227 # SKIP Get and set data for VL 6544
7120 12:28:22.434873 # ok 1228 Set VL 6560
7121 12:28:22.434995 # ok 1229 # SKIP Disabled ZA for VL 6560
7122 12:28:22.435174 # ok 1230 # SKIP Get and set data for VL 6560
7123 12:28:22.435295 # ok 1231 Set VL 6576
7124 12:28:22.435476 # ok 1232 # SKIP Disabled ZA for VL 6576
7125 12:28:22.435638 # ok 1233 # SKIP Get and set data for VL 6576
7126 12:28:22.435798 # ok 1234 Set VL 6592
7127 12:28:22.435920 # ok 1235 # SKIP Disabled ZA for VL 6592
7128 12:28:22.436103 # ok 1236 # SKIP Get and set data for VL 6592
7129 12:28:22.436284 # ok 1237 Set VL 6608
7130 12:28:22.436472 # ok 1238 # SKIP Disabled ZA for VL 6608
7131 12:28:22.436627 # ok 1239 # SKIP Get and set data for VL 6608
7132 12:28:22.436755 # ok 1240 Set VL 6624
7133 12:28:22.436880 # ok 1241 # SKIP Disabled ZA for VL 6624
7134 12:28:22.437004 # ok 1242 # SKIP Get and set data for VL 6624
7135 12:28:22.437433 # ok 1243 Set VL 6640
7136 12:28:22.437596 # ok 1244 # SKIP Disabled ZA for VL 6640
7137 12:28:22.437753 # ok 1245 # SKIP Get and set data for VL 6640
7138 12:28:22.437873 # ok 1246 Set VL 6656
7139 12:28:22.437990 # ok 1247 # SKIP Disabled ZA for VL 6656
7140 12:28:22.438138 # ok 1248 # SKIP Get and set data for VL 6656
7141 12:28:22.438270 # ok 1249 Set VL 6672
7142 12:28:22.438387 # ok 1250 # SKIP Disabled ZA for VL 6672
7143 12:28:22.438502 # ok 1251 # SKIP Get and set data for VL 6672
7144 12:28:22.438616 # ok 1252 Set VL 6688
7145 12:28:22.438728 # ok 1253 # SKIP Disabled ZA for VL 6688
7146 12:28:22.438843 # ok 1254 # SKIP Get and set data for VL 6688
7147 12:28:22.438957 # ok 1255 Set VL 6704
7148 12:28:22.439071 # ok 1256 # SKIP Disabled ZA for VL 6704
7149 12:28:22.439187 # ok 1257 # SKIP Get and set data for VL 6704
7150 12:28:22.439302 # ok 1258 Set VL 6720
7151 12:28:22.439414 # ok 1259 # SKIP Disabled ZA for VL 6720
7152 12:28:22.439529 # ok 1260 # SKIP Get and set data for VL 6720
7153 12:28:22.439652 # ok 1261 Set VL 6736
7154 12:28:22.439826 # ok 1262 # SKIP Disabled ZA for VL 6736
7155 12:28:22.439971 # ok 1263 # SKIP Get and set data for VL 6736
7156 12:28:22.440114 # ok 1264 Set VL 6752
7157 12:28:22.440297 # ok 1265 # SKIP Disabled ZA for VL 6752
7158 12:28:22.440487 # ok 1266 # SKIP Get and set data for VL 6752
7159 12:28:22.440670 # ok 1267 Set VL 6768
7160 12:28:22.440873 # ok 1268 # SKIP Disabled ZA for VL 6768
7161 12:28:22.447458 # ok 1269 # SKIP Get and set data for VL 6768
7162 12:28:22.447749 # ok 1270 Set VL 6784
7163 12:28:22.448172 # ok 1271 # SKIP Disabled ZA for VL 6784
7164 12:28:22.448330 # ok 1272 # SKIP Get and set data for VL 6784
7165 12:28:22.448456 # ok 1273 Set VL 6800
7166 12:28:22.448614 # ok 1274 # SKIP Disabled ZA for VL 6800
7167 12:28:22.448737 # ok 1275 # SKIP Get and set data for VL 6800
7168 12:28:22.448857 # ok 1276 Set VL 6816
7169 12:28:22.449020 # ok 1277 # SKIP Disabled ZA for VL 6816
7170 12:28:22.449220 # ok 1278 # SKIP Get and set data for VL 6816
7171 12:28:22.449360 # ok 1279 Set VL 6832
7172 12:28:22.449593 # ok 1280 # SKIP Disabled ZA for VL 6832
7173 12:28:22.449801 # ok 1281 # SKIP Get and set data for VL 6832
7174 12:28:22.449977 # ok 1282 Set VL 6848
7175 12:28:22.450157 # ok 1283 # SKIP Disabled ZA for VL 6848
7176 12:28:22.463591 # ok 1284 # SKIP Get and set data for VL 6848
7177 12:28:22.463932 # ok 1285 Set VL 6864
7178 12:28:22.464102 # ok 1286 # SKIP Disabled ZA for VL 6864
7179 12:28:22.464427 # ok 1287 # SKIP Get and set data for VL 6864
7180 12:28:22.464853 # ok 1288 Set VL 6880
7181 12:28:22.465037 # ok 1289 # SKIP Disabled ZA for VL 6880
7182 12:28:22.465195 # ok 1290 # SKIP Get and set data for VL 6880
7183 12:28:22.465335 # ok 1291 Set VL 6896
7184 12:28:22.465472 # ok 1292 # SKIP Disabled ZA for VL 6896
7185 12:28:22.465613 # ok 1293 # SKIP Get and set data for VL 6896
7186 12:28:22.465770 # ok 1294 Set VL 6912
7187 12:28:22.465892 # ok 1295 # SKIP Disabled ZA for VL 6912
7188 12:28:22.466010 # ok 1296 # SKIP Get and set data for VL 6912
7189 12:28:22.466169 # ok 1297 Set VL 6928
7190 12:28:22.466325 # ok 1298 # SKIP Disabled ZA for VL 6928
7191 12:28:22.466446 # ok 1299 # SKIP Get and set data for VL 6928
7192 12:28:22.466578 # ok 1300 Set VL 6944
7193 12:28:22.466699 # ok 1301 # SKIP Disabled ZA for VL 6944
7194 12:28:22.466817 # ok 1302 # SKIP Get and set data for VL 6944
7195 12:28:22.466935 # ok 1303 Set VL 6960
7196 12:28:22.467057 # ok 1304 # SKIP Disabled ZA for VL 6960
7197 12:28:22.467175 # ok 1305 # SKIP Get and set data for VL 6960
7198 12:28:22.467291 # ok 1306 Set VL 6976
7199 12:28:22.467414 # ok 1307 # SKIP Disabled ZA for VL 6976
7200 12:28:22.467532 # ok 1308 # SKIP Get and set data for VL 6976
7201 12:28:22.467649 # ok 1309 Set VL 6992
7202 12:28:22.467773 # ok 1310 # SKIP Disabled ZA for VL 6992
7203 12:28:22.474931 # ok 1311 # SKIP Get and set data for VL 6992
7204 12:28:22.475179 # ok 1312 Set VL 7008
7205 12:28:22.475487 # ok 1313 # SKIP Disabled ZA for VL 7008
7206 12:28:22.475592 # ok 1314 # SKIP Get and set data for VL 7008
7207 12:28:22.475681 # ok 1315 Set VL 7024
7208 12:28:22.475782 # ok 1316 # SKIP Disabled ZA for VL 7024
7209 12:28:22.475870 # ok 1317 # SKIP Get and set data for VL 7024
7210 12:28:22.475954 # ok 1318 Set VL 7040
7211 12:28:22.476038 # ok 1319 # SKIP Disabled ZA for VL 7040
7212 12:28:22.476121 # ok 1320 # SKIP Get and set data for VL 7040
7213 12:28:22.476209 # ok 1321 Set VL 7056
7214 12:28:22.476309 # ok 1322 # SKIP Disabled ZA for VL 7056
7215 12:28:22.476397 # ok 1323 # SKIP Get and set data for VL 7056
7216 12:28:22.476480 # ok 1324 Set VL 7072
7217 12:28:22.476579 # ok 1325 # SKIP Disabled ZA for VL 7072
7218 12:28:22.476663 # ok 1326 # SKIP Get and set data for VL 7072
7219 12:28:22.476764 # ok 1327 Set VL 7088
7220 12:28:22.476852 # ok 1328 # SKIP Disabled ZA for VL 7088
7221 12:28:22.476950 # ok 1329 # SKIP Get and set data for VL 7088
7222 12:28:22.477036 # ok 1330 Set VL 7104
7223 12:28:22.477136 # ok 1331 # SKIP Disabled ZA for VL 7104
7224 12:28:22.477236 # ok 1332 # SKIP Get and set data for VL 7104
7225 12:28:22.477334 # ok 1333 Set VL 7120
7226 12:28:22.477816 # ok 1334 # SKIP Disabled ZA for VL 7120
7227 12:28:22.477914 # ok 1335 # SKIP Get and set data for VL 7120
7228 12:28:22.491462 # ok 1336 Set VL 7136
7229 12:28:22.491817 # ok 1337 # SKIP Disabled ZA for VL 7136
7230 12:28:22.492381 # ok 1338 # SKIP Get and set data for VL 7136
7231 12:28:22.492545 # ok 1339 Set VL 7152
7232 12:28:22.492703 # ok 1340 # SKIP Disabled ZA for VL 7152
7233 12:28:22.492872 # ok 1341 # SKIP Get and set data for VL 7152
7234 12:28:22.493007 # ok 1342 Set VL 7168
7235 12:28:22.493164 # ok 1343 # SKIP Disabled ZA for VL 7168
7236 12:28:22.493318 # ok 1344 # SKIP Get and set data for VL 7168
7237 12:28:22.493470 # ok 1345 Set VL 7184
7238 12:28:22.493644 # ok 1346 # SKIP Disabled ZA for VL 7184
7239 12:28:22.493869 # ok 1347 # SKIP Get and set data for VL 7184
7240 12:28:22.494093 # ok 1348 Set VL 7200
7241 12:28:22.494232 # ok 1349 # SKIP Disabled ZA for VL 7200
7242 12:28:22.494379 # ok 1350 # SKIP Get and set data for VL 7200
7243 12:28:22.494524 # ok 1351 Set VL 7216
7244 12:28:22.494667 # ok 1352 # SKIP Disabled ZA for VL 7216
7245 12:28:22.494811 # ok 1353 # SKIP Get and set data for VL 7216
7246 12:28:22.494955 # ok 1354 Set VL 7232
7247 12:28:22.495097 # ok 1355 # SKIP Disabled ZA for VL 7232
7248 12:28:22.495239 # ok 1356 # SKIP Get and set data for VL 7232
7249 12:28:22.495381 # ok 1357 Set VL 7248
7250 12:28:22.495565 # ok 1358 # SKIP Disabled ZA for VL 7248
7251 12:28:22.495740 # ok 1359 # SKIP Get and set data for VL 7248
7252 12:28:22.495887 # ok 1360 Set VL 7264
7253 12:28:22.496030 # ok 1361 # SKIP Disabled ZA for VL 7264
7254 12:28:22.496171 # ok 1362 # SKIP Get and set data for VL 7264
7255 12:28:22.496315 # ok 1363 Set VL 7280
7256 12:28:22.496458 # ok 1364 # SKIP Disabled ZA for VL 7280
7257 12:28:22.496600 # ok 1365 # SKIP Get and set data for VL 7280
7258 12:28:22.503461 # ok 1366 Set VL 7296
7259 12:28:22.503750 # ok 1367 # SKIP Disabled ZA for VL 7296
7260 12:28:22.503972 # ok 1368 # SKIP Get and set data for VL 7296
7261 12:28:22.504114 # ok 1369 Set VL 7312
7262 12:28:22.504257 # ok 1370 # SKIP Disabled ZA for VL 7312
7263 12:28:22.504408 # ok 1371 # SKIP Get and set data for VL 7312
7264 12:28:22.504552 # ok 1372 Set VL 7328
7265 12:28:22.504695 # ok 1373 # SKIP Disabled ZA for VL 7328
7266 12:28:22.504840 # ok 1374 # SKIP Get and set data for VL 7328
7267 12:28:22.505021 # ok 1375 Set VL 7344
7268 12:28:22.505158 # ok 1376 # SKIP Disabled ZA for VL 7344
7269 12:28:22.505305 # ok 1377 # SKIP Get and set data for VL 7344
7270 12:28:22.505448 # ok 1378 Set VL 7360
7271 12:28:22.505664 # ok 1379 # SKIP Disabled ZA for VL 7360
7272 12:28:22.505837 # ok 1380 # SKIP Get and set data for VL 7360
7273 12:28:22.506044 # ok 1381 Set VL 7376
7274 12:28:22.506227 # ok 1382 # SKIP Disabled ZA for VL 7376
7275 12:28:22.506415 # ok 1383 # SKIP Get and set data for VL 7376
7276 12:28:22.506541 # ok 1384 Set VL 7392
7277 12:28:22.506681 # ok 1385 # SKIP Disabled ZA for VL 7392
7278 12:28:22.506861 # ok 1386 # SKIP Get and set data for VL 7392
7279 12:28:22.506992 # ok 1387 Set VL 7408
7280 12:28:22.507151 # ok 1388 # SKIP Disabled ZA for VL 7408
7281 12:28:22.507275 # ok 1389 # SKIP Get and set data for VL 7408
7282 12:28:22.507408 # ok 1390 Set VL 7424
7283 12:28:22.507550 # ok 1391 # SKIP Disabled ZA for VL 7424
7284 12:28:22.513852 # ok 1392 # SKIP Get and set data for VL 7424
7285 12:28:22.515255 # ok 1393 Set VL 7440
7286 12:28:22.515426 # ok 1394 # SKIP Disabled ZA for VL 7440
7287 12:28:22.515781 # ok 1395 # SKIP Get and set data for VL 7440
7288 12:28:22.515941 # ok 1396 Set VL 7456
7289 12:28:22.516106 # ok 1397 # SKIP Disabled ZA for VL 7456
7290 12:28:22.516230 # ok 1398 # SKIP Get and set data for VL 7456
7291 12:28:22.516372 # ok 1399 Set VL 7472
7292 12:28:22.516569 # ok 1400 # SKIP Disabled ZA for VL 7472
7293 12:28:22.516731 # ok 1401 # SKIP Get and set data for VL 7472
7294 12:28:22.516875 # ok 1402 Set VL 7488
7295 12:28:22.517013 # ok 1403 # SKIP Disabled ZA for VL 7488
7296 12:28:22.517129 # ok 1404 # SKIP Get and set data for VL 7488
7297 12:28:22.517284 # ok 1405 Set VL 7504
7298 12:28:22.517406 # ok 1406 # SKIP Disabled ZA for VL 7504
7299 12:28:22.517526 # ok 1407 # SKIP Get and set data for VL 7504
7300 12:28:22.517693 # ok 1408 Set VL 7520
7301 12:28:22.517813 # ok 1409 # SKIP Disabled ZA for VL 7520
7302 12:28:22.517954 # ok 1410 # SKIP Get and set data for VL 7520
7303 12:28:22.518101 # ok 1411 Set VL 7536
7304 12:28:22.518220 # ok 1412 # SKIP Disabled ZA for VL 7536
7305 12:28:22.518399 # ok 1413 # SKIP Get and set data for VL 7536
7306 12:28:22.518532 # ok 1414 Set VL 7552
7307 12:28:22.518660 # ok 1415 # SKIP Disabled ZA for VL 7552
7308 12:28:22.518816 # ok 1416 # SKIP Get and set data for VL 7552
7309 12:28:22.518939 # ok 1417 Set VL 7568
7310 12:28:22.519056 # ok 1418 # SKIP Disabled ZA for VL 7568
7311 12:28:22.519211 # ok 1419 # SKIP Get and set data for VL 7568
7312 12:28:22.519332 # ok 1420 Set VL 7584
7313 12:28:22.519473 # ok 1421 # SKIP Disabled ZA for VL 7584
7314 12:28:22.519621 # ok 1422 # SKIP Get and set data for VL 7584
7315 12:28:22.519741 # ok 1423 Set VL 7600
7316 12:28:22.519893 # ok 1424 # SKIP Disabled ZA for VL 7600
7317 12:28:22.520016 # ok 1425 # SKIP Get and set data for VL 7600
7318 12:28:22.520148 # ok 1426 Set VL 7616
7319 12:28:22.520286 # ok 1427 # SKIP Disabled ZA for VL 7616
7320 12:28:22.527413 # ok 1428 # SKIP Get and set data for VL 7616
7321 12:28:22.527926 # ok 1429 Set VL 7632
7322 12:28:22.528080 # ok 1430 # SKIP Disabled ZA for VL 7632
7323 12:28:22.528209 # ok 1431 # SKIP Get and set data for VL 7632
7324 12:28:22.528396 # ok 1432 Set VL 7648
7325 12:28:22.528554 # ok 1433 # SKIP Disabled ZA for VL 7648
7326 12:28:22.528682 # ok 1434 # SKIP Get and set data for VL 7648
7327 12:28:22.528872 # ok 1435 Set VL 7664
7328 12:28:22.529026 # ok 1436 # SKIP Disabled ZA for VL 7664
7329 12:28:22.529206 # ok 1437 # SKIP Get and set data for VL 7664
7330 12:28:22.529341 # ok 1438 Set VL 7680
7331 12:28:22.529489 # ok 1439 # SKIP Disabled ZA for VL 7680
7332 12:28:22.529630 # ok 1440 # SKIP Get and set data for VL 7680
7333 12:28:22.529846 # ok 1441 Set VL 7696
7334 12:28:22.530017 # ok 1442 # SKIP Disabled ZA for VL 7696
7335 12:28:22.530163 # ok 1443 # SKIP Get and set data for VL 7696
7336 12:28:22.530307 # ok 1444 Set VL 7712
7337 12:28:22.530451 # ok 1445 # SKIP Disabled ZA for VL 7712
7338 12:28:22.530594 # ok 1446 # SKIP Get and set data for VL 7712
7339 12:28:22.530736 # ok 1447 Set VL 7728
7340 12:28:22.530879 # ok 1448 # SKIP Disabled ZA for VL 7728
7341 12:28:22.531022 # ok 1449 # SKIP Get and set data for VL 7728
7342 12:28:22.531209 # ok 1450 Set VL 7744
7343 12:28:22.531346 # ok 1451 # SKIP Disabled ZA for VL 7744
7344 12:28:22.531505 # ok 1452 # SKIP Get and set data for VL 7744
7345 12:28:22.531647 # ok 1453 Set VL 7760
7346 12:28:22.531791 # ok 1454 # SKIP Disabled ZA for VL 7760
7347 12:28:22.531934 # ok 1455 # SKIP Get and set data for VL 7760
7348 12:28:22.532076 # ok 1456 Set VL 7776
7349 12:28:22.532218 # ok 1457 # SKIP Disabled ZA for VL 7776
7350 12:28:22.541849 # ok 1458 # SKIP Get and set data for VL 7776
7351 12:28:22.542149 # ok 1459 Set VL 7792
7352 12:28:22.547863 # ok 1460 # SKIP Disabled ZA for VL 7792
7353 12:28:22.548185 # ok 1461 # SKIP Get and set data for VL 7792
7354 12:28:22.548351 # ok 1462 Set VL 7808
7355 12:28:22.548795 # ok 1463 # SKIP Disabled ZA for VL 7808
7356 12:28:22.548913 # ok 1464 # SKIP Get and set data for VL 7808
7357 12:28:22.549012 # ok 1465 Set VL 7824
7358 12:28:22.549101 # ok 1466 # SKIP Disabled ZA for VL 7824
7359 12:28:22.549190 # ok 1467 # SKIP Get and set data for VL 7824
7360 12:28:22.549278 # ok 1468 Set VL 7840
7361 12:28:22.549367 # ok 1469 # SKIP Disabled ZA for VL 7840
7362 12:28:22.549457 # ok 1470 # SKIP Get and set data for VL 7840
7363 12:28:22.549562 # ok 1471 Set VL 7856
7364 12:28:22.549661 # ok 1472 # SKIP Disabled ZA for VL 7856
7365 12:28:22.549750 # ok 1473 # SKIP Get and set data for VL 7856
7366 12:28:22.549835 # ok 1474 Set VL 7872
7367 12:28:22.549936 # ok 1475 # SKIP Disabled ZA for VL 7872
7368 12:28:22.555592 # ok 1476 # SKIP Get and set data for VL 7872
7369 12:28:22.555841 # ok 1477 Set VL 7888
7370 12:28:22.556154 # ok 1478 # SKIP Disabled ZA for VL 7888
7371 12:28:22.556261 # ok 1479 # SKIP Get and set data for VL 7888
7372 12:28:22.556352 # ok 1480 Set VL 7904
7373 12:28:22.556437 # ok 1481 # SKIP Disabled ZA for VL 7904
7374 12:28:22.556525 # ok 1482 # SKIP Get and set data for VL 7904
7375 12:28:22.556612 # ok 1483 Set VL 7920
7376 12:28:22.556714 # ok 1484 # SKIP Disabled ZA for VL 7920
7377 12:28:22.556798 # ok 1485 # SKIP Get and set data for VL 7920
7378 12:28:22.556881 # ok 1486 Set VL 7936
7379 12:28:22.556966 # ok 1487 # SKIP Disabled ZA for VL 7936
7380 12:28:22.557064 # ok 1488 # SKIP Get and set data for VL 7936
7381 12:28:22.557146 # ok 1489 Set VL 7952
7382 12:28:22.557227 # ok 1490 # SKIP Disabled ZA for VL 7952
7383 12:28:22.557310 # ok 1491 # SKIP Get and set data for VL 7952
7384 12:28:22.557412 # ok 1492 Set VL 7968
7385 12:28:22.557497 # ok 1493 # SKIP Disabled ZA for VL 7968
7386 12:28:22.557582 # ok 1494 # SKIP Get and set data for VL 7968
7387 12:28:22.557673 # ok 1495 Set VL 7984
7388 12:28:22.557777 # ok 1496 # SKIP Disabled ZA for VL 7984
7389 12:28:22.557865 # ok 1497 # SKIP Get and set data for VL 7984
7390 12:28:22.557954 # ok 1498 Set VL 8000
7391 12:28:22.563660 # ok 1499 # SKIP Disabled ZA for VL 8000
7392 12:28:22.564169 # ok 1500 # SKIP Get and set data for VL 8000
7393 12:28:22.564295 # ok 1501 Set VL 8016
7394 12:28:22.564385 # ok 1502 # SKIP Disabled ZA for VL 8016
7395 12:28:22.565186 # ok 1503 # SKIP Get and set data for VL 8016
7396 12:28:22.565320 # ok 1504 Set VL 8032
7397 12:28:22.565643 # ok 1505 # SKIP Disabled ZA for VL 8032
7398 12:28:22.565750 # ok 1506 # SKIP Get and set data for VL 8032
7399 12:28:22.565845 # ok 1507 Set VL 8048
7400 12:28:22.565922 # ok 1508 # SKIP Disabled ZA for VL 8048
7401 12:28:22.571578 # ok 1509 # SKIP Get and set data for VL 8048
7402 12:28:22.571831 # ok 1510 Set VL 8064
7403 12:28:22.572199 # ok 1511 # SKIP Disabled ZA for VL 8064
7404 12:28:22.572312 # ok 1512 # SKIP Get and set data for VL 8064
7405 12:28:22.572405 # ok 1513 Set VL 8080
7406 12:28:22.572495 # ok 1514 # SKIP Disabled ZA for VL 8080
7407 12:28:22.572579 # ok 1515 # SKIP Get and set data for VL 8080
7408 12:28:22.572666 # ok 1516 Set VL 8096
7409 12:28:22.572751 # ok 1517 # SKIP Disabled ZA for VL 8096
7410 12:28:22.572855 # ok 1518 # SKIP Get and set data for VL 8096
7411 12:28:22.572943 # ok 1519 Set VL 8112
7412 12:28:22.573030 # ok 1520 # SKIP Disabled ZA for VL 8112
7413 12:28:22.573113 # ok 1521 # SKIP Get and set data for VL 8112
7414 12:28:22.573196 # ok 1522 Set VL 8128
7415 12:28:22.573278 # ok 1523 # SKIP Disabled ZA for VL 8128
7416 12:28:22.573380 # ok 1524 # SKIP Get and set data for VL 8128
7417 12:28:22.573464 # ok 1525 Set VL 8144
7418 12:28:22.573552 # ok 1526 # SKIP Disabled ZA for VL 8144
7419 12:28:22.573925 # ok 1527 # SKIP Get and set data for VL 8144
7420 12:28:22.574025 # ok 1528 Set VL 8160
7421 12:28:22.574109 # ok 1529 # SKIP Disabled ZA for VL 8160
7422 12:28:22.574213 # ok 1530 # SKIP Get and set data for VL 8160
7423 12:28:22.574304 # ok 1531 Set VL 8176
7424 12:28:22.574393 # ok 1532 # SKIP Disabled ZA for VL 8176
7425 12:28:22.593709 # ok 1533 # SKIP Get and set data for VL 8176
7426 12:28:22.594186 # ok 1534 Set VL 8192
7427 12:28:22.594752 # ok 1535 # SKIP Disabled ZA for VL 8192
7428 12:28:22.595059 # ok 1536 # SKIP Get and set data for VL 8192
7429 12:28:22.595225 # # Totals: pass:522 fail:0 xfail:0 xpass:0 skip:1014 error:0
7430 12:28:22.595398 ok 34 selftests: arm64: za-ptrace
7431 12:28:22.595564 # selftests: arm64: check_buffer_fill
7432 12:28:23.308877 # 1..20
7433 12:28:23.309525 # ok 1 Check buffer correctness by byte with sync err mode and mmap memory
7434 12:28:23.309638 # ok 2 Check buffer correctness by byte with async err mode and mmap memory
7435 12:28:23.309739 # ok 3 Check buffer correctness by byte with sync err mode and mmap/mprotect memory
7436 12:28:23.309842 # ok 4 Check buffer correctness by byte with async err mode and mmap/mprotect memory
7437 12:28:23.310133 # not ok 5 Check buffer write underflow by byte with sync mode and mmap memory
7438 12:28:23.310231 # not ok 6 Check buffer write underflow by byte with async mode and mmap memory
7439 12:28:23.321666 # ok 7 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7440 12:28:23.322652 # ok 8 Check buffer write underflow by byte with sync mode and mmap memory
7441 12:28:23.322743 # ok 9 Check buffer write underflow by byte with async mode and mmap memory
7442 12:28:23.324131 # ok 10 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7443 12:28:23.324381 # not ok 11 Check buffer write overflow by byte with sync mode and mmap memory
7444 12:28:23.324944 # not ok 12 Check buffer write overflow by byte with async mode and mmap memory
7445 12:28:23.325081 # ok 13 Check buffer write overflow by byte with tag fault ignore mode and mmap memory
7446 12:28:23.325345 # not ok 14 Check buffer write correctness by block with sync mode and mmap memory
7447 12:28:23.325476 # not ok 15 Check buffer write correctness by block with async mode and mmap memory
7448 12:28:23.325587 # ok 16 Check buffer write correctness by block with tag fault ignore and mmap memory
7449 12:28:23.325723 # ok 17 Check initial tags with private mapping, sync error mode and mmap memory
7450 12:28:23.326039 # ok 18 Check initial tags with private mapping, sync error mode and mmap/mprotect memory
7451 12:28:23.326377 # ok 19 Check initial tags with shared mapping, sync error mode and mmap memory
7452 12:28:23.336699 # ok 20 Check initial tags with shared mapping, sync error mode and mmap/mprotect memory
7453 12:28:23.337178 # # Totals: pass:14 fail:6 xfail:0 xpass:0 skip:0 error:0
7454 12:28:23.378175 not ok 35 selftests: arm64: check_buffer_fill # exit=1
7455 12:28:23.588396 # selftests: arm64: check_child_memory
7456 12:28:24.249771 # 1..12
7457 12:28:24.250244 # not ok 1 Check child anonymous memory with private mapping, precise mode and mmap memory
7458 12:28:24.250342 # not ok 2 Check child anonymous memory with shared mapping, precise mode and mmap memory
7459 12:28:24.250423 # not ok 3 Check child anonymous memory with private mapping, imprecise mode and mmap memory
7460 12:28:24.250511 # not ok 4 Check child anonymous memory with shared mapping, imprecise mode and mmap memory
7461 12:28:24.256560 # not ok 5 Check child anonymous memory with private mapping, precise mode and mmap/mprotect memory
7462 12:28:24.257007 # not ok 6 Check child anonymous memory with shared mapping, precise mode and mmap/mprotect memory
7463 12:28:24.257104 # not ok 7 Check child file memory with private mapping, precise mode and mmap memory
7464 12:28:24.257184 # not ok 8 Check child file memory with shared mapping, precise mode and mmap memory
7465 12:28:24.257270 # not ok 9 Check child file memory with private mapping, imprecise mode and mmap memory
7466 12:28:24.257679 # not ok 10 Check child file memory with shared mapping, imprecise mode and mmap memory
7467 12:28:24.257955 # not ok 11 Check child file memory with private mapping, precise mode and mmap/mprotect memory
7468 12:28:24.258062 # not ok 12 Check child file memory with shared mapping, precise mode and mmap/mprotect memory
7469 12:28:24.258150 # # Totals: pass:0 fail:12 xfail:0 xpass:0 skip:0 error:0
7470 12:28:24.290606 not ok 36 selftests: arm64: check_child_memory # exit=1
7471 12:28:24.429031 # selftests: arm64: check_gcr_el1_cswitch
7472 12:29:09.831847 <47>[ 101.451272] systemd-journald[105]: Sent WATCHDOG=1 notification.
7473 12:29:11.048216 <47>[ 102.669951] systemd-journald[105]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3329 of 4437 items, 2555904 file size, 767 bytes per hash table item), suggesting rotation.
7474 12:29:11.048824 <47>[ 102.670665] systemd-journald[105]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
7475 12:29:11.048991 <47>[ 102.671049] systemd-journald[105]: Rotating...
7476 12:29:11.116666 <47>[ 102.738732] systemd-journald[105]: Reserving 333 entries in field hash table.
7477 12:29:11.189332 <47>[ 102.811326] systemd-journald[105]: Reserving 4437 entries in data hash table.
7478 12:29:11.195863 # 1..1
7479 12:29:11.196191 # 1..1
7480 12:29:11.196364 # 1..1
7481 12:29:11.196743 # 1..1
7482 12:29:11.196891 # 1..1
7483 12:29:11.197015 # 1..1
7484 12:29:11.197133 # 1..1
7485 12:29:11.197249 # 1..1
7486 12:29:11.197366 # 1..1
7487 12:29:11.197482 # 1..1
7488 12:29:11.197599 # 1..1
7489 12:29:11.197731 # 1..1
7490 12:29:11.197851 # 1..1
7491 12:29:11.197967 # 1..1
7492 12:29:11.198083 # 1..1
7493 12:29:11.198199 # 1..1
7494 12:29:11.198315 # 1..1
7495 12:29:11.198430 # 1..1
7496 12:29:11.198556 # 1..1
7497 12:29:11.198731 # 1..1
7498 12:29:11.198876 # 1..1
7499 12:29:11.199018 # 1..1
7500 12:29:11.199158 # 1..1
7501 12:29:11.199298 # 1..1
7502 12:29:11.199438 # 1..1
7503 12:29:11.199622 # 1..1
7504 12:29:11.199757 # 1..1
7505 12:29:11.199903 # 1..1
7506 12:29:11.200046 # 1..1
7507 12:29:11.200187 # 1..1
7508 12:29:11.200327 # 1..1
7509 12:29:11.200468 # 1..1
7510 12:29:11.200608 # 1..1
7511 12:29:11.200748 # 1..1
7512 12:29:11.200887 # 1..1
7513 12:29:11.201028 # 1..1
7514 12:29:11.201169 # 1..1
7515 12:29:11.201309 # 1..1
7516 12:29:11.201451 # 1..1
7517 12:29:11.201592 # 1..1
7518 12:29:11.201752 # 1..1
7519 12:29:11.201896 # 1..1
7520 12:29:11.202037 # 1..1
7521 12:29:11.202178 # 1..1
7522 12:29:11.202317 # 1..1
7523 12:29:11.202457 # 1..1
7524 12:29:11.202597 # 1..1
7525 12:29:11.217838 <47>[ 102.839867] systemd-journald[105]: Vacuuming...
7526 12:29:11.245422 <47>[ 102.867189] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
7527 12:29:11.283711 # 1..1
7528 12:29:11.283989 # 1..1
7529 12:29:11.284406 # 1..1
7530 12:29:11.284549 # 1..1
7531 12:29:11.284696 # 1..1
7532 12:29:11.284884 # 1..1
7533 12:29:11.285059 # 1..1
7534 12:29:11.285205 # 1..1
7535 12:29:11.285347 # 1..1
7536 12:29:11.285489 # 1..1
7537 12:29:11.285631 # 1..1
7538 12:29:11.285786 # 1..1
7539 12:29:11.285931 # 1..1
7540 12:29:11.286072 # 1..1
7541 12:29:11.286213 # 1..1
7542 12:29:11.286354 # 1..1
7543 12:29:11.286493 # 1..1
7544 12:29:11.286648 # 1..1
7545 12:29:11.286878 # 1..1
7546 12:29:11.287023 # 1..1
7547 12:29:11.287149 # 1..1
7548 12:29:11.287271 # 1..1
7549 12:29:11.287388 # 1..1
7550 12:29:11.287512 # 1..1
7551 12:29:11.287692 # 1..1
7552 12:29:11.287865 # 1..1
7553 12:29:11.288012 # 1..1
7554 12:29:11.288153 # 1..1
7555 12:29:11.288293 # 1..1
7556 12:29:11.288432 # 1..1
7557 12:29:11.288572 # 1..1
7558 12:29:11.288711 # 1..1
7559 12:29:11.288851 # 1..1
7560 12:29:11.288992 # 1..1
7561 12:29:11.289131 # 1..1
7562 12:29:11.289305 # 1..1
7563 12:29:11.289476 # 1..1
7564 12:29:11.289618 # 1..1
7565 12:29:11.289776 # 1..1
7566 12:29:11.289918 # 1..1
7567 12:29:11.290058 # 1..1
7568 12:29:11.290198 # 1..1
7569 12:29:11.290338 # 1..1
7570 12:29:11.290477 # 1..1
7571 12:29:11.290616 # 1..1
7572 12:29:11.290756 # 1..1
7573 12:29:11.290895 # 1..1
7574 12:29:11.291035 # 1..1
7575 12:29:11.291173 # 1..1
7576 12:29:11.320631 # 1..1
7577 12:29:11.320943 # 1..1
7578 12:29:11.321130 # 1..1
7579 12:29:11.321299 # 1..1
7580 12:29:11.321467 # 1..1
7581 12:29:11.321628 # 1..1
7582 12:29:11.321798 # 1..1
7583 12:29:11.321925 # 1..1
7584 12:29:11.322044 # 1..1
7585 12:29:11.322188 # 1..1
7586 12:29:11.322316 # 1..1
7587 12:29:11.322508 # 1..1
7588 12:29:11.322681 # 1..1
7589 12:29:11.322826 # 1..1
7590 12:29:11.322968 # 1..1
7591 12:29:11.323109 # 1..1
7592 12:29:11.323249 # 1..1
7593 12:29:11.323389 # 1..1
7594 12:29:11.323530 # 1..1
7595 12:29:11.323671 # 1..1
7596 12:29:11.323813 # 1..1
7597 12:29:11.323953 # 1..1
7598 12:29:11.324093 # 1..1
7599 12:29:11.324234 # 1..1
7600 12:29:11.324375 # 1..1
7601 12:29:11.324515 # 1..1
7602 12:29:11.324653 # 1..1
7603 12:29:11.324795 # 1..1
7604 12:29:11.324935 # 1..1
7605 12:29:11.325075 # 1..1
7606 12:29:11.325216 # 1..1
7607 12:29:11.325355 # 1..1
7608 12:29:11.325495 # 1..1
7609 12:29:11.325635 # 1..1
7610 12:29:11.325792 # 1..1
7611 12:29:11.325934 # 1..1
7612 12:29:11.326077 # 1..1
7613 12:29:11.326217 # 1..1
7614 12:29:11.326357 # 1..1
7615 12:29:11.326497 # 1..1
7616 12:29:11.326637 # 1..1
7617 12:29:11.326776 # 1..1
7618 12:29:11.326915 # 1..1
7619 12:29:11.327057 # 1..1
7620 12:29:11.349774 # 1..1
7621 12:29:11.350119 # 1..1
7622 12:29:11.350304 # 1..1
7623 12:29:11.350482 # 1..1
7624 12:29:11.350647 # 1..1
7625 12:29:11.350822 # 1..1
7626 12:29:11.351002 # 1..1
7627 12:29:11.351424 # 1..1
7628 12:29:11.371595 # 1..1
7629 12:29:11.371850 # 1..1
7630 12:29:11.371947 # 1..1
7631 12:29:11.372035 # 1..1
7632 12:29:11.372498 # 1..1
7633 12:29:11.372719 # 1..1
7634 12:29:11.372960 # 1..1
7635 12:29:11.373181 # 1..1
7636 12:29:11.373403 # 1..1
7637 12:29:11.373624 # 1..1
7638 12:29:11.373867 # 1..1
7639 12:29:11.374019 # 1..1
7640 12:29:11.374147 # 1..1
7641 12:29:11.374264 # 1..1
7642 12:29:11.374379 # 1..1
7643 12:29:11.374491 # 1..1
7644 12:29:11.374605 # 1..1
7645 12:29:11.374717 # 1..1
7646 12:29:11.374831 # 1..1
7647 12:29:11.374945 # 1..1
7648 12:29:11.375060 # 1..1
7649 12:29:11.375177 # 1..1
7650 12:29:11.375290 # 1..1
7651 12:29:11.375404 # 1..1
7652 12:29:11.375518 # 1..1
7653 12:29:11.375632 # 1..1
7654 12:29:11.375747 # 1..1
7655 12:29:11.375861 # 1..1
7656 12:29:11.376027 # 1..1
7657 12:29:11.376151 # 1..1
7658 12:29:11.376268 # 1..1
7659 12:29:11.376383 # 1..1
7660 12:29:11.376496 # 1..1
7661 12:29:11.376609 # 1..1
7662 12:29:11.376722 # 1..1
7663 12:29:11.376836 # 1..1
7664 12:29:11.376950 # 1..1
7665 12:29:11.377063 # 1..1
7666 12:29:11.377178 # 1..1
7667 12:29:11.377290 # 1..1
7668 12:29:11.377404 # 1..1
7669 12:29:11.377518 # 1..1
7670 12:29:11.377632 # 1..1
7671 12:29:11.377870 # 1..1
7672 12:29:11.378066 # 1..1
7673 12:29:11.378250 # 1..1
7674 12:29:11.378433 # 1..1
7675 12:29:11.378614 # 1..1
7676 12:29:11.378796 # 1..1
7677 12:29:11.378978 # 1..1
7678 12:29:11.379158 # 1..1
7679 12:29:11.379337 # 1..1
7680 12:29:11.379481 # 1..1
7681 12:29:11.379622 # 1..1
7682 12:29:11.379764 # 1..1
7683 12:29:11.379905 # 1..1
7684 12:29:11.380046 # 1..1
7685 12:29:11.380186 # 1..1
7686 12:29:11.395542 # 1..1
7687 12:29:11.396448 # 1..1
7688 12:29:11.396660 # 1..1
7689 12:29:11.396883 # 1..1
7690 12:29:11.397081 # 1..1
7691 12:29:11.397297 # 1..1
7692 12:29:11.397512 # 1..1
7693 12:29:11.397731 # 1..1
7694 12:29:11.397914 # 1..1
7695 12:29:11.398064 # 1..1
7696 12:29:11.398192 # 1..1
7697 12:29:11.398317 # 1..1
7698 12:29:11.398440 # 1..1
7699 12:29:11.398565 # 1..1
7700 12:29:11.398689 # 1..1
7701 12:29:11.398811 # 1..1
7702 12:29:11.398934 # 1..1
7703 12:29:11.399055 # 1..1
7704 12:29:11.399178 # 1..1
7705 12:29:11.399301 # 1..1
7706 12:29:11.399422 # 1..1
7707 12:29:11.399583 # 1..1
7708 12:29:11.399707 # 1..1
7709 12:29:11.399829 # 1..1
7710 12:29:11.399948 # 1..1
7711 12:29:11.400063 # 1..1
7712 12:29:11.400188 # 1..1
7713 12:29:11.400305 # 1..1
7714 12:29:11.400419 # 1..1
7715 12:29:11.400534 # 1..1
7716 12:29:11.400648 # 1..1
7717 12:29:11.400761 # 1..1
7718 12:29:11.400882 # 1..1
7719 12:29:11.400999 # 1..1
7720 12:29:11.401114 # 1..1
7721 12:29:11.401230 # 1..1
7722 12:29:11.401346 # 1..1
7723 12:29:11.401461 # 1..1
7724 12:29:11.401575 # 1..1
7725 12:29:11.401702 # 1..1
7726 12:29:11.401818 # 1..1
7727 12:29:11.401931 # 1..1
7728 12:29:11.402046 # 1..1
7729 12:29:11.402161 # 1..1
7730 12:29:11.402283 # 1..1
7731 12:29:11.402398 # 1..1
7732 12:29:11.402513 # 1..1
7733 12:29:11.402627 # 1..1
7734 12:29:11.402741 # 1..1
7735 12:29:11.402856 # 1..1
7736 12:29:11.402970 # 1..1
7737 12:29:11.403085 # 1..1
7738 12:29:11.403202 # 1..1
7739 12:29:11.403319 # 1..1
7740 12:29:11.403435 # 1..1
7741 12:29:11.403549 # 1..1
7742 12:29:11.423395 # 1..1
7743 12:29:11.423771 # 1..1
7744 12:29:11.424000 # 1..1
7745 12:29:11.424201 # 1..1
7746 12:29:11.424419 # 1..1
7747 12:29:11.424652 # 1..1
7748 12:29:11.424891 # 1..1
7749 12:29:11.425108 # 1..1
7750 12:29:11.425571 # 1..1
7751 12:29:11.425810 # 1..1
7752 12:29:11.425964 # 1..1
7753 12:29:11.426084 # 1..1
7754 12:29:11.426201 # 1..1
7755 12:29:11.426317 # 1..1
7756 12:29:11.426432 # 1..1
7757 12:29:11.426546 # 1..1
7758 12:29:11.426662 # 1..1
7759 12:29:11.426776 # 1..1
7760 12:29:11.426890 # 1..1
7761 12:29:11.427003 # 1..1
7762 12:29:11.427118 # 1..1
7763 12:29:11.427232 # 1..1
7764 12:29:11.427352 # 1..1
7765 12:29:11.427467 # 1..1
7766 12:29:11.427583 # 1..1
7767 12:29:11.427698 # 1..1
7768 12:29:11.427814 # 1..1
7769 12:29:11.427930 # 1..1
7770 12:29:11.428046 # 1..1
7771 12:29:11.428160 # 1..1
7772 12:29:11.428276 # 1..1
7773 12:29:11.428391 # 1..1
7774 12:29:11.428506 # 1..1
7775 12:29:11.428621 # 1..1
7776 12:29:11.428737 # 1..1
7777 12:29:11.428852 # 1..1
7778 12:29:11.428967 # 1..1
7779 12:29:11.429083 # 1..1
7780 12:29:11.429199 # 1..1
7781 12:29:11.429315 # 1..1
7782 12:29:11.429429 # 1..1
7783 12:29:11.429542 # 1..1
7784 12:29:11.429673 # 1..1
7785 12:29:11.429788 # 1..1
7786 12:29:11.429900 # 1..1
7787 12:29:11.430011 # 1..1
7788 12:29:11.430122 # 1..1
7789 12:29:11.430236 # 1..1
7790 12:29:11.430350 # 1..1
7791 12:29:11.430461 # 1..1
7792 12:29:11.430573 # 1..1
7793 12:29:11.430685 # 1..1
7794 12:29:11.430797 # 1..1
7795 12:29:11.430909 # 1..1
7796 12:29:11.431021 # 1..1
7797 12:29:11.431177 # 1..1
7798 12:29:11.431299 # 1..1
7799 12:29:11.431413 # 1..1
7800 12:29:11.431527 # 1..1
7801 12:29:11.431642 # 1..1
7802 12:29:11.431755 # 1..1
7803 12:29:11.451365 # 1..1
7804 12:29:11.451722 # 1..1
7805 12:29:11.451937 # 1..1
7806 12:29:11.452150 # 1..1
7807 12:29:11.452343 # 1..1
7808 12:29:11.452515 # 1..1
7809 12:29:11.452660 # 1..1
7810 12:29:11.452785 # 1..1
7811 12:29:11.452938 # 1..1
7812 12:29:11.453068 # 1..1
7813 12:29:11.453191 # 1..1
7814 12:29:11.453315 # 1..1
7815 12:29:11.453438 # 1..1
7816 12:29:11.453562 # 1..1
7817 12:29:11.453717 # 1..1
7818 12:29:11.453917 # 1..1
7819 12:29:11.454103 # 1..1
7820 12:29:11.454277 # 1..1
7821 12:29:11.454419 # 1..1
7822 12:29:11.454561 # 1..1
7823 12:29:11.454702 # 1..1
7824 12:29:11.454843 # 1..1
7825 12:29:11.454984 # 1..1
7826 12:29:11.455126 # 1..1
7827 12:29:11.455267 # 1..1
7828 12:29:11.455407 # 1..1
7829 12:29:11.455549 # 1..1
7830 12:29:11.455689 # 1..1
7831 12:29:11.455829 # 1..1
7832 12:29:11.455970 # 1..1
7833 12:29:11.456111 # 1..1
7834 12:29:11.456252 # 1..1
7835 12:29:11.456395 # 1..1
7836 12:29:11.456537 # 1..1
7837 12:29:11.456679 # 1..1
7838 12:29:11.456820 # 1..1
7839 12:29:11.456962 # 1..1
7840 12:29:11.457102 # 1..1
7841 12:29:11.457244 # 1..1
7842 12:29:11.457388 # 1..1
7843 12:29:11.457529 # 1..1
7844 12:29:11.457687 # 1..1
7845 12:29:11.457832 # 1..1
7846 12:29:11.457974 # 1..1
7847 12:29:11.458115 # 1..1
7848 12:29:11.458257 # 1..1
7849 12:29:11.458403 # 1..1
7850 12:29:11.458603 # 1..1
7851 12:29:11.458739 # 1..1
7852 12:29:11.458884 # 1..1
7853 12:29:11.459027 # 1..1
7854 12:29:11.459170 # 1..1
7855 12:29:11.459313 # 1..1
7856 12:29:11.459455 # 1..1
7857 12:29:11.459597 # 1..1
7858 12:29:11.459739 # 1..1
7859 12:29:11.459881 # 1..1
7860 12:29:11.460022 # 1..1
7861 12:29:11.460164 # 1..1
7862 12:29:11.460309 # 1..1
7863 12:29:11.460451 # 1..1
7864 12:29:11.460593 # 1..1
7865 12:29:11.460735 # 1..1
7866 12:29:11.460877 # 1..1
7867 12:29:11.461019 # 1..1
7868 12:29:11.461163 # 1..1
7869 12:29:11.461307 # 1..1
7870 12:29:11.461447 # 1..1
7871 12:29:11.461587 # 1..1
7872 12:29:11.461746 # 1..1
7873 12:29:11.461889 # 1..1
7874 12:29:11.462029 # 1..1
7875 12:29:11.462173 # 1..1
7876 12:29:11.475442 # 1..1
7877 12:29:11.475780 # 1..1
7878 12:29:11.475988 # 1..1
7879 12:29:11.476387 # 1..1
7880 12:29:11.476497 # 1..1
7881 12:29:11.476580 # 1..1
7882 12:29:11.476655 # 1..1
7883 12:29:11.476727 # 1..1
7884 12:29:11.476798 # 1..1
7885 12:29:11.476871 # 1..1
7886 12:29:11.476942 # 1..1
7887 12:29:11.477013 # 1..1
7888 12:29:11.477083 # 1..1
7889 12:29:11.477154 # 1..1
7890 12:29:11.477225 # 1..1
7891 12:29:11.477298 # 1..1
7892 12:29:11.477369 # 1..1
7893 12:29:11.477439 # 1..1
7894 12:29:11.477510 # 1..1
7895 12:29:11.477579 # 1..1
7896 12:29:11.477656 # 1..1
7897 12:29:11.477728 # 1..1
7898 12:29:11.477798 # 1..1
7899 12:29:11.477868 # 1..1
7900 12:29:11.477937 # 1..1
7901 12:29:11.478005 # 1..1
7902 12:29:11.478075 # 1..1
7903 12:29:11.478145 # 1..1
7904 12:29:11.478214 # 1..1
7905 12:29:11.478304 # 1..1
7906 12:29:11.478378 # 1..1
7907 12:29:11.478448 # 1..1
7908 12:29:11.478517 # 1..1
7909 12:29:11.478588 # 1..1
7910 12:29:11.478657 # 1..1
7911 12:29:11.478727 # 1..1
7912 12:29:11.478796 # 1..1
7913 12:29:11.478864 # 1..1
7914 12:29:11.478934 # 1..1
7915 12:29:11.479003 # 1..1
7916 12:29:11.479075 # 1..1
7917 12:29:11.479147 # 1..1
7918 12:29:11.479219 # 1..1
7919 12:29:11.479294 # 1..1
7920 12:29:11.479367 # 1..1
7921 12:29:11.479442 # 1..1
7922 12:29:11.479514 # 1..1
7923 12:29:11.479585 # 1..1
7924 12:29:11.479659 # 1..1
7925 12:29:11.479730 # 1..1
7926 12:29:11.479804 # 1..1
7927 12:29:11.479876 # 1..1
7928 12:29:11.479949 # 1..1
7929 12:29:11.480023 # 1..1
7930 12:29:11.480096 # 1..1
7931 12:29:11.480167 # 1..1
7932 12:29:11.480239 # 1..1
7933 12:29:11.480315 # 1..1
7934 12:29:11.480394 # 1..1
7935 12:29:11.480475 # 1..1
7936 12:29:11.480551 # 1..1
7937 12:29:11.480625 # 1..1
7938 12:29:11.480697 # 1..1
7939 12:29:11.480768 # 1..1
7940 12:29:11.480838 # 1..1
7941 12:29:11.480910 # 1..1
7942 12:29:11.480981 # 1..1
7943 12:29:11.481053 # 1..1
7944 12:29:11.481125 # 1..1
7945 12:29:11.503648 # 1..1
7946 12:29:11.503926 # 1..1
7947 12:29:11.504051 # 1..1
7948 12:29:11.504167 # 1..1
7949 12:29:11.504282 # 1..1
7950 12:29:11.504929 #
7951 12:29:11.505301 not ok 37 selftests: arm64: check_gcr_el1_cswitch # TIMEOUT 45 seconds
7952 12:29:11.957000 # selftests: arm64: check_ksm_options
7953 12:29:12.700234 # 1..4
7954 12:29:12.700521 # # Invalid MTE synchronous exception caught!
7955 12:29:12.779956 not ok 38 selftests: arm64: check_ksm_options # exit=1
7956 12:29:13.356972 # selftests: arm64: check_mmap_options
7957 12:29:14.477811 # 1..22
7958 12:29:14.478988 # ok 1 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check off
7959 12:29:14.479348 # ok 2 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check off
7960 12:29:14.479446 # ok 3 Check anonymous memory with private mapping, no error mode, mmap memory and tag check off
7961 12:29:14.479545 # ok 4 Check file memory with private mapping, no error mode, mmap/mprotect memory and tag check off
7962 12:29:14.479827 # not ok 5 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check on
7963 12:29:14.479935 # not ok 6 Check anonymous memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
7964 12:29:14.480111 # not ok 7 Check anonymous memory with shared mapping, sync error mode, mmap memory and tag check on
7965 12:29:14.480204 # not ok 8 Check anonymous memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
7966 12:29:14.480491 # not ok 9 Check anonymous memory with private mapping, async error mode, mmap memory and tag check on
7967 12:29:14.480586 # not ok 10 Check anonymous memory with private mapping, async error mode, mmap/mprotect memory and tag check on
7968 12:29:14.481825 # not ok 11 Check anonymous memory with shared mapping, async error mode, mmap memory and tag check on
7969 12:29:14.481945 # not ok 12 Check anonymous memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
7970 12:29:14.482034 # not ok 13 Check file memory with private mapping, sync error mode, mmap memory and tag check on
7971 12:29:14.482121 # not ok 14 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
7972 12:29:14.482199 # not ok 15 Check file memory with shared mapping, sync error mode, mmap memory and tag check on
7973 12:29:14.482278 # not ok 16 Check file memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
7974 12:29:14.505241 # not ok 17 Check file memory with private mapping, async error mode, mmap memory and tag check on
7975 12:29:14.505710 # not ok 18 Check file memory with private mapping, async error mode, mmap/mprotect memory and tag check on
7976 12:29:14.505811 # not ok 19 Check file memory with shared mapping, async error mode, mmap memory and tag check on
7977 12:29:14.541885 # not ok 20 Check file memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
7978 12:29:14.543061 # not ok 21 Check clear PROT_MTE flags with private mapping, sync error mode and mmap memory
7979 12:29:14.543580 # not ok 22 Check clear PROT_MTE flags with private mapping and sync error mode and mmap/mprotect memory
7980 12:29:14.543691 # # Totals: pass:4 fail:18 xfail:0 xpass:0 skip:0 error:0
7981 12:29:14.559326 not ok 39 selftests: arm64: check_mmap_options # exit=1
7982 12:29:14.928570 # selftests: arm64: check_prctl
7983 12:29:15.317141 # TAP version 13
7984 12:29:15.317404 # 1..5
7985 12:29:15.317709 # ok 1 check_basic_read
7986 12:29:15.317808 # ok 2 NONE
7987 12:29:15.317890 # ok 3 SYNC
7988 12:29:15.317963 # ok 4 ASYNC
7989 12:29:15.318036 # ok 5 SYNC+ASYNC
7990 12:29:15.318108 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
7991 12:29:15.379233 ok 40 selftests: arm64: check_prctl
7992 12:29:15.770056 # selftests: arm64: check_tags_inclusion
7993 12:29:16.159117 # 1..4
7994 12:29:16.159600 # # Unexpected fault recorded for 0x500ffff80e8a000-0x500ffff80e8a050 in mode 1
7995 12:29:16.159709 # not ok 1 Check an included tag value with sync mode
7996 12:29:16.159805 # # Unexpected fault recorded for 0x100ffff80e8a000-0x100ffff80e8a050 in mode 1
7997 12:29:16.159911 # not ok 2 Check different included tags value with sync mode
7998 12:29:16.159999 # ok 3 Check none included tags value with sync mode
7999 12:29:16.161792 # # Unexpected fault recorded for 0xa00ffff80e8a000-0xa00ffff80e8a050 in mode 1
8000 12:29:16.161902 # not ok 4 Check all included tags value with sync mode
8001 12:29:16.161982 # # Totals: pass:1 fail:3 xfail:0 xpass:0 skip:0 error:0
8002 12:29:16.228083 not ok 41 selftests: arm64: check_tags_inclusion # exit=1
8003 12:29:16.584293 # selftests: arm64: check_user_mem
8004 12:29:24.761752 # 1..64
8005 12:29:24.762068 # ok 1 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8006 12:29:24.762427 # ok 2 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8007 12:29:24.763143 # ok 3 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8008 12:29:24.763591 # ok 4 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8009 12:29:24.763791 # ok 5 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8010 12:29:24.763979 # ok 6 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8011 12:29:24.764180 # ok 7 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8012 12:29:24.764398 # ok 8 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8013 12:29:24.764603 # ok 9 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8014 12:29:24.764769 # ok 10 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8015 12:29:24.764895 # ok 11 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8016 12:29:24.765035 # ok 12 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8017 12:29:24.765173 # ok 13 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8018 12:29:24.765336 # ok 14 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8019 12:29:24.765539 # ok 15 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8020 12:29:24.765693 # ok 16 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8021 12:29:24.765882 # ok 17 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8022 12:29:24.766012 # ok 18 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8023 12:29:24.771304 # ok 19 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8024 12:29:24.771882 # ok 20 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8025 12:29:24.772118 # ok 21 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8026 12:29:24.772373 # ok 22 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8027 12:29:24.772608 # ok 23 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8028 12:29:24.772811 # ok 24 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8029 12:29:24.773077 # ok 25 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8030 12:29:24.773286 # ok 26 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8031 12:29:24.773508 # ok 27 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8032 12:29:24.773752 # ok 28 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8033 12:29:24.773964 # ok 29 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8034 12:29:24.774115 # ok 30 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8035 12:29:24.774529 # ok 31 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8036 12:29:24.774764 # ok 32 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8037 12:29:24.774999 # ok 33 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8038 12:29:24.775215 # ok 34 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8039 12:29:24.775457 # ok 35 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8040 12:29:24.775702 # ok 36 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8041 12:29:24.775941 # ok 37 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8042 12:29:24.776161 # ok 38 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8043 12:29:24.776367 # ok 39 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8044 12:29:24.777180 # ok 40 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8045 12:29:24.777432 # ok 41 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8046 12:29:24.777674 # ok 42 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8047 12:29:24.777865 # ok 43 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8048 12:29:24.777992 # ok 44 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8049 12:29:24.778110 # ok 45 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8050 12:29:24.786386 # ok 46 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8051 12:29:24.786622 # ok 47 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8052 12:29:24.787091 # ok 48 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8053 12:29:24.787282 # ok 49 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8054 12:29:24.787418 # ok 50 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8055 12:29:24.787746 # ok 51 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8056 12:29:26.351308 # ok 52 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8057 12:29:26.351899 # ok 53 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8058 12:29:26.352065 # ok 54 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8059 12:29:26.352275 # ok 55 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8060 12:29:26.352469 # ok 56 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8061 12:29:26.352613 # ok 57 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8062 12:29:26.352758 # ok 58 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8063 12:29:26.352935 # ok 59 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8064 12:29:26.353072 # ok 60 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8065 12:29:26.353247 # ok 61 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8066 12:29:26.353415 # ok 62 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8067 12:29:26.353819 # ok 63 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8068 12:29:26.357069 # ok 64 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8069 12:29:26.357502 # # Totals: pass:64 fail:0 xfail:0 xpass:0 skip:0 error:0
8070 12:29:26.373582 ok 42 selftests: arm64: check_user_mem
8071 12:29:26.500244 # selftests: arm64: btitest
8072 12:29:26.649105 # TAP version 13
8073 12:29:26.649405 # 1..18
8074 12:29:26.649749 # # HWCAP_PACA present
8075 12:29:26.650145 # # HWCAP2_BTI present
8076 12:29:26.650280 # # Test binary built for BTI
8077 12:29:26.650399 # # [SIGILL in nohint_func/call_using_br_x0, BTYPE=11 (expected)]
8078 12:29:26.650516 # ok 1 nohint_func/call_using_br_x0
8079 12:29:26.653410 # # [SIGILL in nohint_func/call_using_br_x16, BTYPE=01 (expected)]
8080 12:29:26.653615 # ok 2 nohint_func/call_using_br_x16
8081 12:29:26.653928 # # [SIGILL in nohint_func/call_using_blr, BTYPE=10 (expected)]
8082 12:29:26.654015 # ok 3 nohint_func/call_using_blr
8083 12:29:26.660119 # # [SIGILL in bti_none_func/call_using_br_x0, BTYPE=11 (expected)]
8084 12:29:26.660562 # ok 4 bti_none_func/call_using_br_x0
8085 12:29:26.660648 # # [SIGILL in bti_none_func/call_using_br_x16, BTYPE=01 (expected)]
8086 12:29:26.660723 # ok 5 bti_none_func/call_using_br_x16
8087 12:29:26.660808 # # [SIGILL in bti_none_func/call_using_blr, BTYPE=10 (expected)]
8088 12:29:26.660897 # ok 6 bti_none_func/call_using_blr
8089 12:29:26.661161 # # [SIGILL in bti_c_func/call_using_br_x0, BTYPE=11 (expected)]
8090 12:29:26.661240 # ok 7 bti_c_func/call_using_br_x0
8091 12:29:26.661325 # ok 8 bti_c_func/call_using_br_x16
8092 12:29:26.661410 # ok 9 bti_c_func/call_using_blr
8093 12:29:26.661497 # ok 10 bti_j_func/call_using_br_x0
8094 12:29:26.661573 # ok 11 bti_j_func/call_using_br_x16
8095 12:29:26.661666 # # [SIGILL in bti_j_func/call_using_blr, BTYPE=10 (expected)]
8096 12:29:26.661754 # ok 12 bti_j_func/call_using_blr
8097 12:29:26.661831 # ok 13 bti_jc_func/call_using_br_x0
8098 12:29:26.665002 # ok 14 bti_jc_func/call_using_br_x16
8099 12:29:26.665143 # ok 15 bti_jc_func/call_using_blr
8100 12:29:26.665232 # # [SIGILL in paciasp_func/call_using_br_x0, BTYPE=11 (expected)]
8101 12:29:26.665308 # ok 16 paciasp_func/call_using_br_x0
8102 12:29:26.665394 # ok 17 paciasp_func/call_using_br_x16
8103 12:29:26.665481 # ok 18 paciasp_func/call_using_blr
8104 12:29:26.665557 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8105 12:29:26.684500 ok 43 selftests: arm64: btitest
8106 12:29:26.821618 # selftests: arm64: nobtitest
8107 12:29:26.940832 # TAP version 13
8108 12:29:26.941082 # 1..18
8109 12:29:26.941170 # # HWCAP_PACA present
8110 12:29:26.941528 # # HWCAP2_BTI present
8111 12:29:26.941638 # # Test binary not built for BTI
8112 12:29:26.941733 # ok 1 nohint_func/call_using_br_x0
8113 12:29:26.941819 # ok 2 nohint_func/call_using_br_x16
8114 12:29:26.941900 # ok 3 nohint_func/call_using_blr
8115 12:29:26.941996 # ok 4 bti_none_func/call_using_br_x0
8116 12:29:26.942081 # ok 5 bti_none_func/call_using_br_x16
8117 12:29:26.943340 # ok 6 bti_none_func/call_using_blr
8118 12:29:26.943791 # ok 7 bti_c_func/call_using_br_x0
8119 12:29:26.943984 # ok 8 bti_c_func/call_using_br_x16
8120 12:29:26.944194 # ok 9 bti_c_func/call_using_blr
8121 12:29:26.944416 # ok 10 bti_j_func/call_using_br_x0
8122 12:29:26.944580 # ok 11 bti_j_func/call_using_br_x16
8123 12:29:26.944734 # ok 12 bti_j_func/call_using_blr
8124 12:29:26.944915 # ok 13 bti_jc_func/call_using_br_x0
8125 12:29:26.945047 # ok 14 bti_jc_func/call_using_br_x16
8126 12:29:26.945164 # ok 15 bti_jc_func/call_using_blr
8127 12:29:26.945279 # ok 16 paciasp_func/call_using_br_x0
8128 12:29:26.945394 # ok 17 paciasp_func/call_using_br_x16
8129 12:29:26.945530 # ok 18 paciasp_func/call_using_blr
8130 12:29:26.945678 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8131 12:29:26.968708 ok 44 selftests: arm64: nobtitest
8132 12:29:27.096135 # selftests: arm64: hwcap
8133 12:29:27.275750 # TAP version 13
8134 12:29:27.276178 # 1..28
8135 12:29:27.276289 # # RNG present
8136 12:29:27.276385 # ok 1 cpuinfo_match_RNG
8137 12:29:27.276474 # ok 2 sigill_RNG
8138 12:29:27.276563 # # SME present
8139 12:29:27.276672 # ok 3 cpuinfo_match_SME
8140 12:29:27.276758 # ok 4 sigill_SME
8141 12:29:27.276861 # # SVE present
8142 12:29:27.276953 # ok 5 cpuinfo_match_SVE
8143 12:29:27.277051 # ok 6 sigill_SVE
8144 12:29:27.277146 # # SVE 2 present
8145 12:29:27.277236 # ok 7 cpuinfo_match_SVE 2
8146 12:29:27.277320 # ok 8 sigill_SVE 2
8147 12:29:27.277405 # # SVE AES present
8148 12:29:27.277489 # ok 9 cpuinfo_match_SVE AES
8149 12:29:27.277603 # ok 10 sigill_SVE AES
8150 12:29:27.277702 # # SVE2 PMULL present
8151 12:29:27.277788 # ok 11 cpuinfo_match_SVE2 PMULL
8152 12:29:27.277868 # ok 12 sigill_SVE2 PMULL
8153 12:29:27.277944 # # SVE2 BITPERM present
8154 12:29:27.278018 # ok 13 cpuinfo_match_SVE2 BITPERM
8155 12:29:27.278110 # ok 14 sigill_SVE2 BITPERM
8156 12:29:27.278188 # # SVE2 SHA3 present
8157 12:29:27.278263 # ok 15 cpuinfo_match_SVE2 SHA3
8158 12:29:27.284624 # ok 16 sigill_SVE2 SHA3
8159 12:29:27.285187 # # SVE2 SM4 present
8160 12:29:27.285378 # ok 17 cpuinfo_match_SVE2 SM4
8161 12:29:27.285548 # ok 18 sigill_SVE2 SM4
8162 12:29:27.285884 # # SVE2 I8MM present
8163 12:29:27.286022 # ok 19 cpuinfo_match_SVE2 I8MM
8164 12:29:27.286171 # ok 20 sigill_SVE2 I8MM
8165 12:29:27.286317 # # SVE2 F32MM present
8166 12:29:27.286437 # ok 21 cpuinfo_match_SVE2 F32MM
8167 12:29:27.286584 # ok 22 sigill_SVE2 F32MM
8168 12:29:27.286708 # # SVE2 F64MM present
8169 12:29:27.286827 # ok 23 cpuinfo_match_SVE2 F64MM
8170 12:29:27.286944 # ok 24 sigill_SVE2 F64MM
8171 12:29:27.287061 # # SVE2 BF16 present
8172 12:29:27.287178 # ok 25 cpuinfo_match_SVE2 BF16
8173 12:29:27.287293 # ok 26 sigill_SVE2 BF16
8174 12:29:27.299372 # ok 27 cpuinfo_match_SVE2 EBF16
8175 12:29:27.299618 # ok 28 # SKIP sigill_SVE2 EBF16
8176 12:29:27.299918 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:1 error:0
8177 12:29:27.304077 ok 45 selftests: arm64: hwcap
8178 12:29:27.463425 # selftests: arm64: ptrace
8179 12:29:27.614921 # TAP version 13
8180 12:29:27.615166 # 1..7
8181 12:29:27.615502 # # Parent is 4088, child is 4089
8182 12:29:27.615677 # ok 1 read_tpidr_one
8183 12:29:27.615858 # ok 2 write_tpidr_one
8184 12:29:27.616013 # ok 3 verify_tpidr_one
8185 12:29:27.616159 # ok 4 count_tpidrs
8186 12:29:27.616304 # ok 5 tpidr2_write
8187 12:29:27.616449 # ok 6 tpidr2_read
8188 12:29:27.616595 # ok 7 write_tpidr_only
8189 12:29:27.616739 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
8190 12:29:27.643454 ok 46 selftests: arm64: ptrace
8191 12:29:27.752606 # selftests: arm64: syscall-abi
8192 12:29:30.380559 # TAP version 13
8193 12:29:30.380981 # 1..514
8194 12:29:30.381086 # # SME with FA64
8195 12:29:30.381171 # ok 1 getpid() FPSIMD
8196 12:29:30.381257 # ok 2 getpid() SVE VL 256
8197 12:29:30.381341 # ok 3 getpid() SVE VL 256/SME VL 256 SM+ZA
8198 12:29:30.381445 # ok 4 getpid() SVE VL 256/SME VL 256 SM
8199 12:29:30.381533 # ok 5 getpid() SVE VL 256/SME VL 256 ZA
8200 12:29:30.381617 # ok 6 getpid() SVE VL 256/SME VL 128 SM+ZA
8201 12:29:30.381709 # ok 7 getpid() SVE VL 256/SME VL 128 SM
8202 12:29:30.381810 # ok 8 getpid() SVE VL 256/SME VL 128 ZA
8203 12:29:30.381895 # ok 9 getpid() SVE VL 256/SME VL 64 SM+ZA
8204 12:29:30.381979 # ok 10 getpid() SVE VL 256/SME VL 64 SM
8205 12:29:30.382820 # ok 11 getpid() SVE VL 256/SME VL 64 ZA
8206 12:29:30.383165 # ok 12 getpid() SVE VL 256/SME VL 32 SM+ZA
8207 12:29:30.383377 # ok 13 getpid() SVE VL 256/SME VL 32 SM
8208 12:29:30.383576 # ok 14 getpid() SVE VL 256/SME VL 32 ZA
8209 12:29:30.383756 # ok 15 getpid() SVE VL 256/SME VL 16 SM+ZA
8210 12:29:30.383924 # ok 16 getpid() SVE VL 256/SME VL 16 SM
8211 12:29:30.384064 # ok 17 getpid() SVE VL 256/SME VL 16 ZA
8212 12:29:30.384248 # ok 18 getpid() SVE VL 240
8213 12:29:30.384413 # ok 19 getpid() SVE VL 240/SME VL 256 SM+ZA
8214 12:29:30.384576 # ok 20 getpid() SVE VL 240/SME VL 256 SM
8215 12:29:30.384744 # ok 21 getpid() SVE VL 240/SME VL 256 ZA
8216 12:29:30.384909 # ok 22 getpid() SVE VL 240/SME VL 128 SM+ZA
8217 12:29:30.385106 # ok 23 getpid() SVE VL 240/SME VL 128 SM
8218 12:29:30.385279 # ok 24 getpid() SVE VL 240/SME VL 128 ZA
8219 12:29:30.385434 # ok 25 getpid() SVE VL 240/SME VL 64 SM+ZA
8220 12:29:30.385598 # ok 26 getpid() SVE VL 240/SME VL 64 SM
8221 12:29:30.385773 # ok 27 getpid() SVE VL 240/SME VL 64 ZA
8222 12:29:30.385899 # ok 28 getpid() SVE VL 240/SME VL 32 SM+ZA
8223 12:29:30.386021 # ok 29 getpid() SVE VL 240/SME VL 32 SM
8224 12:29:30.386166 # ok 30 getpid() SVE VL 240/SME VL 32 ZA
8225 12:29:30.386289 # ok 31 getpid() SVE VL 240/SME VL 16 SM+ZA
8226 12:29:30.386408 # ok 32 getpid() SVE VL 240/SME VL 16 SM
8227 12:29:30.386526 # ok 33 getpid() SVE VL 240/SME VL 16 ZA
8228 12:29:30.386642 # ok 34 getpid() SVE VL 224
8229 12:29:30.386759 # ok 35 getpid() SVE VL 224/SME VL 256 SM+ZA
8230 12:29:30.390200 # ok 36 getpid() SVE VL 224/SME VL 256 SM
8231 12:29:30.390494 # ok 37 getpid() SVE VL 224/SME VL 256 ZA
8232 12:29:30.390903 # ok 38 getpid() SVE VL 224/SME VL 128 SM+ZA
8233 12:29:30.391099 # ok 39 getpid() SVE VL 224/SME VL 128 SM
8234 12:29:30.391281 # ok 40 getpid() SVE VL 224/SME VL 128 ZA
8235 12:29:30.391428 # ok 41 getpid() SVE VL 224/SME VL 64 SM+ZA
8236 12:29:30.391554 # ok 42 getpid() SVE VL 224/SME VL 64 SM
8237 12:29:30.391672 # ok 43 getpid() SVE VL 224/SME VL 64 ZA
8238 12:29:30.391809 # ok 44 getpid() SVE VL 224/SME VL 32 SM+ZA
8239 12:29:30.391973 # ok 45 getpid() SVE VL 224/SME VL 32 SM
8240 12:29:30.392109 # ok 46 getpid() SVE VL 224/SME VL 32 ZA
8241 12:29:30.392248 # ok 47 getpid() SVE VL 224/SME VL 16 SM+ZA
8242 12:29:30.392384 # ok 48 getpid() SVE VL 224/SME VL 16 SM
8243 12:29:30.392526 # ok 49 getpid() SVE VL 224/SME VL 16 ZA
8244 12:29:30.392679 # ok 50 getpid() SVE VL 208
8245 12:29:30.392849 # ok 51 getpid() SVE VL 208/SME VL 256 SM+ZA
8246 12:29:30.393010 # ok 52 getpid() SVE VL 208/SME VL 256 SM
8247 12:29:30.393150 # ok 53 getpid() SVE VL 208/SME VL 256 ZA
8248 12:29:30.393298 # ok 54 getpid() SVE VL 208/SME VL 128 SM+ZA
8249 12:29:30.393440 # ok 55 getpid() SVE VL 208/SME VL 128 SM
8250 12:29:30.393597 # ok 56 getpid() SVE VL 208/SME VL 128 ZA
8251 12:29:30.393789 # ok 57 getpid() SVE VL 208/SME VL 64 SM+ZA
8252 12:29:30.393914 # ok 58 getpid() SVE VL 208/SME VL 64 SM
8253 12:29:30.394031 # ok 59 getpid() SVE VL 208/SME VL 64 ZA
8254 12:29:30.394147 # ok 60 getpid() SVE VL 208/SME VL 32 SM+ZA
8255 12:29:30.394261 # ok 61 getpid() SVE VL 208/SME VL 32 SM
8256 12:29:30.394377 # ok 62 getpid() SVE VL 208/SME VL 32 ZA
8257 12:29:30.394492 # ok 63 getpid() SVE VL 208/SME VL 16 SM+ZA
8258 12:29:30.398075 # ok 64 getpid() SVE VL 208/SME VL 16 SM
8259 12:29:30.398588 # ok 65 getpid() SVE VL 208/SME VL 16 ZA
8260 12:29:30.398813 # ok 66 getpid() SVE VL 192
8261 12:29:30.399044 # ok 67 getpid() SVE VL 192/SME VL 256 SM+ZA
8262 12:29:30.399226 # ok 68 getpid() SVE VL 192/SME VL 256 SM
8263 12:29:30.399396 # ok 69 getpid() SVE VL 192/SME VL 256 ZA
8264 12:29:30.399587 # ok 70 getpid() SVE VL 192/SME VL 128 SM+ZA
8265 12:29:30.399754 # ok 71 getpid() SVE VL 192/SME VL 128 SM
8266 12:29:30.399921 # ok 72 getpid() SVE VL 192/SME VL 128 ZA
8267 12:29:30.400099 # ok 73 getpid() SVE VL 192/SME VL 64 SM+ZA
8268 12:29:30.400265 # ok 74 getpid() SVE VL 192/SME VL 64 SM
8269 12:29:30.400477 # ok 75 getpid() SVE VL 192/SME VL 64 ZA
8270 12:29:30.400695 # ok 76 getpid() SVE VL 192/SME VL 32 SM+ZA
8271 12:29:30.400898 # ok 77 getpid() SVE VL 192/SME VL 32 SM
8272 12:29:30.401094 # ok 78 getpid() SVE VL 192/SME VL 32 ZA
8273 12:29:30.401285 # ok 79 getpid() SVE VL 192/SME VL 16 SM+ZA
8274 12:29:30.401498 # ok 80 getpid() SVE VL 192/SME VL 16 SM
8275 12:29:30.401670 # ok 81 getpid() SVE VL 192/SME VL 16 ZA
8276 12:29:30.401880 # ok 82 getpid() SVE VL 176
8277 12:29:30.402071 # ok 83 getpid() SVE VL 176/SME VL 256 SM+ZA
8278 12:29:30.402265 # ok 84 getpid() SVE VL 176/SME VL 256 SM
8279 12:29:30.402411 # ok 85 getpid() SVE VL 176/SME VL 256 ZA
8280 12:29:30.402556 # ok 86 getpid() SVE VL 176/SME VL 128 SM+ZA
8281 12:29:30.402698 # ok 87 getpid() SVE VL 176/SME VL 128 SM
8282 12:29:30.402841 # ok 88 getpid() SVE VL 176/SME VL 128 ZA
8283 12:29:30.402984 # ok 89 getpid() SVE VL 176/SME VL 64 SM+ZA
8284 12:29:30.403126 # ok 90 getpid() SVE VL 176/SME VL 64 SM
8285 12:29:30.403270 # ok 91 getpid() SVE VL 176/SME VL 64 ZA
8286 12:29:30.403413 # ok 92 getpid() SVE VL 176/SME VL 32 SM+ZA
8287 12:29:30.403556 # ok 93 getpid() SVE VL 176/SME VL 32 SM
8288 12:29:30.403698 # ok 94 getpid() SVE VL 176/SME VL 32 ZA
8289 12:29:30.403841 # ok 95 getpid() SVE VL 176/SME VL 16 SM+ZA
8290 12:29:30.404024 # ok 96 getpid() SVE VL 176/SME VL 16 SM
8291 12:29:30.404160 # ok 97 getpid() SVE VL 176/SME VL 16 ZA
8292 12:29:30.404304 # ok 98 getpid() SVE VL 160
8293 12:29:32.874319 # ok 99 getpid() SVE VL 160/SME VL 256 SM+ZA
8294 12:29:32.874553 # ok 100 getpid() SVE VL 160/SME VL 256 SM
8295 12:29:32.874837 # ok 101 getpid() SVE VL 160/SME VL 256 ZA
8296 12:29:32.874998 # ok 102 getpid() SVE VL 160/SME VL 128 SM+ZA
8297 12:29:32.875087 # ok 103 getpid() SVE VL 160/SME VL 128 SM
8298 12:29:32.875164 # ok 104 getpid() SVE VL 160/SME VL 128 ZA
8299 12:29:32.875244 # ok 105 getpid() SVE VL 160/SME VL 64 SM+ZA
8300 12:29:32.875340 # ok 106 getpid() SVE VL 160/SME VL 64 SM
8301 12:29:32.875425 # ok 107 getpid() SVE VL 160/SME VL 64 ZA
8302 12:29:32.875506 # ok 108 getpid() SVE VL 160/SME VL 32 SM+ZA
8303 12:29:32.875602 # ok 109 getpid() SVE VL 160/SME VL 32 SM
8304 12:29:32.875877 # ok 110 getpid() SVE VL 160/SME VL 32 ZA
8305 12:29:32.875963 # ok 111 getpid() SVE VL 160/SME VL 16 SM+ZA
8306 12:29:32.876052 # ok 112 getpid() SVE VL 160/SME VL 16 SM
8307 12:29:32.876325 # ok 113 getpid() SVE VL 160/SME VL 16 ZA
8308 12:29:32.876416 # ok 114 getpid() SVE VL 144
8309 12:29:32.876698 # ok 115 getpid() SVE VL 144/SME VL 256 SM+ZA
8310 12:29:32.876991 # ok 116 getpid() SVE VL 144/SME VL 256 SM
8311 12:29:32.877081 # ok 117 getpid() SVE VL 144/SME VL 256 ZA
8312 12:29:32.877354 # ok 118 getpid() SVE VL 144/SME VL 128 SM+ZA
8313 12:29:32.877437 # ok 119 getpid() SVE VL 144/SME VL 128 SM
8314 12:29:32.877698 # ok 120 getpid() SVE VL 144/SME VL 128 ZA
8315 12:29:32.877826 # ok 121 getpid() SVE VL 144/SME VL 64 SM+ZA
8316 12:29:32.882662 # ok 122 getpid() SVE VL 144/SME VL 64 SM
8317 12:29:32.882874 # ok 123 getpid() SVE VL 144/SME VL 64 ZA
8318 12:29:32.883021 # ok 124 getpid() SVE VL 144/SME VL 32 SM+ZA
8319 12:29:32.883104 # ok 125 getpid() SVE VL 144/SME VL 32 SM
8320 12:29:32.883402 # ok 126 getpid() SVE VL 144/SME VL 32 ZA
8321 12:29:32.883494 # ok 127 getpid() SVE VL 144/SME VL 16 SM+ZA
8322 12:29:32.883570 # ok 128 getpid() SVE VL 144/SME VL 16 SM
8323 12:29:32.883642 # ok 129 getpid() SVE VL 144/SME VL 16 ZA
8324 12:29:32.883712 # ok 130 getpid() SVE VL 128
8325 12:29:32.883782 # ok 131 getpid() SVE VL 128/SME VL 256 SM+ZA
8326 12:29:32.883852 # ok 132 getpid() SVE VL 128/SME VL 256 SM
8327 12:29:32.883922 # ok 133 getpid() SVE VL 128/SME VL 256 ZA
8328 12:29:32.884007 # ok 134 getpid() SVE VL 128/SME VL 128 SM+ZA
8329 12:29:32.884079 # ok 135 getpid() SVE VL 128/SME VL 128 SM
8330 12:29:32.884149 # ok 136 getpid() SVE VL 128/SME VL 128 ZA
8331 12:29:32.884218 # ok 137 getpid() SVE VL 128/SME VL 64 SM+ZA
8332 12:29:32.884304 # ok 138 getpid() SVE VL 128/SME VL 64 SM
8333 12:29:32.884376 # ok 139 getpid() SVE VL 128/SME VL 64 ZA
8334 12:29:32.884445 # ok 140 getpid() SVE VL 128/SME VL 32 SM+ZA
8335 12:29:32.884514 # ok 141 getpid() SVE VL 128/SME VL 32 SM
8336 12:29:32.884638 # ok 142 getpid() SVE VL 128/SME VL 32 ZA
8337 12:29:32.884723 # ok 143 getpid() SVE VL 128/SME VL 16 SM+ZA
8338 12:29:32.884794 # ok 144 getpid() SVE VL 128/SME VL 16 SM
8339 12:29:32.884865 # ok 145 getpid() SVE VL 128/SME VL 16 ZA
8340 12:29:32.884941 # ok 146 getpid() SVE VL 112
8341 12:29:32.885027 # ok 147 getpid() SVE VL 112/SME VL 256 SM+ZA
8342 12:29:32.885099 # ok 148 getpid() SVE VL 112/SME VL 256 SM
8343 12:29:32.885172 # ok 149 getpid() SVE VL 112/SME VL 256 ZA
8344 12:29:32.885258 # ok 150 getpid() SVE VL 112/SME VL 128 SM+ZA
8345 12:29:32.885343 # ok 151 getpid() SVE VL 112/SME VL 128 SM
8346 12:29:32.885415 # ok 152 getpid() SVE VL 112/SME VL 128 ZA
8347 12:29:32.885497 # ok 153 getpid() SVE VL 112/SME VL 64 SM+ZA
8348 12:29:32.885570 # ok 154 getpid() SVE VL 112/SME VL 64 SM
8349 12:29:32.885661 # ok 155 getpid() SVE VL 112/SME VL 64 ZA
8350 12:29:32.885941 # ok 156 getpid() SVE VL 112/SME VL 32 SM+ZA
8351 12:29:32.890064 # ok 157 getpid() SVE VL 112/SME VL 32 SM
8352 12:29:32.890433 # ok 158 getpid() SVE VL 112/SME VL 32 ZA
8353 12:29:32.890521 # ok 159 getpid() SVE VL 112/SME VL 16 SM+ZA
8354 12:29:32.890600 # ok 160 getpid() SVE VL 112/SME VL 16 SM
8355 12:29:32.890677 # ok 161 getpid() SVE VL 112/SME VL 16 ZA
8356 12:29:32.890755 # ok 162 getpid() SVE VL 96
8357 12:29:32.890848 # ok 163 getpid() SVE VL 96/SME VL 256 SM+ZA
8358 12:29:32.890928 # ok 164 getpid() SVE VL 96/SME VL 256 SM
8359 12:29:32.891006 # ok 165 getpid() SVE VL 96/SME VL 256 ZA
8360 12:29:32.893756 # ok 166 getpid() SVE VL 96/SME VL 128 SM+ZA
8361 12:29:32.893973 # ok 167 getpid() SVE VL 96/SME VL 128 SM
8362 12:29:32.894109 # ok 168 getpid() SVE VL 96/SME VL 128 ZA
8363 12:29:32.894231 # ok 169 getpid() SVE VL 96/SME VL 64 SM+ZA
8364 12:29:32.894350 # ok 170 getpid() SVE VL 96/SME VL 64 SM
8365 12:29:32.894466 # ok 171 getpid() SVE VL 96/SME VL 64 ZA
8366 12:29:32.894584 # ok 172 getpid() SVE VL 96/SME VL 32 SM+ZA
8367 12:29:32.894700 # ok 173 getpid() SVE VL 96/SME VL 32 SM
8368 12:29:32.894815 # ok 174 getpid() SVE VL 96/SME VL 32 ZA
8369 12:29:32.894933 # ok 175 getpid() SVE VL 96/SME VL 16 SM+ZA
8370 12:29:32.895050 # ok 176 getpid() SVE VL 96/SME VL 16 SM
8371 12:29:32.895166 # ok 177 getpid() SVE VL 96/SME VL 16 ZA
8372 12:29:32.895281 # ok 178 getpid() SVE VL 80
8373 12:29:32.895396 # ok 179 getpid() SVE VL 80/SME VL 256 SM+ZA
8374 12:29:32.895512 # ok 180 getpid() SVE VL 80/SME VL 256 SM
8375 12:29:32.895627 # ok 181 getpid() SVE VL 80/SME VL 256 ZA
8376 12:29:32.895744 # ok 182 getpid() SVE VL 80/SME VL 128 SM+ZA
8377 12:29:32.895860 # ok 183 getpid() SVE VL 80/SME VL 128 SM
8378 12:29:32.895975 # ok 184 getpid() SVE VL 80/SME VL 128 ZA
8379 12:29:32.896091 # ok 185 getpid() SVE VL 80/SME VL 64 SM+ZA
8380 12:29:32.896207 # ok 186 getpid() SVE VL 80/SME VL 64 SM
8381 12:29:32.896321 # ok 187 getpid() SVE VL 80/SME VL 64 ZA
8382 12:29:32.896436 # ok 188 getpid() SVE VL 80/SME VL 32 SM+ZA
8383 12:29:32.896552 # ok 189 getpid() SVE VL 80/SME VL 32 SM
8384 12:29:32.896666 # ok 190 getpid() SVE VL 80/SME VL 32 ZA
8385 12:29:32.898112 # ok 191 getpid() SVE VL 80/SME VL 16 SM+ZA
8386 12:29:32.898515 # ok 192 getpid() SVE VL 80/SME VL 16 SM
8387 12:29:32.898627 # ok 193 getpid() SVE VL 80/SME VL 16 ZA
8388 12:29:32.898717 # ok 194 getpid() SVE VL 64
8389 12:29:32.898803 # ok 195 getpid() SVE VL 64/SME VL 256 SM+ZA
8390 12:29:35.182588 # ok 196 getpid() SVE VL 64/SME VL 256 SM
8391 12:29:35.183212 # ok 197 getpid() SVE VL 64/SME VL 256 ZA
8392 12:29:35.183431 # ok 198 getpid() SVE VL 64/SME VL 128 SM+ZA
8393 12:29:35.183654 # ok 199 getpid() SVE VL 64/SME VL 128 SM
8394 12:29:35.183855 # ok 200 getpid() SVE VL 64/SME VL 128 ZA
8395 12:29:35.184067 # ok 201 getpid() SVE VL 64/SME VL 64 SM+ZA
8396 12:29:35.184474 # ok 202 getpid() SVE VL 64/SME VL 64 SM
8397 12:29:35.184669 # ok 203 getpid() SVE VL 64/SME VL 64 ZA
8398 12:29:35.184889 # ok 204 getpid() SVE VL 64/SME VL 32 SM+ZA
8399 12:29:35.185066 # ok 205 getpid() SVE VL 64/SME VL 32 SM
8400 12:29:35.185280 # ok 206 getpid() SVE VL 64/SME VL 32 ZA
8401 12:29:35.185461 # ok 207 getpid() SVE VL 64/SME VL 16 SM+ZA
8402 12:29:35.185671 # ok 208 getpid() SVE VL 64/SME VL 16 SM
8403 12:29:35.185857 # ok 209 getpid() SVE VL 64/SME VL 16 ZA
8404 12:29:35.185997 # ok 210 getpid() SVE VL 48
8405 12:29:35.186116 # ok 211 getpid() SVE VL 48/SME VL 256 SM+ZA
8406 12:29:35.186234 # ok 212 getpid() SVE VL 48/SME VL 256 SM
8407 12:29:35.186353 # ok 213 getpid() SVE VL 48/SME VL 256 ZA
8408 12:29:35.186468 # ok 214 getpid() SVE VL 48/SME VL 128 SM+ZA
8409 12:29:35.186585 # ok 215 getpid() SVE VL 48/SME VL 128 SM
8410 12:29:35.186701 # ok 216 getpid() SVE VL 48/SME VL 128 ZA
8411 12:29:35.186815 # ok 217 getpid() SVE VL 48/SME VL 64 SM+ZA
8412 12:29:35.186940 # ok 218 getpid() SVE VL 48/SME VL 64 SM
8413 12:29:35.187054 # ok 219 getpid() SVE VL 48/SME VL 64 ZA
8414 12:29:35.187170 # ok 220 getpid() SVE VL 48/SME VL 32 SM+ZA
8415 12:29:35.187316 # ok 221 getpid() SVE VL 48/SME VL 32 SM
8416 12:29:35.187441 # ok 222 getpid() SVE VL 48/SME VL 32 ZA
8417 12:29:35.187558 # ok 223 getpid() SVE VL 48/SME VL 16 SM+ZA
8418 12:29:35.187673 # ok 224 getpid() SVE VL 48/SME VL 16 SM
8419 12:29:35.187790 # ok 225 getpid() SVE VL 48/SME VL 16 ZA
8420 12:29:35.187940 # ok 226 getpid() SVE VL 32
8421 12:29:35.188087 # ok 227 getpid() SVE VL 32/SME VL 256 SM+ZA
8422 12:29:35.188822 # ok 228 getpid() SVE VL 32/SME VL 256 SM
8423 12:29:35.190340 # ok 229 getpid() SVE VL 32/SME VL 256 ZA
8424 12:29:35.190767 # ok 230 getpid() SVE VL 32/SME VL 128 SM+ZA
8425 12:29:35.190875 # ok 231 getpid() SVE VL 32/SME VL 128 SM
8426 12:29:35.190968 # ok 232 getpid() SVE VL 32/SME VL 128 ZA
8427 12:29:35.191052 # ok 233 getpid() SVE VL 32/SME VL 64 SM+ZA
8428 12:29:35.191145 # ok 234 getpid() SVE VL 32/SME VL 64 SM
8429 12:29:35.191226 # ok 235 getpid() SVE VL 32/SME VL 64 ZA
8430 12:29:35.191303 # ok 236 getpid() SVE VL 32/SME VL 32 SM+ZA
8431 12:29:35.191394 # ok 237 getpid() SVE VL 32/SME VL 32 SM
8432 12:29:35.191473 # ok 238 getpid() SVE VL 32/SME VL 32 ZA
8433 12:29:35.191563 # ok 239 getpid() SVE VL 32/SME VL 16 SM+ZA
8434 12:29:35.191654 # ok 240 getpid() SVE VL 32/SME VL 16 SM
8435 12:29:35.191941 # ok 241 getpid() SVE VL 32/SME VL 16 ZA
8436 12:29:35.192038 # ok 242 getpid() SVE VL 16
8437 12:29:35.192117 # ok 243 getpid() SVE VL 16/SME VL 256 SM+ZA
8438 12:29:35.192209 # ok 244 getpid() SVE VL 16/SME VL 256 SM
8439 12:29:35.192290 # ok 245 getpid() SVE VL 16/SME VL 256 ZA
8440 12:29:35.192579 # ok 246 getpid() SVE VL 16/SME VL 128 SM+ZA
8441 12:29:35.192774 # ok 247 getpid() SVE VL 16/SME VL 128 SM
8442 12:29:35.192927 # ok 248 getpid() SVE VL 16/SME VL 128 ZA
8443 12:29:35.193094 # ok 249 getpid() SVE VL 16/SME VL 64 SM+ZA
8444 12:29:35.193274 # ok 250 getpid() SVE VL 16/SME VL 64 SM
8445 12:29:35.193446 # ok 251 getpid() SVE VL 16/SME VL 64 ZA
8446 12:29:35.193573 # ok 252 getpid() SVE VL 16/SME VL 32 SM+ZA
8447 12:29:35.193744 # ok 253 getpid() SVE VL 16/SME VL 32 SM
8448 12:29:35.193906 # ok 254 getpid() SVE VL 16/SME VL 32 ZA
8449 12:29:35.194056 # ok 255 getpid() SVE VL 16/SME VL 16 SM+ZA
8450 12:29:35.198078 # ok 256 getpid() SVE VL 16/SME VL 16 SM
8451 12:29:35.198552 # ok 257 getpid() SVE VL 16/SME VL 16 ZA
8452 12:29:35.198751 # ok 258 sched_yield() FPSIMD
8453 12:29:35.198996 # ok 259 sched_yield() SVE VL 256
8454 12:29:35.199237 # ok 260 sched_yield() SVE VL 256/SME VL 256 SM+ZA
8455 12:29:35.199397 # ok 261 sched_yield() SVE VL 256/SME VL 256 SM
8456 12:29:35.199582 # ok 262 sched_yield() SVE VL 256/SME VL 256 ZA
8457 12:29:35.199746 # ok 263 sched_yield() SVE VL 256/SME VL 128 SM+ZA
8458 12:29:35.199886 # ok 264 sched_yield() SVE VL 256/SME VL 128 SM
8459 12:29:35.200015 # ok 265 sched_yield() SVE VL 256/SME VL 128 ZA
8460 12:29:35.200255 # ok 266 sched_yield() SVE VL 256/SME VL 64 SM+ZA
8461 12:29:35.200424 # ok 267 sched_yield() SVE VL 256/SME VL 64 SM
8462 12:29:35.200561 # ok 268 sched_yield() SVE VL 256/SME VL 64 ZA
8463 12:29:35.200687 # ok 269 sched_yield() SVE VL 256/SME VL 32 SM+ZA
8464 12:29:35.200808 # ok 270 sched_yield() SVE VL 256/SME VL 32 SM
8465 12:29:35.200932 # ok 271 sched_yield() SVE VL 256/SME VL 32 ZA
8466 12:29:35.201056 # ok 272 sched_yield() SVE VL 256/SME VL 16 SM+ZA
8467 12:29:35.201180 # ok 273 sched_yield() SVE VL 256/SME VL 16 SM
8468 12:29:35.201335 # ok 274 sched_yield() SVE VL 256/SME VL 16 ZA
8469 12:29:35.201467 # ok 275 sched_yield() SVE VL 240
8470 12:29:35.201592 # ok 276 sched_yield() SVE VL 240/SME VL 256 SM+ZA
8471 12:29:35.202161 # ok 277 sched_yield() SVE VL 240/SME VL 256 SM
8472 12:29:35.202341 # ok 278 sched_yield() SVE VL 240/SME VL 256 ZA
8473 12:29:35.202489 # ok 279 sched_yield() SVE VL 240/SME VL 128 SM+ZA
8474 12:29:35.202634 # ok 280 sched_yield() SVE VL 240/SME VL 128 SM
8475 12:29:35.202777 # ok 281 sched_yield() SVE VL 240/SME VL 128 ZA
8476 12:29:35.202930 # ok 282 sched_yield() SVE VL 240/SME VL 64 SM+ZA
8477 12:29:35.203087 # ok 283 sched_yield() SVE VL 240/SME VL 64 SM
8478 12:29:35.203234 # ok 284 sched_yield() SVE VL 240/SME VL 64 ZA
8479 12:29:35.203361 # ok 285 sched_yield() SVE VL 240/SME VL 32 SM+ZA
8480 12:29:35.203477 # ok 286 sched_yield() SVE VL 240/SME VL 32 SM
8481 12:29:35.203610 # ok 287 sched_yield() SVE VL 240/SME VL 32 ZA
8482 12:29:35.206063 # ok 288 sched_yield() SVE VL 240/SME VL 16 SM+ZA
8483 12:29:35.206488 # ok 289 sched_yield() SVE VL 240/SME VL 16 SM
8484 12:29:37.249184 # ok 290 sched_yield() SVE VL 240/SME VL 16 ZA
8485 12:29:37.249700 # ok 291 sched_yield() SVE VL 224
8486 12:29:37.249813 # ok 292 sched_yield() SVE VL 224/SME VL 256 SM+ZA
8487 12:29:37.249908 # ok 293 sched_yield() SVE VL 224/SME VL 256 SM
8488 12:29:37.249998 # ok 294 sched_yield() SVE VL 224/SME VL 256 ZA
8489 12:29:37.250999 # ok 295 sched_yield() SVE VL 224/SME VL 128 SM+ZA
8490 12:29:37.251319 # ok 296 sched_yield() SVE VL 224/SME VL 128 SM
8491 12:29:37.251507 # ok 297 sched_yield() SVE VL 224/SME VL 128 ZA
8492 12:29:37.251682 # ok 298 sched_yield() SVE VL 224/SME VL 64 SM+ZA
8493 12:29:37.251810 # ok 299 sched_yield() SVE VL 224/SME VL 64 SM
8494 12:29:37.251959 # ok 300 sched_yield() SVE VL 224/SME VL 64 ZA
8495 12:29:37.252080 # ok 301 sched_yield() SVE VL 224/SME VL 32 SM+ZA
8496 12:29:37.252220 # ok 302 sched_yield() SVE VL 224/SME VL 32 SM
8497 12:29:37.252344 # ok 303 sched_yield() SVE VL 224/SME VL 32 ZA
8498 12:29:37.252478 # ok 304 sched_yield() SVE VL 224/SME VL 16 SM+ZA
8499 12:29:37.252599 # ok 305 sched_yield() SVE VL 224/SME VL 16 SM
8500 12:29:37.252735 # ok 306 sched_yield() SVE VL 224/SME VL 16 ZA
8501 12:29:37.252855 # ok 307 sched_yield() SVE VL 208
8502 12:29:37.252991 # ok 308 sched_yield() SVE VL 208/SME VL 256 SM+ZA
8503 12:29:37.253131 # ok 309 sched_yield() SVE VL 208/SME VL 256 SM
8504 12:29:37.253250 # ok 310 sched_yield() SVE VL 208/SME VL 256 ZA
8505 12:29:37.253386 # ok 311 sched_yield() SVE VL 208/SME VL 128 SM+ZA
8506 12:29:37.253508 # ok 312 sched_yield() SVE VL 208/SME VL 128 SM
8507 12:29:37.253623 # ok 313 sched_yield() SVE VL 208/SME VL 128 ZA
8508 12:29:37.253868 # ok 314 sched_yield() SVE VL 208/SME VL 64 SM+ZA
8509 12:29:37.254069 # ok 315 sched_yield() SVE VL 208/SME VL 64 SM
8510 12:29:37.254259 # ok 316 sched_yield() SVE VL 208/SME VL 64 ZA
8511 12:29:37.258170 # ok 317 sched_yield() SVE VL 208/SME VL 32 SM+ZA
8512 12:29:37.258574 # ok 318 sched_yield() SVE VL 208/SME VL 32 SM
8513 12:29:37.258688 # ok 319 sched_yield() SVE VL 208/SME VL 32 ZA
8514 12:29:37.258795 # ok 320 sched_yield() SVE VL 208/SME VL 16 SM+ZA
8515 12:29:37.258903 # ok 321 sched_yield() SVE VL 208/SME VL 16 SM
8516 12:29:37.259228 # ok 322 sched_yield() SVE VL 208/SME VL 16 ZA
8517 12:29:37.259439 # ok 323 sched_yield() SVE VL 192
8518 12:29:37.259652 # ok 324 sched_yield() SVE VL 192/SME VL 256 SM+ZA
8519 12:29:37.259827 # ok 325 sched_yield() SVE VL 192/SME VL 256 SM
8520 12:29:37.260059 # ok 326 sched_yield() SVE VL 192/SME VL 256 ZA
8521 12:29:37.260298 # ok 327 sched_yield() SVE VL 192/SME VL 128 SM+ZA
8522 12:29:37.260472 # ok 328 sched_yield() SVE VL 192/SME VL 128 SM
8523 12:29:37.260603 # ok 329 sched_yield() SVE VL 192/SME VL 128 ZA
8524 12:29:37.260720 # ok 330 sched_yield() SVE VL 192/SME VL 64 SM+ZA
8525 12:29:37.260861 # ok 331 sched_yield() SVE VL 192/SME VL 64 SM
8526 12:29:37.261013 # ok 332 sched_yield() SVE VL 192/SME VL 64 ZA
8527 12:29:37.261189 # ok 333 sched_yield() SVE VL 192/SME VL 32 SM+ZA
8528 12:29:37.261379 # ok 334 sched_yield() SVE VL 192/SME VL 32 SM
8529 12:29:37.261544 # ok 335 sched_yield() SVE VL 192/SME VL 32 ZA
8530 12:29:37.261747 # ok 336 sched_yield() SVE VL 192/SME VL 16 SM+ZA
8531 12:29:37.261884 # ok 337 sched_yield() SVE VL 192/SME VL 16 SM
8532 12:29:37.262003 # ok 338 sched_yield() SVE VL 192/SME VL 16 ZA
8533 12:29:37.266689 # ok 339 sched_yield() SVE VL 176
8534 12:29:37.267147 # ok 340 sched_yield() SVE VL 176/SME VL 256 SM+ZA
8535 12:29:37.267252 # ok 341 sched_yield() SVE VL 176/SME VL 256 SM
8536 12:29:37.267367 # ok 342 sched_yield() SVE VL 176/SME VL 256 ZA
8537 12:29:37.267461 # ok 343 sched_yield() SVE VL 176/SME VL 128 SM+ZA
8538 12:29:37.267540 # ok 344 sched_yield() SVE VL 176/SME VL 128 SM
8539 12:29:37.267625 # ok 345 sched_yield() SVE VL 176/SME VL 128 ZA
8540 12:29:37.267711 # ok 346 sched_yield() SVE VL 176/SME VL 64 SM+ZA
8541 12:29:37.267979 # ok 347 sched_yield() SVE VL 176/SME VL 64 SM
8542 12:29:37.268168 # ok 348 sched_yield() SVE VL 176/SME VL 64 ZA
8543 12:29:37.268250 # ok 349 sched_yield() SVE VL 176/SME VL 32 SM+ZA
8544 12:29:37.268341 # ok 350 sched_yield() SVE VL 176/SME VL 32 SM
8545 12:29:37.268619 # ok 351 sched_yield() SVE VL 176/SME VL 32 ZA
8546 12:29:37.268712 # ok 352 sched_yield() SVE VL 176/SME VL 16 SM+ZA
8547 12:29:37.268799 # ok 353 sched_yield() SVE VL 176/SME VL 16 SM
8548 12:29:37.269067 # ok 354 sched_yield() SVE VL 176/SME VL 16 ZA
8549 12:29:37.269161 # ok 355 sched_yield() SVE VL 160
8550 12:29:37.269433 # ok 356 sched_yield() SVE VL 160/SME VL 256 SM+ZA
8551 12:29:37.269529 # ok 357 sched_yield() SVE VL 160/SME VL 256 SM
8552 12:29:37.269607 # ok 358 sched_yield() SVE VL 160/SME VL 256 ZA
8553 12:29:37.269710 # ok 359 sched_yield() SVE VL 160/SME VL 128 SM+ZA
8554 12:29:37.269794 # ok 360 sched_yield() SVE VL 160/SME VL 128 SM
8555 12:29:37.269882 # ok 361 sched_yield() SVE VL 160/SME VL 128 ZA
8556 12:29:37.274221 # ok 362 sched_yield() SVE VL 160/SME VL 64 SM+ZA
8557 12:29:37.274579 # ok 363 sched_yield() SVE VL 160/SME VL 64 SM
8558 12:29:37.274691 # ok 364 sched_yield() SVE VL 160/SME VL 64 ZA
8559 12:29:37.274781 # ok 365 sched_yield() SVE VL 160/SME VL 32 SM+ZA
8560 12:29:37.274890 # ok 366 sched_yield() SVE VL 160/SME VL 32 SM
8561 12:29:37.274984 # ok 367 sched_yield() SVE VL 160/SME VL 32 ZA
8562 12:29:37.275087 # ok 368 sched_yield() SVE VL 160/SME VL 16 SM+ZA
8563 12:29:37.275177 # ok 369 sched_yield() SVE VL 160/SME VL 16 SM
8564 12:29:37.275278 # ok 370 sched_yield() SVE VL 160/SME VL 16 ZA
8565 12:29:37.275368 # ok 371 sched_yield() SVE VL 144
8566 12:29:37.275468 # ok 372 sched_yield() SVE VL 144/SME VL 256 SM+ZA
8567 12:29:37.275569 # ok 373 sched_yield() SVE VL 144/SME VL 256 SM
8568 12:29:37.275670 # ok 374 sched_yield() SVE VL 144/SME VL 256 ZA
8569 12:29:37.276000 # ok 375 sched_yield() SVE VL 144/SME VL 128 SM+ZA
8570 12:29:37.276165 # ok 376 sched_yield() SVE VL 144/SME VL 128 SM
8571 12:29:39.455950 # ok 377 sched_yield() SVE VL 144/SME VL 128 ZA
8572 12:29:39.459642 # ok 378 sched_yield() SVE VL 144/SME VL 64 SM+ZA
8573 12:29:39.459754 # ok 379 sched_yield() SVE VL 144/SME VL 64 SM
8574 12:29:39.459838 # ok 380 sched_yield() SVE VL 144/SME VL 64 ZA
8575 12:29:39.459921 # ok 381 sched_yield() SVE VL 144/SME VL 32 SM+ZA
8576 12:29:39.460007 # ok 382 sched_yield() SVE VL 144/SME VL 32 SM
8577 12:29:39.460086 # ok 383 sched_yield() SVE VL 144/SME VL 32 ZA
8578 12:29:39.460163 # ok 384 sched_yield() SVE VL 144/SME VL 16 SM+ZA
8579 12:29:39.460241 # ok 385 sched_yield() SVE VL 144/SME VL 16 SM
8580 12:29:39.460319 # ok 386 sched_yield() SVE VL 144/SME VL 16 ZA
8581 12:29:39.460395 # ok 387 sched_yield() SVE VL 128
8582 12:29:39.460473 # ok 388 sched_yield() SVE VL 128/SME VL 256 SM+ZA
8583 12:29:39.460549 # ok 389 sched_yield() SVE VL 128/SME VL 256 SM
8584 12:29:39.460626 # ok 390 sched_yield() SVE VL 128/SME VL 256 ZA
8585 12:29:39.460702 # ok 391 sched_yield() SVE VL 128/SME VL 128 SM+ZA
8586 12:29:39.460778 # ok 392 sched_yield() SVE VL 128/SME VL 128 SM
8587 12:29:39.460854 # ok 393 sched_yield() SVE VL 128/SME VL 128 ZA
8588 12:29:39.460930 # ok 394 sched_yield() SVE VL 128/SME VL 64 SM+ZA
8589 12:29:39.461006 # ok 395 sched_yield() SVE VL 128/SME VL 64 SM
8590 12:29:39.461082 # ok 396 sched_yield() SVE VL 128/SME VL 64 ZA
8591 12:29:39.461158 # ok 397 sched_yield() SVE VL 128/SME VL 32 SM+ZA
8592 12:29:39.461235 # ok 398 sched_yield() SVE VL 128/SME VL 32 SM
8593 12:29:39.461311 # ok 399 sched_yield() SVE VL 128/SME VL 32 ZA
8594 12:29:39.466903 # ok 400 sched_yield() SVE VL 128/SME VL 16 SM+ZA
8595 12:29:39.467008 # ok 401 sched_yield() SVE VL 128/SME VL 16 SM
8596 12:29:39.467089 # ok 402 sched_yield() SVE VL 128/SME VL 16 ZA
8597 12:29:39.467395 # ok 403 sched_yield() SVE VL 112
8598 12:29:39.467494 # ok 404 sched_yield() SVE VL 112/SME VL 256 SM+ZA
8599 12:29:39.467574 # ok 405 sched_yield() SVE VL 112/SME VL 256 SM
8600 12:29:39.467651 # ok 406 sched_yield() SVE VL 112/SME VL 256 ZA
8601 12:29:39.467740 # ok 407 sched_yield() SVE VL 112/SME VL 128 SM+ZA
8602 12:29:39.467832 # ok 408 sched_yield() SVE VL 112/SME VL 128 SM
8603 12:29:39.467926 # ok 409 sched_yield() SVE VL 112/SME VL 128 ZA
8604 12:29:39.468022 # ok 410 sched_yield() SVE VL 112/SME VL 64 SM+ZA
8605 12:29:39.468117 # ok 411 sched_yield() SVE VL 112/SME VL 64 SM
8606 12:29:39.468211 # ok 412 sched_yield() SVE VL 112/SME VL 64 ZA
8607 12:29:39.468478 # ok 413 sched_yield() SVE VL 112/SME VL 32 SM+ZA
8608 12:29:39.468575 # ok 414 sched_yield() SVE VL 112/SME VL 32 SM
8609 12:29:39.468666 # ok 415 sched_yield() SVE VL 112/SME VL 32 ZA
8610 12:29:39.468756 # ok 416 sched_yield() SVE VL 112/SME VL 16 SM+ZA
8611 12:29:39.469020 # ok 417 sched_yield() SVE VL 112/SME VL 16 SM
8612 12:29:39.469102 # ok 418 sched_yield() SVE VL 112/SME VL 16 ZA
8613 12:29:39.469190 # ok 419 sched_yield() SVE VL 96
8614 12:29:39.469712 # ok 420 sched_yield() SVE VL 96/SME VL 256 SM+ZA
8615 12:29:39.476334 # ok 421 sched_yield() SVE VL 96/SME VL 256 SM
8616 12:29:39.476650 # ok 422 sched_yield() SVE VL 96/SME VL 256 ZA
8617 12:29:39.476865 # ok 423 sched_yield() SVE VL 96/SME VL 128 SM+ZA
8618 12:29:39.477061 # ok 424 sched_yield() SVE VL 96/SME VL 128 SM
8619 12:29:39.477240 # ok 425 sched_yield() SVE VL 96/SME VL 128 ZA
8620 12:29:39.477444 # ok 426 sched_yield() SVE VL 96/SME VL 64 SM+ZA
8621 12:29:39.477618 # ok 427 sched_yield() SVE VL 96/SME VL 64 SM
8622 12:29:39.477810 # ok 428 sched_yield() SVE VL 96/SME VL 64 ZA
8623 12:29:39.477977 # ok 429 sched_yield() SVE VL 96/SME VL 32 SM+ZA
8624 12:29:39.478100 # ok 430 sched_yield() SVE VL 96/SME VL 32 SM
8625 12:29:39.479621 # ok 431 sched_yield() SVE VL 96/SME VL 32 ZA
8626 12:29:39.480052 # ok 432 sched_yield() SVE VL 96/SME VL 16 SM+ZA
8627 12:29:39.480242 # ok 433 sched_yield() SVE VL 96/SME VL 16 SM
8628 12:29:39.480412 # ok 434 sched_yield() SVE VL 96/SME VL 16 ZA
8629 12:29:39.480604 # ok 435 sched_yield() SVE VL 80
8630 12:29:39.480763 # ok 436 sched_yield() SVE VL 80/SME VL 256 SM+ZA
8631 12:29:39.480936 # ok 437 sched_yield() SVE VL 80/SME VL 256 SM
8632 12:29:39.481104 # ok 438 sched_yield() SVE VL 80/SME VL 256 ZA
8633 12:29:39.481308 # ok 439 sched_yield() SVE VL 80/SME VL 128 SM+ZA
8634 12:29:39.481486 # ok 440 sched_yield() SVE VL 80/SME VL 128 SM
8635 12:29:39.481662 # ok 441 sched_yield() SVE VL 80/SME VL 128 ZA
8636 12:29:39.481807 # ok 442 sched_yield() SVE VL 80/SME VL 64 SM+ZA
8637 12:29:39.481924 # ok 443 sched_yield() SVE VL 80/SME VL 64 SM
8638 12:29:39.482064 # ok 444 sched_yield() SVE VL 80/SME VL 64 ZA
8639 12:29:39.482185 # ok 445 sched_yield() SVE VL 80/SME VL 32 SM+ZA
8640 12:29:39.482300 # ok 446 sched_yield() SVE VL 80/SME VL 32 SM
8641 12:29:39.482414 # ok 447 sched_yield() SVE VL 80/SME VL 32 ZA
8642 12:29:39.488537 # ok 448 sched_yield() SVE VL 80/SME VL 16 SM+ZA
8643 12:29:39.488829 # ok 449 sched_yield() SVE VL 80/SME VL 16 SM
8644 12:29:39.489033 # ok 450 sched_yield() SVE VL 80/SME VL 16 ZA
8645 12:29:39.489210 # ok 451 sched_yield() SVE VL 64
8646 12:29:39.489454 # ok 452 sched_yield() SVE VL 64/SME VL 256 SM+ZA
8647 12:29:39.489662 # ok 453 sched_yield() SVE VL 64/SME VL 256 SM
8648 12:29:39.489862 # ok 454 sched_yield() SVE VL 64/SME VL 256 ZA
8649 12:29:39.490048 # ok 455 sched_yield() SVE VL 64/SME VL 128 SM+ZA
8650 12:29:39.490240 # ok 456 sched_yield() SVE VL 64/SME VL 128 SM
8651 12:29:39.490368 # ok 457 sched_yield() SVE VL 64/SME VL 128 ZA
8652 12:29:39.490489 # ok 458 sched_yield() SVE VL 64/SME VL 64 SM+ZA
8653 12:29:39.490605 # ok 459 sched_yield() SVE VL 64/SME VL 64 SM
8654 12:29:39.491661 # ok 460 sched_yield() SVE VL 64/SME VL 64 ZA
8655 12:29:39.492142 # ok 461 sched_yield() SVE VL 64/SME VL 32 SM+ZA
8656 12:29:39.492338 # ok 462 sched_yield() SVE VL 64/SME VL 32 SM
8657 12:29:39.492514 # ok 463 sched_yield() SVE VL 64/SME VL 32 ZA
8658 12:29:40.240629 # ok 464 sched_yield() SVE VL 64/SME VL 16 SM+ZA
8659 12:29:40.240974 # ok 465 sched_yield() SVE VL 64/SME VL 16 SM
8660 12:29:40.241423 # ok 466 sched_yield() SVE VL 64/SME VL 16 ZA
8661 12:29:40.241622 # ok 467 sched_yield() SVE VL 48
8662 12:29:40.241806 # ok 468 sched_yield() SVE VL 48/SME VL 256 SM+ZA
8663 12:29:40.242000 # ok 469 sched_yield() SVE VL 48/SME VL 256 SM
8664 12:29:40.242212 # ok 470 sched_yield() SVE VL 48/SME VL 256 ZA
8665 12:29:40.242434 # ok 471 sched_yield() SVE VL 48/SME VL 128 SM+ZA
8666 12:29:40.242575 # ok 472 sched_yield() SVE VL 48/SME VL 128 SM
8667 12:29:40.242695 # ok 473 sched_yield() SVE VL 48/SME VL 128 ZA
8668 12:29:40.242813 # ok 474 sched_yield() SVE VL 48/SME VL 64 SM+ZA
8669 12:29:40.242931 # ok 475 sched_yield() SVE VL 48/SME VL 64 SM
8670 12:29:40.243047 # ok 476 sched_yield() SVE VL 48/SME VL 64 ZA
8671 12:29:40.243164 # ok 477 sched_yield() SVE VL 48/SME VL 32 SM+ZA
8672 12:29:40.243279 # ok 478 sched_yield() SVE VL 48/SME VL 32 SM
8673 12:29:40.243394 # ok 479 sched_yield() SVE VL 48/SME VL 32 ZA
8674 12:29:40.251744 # ok 480 sched_yield() SVE VL 48/SME VL 16 SM+ZA
8675 12:29:40.252257 # ok 481 sched_yield() SVE VL 48/SME VL 16 SM
8676 12:29:40.252457 # ok 482 sched_yield() SVE VL 48/SME VL 16 ZA
8677 12:29:40.252633 # ok 483 sched_yield() SVE VL 32
8678 12:29:40.253862 # ok 484 sched_yield() SVE VL 32/SME VL 256 SM+ZA
8679 12:29:40.254032 # ok 485 sched_yield() SVE VL 32/SME VL 256 SM
8680 12:29:40.254158 # ok 486 sched_yield() SVE VL 32/SME VL 256 ZA
8681 12:29:40.254276 # ok 487 sched_yield() SVE VL 32/SME VL 128 SM+ZA
8682 12:29:40.254394 # ok 488 sched_yield() SVE VL 32/SME VL 128 SM
8683 12:29:40.254511 # ok 489 sched_yield() SVE VL 32/SME VL 128 ZA
8684 12:29:40.254628 # ok 490 sched_yield() SVE VL 32/SME VL 64 SM+ZA
8685 12:29:40.254766 # ok 491 sched_yield() SVE VL 32/SME VL 64 SM
8686 12:29:40.254934 # ok 492 sched_yield() SVE VL 32/SME VL 64 ZA
8687 12:29:40.255102 # ok 493 sched_yield() SVE VL 32/SME VL 32 SM+ZA
8688 12:29:40.255270 # ok 494 sched_yield() SVE VL 32/SME VL 32 SM
8689 12:29:40.255435 # ok 495 sched_yield() SVE VL 32/SME VL 32 ZA
8690 12:29:40.255585 # ok 496 sched_yield() SVE VL 32/SME VL 16 SM+ZA
8691 12:29:40.255742 # ok 497 sched_yield() SVE VL 32/SME VL 16 SM
8692 12:29:40.255908 # ok 498 sched_yield() SVE VL 32/SME VL 16 ZA
8693 12:29:40.256071 # ok 499 sched_yield() SVE VL 16
8694 12:29:40.256225 # ok 500 sched_yield() SVE VL 16/SME VL 256 SM+ZA
8695 12:29:40.256373 # ok 501 sched_yield() SVE VL 16/SME VL 256 SM
8696 12:29:40.256492 # ok 502 sched_yield() SVE VL 16/SME VL 256 ZA
8697 12:29:40.257006 # ok 503 sched_yield() SVE VL 16/SME VL 128 SM+ZA
8698 12:29:40.257165 # ok 504 sched_yield() SVE VL 16/SME VL 128 SM
8699 12:29:40.257290 # ok 505 sched_yield() SVE VL 16/SME VL 128 ZA
8700 12:29:40.257407 # ok 506 sched_yield() SVE VL 16/SME VL 64 SM+ZA
8701 12:29:40.257525 # ok 507 sched_yield() SVE VL 16/SME VL 64 SM
8702 12:29:40.257642 # ok 508 sched_yield() SVE VL 16/SME VL 64 ZA
8703 12:29:40.257824 # ok 509 sched_yield() SVE VL 16/SME VL 32 SM+ZA
8704 12:29:40.257955 # ok 510 sched_yield() SVE VL 16/SME VL 32 SM
8705 12:29:40.258073 # ok 511 sched_yield() SVE VL 16/SME VL 32 ZA
8706 12:29:40.258188 # ok 512 sched_yield() SVE VL 16/SME VL 16 SM+ZA
8707 12:29:40.258302 # ok 513 sched_yield() SVE VL 16/SME VL 16 SM
8708 12:29:40.258416 # ok 514 sched_yield() SVE VL 16/SME VL 16 ZA
8709 12:29:40.258531 # # Totals: pass:514 fail:0 xfail:0 xpass:0 skip:0 error:0
8710 12:29:40.258648 ok 47 selftests: arm64: syscall-abi
8711 12:29:40.317765 # selftests: arm64: tpidr2
8712 12:29:40.478700 # TAP version 13
8713 12:29:40.478924 # 1..5
8714 12:29:40.479509 # # PID: 4123
8715 12:29:40.479649 # ok 1 default_value
8716 12:29:40.479831 # ok 2 write_read
8717 12:29:40.479962 # ok 3 write_sleep_read
8718 12:29:40.480059 # ok 4 write_fork_read
8719 12:29:40.480148 # ok 5 write_clone_read
8720 12:29:40.480236 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8721 12:29:40.490674 ok 48 selftests: arm64: tpidr2
8722 12:29:41.149717 arm64_tags_test pass
8723 12:29:41.149910 arm64_run_tags_test_sh pass
8724 12:29:41.149983 arm64_fake_sigreturn_bad_magic pass
8725 12:29:41.150046 arm64_fake_sigreturn_bad_size pass
8726 12:29:41.150136 arm64_fake_sigreturn_bad_size_for_magic0 pass
8727 12:29:41.150227 arm64_fake_sigreturn_duplicated_fpsimd pass
8728 12:29:41.150352 arm64_fake_sigreturn_misaligned_sp pass
8729 12:29:41.150459 arm64_fake_sigreturn_missing_fpsimd pass
8730 12:29:41.150576 arm64_fake_sigreturn_sme_change_vl pass
8731 12:29:41.150675 arm64_fake_sigreturn_sve_change_vl pass
8732 12:29:41.150762 arm64_mangle_pstate_invalid_compat_toggle pass
8733 12:29:41.150836 arm64_mangle_pstate_invalid_daif_bits pass
8734 12:29:41.150926 arm64_mangle_pstate_invalid_mode_el1h pass
8735 12:29:41.151022 arm64_mangle_pstate_invalid_mode_el1t pass
8736 12:29:41.151099 arm64_mangle_pstate_invalid_mode_el2h pass
8737 12:29:41.151164 arm64_mangle_pstate_invalid_mode_el2t pass
8738 12:29:41.151226 arm64_mangle_pstate_invalid_mode_el3h pass
8739 12:29:41.151965 arm64_mangle_pstate_invalid_mode_el3t pass
8740 12:29:41.152104 arm64_sme_trap_no_sm pass
8741 12:29:41.152210 arm64_sme_trap_non_streaming skip
8742 12:29:41.152305 arm64_sme_trap_za pass
8743 12:29:41.152436 arm64_sme_vl pass
8744 12:29:41.152548 arm64_ssve_regs pass
8745 12:29:41.152656 arm64_sve_regs pass
8746 12:29:41.152735 arm64_sve_vl pass
8747 12:29:41.152808 arm64_za_no_regs pass
8748 12:29:41.152881 arm64_za_regs pass
8749 12:29:41.152954 arm64_pac_global_corrupt_pac pass
8750 12:29:41.153028 arm64_pac_global_pac_instructions_not_nop pass
8751 12:29:41.153102 arm64_pac_global_pac_instructions_not_nop_generic pass
8752 12:29:41.153176 arm64_pac_global_single_thread_different_keys pass
8753 12:29:41.153250 arm64_pac_global_exec_changed_keys pass
8754 12:29:41.153323 arm64_pac_global_context_switch_keep_keys pass
8755 12:29:41.153397 arm64_pac_global_context_switch_keep_keys_generic pass
8756 12:29:41.153471 arm64_pac pass
8757 12:29:41.153544 arm64_fp-stress_FPSIMD-0-0 pass
8758 12:29:41.154153 arm64_fp-stress_SVE-VL-256-0 pass
8759 12:29:41.154728 arm64_fp-stress_SVE-VL-240-0 pass
8760 12:29:41.154841 arm64_fp-stress_SVE-VL-224-0 pass
8761 12:29:41.154931 arm64_fp-stress_SVE-VL-208-0 pass
8762 12:29:41.155014 arm64_fp-stress_SVE-VL-192-0 pass
8763 12:29:41.155094 arm64_fp-stress_SVE-VL-176-0 pass
8764 12:29:41.155175 arm64_fp-stress_SVE-VL-160-0 pass
8765 12:29:41.155536 arm64_fp-stress_SVE-VL-144-0 pass
8766 12:29:41.155649 arm64_fp-stress_SVE-VL-128-0 pass
8767 12:29:41.155728 arm64_fp-stress_SVE-VL-112-0 pass
8768 12:29:41.155820 arm64_fp-stress_SVE-VL-96-0 pass
8769 12:29:41.155928 arm64_fp-stress_SVE-VL-80-0 pass
8770 12:29:41.156015 arm64_fp-stress_SVE-VL-64-0 pass
8771 12:29:41.156108 arm64_fp-stress_SVE-VL-48-0 pass
8772 12:29:41.156207 arm64_fp-stress_SVE-VL-32-0 pass
8773 12:29:41.156299 arm64_fp-stress_SVE-VL-16-0 pass
8774 12:29:41.156588 arm64_fp-stress_SSVE-VL-256-0 pass
8775 12:29:41.156686 arm64_fp-stress_ZA-VL-256-0 pass
8776 12:29:41.156770 arm64_fp-stress_SSVE-VL-128-0 pass
8777 12:29:41.156849 arm64_fp-stress_ZA-VL-128-0 pass
8778 12:29:41.156931 arm64_fp-stress_SSVE-VL-64-0 pass
8779 12:29:41.157017 arm64_fp-stress_ZA-VL-64-0 pass
8780 12:29:41.157115 arm64_fp-stress_SSVE-VL-32-0 pass
8781 12:29:41.157209 arm64_fp-stress_ZA-VL-32-0 pass
8782 12:29:41.157290 arm64_fp-stress_SSVE-VL-16-0 pass
8783 12:29:41.157371 arm64_fp-stress_ZA-VL-16-0 pass
8784 12:29:41.157451 arm64_fp-stress pass
8785 12:29:41.157546 arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 pass
8786 12:29:41.157631 arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state pass
8787 12:29:41.157736 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set pass
8788 12:29:41.157835 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared pass
8789 12:29:41.157921 arm64_sve-ptrace_Set_SVE_VL_16 pass
8790 12:29:41.158016 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 pass
8791 12:29:41.158119 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 pass
8792 12:29:41.158223 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 pass
8793 12:29:41.158303 arm64_sve-ptrace_Set_SVE_VL_32 pass
8794 12:29:41.158406 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 pass
8795 12:29:41.158523 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 pass
8796 12:29:41.163182 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 pass
8797 12:29:41.164431 arm64_sve-ptrace_Set_SVE_VL_48 pass
8798 12:29:41.164638 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 pass
8799 12:29:41.164809 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 pass
8800 12:29:41.165128 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 pass
8801 12:29:41.165307 arm64_sve-ptrace_Set_SVE_VL_64 pass
8802 12:29:41.165470 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 pass
8803 12:29:41.165633 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 pass
8804 12:29:41.166233 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 pass
8805 12:29:41.166371 arm64_sve-ptrace_Set_SVE_VL_80 pass
8806 12:29:41.166556 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 pass
8807 12:29:41.166713 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 pass
8808 12:29:41.166860 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 pass
8809 12:29:41.166979 arm64_sve-ptrace_Set_SVE_VL_96 pass
8810 12:29:41.167095 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 pass
8811 12:29:41.167210 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 pass
8812 12:29:41.167325 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 pass
8813 12:29:41.167443 arm64_sve-ptrace_Set_SVE_VL_112 pass
8814 12:29:41.167559 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 pass
8815 12:29:41.167674 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 pass
8816 12:29:41.167794 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 pass
8817 12:29:41.167952 arm64_sve-ptrace_Set_SVE_VL_128 pass
8818 12:29:41.168110 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 pass
8819 12:29:41.168307 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 pass
8820 12:29:41.168480 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 pass
8821 12:29:41.168652 arm64_sve-ptrace_Set_SVE_VL_144 pass
8822 12:29:41.168823 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 pass
8823 12:29:41.168987 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 pass
8824 12:29:41.169150 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 pass
8825 12:29:41.171152 arm64_sve-ptrace_Set_SVE_VL_160 pass
8826 12:29:41.171366 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 pass
8827 12:29:41.172530 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 pass
8828 12:29:41.173104 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 pass
8829 12:29:41.173293 arm64_sve-ptrace_Set_SVE_VL_176 pass
8830 12:29:41.173457 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 pass
8831 12:29:41.173827 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 pass
8832 12:29:41.173957 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 pass
8833 12:29:41.174052 arm64_sve-ptrace_Set_SVE_VL_192 pass
8834 12:29:41.174140 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 pass
8835 12:29:41.174214 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 pass
8836 12:29:41.174278 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 pass
8837 12:29:41.174338 arm64_sve-ptrace_Set_SVE_VL_208 pass
8838 12:29:41.174399 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 pass
8839 12:29:41.174460 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 pass
8840 12:29:41.174521 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 pass
8841 12:29:41.174582 arm64_sve-ptrace_Set_SVE_VL_224 pass
8842 12:29:41.174645 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 pass
8843 12:29:41.174705 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 pass
8844 12:29:41.174765 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 pass
8845 12:29:41.174825 arm64_sve-ptrace_Set_SVE_VL_240 pass
8846 12:29:41.174901 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 pass
8847 12:29:41.174966 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 pass
8848 12:29:41.175027 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 pass
8849 12:29:41.175087 arm64_sve-ptrace_Set_SVE_VL_256 pass
8850 12:29:41.175148 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 pass
8851 12:29:41.178543 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 pass
8852 12:29:41.178702 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 pass
8853 12:29:41.178901 arm64_sve-ptrace_Set_SVE_VL_272 pass
8854 12:29:41.179287 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 skip
8855 12:29:41.179472 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
8856 12:29:41.180342 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
8857 12:29:41.180625 arm64_sve-ptrace_Set_SVE_VL_288 pass
8858 12:29:41.180816 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 skip
8859 12:29:41.181029 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
8860 12:29:41.181220 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
8861 12:29:41.181312 arm64_sve-ptrace_Set_SVE_VL_304 pass
8862 12:29:41.181419 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 skip
8863 12:29:41.181521 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
8864 12:29:41.181637 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
8865 12:29:41.181769 arm64_sve-ptrace_Set_SVE_VL_320 pass
8866 12:29:41.181872 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 skip
8867 12:29:41.181963 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
8868 12:29:41.182039 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
8869 12:29:41.182115 arm64_sve-ptrace_Set_SVE_VL_336 pass
8870 12:29:41.182190 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 skip
8871 12:29:41.182263 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
8872 12:29:41.182338 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
8873 12:29:41.182413 arm64_sve-ptrace_Set_SVE_VL_352 pass
8874 12:29:41.182509 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 skip
8875 12:29:41.182581 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
8876 12:29:41.182659 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
8877 12:29:41.182733 arm64_sve-ptrace_Set_SVE_VL_368 pass
8878 12:29:41.182807 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 skip
8879 12:29:41.182880 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
8880 12:29:41.182954 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
8881 12:29:41.183027 arm64_sve-ptrace_Set_SVE_VL_384 pass
8882 12:29:41.183101 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 skip
8883 12:29:41.186086 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
8884 12:29:41.187012 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
8885 12:29:41.187112 arm64_sve-ptrace_Set_SVE_VL_400 pass
8886 12:29:41.187201 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 skip
8887 12:29:41.187285 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
8888 12:29:41.187367 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
8889 12:29:41.187562 arm64_sve-ptrace_Set_SVE_VL_416 pass
8890 12:29:41.187669 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 skip
8891 12:29:41.187772 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
8892 12:29:41.187931 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
8893 12:29:41.188033 arm64_sve-ptrace_Set_SVE_VL_432 pass
8894 12:29:41.188110 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 skip
8895 12:29:41.188174 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
8896 12:29:41.188270 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
8897 12:29:41.188334 arm64_sve-ptrace_Set_SVE_VL_448 pass
8898 12:29:41.188393 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 skip
8899 12:29:41.188466 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
8900 12:29:41.209709 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
8901 12:29:41.209887 arm64_sve-ptrace_Set_SVE_VL_464 pass
8902 12:29:41.209989 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 skip
8903 12:29:41.210073 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
8904 12:29:41.210169 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
8905 12:29:41.210274 arm64_sve-ptrace_Set_SVE_VL_480 pass
8906 12:29:41.210378 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 skip
8907 12:29:41.210485 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
8908 12:29:41.210588 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
8909 12:29:41.217727 arm64_sve-ptrace_Set_SVE_VL_496 pass
8910 12:29:41.217877 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 skip
8911 12:29:41.217975 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
8912 12:29:41.218068 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
8913 12:29:41.218160 arm64_sve-ptrace_Set_SVE_VL_512 pass
8914 12:29:41.218252 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 skip
8915 12:29:41.218345 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
8916 12:29:41.218437 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
8917 12:29:41.218529 arm64_sve-ptrace_Set_SVE_VL_528 pass
8918 12:29:41.218621 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 skip
8919 12:29:41.218713 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
8920 12:29:41.218805 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
8921 12:29:41.218896 arm64_sve-ptrace_Set_SVE_VL_544 pass
8922 12:29:41.218986 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 skip
8923 12:29:41.219077 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
8924 12:29:41.219166 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
8925 12:29:41.219252 arm64_sve-ptrace_Set_SVE_VL_560 pass
8926 12:29:41.219344 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 skip
8927 12:29:41.219435 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
8928 12:29:41.219526 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
8929 12:29:41.219617 arm64_sve-ptrace_Set_SVE_VL_576 pass
8930 12:29:41.219710 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 skip
8931 12:29:41.219800 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
8932 12:29:41.219891 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
8933 12:29:41.219982 arm64_sve-ptrace_Set_SVE_VL_592 pass
8934 12:29:41.220072 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 skip
8935 12:29:41.220165 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
8936 12:29:41.220257 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
8937 12:29:41.220348 arm64_sve-ptrace_Set_SVE_VL_608 pass
8938 12:29:41.220440 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 skip
8939 12:29:41.220532 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
8940 12:29:41.220621 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
8941 12:29:41.220709 arm64_sve-ptrace_Set_SVE_VL_624 pass
8942 12:29:41.222301 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 skip
8943 12:29:41.222454 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
8944 12:29:41.222878 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
8945 12:29:41.223596 arm64_sve-ptrace_Set_SVE_VL_640 pass
8946 12:29:41.224001 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 skip
8947 12:29:41.224102 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
8948 12:29:41.224192 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
8949 12:29:41.224280 arm64_sve-ptrace_Set_SVE_VL_656 pass
8950 12:29:41.224367 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 skip
8951 12:29:41.224456 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
8952 12:29:41.224544 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
8953 12:29:41.224633 arm64_sve-ptrace_Set_SVE_VL_672 pass
8954 12:29:41.224746 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 skip
8955 12:29:41.224836 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
8956 12:29:41.224925 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
8957 12:29:41.225014 arm64_sve-ptrace_Set_SVE_VL_688 pass
8958 12:29:41.225101 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 skip
8959 12:29:41.225190 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
8960 12:29:41.225278 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
8961 12:29:41.225366 arm64_sve-ptrace_Set_SVE_VL_704 pass
8962 12:29:41.225850 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 skip
8963 12:29:41.225950 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
8964 12:29:41.226041 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
8965 12:29:41.226132 arm64_sve-ptrace_Set_SVE_VL_720 pass
8966 12:29:41.226223 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 skip
8967 12:29:41.226313 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
8968 12:29:41.226403 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
8969 12:29:41.226493 arm64_sve-ptrace_Set_SVE_VL_736 pass
8970 12:29:41.226583 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 skip
8971 12:29:41.226674 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
8972 12:29:41.226763 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
8973 12:29:41.226853 arm64_sve-ptrace_Set_SVE_VL_752 pass
8974 12:29:41.226943 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 skip
8975 12:29:41.227033 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
8976 12:29:41.230454 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
8977 12:29:41.230577 arm64_sve-ptrace_Set_SVE_VL_768 pass
8978 12:29:41.231378 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 skip
8979 12:29:41.231486 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
8980 12:29:41.231574 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
8981 12:29:41.231659 arm64_sve-ptrace_Set_SVE_VL_784 pass
8982 12:29:41.231753 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 skip
8983 12:29:41.231990 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
8984 12:29:41.232199 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
8985 12:29:41.232304 arm64_sve-ptrace_Set_SVE_VL_800 pass
8986 12:29:41.232397 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 skip
8987 12:29:41.232487 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
8988 12:29:41.232577 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
8989 12:29:41.232667 arm64_sve-ptrace_Set_SVE_VL_816 pass
8990 12:29:41.232763 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 skip
8991 12:29:41.232872 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
8992 12:29:41.232965 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
8993 12:29:41.233055 arm64_sve-ptrace_Set_SVE_VL_832 pass
8994 12:29:41.233145 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 skip
8995 12:29:41.233236 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
8996 12:29:41.233326 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
8997 12:29:41.233416 arm64_sve-ptrace_Set_SVE_VL_848 pass
8998 12:29:41.233523 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 skip
8999 12:29:41.233615 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
9000 12:29:41.233755 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
9001 12:29:41.233846 arm64_sve-ptrace_Set_SVE_VL_864 pass
9002 12:29:41.233935 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 skip
9003 12:29:41.234024 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
9004 12:29:41.234131 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
9005 12:29:41.234224 arm64_sve-ptrace_Set_SVE_VL_880 pass
9006 12:29:41.234314 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 skip
9007 12:29:41.238238 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
9008 12:29:41.239417 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
9009 12:29:41.239876 arm64_sve-ptrace_Set_SVE_VL_896 pass
9010 12:29:41.239994 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 skip
9011 12:29:41.240107 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
9012 12:29:41.240215 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
9013 12:29:41.240315 arm64_sve-ptrace_Set_SVE_VL_912 pass
9014 12:29:41.240626 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 skip
9015 12:29:41.240957 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
9016 12:29:41.241216 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
9017 12:29:41.241301 arm64_sve-ptrace_Set_SVE_VL_928 pass
9018 12:29:41.241369 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 skip
9019 12:29:41.241453 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
9020 12:29:41.241544 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
9021 12:29:41.241636 arm64_sve-ptrace_Set_SVE_VL_944 pass
9022 12:29:41.241748 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 skip
9023 12:29:41.241824 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
9024 12:29:41.241886 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
9025 12:29:41.241945 arm64_sve-ptrace_Set_SVE_VL_960 pass
9026 12:29:41.242005 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 skip
9027 12:29:41.242064 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
9028 12:29:41.242122 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
9029 12:29:41.242207 arm64_sve-ptrace_Set_SVE_VL_976 pass
9030 12:29:41.242275 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 skip
9031 12:29:41.242341 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
9032 12:29:41.242418 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
9033 12:29:41.242490 arm64_sve-ptrace_Set_SVE_VL_992 pass
9034 12:29:41.242549 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 skip
9035 12:29:41.242609 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
9036 12:29:41.242669 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
9037 12:29:41.242727 arm64_sve-ptrace_Set_SVE_VL_1008 pass
9038 12:29:41.246277 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 skip
9039 12:29:41.246421 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
9040 12:29:41.248068 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
9041 12:29:41.248175 arm64_sve-ptrace_Set_SVE_VL_1024 pass
9042 12:29:41.248258 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 skip
9043 12:29:41.248334 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
9044 12:29:41.248413 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
9045 12:29:41.248490 arm64_sve-ptrace_Set_SVE_VL_1040 pass
9046 12:29:41.248569 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 skip
9047 12:29:41.248648 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
9048 12:29:41.248714 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
9049 12:29:41.248779 arm64_sve-ptrace_Set_SVE_VL_1056 pass
9050 12:29:41.248839 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 skip
9051 12:29:41.248898 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
9052 12:29:41.248957 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
9053 12:29:41.249015 arm64_sve-ptrace_Set_SVE_VL_1072 pass
9054 12:29:41.249093 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 skip
9055 12:29:41.249173 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
9056 12:29:41.249238 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
9057 12:29:41.249297 arm64_sve-ptrace_Set_SVE_VL_1088 pass
9058 12:29:41.249356 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 skip
9059 12:29:41.249415 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
9060 12:29:41.249473 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
9061 12:29:41.249532 arm64_sve-ptrace_Set_SVE_VL_1104 pass
9062 12:29:41.263364 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 skip
9063 12:29:41.263872 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
9064 12:29:41.264081 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
9065 12:29:41.264286 arm64_sve-ptrace_Set_SVE_VL_1120 pass
9066 12:29:41.264473 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 skip
9067 12:29:41.264638 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
9068 12:29:41.264838 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
9069 12:29:41.265010 arm64_sve-ptrace_Set_SVE_VL_1136 pass
9070 12:29:41.265174 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 skip
9071 12:29:41.265357 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
9072 12:29:41.265574 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
9073 12:29:41.265801 arm64_sve-ptrace_Set_SVE_VL_1152 pass
9074 12:29:41.265971 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 skip
9075 12:29:41.266221 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
9076 12:29:41.266422 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
9077 12:29:41.266604 arm64_sve-ptrace_Set_SVE_VL_1168 pass
9078 12:29:41.266783 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 skip
9079 12:29:41.266981 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
9080 12:29:41.267172 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
9081 12:29:41.267363 arm64_sve-ptrace_Set_SVE_VL_1184 pass
9082 12:29:41.267551 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 skip
9083 12:29:41.267784 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
9084 12:29:41.267977 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
9085 12:29:41.268168 arm64_sve-ptrace_Set_SVE_VL_1200 pass
9086 12:29:41.268351 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 skip
9087 12:29:41.268534 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
9088 12:29:41.268713 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
9089 12:29:41.268908 arm64_sve-ptrace_Set_SVE_VL_1216 pass
9090 12:29:41.269105 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 skip
9091 12:29:41.269281 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
9092 12:29:41.269476 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
9093 12:29:41.271709 arm64_sve-ptrace_Set_SVE_VL_1232 pass
9094 12:29:41.271967 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 skip
9095 12:29:41.272117 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
9096 12:29:41.272264 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
9097 12:29:41.272481 arm64_sve-ptrace_Set_SVE_VL_1248 pass
9098 12:29:41.272742 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 skip
9099 12:29:41.272932 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
9100 12:29:41.273129 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
9101 12:29:41.273789 arm64_sve-ptrace_Set_SVE_VL_1264 pass
9102 12:29:41.273999 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 skip
9103 12:29:41.274184 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
9104 12:29:41.274413 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
9105 12:29:41.274626 arm64_sve-ptrace_Set_SVE_VL_1280 pass
9106 12:29:41.274856 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 skip
9107 12:29:41.275085 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
9108 12:29:41.275290 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
9109 12:29:41.275529 arm64_sve-ptrace_Set_SVE_VL_1296 pass
9110 12:29:41.275749 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 skip
9111 12:29:41.278018 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
9112 12:29:41.279094 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
9113 12:29:41.279240 arm64_sve-ptrace_Set_SVE_VL_1312 pass
9114 12:29:41.279389 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 skip
9115 12:29:41.279532 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
9116 12:29:41.279681 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
9117 12:29:41.279801 arm64_sve-ptrace_Set_SVE_VL_1328 pass
9118 12:29:41.279881 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 skip
9119 12:29:41.279962 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
9120 12:29:41.280068 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
9121 12:29:41.280149 arm64_sve-ptrace_Set_SVE_VL_1344 pass
9122 12:29:41.280296 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 skip
9123 12:29:41.280402 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
9124 12:29:41.280506 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
9125 12:29:41.280603 arm64_sve-ptrace_Set_SVE_VL_1360 pass
9126 12:29:41.280700 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 skip
9127 12:29:41.280808 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
9128 12:29:41.280939 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
9129 12:29:41.281055 arm64_sve-ptrace_Set_SVE_VL_1376 pass
9130 12:29:41.281155 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 skip
9131 12:29:41.281256 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
9132 12:29:41.281365 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
9133 12:29:41.281469 arm64_sve-ptrace_Set_SVE_VL_1392 pass
9134 12:29:41.281593 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 skip
9135 12:29:41.281706 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
9136 12:29:41.281829 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
9137 12:29:41.281953 arm64_sve-ptrace_Set_SVE_VL_1408 pass
9138 12:29:41.282064 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 skip
9139 12:29:41.286166 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
9140 12:29:41.286560 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
9141 12:29:41.286662 arm64_sve-ptrace_Set_SVE_VL_1424 pass
9142 12:29:41.286738 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 skip
9143 12:29:41.286815 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
9144 12:29:41.286897 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
9145 12:29:41.286968 arm64_sve-ptrace_Set_SVE_VL_1440 pass
9146 12:29:41.287061 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 skip
9147 12:29:41.287137 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
9148 12:29:41.287589 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
9149 12:29:41.287706 arm64_sve-ptrace_Set_SVE_VL_1456 pass
9150 12:29:41.287823 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 skip
9151 12:29:41.287945 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
9152 12:29:41.288047 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
9153 12:29:41.288300 arm64_sve-ptrace_Set_SVE_VL_1472 pass
9154 12:29:41.288401 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 skip
9155 12:29:41.288502 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
9156 12:29:41.288638 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
9157 12:29:41.288745 arm64_sve-ptrace_Set_SVE_VL_1488 pass
9158 12:29:41.288874 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 skip
9159 12:29:41.288980 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
9160 12:29:41.289102 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
9161 12:29:41.289639 arm64_sve-ptrace_Set_SVE_VL_1504 pass
9162 12:29:41.289767 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 skip
9163 12:29:41.290145 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
9164 12:29:41.290249 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
9165 12:29:41.290333 arm64_sve-ptrace_Set_SVE_VL_1520 pass
9166 12:29:41.290412 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 skip
9167 12:29:41.294118 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
9168 12:29:41.294466 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
9169 12:29:41.294563 arm64_sve-ptrace_Set_SVE_VL_1536 pass
9170 12:29:41.294670 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 skip
9171 12:29:41.294758 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
9172 12:29:41.294857 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
9173 12:29:41.295079 arm64_sve-ptrace_Set_SVE_VL_1552 pass
9174 12:29:41.295184 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 skip
9175 12:29:41.295273 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
9176 12:29:41.295374 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
9177 12:29:41.295653 arm64_sve-ptrace_Set_SVE_VL_1568 pass
9178 12:29:41.295745 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 skip
9179 12:29:41.295846 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
9180 12:29:41.295945 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
9181 12:29:41.296046 arm64_sve-ptrace_Set_SVE_VL_1584 pass
9182 12:29:41.296869 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 skip
9183 12:29:41.296983 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
9184 12:29:41.297072 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
9185 12:29:41.297158 arm64_sve-ptrace_Set_SVE_VL_1600 pass
9186 12:29:41.297478 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 skip
9187 12:29:41.297583 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
9188 12:29:41.297679 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
9189 12:29:41.297767 arm64_sve-ptrace_Set_SVE_VL_1616 pass
9190 12:29:41.298049 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 skip
9191 12:29:41.298150 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
9192 12:29:41.298232 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
9193 12:29:41.298312 arm64_sve-ptrace_Set_SVE_VL_1632 pass
9194 12:29:41.298389 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 skip
9195 12:29:41.302222 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
9196 12:29:41.302438 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
9197 12:29:41.302736 arm64_sve-ptrace_Set_SVE_VL_1648 pass
9198 12:29:41.302839 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 skip
9199 12:29:41.302945 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
9200 12:29:41.303031 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
9201 12:29:41.303129 arm64_sve-ptrace_Set_SVE_VL_1664 pass
9202 12:29:41.303263 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 skip
9203 12:29:41.303365 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
9204 12:29:41.303668 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
9205 12:29:41.303777 arm64_sve-ptrace_Set_SVE_VL_1680 pass
9206 12:29:41.303899 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 skip
9207 12:29:41.304010 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
9208 12:29:41.304114 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
9209 12:29:41.304209 arm64_sve-ptrace_Set_SVE_VL_1696 pass
9210 12:29:41.304308 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 skip
9211 12:29:41.304388 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
9212 12:29:41.304479 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
9213 12:29:41.304559 arm64_sve-ptrace_Set_SVE_VL_1712 pass
9214 12:29:41.304883 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 skip
9215 12:29:41.304992 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
9216 12:29:41.305079 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
9217 12:29:41.305393 arm64_sve-ptrace_Set_SVE_VL_1728 pass
9218 12:29:41.305487 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 skip
9219 12:29:41.305621 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
9220 12:29:41.305750 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
9221 12:29:41.305872 arm64_sve-ptrace_Set_SVE_VL_1744 pass
9222 12:29:41.326355 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 skip
9223 12:29:41.326888 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
9224 12:29:41.326995 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
9225 12:29:41.327095 arm64_sve-ptrace_Set_SVE_VL_1760 pass
9226 12:29:41.327190 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 skip
9227 12:29:41.327318 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
9228 12:29:41.327416 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
9229 12:29:41.327507 arm64_sve-ptrace_Set_SVE_VL_1776 pass
9230 12:29:41.327600 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 skip
9231 12:29:41.327706 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
9232 12:29:41.327798 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
9233 12:29:41.328461 arm64_sve-ptrace_Set_SVE_VL_1792 pass
9234 12:29:41.328575 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 skip
9235 12:29:41.328679 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
9236 12:29:41.328774 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
9237 12:29:41.328874 arm64_sve-ptrace_Set_SVE_VL_1808 pass
9238 12:29:41.329156 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 skip
9239 12:29:41.330103 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
9240 12:29:41.330213 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
9241 12:29:41.330318 arm64_sve-ptrace_Set_SVE_VL_1824 pass
9242 12:29:41.330416 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 skip
9243 12:29:41.330517 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
9244 12:29:41.330600 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
9245 12:29:41.330681 arm64_sve-ptrace_Set_SVE_VL_1840 pass
9246 12:29:41.330792 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 skip
9247 12:29:41.330902 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
9248 12:29:41.331007 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
9249 12:29:41.331110 arm64_sve-ptrace_Set_SVE_VL_1856 pass
9250 12:29:41.331213 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 skip
9251 12:29:41.331318 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
9252 12:29:41.334438 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
9253 12:29:41.334665 arm64_sve-ptrace_Set_SVE_VL_1872 pass
9254 12:29:41.334788 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 skip
9255 12:29:41.335071 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
9256 12:29:41.335184 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
9257 12:29:41.335386 arm64_sve-ptrace_Set_SVE_VL_1888 pass
9258 12:29:41.335488 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 skip
9259 12:29:41.335587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
9260 12:29:41.335686 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
9261 12:29:41.335776 arm64_sve-ptrace_Set_SVE_VL_1904 pass
9262 12:29:41.335866 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 skip
9263 12:29:41.335934 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
9264 12:29:41.336001 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
9265 12:29:41.336065 arm64_sve-ptrace_Set_SVE_VL_1920 pass
9266 12:29:41.336142 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 skip
9267 12:29:41.336226 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
9268 12:29:41.336305 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
9269 12:29:41.336379 arm64_sve-ptrace_Set_SVE_VL_1936 pass
9270 12:29:41.337842 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 skip
9271 12:29:41.337942 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
9272 12:29:41.338032 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
9273 12:29:41.338307 arm64_sve-ptrace_Set_SVE_VL_1952 pass
9274 12:29:41.338391 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 skip
9275 12:29:41.338455 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
9276 12:29:41.338517 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
9277 12:29:41.338577 arm64_sve-ptrace_Set_SVE_VL_1968 pass
9278 12:29:41.338636 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 skip
9279 12:29:41.338695 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
9280 12:29:41.338754 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
9281 12:29:41.338813 arm64_sve-ptrace_Set_SVE_VL_1984 pass
9282 12:29:41.338878 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 skip
9283 12:29:41.342182 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
9284 12:29:41.342297 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
9285 12:29:41.342558 arm64_sve-ptrace_Set_SVE_VL_2000 pass
9286 12:29:41.342652 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 skip
9287 12:29:41.342765 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
9288 12:29:41.342869 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
9289 12:29:41.342963 arm64_sve-ptrace_Set_SVE_VL_2016 pass
9290 12:29:41.343073 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 skip
9291 12:29:41.343149 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
9292 12:29:41.343241 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
9293 12:29:41.343511 arm64_sve-ptrace_Set_SVE_VL_2032 pass
9294 12:29:41.343619 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 skip
9295 12:29:41.343734 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
9296 12:29:41.343842 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
9297 12:29:41.343930 arm64_sve-ptrace_Set_SVE_VL_2048 pass
9298 12:29:41.344015 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 skip
9299 12:29:41.344147 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
9300 12:29:41.344275 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
9301 12:29:41.344389 arm64_sve-ptrace_Set_SVE_VL_2064 pass
9302 12:29:41.344501 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 skip
9303 12:29:41.344611 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
9304 12:29:41.344694 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
9305 12:29:41.344760 arm64_sve-ptrace_Set_SVE_VL_2080 pass
9306 12:29:41.345265 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 skip
9307 12:29:41.345368 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
9308 12:29:41.345440 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
9309 12:29:41.345527 arm64_sve-ptrace_Set_SVE_VL_2096 pass
9310 12:29:41.345614 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 skip
9311 12:29:41.345926 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
9312 12:29:41.346015 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
9313 12:29:41.346120 arm64_sve-ptrace_Set_SVE_VL_2112 pass
9314 12:29:41.346226 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 skip
9315 12:29:41.346327 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
9316 12:29:41.350299 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
9317 12:29:41.350457 arm64_sve-ptrace_Set_SVE_VL_2128 pass
9318 12:29:41.350713 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 skip
9319 12:29:41.350806 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
9320 12:29:41.350900 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
9321 12:29:41.350975 arm64_sve-ptrace_Set_SVE_VL_2144 pass
9322 12:29:41.351084 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 skip
9323 12:29:41.351175 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
9324 12:29:41.351263 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
9325 12:29:41.351356 arm64_sve-ptrace_Set_SVE_VL_2160 pass
9326 12:29:41.351443 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 skip
9327 12:29:41.357799 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
9328 12:29:41.358051 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
9329 12:29:41.358155 arm64_sve-ptrace_Set_SVE_VL_2176 pass
9330 12:29:41.358242 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 skip
9331 12:29:41.358334 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
9332 12:29:41.358417 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
9333 12:29:41.358481 arm64_sve-ptrace_Set_SVE_VL_2192 pass
9334 12:29:41.358559 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 skip
9335 12:29:41.358669 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
9336 12:29:41.358776 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
9337 12:29:41.358894 arm64_sve-ptrace_Set_SVE_VL_2208 pass
9338 12:29:41.359009 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 skip
9339 12:29:41.359126 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
9340 12:29:41.359235 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
9341 12:29:41.359346 arm64_sve-ptrace_Set_SVE_VL_2224 pass
9342 12:29:41.359455 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 skip
9343 12:29:41.359554 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
9344 12:29:41.359663 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
9345 12:29:41.359777 arm64_sve-ptrace_Set_SVE_VL_2240 pass
9346 12:29:41.359898 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 skip
9347 12:29:41.360019 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
9348 12:29:41.360118 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
9349 12:29:41.360447 arm64_sve-ptrace_Set_SVE_VL_2256 pass
9350 12:29:41.360541 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 skip
9351 12:29:41.360616 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
9352 12:29:41.360691 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
9353 12:29:41.360762 arm64_sve-ptrace_Set_SVE_VL_2272 pass
9354 12:29:41.360832 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 skip
9355 12:29:41.360905 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
9356 12:29:41.360975 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
9357 12:29:41.361045 arm64_sve-ptrace_Set_SVE_VL_2288 pass
9358 12:29:41.361117 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 skip
9359 12:29:41.361190 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
9360 12:29:41.361264 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
9361 12:29:41.361337 arm64_sve-ptrace_Set_SVE_VL_2304 pass
9362 12:29:41.361414 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 skip
9363 12:29:41.361492 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
9364 12:29:41.361564 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
9365 12:29:41.361636 arm64_sve-ptrace_Set_SVE_VL_2320 pass
9366 12:29:41.361719 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 skip
9367 12:29:41.362068 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
9368 12:29:41.362162 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
9369 12:29:41.362236 arm64_sve-ptrace_Set_SVE_VL_2336 pass
9370 12:29:41.362310 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 skip
9371 12:29:41.362386 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
9372 12:29:41.362456 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
9373 12:29:41.362528 arm64_sve-ptrace_Set_SVE_VL_2352 pass
9374 12:29:41.362597 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 skip
9375 12:29:41.362666 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
9376 12:29:41.362737 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
9377 12:29:41.366264 arm64_sve-ptrace_Set_SVE_VL_2368 pass
9378 12:29:41.366495 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 skip
9379 12:29:41.366782 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
9380 12:29:41.366873 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
9381 12:29:41.366957 arm64_sve-ptrace_Set_SVE_VL_2384 pass
9382 12:29:41.396712 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 skip
9383 12:29:41.397032 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
9384 12:29:41.397351 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
9385 12:29:41.397447 arm64_sve-ptrace_Set_SVE_VL_2400 pass
9386 12:29:41.397536 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 skip
9387 12:29:41.397623 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
9388 12:29:41.397738 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
9389 12:29:41.397829 arm64_sve-ptrace_Set_SVE_VL_2416 pass
9390 12:29:41.397916 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 skip
9391 12:29:41.398546 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
9392 12:29:41.398722 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
9393 12:29:41.398899 arm64_sve-ptrace_Set_SVE_VL_2432 pass
9394 12:29:41.399461 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 skip
9395 12:29:41.399554 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
9396 12:29:41.399632 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
9397 12:29:41.399705 arm64_sve-ptrace_Set_SVE_VL_2448 pass
9398 12:29:41.399777 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 skip
9399 12:29:41.399849 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
9400 12:29:41.399920 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
9401 12:29:41.399990 arm64_sve-ptrace_Set_SVE_VL_2464 pass
9402 12:29:41.400076 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 skip
9403 12:29:41.400150 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
9404 12:29:41.400403 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
9405 12:29:41.400506 arm64_sve-ptrace_Set_SVE_VL_2480 pass
9406 12:29:41.400590 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 skip
9407 12:29:41.400662 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
9408 12:29:41.400747 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
9409 12:29:41.400818 arm64_sve-ptrace_Set_SVE_VL_2496 pass
9410 12:29:41.401343 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 skip
9411 12:29:41.401449 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
9412 12:29:41.401689 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
9413 12:29:41.401782 arm64_sve-ptrace_Set_SVE_VL_2512 pass
9414 12:29:41.401885 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 skip
9415 12:29:41.401971 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
9416 12:29:41.406138 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
9417 12:29:41.406530 arm64_sve-ptrace_Set_SVE_VL_2528 pass
9418 12:29:41.406617 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 skip
9419 12:29:41.406704 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
9420 12:29:41.406966 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
9421 12:29:41.407055 arm64_sve-ptrace_Set_SVE_VL_2544 pass
9422 12:29:41.407135 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 skip
9423 12:29:41.407395 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
9424 12:29:41.407505 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
9425 12:29:41.407589 arm64_sve-ptrace_Set_SVE_VL_2560 pass
9426 12:29:41.407682 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 skip
9427 12:29:41.407955 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
9428 12:29:41.408065 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
9429 12:29:41.408347 arm64_sve-ptrace_Set_SVE_VL_2576 pass
9430 12:29:41.408954 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 skip
9431 12:29:41.409138 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
9432 12:29:41.409254 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
9433 12:29:41.409373 arm64_sve-ptrace_Set_SVE_VL_2592 pass
9434 12:29:41.409484 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 skip
9435 12:29:41.409623 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
9436 12:29:41.410036 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
9437 12:29:41.410154 arm64_sve-ptrace_Set_SVE_VL_2608 pass
9438 12:29:41.410275 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 skip
9439 12:29:41.410614 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
9440 12:29:41.414314 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
9441 12:29:41.414574 arm64_sve-ptrace_Set_SVE_VL_2624 pass
9442 12:29:41.414888 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 skip
9443 12:29:41.414984 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
9444 12:29:41.415066 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
9445 12:29:41.415142 arm64_sve-ptrace_Set_SVE_VL_2640 pass
9446 12:29:41.415228 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 skip
9447 12:29:41.415301 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
9448 12:29:41.415573 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
9449 12:29:41.415667 arm64_sve-ptrace_Set_SVE_VL_2656 pass
9450 12:29:41.415755 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 skip
9451 12:29:41.415830 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
9452 12:29:41.415913 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
9453 12:29:41.415986 arm64_sve-ptrace_Set_SVE_VL_2672 pass
9454 12:29:41.416074 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 skip
9455 12:29:41.416385 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
9456 12:29:41.416654 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
9457 12:29:41.416901 arm64_sve-ptrace_Set_SVE_VL_2688 pass
9458 12:29:41.416981 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 skip
9459 12:29:41.417450 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
9460 12:29:41.417894 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
9461 12:29:41.418062 arm64_sve-ptrace_Set_SVE_VL_2704 pass
9462 12:29:41.418151 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 skip
9463 12:29:41.418228 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
9464 12:29:41.418302 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
9465 12:29:41.422120 arm64_sve-ptrace_Set_SVE_VL_2720 pass
9466 12:29:41.422824 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 skip
9467 12:29:41.423151 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
9468 12:29:41.423267 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
9469 12:29:41.423350 arm64_sve-ptrace_Set_SVE_VL_2736 pass
9470 12:29:41.423424 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 skip
9471 12:29:41.423514 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
9472 12:29:41.423590 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
9473 12:29:41.423667 arm64_sve-ptrace_Set_SVE_VL_2752 pass
9474 12:29:41.423745 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 skip
9475 12:29:41.423833 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
9476 12:29:41.423908 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
9477 12:29:41.423979 arm64_sve-ptrace_Set_SVE_VL_2768 pass
9478 12:29:41.424053 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 skip
9479 12:29:41.424142 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
9480 12:29:41.424229 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
9481 12:29:41.424315 arm64_sve-ptrace_Set_SVE_VL_2784 pass
9482 12:29:41.424402 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 skip
9483 12:29:41.424478 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
9484 12:29:41.424552 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
9485 12:29:41.424640 arm64_sve-ptrace_Set_SVE_VL_2800 pass
9486 12:29:41.424715 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 skip
9487 12:29:41.424803 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
9488 12:29:41.424890 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
9489 12:29:41.424965 arm64_sve-ptrace_Set_SVE_VL_2816 pass
9490 12:29:41.425049 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 skip
9491 12:29:41.425342 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
9492 12:29:41.425454 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
9493 12:29:41.425560 arm64_sve-ptrace_Set_SVE_VL_2832 pass
9494 12:29:41.425674 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 skip
9495 12:29:41.425776 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
9496 12:29:41.430057 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
9497 12:29:41.430435 arm64_sve-ptrace_Set_SVE_VL_2848 pass
9498 12:29:41.430529 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 skip
9499 12:29:41.430617 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
9500 12:29:41.430720 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
9501 12:29:41.430811 arm64_sve-ptrace_Set_SVE_VL_2864 pass
9502 12:29:41.430922 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 skip
9503 12:29:41.431010 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
9504 12:29:41.431115 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
9505 12:29:41.431217 arm64_sve-ptrace_Set_SVE_VL_2880 pass
9506 12:29:41.431520 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 skip
9507 12:29:41.431627 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
9508 12:29:41.431734 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
9509 12:29:41.431823 arm64_sve-ptrace_Set_SVE_VL_2896 pass
9510 12:29:41.431923 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 skip
9511 12:29:41.432248 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
9512 12:29:41.432387 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
9513 12:29:41.432491 arm64_sve-ptrace_Set_SVE_VL_2912 pass
9514 12:29:41.432804 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 skip
9515 12:29:41.432910 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
9516 12:29:41.432995 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
9517 12:29:41.433075 arm64_sve-ptrace_Set_SVE_VL_2928 pass
9518 12:29:41.433166 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 skip
9519 12:29:41.433246 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
9520 12:29:41.433337 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
9521 12:29:41.433430 arm64_sve-ptrace_Set_SVE_VL_2944 pass
9522 12:29:41.433681 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 skip
9523 12:29:41.433772 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
9524 12:29:41.438241 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
9525 12:29:41.439141 arm64_sve-ptrace_Set_SVE_VL_2960 pass
9526 12:29:41.439407 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 skip
9527 12:29:41.439575 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
9528 12:29:41.440147 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
9529 12:29:41.440236 arm64_sve-ptrace_Set_SVE_VL_2976 pass
9530 12:29:41.440313 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 skip
9531 12:29:41.440388 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
9532 12:29:41.440467 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
9533 12:29:41.440549 arm64_sve-ptrace_Set_SVE_VL_2992 pass
9534 12:29:41.440626 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 skip
9535 12:29:41.440702 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
9536 12:29:41.440823 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
9537 12:29:41.440912 arm64_sve-ptrace_Set_SVE_VL_3008 pass
9538 12:29:41.440986 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 skip
9539 12:29:41.441077 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
9540 12:29:41.441150 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
9541 12:29:41.441219 arm64_sve-ptrace_Set_SVE_VL_3024 pass
9542 12:29:41.463239 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 skip
9543 12:29:41.463737 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
9544 12:29:41.463861 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
9545 12:29:41.463944 arm64_sve-ptrace_Set_SVE_VL_3040 pass
9546 12:29:41.464067 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 skip
9547 12:29:41.464195 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
9548 12:29:41.464297 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
9549 12:29:41.464394 arm64_sve-ptrace_Set_SVE_VL_3056 pass
9550 12:29:41.464508 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 skip
9551 12:29:41.464584 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
9552 12:29:41.464684 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
9553 12:29:41.464749 arm64_sve-ptrace_Set_SVE_VL_3072 pass
9554 12:29:41.464822 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 skip
9555 12:29:41.465121 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
9556 12:29:41.465217 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
9557 12:29:41.465339 arm64_sve-ptrace_Set_SVE_VL_3088 pass
9558 12:29:41.465446 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 skip
9559 12:29:41.465561 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
9560 12:29:41.465691 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
9561 12:29:41.465790 arm64_sve-ptrace_Set_SVE_VL_3104 pass
9562 12:29:41.470066 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 skip
9563 12:29:41.470429 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
9564 12:29:41.470566 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
9565 12:29:41.470676 arm64_sve-ptrace_Set_SVE_VL_3120 pass
9566 12:29:41.470814 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 skip
9567 12:29:41.470936 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
9568 12:29:41.471300 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
9569 12:29:41.471397 arm64_sve-ptrace_Set_SVE_VL_3136 pass
9570 12:29:41.471477 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 skip
9571 12:29:41.471742 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
9572 12:29:41.471837 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
9573 12:29:41.471913 arm64_sve-ptrace_Set_SVE_VL_3152 pass
9574 12:29:41.472176 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 skip
9575 12:29:41.472264 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
9576 12:29:41.472341 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
9577 12:29:41.472416 arm64_sve-ptrace_Set_SVE_VL_3168 pass
9578 12:29:41.472494 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 skip
9579 12:29:41.472578 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
9580 12:29:41.472680 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
9581 12:29:41.472766 arm64_sve-ptrace_Set_SVE_VL_3184 pass
9582 12:29:41.472847 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 skip
9583 12:29:41.472924 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
9584 12:29:41.473008 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
9585 12:29:41.473109 arm64_sve-ptrace_Set_SVE_VL_3200 pass
9586 12:29:41.473200 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 skip
9587 12:29:41.473299 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
9588 12:29:41.473385 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
9589 12:29:41.473484 arm64_sve-ptrace_Set_SVE_VL_3216 pass
9590 12:29:41.473766 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 skip
9591 12:29:41.473857 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
9592 12:29:41.478253 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
9593 12:29:41.478477 arm64_sve-ptrace_Set_SVE_VL_3232 pass
9594 12:29:41.478779 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 skip
9595 12:29:41.478870 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
9596 12:29:41.478963 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
9597 12:29:41.479037 arm64_sve-ptrace_Set_SVE_VL_3248 pass
9598 12:29:41.479109 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 skip
9599 12:29:41.479180 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
9600 12:29:41.479265 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
9601 12:29:41.479337 arm64_sve-ptrace_Set_SVE_VL_3264 pass
9602 12:29:41.479408 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 skip
9603 12:29:41.479490 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
9604 12:29:41.479574 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
9605 12:29:41.479646 arm64_sve-ptrace_Set_SVE_VL_3280 pass
9606 12:29:41.479729 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 skip
9607 12:29:41.480001 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
9608 12:29:41.480402 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
9609 12:29:41.480491 arm64_sve-ptrace_Set_SVE_VL_3296 pass
9610 12:29:41.480564 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 skip
9611 12:29:41.480831 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
9612 12:29:41.480908 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
9613 12:29:41.480990 arm64_sve-ptrace_Set_SVE_VL_3312 pass
9614 12:29:41.481255 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 skip
9615 12:29:41.481350 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
9616 12:29:41.481438 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
9617 12:29:41.481553 arm64_sve-ptrace_Set_SVE_VL_3328 pass
9618 12:29:41.481683 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 skip
9619 12:29:41.481772 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
9620 12:29:41.486191 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
9621 12:29:41.486692 arm64_sve-ptrace_Set_SVE_VL_3344 pass
9622 12:29:41.486795 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 skip
9623 12:29:41.486887 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
9624 12:29:41.486990 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
9625 12:29:41.487094 arm64_sve-ptrace_Set_SVE_VL_3360 pass
9626 12:29:41.487183 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 skip
9627 12:29:41.487289 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
9628 12:29:41.487586 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
9629 12:29:41.487689 arm64_sve-ptrace_Set_SVE_VL_3376 pass
9630 12:29:41.487797 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 skip
9631 12:29:41.487891 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
9632 12:29:41.487992 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
9633 12:29:41.488096 arm64_sve-ptrace_Set_SVE_VL_3392 pass
9634 12:29:41.489920 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 skip
9635 12:29:41.490021 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
9636 12:29:41.490085 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
9637 12:29:41.490146 arm64_sve-ptrace_Set_SVE_VL_3408 pass
9638 12:29:41.490211 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 skip
9639 12:29:41.490271 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
9640 12:29:41.490332 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
9641 12:29:41.490399 arm64_sve-ptrace_Set_SVE_VL_3424 pass
9642 12:29:41.490459 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 skip
9643 12:29:41.490518 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
9644 12:29:41.490578 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
9645 12:29:41.490638 arm64_sve-ptrace_Set_SVE_VL_3440 pass
9646 12:29:41.494451 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 skip
9647 12:29:41.494658 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
9648 12:29:41.494776 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
9649 12:29:41.494868 arm64_sve-ptrace_Set_SVE_VL_3456 pass
9650 12:29:41.494974 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 skip
9651 12:29:41.495247 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
9652 12:29:41.496411 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
9653 12:29:41.496505 arm64_sve-ptrace_Set_SVE_VL_3472 pass
9654 12:29:41.496572 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 skip
9655 12:29:41.496634 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
9656 12:29:41.496698 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
9657 12:29:41.497800 arm64_sve-ptrace_Set_SVE_VL_3488 pass
9658 12:29:41.497918 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 skip
9659 12:29:41.498015 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
9660 12:29:41.498098 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
9661 12:29:41.498168 arm64_sve-ptrace_Set_SVE_VL_3504 pass
9662 12:29:41.498266 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 skip
9663 12:29:41.498377 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
9664 12:29:41.498497 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
9665 12:29:41.498605 arm64_sve-ptrace_Set_SVE_VL_3520 pass
9666 12:29:41.498713 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 skip
9667 12:29:41.498818 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
9668 12:29:41.502135 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
9669 12:29:41.502468 arm64_sve-ptrace_Set_SVE_VL_3536 pass
9670 12:29:41.502538 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 skip
9671 12:29:41.502615 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
9672 12:29:41.502870 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
9673 12:29:41.502941 arm64_sve-ptrace_Set_SVE_VL_3552 pass
9674 12:29:41.503034 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 skip
9675 12:29:41.503337 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
9676 12:29:41.503444 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
9677 12:29:41.503550 arm64_sve-ptrace_Set_SVE_VL_3568 pass
9678 12:29:41.503653 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 skip
9679 12:29:41.503932 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
9680 12:29:41.504031 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
9681 12:29:41.504136 arm64_sve-ptrace_Set_SVE_VL_3584 pass
9682 12:29:41.504937 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 skip
9683 12:29:41.505054 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
9684 12:29:41.505153 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
9685 12:29:41.505258 arm64_sve-ptrace_Set_SVE_VL_3600 pass
9686 12:29:41.505349 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 skip
9687 12:29:41.505822 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
9688 12:29:41.505956 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
9689 12:29:41.506051 arm64_sve-ptrace_Set_SVE_VL_3616 pass
9690 12:29:41.506136 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 skip
9691 12:29:41.506221 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
9692 12:29:41.506306 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
9693 12:29:41.510179 arm64_sve-ptrace_Set_SVE_VL_3632 pass
9694 12:29:41.510574 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 skip
9695 12:29:41.510667 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
9696 12:29:41.510771 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
9697 12:29:41.510860 arm64_sve-ptrace_Set_SVE_VL_3648 pass
9698 12:29:41.510953 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 skip
9699 12:29:41.511216 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
9700 12:29:41.511295 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
9701 12:29:41.511379 arm64_sve-ptrace_Set_SVE_VL_3664 pass
9702 12:29:41.538233 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 skip
9703 12:29:41.538717 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
9704 12:29:41.538867 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
9705 12:29:41.538969 arm64_sve-ptrace_Set_SVE_VL_3680 pass
9706 12:29:41.539070 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 skip
9707 12:29:41.539171 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
9708 12:29:41.539240 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
9709 12:29:41.539309 arm64_sve-ptrace_Set_SVE_VL_3696 pass
9710 12:29:41.539383 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 skip
9711 12:29:41.539653 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
9712 12:29:41.540078 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
9713 12:29:41.540205 arm64_sve-ptrace_Set_SVE_VL_3712 pass
9714 12:29:41.540352 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 skip
9715 12:29:41.540446 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
9716 12:29:41.540759 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
9717 12:29:41.540974 arm64_sve-ptrace_Set_SVE_VL_3728 pass
9718 12:29:41.541069 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 skip
9719 12:29:41.541155 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
9720 12:29:41.541257 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
9721 12:29:41.541344 arm64_sve-ptrace_Set_SVE_VL_3744 pass
9722 12:29:41.541428 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 skip
9723 12:29:41.541529 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
9724 12:29:41.541615 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
9725 12:29:41.541709 arm64_sve-ptrace_Set_SVE_VL_3760 pass
9726 12:29:41.541808 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 skip
9727 12:29:41.541910 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
9728 12:29:41.546642 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
9729 12:29:41.546843 arm64_sve-ptrace_Set_SVE_VL_3776 pass
9730 12:29:41.546920 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 skip
9731 12:29:41.546993 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
9732 12:29:41.547272 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
9733 12:29:41.547360 arm64_sve-ptrace_Set_SVE_VL_3792 pass
9734 12:29:41.547441 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 skip
9735 12:29:41.547521 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
9736 12:29:41.547595 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
9737 12:29:41.547674 arm64_sve-ptrace_Set_SVE_VL_3808 pass
9738 12:29:41.547749 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 skip
9739 12:29:41.548337 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
9740 12:29:41.548440 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
9741 12:29:41.548518 arm64_sve-ptrace_Set_SVE_VL_3824 pass
9742 12:29:41.548593 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 skip
9743 12:29:41.548666 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
9744 12:29:41.548739 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
9745 12:29:41.548819 arm64_sve-ptrace_Set_SVE_VL_3840 pass
9746 12:29:41.548902 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 skip
9747 12:29:41.548988 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
9748 12:29:41.549073 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
9749 12:29:41.549357 arm64_sve-ptrace_Set_SVE_VL_3856 pass
9750 12:29:41.549451 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 skip
9751 12:29:41.549540 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
9752 12:29:41.549625 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
9753 12:29:41.549719 arm64_sve-ptrace_Set_SVE_VL_3872 pass
9754 12:29:41.549803 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 skip
9755 12:29:41.549886 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
9756 12:29:41.549969 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
9757 12:29:41.550053 arm64_sve-ptrace_Set_SVE_VL_3888 pass
9758 12:29:41.550136 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 skip
9759 12:29:41.550220 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
9760 12:29:41.550321 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
9761 12:29:41.550413 arm64_sve-ptrace_Set_SVE_VL_3904 pass
9762 12:29:41.550498 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 skip
9763 12:29:41.550582 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
9764 12:29:41.553997 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
9765 12:29:41.554324 arm64_sve-ptrace_Set_SVE_VL_3920 pass
9766 12:29:41.554416 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 skip
9767 12:29:41.554482 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
9768 12:29:41.554556 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
9769 12:29:41.554620 arm64_sve-ptrace_Set_SVE_VL_3936 pass
9770 12:29:41.554722 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 skip
9771 12:29:41.555329 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
9772 12:29:41.555586 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
9773 12:29:41.555810 arm64_sve-ptrace_Set_SVE_VL_3952 pass
9774 12:29:41.555907 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 skip
9775 12:29:41.556200 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
9776 12:29:41.556329 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
9777 12:29:41.556435 arm64_sve-ptrace_Set_SVE_VL_3968 pass
9778 12:29:41.556540 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 skip
9779 12:29:41.556639 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
9780 12:29:41.556731 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
9781 12:29:41.556824 arm64_sve-ptrace_Set_SVE_VL_3984 pass
9782 12:29:41.556952 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 skip
9783 12:29:41.557037 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
9784 12:29:41.557122 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
9785 12:29:41.557191 arm64_sve-ptrace_Set_SVE_VL_4000 pass
9786 12:29:41.557251 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 skip
9787 12:29:41.557311 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
9788 12:29:41.557390 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
9789 12:29:41.557658 arm64_sve-ptrace_Set_SVE_VL_4016 pass
9790 12:29:41.557757 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 skip
9791 12:29:41.557847 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
9792 12:29:41.557936 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
9793 12:29:41.558236 arm64_sve-ptrace_Set_SVE_VL_4032 pass
9794 12:29:41.562200 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 skip
9795 12:29:41.562577 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
9796 12:29:41.562663 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
9797 12:29:41.562733 arm64_sve-ptrace_Set_SVE_VL_4048 pass
9798 12:29:41.562798 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 skip
9799 12:29:41.562889 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
9800 12:29:41.562977 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
9801 12:29:41.563051 arm64_sve-ptrace_Set_SVE_VL_4064 pass
9802 12:29:41.563131 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 skip
9803 12:29:41.563211 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
9804 12:29:41.563288 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
9805 12:29:41.563359 arm64_sve-ptrace_Set_SVE_VL_4080 pass
9806 12:29:41.563625 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 skip
9807 12:29:41.563706 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
9808 12:29:41.563773 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
9809 12:29:41.563851 arm64_sve-ptrace_Set_SVE_VL_4096 pass
9810 12:29:41.563917 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 skip
9811 12:29:41.563991 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
9812 12:29:41.564237 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
9813 12:29:41.564326 arm64_sve-ptrace_Set_SVE_VL_4112 pass
9814 12:29:41.564444 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 skip
9815 12:29:41.564697 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
9816 12:29:41.564796 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
9817 12:29:41.564877 arm64_sve-ptrace_Set_SVE_VL_4128 pass
9818 12:29:41.564970 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 skip
9819 12:29:41.565294 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
9820 12:29:41.565387 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
9821 12:29:41.565469 arm64_sve-ptrace_Set_SVE_VL_4144 pass
9822 12:29:41.565741 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 skip
9823 12:29:41.565836 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
9824 12:29:41.565926 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
9825 12:29:41.570005 arm64_sve-ptrace_Set_SVE_VL_4160 pass
9826 12:29:41.570359 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 skip
9827 12:29:41.570461 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
9828 12:29:41.570550 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
9829 12:29:41.570653 arm64_sve-ptrace_Set_SVE_VL_4176 pass
9830 12:29:41.570742 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 skip
9831 12:29:41.570846 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
9832 12:29:41.570936 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
9833 12:29:41.571014 arm64_sve-ptrace_Set_SVE_VL_4192 pass
9834 12:29:41.571103 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 skip
9835 12:29:41.571191 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
9836 12:29:41.571268 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
9837 12:29:41.571357 arm64_sve-ptrace_Set_SVE_VL_4208 pass
9838 12:29:41.571446 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 skip
9839 12:29:41.571536 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
9840 12:29:41.571812 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
9841 12:29:41.571896 arm64_sve-ptrace_Set_SVE_VL_4224 pass
9842 12:29:41.571973 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 skip
9843 12:29:41.572061 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
9844 12:29:41.572325 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
9845 12:29:41.572417 arm64_sve-ptrace_Set_SVE_VL_4240 pass
9846 12:29:41.572497 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 skip
9847 12:29:41.572594 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
9848 12:29:41.572693 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
9849 12:29:41.572778 arm64_sve-ptrace_Set_SVE_VL_4256 pass
9850 12:29:41.572877 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 skip
9851 12:29:41.572960 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
9852 12:29:41.573050 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
9853 12:29:41.573144 arm64_sve-ptrace_Set_SVE_VL_4272 pass
9854 12:29:41.573229 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 skip
9855 12:29:41.573527 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
9856 12:29:41.573634 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
9857 12:29:41.573922 arm64_sve-ptrace_Set_SVE_VL_4288 pass
9858 12:29:41.574014 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 skip
9859 12:29:41.578043 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
9860 12:29:41.578409 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
9861 12:29:41.578511 arm64_sve-ptrace_Set_SVE_VL_4304 pass
9862 12:29:41.600445 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 skip
9863 12:29:41.600868 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
9864 12:29:41.600970 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
9865 12:29:41.601054 arm64_sve-ptrace_Set_SVE_VL_4320 pass
9866 12:29:41.601157 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 skip
9867 12:29:41.601248 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
9868 12:29:41.601359 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
9869 12:29:41.601448 arm64_sve-ptrace_Set_SVE_VL_4336 pass
9870 12:29:41.601557 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 skip
9871 12:29:41.601640 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
9872 12:29:41.601755 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
9873 12:29:41.601841 arm64_sve-ptrace_Set_SVE_VL_4352 pass
9874 12:29:41.602133 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 skip
9875 12:29:41.602218 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
9876 12:29:41.602302 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
9877 12:29:41.602372 arm64_sve-ptrace_Set_SVE_VL_4368 pass
9878 12:29:41.602447 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 skip
9879 12:29:41.602524 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
9880 12:29:41.602777 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
9881 12:29:41.602851 arm64_sve-ptrace_Set_SVE_VL_4384 pass
9882 12:29:41.602971 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 skip
9883 12:29:41.603062 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
9884 12:29:41.603170 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
9885 12:29:41.603562 arm64_sve-ptrace_Set_SVE_VL_4400 pass
9886 12:29:41.603658 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 skip
9887 12:29:41.603764 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
9888 12:29:41.603850 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
9889 12:29:41.604124 arm64_sve-ptrace_Set_SVE_VL_4416 pass
9890 12:29:41.604210 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 skip
9891 12:29:41.604300 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
9892 12:29:41.604376 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
9893 12:29:41.604472 arm64_sve-ptrace_Set_SVE_VL_4432 pass
9894 12:29:41.604544 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 skip
9895 12:29:41.604933 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
9896 12:29:41.605006 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
9897 12:29:41.605083 arm64_sve-ptrace_Set_SVE_VL_4448 pass
9898 12:29:41.605158 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 skip
9899 12:29:41.605234 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
9900 12:29:41.605309 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
9901 12:29:41.605383 arm64_sve-ptrace_Set_SVE_VL_4464 pass
9902 12:29:41.605663 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 skip
9903 12:29:41.605750 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
9904 12:29:41.605840 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
9905 12:29:41.605914 arm64_sve-ptrace_Set_SVE_VL_4480 pass
9906 12:29:41.605989 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 skip
9907 12:29:41.606062 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
9908 12:29:41.606136 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
9909 12:29:41.606209 arm64_sve-ptrace_Set_SVE_VL_4496 pass
9910 12:29:41.606283 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 skip
9911 12:29:41.606374 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
9912 12:29:41.610090 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
9913 12:29:41.610508 arm64_sve-ptrace_Set_SVE_VL_4512 pass
9914 12:29:41.610611 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 skip
9915 12:29:41.610712 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
9916 12:29:41.610847 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
9917 12:29:41.610942 arm64_sve-ptrace_Set_SVE_VL_4528 pass
9918 12:29:41.611031 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 skip
9919 12:29:41.611129 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
9920 12:29:41.611533 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
9921 12:29:41.611651 arm64_sve-ptrace_Set_SVE_VL_4544 pass
9922 12:29:41.611757 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 skip
9923 12:29:41.611879 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
9924 12:29:41.612052 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
9925 12:29:41.612136 arm64_sve-ptrace_Set_SVE_VL_4560 pass
9926 12:29:41.612446 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 skip
9927 12:29:41.612554 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
9928 12:29:41.612815 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
9929 12:29:41.612937 arm64_sve-ptrace_Set_SVE_VL_4576 pass
9930 12:29:41.613046 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 skip
9931 12:29:41.613135 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
9932 12:29:41.613234 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
9933 12:29:41.613319 arm64_sve-ptrace_Set_SVE_VL_4592 pass
9934 12:29:41.613683 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 skip
9935 12:29:41.613806 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
9936 12:29:41.618262 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
9937 12:29:41.618436 arm64_sve-ptrace_Set_SVE_VL_4608 pass
9938 12:29:41.618766 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 skip
9939 12:29:41.618922 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
9940 12:29:41.619017 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
9941 12:29:41.619881 arm64_sve-ptrace_Set_SVE_VL_4624 pass
9942 12:29:41.620102 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 skip
9943 12:29:41.620456 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
9944 12:29:41.620628 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
9945 12:29:41.621191 arm64_sve-ptrace_Set_SVE_VL_4640 pass
9946 12:29:41.621295 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 skip
9947 12:29:41.621511 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
9948 12:29:41.621603 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
9949 12:29:41.621701 arm64_sve-ptrace_Set_SVE_VL_4656 pass
9950 12:29:41.621803 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 skip
9951 12:29:41.621889 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
9952 12:29:41.621971 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
9953 12:29:41.622212 arm64_sve-ptrace_Set_SVE_VL_4672 pass
9954 12:29:41.622313 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 skip
9955 12:29:41.622401 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
9956 12:29:41.622488 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
9957 12:29:41.622573 arm64_sve-ptrace_Set_SVE_VL_4688 pass
9958 12:29:41.622657 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 skip
9959 12:29:41.622744 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
9960 12:29:41.626370 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
9961 12:29:41.626524 arm64_sve-ptrace_Set_SVE_VL_4704 pass
9962 12:29:41.626629 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 skip
9963 12:29:41.626728 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
9964 12:29:41.626823 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
9965 12:29:41.627066 arm64_sve-ptrace_Set_SVE_VL_4720 pass
9966 12:29:41.627180 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 skip
9967 12:29:41.627482 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
9968 12:29:41.627620 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
9969 12:29:41.627714 arm64_sve-ptrace_Set_SVE_VL_4736 pass
9970 12:29:41.628096 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 skip
9971 12:29:41.628170 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
9972 12:29:41.628234 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
9973 12:29:41.628302 arm64_sve-ptrace_Set_SVE_VL_4752 pass
9974 12:29:41.628613 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 skip
9975 12:29:41.628720 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
9976 12:29:41.629825 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
9977 12:29:41.629935 arm64_sve-ptrace_Set_SVE_VL_4768 pass
9978 12:29:41.630025 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 skip
9979 12:29:41.630113 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
9980 12:29:41.630198 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
9981 12:29:41.630284 arm64_sve-ptrace_Set_SVE_VL_4784 pass
9982 12:29:41.630369 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 skip
9983 12:29:41.630458 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
9984 12:29:41.630544 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
9985 12:29:41.630629 arm64_sve-ptrace_Set_SVE_VL_4800 pass
9986 12:29:41.630715 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 skip
9987 12:29:41.630801 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
9988 12:29:41.633990 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
9989 12:29:41.634291 arm64_sve-ptrace_Set_SVE_VL_4816 pass
9990 12:29:41.634372 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 skip
9991 12:29:41.634467 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
9992 12:29:41.634741 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
9993 12:29:41.634852 arm64_sve-ptrace_Set_SVE_VL_4832 pass
9994 12:29:41.634941 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 skip
9995 12:29:41.635044 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
9996 12:29:41.635133 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
9997 12:29:41.635220 arm64_sve-ptrace_Set_SVE_VL_4848 pass
9998 12:29:41.635321 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 skip
9999 12:29:41.635411 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
10000 12:29:41.635517 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
10001 12:29:41.635605 arm64_sve-ptrace_Set_SVE_VL_4864 pass
10002 12:29:41.635704 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 skip
10003 12:29:41.635994 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
10004 12:29:41.636282 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
10005 12:29:41.636384 arm64_sve-ptrace_Set_SVE_VL_4880 pass
10006 12:29:41.636470 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 skip
10007 12:29:41.636567 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
10008 12:29:41.636651 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
10009 12:29:41.636749 arm64_sve-ptrace_Set_SVE_VL_4896 pass
10010 12:29:41.637158 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 skip
10011 12:29:41.637247 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
10012 12:29:41.637330 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
10013 12:29:41.637608 arm64_sve-ptrace_Set_SVE_VL_4912 pass
10014 12:29:41.637717 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 skip
10015 12:29:41.637837 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
10016 12:29:41.637946 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
10017 12:29:41.642051 arm64_sve-ptrace_Set_SVE_VL_4928 pass
10018 12:29:41.642415 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 skip
10019 12:29:41.642525 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
10020 12:29:41.642630 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
10021 12:29:41.642716 arm64_sve-ptrace_Set_SVE_VL_4944 pass
10022 12:29:41.663701 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 skip
10023 12:29:41.664141 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
10024 12:29:41.664252 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
10025 12:29:41.664355 arm64_sve-ptrace_Set_SVE_VL_4960 pass
10026 12:29:41.664461 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 skip
10027 12:29:41.664563 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
10028 12:29:41.664662 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
10029 12:29:41.664751 arm64_sve-ptrace_Set_SVE_VL_4976 pass
10030 12:29:41.664828 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 skip
10031 12:29:41.664928 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
10032 12:29:41.665002 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
10033 12:29:41.665091 arm64_sve-ptrace_Set_SVE_VL_4992 pass
10034 12:29:41.665202 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 skip
10035 12:29:41.665284 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
10036 12:29:41.665374 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
10037 12:29:41.665485 arm64_sve-ptrace_Set_SVE_VL_5008 pass
10038 12:29:41.665622 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 skip
10039 12:29:41.665745 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
10040 12:29:41.666060 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
10041 12:29:41.666176 arm64_sve-ptrace_Set_SVE_VL_5024 pass
10042 12:29:41.666472 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 skip
10043 12:29:41.666600 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
10044 12:29:41.666704 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
10045 12:29:41.666801 arm64_sve-ptrace_Set_SVE_VL_5040 pass
10046 12:29:41.667083 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 skip
10047 12:29:41.667202 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
10048 12:29:41.667296 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
10049 12:29:41.667534 arm64_sve-ptrace_Set_SVE_VL_5056 pass
10050 12:29:41.667635 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 skip
10051 12:29:41.668023 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
10052 12:29:41.668120 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
10053 12:29:41.668201 arm64_sve-ptrace_Set_SVE_VL_5072 pass
10054 12:29:41.668282 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 skip
10055 12:29:41.668373 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
10056 12:29:41.668456 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
10057 12:29:41.668549 arm64_sve-ptrace_Set_SVE_VL_5088 pass
10058 12:29:41.668634 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 skip
10059 12:29:41.668728 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
10060 12:29:41.669020 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
10061 12:29:41.669123 arm64_sve-ptrace_Set_SVE_VL_5104 pass
10062 12:29:41.669220 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 skip
10063 12:29:41.669308 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
10064 12:29:41.669603 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
10065 12:29:41.669717 arm64_sve-ptrace_Set_SVE_VL_5120 pass
10066 12:29:41.669821 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 skip
10067 12:29:41.674529 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
10068 12:29:41.674718 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
10069 12:29:41.674810 arm64_sve-ptrace_Set_SVE_VL_5136 pass
10070 12:29:41.676332 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 skip
10071 12:29:41.676445 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
10072 12:29:41.676744 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
10073 12:29:41.676861 arm64_sve-ptrace_Set_SVE_VL_5152 pass
10074 12:29:41.676955 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 skip
10075 12:29:41.677043 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
10076 12:29:41.677129 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
10077 12:29:41.677214 arm64_sve-ptrace_Set_SVE_VL_5168 pass
10078 12:29:41.677299 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 skip
10079 12:29:41.677385 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
10080 12:29:41.677471 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
10081 12:29:41.677558 arm64_sve-ptrace_Set_SVE_VL_5184 pass
10082 12:29:41.677657 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 skip
10083 12:29:41.677743 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
10084 12:29:41.677826 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
10085 12:29:41.677910 arm64_sve-ptrace_Set_SVE_VL_5200 pass
10086 12:29:41.678015 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 skip
10087 12:29:41.678102 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
10088 12:29:41.678187 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
10089 12:29:41.678272 arm64_sve-ptrace_Set_SVE_VL_5216 pass
10090 12:29:41.678357 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 skip
10091 12:29:41.678442 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
10092 12:29:41.678526 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
10093 12:29:41.678610 arm64_sve-ptrace_Set_SVE_VL_5232 pass
10094 12:29:41.683138 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 skip
10095 12:29:41.683317 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
10096 12:29:41.683423 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
10097 12:29:41.683539 arm64_sve-ptrace_Set_SVE_VL_5248 pass
10098 12:29:41.683656 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 skip
10099 12:29:41.683774 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
10100 12:29:41.683886 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
10101 12:29:41.684398 arm64_sve-ptrace_Set_SVE_VL_5264 pass
10102 12:29:41.684513 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 skip
10103 12:29:41.684652 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
10104 12:29:41.684757 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
10105 12:29:41.684857 arm64_sve-ptrace_Set_SVE_VL_5280 pass
10106 12:29:41.684963 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 skip
10107 12:29:41.685067 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
10108 12:29:41.685160 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
10109 12:29:41.685226 arm64_sve-ptrace_Set_SVE_VL_5296 pass
10110 12:29:41.685303 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 skip
10111 12:29:41.685368 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
10112 12:29:41.685430 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
10113 12:29:41.685492 arm64_sve-ptrace_Set_SVE_VL_5312 pass
10114 12:29:41.685554 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 skip
10115 12:29:41.685615 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
10116 12:29:41.685688 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
10117 12:29:41.685749 arm64_sve-ptrace_Set_SVE_VL_5328 pass
10118 12:29:41.685822 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 skip
10119 12:29:41.685885 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
10120 12:29:41.685947 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
10121 12:29:41.686007 arm64_sve-ptrace_Set_SVE_VL_5344 pass
10122 12:29:41.690271 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 skip
10123 12:29:41.690745 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
10124 12:29:41.690966 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
10125 12:29:41.691075 arm64_sve-ptrace_Set_SVE_VL_5360 pass
10126 12:29:41.691182 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 skip
10127 12:29:41.692414 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
10128 12:29:41.692526 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
10129 12:29:41.692640 arm64_sve-ptrace_Set_SVE_VL_5376 pass
10130 12:29:41.692743 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 skip
10131 12:29:41.692822 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
10132 12:29:41.692887 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
10133 12:29:41.692952 arm64_sve-ptrace_Set_SVE_VL_5392 pass
10134 12:29:41.693017 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 skip
10135 12:29:41.693080 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
10136 12:29:41.693159 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
10137 12:29:41.693226 arm64_sve-ptrace_Set_SVE_VL_5408 pass
10138 12:29:41.693290 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 skip
10139 12:29:41.693352 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
10140 12:29:41.693428 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
10141 12:29:41.693493 arm64_sve-ptrace_Set_SVE_VL_5424 pass
10142 12:29:41.693554 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 skip
10143 12:29:41.693633 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
10144 12:29:41.693927 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
10145 12:29:41.698224 arm64_sve-ptrace_Set_SVE_VL_5440 pass
10146 12:29:41.699574 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 skip
10147 12:29:41.699815 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
10148 12:29:41.700125 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
10149 12:29:41.700237 arm64_sve-ptrace_Set_SVE_VL_5456 pass
10150 12:29:41.700327 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 skip
10151 12:29:41.700399 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
10152 12:29:41.700487 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
10153 12:29:41.700684 arm64_sve-ptrace_Set_SVE_VL_5472 pass
10154 12:29:41.700762 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 skip
10155 12:29:41.700833 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
10156 12:29:41.700904 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
10157 12:29:41.700974 arm64_sve-ptrace_Set_SVE_VL_5488 pass
10158 12:29:41.701043 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 skip
10159 12:29:41.701130 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
10160 12:29:41.701205 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
10161 12:29:41.701275 arm64_sve-ptrace_Set_SVE_VL_5504 pass
10162 12:29:41.701348 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 skip
10163 12:29:41.701420 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
10164 12:29:41.701510 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
10165 12:29:41.701581 arm64_sve-ptrace_Set_SVE_VL_5520 pass
10166 12:29:41.701680 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 skip
10167 12:29:41.701766 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
10168 12:29:41.706327 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
10169 12:29:41.706890 arm64_sve-ptrace_Set_SVE_VL_5536 pass
10170 12:29:41.707074 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 skip
10171 12:29:41.707175 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
10172 12:29:41.707263 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
10173 12:29:41.707348 arm64_sve-ptrace_Set_SVE_VL_5552 pass
10174 12:29:41.707451 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 skip
10175 12:29:41.707540 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
10176 12:29:41.707643 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
10177 12:29:41.707733 arm64_sve-ptrace_Set_SVE_VL_5568 pass
10178 12:29:41.707836 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 skip
10179 12:29:41.707922 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
10180 12:29:41.708023 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
10181 12:29:41.708132 arm64_sve-ptrace_Set_SVE_VL_5584 pass
10182 12:29:41.729237 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 skip
10183 12:29:41.730227 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
10184 12:29:41.730713 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
10185 12:29:41.730855 arm64_sve-ptrace_Set_SVE_VL_5600 pass
10186 12:29:41.731072 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 skip
10187 12:29:41.732636 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
10188 12:29:41.732956 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
10189 12:29:41.733262 arm64_sve-ptrace_Set_SVE_VL_5616 pass
10190 12:29:41.733483 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 skip
10191 12:29:41.733586 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
10192 12:29:41.733767 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
10193 12:29:41.733860 arm64_sve-ptrace_Set_SVE_VL_5632 pass
10194 12:29:41.733945 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 skip
10195 12:29:41.734027 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
10196 12:29:41.734113 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
10197 12:29:41.734192 arm64_sve-ptrace_Set_SVE_VL_5648 pass
10198 12:29:41.734271 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 skip
10199 12:29:41.734348 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
10200 12:29:41.734429 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
10201 12:29:41.734513 arm64_sve-ptrace_Set_SVE_VL_5664 pass
10202 12:29:41.734594 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 skip
10203 12:29:41.734882 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
10204 12:29:41.734966 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
10205 12:29:41.735031 arm64_sve-ptrace_Set_SVE_VL_5680 pass
10206 12:29:41.735094 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 skip
10207 12:29:41.735155 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
10208 12:29:41.735216 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
10209 12:29:41.738545 arm64_sve-ptrace_Set_SVE_VL_5696 pass
10210 12:29:41.738681 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 skip
10211 12:29:41.738794 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
10212 12:29:41.739111 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
10213 12:29:41.739463 arm64_sve-ptrace_Set_SVE_VL_5712 pass
10214 12:29:41.739573 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 skip
10215 12:29:41.740058 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
10216 12:29:41.740236 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
10217 12:29:41.740340 arm64_sve-ptrace_Set_SVE_VL_5728 pass
10218 12:29:41.740437 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 skip
10219 12:29:41.740535 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
10220 12:29:41.740654 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
10221 12:29:41.740752 arm64_sve-ptrace_Set_SVE_VL_5744 pass
10222 12:29:41.740851 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 skip
10223 12:29:41.740941 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
10224 12:29:41.741044 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
10225 12:29:41.741149 arm64_sve-ptrace_Set_SVE_VL_5760 pass
10226 12:29:41.741238 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 skip
10227 12:29:41.741321 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
10228 12:29:41.741418 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
10229 12:29:41.741507 arm64_sve-ptrace_Set_SVE_VL_5776 pass
10230 12:29:41.741603 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 skip
10231 12:29:41.741767 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
10232 12:29:41.746114 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
10233 12:29:41.746910 arm64_sve-ptrace_Set_SVE_VL_5792 pass
10234 12:29:41.747058 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 skip
10235 12:29:41.747259 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
10236 12:29:41.747450 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
10237 12:29:41.747575 arm64_sve-ptrace_Set_SVE_VL_5808 pass
10238 12:29:41.747723 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 skip
10239 12:29:41.747832 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
10240 12:29:41.747944 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
10241 12:29:41.748044 arm64_sve-ptrace_Set_SVE_VL_5824 pass
10242 12:29:41.748142 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 skip
10243 12:29:41.748259 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
10244 12:29:41.748358 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
10245 12:29:41.748446 arm64_sve-ptrace_Set_SVE_VL_5840 pass
10246 12:29:41.748522 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 skip
10247 12:29:41.748585 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
10248 12:29:41.748665 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
10249 12:29:41.748737 arm64_sve-ptrace_Set_SVE_VL_5856 pass
10250 12:29:41.748801 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 skip
10251 12:29:41.748878 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
10252 12:29:41.748954 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
10253 12:29:41.749278 arm64_sve-ptrace_Set_SVE_VL_5872 pass
10254 12:29:41.749364 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 skip
10255 12:29:41.749482 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
10256 12:29:41.749582 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
10257 12:29:41.749692 arm64_sve-ptrace_Set_SVE_VL_5888 pass
10258 12:29:41.754770 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 skip
10259 12:29:41.755436 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
10260 12:29:41.756048 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
10261 12:29:41.756345 arm64_sve-ptrace_Set_SVE_VL_5904 pass
10262 12:29:41.756713 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 skip
10263 12:29:41.757080 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
10264 12:29:41.757311 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
10265 12:29:41.757405 arm64_sve-ptrace_Set_SVE_VL_5920 pass
10266 12:29:41.757473 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 skip
10267 12:29:41.757533 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
10268 12:29:41.757808 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
10269 12:29:41.757897 arm64_sve-ptrace_Set_SVE_VL_5936 pass
10270 12:29:41.757988 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 skip
10271 12:29:41.758064 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
10272 12:29:41.758139 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
10273 12:29:41.758213 arm64_sve-ptrace_Set_SVE_VL_5952 pass
10274 12:29:41.758288 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 skip
10275 12:29:41.758361 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
10276 12:29:41.758435 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
10277 12:29:41.758508 arm64_sve-ptrace_Set_SVE_VL_5968 pass
10278 12:29:41.758582 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 skip
10279 12:29:41.758656 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
10280 12:29:41.758751 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
10281 12:29:41.762562 arm64_sve-ptrace_Set_SVE_VL_5984 pass
10282 12:29:41.762752 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 skip
10283 12:29:41.763054 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
10284 12:29:41.763161 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
10285 12:29:41.763251 arm64_sve-ptrace_Set_SVE_VL_6000 pass
10286 12:29:41.763339 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 skip
10287 12:29:41.763443 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
10288 12:29:41.763532 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
10289 12:29:41.763633 arm64_sve-ptrace_Set_SVE_VL_6016 pass
10290 12:29:41.763722 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 skip
10291 12:29:41.763823 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
10292 12:29:41.764133 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
10293 12:29:41.764240 arm64_sve-ptrace_Set_SVE_VL_6032 pass
10294 12:29:41.764344 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 skip
10295 12:29:41.764448 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
10296 12:29:41.764553 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
10297 12:29:41.764658 arm64_sve-ptrace_Set_SVE_VL_6048 pass
10298 12:29:41.764957 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 skip
10299 12:29:41.765076 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
10300 12:29:41.765379 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
10301 12:29:41.765560 arm64_sve-ptrace_Set_SVE_VL_6064 pass
10302 12:29:41.765679 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 skip
10303 12:29:41.765766 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
10304 12:29:41.770163 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
10305 12:29:41.770753 arm64_sve-ptrace_Set_SVE_VL_6080 pass
10306 12:29:41.770861 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 skip
10307 12:29:41.770952 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
10308 12:29:41.771051 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
10309 12:29:41.771138 arm64_sve-ptrace_Set_SVE_VL_6096 pass
10310 12:29:41.771237 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 skip
10311 12:29:41.771865 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
10312 12:29:41.772076 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
10313 12:29:41.772172 arm64_sve-ptrace_Set_SVE_VL_6112 pass
10314 12:29:41.772260 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 skip
10315 12:29:41.772348 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
10316 12:29:41.772450 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
10317 12:29:41.772540 arm64_sve-ptrace_Set_SVE_VL_6128 pass
10318 12:29:41.772627 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 skip
10319 12:29:41.772732 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
10320 12:29:41.772822 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
10321 12:29:41.773129 arm64_sve-ptrace_Set_SVE_VL_6144 pass
10322 12:29:41.773234 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 skip
10323 12:29:41.773339 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
10324 12:29:41.773730 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
10325 12:29:41.773847 arm64_sve-ptrace_Set_SVE_VL_6160 pass
10326 12:29:41.773937 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 skip
10327 12:29:41.778138 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
10328 12:29:41.778749 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
10329 12:29:41.779184 arm64_sve-ptrace_Set_SVE_VL_6176 pass
10330 12:29:41.779351 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 skip
10331 12:29:41.779513 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
10332 12:29:41.779799 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
10333 12:29:41.779991 arm64_sve-ptrace_Set_SVE_VL_6192 pass
10334 12:29:41.780089 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 skip
10335 12:29:41.780178 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
10336 12:29:41.780269 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
10337 12:29:41.780354 arm64_sve-ptrace_Set_SVE_VL_6208 pass
10338 12:29:41.780453 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 skip
10339 12:29:41.780540 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
10340 12:29:41.780621 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
10341 12:29:41.780701 arm64_sve-ptrace_Set_SVE_VL_6224 pass
10342 12:29:41.801420 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 skip
10343 12:29:41.801874 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
10344 12:29:41.801984 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
10345 12:29:41.802077 arm64_sve-ptrace_Set_SVE_VL_6240 pass
10346 12:29:41.802402 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 skip
10347 12:29:41.802506 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
10348 12:29:41.802589 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
10349 12:29:41.802897 arm64_sve-ptrace_Set_SVE_VL_6256 pass
10350 12:29:41.803039 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 skip
10351 12:29:41.803140 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
10352 12:29:41.803241 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
10353 12:29:41.803323 arm64_sve-ptrace_Set_SVE_VL_6272 pass
10354 12:29:41.803607 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 skip
10355 12:29:41.803713 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
10356 12:29:41.803803 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
10357 12:29:41.803920 arm64_sve-ptrace_Set_SVE_VL_6288 pass
10358 12:29:41.803995 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 skip
10359 12:29:41.804089 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
10360 12:29:41.804173 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
10361 12:29:41.804455 arm64_sve-ptrace_Set_SVE_VL_6304 pass
10362 12:29:41.804578 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 skip
10363 12:29:41.804656 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
10364 12:29:41.805451 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
10365 12:29:41.805555 arm64_sve-ptrace_Set_SVE_VL_6320 pass
10366 12:29:41.805639 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 skip
10367 12:29:41.805732 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
10368 12:29:41.805815 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
10369 12:29:41.805900 arm64_sve-ptrace_Set_SVE_VL_6336 pass
10370 12:29:41.807106 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 skip
10371 12:29:41.807221 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
10372 12:29:41.810140 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
10373 12:29:41.810633 arm64_sve-ptrace_Set_SVE_VL_6352 pass
10374 12:29:41.810750 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 skip
10375 12:29:41.810876 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
10376 12:29:41.811009 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
10377 12:29:41.811129 arm64_sve-ptrace_Set_SVE_VL_6368 pass
10378 12:29:41.811256 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 skip
10379 12:29:41.811369 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
10380 12:29:41.811490 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
10381 12:29:41.811571 arm64_sve-ptrace_Set_SVE_VL_6384 pass
10382 12:29:41.811650 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 skip
10383 12:29:41.811733 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
10384 12:29:41.812089 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
10385 12:29:41.812185 arm64_sve-ptrace_Set_SVE_VL_6400 pass
10386 12:29:41.812608 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 skip
10387 12:29:41.812708 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
10388 12:29:41.812793 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
10389 12:29:41.813157 arm64_sve-ptrace_Set_SVE_VL_6416 pass
10390 12:29:41.813287 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 skip
10391 12:29:41.813390 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
10392 12:29:41.813470 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
10393 12:29:41.813545 arm64_sve-ptrace_Set_SVE_VL_6432 pass
10394 12:29:41.813869 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 skip
10395 12:29:41.814015 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
10396 12:29:41.814268 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
10397 12:29:41.814582 arm64_sve-ptrace_Set_SVE_VL_6448 pass
10398 12:29:41.818225 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 skip
10399 12:29:41.818622 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
10400 12:29:41.818748 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
10401 12:29:41.818850 arm64_sve-ptrace_Set_SVE_VL_6464 pass
10402 12:29:41.818947 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 skip
10403 12:29:41.819018 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
10404 12:29:41.819217 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
10405 12:29:41.819315 arm64_sve-ptrace_Set_SVE_VL_6480 pass
10406 12:29:41.819409 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 skip
10407 12:29:41.819501 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
10408 12:29:41.819787 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
10409 12:29:41.819879 arm64_sve-ptrace_Set_SVE_VL_6496 pass
10410 12:29:41.820000 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 skip
10411 12:29:41.820466 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
10412 12:29:41.820576 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
10413 12:29:41.820667 arm64_sve-ptrace_Set_SVE_VL_6512 pass
10414 12:29:41.820739 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 skip
10415 12:29:41.821174 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
10416 12:29:41.821292 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
10417 12:29:41.821369 arm64_sve-ptrace_Set_SVE_VL_6528 pass
10418 12:29:41.821432 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 skip
10419 12:29:41.821808 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
10420 12:29:41.822120 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
10421 12:29:41.822220 arm64_sve-ptrace_Set_SVE_VL_6544 pass
10422 12:29:41.822317 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 skip
10423 12:29:41.826187 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
10424 12:29:41.826577 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
10425 12:29:41.826668 arm64_sve-ptrace_Set_SVE_VL_6560 pass
10426 12:29:41.826766 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 skip
10427 12:29:41.826890 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
10428 12:29:41.827007 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
10429 12:29:41.827129 arm64_sve-ptrace_Set_SVE_VL_6576 pass
10430 12:29:41.827224 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 skip
10431 12:29:41.827347 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
10432 12:29:41.827467 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
10433 12:29:41.827560 arm64_sve-ptrace_Set_SVE_VL_6592 pass
10434 12:29:41.827671 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 skip
10435 12:29:41.827793 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
10436 12:29:41.828088 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
10437 12:29:41.828206 arm64_sve-ptrace_Set_SVE_VL_6608 pass
10438 12:29:41.828298 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 skip
10439 12:29:41.828376 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
10440 12:29:41.829027 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
10441 12:29:41.829124 arm64_sve-ptrace_Set_SVE_VL_6624 pass
10442 12:29:41.829227 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 skip
10443 12:29:41.829335 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
10444 12:29:41.829431 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
10445 12:29:41.829701 arm64_sve-ptrace_Set_SVE_VL_6640 pass
10446 12:29:41.829804 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 skip
10447 12:29:41.829877 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
10448 12:29:41.829942 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
10449 12:29:41.830016 arm64_sve-ptrace_Set_SVE_VL_6656 pass
10450 12:29:41.834236 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 skip
10451 12:29:41.834704 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
10452 12:29:41.834810 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
10453 12:29:41.835011 arm64_sve-ptrace_Set_SVE_VL_6672 pass
10454 12:29:41.835107 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 skip
10455 12:29:41.835212 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
10456 12:29:41.835302 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
10457 12:29:41.835390 arm64_sve-ptrace_Set_SVE_VL_6688 pass
10458 12:29:41.835491 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 skip
10459 12:29:41.835787 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
10460 12:29:41.835899 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
10461 12:29:41.835988 arm64_sve-ptrace_Set_SVE_VL_6704 pass
10462 12:29:41.837286 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 skip
10463 12:29:41.837426 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
10464 12:29:41.837516 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
10465 12:29:41.837603 arm64_sve-ptrace_Set_SVE_VL_6720 pass
10466 12:29:41.837717 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 skip
10467 12:29:41.837812 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
10468 12:29:41.837901 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
10469 12:29:41.837982 arm64_sve-ptrace_Set_SVE_VL_6736 pass
10470 12:29:41.838062 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 skip
10471 12:29:41.838146 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
10472 12:29:41.838226 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
10473 12:29:41.838305 arm64_sve-ptrace_Set_SVE_VL_6752 pass
10474 12:29:41.838603 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 skip
10475 12:29:41.838706 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
10476 12:29:41.838789 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
10477 12:29:41.838879 arm64_sve-ptrace_Set_SVE_VL_6768 pass
10478 12:29:41.842417 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 skip
10479 12:29:41.842673 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
10480 12:29:41.843011 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
10481 12:29:41.843112 arm64_sve-ptrace_Set_SVE_VL_6784 pass
10482 12:29:41.843191 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 skip
10483 12:29:41.843267 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
10484 12:29:41.843673 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
10485 12:29:41.843775 arm64_sve-ptrace_Set_SVE_VL_6800 pass
10486 12:29:41.843860 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 skip
10487 12:29:41.843941 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
10488 12:29:41.844016 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
10489 12:29:41.844409 arm64_sve-ptrace_Set_SVE_VL_6816 pass
10490 12:29:41.844510 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 skip
10491 12:29:41.844590 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
10492 12:29:41.844874 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
10493 12:29:41.844989 arm64_sve-ptrace_Set_SVE_VL_6832 pass
10494 12:29:41.845069 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 skip
10495 12:29:41.845144 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
10496 12:29:41.845221 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
10497 12:29:41.845297 arm64_sve-ptrace_Set_SVE_VL_6848 pass
10498 12:29:41.845390 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 skip
10499 12:29:41.845468 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
10500 12:29:41.845541 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
10501 12:29:41.845616 arm64_sve-ptrace_Set_SVE_VL_6864 pass
10502 12:29:41.873027 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 skip
10503 12:29:41.873243 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
10504 12:29:41.873342 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
10505 12:29:41.873640 arm64_sve-ptrace_Set_SVE_VL_6880 pass
10506 12:29:41.873751 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 skip
10507 12:29:41.873839 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
10508 12:29:41.873922 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
10509 12:29:41.874020 arm64_sve-ptrace_Set_SVE_VL_6896 pass
10510 12:29:41.874104 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 skip
10511 12:29:41.874188 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
10512 12:29:41.874278 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
10513 12:29:41.874367 arm64_sve-ptrace_Set_SVE_VL_6912 pass
10514 12:29:41.874460 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 skip
10515 12:29:41.874570 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
10516 12:29:41.874667 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
10517 12:29:41.874758 arm64_sve-ptrace_Set_SVE_VL_6928 pass
10518 12:29:41.874848 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 skip
10519 12:29:41.874962 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
10520 12:29:41.875056 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
10521 12:29:41.875146 arm64_sve-ptrace_Set_SVE_VL_6944 pass
10522 12:29:41.875236 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 skip
10523 12:29:41.875343 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
10524 12:29:41.875436 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
10525 12:29:41.875526 arm64_sve-ptrace_Set_SVE_VL_6960 pass
10526 12:29:41.875626 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 skip
10527 12:29:41.875717 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
10528 12:29:41.876027 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
10529 12:29:41.876270 arm64_sve-ptrace_Set_SVE_VL_6976 pass
10530 12:29:41.876421 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 skip
10531 12:29:41.877059 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
10532 12:29:41.877437 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
10533 12:29:41.877691 arm64_sve-ptrace_Set_SVE_VL_6992 pass
10534 12:29:41.879165 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 skip
10535 12:29:41.879403 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
10536 12:29:41.879517 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
10537 12:29:41.879762 arm64_sve-ptrace_Set_SVE_VL_7008 pass
10538 12:29:41.879893 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 skip
10539 12:29:41.880075 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
10540 12:29:41.881611 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
10541 12:29:41.881715 arm64_sve-ptrace_Set_SVE_VL_7024 pass
10542 12:29:41.881804 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 skip
10543 12:29:41.881890 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
10544 12:29:41.881978 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
10545 12:29:41.882070 arm64_sve-ptrace_Set_SVE_VL_7040 pass
10546 12:29:41.882182 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 skip
10547 12:29:41.882274 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
10548 12:29:41.882375 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
10549 12:29:41.882478 arm64_sve-ptrace_Set_SVE_VL_7056 pass
10550 12:29:41.882568 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 skip
10551 12:29:41.882672 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
10552 12:29:41.882773 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
10553 12:29:41.883055 arm64_sve-ptrace_Set_SVE_VL_7072 pass
10554 12:29:41.883150 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 skip
10555 12:29:41.883238 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
10556 12:29:41.883312 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
10557 12:29:41.883394 arm64_sve-ptrace_Set_SVE_VL_7088 pass
10558 12:29:41.883479 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 skip
10559 12:29:41.883562 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
10560 12:29:41.883842 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
10561 12:29:41.883947 arm64_sve-ptrace_Set_SVE_VL_7104 pass
10562 12:29:41.884033 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 skip
10563 12:29:41.884105 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
10564 12:29:41.884189 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
10565 12:29:41.884260 arm64_sve-ptrace_Set_SVE_VL_7120 pass
10566 12:29:41.884753 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 skip
10567 12:29:41.884849 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
10568 12:29:41.884926 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
10569 12:29:41.885011 arm64_sve-ptrace_Set_SVE_VL_7136 pass
10570 12:29:41.885084 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 skip
10571 12:29:41.885154 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
10572 12:29:41.885239 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
10573 12:29:41.885314 arm64_sve-ptrace_Set_SVE_VL_7152 pass
10574 12:29:41.885399 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 skip
10575 12:29:41.885481 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
10576 12:29:41.885564 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
10577 12:29:41.885635 arm64_sve-ptrace_Set_SVE_VL_7168 pass
10578 12:29:41.889754 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 skip
10579 12:29:41.890187 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
10580 12:29:41.890477 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
10581 12:29:41.890682 arm64_sve-ptrace_Set_SVE_VL_7184 pass
10582 12:29:41.890799 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 skip
10583 12:29:41.890888 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
10584 12:29:41.890992 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
10585 12:29:41.891082 arm64_sve-ptrace_Set_SVE_VL_7200 pass
10586 12:29:41.891181 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 skip
10587 12:29:41.891541 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
10588 12:29:41.891703 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
10589 12:29:41.892066 arm64_sve-ptrace_Set_SVE_VL_7216 pass
10590 12:29:41.892217 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 skip
10591 12:29:41.892369 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
10592 12:29:41.892521 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
10593 12:29:41.892684 arm64_sve-ptrace_Set_SVE_VL_7232 pass
10594 12:29:41.892872 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 skip
10595 12:29:41.893037 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
10596 12:29:41.893186 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
10597 12:29:41.893354 arm64_sve-ptrace_Set_SVE_VL_7248 pass
10598 12:29:41.893491 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 skip
10599 12:29:41.893643 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
10600 12:29:41.893801 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
10601 12:29:41.893910 arm64_sve-ptrace_Set_SVE_VL_7264 pass
10602 12:29:41.894028 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 skip
10603 12:29:41.894126 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
10604 12:29:41.894220 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
10605 12:29:41.894315 arm64_sve-ptrace_Set_SVE_VL_7280 pass
10606 12:29:41.894411 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 skip
10607 12:29:41.894505 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
10608 12:29:41.894598 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
10609 12:29:41.897999 arm64_sve-ptrace_Set_SVE_VL_7296 pass
10610 12:29:41.898394 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 skip
10611 12:29:41.898496 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
10612 12:29:41.898608 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
10613 12:29:41.898705 arm64_sve-ptrace_Set_SVE_VL_7312 pass
10614 12:29:41.898817 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 skip
10615 12:29:41.898931 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
10616 12:29:41.899028 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
10617 12:29:41.899124 arm64_sve-ptrace_Set_SVE_VL_7328 pass
10618 12:29:41.899224 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 skip
10619 12:29:41.899503 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
10620 12:29:41.899604 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
10621 12:29:41.899718 arm64_sve-ptrace_Set_SVE_VL_7344 pass
10622 12:29:41.899990 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 skip
10623 12:29:41.900129 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
10624 12:29:41.900260 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
10625 12:29:41.900397 arm64_sve-ptrace_Set_SVE_VL_7360 pass
10626 12:29:41.900551 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 skip
10627 12:29:41.900688 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
10628 12:29:41.900843 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
10629 12:29:41.900958 arm64_sve-ptrace_Set_SVE_VL_7376 pass
10630 12:29:41.901114 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 skip
10631 12:29:41.901504 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
10632 12:29:41.901758 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
10633 12:29:41.901901 arm64_sve-ptrace_Set_SVE_VL_7392 pass
10634 12:29:41.902024 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 skip
10635 12:29:41.902121 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
10636 12:29:41.906214 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
10637 12:29:41.906668 arm64_sve-ptrace_Set_SVE_VL_7408 pass
10638 12:29:41.906763 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 skip
10639 12:29:41.906851 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
10640 12:29:41.909738 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
10641 12:29:41.909959 arm64_sve-ptrace_Set_SVE_VL_7424 pass
10642 12:29:41.910074 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 skip
10643 12:29:41.910165 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
10644 12:29:41.910250 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
10645 12:29:41.910341 arm64_sve-ptrace_Set_SVE_VL_7440 pass
10646 12:29:41.910444 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 skip
10647 12:29:41.910547 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
10648 12:29:41.910650 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
10649 12:29:41.910753 arm64_sve-ptrace_Set_SVE_VL_7456 pass
10650 12:29:41.910856 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 skip
10651 12:29:41.910956 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
10652 12:29:41.911058 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
10653 12:29:41.911154 arm64_sve-ptrace_Set_SVE_VL_7472 pass
10654 12:29:41.911250 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 skip
10655 12:29:41.911346 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
10656 12:29:41.911443 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
10657 12:29:41.911539 arm64_sve-ptrace_Set_SVE_VL_7488 pass
10658 12:29:41.911634 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 skip
10659 12:29:41.911731 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
10660 12:29:41.911827 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
10661 12:29:41.914104 arm64_sve-ptrace_Set_SVE_VL_7504 pass
10662 12:29:41.936491 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 skip
10663 12:29:41.936910 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
10664 12:29:41.936983 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
10665 12:29:41.937860 arm64_sve-ptrace_Set_SVE_VL_7520 pass
10666 12:29:41.937932 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 skip
10667 12:29:41.937997 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
10668 12:29:41.938069 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
10669 12:29:41.938136 arm64_sve-ptrace_Set_SVE_VL_7536 pass
10670 12:29:41.938197 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 skip
10671 12:29:41.938259 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
10672 12:29:41.938322 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
10673 12:29:41.938386 arm64_sve-ptrace_Set_SVE_VL_7552 pass
10674 12:29:41.938448 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 skip
10675 12:29:41.938509 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
10676 12:29:41.940249 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
10677 12:29:41.940375 arm64_sve-ptrace_Set_SVE_VL_7568 pass
10678 12:29:41.940446 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 skip
10679 12:29:41.940512 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
10680 12:29:41.940575 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
10681 12:29:41.940642 arm64_sve-ptrace_Set_SVE_VL_7584 pass
10682 12:29:41.940704 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 skip
10683 12:29:41.940766 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
10684 12:29:41.940827 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
10685 12:29:41.940891 arm64_sve-ptrace_Set_SVE_VL_7600 pass
10686 12:29:41.940957 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 skip
10687 12:29:41.941020 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
10688 12:29:41.941086 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
10689 12:29:41.941151 arm64_sve-ptrace_Set_SVE_VL_7616 pass
10690 12:29:41.941214 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 skip
10691 12:29:41.941277 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
10692 12:29:41.941337 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
10693 12:29:41.941401 arm64_sve-ptrace_Set_SVE_VL_7632 pass
10694 12:29:41.941465 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 skip
10695 12:29:41.941539 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
10696 12:29:41.941619 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
10697 12:29:41.941938 arm64_sve-ptrace_Set_SVE_VL_7648 pass
10698 12:29:41.942007 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 skip
10699 12:29:41.942067 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
10700 12:29:41.942127 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
10701 12:29:41.942187 arm64_sve-ptrace_Set_SVE_VL_7664 pass
10702 12:29:41.942246 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 skip
10703 12:29:41.942308 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
10704 12:29:41.942367 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
10705 12:29:41.942426 arm64_sve-ptrace_Set_SVE_VL_7680 pass
10706 12:29:41.942485 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 skip
10707 12:29:41.942543 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
10708 12:29:41.942602 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
10709 12:29:41.942660 arm64_sve-ptrace_Set_SVE_VL_7696 pass
10710 12:29:41.942718 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 skip
10711 12:29:41.946306 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
10712 12:29:41.946916 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
10713 12:29:41.947025 arm64_sve-ptrace_Set_SVE_VL_7712 pass
10714 12:29:41.947115 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 skip
10715 12:29:41.947197 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
10716 12:29:41.947305 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
10717 12:29:41.947380 arm64_sve-ptrace_Set_SVE_VL_7728 pass
10718 12:29:41.947471 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 skip
10719 12:29:41.948109 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
10720 12:29:41.948214 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
10721 12:29:41.948302 arm64_sve-ptrace_Set_SVE_VL_7744 pass
10722 12:29:41.948415 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 skip
10723 12:29:41.948517 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
10724 12:29:41.948601 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
10725 12:29:41.948686 arm64_sve-ptrace_Set_SVE_VL_7760 pass
10726 12:29:41.948977 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 skip
10727 12:29:41.949114 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
10728 12:29:41.949201 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
10729 12:29:41.949289 arm64_sve-ptrace_Set_SVE_VL_7776 pass
10730 12:29:41.949440 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 skip
10731 12:29:41.949544 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
10732 12:29:41.949664 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
10733 12:29:41.949748 arm64_sve-ptrace_Set_SVE_VL_7792 pass
10734 12:29:41.949825 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 skip
10735 12:29:41.949913 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
10736 12:29:41.949997 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
10737 12:29:41.954143 arm64_sve-ptrace_Set_SVE_VL_7808 pass
10738 12:29:41.954596 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 skip
10739 12:29:41.954717 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
10740 12:29:41.954803 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
10741 12:29:41.954944 arm64_sve-ptrace_Set_SVE_VL_7824 pass
10742 12:29:41.955063 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 skip
10743 12:29:41.955170 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
10744 12:29:41.955267 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
10745 12:29:41.955346 arm64_sve-ptrace_Set_SVE_VL_7840 pass
10746 12:29:41.955467 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 skip
10747 12:29:41.955559 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
10748 12:29:41.955645 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
10749 12:29:41.956029 arm64_sve-ptrace_Set_SVE_VL_7856 pass
10750 12:29:41.956172 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 skip
10751 12:29:41.956259 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
10752 12:29:41.956386 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
10753 12:29:41.956490 arm64_sve-ptrace_Set_SVE_VL_7872 pass
10754 12:29:41.956598 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 skip
10755 12:29:41.956685 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
10756 12:29:41.956807 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
10757 12:29:41.957174 arm64_sve-ptrace_Set_SVE_VL_7888 pass
10758 12:29:41.957269 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 skip
10759 12:29:41.957677 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
10760 12:29:41.957790 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
10761 12:29:41.957859 arm64_sve-ptrace_Set_SVE_VL_7904 pass
10762 12:29:41.957920 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 skip
10763 12:29:41.962308 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
10764 12:29:41.962593 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
10765 12:29:41.962921 arm64_sve-ptrace_Set_SVE_VL_7920 pass
10766 12:29:41.963043 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 skip
10767 12:29:41.963134 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
10768 12:29:41.963213 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
10769 12:29:41.963316 arm64_sve-ptrace_Set_SVE_VL_7936 pass
10770 12:29:41.963400 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 skip
10771 12:29:41.963486 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
10772 12:29:41.963580 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
10773 12:29:41.963664 arm64_sve-ptrace_Set_SVE_VL_7952 pass
10774 12:29:41.963757 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 skip
10775 12:29:41.964062 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
10776 12:29:41.964163 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
10777 12:29:41.964428 arm64_sve-ptrace_Set_SVE_VL_7968 pass
10778 12:29:41.964523 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 skip
10779 12:29:41.964593 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
10780 12:29:41.964683 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
10781 12:29:41.964766 arm64_sve-ptrace_Set_SVE_VL_7984 pass
10782 12:29:41.964858 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 skip
10783 12:29:41.964951 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
10784 12:29:41.965042 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
10785 12:29:41.965136 arm64_sve-ptrace_Set_SVE_VL_8000 pass
10786 12:29:41.965248 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 skip
10787 12:29:41.965342 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
10788 12:29:41.965617 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
10789 12:29:41.965706 arm64_sve-ptrace_Set_SVE_VL_8016 pass
10790 12:29:41.965792 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 skip
10791 12:29:41.965854 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
10792 12:29:41.970141 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
10793 12:29:41.970596 arm64_sve-ptrace_Set_SVE_VL_8032 pass
10794 12:29:41.970740 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 skip
10795 12:29:41.970937 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
10796 12:29:41.971078 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
10797 12:29:41.971218 arm64_sve-ptrace_Set_SVE_VL_8048 pass
10798 12:29:41.971377 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 skip
10799 12:29:41.971527 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
10800 12:29:41.971667 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
10801 12:29:41.971827 arm64_sve-ptrace_Set_SVE_VL_8064 pass
10802 12:29:41.971968 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 skip
10803 12:29:41.972073 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
10804 12:29:41.972165 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
10805 12:29:41.972271 arm64_sve-ptrace_Set_SVE_VL_8080 pass
10806 12:29:41.972360 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 skip
10807 12:29:41.972470 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
10808 12:29:41.972558 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
10809 12:29:41.972657 arm64_sve-ptrace_Set_SVE_VL_8096 pass
10810 12:29:41.972761 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 skip
10811 12:29:41.973074 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
10812 12:29:41.973172 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
10813 12:29:41.973271 arm64_sve-ptrace_Set_SVE_VL_8112 pass
10814 12:29:41.973529 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 skip
10815 12:29:41.973628 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
10816 12:29:41.973753 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
10817 12:29:41.973847 arm64_sve-ptrace_Set_SVE_VL_8128 pass
10818 12:29:41.979807 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 skip
10819 12:29:41.980269 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
10820 12:29:41.980369 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
10821 12:29:41.980455 arm64_sve-ptrace_Set_SVE_VL_8144 pass
10822 12:29:41.995376 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 skip
10823 12:29:41.995626 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
10824 12:29:41.996260 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
10825 12:29:41.996358 arm64_sve-ptrace_Set_SVE_VL_8160 pass
10826 12:29:41.996461 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 skip
10827 12:29:41.996547 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
10828 12:29:41.996620 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
10829 12:29:41.996697 arm64_sve-ptrace_Set_SVE_VL_8176 pass
10830 12:29:41.996767 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 skip
10831 12:29:41.997031 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
10832 12:29:41.997133 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
10833 12:29:41.997222 arm64_sve-ptrace_Set_SVE_VL_8192 pass
10834 12:29:41.997305 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 skip
10835 12:29:41.997388 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
10836 12:29:41.997473 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
10837 12:29:41.997555 arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 pass
10838 12:29:41.997666 arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state pass
10839 12:29:41.997752 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set pass
10840 12:29:41.997824 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared pass
10841 12:29:41.997888 arm64_sve-ptrace_Set_Streaming_SVE_VL_16 pass
10842 12:29:41.997961 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 pass
10843 12:29:41.998055 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 pass
10844 12:29:41.998142 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 pass
10845 12:29:41.998610 arm64_sve-ptrace_Set_Streaming_SVE_VL_32 pass
10846 12:29:41.999062 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 pass
10847 12:29:41.999164 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 pass
10848 12:29:41.999263 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 pass
10849 12:29:41.999363 arm64_sve-ptrace_Set_Streaming_SVE_VL_48 pass
10850 12:29:41.999453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 skip
10851 12:29:41.999538 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 skip
10852 12:29:41.999638 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 skip
10853 12:29:41.999724 arm64_sve-ptrace_Set_Streaming_SVE_VL_64 pass
10854 12:29:41.999804 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 pass
10855 12:29:41.999886 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 pass
10856 12:29:41.999985 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 pass
10857 12:29:42.000069 arm64_sve-ptrace_Set_Streaming_SVE_VL_80 pass
10858 12:29:42.000265 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 skip
10859 12:29:42.000393 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 skip
10860 12:29:42.000513 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 skip
10861 12:29:42.000622 arm64_sve-ptrace_Set_Streaming_SVE_VL_96 pass
10862 12:29:42.000969 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 skip
10863 12:29:42.001197 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 skip
10864 12:29:42.001399 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 skip
10865 12:29:42.001491 arm64_sve-ptrace_Set_Streaming_SVE_VL_112 pass
10866 12:29:42.001586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 skip
10867 12:29:42.002216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 skip
10868 12:29:42.002421 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 skip
10869 12:29:42.002529 arm64_sve-ptrace_Set_Streaming_SVE_VL_128 pass
10870 12:29:42.002634 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 pass
10871 12:29:42.006031 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 pass
10872 12:29:42.006409 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 pass
10873 12:29:42.006668 arm64_sve-ptrace_Set_Streaming_SVE_VL_144 pass
10874 12:29:42.006852 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 skip
10875 12:29:42.006952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 skip
10876 12:29:42.007057 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 skip
10877 12:29:42.007158 arm64_sve-ptrace_Set_Streaming_SVE_VL_160 pass
10878 12:29:42.007408 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 skip
10879 12:29:42.007693 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 skip
10880 12:29:42.007794 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 skip
10881 12:29:42.007882 arm64_sve-ptrace_Set_Streaming_SVE_VL_176 pass
10882 12:29:42.007990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 skip
10883 12:29:42.008753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 skip
10884 12:29:42.008930 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 skip
10885 12:29:42.009042 arm64_sve-ptrace_Set_Streaming_SVE_VL_192 pass
10886 12:29:42.009136 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 skip
10887 12:29:42.009222 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 skip
10888 12:29:42.009321 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 skip
10889 12:29:42.009407 arm64_sve-ptrace_Set_Streaming_SVE_VL_208 pass
10890 12:29:42.009945 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 skip
10891 12:29:42.010061 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 skip
10892 12:29:42.010163 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 skip
10893 12:29:42.018135 arm64_sve-ptrace_Set_Streaming_SVE_VL_224 pass
10894 12:29:42.018581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 skip
10895 12:29:42.018690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 skip
10896 12:29:42.018778 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 skip
10897 12:29:42.018860 arm64_sve-ptrace_Set_Streaming_SVE_VL_240 pass
10898 12:29:42.019074 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 skip
10899 12:29:42.019178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 skip
10900 12:29:42.019305 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 skip
10901 12:29:42.019411 arm64_sve-ptrace_Set_Streaming_SVE_VL_256 pass
10902 12:29:42.019704 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 pass
10903 12:29:42.019801 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 pass
10904 12:29:42.019909 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 pass
10905 12:29:42.019998 arm64_sve-ptrace_Set_Streaming_SVE_VL_272 pass
10906 12:29:42.020103 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 skip
10907 12:29:42.020405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
10908 12:29:42.020524 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
10909 12:29:42.020648 arm64_sve-ptrace_Set_Streaming_SVE_VL_288 pass
10910 12:29:42.021030 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 skip
10911 12:29:42.021138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
10912 12:29:42.021247 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
10913 12:29:42.021356 arm64_sve-ptrace_Set_Streaming_SVE_VL_304 pass
10914 12:29:42.021658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 skip
10915 12:29:42.021766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
10916 12:29:42.026125 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
10917 12:29:42.026542 arm64_sve-ptrace_Set_Streaming_SVE_VL_320 pass
10918 12:29:42.026645 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 skip
10919 12:29:42.026732 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
10920 12:29:42.026838 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
10921 12:29:42.026931 arm64_sve-ptrace_Set_Streaming_SVE_VL_336 pass
10922 12:29:42.027180 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 skip
10923 12:29:42.027268 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
10924 12:29:42.027352 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
10925 12:29:42.027433 arm64_sve-ptrace_Set_Streaming_SVE_VL_352 pass
10926 12:29:42.027701 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 skip
10927 12:29:42.027786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
10928 12:29:42.028060 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
10929 12:29:42.028163 arm64_sve-ptrace_Set_Streaming_SVE_VL_368 pass
10930 12:29:42.028254 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 skip
10931 12:29:42.028331 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
10932 12:29:42.028412 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
10933 12:29:42.028534 arm64_sve-ptrace_Set_Streaming_SVE_VL_384 pass
10934 12:29:42.028641 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 skip
10935 12:29:42.028927 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
10936 12:29:42.029030 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
10937 12:29:42.029139 arm64_sve-ptrace_Set_Streaming_SVE_VL_400 pass
10938 12:29:42.029450 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 skip
10939 12:29:42.029551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
10940 12:29:42.029654 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
10941 12:29:42.034063 arm64_sve-ptrace_Set_Streaming_SVE_VL_416 pass
10942 12:29:42.034472 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 skip
10943 12:29:42.034576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
10944 12:29:42.034676 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
10945 12:29:42.034751 arm64_sve-ptrace_Set_Streaming_SVE_VL_432 pass
10946 12:29:42.034847 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 skip
10947 12:29:42.034933 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
10948 12:29:42.035190 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
10949 12:29:42.035454 arm64_sve-ptrace_Set_Streaming_SVE_VL_448 pass
10950 12:29:42.035536 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 skip
10951 12:29:42.035615 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
10952 12:29:42.035954 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
10953 12:29:42.036023 arm64_sve-ptrace_Set_Streaming_SVE_VL_464 pass
10954 12:29:42.036085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 skip
10955 12:29:42.036322 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
10956 12:29:42.036390 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
10957 12:29:42.036462 arm64_sve-ptrace_Set_Streaming_SVE_VL_480 pass
10958 12:29:42.036539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 skip
10959 12:29:42.053926 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
10960 12:29:42.054351 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
10961 12:29:42.054446 arm64_sve-ptrace_Set_Streaming_SVE_VL_496 pass
10962 12:29:42.054546 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 skip
10963 12:29:42.054659 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
10964 12:29:42.054922 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
10965 12:29:42.055036 arm64_sve-ptrace_Set_Streaming_SVE_VL_512 pass
10966 12:29:42.055331 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 skip
10967 12:29:42.055518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
10968 12:29:42.055652 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
10969 12:29:42.055780 arm64_sve-ptrace_Set_Streaming_SVE_VL_528 pass
10970 12:29:42.055889 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 skip
10971 12:29:42.056182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
10972 12:29:42.056298 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
10973 12:29:42.056401 arm64_sve-ptrace_Set_Streaming_SVE_VL_544 pass
10974 12:29:42.056706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 skip
10975 12:29:42.056806 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
10976 12:29:42.056909 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
10977 12:29:42.057007 arm64_sve-ptrace_Set_Streaming_SVE_VL_560 pass
10978 12:29:42.057103 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 skip
10979 12:29:42.057379 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
10980 12:29:42.057477 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
10981 12:29:42.057558 arm64_sve-ptrace_Set_Streaming_SVE_VL_576 pass
10982 12:29:42.057662 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 skip
10983 12:29:42.062038 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
10984 12:29:42.063351 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
10985 12:29:42.063460 arm64_sve-ptrace_Set_Streaming_SVE_VL_592 pass
10986 12:29:42.063657 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 skip
10987 12:29:42.063766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
10988 12:29:42.063855 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
10989 12:29:42.063943 arm64_sve-ptrace_Set_Streaming_SVE_VL_608 pass
10990 12:29:42.064031 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 skip
10991 12:29:42.064319 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
10992 12:29:42.064427 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
10993 12:29:42.064518 arm64_sve-ptrace_Set_Streaming_SVE_VL_624 pass
10994 12:29:42.064607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 skip
10995 12:29:42.064693 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
10996 12:29:42.064781 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
10997 12:29:42.064885 arm64_sve-ptrace_Set_Streaming_SVE_VL_640 pass
10998 12:29:42.064976 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 skip
10999 12:29:42.065065 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
11000 12:29:42.065154 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
11001 12:29:42.065260 arm64_sve-ptrace_Set_Streaming_SVE_VL_656 pass
11002 12:29:42.065373 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 skip
11003 12:29:42.065462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
11004 12:29:42.065565 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
11005 12:29:42.065677 arm64_sve-ptrace_Set_Streaming_SVE_VL_672 pass
11006 12:29:42.070488 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 skip
11007 12:29:42.070688 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
11008 12:29:42.070985 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
11009 12:29:42.071090 arm64_sve-ptrace_Set_Streaming_SVE_VL_688 pass
11010 12:29:42.071181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 skip
11011 12:29:42.071898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
11012 12:29:42.072005 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
11013 12:29:42.072097 arm64_sve-ptrace_Set_Streaming_SVE_VL_704 pass
11014 12:29:42.072182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 skip
11015 12:29:42.072269 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
11016 12:29:42.072357 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
11017 12:29:42.072644 arm64_sve-ptrace_Set_Streaming_SVE_VL_720 pass
11018 12:29:42.072740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 skip
11019 12:29:42.072847 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
11020 12:29:42.072954 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
11021 12:29:42.073040 arm64_sve-ptrace_Set_Streaming_SVE_VL_736 pass
11022 12:29:42.073137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 skip
11023 12:29:42.073220 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
11024 12:29:42.073490 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
11025 12:29:42.073589 arm64_sve-ptrace_Set_Streaming_SVE_VL_752 pass
11026 12:29:42.073694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 skip
11027 12:29:42.073775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
11028 12:29:42.073838 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
11029 12:29:42.073910 arm64_sve-ptrace_Set_Streaming_SVE_VL_768 pass
11030 12:29:42.078134 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 skip
11031 12:29:42.078526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
11032 12:29:42.078630 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
11033 12:29:42.078722 arm64_sve-ptrace_Set_Streaming_SVE_VL_784 pass
11034 12:29:42.078829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 skip
11035 12:29:42.080262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
11036 12:29:42.080400 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
11037 12:29:42.080492 arm64_sve-ptrace_Set_Streaming_SVE_VL_800 pass
11038 12:29:42.080579 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 skip
11039 12:29:42.080665 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
11040 12:29:42.080750 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
11041 12:29:42.080861 arm64_sve-ptrace_Set_Streaming_SVE_VL_816 pass
11042 12:29:42.080946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 skip
11043 12:29:42.081022 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
11044 12:29:42.081093 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
11045 12:29:42.081172 arm64_sve-ptrace_Set_Streaming_SVE_VL_832 pass
11046 12:29:42.081280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 skip
11047 12:29:42.081396 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
11048 12:29:42.081481 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
11049 12:29:42.081576 arm64_sve-ptrace_Set_Streaming_SVE_VL_848 pass
11050 12:29:42.081681 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 skip
11051 12:29:42.081765 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
11052 12:29:42.081870 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
11053 12:29:42.081973 arm64_sve-ptrace_Set_Streaming_SVE_VL_864 pass
11054 12:29:42.082057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 skip
11055 12:29:42.082127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
11056 12:29:42.086032 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
11057 12:29:42.086404 arm64_sve-ptrace_Set_Streaming_SVE_VL_880 pass
11058 12:29:42.086509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 skip
11059 12:29:42.086614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
11060 12:29:42.086718 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
11061 12:29:42.087006 arm64_sve-ptrace_Set_Streaming_SVE_VL_896 pass
11062 12:29:42.087126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 skip
11063 12:29:42.087429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
11064 12:29:42.087523 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
11065 12:29:42.087623 arm64_sve-ptrace_Set_Streaming_SVE_VL_912 pass
11066 12:29:42.087724 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 skip
11067 12:29:42.088340 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
11068 12:29:42.088445 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
11069 12:29:42.088535 arm64_sve-ptrace_Set_Streaming_SVE_VL_928 pass
11070 12:29:42.088824 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 skip
11071 12:29:42.088936 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
11072 12:29:42.089026 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
11073 12:29:42.089112 arm64_sve-ptrace_Set_Streaming_SVE_VL_944 pass
11074 12:29:42.089210 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 skip
11075 12:29:42.089296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
11076 12:29:42.089396 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
11077 12:29:42.089498 arm64_sve-ptrace_Set_Streaming_SVE_VL_960 pass
11078 12:29:42.089793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 skip
11079 12:29:42.094165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
11080 12:29:42.094341 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
11081 12:29:42.094638 arm64_sve-ptrace_Set_Streaming_SVE_VL_976 pass
11082 12:29:42.094742 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 skip
11083 12:29:42.094830 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
11084 12:29:42.094930 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
11085 12:29:42.095019 arm64_sve-ptrace_Set_Streaming_SVE_VL_992 pass
11086 12:29:42.095117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 skip
11087 12:29:42.095420 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
11088 12:29:42.095563 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
11089 12:29:42.095685 arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 pass
11090 12:29:42.095786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 skip
11091 12:29:42.096099 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
11092 12:29:42.096220 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
11093 12:29:42.096512 arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 pass
11094 12:29:42.096603 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 skip
11095 12:29:42.113021 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
11096 12:29:42.113270 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
11097 12:29:42.113380 arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 pass
11098 12:29:42.113752 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 skip
11099 12:29:42.113865 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
11100 12:29:42.113957 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
11101 12:29:42.114043 arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 pass
11102 12:29:42.114344 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 skip
11103 12:29:42.114450 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
11104 12:29:42.114555 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
11105 12:29:42.114897 arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 pass
11106 12:29:42.115094 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 skip
11107 12:29:42.116875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
11108 12:29:42.117063 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
11109 12:29:42.117175 arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 pass
11110 12:29:42.117264 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 skip
11111 12:29:42.117351 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
11112 12:29:42.117434 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
11113 12:29:42.117519 arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 pass
11114 12:29:42.117602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 skip
11115 12:29:42.117696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
11116 12:29:42.117783 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
11117 12:29:42.117870 arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 pass
11118 12:29:42.117954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 skip
11119 12:29:42.118035 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
11120 12:29:42.118310 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
11121 12:29:42.118393 arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 pass
11122 12:29:42.118463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 skip
11123 12:29:42.118525 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
11124 12:29:42.122118 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
11125 12:29:42.122620 arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 pass
11126 12:29:42.122785 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 skip
11127 12:29:42.122983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
11128 12:29:42.123216 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
11129 12:29:42.123330 arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 pass
11130 12:29:42.123509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 skip
11131 12:29:42.123630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
11132 12:29:42.123733 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
11133 12:29:42.123856 arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 pass
11134 12:29:42.124020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 skip
11135 12:29:42.124157 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
11136 12:29:42.124302 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
11137 12:29:42.124430 arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 pass
11138 12:29:42.124741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 skip
11139 12:29:42.124880 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
11140 12:29:42.124969 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
11141 12:29:42.125067 arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 pass
11142 12:29:42.125350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 skip
11143 12:29:42.125655 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
11144 12:29:42.125760 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
11145 12:29:42.125872 arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 pass
11146 12:29:42.130368 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 skip
11147 12:29:42.130743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
11148 12:29:42.130908 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
11149 12:29:42.131007 arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 pass
11150 12:29:42.131095 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 skip
11151 12:29:42.131181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
11152 12:29:42.131685 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
11153 12:29:42.131792 arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 pass
11154 12:29:42.131882 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 skip
11155 12:29:42.132108 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
11156 12:29:42.132386 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
11157 12:29:42.132509 arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 pass
11158 12:29:42.132867 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 skip
11159 12:29:42.132975 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
11160 12:29:42.133061 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
11161 12:29:42.133137 arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 pass
11162 12:29:42.133218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 skip
11163 12:29:42.133294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
11164 12:29:42.133380 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
11165 12:29:42.133468 arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 pass
11166 12:29:42.133542 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 skip
11167 12:29:42.133637 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
11168 12:29:42.133771 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
11169 12:29:42.138813 arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 pass
11170 12:29:42.139018 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 skip
11171 12:29:42.139105 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
11172 12:29:42.139597 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
11173 12:29:42.139701 arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 pass
11174 12:29:42.139782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 skip
11175 12:29:42.139859 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
11176 12:29:42.139986 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
11177 12:29:42.140088 arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 pass
11178 12:29:42.140183 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 skip
11179 12:29:42.140282 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
11180 12:29:42.140365 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
11181 12:29:42.140447 arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 pass
11182 12:29:42.140549 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 skip
11183 12:29:42.140658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
11184 12:29:42.140761 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
11185 12:29:42.141052 arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 pass
11186 12:29:42.141422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 skip
11187 12:29:42.141616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
11188 12:29:42.141801 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
11189 12:29:42.141961 arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 pass
11190 12:29:42.142068 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 skip
11191 12:29:42.148292 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
11192 12:29:42.148507 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
11193 12:29:42.148598 arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 pass
11194 12:29:42.148683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 skip
11195 12:29:42.148768 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
11196 12:29:42.148850 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
11197 12:29:42.148939 arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 pass
11198 12:29:42.149024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 skip
11199 12:29:42.149110 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
11200 12:29:42.149197 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
11201 12:29:42.149282 arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 pass
11202 12:29:42.149368 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 skip
11203 12:29:42.149680 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
11204 12:29:42.149793 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
11205 12:29:42.149880 arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 pass
11206 12:29:42.149962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 skip
11207 12:29:42.150044 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
11208 12:29:42.150124 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
11209 12:29:42.150202 arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 pass
11210 12:29:42.150279 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 skip
11211 12:29:42.150376 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
11212 12:29:42.150464 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
11213 12:29:42.159898 arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 pass
11214 12:29:42.160138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 skip
11215 12:29:42.160235 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
11216 12:29:42.160328 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
11217 12:29:42.160417 arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 pass
11218 12:29:42.160508 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 skip
11219 12:29:42.160597 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
11220 12:29:42.160687 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
11221 12:29:42.160778 arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 pass
11222 12:29:42.160869 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 skip
11223 12:29:42.160959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
11224 12:29:42.161047 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
11225 12:29:42.161138 arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 pass
11226 12:29:42.161226 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 skip
11227 12:29:42.161315 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
11228 12:29:42.161403 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
11229 12:29:42.181741 arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 pass
11230 12:29:42.181977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 skip
11231 12:29:42.182069 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
11232 12:29:42.182154 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
11233 12:29:42.182236 arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 pass
11234 12:29:42.182318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 skip
11235 12:29:42.182399 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
11236 12:29:42.182479 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
11237 12:29:42.182565 arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 pass
11238 12:29:42.182646 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 skip
11239 12:29:42.182729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
11240 12:29:42.182814 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
11241 12:29:42.182912 arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 pass
11242 12:29:42.183003 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 skip
11243 12:29:42.183087 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
11244 12:29:42.183166 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
11245 12:29:42.183246 arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 pass
11246 12:29:42.183324 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 skip
11247 12:29:42.183410 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
11248 12:29:42.183516 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
11249 12:29:42.183608 arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 pass
11250 12:29:42.184532 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 skip
11251 12:29:42.184666 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
11252 12:29:42.184753 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
11253 12:29:42.184833 arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 pass
11254 12:29:42.184907 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 skip
11255 12:29:42.184990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
11256 12:29:42.185075 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
11257 12:29:42.185160 arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 pass
11258 12:29:42.186319 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 skip
11259 12:29:42.187119 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
11260 12:29:42.187217 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
11261 12:29:42.187292 arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 pass
11262 12:29:42.187377 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 skip
11263 12:29:42.187656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
11264 12:29:42.187761 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
11265 12:29:42.188041 arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 pass
11266 12:29:42.188338 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 skip
11267 12:29:42.188431 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
11268 12:29:42.188517 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
11269 12:29:42.188785 arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 pass
11270 12:29:42.188877 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 skip
11271 12:29:42.188965 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
11272 12:29:42.189050 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
11273 12:29:42.189133 arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 pass
11274 12:29:42.189216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 skip
11275 12:29:42.189491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
11276 12:29:42.189586 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
11277 12:29:42.189686 arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 pass
11278 12:29:42.189774 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 skip
11279 12:29:42.189962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
11280 12:29:42.190075 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
11281 12:29:42.190364 arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 pass
11282 12:29:42.193800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 skip
11283 12:29:42.199207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
11284 12:29:42.200111 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
11285 12:29:42.200460 arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 pass
11286 12:29:42.200575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 skip
11287 12:29:42.200770 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
11288 12:29:42.201315 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
11289 12:29:42.201898 arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 pass
11290 12:29:42.202011 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 skip
11291 12:29:42.202106 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
11292 12:29:42.202435 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
11293 12:29:42.202586 arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 pass
11294 12:29:42.202794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 skip
11295 12:29:42.202985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
11296 12:29:42.203187 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
11297 12:29:42.203389 arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 pass
11298 12:29:42.203585 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 skip
11299 12:29:42.203789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
11300 12:29:42.203938 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
11301 12:29:42.204170 arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 pass
11302 12:29:42.204375 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 skip
11303 12:29:42.204672 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
11304 12:29:42.204837 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
11305 12:29:42.205042 arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 pass
11306 12:29:42.205217 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 skip
11307 12:29:42.205520 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
11308 12:29:42.205630 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
11309 12:29:42.205730 arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 pass
11310 12:29:42.206013 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 skip
11311 12:29:42.206221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
11312 12:29:42.206468 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
11313 12:29:42.206623 arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 pass
11314 12:29:42.206854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 skip
11315 12:29:42.206967 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
11316 12:29:42.207578 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
11317 12:29:42.208010 arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 pass
11318 12:29:42.208129 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 skip
11319 12:29:42.208226 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
11320 12:29:42.208343 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
11321 12:29:42.208441 arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 pass
11322 12:29:42.208536 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 skip
11323 12:29:42.208630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
11324 12:29:42.208724 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
11325 12:29:42.210259 arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 pass
11326 12:29:42.210609 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 skip
11327 12:29:42.210763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
11328 12:29:42.210933 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
11329 12:29:42.211081 arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 pass
11330 12:29:42.213095 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 skip
11331 12:29:42.213354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
11332 12:29:42.213771 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
11333 12:29:42.213905 arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 pass
11334 12:29:42.214006 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 skip
11335 12:29:42.214098 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
11336 12:29:42.214190 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
11337 12:29:42.214507 arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 pass
11338 12:29:42.214623 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 skip
11339 12:29:42.214724 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
11340 12:29:42.214818 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
11341 12:29:42.214912 arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 pass
11342 12:29:42.215006 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 skip
11343 12:29:42.215100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
11344 12:29:42.215196 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
11345 12:29:42.215289 arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 pass
11346 12:29:42.215380 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 skip
11347 12:29:42.215471 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
11348 12:29:42.215563 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
11349 12:29:42.215656 arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 pass
11350 12:29:42.218283 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 skip
11351 12:29:42.218795 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
11352 12:29:42.218922 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
11353 12:29:42.219024 arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 pass
11354 12:29:42.219110 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 skip
11355 12:29:42.219426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
11356 12:29:42.219531 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
11357 12:29:42.219827 arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 pass
11358 12:29:42.219932 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 skip
11359 12:29:42.220041 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
11360 12:29:42.220146 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
11361 12:29:42.220251 arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 pass
11362 12:29:42.220534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 skip
11363 12:29:42.243603 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
11364 12:29:42.244119 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
11365 12:29:42.244219 arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 pass
11366 12:29:42.244316 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 skip
11367 12:29:42.244422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
11368 12:29:42.244550 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
11369 12:29:42.244663 arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 pass
11370 12:29:42.244763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 skip
11371 12:29:42.245185 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
11372 12:29:42.245284 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
11373 12:29:42.245367 arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 pass
11374 12:29:42.245447 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 skip
11375 12:29:42.245526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
11376 12:29:42.245624 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
11377 12:29:42.245719 arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 pass
11378 12:29:42.245812 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 skip
11379 12:29:42.245927 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
11380 12:29:42.246011 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
11381 12:29:42.246327 arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 pass
11382 12:29:42.246429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 skip
11383 12:29:42.246815 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
11384 12:29:42.246945 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
11385 12:29:42.247043 arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 pass
11386 12:29:42.247135 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 skip
11387 12:29:42.247375 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
11388 12:29:42.247474 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
11389 12:29:42.247581 arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 pass
11390 12:29:42.247694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 skip
11391 12:29:42.247831 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
11392 12:29:42.247946 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
11393 12:29:42.248064 arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 pass
11394 12:29:42.248146 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 skip
11395 12:29:42.257759 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
11396 12:29:42.258005 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
11397 12:29:42.258097 arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 pass
11398 12:29:42.258183 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 skip
11399 12:29:42.258265 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
11400 12:29:42.258345 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
11401 12:29:42.258428 arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 pass
11402 12:29:42.258512 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 skip
11403 12:29:42.258600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
11404 12:29:42.258726 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
11405 12:29:42.258822 arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 pass
11406 12:29:42.258914 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 skip
11407 12:29:42.259005 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
11408 12:29:42.259096 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
11409 12:29:42.259189 arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 pass
11410 12:29:42.259280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 skip
11411 12:29:42.259374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
11412 12:29:42.259466 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
11413 12:29:42.259558 arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 pass
11414 12:29:42.259648 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 skip
11415 12:29:42.259739 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
11416 12:29:42.259831 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
11417 12:29:42.259923 arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 pass
11418 12:29:42.260017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 skip
11419 12:29:42.260301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
11420 12:29:42.260399 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
11421 12:29:42.260494 arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 pass
11422 12:29:42.260586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 skip
11423 12:29:42.260677 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
11424 12:29:42.260767 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
11425 12:29:42.260857 arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 pass
11426 12:29:42.260948 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 skip
11427 12:29:42.261288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
11428 12:29:42.261384 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
11429 12:29:42.261459 arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 pass
11430 12:29:42.261534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 skip
11431 12:29:42.261618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
11432 12:29:42.261719 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
11433 12:29:42.266171 arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 pass
11434 12:29:42.266391 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 skip
11435 12:29:42.266694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
11436 12:29:42.266788 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
11437 12:29:42.266877 arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 pass
11438 12:29:42.266970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 skip
11439 12:29:42.267047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
11440 12:29:42.267121 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
11441 12:29:42.267206 arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 pass
11442 12:29:42.267293 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 skip
11443 12:29:42.267380 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
11444 12:29:42.267672 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
11445 12:29:42.267775 arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 pass
11446 12:29:42.267863 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 skip
11447 12:29:42.268320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
11448 12:29:42.268461 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
11449 12:29:42.268626 arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 pass
11450 12:29:42.268892 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 skip
11451 12:29:42.269804 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
11452 12:29:42.269946 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
11453 12:29:42.270053 arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 pass
11454 12:29:42.270147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 skip
11455 12:29:42.270238 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
11456 12:29:42.270325 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
11457 12:29:42.270431 arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 pass
11458 12:29:42.274359 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 skip
11459 12:29:42.274537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
11460 12:29:42.274631 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
11461 12:29:42.274920 arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 pass
11462 12:29:42.275033 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 skip
11463 12:29:42.275148 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
11464 12:29:42.275242 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
11465 12:29:42.275331 arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 pass
11466 12:29:42.275436 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 skip
11467 12:29:42.275546 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
11468 12:29:42.275906 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
11469 12:29:42.276419 arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 pass
11470 12:29:42.276530 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 skip
11471 12:29:42.276623 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
11472 12:29:42.276728 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
11473 12:29:42.276820 arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 pass
11474 12:29:42.277168 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 skip
11475 12:29:42.277276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
11476 12:29:42.277367 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
11477 12:29:42.277458 arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 pass
11478 12:29:42.277565 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 skip
11479 12:29:42.277666 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
11480 12:29:42.277772 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
11481 12:29:42.282130 arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 pass
11482 12:29:42.285777 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 skip
11483 12:29:42.285996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
11484 12:29:42.286079 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
11485 12:29:42.286154 arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 pass
11486 12:29:42.286228 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 skip
11487 12:29:42.286302 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
11488 12:29:42.286376 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
11489 12:29:42.286447 arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 pass
11490 12:29:42.286519 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 skip
11491 12:29:42.286593 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
11492 12:29:42.286665 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
11493 12:29:42.286740 arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 pass
11494 12:29:42.286820 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 skip
11495 12:29:42.286898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
11496 12:29:42.286973 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
11497 12:29:42.310561 arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 pass
11498 12:29:42.311852 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 skip
11499 12:29:42.311964 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
11500 12:29:42.312055 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
11501 12:29:42.312141 arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 pass
11502 12:29:42.312227 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 skip
11503 12:29:42.312313 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
11504 12:29:42.312396 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
11505 12:29:42.312481 arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 pass
11506 12:29:42.312565 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 skip
11507 12:29:42.312650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
11508 12:29:42.312734 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
11509 12:29:42.312822 arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 pass
11510 12:29:42.312933 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 skip
11511 12:29:42.313025 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
11512 12:29:42.313110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
11513 12:29:42.313195 arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 pass
11514 12:29:42.313278 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 skip
11515 12:29:42.313369 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
11516 12:29:42.313453 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
11517 12:29:42.313555 arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 pass
11518 12:29:42.313963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 skip
11519 12:29:42.314068 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
11520 12:29:42.314343 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
11521 12:29:42.314436 arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 pass
11522 12:29:42.314524 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 skip
11523 12:29:42.318214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
11524 12:29:42.319826 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
11525 12:29:42.319965 arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 pass
11526 12:29:42.320488 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 skip
11527 12:29:42.320770 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
11528 12:29:42.321131 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
11529 12:29:42.321223 arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 pass
11530 12:29:42.321308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 skip
11531 12:29:42.321390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
11532 12:29:42.321475 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
11533 12:29:42.321560 arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 pass
11534 12:29:42.321697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 skip
11535 12:29:42.321789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
11536 12:29:42.321875 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
11537 12:29:42.321957 arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 pass
11538 12:29:42.322038 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 skip
11539 12:29:42.322121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
11540 12:29:42.322220 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
11541 12:29:42.322304 arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 pass
11542 12:29:42.326446 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 skip
11543 12:29:42.327555 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
11544 12:29:42.328164 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
11545 12:29:42.328604 arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 pass
11546 12:29:42.328781 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 skip
11547 12:29:42.328915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
11548 12:29:42.329040 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
11549 12:29:42.329162 arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 pass
11550 12:29:42.329285 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 skip
11551 12:29:42.329413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
11552 12:29:42.329544 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
11553 12:29:42.329699 arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 pass
11554 12:29:42.329918 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 skip
11555 12:29:42.330107 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
11556 12:29:42.330254 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
11557 12:29:42.330399 arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 pass
11558 12:29:42.330543 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 skip
11559 12:29:42.330687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
11560 12:29:42.330834 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
11561 12:29:42.331239 arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 pass
11562 12:29:42.331414 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 skip
11563 12:29:42.331546 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
11564 12:29:42.331664 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
11565 12:29:42.331824 arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 pass
11566 12:29:42.331984 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 skip
11567 12:29:42.332169 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
11568 12:29:42.336040 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
11569 12:29:42.336316 arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 pass
11570 12:29:42.336700 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 skip
11571 12:29:42.336806 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
11572 12:29:42.336902 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
11573 12:29:42.336990 arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 pass
11574 12:29:42.337072 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 skip
11575 12:29:42.337174 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
11576 12:29:42.337260 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
11577 12:29:42.337342 arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 pass
11578 12:29:42.337825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 skip
11579 12:29:42.337929 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
11580 12:29:42.338014 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
11581 12:29:42.338096 arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 pass
11582 12:29:42.338377 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 skip
11583 12:29:42.338510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
11584 12:29:42.339513 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
11585 12:29:42.339651 arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 pass
11586 12:29:42.339744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 skip
11587 12:29:42.339834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
11588 12:29:42.339957 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
11589 12:29:42.340574 arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 pass
11590 12:29:42.340712 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 skip
11591 12:29:42.340833 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
11592 12:29:42.341200 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
11593 12:29:42.341922 arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 pass
11594 12:29:42.342022 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 skip
11595 12:29:42.342104 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
11596 12:29:42.342188 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
11597 12:29:42.342266 arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 pass
11598 12:29:42.342348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 skip
11599 12:29:42.342430 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
11600 12:29:42.342604 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
11601 12:29:42.342695 arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 pass
11602 12:29:42.346432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 skip
11603 12:29:42.346649 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
11604 12:29:42.346742 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
11605 12:29:42.347041 arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 pass
11606 12:29:42.347145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 skip
11607 12:29:42.347233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
11608 12:29:42.347521 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
11609 12:29:42.347624 arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 pass
11610 12:29:42.347710 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 skip
11611 12:29:42.347855 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
11612 12:29:42.347967 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
11613 12:29:42.348069 arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 pass
11614 12:29:42.348582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 skip
11615 12:29:42.348733 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
11616 12:29:42.349782 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
11617 12:29:42.349886 arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 pass
11618 12:29:42.349973 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 skip
11619 12:29:42.350053 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
11620 12:29:42.350132 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
11621 12:29:42.350209 arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 pass
11622 12:29:42.350294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 skip
11623 12:29:42.350381 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
11624 12:29:42.350466 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
11625 12:29:42.354141 arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 pass
11626 12:29:42.354544 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 skip
11627 12:29:42.354653 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
11628 12:29:42.354756 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
11629 12:29:42.355041 arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 pass
11630 12:29:42.355154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 skip
11631 12:29:42.380775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
11632 12:29:42.381015 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
11633 12:29:42.381106 arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 pass
11634 12:29:42.381191 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 skip
11635 12:29:42.381278 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
11636 12:29:42.381365 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
11637 12:29:42.381451 arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 pass
11638 12:29:42.381536 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 skip
11639 12:29:42.381622 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
11640 12:29:42.381713 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
11641 12:29:42.381798 arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 pass
11642 12:29:42.381878 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 skip
11643 12:29:42.381959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
11644 12:29:42.382042 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
11645 12:29:42.382122 arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 pass
11646 12:29:42.385780 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 skip
11647 12:29:42.386000 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
11648 12:29:42.386090 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
11649 12:29:42.386176 arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 pass
11650 12:29:42.386263 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 skip
11651 12:29:42.386351 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
11652 12:29:42.386438 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
11653 12:29:42.386524 arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 pass
11654 12:29:42.386632 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 skip
11655 12:29:42.386719 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
11656 12:29:42.386805 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
11657 12:29:42.386892 arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 pass
11658 12:29:42.386995 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 skip
11659 12:29:42.390169 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
11660 12:29:42.390356 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
11661 12:29:42.390443 arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 pass
11662 12:29:42.390526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 skip
11663 12:29:42.390612 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
11664 12:29:42.390697 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
11665 12:29:42.390787 arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 pass
11666 12:29:42.390878 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 skip
11667 12:29:42.390971 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
11668 12:29:42.391062 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
11669 12:29:42.391152 arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 pass
11670 12:29:42.391242 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 skip
11671 12:29:42.391330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
11672 12:29:42.391421 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
11673 12:29:42.391510 arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 pass
11674 12:29:42.391599 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 skip
11675 12:29:42.391687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
11676 12:29:42.394455 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
11677 12:29:42.394982 arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 pass
11678 12:29:42.395170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 skip
11679 12:29:42.395380 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
11680 12:29:42.395557 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
11681 12:29:42.395728 arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 pass
11682 12:29:42.395932 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 skip
11683 12:29:42.396262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
11684 12:29:42.396448 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
11685 12:29:42.396637 arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 pass
11686 12:29:42.396794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 skip
11687 12:29:42.396949 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
11688 12:29:42.397098 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
11689 12:29:42.397250 arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 pass
11690 12:29:42.397401 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 skip
11691 12:29:42.397580 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
11692 12:29:42.397776 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
11693 12:29:42.397938 arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 pass
11694 12:29:42.398100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 skip
11695 12:29:42.398260 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
11696 12:29:42.398449 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
11697 12:29:42.398685 arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 pass
11698 12:29:42.402307 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 skip
11699 12:29:42.402844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
11700 12:29:42.403047 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
11701 12:29:42.403233 arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 pass
11702 12:29:42.403430 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 skip
11703 12:29:42.403600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
11704 12:29:42.403795 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
11705 12:29:42.403967 arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 pass
11706 12:29:42.404154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 skip
11707 12:29:42.404313 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
11708 12:29:42.404846 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
11709 12:29:42.405047 arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 pass
11710 12:29:42.405216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 skip
11711 12:29:42.405378 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
11712 12:29:42.405575 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
11713 12:29:42.405792 arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 pass
11714 12:29:42.406203 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 skip
11715 12:29:42.406360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
11716 12:29:42.406483 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
11717 12:29:42.406602 arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 pass
11718 12:29:42.406717 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 skip
11719 12:29:42.410294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
11720 12:29:42.410715 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
11721 12:29:42.410828 arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 pass
11722 12:29:42.410925 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 skip
11723 12:29:42.411035 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
11724 12:29:42.411127 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
11725 12:29:42.411233 arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 pass
11726 12:29:42.411324 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 skip
11727 12:29:42.411428 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
11728 12:29:42.411777 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
11729 12:29:42.411893 arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 pass
11730 12:29:42.412173 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 skip
11731 12:29:42.412268 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
11732 12:29:42.412677 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
11733 12:29:42.412789 arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 pass
11734 12:29:42.412884 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 skip
11735 12:29:42.413171 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
11736 12:29:42.413285 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
11737 12:29:42.413569 arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 pass
11738 12:29:42.413679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 skip
11739 12:29:42.417950 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
11740 12:29:42.418269 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
11741 12:29:42.418396 arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 pass
11742 12:29:42.418514 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 skip
11743 12:29:42.418812 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
11744 12:29:42.418937 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
11745 12:29:42.419223 arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 pass
11746 12:29:42.419515 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 skip
11747 12:29:42.419597 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
11748 12:29:42.419691 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
11749 12:29:42.419991 arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 pass
11750 12:29:42.420112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 skip
11751 12:29:42.420207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
11752 12:29:42.420493 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
11753 12:29:42.420597 arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 pass
11754 12:29:42.420894 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 skip
11755 12:29:42.420991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
11756 12:29:42.421356 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
11757 12:29:42.421470 arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 pass
11758 12:29:42.421747 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 skip
11759 12:29:42.421827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
11760 12:29:42.426183 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
11761 12:29:42.426276 arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 pass
11762 12:29:42.426592 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 skip
11763 12:29:42.426681 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
11764 12:29:42.426789 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
11765 12:29:42.443606 arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 pass
11766 12:29:42.443961 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 skip
11767 12:29:42.444099 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
11768 12:29:42.444213 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
11769 12:29:42.444312 arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 pass
11770 12:29:42.444426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 skip
11771 12:29:42.444541 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
11772 12:29:42.444843 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
11773 12:29:42.444972 arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 pass
11774 12:29:42.445276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 skip
11775 12:29:42.445629 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
11776 12:29:42.445758 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
11777 12:29:42.446038 arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 pass
11778 12:29:42.446142 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 skip
11779 12:29:42.446264 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
11780 12:29:42.446384 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
11781 12:29:42.446701 arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 pass
11782 12:29:42.446807 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 skip
11783 12:29:42.446924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
11784 12:29:42.447290 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
11785 12:29:42.447403 arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 pass
11786 12:29:42.447507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 skip
11787 12:29:42.447604 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
11788 12:29:42.447919 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
11789 12:29:42.448012 arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 pass
11790 12:29:42.448097 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 skip
11791 12:29:42.448915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
11792 12:29:42.451011 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
11793 12:29:42.451122 arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 pass
11794 12:29:42.451205 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 skip
11795 12:29:42.451289 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
11796 12:29:42.451372 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
11797 12:29:42.451455 arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 pass
11798 12:29:42.451538 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 skip
11799 12:29:42.451620 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
11800 12:29:42.451704 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
11801 12:29:42.451787 arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 pass
11802 12:29:42.454124 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 skip
11803 12:29:42.454480 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
11804 12:29:42.454588 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
11805 12:29:42.454687 arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 pass
11806 12:29:42.454759 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 skip
11807 12:29:42.454841 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
11808 12:29:42.455178 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
11809 12:29:42.455351 arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 pass
11810 12:29:42.455450 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 skip
11811 12:29:42.455553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
11812 12:29:42.455641 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
11813 12:29:42.455739 arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 pass
11814 12:29:42.455838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 skip
11815 12:29:42.455940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
11816 12:29:42.456598 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
11817 12:29:42.456713 arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 pass
11818 12:29:42.456803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 skip
11819 12:29:42.456888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
11820 12:29:42.456987 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
11821 12:29:42.457617 arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 pass
11822 12:29:42.457739 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 skip
11823 12:29:42.457829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
11824 12:29:42.457916 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
11825 12:29:42.458004 arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 pass
11826 12:29:42.458092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 skip
11827 12:29:42.458199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
11828 12:29:42.462055 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
11829 12:29:42.462377 arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 pass
11830 12:29:42.462503 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 skip
11831 12:29:42.462596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
11832 12:29:42.462701 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
11833 12:29:42.462806 arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 pass
11834 12:29:42.462910 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 skip
11835 12:29:42.463282 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
11836 12:29:42.463408 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
11837 12:29:42.463514 arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 pass
11838 12:29:42.463619 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 skip
11839 12:29:42.463724 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
11840 12:29:42.463987 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
11841 12:29:42.464177 arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 pass
11842 12:29:42.464300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 skip
11843 12:29:42.464388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
11844 12:29:42.464484 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
11845 12:29:42.464871 arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 pass
11846 12:29:42.465182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 skip
11847 12:29:42.465265 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
11848 12:29:42.465371 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
11849 12:29:42.465494 arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 pass
11850 12:29:42.465589 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 skip
11851 12:29:42.465750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
11852 12:29:42.465874 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
11853 12:29:42.473930 arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 pass
11854 12:29:42.474269 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 skip
11855 12:29:42.474393 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
11856 12:29:42.474488 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
11857 12:29:42.474871 arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 pass
11858 12:29:42.474980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 skip
11859 12:29:42.475084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
11860 12:29:42.475189 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
11861 12:29:42.475288 arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 pass
11862 12:29:42.475387 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 skip
11863 12:29:42.475706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
11864 12:29:42.475829 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
11865 12:29:42.476129 arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 pass
11866 12:29:42.476619 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 skip
11867 12:29:42.476838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
11868 12:29:42.476931 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
11869 12:29:42.477015 arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 pass
11870 12:29:42.477410 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 skip
11871 12:29:42.477730 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
11872 12:29:42.477828 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
11873 12:29:42.477906 arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 pass
11874 12:29:42.478071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 skip
11875 12:29:42.481756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
11876 12:29:42.482197 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
11877 12:29:42.482473 arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 pass
11878 12:29:42.482576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 skip
11879 12:29:42.482866 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
11880 12:29:42.482977 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
11881 12:29:42.483070 arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 pass
11882 12:29:42.483158 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 skip
11883 12:29:42.483270 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
11884 12:29:42.483362 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
11885 12:29:42.483686 arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 pass
11886 12:29:42.483796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 skip
11887 12:29:42.483889 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
11888 12:29:42.484166 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
11889 12:29:42.484268 arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 pass
11890 12:29:42.484356 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 skip
11891 12:29:42.484443 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
11892 12:29:42.484549 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
11893 12:29:42.484638 arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 pass
11894 12:29:42.484726 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 skip
11895 12:29:42.484830 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
11896 12:29:42.484935 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
11897 12:29:42.485277 arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 pass
11898 12:29:42.485386 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 skip
11899 12:29:42.503855 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
11900 12:29:42.504286 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
11901 12:29:42.504393 arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 pass
11902 12:29:42.504499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 skip
11903 12:29:42.504590 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
11904 12:29:42.504692 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
11905 12:29:42.504778 arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 pass
11906 12:29:42.504880 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 skip
11907 12:29:42.505682 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
11908 12:29:42.505794 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
11909 12:29:42.505886 arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 pass
11910 12:29:42.505970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 skip
11911 12:29:42.506073 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
11912 12:29:42.507380 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
11913 12:29:42.507487 arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 pass
11914 12:29:42.507578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 skip
11915 12:29:42.507664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
11916 12:29:42.507750 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
11917 12:29:42.507836 arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 pass
11918 12:29:42.507921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 skip
11919 12:29:42.508010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
11920 12:29:42.508098 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
11921 12:29:42.508204 arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 pass
11922 12:29:42.508294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 skip
11923 12:29:42.508385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
11924 12:29:42.508475 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
11925 12:29:42.508565 arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 pass
11926 12:29:42.508673 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 skip
11927 12:29:42.508767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
11928 12:29:42.508859 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
11929 12:29:42.508966 arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 pass
11930 12:29:42.509058 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 skip
11931 12:29:42.509164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
11932 12:29:42.509281 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
11933 12:29:42.509389 arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 pass
11934 12:29:42.509497 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 skip
11935 12:29:42.509606 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
11936 12:29:42.509913 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
11937 12:29:42.514157 arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 pass
11938 12:29:42.514767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 skip
11939 12:29:42.514880 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
11940 12:29:42.514981 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
11941 12:29:42.515425 arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 pass
11942 12:29:42.515534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 skip
11943 12:29:42.515623 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
11944 12:29:42.515711 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
11945 12:29:42.515797 arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 pass
11946 12:29:42.516171 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 skip
11947 12:29:42.516685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
11948 12:29:42.516821 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
11949 12:29:42.516913 arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 pass
11950 12:29:42.516998 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 skip
11951 12:29:42.517080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
11952 12:29:42.517158 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
11953 12:29:42.517237 arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 pass
11954 12:29:42.517301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 skip
11955 12:29:42.517728 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
11956 12:29:42.517839 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
11957 12:29:42.517924 arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 pass
11958 12:29:42.518006 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 skip
11959 12:29:42.518274 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
11960 12:29:42.518361 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
11961 12:29:42.518436 arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 pass
11962 12:29:42.522082 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 skip
11963 12:29:42.522385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
11964 12:29:42.522519 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
11965 12:29:42.522792 arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 pass
11966 12:29:42.522906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 skip
11967 12:29:42.523200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
11968 12:29:42.523531 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
11969 12:29:42.523635 arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 pass
11970 12:29:42.523748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 skip
11971 12:29:42.523867 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
11972 12:29:42.523991 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
11973 12:29:42.524104 arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 pass
11974 12:29:42.526524 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 skip
11975 12:29:42.526641 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
11976 12:29:42.526731 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
11977 12:29:42.526818 arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 pass
11978 12:29:42.526904 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 skip
11979 12:29:42.526989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
11980 12:29:42.527071 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
11981 12:29:42.527157 arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 pass
11982 12:29:42.527245 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 skip
11983 12:29:42.527329 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
11984 12:29:42.527413 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
11985 12:29:42.530133 arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 pass
11986 12:29:42.530531 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 skip
11987 12:29:42.530639 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
11988 12:29:42.530941 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
11989 12:29:42.531052 arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 pass
11990 12:29:42.531138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 skip
11991 12:29:42.531234 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
11992 12:29:42.531317 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
11993 12:29:42.531407 arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 pass
11994 12:29:42.531849 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 skip
11995 12:29:42.532041 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
11996 12:29:42.532141 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
11997 12:29:42.532235 arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 pass
11998 12:29:42.532341 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 skip
11999 12:29:42.532671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
12000 12:29:42.532938 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
12001 12:29:42.533053 arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 pass
12002 12:29:42.533446 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 skip
12003 12:29:42.533556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
12004 12:29:42.533643 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
12005 12:29:42.533726 arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 pass
12006 12:29:42.533811 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 skip
12007 12:29:42.533887 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
12008 12:29:42.535649 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
12009 12:29:42.535767 arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 pass
12010 12:29:42.538135 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 skip
12011 12:29:42.538453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
12012 12:29:42.538571 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
12013 12:29:42.538873 arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 pass
12014 12:29:42.539004 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 skip
12015 12:29:42.539104 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
12016 12:29:42.539469 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
12017 12:29:42.539588 arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 pass
12018 12:29:42.539698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 skip
12019 12:29:42.539806 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
12020 12:29:42.539917 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
12021 12:29:42.540019 arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 pass
12022 12:29:42.540128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 skip
12023 12:29:42.540434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
12024 12:29:42.540559 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
12025 12:29:42.540669 arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 pass
12026 12:29:42.540980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 skip
12027 12:29:42.541115 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
12028 12:29:42.541696 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
12029 12:29:42.545818 arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 pass
12030 12:29:42.545968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 skip
12031 12:29:42.546059 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
12032 12:29:42.546418 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
12033 12:29:42.564877 arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 pass
12034 12:29:42.565402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 skip
12035 12:29:42.565502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
12036 12:29:42.565583 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
12037 12:29:42.565742 arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 pass
12038 12:29:42.565855 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 skip
12039 12:29:42.565990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
12040 12:29:42.566286 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
12041 12:29:42.566394 arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 pass
12042 12:29:42.566490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 skip
12043 12:29:42.566574 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
12044 12:29:42.566665 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
12045 12:29:42.566744 arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 pass
12046 12:29:42.566834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 skip
12047 12:29:42.567207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
12048 12:29:42.567311 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
12049 12:29:42.567667 arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 pass
12050 12:29:42.567771 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 skip
12051 12:29:42.567853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
12052 12:29:42.567931 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
12053 12:29:42.568008 arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 pass
12054 12:29:42.568302 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 skip
12055 12:29:42.568405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
12056 12:29:42.568486 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
12057 12:29:42.568563 arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 pass
12058 12:29:42.568652 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 skip
12059 12:29:42.568866 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
12060 12:29:42.568982 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
12061 12:29:42.569063 arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 pass
12062 12:29:42.569572 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 skip
12063 12:29:42.569710 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
12064 12:29:42.570000 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
12065 12:29:42.570104 arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 pass
12066 12:29:42.570192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 skip
12067 12:29:42.570277 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
12068 12:29:42.570393 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
12069 12:29:42.570486 arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 pass
12070 12:29:42.574257 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 skip
12071 12:29:42.574897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
12072 12:29:42.575019 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
12073 12:29:42.575117 arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 pass
12074 12:29:42.575210 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 skip
12075 12:29:42.575327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
12076 12:29:42.575422 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
12077 12:29:42.575718 arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 pass
12078 12:29:42.575829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 skip
12079 12:29:42.575934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
12080 12:29:42.576019 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
12081 12:29:42.576116 arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 pass
12082 12:29:42.576215 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 skip
12083 12:29:42.576510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
12084 12:29:42.577845 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
12085 12:29:42.578004 arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 pass
12086 12:29:42.578099 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 skip
12087 12:29:42.578184 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
12088 12:29:42.578269 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
12089 12:29:42.578353 arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 pass
12090 12:29:42.578435 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 skip
12091 12:29:42.578521 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
12092 12:29:42.582450 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
12093 12:29:42.582685 arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 pass
12094 12:29:42.582787 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 skip
12095 12:29:42.583093 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
12096 12:29:42.583196 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
12097 12:29:42.583308 arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 pass
12098 12:29:42.583413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 skip
12099 12:29:42.583524 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
12100 12:29:42.583816 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
12101 12:29:42.584105 arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 pass
12102 12:29:42.584213 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 skip
12103 12:29:42.584302 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
12104 12:29:42.584833 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
12105 12:29:42.584968 arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 pass
12106 12:29:42.585119 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 skip
12107 12:29:42.585215 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
12108 12:29:42.586206 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
12109 12:29:42.586438 arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 pass
12110 12:29:42.586530 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 skip
12111 12:29:42.586618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
12112 12:29:42.590151 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
12113 12:29:42.591237 arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 pass
12114 12:29:42.592046 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 skip
12115 12:29:42.592383 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
12116 12:29:42.592648 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
12117 12:29:42.592799 arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 pass
12118 12:29:42.592900 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 skip
12119 12:29:42.593013 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
12120 12:29:42.593107 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
12121 12:29:42.593197 arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 pass
12122 12:29:42.593287 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 skip
12123 12:29:42.593380 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
12124 12:29:42.593474 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
12125 12:29:42.593567 arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 pass
12126 12:29:42.593749 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 skip
12127 12:29:42.593854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
12128 12:29:42.594017 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
12129 12:29:42.594119 arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 pass
12130 12:29:42.594212 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 skip
12131 12:29:42.594306 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
12132 12:29:42.594404 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
12133 12:29:42.594496 arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 pass
12134 12:29:42.598227 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 skip
12135 12:29:42.598665 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
12136 12:29:42.598770 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
12137 12:29:42.598882 arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 pass
12138 12:29:42.598995 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 skip
12139 12:29:42.599300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
12140 12:29:42.599419 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
12141 12:29:42.599530 arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 pass
12142 12:29:42.599830 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 skip
12143 12:29:42.599926 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
12144 12:29:42.600208 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
12145 12:29:42.600324 arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 pass
12146 12:29:42.600436 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 skip
12147 12:29:42.600533 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
12148 12:29:42.600643 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
12149 12:29:42.600754 arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 pass
12150 12:29:42.601054 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 skip
12151 12:29:42.601155 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
12152 12:29:42.601455 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
12153 12:29:42.601555 arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 pass
12154 12:29:42.601858 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 skip
12155 12:29:42.601959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
12156 12:29:42.606190 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
12157 12:29:42.606528 arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 pass
12158 12:29:42.606846 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 skip
12159 12:29:42.606970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
12160 12:29:42.607161 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
12161 12:29:42.608146 arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 pass
12162 12:29:42.608265 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 skip
12163 12:29:42.608366 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
12164 12:29:42.608465 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
12165 12:29:42.608557 arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 pass
12166 12:29:42.608668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 skip
12167 12:29:42.630247 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
12168 12:29:42.630642 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
12169 12:29:42.630760 arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 pass
12170 12:29:42.630876 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 skip
12171 12:29:42.630972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
12172 12:29:42.631082 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
12173 12:29:42.631192 arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 pass
12174 12:29:42.631490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 skip
12175 12:29:42.631797 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
12176 12:29:42.631901 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
12177 12:29:42.633155 arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 pass
12178 12:29:42.634163 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 skip
12179 12:29:42.634266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
12180 12:29:42.634359 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
12181 12:29:42.634451 arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 pass
12182 12:29:42.634543 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 skip
12183 12:29:42.634633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
12184 12:29:42.634725 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
12185 12:29:42.634816 arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 pass
12186 12:29:42.635130 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 skip
12187 12:29:42.635241 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
12188 12:29:42.635337 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
12189 12:29:42.641678 arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 pass
12190 12:29:42.642108 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 skip
12191 12:29:42.642211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
12192 12:29:42.642295 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
12193 12:29:42.642374 arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 pass
12194 12:29:42.642457 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 skip
12195 12:29:42.642533 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
12196 12:29:42.642609 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
12197 12:29:42.642685 arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 pass
12198 12:29:42.642761 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 skip
12199 12:29:42.642836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
12200 12:29:42.642912 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
12201 12:29:42.642990 arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 pass
12202 12:29:42.643065 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 skip
12203 12:29:42.643140 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
12204 12:29:42.643214 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
12205 12:29:42.643289 arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 pass
12206 12:29:42.643363 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 skip
12207 12:29:42.643441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
12208 12:29:42.643516 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
12209 12:29:42.643590 arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 pass
12210 12:29:42.643665 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 skip
12211 12:29:42.643740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
12212 12:29:42.646196 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
12213 12:29:42.646504 arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 pass
12214 12:29:42.646612 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 skip
12215 12:29:42.646744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
12216 12:29:42.646869 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
12217 12:29:42.646994 arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 pass
12218 12:29:42.647308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 skip
12219 12:29:42.647440 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
12220 12:29:42.647571 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
12221 12:29:42.647693 arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 pass
12222 12:29:42.648010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 skip
12223 12:29:42.649321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
12224 12:29:42.649442 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
12225 12:29:42.649538 arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 pass
12226 12:29:42.649612 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 skip
12227 12:29:42.649708 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
12228 12:29:42.649810 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
12229 12:29:42.649904 arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 pass
12230 12:29:42.650197 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 skip
12231 12:29:42.650280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
12232 12:29:42.650345 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
12233 12:29:42.654107 arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 pass
12234 12:29:42.654430 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 skip
12235 12:29:42.654744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
12236 12:29:42.654854 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
12237 12:29:42.654966 arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 pass
12238 12:29:42.655356 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 skip
12239 12:29:42.655459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
12240 12:29:42.655744 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
12241 12:29:42.655844 arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 pass
12242 12:29:42.655999 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 skip
12243 12:29:42.656098 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
12244 12:29:42.656208 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
12245 12:29:42.656317 arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 pass
12246 12:29:42.656618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 skip
12247 12:29:42.656735 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
12248 12:29:42.657074 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
12249 12:29:42.657364 arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 pass
12250 12:29:42.657469 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 skip
12251 12:29:42.657576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
12252 12:29:42.657871 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
12253 12:29:42.657972 arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 pass
12254 12:29:42.658064 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 skip
12255 12:29:42.663114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
12256 12:29:42.663228 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
12257 12:29:42.663311 arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 pass
12258 12:29:42.663591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 skip
12259 12:29:42.663695 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
12260 12:29:42.663775 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
12261 12:29:42.664050 arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 pass
12262 12:29:42.664390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 skip
12263 12:29:42.664506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
12264 12:29:42.664603 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
12265 12:29:42.664698 arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 pass
12266 12:29:42.664795 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 skip
12267 12:29:42.664911 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
12268 12:29:42.665010 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
12269 12:29:42.665107 arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 pass
12270 12:29:42.665205 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 skip
12271 12:29:42.665567 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
12272 12:29:42.665698 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
12273 12:29:42.665799 arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 pass
12274 12:29:42.665897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 skip
12275 12:29:42.665995 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
12276 12:29:42.666110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
12277 12:29:42.666210 arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 pass
12278 12:29:42.670043 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 skip
12279 12:29:42.670373 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
12280 12:29:42.670477 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
12281 12:29:42.670570 arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 pass
12282 12:29:42.670668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 skip
12283 12:29:42.670972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
12284 12:29:42.671280 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
12285 12:29:42.671381 arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 pass
12286 12:29:42.671481 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 skip
12287 12:29:42.671583 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
12288 12:29:42.671915 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
12289 12:29:42.672035 arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 pass
12290 12:29:42.672159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 skip
12291 12:29:42.672436 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
12292 12:29:42.672548 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
12293 12:29:42.672666 arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 pass
12294 12:29:42.672781 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 skip
12295 12:29:42.672881 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
12296 12:29:42.673028 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
12297 12:29:42.673174 arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 pass
12298 12:29:42.673296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 skip
12299 12:29:42.673575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
12300 12:29:42.673678 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
12301 12:29:42.695014 arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 pass
12302 12:29:42.695390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 skip
12303 12:29:42.695507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
12304 12:29:42.695626 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
12305 12:29:42.695736 arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 pass
12306 12:29:42.695829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 skip
12307 12:29:42.696178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
12308 12:29:42.696285 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
12309 12:29:42.696399 arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 pass
12310 12:29:42.696508 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 skip
12311 12:29:42.698839 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
12312 12:29:42.698927 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
12313 12:29:42.698996 arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 pass
12314 12:29:42.699079 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 skip
12315 12:29:42.699192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
12316 12:29:42.699263 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
12317 12:29:42.699324 arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 pass
12318 12:29:42.699384 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 skip
12319 12:29:42.699442 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
12320 12:29:42.702099 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
12321 12:29:42.702479 arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 pass
12322 12:29:42.702579 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 skip
12323 12:29:42.702879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
12324 12:29:42.702992 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
12325 12:29:42.703091 arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 pass
12326 12:29:42.703202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 skip
12327 12:29:42.703296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
12328 12:29:42.703403 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
12329 12:29:42.703512 arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 pass
12330 12:29:42.703603 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 skip
12331 12:29:42.703907 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
12332 12:29:42.704031 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
12333 12:29:42.704143 arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 pass
12334 12:29:42.704251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 skip
12335 12:29:42.704605 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
12336 12:29:42.704733 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
12337 12:29:42.705069 arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 pass
12338 12:29:42.705247 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 skip
12339 12:29:42.705404 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
12340 12:29:42.705535 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
12341 12:29:42.705653 arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 pass
12342 12:29:42.705764 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 skip
12343 12:29:42.705869 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
12344 12:29:42.705948 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
12345 12:29:42.710004 arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 pass
12346 12:29:42.710349 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 skip
12347 12:29:42.710460 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
12348 12:29:42.710571 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
12349 12:29:42.711422 arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 pass
12350 12:29:42.711553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 skip
12351 12:29:42.711639 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
12352 12:29:42.711723 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
12353 12:29:42.712036 arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 pass
12354 12:29:42.712173 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 skip
12355 12:29:42.712260 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
12356 12:29:42.712340 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
12357 12:29:42.712417 arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 pass
12358 12:29:42.713200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 skip
12359 12:29:42.713300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
12360 12:29:42.713567 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
12361 12:29:42.713662 arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 pass
12362 12:29:42.713741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 skip
12363 12:29:42.713816 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
12364 12:29:42.713891 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
12365 12:29:42.713966 arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 pass
12366 12:29:42.714039 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 skip
12367 12:29:42.714128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
12368 12:29:42.720309 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
12369 12:29:42.720427 arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 pass
12370 12:29:42.720584 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 skip
12371 12:29:42.720691 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
12372 12:29:42.720772 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
12373 12:29:42.720849 arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 pass
12374 12:29:42.720926 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 skip
12375 12:29:42.721002 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
12376 12:29:42.721078 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
12377 12:29:42.721153 arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 pass
12378 12:29:42.721228 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 skip
12379 12:29:42.721304 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
12380 12:29:42.721380 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
12381 12:29:42.721457 arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 pass
12382 12:29:42.721534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 skip
12383 12:29:42.721616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
12384 12:29:42.721897 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
12385 12:29:42.721980 arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 pass
12386 12:29:42.722057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 skip
12387 12:29:42.722134 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
12388 12:29:42.722210 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
12389 12:29:42.722286 arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 pass
12390 12:29:42.722361 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 skip
12391 12:29:42.722437 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
12392 12:29:42.722513 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
12393 12:29:42.726314 arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 pass
12394 12:29:42.726424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 skip
12395 12:29:42.726515 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
12396 12:29:42.726746 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
12397 12:29:42.726830 arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 pass
12398 12:29:42.727096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 skip
12399 12:29:42.727165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
12400 12:29:42.727228 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
12401 12:29:42.727299 arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 pass
12402 12:29:42.727612 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 skip
12403 12:29:42.727723 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
12404 12:29:42.727841 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
12405 12:29:42.728146 arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 pass
12406 12:29:42.728263 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 skip
12407 12:29:42.728366 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
12408 12:29:42.728456 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
12409 12:29:42.728546 arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 pass
12410 12:29:42.728676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 skip
12411 12:29:42.728797 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
12412 12:29:42.728913 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
12413 12:29:42.729030 arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 pass
12414 12:29:42.729325 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 skip
12415 12:29:42.729418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
12416 12:29:42.729687 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
12417 12:29:42.729774 arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 pass
12418 12:29:42.734338 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 skip
12419 12:29:42.734458 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
12420 12:29:42.734540 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
12421 12:29:42.735306 arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 pass
12422 12:29:42.735412 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 skip
12423 12:29:42.735492 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
12424 12:29:42.735568 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
12425 12:29:42.735643 arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 pass
12426 12:29:42.735717 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 skip
12427 12:29:42.736033 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
12428 12:29:42.736272 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
12429 12:29:42.736361 arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 pass
12430 12:29:42.736437 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 skip
12431 12:29:42.736513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
12432 12:29:42.736605 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
12433 12:29:42.736684 arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 pass
12434 12:29:42.736761 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 skip
12435 12:29:42.754653 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
12436 12:29:42.755016 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
12437 12:29:42.755131 arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 pass
12438 12:29:42.755226 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 skip
12439 12:29:42.755422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
12440 12:29:42.755520 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
12441 12:29:42.755624 arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 pass
12442 12:29:42.755717 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 skip
12443 12:29:42.756043 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
12444 12:29:42.756151 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
12445 12:29:42.756447 arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 pass
12446 12:29:42.756764 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 skip
12447 12:29:42.756884 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
12448 12:29:42.756980 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
12449 12:29:42.757068 arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 pass
12450 12:29:42.757173 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 skip
12451 12:29:42.757260 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
12452 12:29:42.757645 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
12453 12:29:42.757764 arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 pass
12454 12:29:42.757854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 skip
12455 12:29:42.757954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
12456 12:29:42.762227 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
12457 12:29:42.762565 arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 pass
12458 12:29:42.762672 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 skip
12459 12:29:42.762770 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
12460 12:29:42.762852 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
12461 12:29:42.762944 arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 pass
12462 12:29:42.763037 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 skip
12463 12:29:42.763445 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
12464 12:29:42.763663 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
12465 12:29:42.763833 arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 pass
12466 12:29:42.763954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 skip
12467 12:29:42.764041 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
12468 12:29:42.764122 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
12469 12:29:42.764225 arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 pass
12470 12:29:42.764313 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 skip
12471 12:29:42.764411 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
12472 12:29:42.764511 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
12473 12:29:42.764610 arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 pass
12474 12:29:42.764710 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 skip
12475 12:29:42.765035 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
12476 12:29:42.765158 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
12477 12:29:42.765249 arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 pass
12478 12:29:42.765429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 skip
12479 12:29:42.765739 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
12480 12:29:42.765881 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
12481 12:29:42.765975 arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 pass
12482 12:29:42.770095 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 skip
12483 12:29:42.770692 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
12484 12:29:42.770794 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
12485 12:29:42.770884 arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 pass
12486 12:29:42.770963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 skip
12487 12:29:42.771052 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
12488 12:29:42.771139 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
12489 12:29:42.771226 arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 pass
12490 12:29:42.771326 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 skip
12491 12:29:42.771429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
12492 12:29:42.771528 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
12493 12:29:42.771833 arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 pass
12494 12:29:42.771956 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 skip
12495 12:29:42.772061 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
12496 12:29:42.772150 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
12497 12:29:42.772501 arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 pass
12498 12:29:42.772606 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 skip
12499 12:29:42.772710 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
12500 12:29:42.772800 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
12501 12:29:42.772902 arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 pass
12502 12:29:42.773604 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 skip
12503 12:29:42.773722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
12504 12:29:42.773814 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
12505 12:29:42.773901 arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 pass
12506 12:29:42.773990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 skip
12507 12:29:42.774100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
12508 12:29:42.774193 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
12509 12:29:42.777950 arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 pass
12510 12:29:42.778374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 skip
12511 12:29:42.778480 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
12512 12:29:42.778583 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
12513 12:29:42.778673 arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 pass
12514 12:29:42.778776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 skip
12515 12:29:42.779163 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
12516 12:29:42.779345 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
12517 12:29:42.779439 arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 pass
12518 12:29:42.779553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 skip
12519 12:29:42.779647 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
12520 12:29:42.779749 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
12521 12:29:42.779838 arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 pass
12522 12:29:42.779953 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 skip
12523 12:29:42.780049 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
12524 12:29:42.780138 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
12525 12:29:42.780225 arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 pass
12526 12:29:42.780329 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 skip
12527 12:29:42.780418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
12528 12:29:42.780522 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
12529 12:29:42.780915 arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 pass
12530 12:29:42.781023 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 skip
12531 12:29:42.781113 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
12532 12:29:42.781218 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
12533 12:29:42.781310 arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 pass
12534 12:29:42.781413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 skip
12535 12:29:42.781503 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
12536 12:29:42.781603 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
12537 12:29:42.781900 arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 pass
12538 12:29:42.782004 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 skip
12539 12:29:42.782094 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
12540 12:29:42.786242 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
12541 12:29:42.786502 arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 pass
12542 12:29:42.786600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 skip
12543 12:29:42.786924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
12544 12:29:42.787050 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
12545 12:29:42.787140 arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 pass
12546 12:29:42.787229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 skip
12547 12:29:42.787336 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
12548 12:29:42.787428 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
12549 12:29:42.787516 arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 pass
12550 12:29:42.787606 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 skip
12551 12:29:42.787718 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
12552 12:29:42.787823 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
12553 12:29:42.787936 arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 pass
12554 12:29:42.788240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 skip
12555 12:29:42.788374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
12556 12:29:42.788672 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
12557 12:29:42.788857 arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 pass
12558 12:29:42.789063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 skip
12559 12:29:42.789183 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
12560 12:29:42.789293 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
12561 12:29:42.789403 arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 pass
12562 12:29:42.789529 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 skip
12563 12:29:42.789698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
12564 12:29:42.794105 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
12565 12:29:42.794302 arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 pass
12566 12:29:42.794682 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 skip
12567 12:29:42.794809 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
12568 12:29:42.794905 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
12569 12:29:42.809282 arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 pass
12570 12:29:42.809706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 skip
12571 12:29:42.809826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
12572 12:29:42.809925 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
12573 12:29:42.810032 arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 pass
12574 12:29:42.810402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 skip
12575 12:29:42.811245 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
12576 12:29:42.811729 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
12577 12:29:42.812186 arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 pass
12578 12:29:42.812275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 skip
12579 12:29:42.812360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
12580 12:29:42.812427 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
12581 12:29:42.812488 arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 pass
12582 12:29:42.812550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 skip
12583 12:29:42.812613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
12584 12:29:42.812675 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
12585 12:29:42.812737 arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 pass
12586 12:29:42.812810 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 skip
12587 12:29:42.812874 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
12588 12:29:42.812948 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
12589 12:29:42.813216 arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 pass
12590 12:29:42.813312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 skip
12591 12:29:42.813580 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
12592 12:29:42.813694 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
12593 12:29:42.818123 arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 pass
12594 12:29:42.818491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 skip
12595 12:29:42.818855 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
12596 12:29:42.819031 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
12597 12:29:42.819171 arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 pass
12598 12:29:42.819312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 skip
12599 12:29:42.819468 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
12600 12:29:42.819606 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
12601 12:29:42.819761 arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 pass
12602 12:29:42.819931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 skip
12603 12:29:42.820137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
12604 12:29:42.820291 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
12605 12:29:42.820416 arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 pass
12606 12:29:42.820510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 skip
12607 12:29:42.820600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
12608 12:29:42.820687 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
12609 12:29:42.820790 arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 pass
12610 12:29:42.820883 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 skip
12611 12:29:42.820981 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
12612 12:29:42.821063 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
12613 12:29:42.821166 arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 pass
12614 12:29:42.821254 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 skip
12615 12:29:42.821353 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
12616 12:29:42.821709 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
12617 12:29:42.821964 arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 pass
12618 12:29:42.826250 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 skip
12619 12:29:42.826641 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
12620 12:29:42.826749 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
12621 12:29:42.826840 arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 pass
12622 12:29:42.826946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 skip
12623 12:29:42.827040 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
12624 12:29:42.827335 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
12625 12:29:42.827443 arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 pass
12626 12:29:42.828101 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 skip
12627 12:29:42.828196 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
12628 12:29:42.828288 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
12629 12:29:42.828362 arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 pass
12630 12:29:42.828443 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 skip
12631 12:29:42.828527 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
12632 12:29:42.828829 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
12633 12:29:42.828972 arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 pass
12634 12:29:42.829074 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 skip
12635 12:29:42.829186 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
12636 12:29:42.829293 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
12637 12:29:42.829398 arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 pass
12638 12:29:42.829759 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 skip
12639 12:29:42.829984 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
12640 12:29:42.834692 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
12641 12:29:42.834917 arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 pass
12642 12:29:42.835057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 skip
12643 12:29:42.835402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
12644 12:29:42.835516 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
12645 12:29:42.835609 arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 pass
12646 12:29:42.835722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 skip
12647 12:29:42.835824 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
12648 12:29:42.835916 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
12649 12:29:42.836022 arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 pass
12650 12:29:42.836116 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 skip
12651 12:29:42.836225 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
12652 12:29:42.836528 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
12653 12:29:42.836626 arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 pass
12654 12:29:42.836731 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 skip
12655 12:29:42.836838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
12656 12:29:42.837143 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
12657 12:29:42.837263 arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 pass
12658 12:29:42.837760 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 skip
12659 12:29:42.837890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
12660 12:29:42.838005 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
12661 12:29:42.842238 arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 pass
12662 12:29:42.842617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 skip
12663 12:29:42.842727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
12664 12:29:42.843052 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
12665 12:29:42.843169 arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 pass
12666 12:29:42.843285 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 skip
12667 12:29:42.843389 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
12668 12:29:42.843684 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
12669 12:29:42.843780 arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 pass
12670 12:29:42.843891 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 skip
12671 12:29:42.844007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
12672 12:29:42.844308 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
12673 12:29:42.844669 arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 pass
12674 12:29:42.844768 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 skip
12675 12:29:42.845048 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
12676 12:29:42.845144 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
12677 12:29:42.845252 arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 pass
12678 12:29:42.845359 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 skip
12679 12:29:42.845690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
12680 12:29:42.845790 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
12681 12:29:42.846069 arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 pass
12682 12:29:42.850137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 skip
12683 12:29:42.850453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
12684 12:29:42.850579 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
12685 12:29:42.850688 arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 pass
12686 12:29:42.850797 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 skip
12687 12:29:42.850932 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
12688 12:29:42.851414 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
12689 12:29:42.851518 arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 pass
12690 12:29:42.852083 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 skip
12691 12:29:42.852527 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
12692 12:29:42.853023 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
12693 12:29:42.853131 arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 pass
12694 12:29:42.853295 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 skip
12695 12:29:42.853403 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
12696 12:29:42.853497 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
12697 12:29:42.853592 arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 pass
12698 12:29:42.853689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 skip
12699 12:29:42.853780 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
12700 12:29:42.853872 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
12701 12:29:42.853981 arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 pass
12702 12:29:42.854074 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 skip
12703 12:29:42.881766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
12704 12:29:42.882160 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
12705 12:29:42.882455 arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 pass
12706 12:29:42.882541 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 skip
12707 12:29:42.882831 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
12708 12:29:42.882915 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
12709 12:29:42.883033 arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 pass
12710 12:29:42.883123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 skip
12711 12:29:42.883218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
12712 12:29:42.883680 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
12713 12:29:42.883765 arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 pass
12714 12:29:42.884025 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 skip
12715 12:29:42.884393 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
12716 12:29:42.884468 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
12717 12:29:42.885141 arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 pass
12718 12:29:42.885213 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 skip
12719 12:29:42.885460 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
12720 12:29:42.885530 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
12721 12:29:42.885596 arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 pass
12722 12:29:42.885674 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 skip
12723 12:29:42.885765 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
12724 12:29:42.885843 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
12725 12:29:42.885918 arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 pass
12726 12:29:42.885993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 skip
12727 12:29:42.886084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
12728 12:29:42.890155 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
12729 12:29:42.890244 arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 pass
12730 12:29:42.890505 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 skip
12731 12:29:42.890589 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
12732 12:29:42.891034 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
12733 12:29:42.891117 arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 pass
12734 12:29:42.891576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 skip
12735 12:29:42.891648 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
12736 12:29:42.891723 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
12737 12:29:42.892460 arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 pass
12738 12:29:42.892728 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 skip
12739 12:29:42.892811 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
12740 12:29:42.892888 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
12741 12:29:42.892978 arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 pass
12742 12:29:42.893049 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 skip
12743 12:29:42.893122 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
12744 12:29:42.893605 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
12745 12:29:42.893696 arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 pass
12746 12:29:42.893977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 skip
12747 12:29:42.894066 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
12748 12:29:42.894163 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
12749 12:29:42.898453 arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 pass
12750 12:29:42.898604 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 skip
12751 12:29:42.898707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
12752 12:29:42.898995 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
12753 12:29:42.899163 arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 pass
12754 12:29:42.899308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 skip
12755 12:29:42.899468 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
12756 12:29:42.899608 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
12757 12:29:42.899769 arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 pass
12758 12:29:42.899912 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 skip
12759 12:29:42.900264 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
12760 12:29:42.900352 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
12761 12:29:42.900432 arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 pass
12762 12:29:42.900690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 skip
12763 12:29:42.900759 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
12764 12:29:42.901012 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
12765 12:29:42.901082 arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 pass
12766 12:29:42.901336 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 skip
12767 12:29:42.901406 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
12768 12:29:42.901665 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
12769 12:29:42.901767 arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 pass
12770 12:29:42.906227 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 skip
12771 12:29:42.906544 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
12772 12:29:42.906623 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
12773 12:29:42.906924 arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 pass
12774 12:29:42.907021 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 skip
12775 12:29:42.909145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
12776 12:29:42.909289 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
12777 12:29:42.909404 arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 pass
12778 12:29:42.909500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 skip
12779 12:29:42.909605 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
12780 12:29:42.909720 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
12781 12:29:42.909811 arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 pass
12782 12:29:42.909888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 skip
12783 12:29:42.909963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
12784 12:29:42.910038 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
12785 12:29:42.910113 arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 pass
12786 12:29:42.910187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 skip
12787 12:29:42.910262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
12788 12:29:42.910336 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
12789 12:29:42.910411 arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 pass
12790 12:29:42.910485 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 skip
12791 12:29:42.910758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
12792 12:29:42.910830 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
12793 12:29:42.910906 arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 pass
12794 12:29:42.910980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 skip
12795 12:29:42.911055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
12796 12:29:42.914183 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
12797 12:29:42.914488 arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 pass
12798 12:29:42.914586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 skip
12799 12:29:42.914683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
12800 12:29:42.914773 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
12801 12:29:42.915045 arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 pass
12802 12:29:42.915317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 skip
12803 12:29:42.915411 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
12804 12:29:42.915685 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
12805 12:29:42.915772 arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 pass
12806 12:29:42.915865 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 skip
12807 12:29:42.916148 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
12808 12:29:42.916649 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
12809 12:29:42.916754 arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 pass
12810 12:29:42.917005 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 skip
12811 12:29:42.917071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
12812 12:29:42.917143 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
12813 12:29:42.917216 arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 pass
12814 12:29:42.917471 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 skip
12815 12:29:42.917563 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
12816 12:29:42.917814 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
12817 12:29:42.922269 arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 pass
12818 12:29:42.922568 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 skip
12819 12:29:42.922651 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
12820 12:29:42.922943 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
12821 12:29:42.923119 arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 pass
12822 12:29:42.923295 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 skip
12823 12:29:42.923447 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
12824 12:29:42.923825 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
12825 12:29:42.924072 arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 pass
12826 12:29:42.924174 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 skip
12827 12:29:42.924294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
12828 12:29:42.924591 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
12829 12:29:42.924702 arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 pass
12830 12:29:42.924834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 skip
12831 12:29:42.924936 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
12832 12:29:42.925033 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
12833 12:29:42.925112 arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 pass
12834 12:29:42.925202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 skip
12835 12:29:42.925478 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
12836 12:29:42.925587 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
12837 12:29:42.956855 arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 pass
12838 12:29:42.957121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 skip
12839 12:29:42.957442 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
12840 12:29:42.957543 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
12841 12:29:42.957628 arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 pass
12842 12:29:42.957727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 skip
12843 12:29:42.958033 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
12844 12:29:42.958239 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
12845 12:29:42.958402 arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 pass
12846 12:29:42.959394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 skip
12847 12:29:42.959579 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
12848 12:29:42.959745 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
12849 12:29:42.960030 arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 pass
12850 12:29:42.960194 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 skip
12851 12:29:42.960350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
12852 12:29:42.960512 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
12853 12:29:42.960676 arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 pass
12854 12:29:42.960813 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 skip
12855 12:29:42.961297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
12856 12:29:42.961395 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
12857 12:29:42.961504 arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 pass
12858 12:29:42.961613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 skip
12859 12:29:42.961724 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
12860 12:29:42.961829 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
12861 12:29:42.961911 arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 pass
12862 12:29:42.962012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 skip
12863 12:29:42.962101 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
12864 12:29:42.962177 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
12865 12:29:42.962252 arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 pass
12866 12:29:42.962325 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 skip
12867 12:29:42.962420 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
12868 12:29:42.962491 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
12869 12:29:42.962565 arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 pass
12870 12:29:42.962639 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 skip
12871 12:29:42.962714 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
12872 12:29:42.962788 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
12873 12:29:42.966008 arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 pass
12874 12:29:42.966416 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 skip
12875 12:29:42.966535 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
12876 12:29:42.966654 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
12877 12:29:42.966756 arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 pass
12878 12:29:42.966833 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 skip
12879 12:29:42.966926 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
12880 12:29:42.967209 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
12881 12:29:42.967317 arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 pass
12882 12:29:42.967608 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 skip
12883 12:29:42.967893 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
12884 12:29:42.968013 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
12885 12:29:42.968160 arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 pass
12886 12:29:42.968275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 skip
12887 12:29:42.968387 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
12888 12:29:42.968669 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
12889 12:29:42.968758 arm64_sve-ptrace pass
12890 12:29:42.968882 arm64_sve-probe-vls_Enumerated_16_vector_lengths pass
12891 12:29:42.969185 arm64_sve-probe-vls_All_vector_lengths_valid pass
12892 12:29:42.969278 arm64_sve-probe-vls pass
12893 12:29:42.969374 arm64_vec-syscfg_SVE_default_vector_length_64 pass
12894 12:29:42.969480 arm64_vec-syscfg_SVE_minimum_vector_length_16 pass
12895 12:29:42.969580 arm64_vec-syscfg_SVE_maximum_vector_length_256 pass
12896 12:29:42.969712 arm64_vec-syscfg_SVE_current_VL_is_64 pass
12897 12:29:42.969815 arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 pass
12898 12:29:42.974048 arm64_vec-syscfg_SVE_prctl_set_min_max pass
12899 12:29:42.974354 arm64_vec-syscfg_SVE_vector_length_used_default pass
12900 12:29:42.974456 arm64_vec-syscfg_SVE_vector_length_was_inherited pass
12901 12:29:42.974559 arm64_vec-syscfg_SVE_vector_length_set_on_exec pass
12902 12:29:42.974671 arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors pass
12903 12:29:42.974928 arm64_vec-syscfg_SME_default_vector_length_32 pass
12904 12:29:42.975046 arm64_vec-syscfg_SME_minimum_vector_length_16 pass
12905 12:29:42.975217 arm64_vec-syscfg_SME_maximum_vector_length_256 pass
12906 12:29:42.975411 arm64_vec-syscfg_SME_current_VL_is_32 pass
12907 12:29:42.975585 arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 pass
12908 12:29:42.975754 arm64_vec-syscfg_SME_prctl_set_min_max pass
12909 12:29:42.975950 arm64_vec-syscfg_SME_vector_length_used_default pass
12910 12:29:42.976117 arm64_vec-syscfg_SME_vector_length_was_inherited pass
12911 12:29:42.976278 arm64_vec-syscfg_SME_vector_length_set_on_exec pass
12912 12:29:42.976465 arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors pass
12913 12:29:42.976615 arm64_vec-syscfg pass
12914 12:29:42.976774 arm64_za-fork_fork_test pass
12915 12:29:42.976936 arm64_za-fork pass
12916 12:29:42.977089 arm64_za-ptrace_Set_VL_16 pass
12917 12:29:42.977239 arm64_za-ptrace_Disabled_ZA_for_VL_16 pass
12918 12:29:42.977433 arm64_za-ptrace_Data_match_for_VL_16 pass
12919 12:29:42.977600 arm64_za-ptrace_Set_VL_32 pass
12920 12:29:42.977782 arm64_za-ptrace_Disabled_ZA_for_VL_32 pass
12921 12:29:42.977925 arm64_za-ptrace_Data_match_for_VL_32 pass
12922 12:29:42.978044 arm64_za-ptrace_Set_VL_48 pass
12923 12:29:42.978162 arm64_za-ptrace_Disabled_ZA_for_VL_48 skip
12924 12:29:42.978277 arm64_za-ptrace_Get_and_set_data_for_VL_48 skip
12925 12:29:42.978391 arm64_za-ptrace_Set_VL_64 pass
12926 12:29:42.978503 arm64_za-ptrace_Disabled_ZA_for_VL_64 pass
12927 12:29:42.978615 arm64_za-ptrace_Data_match_for_VL_64 pass
12928 12:29:42.978754 arm64_za-ptrace_Set_VL_80 pass
12929 12:29:42.978876 arm64_za-ptrace_Disabled_ZA_for_VL_80 skip
12930 12:29:42.978992 arm64_za-ptrace_Get_and_set_data_for_VL_80 skip
12931 12:29:42.982259 arm64_za-ptrace_Set_VL_96 pass
12932 12:29:42.982473 arm64_za-ptrace_Disabled_ZA_for_VL_96 skip
12933 12:29:42.982623 arm64_za-ptrace_Get_and_set_data_for_VL_96 skip
12934 12:29:42.982763 arm64_za-ptrace_Set_VL_112 pass
12935 12:29:42.982879 arm64_za-ptrace_Disabled_ZA_for_VL_112 skip
12936 12:29:42.983018 arm64_za-ptrace_Get_and_set_data_for_VL_112 skip
12937 12:29:42.983142 arm64_za-ptrace_Set_VL_128 pass
12938 12:29:42.983261 arm64_za-ptrace_Disabled_ZA_for_VL_128 pass
12939 12:29:42.983385 arm64_za-ptrace_Data_match_for_VL_128 pass
12940 12:29:42.983526 arm64_za-ptrace_Set_VL_144 pass
12941 12:29:42.983643 arm64_za-ptrace_Disabled_ZA_for_VL_144 skip
12942 12:29:42.983767 arm64_za-ptrace_Get_and_set_data_for_VL_144 skip
12943 12:29:42.984257 arm64_za-ptrace_Set_VL_160 pass
12944 12:29:42.984436 arm64_za-ptrace_Disabled_ZA_for_VL_160 skip
12945 12:29:42.984598 arm64_za-ptrace_Get_and_set_data_for_VL_160 skip
12946 12:29:42.984742 arm64_za-ptrace_Set_VL_176 pass
12947 12:29:42.984864 arm64_za-ptrace_Disabled_ZA_for_VL_176 skip
12948 12:29:42.984965 arm64_za-ptrace_Get_and_set_data_for_VL_176 skip
12949 12:29:42.985081 arm64_za-ptrace_Set_VL_192 pass
12950 12:29:42.985221 arm64_za-ptrace_Disabled_ZA_for_VL_192 skip
12951 12:29:42.985336 arm64_za-ptrace_Get_and_set_data_for_VL_192 skip
12952 12:29:42.985459 arm64_za-ptrace_Set_VL_208 pass
12953 12:29:42.985584 arm64_za-ptrace_Disabled_ZA_for_VL_208 skip
12954 12:29:42.985713 arm64_za-ptrace_Get_and_set_data_for_VL_208 skip
12955 12:29:42.985839 arm64_za-ptrace_Set_VL_224 pass
12956 12:29:42.985943 arm64_za-ptrace_Disabled_ZA_for_VL_224 skip
12957 12:29:42.986035 arm64_za-ptrace_Get_and_set_data_for_VL_224 skip
12958 12:29:42.986148 arm64_za-ptrace_Set_VL_240 pass
12959 12:29:42.986241 arm64_za-ptrace_Disabled_ZA_for_VL_240 skip
12960 12:29:42.986328 arm64_za-ptrace_Get_and_set_data_for_VL_240 skip
12961 12:29:42.986414 arm64_za-ptrace_Set_VL_256 pass
12962 12:29:42.986500 arm64_za-ptrace_Disabled_ZA_for_VL_256 pass
12963 12:29:42.986586 arm64_za-ptrace_Data_match_for_VL_256 pass
12964 12:29:42.986673 arm64_za-ptrace_Set_VL_272 pass
12965 12:29:42.990054 arm64_za-ptrace_Disabled_ZA_for_VL_272 skip
12966 12:29:42.990614 arm64_za-ptrace_Get_and_set_data_for_VL_272 skip
12967 12:29:42.990823 arm64_za-ptrace_Set_VL_288 pass
12968 12:29:42.991038 arm64_za-ptrace_Disabled_ZA_for_VL_288 skip
12969 12:29:42.991256 arm64_za-ptrace_Get_and_set_data_for_VL_288 skip
12970 12:29:42.991454 arm64_za-ptrace_Set_VL_304 pass
12971 12:29:42.991698 arm64_za-ptrace_Disabled_ZA_for_VL_304 skip
12972 12:29:42.991861 arm64_za-ptrace_Get_and_set_data_for_VL_304 skip
12973 12:29:42.992022 arm64_za-ptrace_Set_VL_320 pass
12974 12:29:42.992153 arm64_za-ptrace_Disabled_ZA_for_VL_320 skip
12975 12:29:42.992280 arm64_za-ptrace_Get_and_set_data_for_VL_320 skip
12976 12:29:42.992417 arm64_za-ptrace_Set_VL_336 pass
12977 12:29:42.992580 arm64_za-ptrace_Disabled_ZA_for_VL_336 skip
12978 12:29:42.992742 arm64_za-ptrace_Get_and_set_data_for_VL_336 skip
12979 12:29:42.992898 arm64_za-ptrace_Set_VL_352 pass
12980 12:29:42.993055 arm64_za-ptrace_Disabled_ZA_for_VL_352 skip
12981 12:29:42.993184 arm64_za-ptrace_Get_and_set_data_for_VL_352 skip
12982 12:29:42.993343 arm64_za-ptrace_Set_VL_368 pass
12983 12:29:42.993485 arm64_za-ptrace_Disabled_ZA_for_VL_368 skip
12984 12:29:42.993641 arm64_za-ptrace_Get_and_set_data_for_VL_368 skip
12985 12:29:42.994291 arm64_za-ptrace_Set_VL_384 pass
12986 12:29:42.994420 arm64_za-ptrace_Disabled_ZA_for_VL_384 skip
12987 12:29:42.994536 arm64_za-ptrace_Get_and_set_data_for_VL_384 skip
12988 12:29:42.994654 arm64_za-ptrace_Set_VL_400 pass
12989 12:29:42.994771 arm64_za-ptrace_Disabled_ZA_for_VL_400 skip
12990 12:29:42.994886 arm64_za-ptrace_Get_and_set_data_for_VL_400 skip
12991 12:29:42.995002 arm64_za-ptrace_Set_VL_416 pass
12992 12:29:42.995118 arm64_za-ptrace_Disabled_ZA_for_VL_416 skip
12993 12:29:42.995232 arm64_za-ptrace_Get_and_set_data_for_VL_416 skip
12994 12:29:42.995377 arm64_za-ptrace_Set_VL_432 pass
12995 12:29:42.995500 arm64_za-ptrace_Disabled_ZA_for_VL_432 skip
12996 12:29:42.995618 arm64_za-ptrace_Get_and_set_data_for_VL_432 skip
12997 12:29:42.995734 arm64_za-ptrace_Set_VL_448 pass
12998 12:29:42.995848 arm64_za-ptrace_Disabled_ZA_for_VL_448 skip
12999 12:29:42.998428 arm64_za-ptrace_Get_and_set_data_for_VL_448 skip
13000 12:29:42.998613 arm64_za-ptrace_Set_VL_464 pass
13001 12:29:42.998770 arm64_za-ptrace_Disabled_ZA_for_VL_464 skip
13002 12:29:42.998942 arm64_za-ptrace_Get_and_set_data_for_VL_464 skip
13003 12:29:42.999046 arm64_za-ptrace_Set_VL_480 pass
13004 12:29:42.999134 arm64_za-ptrace_Disabled_ZA_for_VL_480 skip
13005 12:29:42.999226 arm64_za-ptrace_Get_and_set_data_for_VL_480 skip
13006 12:29:42.999310 arm64_za-ptrace_Set_VL_496 pass
13007 12:29:42.999452 arm64_za-ptrace_Disabled_ZA_for_VL_496 skip
13008 12:29:43.022933 arm64_za-ptrace_Get_and_set_data_for_VL_496 skip
13009 12:29:43.023221 arm64_za-ptrace_Set_VL_512 pass
13010 12:29:43.023399 arm64_za-ptrace_Disabled_ZA_for_VL_512 skip
13011 12:29:43.023559 arm64_za-ptrace_Get_and_set_data_for_VL_512 skip
13012 12:29:43.023709 arm64_za-ptrace_Set_VL_528 pass
13013 12:29:43.023879 arm64_za-ptrace_Disabled_ZA_for_VL_528 skip
13014 12:29:43.024038 arm64_za-ptrace_Get_and_set_data_for_VL_528 skip
13015 12:29:43.024207 arm64_za-ptrace_Set_VL_544 pass
13016 12:29:43.024805 arm64_za-ptrace_Disabled_ZA_for_VL_544 skip
13017 12:29:43.024986 arm64_za-ptrace_Get_and_set_data_for_VL_544 skip
13018 12:29:43.025153 arm64_za-ptrace_Set_VL_560 pass
13019 12:29:43.025302 arm64_za-ptrace_Disabled_ZA_for_VL_560 skip
13020 12:29:43.025461 arm64_za-ptrace_Get_and_set_data_for_VL_560 skip
13021 12:29:43.025623 arm64_za-ptrace_Set_VL_576 pass
13022 12:29:43.025836 arm64_za-ptrace_Disabled_ZA_for_VL_576 skip
13023 12:29:43.026003 arm64_za-ptrace_Get_and_set_data_for_VL_576 skip
13024 12:29:43.026142 arm64_za-ptrace_Set_VL_592 pass
13025 12:29:43.026264 arm64_za-ptrace_Disabled_ZA_for_VL_592 skip
13026 12:29:43.026382 arm64_za-ptrace_Get_and_set_data_for_VL_592 skip
13027 12:29:43.026498 arm64_za-ptrace_Set_VL_608 pass
13028 12:29:43.026617 arm64_za-ptrace_Disabled_ZA_for_VL_608 skip
13029 12:29:43.026733 arm64_za-ptrace_Get_and_set_data_for_VL_608 skip
13030 12:29:43.026846 arm64_za-ptrace_Set_VL_624 pass
13031 12:29:43.026992 arm64_za-ptrace_Disabled_ZA_for_VL_624 skip
13032 12:29:43.027116 arm64_za-ptrace_Get_and_set_data_for_VL_624 skip
13033 12:29:43.027235 arm64_za-ptrace_Set_VL_640 pass
13034 12:29:43.027350 arm64_za-ptrace_Disabled_ZA_for_VL_640 skip
13035 12:29:43.027463 arm64_za-ptrace_Get_and_set_data_for_VL_640 skip
13036 12:29:43.027578 arm64_za-ptrace_Set_VL_656 pass
13037 12:29:43.027698 arm64_za-ptrace_Disabled_ZA_for_VL_656 skip
13038 12:29:43.027814 arm64_za-ptrace_Get_and_set_data_for_VL_656 skip
13039 12:29:43.027928 arm64_za-ptrace_Set_VL_672 pass
13040 12:29:43.028043 arm64_za-ptrace_Disabled_ZA_for_VL_672 skip
13041 12:29:43.030314 arm64_za-ptrace_Get_and_set_data_for_VL_672 skip
13042 12:29:43.030470 arm64_za-ptrace_Set_VL_688 pass
13043 12:29:43.030651 arm64_za-ptrace_Disabled_ZA_for_VL_688 skip
13044 12:29:43.030801 arm64_za-ptrace_Get_and_set_data_for_VL_688 skip
13045 12:29:43.030956 arm64_za-ptrace_Set_VL_704 pass
13046 12:29:43.031143 arm64_za-ptrace_Disabled_ZA_for_VL_704 skip
13047 12:29:43.031307 arm64_za-ptrace_Get_and_set_data_for_VL_704 skip
13048 12:29:43.031464 arm64_za-ptrace_Set_VL_720 pass
13049 12:29:43.031640 arm64_za-ptrace_Disabled_ZA_for_VL_720 skip
13050 12:29:43.031819 arm64_za-ptrace_Get_and_set_data_for_VL_720 skip
13051 12:29:43.031978 arm64_za-ptrace_Set_VL_736 pass
13052 12:29:43.032122 arm64_za-ptrace_Disabled_ZA_for_VL_736 skip
13053 12:29:43.032255 arm64_za-ptrace_Get_and_set_data_for_VL_736 skip
13054 12:29:43.032392 arm64_za-ptrace_Set_VL_752 pass
13055 12:29:43.032539 arm64_za-ptrace_Disabled_ZA_for_VL_752 skip
13056 12:29:43.032665 arm64_za-ptrace_Get_and_set_data_for_VL_752 skip
13057 12:29:43.032791 arm64_za-ptrace_Set_VL_768 pass
13058 12:29:43.032909 arm64_za-ptrace_Disabled_ZA_for_VL_768 skip
13059 12:29:43.033025 arm64_za-ptrace_Get_and_set_data_for_VL_768 skip
13060 12:29:43.033146 arm64_za-ptrace_Set_VL_784 pass
13061 12:29:43.033264 arm64_za-ptrace_Disabled_ZA_for_VL_784 skip
13062 12:29:43.033371 arm64_za-ptrace_Get_and_set_data_for_VL_784 skip
13063 12:29:43.033516 arm64_za-ptrace_Set_VL_800 pass
13064 12:29:43.034077 arm64_za-ptrace_Disabled_ZA_for_VL_800 skip
13065 12:29:43.034197 arm64_za-ptrace_Get_and_set_data_for_VL_800 skip
13066 12:29:43.034290 arm64_za-ptrace_Set_VL_816 pass
13067 12:29:43.034379 arm64_za-ptrace_Disabled_ZA_for_VL_816 skip
13068 12:29:43.034468 arm64_za-ptrace_Get_and_set_data_for_VL_816 skip
13069 12:29:43.034568 arm64_za-ptrace_Set_VL_832 pass
13070 12:29:43.034657 arm64_za-ptrace_Disabled_ZA_for_VL_832 skip
13071 12:29:43.034745 arm64_za-ptrace_Get_and_set_data_for_VL_832 skip
13072 12:29:43.034835 arm64_za-ptrace_Set_VL_848 pass
13073 12:29:43.034924 arm64_za-ptrace_Disabled_ZA_for_VL_848 skip
13074 12:29:43.038059 arm64_za-ptrace_Get_and_set_data_for_VL_848 skip
13075 12:29:43.038472 arm64_za-ptrace_Set_VL_864 pass
13076 12:29:43.038655 arm64_za-ptrace_Disabled_ZA_for_VL_864 skip
13077 12:29:43.038822 arm64_za-ptrace_Get_and_set_data_for_VL_864 skip
13078 12:29:43.038987 arm64_za-ptrace_Set_VL_880 pass
13079 12:29:43.039177 arm64_za-ptrace_Disabled_ZA_for_VL_880 skip
13080 12:29:43.039329 arm64_za-ptrace_Get_and_set_data_for_VL_880 skip
13081 12:29:43.039467 arm64_za-ptrace_Set_VL_896 pass
13082 12:29:43.039627 arm64_za-ptrace_Disabled_ZA_for_VL_896 skip
13083 12:29:43.039785 arm64_za-ptrace_Get_and_set_data_for_VL_896 skip
13084 12:29:43.039929 arm64_za-ptrace_Set_VL_912 pass
13085 12:29:43.040093 arm64_za-ptrace_Disabled_ZA_for_VL_912 skip
13086 12:29:43.040234 arm64_za-ptrace_Get_and_set_data_for_VL_912 skip
13087 12:29:43.040379 arm64_za-ptrace_Set_VL_928 pass
13088 12:29:43.040527 arm64_za-ptrace_Disabled_ZA_for_VL_928 skip
13089 12:29:43.040691 arm64_za-ptrace_Get_and_set_data_for_VL_928 skip
13090 12:29:43.040816 arm64_za-ptrace_Set_VL_944 pass
13091 12:29:43.040931 arm64_za-ptrace_Disabled_ZA_for_VL_944 skip
13092 12:29:43.041043 arm64_za-ptrace_Get_and_set_data_for_VL_944 skip
13093 12:29:43.041176 arm64_za-ptrace_Set_VL_960 pass
13094 12:29:43.041313 arm64_za-ptrace_Disabled_ZA_for_VL_960 skip
13095 12:29:43.041498 arm64_za-ptrace_Get_and_set_data_for_VL_960 skip
13096 12:29:43.041694 arm64_za-ptrace_Set_VL_976 pass
13097 12:29:43.041832 arm64_za-ptrace_Disabled_ZA_for_VL_976 skip
13098 12:29:43.041947 arm64_za-ptrace_Get_and_set_data_for_VL_976 skip
13099 12:29:43.042062 arm64_za-ptrace_Set_VL_992 pass
13100 12:29:43.042181 arm64_za-ptrace_Disabled_ZA_for_VL_992 skip
13101 12:29:43.042334 arm64_za-ptrace_Get_and_set_data_for_VL_992 skip
13102 12:29:43.042457 arm64_za-ptrace_Set_VL_1008 pass
13103 12:29:43.042573 arm64_za-ptrace_Disabled_ZA_for_VL_1008 skip
13104 12:29:43.046179 arm64_za-ptrace_Get_and_set_data_for_VL_1008 skip
13105 12:29:43.046320 arm64_za-ptrace_Set_VL_1024 pass
13106 12:29:43.046709 arm64_za-ptrace_Disabled_ZA_for_VL_1024 skip
13107 12:29:43.046928 arm64_za-ptrace_Get_and_set_data_for_VL_1024 skip
13108 12:29:43.047097 arm64_za-ptrace_Set_VL_1040 pass
13109 12:29:43.047237 arm64_za-ptrace_Disabled_ZA_for_VL_1040 skip
13110 12:29:43.047457 arm64_za-ptrace_Get_and_set_data_for_VL_1040 skip
13111 12:29:43.047654 arm64_za-ptrace_Set_VL_1056 pass
13112 12:29:43.047804 arm64_za-ptrace_Disabled_ZA_for_VL_1056 skip
13113 12:29:43.047942 arm64_za-ptrace_Get_and_set_data_for_VL_1056 skip
13114 12:29:43.048060 arm64_za-ptrace_Set_VL_1072 pass
13115 12:29:43.048193 arm64_za-ptrace_Disabled_ZA_for_VL_1072 skip
13116 12:29:43.048309 arm64_za-ptrace_Get_and_set_data_for_VL_1072 skip
13117 12:29:43.048425 arm64_za-ptrace_Set_VL_1088 pass
13118 12:29:43.048542 arm64_za-ptrace_Disabled_ZA_for_VL_1088 skip
13119 12:29:43.048657 arm64_za-ptrace_Get_and_set_data_for_VL_1088 skip
13120 12:29:43.048797 arm64_za-ptrace_Set_VL_1104 pass
13121 12:29:43.048922 arm64_za-ptrace_Disabled_ZA_for_VL_1104 skip
13122 12:29:43.049038 arm64_za-ptrace_Get_and_set_data_for_VL_1104 skip
13123 12:29:43.049150 arm64_za-ptrace_Set_VL_1120 pass
13124 12:29:43.049251 arm64_za-ptrace_Disabled_ZA_for_VL_1120 skip
13125 12:29:43.049383 arm64_za-ptrace_Get_and_set_data_for_VL_1120 skip
13126 12:29:43.049504 arm64_za-ptrace_Set_VL_1136 pass
13127 12:29:43.049628 arm64_za-ptrace_Disabled_ZA_for_VL_1136 skip
13128 12:29:43.049827 arm64_za-ptrace_Get_and_set_data_for_VL_1136 skip
13129 12:29:43.049976 arm64_za-ptrace_Set_VL_1152 pass
13130 12:29:43.050115 arm64_za-ptrace_Disabled_ZA_for_VL_1152 skip
13131 12:29:43.050254 arm64_za-ptrace_Get_and_set_data_for_VL_1152 skip
13132 12:29:43.050374 arm64_za-ptrace_Set_VL_1168 pass
13133 12:29:43.054083 arm64_za-ptrace_Disabled_ZA_for_VL_1168 skip
13134 12:29:43.054518 arm64_za-ptrace_Get_and_set_data_for_VL_1168 skip
13135 12:29:43.054668 arm64_za-ptrace_Set_VL_1184 pass
13136 12:29:43.054795 arm64_za-ptrace_Disabled_ZA_for_VL_1184 skip
13137 12:29:43.054927 arm64_za-ptrace_Get_and_set_data_for_VL_1184 skip
13138 12:29:43.055034 arm64_za-ptrace_Set_VL_1200 pass
13139 12:29:43.055159 arm64_za-ptrace_Disabled_ZA_for_VL_1200 skip
13140 12:29:43.055541 arm64_za-ptrace_Get_and_set_data_for_VL_1200 skip
13141 12:29:43.055881 arm64_za-ptrace_Set_VL_1216 pass
13142 12:29:43.056048 arm64_za-ptrace_Disabled_ZA_for_VL_1216 skip
13143 12:29:43.056191 arm64_za-ptrace_Get_and_set_data_for_VL_1216 skip
13144 12:29:43.056332 arm64_za-ptrace_Set_VL_1232 pass
13145 12:29:43.056468 arm64_za-ptrace_Disabled_ZA_for_VL_1232 skip
13146 12:29:43.056639 arm64_za-ptrace_Get_and_set_data_for_VL_1232 skip
13147 12:29:43.056783 arm64_za-ptrace_Set_VL_1248 pass
13148 12:29:43.056959 arm64_za-ptrace_Disabled_ZA_for_VL_1248 skip
13149 12:29:43.057096 arm64_za-ptrace_Get_and_set_data_for_VL_1248 skip
13150 12:29:43.057254 arm64_za-ptrace_Set_VL_1264 pass
13151 12:29:43.057407 arm64_za-ptrace_Disabled_ZA_for_VL_1264 skip
13152 12:29:43.057568 arm64_za-ptrace_Get_and_set_data_for_VL_1264 skip
13153 12:29:43.057740 arm64_za-ptrace_Set_VL_1280 pass
13154 12:29:43.057875 arm64_za-ptrace_Disabled_ZA_for_VL_1280 skip
13155 12:29:43.057991 arm64_za-ptrace_Get_and_set_data_for_VL_1280 skip
13156 12:29:43.058104 arm64_za-ptrace_Set_VL_1296 pass
13157 12:29:43.058198 arm64_za-ptrace_Disabled_ZA_for_VL_1296 skip
13158 12:29:43.058323 arm64_za-ptrace_Get_and_set_data_for_VL_1296 skip
13159 12:29:43.058421 arm64_za-ptrace_Set_VL_1312 pass
13160 12:29:43.058509 arm64_za-ptrace_Disabled_ZA_for_VL_1312 skip
13161 12:29:43.058597 arm64_za-ptrace_Get_and_set_data_for_VL_1312 skip
13162 12:29:43.058690 arm64_za-ptrace_Set_VL_1328 pass
13163 12:29:43.062455 arm64_za-ptrace_Disabled_ZA_for_VL_1328 skip
13164 12:29:43.062691 arm64_za-ptrace_Get_and_set_data_for_VL_1328 skip
13165 12:29:43.062864 arm64_za-ptrace_Set_VL_1344 pass
13166 12:29:43.063030 arm64_za-ptrace_Disabled_ZA_for_VL_1344 skip
13167 12:29:43.063196 arm64_za-ptrace_Get_and_set_data_for_VL_1344 skip
13168 12:29:43.063606 arm64_za-ptrace_Set_VL_1360 pass
13169 12:29:43.063824 arm64_za-ptrace_Disabled_ZA_for_VL_1360 skip
13170 12:29:43.064041 arm64_za-ptrace_Get_and_set_data_for_VL_1360 skip
13171 12:29:43.064242 arm64_za-ptrace_Set_VL_1376 pass
13172 12:29:43.064493 arm64_za-ptrace_Disabled_ZA_for_VL_1376 skip
13173 12:29:43.064771 arm64_za-ptrace_Get_and_set_data_for_VL_1376 skip
13174 12:29:43.065024 arm64_za-ptrace_Set_VL_1392 pass
13175 12:29:43.065218 arm64_za-ptrace_Disabled_ZA_for_VL_1392 skip
13176 12:29:43.065433 arm64_za-ptrace_Get_and_set_data_for_VL_1392 skip
13177 12:29:43.065591 arm64_za-ptrace_Set_VL_1408 pass
13178 12:29:43.066077 arm64_za-ptrace_Disabled_ZA_for_VL_1408 skip
13179 12:29:43.066210 arm64_za-ptrace_Get_and_set_data_for_VL_1408 skip
13180 12:29:43.066328 arm64_za-ptrace_Set_VL_1424 pass
13181 12:29:43.066445 arm64_za-ptrace_Disabled_ZA_for_VL_1424 skip
13182 12:29:43.066561 arm64_za-ptrace_Get_and_set_data_for_VL_1424 skip
13183 12:29:43.066678 arm64_za-ptrace_Set_VL_1440 pass
13184 12:29:43.066795 arm64_za-ptrace_Disabled_ZA_for_VL_1440 skip
13185 12:29:43.066910 arm64_za-ptrace_Get_and_set_data_for_VL_1440 skip
13186 12:29:43.067032 arm64_za-ptrace_Set_VL_1456 pass
13187 12:29:43.067147 arm64_za-ptrace_Disabled_ZA_for_VL_1456 skip
13188 12:29:43.067262 arm64_za-ptrace_Get_and_set_data_for_VL_1456 skip
13189 12:29:43.067378 arm64_za-ptrace_Set_VL_1472 pass
13190 12:29:43.067492 arm64_za-ptrace_Disabled_ZA_for_VL_1472 skip
13191 12:29:43.067607 arm64_za-ptrace_Get_and_set_data_for_VL_1472 skip
13192 12:29:43.067723 arm64_za-ptrace_Set_VL_1488 pass
13193 12:29:43.067866 arm64_za-ptrace_Disabled_ZA_for_VL_1488 skip
13194 12:29:43.067991 arm64_za-ptrace_Get_and_set_data_for_VL_1488 skip
13195 12:29:43.068108 arm64_za-ptrace_Set_VL_1504 pass
13196 12:29:43.068226 arm64_za-ptrace_Disabled_ZA_for_VL_1504 skip
13197 12:29:43.072177 arm64_za-ptrace_Get_and_set_data_for_VL_1504 skip
13198 12:29:43.072391 arm64_za-ptrace_Set_VL_1520 pass
13199 12:29:43.072545 arm64_za-ptrace_Disabled_ZA_for_VL_1520 skip
13200 12:29:43.072726 arm64_za-ptrace_Get_and_set_data_for_VL_1520 skip
13201 12:29:43.072867 arm64_za-ptrace_Set_VL_1536 pass
13202 12:29:43.072984 arm64_za-ptrace_Disabled_ZA_for_VL_1536 skip
13203 12:29:43.089615 arm64_za-ptrace_Get_and_set_data_for_VL_1536 skip
13204 12:29:43.089873 arm64_za-ptrace_Set_VL_1552 pass
13205 12:29:43.090185 arm64_za-ptrace_Disabled_ZA_for_VL_1552 skip
13206 12:29:43.090291 arm64_za-ptrace_Get_and_set_data_for_VL_1552 skip
13207 12:29:43.090382 arm64_za-ptrace_Set_VL_1568 pass
13208 12:29:43.090721 arm64_za-ptrace_Disabled_ZA_for_VL_1568 skip
13209 12:29:43.090843 arm64_za-ptrace_Get_and_set_data_for_VL_1568 skip
13210 12:29:43.090960 arm64_za-ptrace_Set_VL_1584 pass
13211 12:29:43.091044 arm64_za-ptrace_Disabled_ZA_for_VL_1584 skip
13212 12:29:43.091117 arm64_za-ptrace_Get_and_set_data_for_VL_1584 skip
13213 12:29:43.091190 arm64_za-ptrace_Set_VL_1600 pass
13214 12:29:43.091278 arm64_za-ptrace_Disabled_ZA_for_VL_1600 skip
13215 12:29:43.091353 arm64_za-ptrace_Get_and_set_data_for_VL_1600 skip
13216 12:29:43.091426 arm64_za-ptrace_Set_VL_1616 pass
13217 12:29:43.091499 arm64_za-ptrace_Disabled_ZA_for_VL_1616 skip
13218 12:29:43.091583 arm64_za-ptrace_Get_and_set_data_for_VL_1616 skip
13219 12:29:43.091657 arm64_za-ptrace_Set_VL_1632 pass
13220 12:29:43.091741 arm64_za-ptrace_Disabled_ZA_for_VL_1632 skip
13221 12:29:43.092003 arm64_za-ptrace_Get_and_set_data_for_VL_1632 skip
13222 12:29:43.092082 arm64_za-ptrace_Set_VL_1648 pass
13223 12:29:43.092153 arm64_za-ptrace_Disabled_ZA_for_VL_1648 skip
13224 12:29:43.092235 arm64_za-ptrace_Get_and_set_data_for_VL_1648 skip
13225 12:29:43.092322 arm64_za-ptrace_Set_VL_1664 pass
13226 12:29:43.092583 arm64_za-ptrace_Disabled_ZA_for_VL_1664 skip
13227 12:29:43.092662 arm64_za-ptrace_Get_and_set_data_for_VL_1664 skip
13228 12:29:43.092740 arm64_za-ptrace_Set_VL_1680 pass
13229 12:29:43.092832 arm64_za-ptrace_Disabled_ZA_for_VL_1680 skip
13230 12:29:43.092923 arm64_za-ptrace_Get_and_set_data_for_VL_1680 skip
13231 12:29:43.093012 arm64_za-ptrace_Set_VL_1696 pass
13232 12:29:43.093099 arm64_za-ptrace_Disabled_ZA_for_VL_1696 skip
13233 12:29:43.093359 arm64_za-ptrace_Get_and_set_data_for_VL_1696 skip
13234 12:29:43.093437 arm64_za-ptrace_Set_VL_1712 pass
13235 12:29:43.093520 arm64_za-ptrace_Disabled_ZA_for_VL_1712 skip
13236 12:29:43.093596 arm64_za-ptrace_Get_and_set_data_for_VL_1712 skip
13237 12:29:43.093687 arm64_za-ptrace_Set_VL_1728 pass
13238 12:29:43.093952 arm64_za-ptrace_Disabled_ZA_for_VL_1728 skip
13239 12:29:43.094044 arm64_za-ptrace_Get_and_set_data_for_VL_1728 skip
13240 12:29:43.098256 arm64_za-ptrace_Set_VL_1744 pass
13241 12:29:43.098643 arm64_za-ptrace_Disabled_ZA_for_VL_1744 skip
13242 12:29:43.098736 arm64_za-ptrace_Get_and_set_data_for_VL_1744 skip
13243 12:29:43.098829 arm64_za-ptrace_Set_VL_1760 pass
13244 12:29:43.098952 arm64_za-ptrace_Disabled_ZA_for_VL_1760 skip
13245 12:29:43.099037 arm64_za-ptrace_Get_and_set_data_for_VL_1760 skip
13246 12:29:43.099141 arm64_za-ptrace_Set_VL_1776 pass
13247 12:29:43.099398 arm64_za-ptrace_Disabled_ZA_for_VL_1776 skip
13248 12:29:43.099488 arm64_za-ptrace_Get_and_set_data_for_VL_1776 skip
13249 12:29:43.099595 arm64_za-ptrace_Set_VL_1792 pass
13250 12:29:43.099669 arm64_za-ptrace_Disabled_ZA_for_VL_1792 skip
13251 12:29:43.099761 arm64_za-ptrace_Get_and_set_data_for_VL_1792 skip
13252 12:29:43.099833 arm64_za-ptrace_Set_VL_1808 pass
13253 12:29:43.099921 arm64_za-ptrace_Disabled_ZA_for_VL_1808 skip
13254 12:29:43.100008 arm64_za-ptrace_Get_and_set_data_for_VL_1808 skip
13255 12:29:43.100079 arm64_za-ptrace_Set_VL_1824 pass
13256 12:29:43.100349 arm64_za-ptrace_Disabled_ZA_for_VL_1824 skip
13257 12:29:43.100420 arm64_za-ptrace_Get_and_set_data_for_VL_1824 skip
13258 12:29:43.100511 arm64_za-ptrace_Set_VL_1840 pass
13259 12:29:43.100583 arm64_za-ptrace_Disabled_ZA_for_VL_1840 skip
13260 12:29:43.100672 arm64_za-ptrace_Get_and_set_data_for_VL_1840 skip
13261 12:29:43.100926 arm64_za-ptrace_Set_VL_1856 pass
13262 12:29:43.100998 arm64_za-ptrace_Disabled_ZA_for_VL_1856 skip
13263 12:29:43.101088 arm64_za-ptrace_Get_and_set_data_for_VL_1856 skip
13264 12:29:43.101160 arm64_za-ptrace_Set_VL_1872 pass
13265 12:29:43.101255 arm64_za-ptrace_Disabled_ZA_for_VL_1872 skip
13266 12:29:43.101518 arm64_za-ptrace_Get_and_set_data_for_VL_1872 skip
13267 12:29:43.101589 arm64_za-ptrace_Set_VL_1888 pass
13268 12:29:43.101690 arm64_za-ptrace_Disabled_ZA_for_VL_1888 skip
13269 12:29:43.101778 arm64_za-ptrace_Get_and_set_data_for_VL_1888 skip
13270 12:29:43.102032 arm64_za-ptrace_Set_VL_1904 pass
13271 12:29:43.106298 arm64_za-ptrace_Disabled_ZA_for_VL_1904 skip
13272 12:29:43.106669 arm64_za-ptrace_Get_and_set_data_for_VL_1904 skip
13273 12:29:43.106749 arm64_za-ptrace_Set_VL_1920 pass
13274 12:29:43.106843 arm64_za-ptrace_Disabled_ZA_for_VL_1920 skip
13275 12:29:43.106941 arm64_za-ptrace_Get_and_set_data_for_VL_1920 skip
13276 12:29:43.107031 arm64_za-ptrace_Set_VL_1936 pass
13277 12:29:43.107121 arm64_za-ptrace_Disabled_ZA_for_VL_1936 skip
13278 12:29:43.107217 arm64_za-ptrace_Get_and_set_data_for_VL_1936 skip
13279 12:29:43.107300 arm64_za-ptrace_Set_VL_1952 pass
13280 12:29:43.107522 arm64_za-ptrace_Disabled_ZA_for_VL_1952 skip
13281 12:29:43.107714 arm64_za-ptrace_Get_and_set_data_for_VL_1952 skip
13282 12:29:43.107859 arm64_za-ptrace_Set_VL_1968 pass
13283 12:29:43.108045 arm64_za-ptrace_Disabled_ZA_for_VL_1968 skip
13284 12:29:43.108229 arm64_za-ptrace_Get_and_set_data_for_VL_1968 skip
13285 12:29:43.108388 arm64_za-ptrace_Set_VL_1984 pass
13286 12:29:43.108558 arm64_za-ptrace_Disabled_ZA_for_VL_1984 skip
13287 12:29:43.108741 arm64_za-ptrace_Get_and_set_data_for_VL_1984 skip
13288 12:29:43.108915 arm64_za-ptrace_Set_VL_2000 pass
13289 12:29:43.109087 arm64_za-ptrace_Disabled_ZA_for_VL_2000 skip
13290 12:29:43.109231 arm64_za-ptrace_Get_and_set_data_for_VL_2000 skip
13291 12:29:43.109418 arm64_za-ptrace_Set_VL_2016 pass
13292 12:29:43.109628 arm64_za-ptrace_Disabled_ZA_for_VL_2016 skip
13293 12:29:43.109847 arm64_za-ptrace_Get_and_set_data_for_VL_2016 skip
13294 12:29:43.109995 arm64_za-ptrace_Set_VL_2032 pass
13295 12:29:43.110112 arm64_za-ptrace_Disabled_ZA_for_VL_2032 skip
13296 12:29:43.110226 arm64_za-ptrace_Get_and_set_data_for_VL_2032 skip
13297 12:29:43.110365 arm64_za-ptrace_Set_VL_2048 pass
13298 12:29:43.110506 arm64_za-ptrace_Disabled_ZA_for_VL_2048 skip
13299 12:29:43.110647 arm64_za-ptrace_Get_and_set_data_for_VL_2048 skip
13300 12:29:43.110785 arm64_za-ptrace_Set_VL_2064 pass
13301 12:29:43.114140 arm64_za-ptrace_Disabled_ZA_for_VL_2064 skip
13302 12:29:43.114525 arm64_za-ptrace_Get_and_set_data_for_VL_2064 skip
13303 12:29:43.114627 arm64_za-ptrace_Set_VL_2080 pass
13304 12:29:43.114707 arm64_za-ptrace_Disabled_ZA_for_VL_2080 skip
13305 12:29:43.114796 arm64_za-ptrace_Get_and_set_data_for_VL_2080 skip
13306 12:29:43.115048 arm64_za-ptrace_Set_VL_2096 pass
13307 12:29:43.115151 arm64_za-ptrace_Disabled_ZA_for_VL_2096 skip
13308 12:29:43.115227 arm64_za-ptrace_Get_and_set_data_for_VL_2096 skip
13309 12:29:43.115312 arm64_za-ptrace_Set_VL_2112 pass
13310 12:29:43.115398 arm64_za-ptrace_Disabled_ZA_for_VL_2112 skip
13311 12:29:43.115755 arm64_za-ptrace_Get_and_set_data_for_VL_2112 skip
13312 12:29:43.115853 arm64_za-ptrace_Set_VL_2128 pass
13313 12:29:43.115929 arm64_za-ptrace_Disabled_ZA_for_VL_2128 skip
13314 12:29:43.116014 arm64_za-ptrace_Get_and_set_data_for_VL_2128 skip
13315 12:29:43.116100 arm64_za-ptrace_Set_VL_2144 pass
13316 12:29:43.116181 arm64_za-ptrace_Disabled_ZA_for_VL_2144 skip
13317 12:29:43.116576 arm64_za-ptrace_Get_and_set_data_for_VL_2144 skip
13318 12:29:43.116683 arm64_za-ptrace_Set_VL_2160 pass
13319 12:29:43.116771 arm64_za-ptrace_Disabled_ZA_for_VL_2160 skip
13320 12:29:43.117074 arm64_za-ptrace_Get_and_set_data_for_VL_2160 skip
13321 12:29:43.117356 arm64_za-ptrace_Set_VL_2176 pass
13322 12:29:43.117467 arm64_za-ptrace_Disabled_ZA_for_VL_2176 skip
13323 12:29:43.117554 arm64_za-ptrace_Get_and_set_data_for_VL_2176 skip
13324 12:29:43.117640 arm64_za-ptrace_Set_VL_2192 pass
13325 12:29:43.117735 arm64_za-ptrace_Disabled_ZA_for_VL_2192 skip
13326 12:29:43.117835 arm64_za-ptrace_Get_and_set_data_for_VL_2192 skip
13327 12:29:43.117921 arm64_za-ptrace_Set_VL_2208 pass
13328 12:29:43.118005 arm64_za-ptrace_Disabled_ZA_for_VL_2208 skip
13329 12:29:43.122778 arm64_za-ptrace_Get_and_set_data_for_VL_2208 skip
13330 12:29:43.123452 arm64_za-ptrace_Set_VL_2224 pass
13331 12:29:43.123650 arm64_za-ptrace_Disabled_ZA_for_VL_2224 skip
13332 12:29:43.124485 arm64_za-ptrace_Get_and_set_data_for_VL_2224 skip
13333 12:29:43.124583 arm64_za-ptrace_Set_VL_2240 pass
13334 12:29:43.124667 arm64_za-ptrace_Disabled_ZA_for_VL_2240 skip
13335 12:29:43.124749 arm64_za-ptrace_Get_and_set_data_for_VL_2240 skip
13336 12:29:43.124826 arm64_za-ptrace_Set_VL_2256 pass
13337 12:29:43.124902 arm64_za-ptrace_Disabled_ZA_for_VL_2256 skip
13338 12:29:43.124982 arm64_za-ptrace_Get_and_set_data_for_VL_2256 skip
13339 12:29:43.125058 arm64_za-ptrace_Set_VL_2272 pass
13340 12:29:43.125129 arm64_za-ptrace_Disabled_ZA_for_VL_2272 skip
13341 12:29:43.125205 arm64_za-ptrace_Get_and_set_data_for_VL_2272 skip
13342 12:29:43.125282 arm64_za-ptrace_Set_VL_2288 pass
13343 12:29:43.125364 arm64_za-ptrace_Disabled_ZA_for_VL_2288 skip
13344 12:29:43.125441 arm64_za-ptrace_Get_and_set_data_for_VL_2288 skip
13345 12:29:43.125512 arm64_za-ptrace_Set_VL_2304 pass
13346 12:29:43.125586 arm64_za-ptrace_Disabled_ZA_for_VL_2304 skip
13347 12:29:43.125689 arm64_za-ptrace_Get_and_set_data_for_VL_2304 skip
13348 12:29:43.125769 arm64_za-ptrace_Set_VL_2320 pass
13349 12:29:43.125845 arm64_za-ptrace_Disabled_ZA_for_VL_2320 skip
13350 12:29:43.125920 arm64_za-ptrace_Get_and_set_data_for_VL_2320 skip
13351 12:29:43.126234 arm64_za-ptrace_Set_VL_2336 pass
13352 12:29:43.126333 arm64_za-ptrace_Disabled_ZA_for_VL_2336 skip
13353 12:29:43.126412 arm64_za-ptrace_Get_and_set_data_for_VL_2336 skip
13354 12:29:43.126488 arm64_za-ptrace_Set_VL_2352 pass
13355 12:29:43.126562 arm64_za-ptrace_Disabled_ZA_for_VL_2352 skip
13356 12:29:43.126637 arm64_za-ptrace_Get_and_set_data_for_VL_2352 skip
13357 12:29:43.130227 arm64_za-ptrace_Set_VL_2368 pass
13358 12:29:43.130371 arm64_za-ptrace_Disabled_ZA_for_VL_2368 skip
13359 12:29:43.130918 arm64_za-ptrace_Get_and_set_data_for_VL_2368 skip
13360 12:29:43.131011 arm64_za-ptrace_Set_VL_2384 pass
13361 12:29:43.131086 arm64_za-ptrace_Disabled_ZA_for_VL_2384 skip
13362 12:29:43.131159 arm64_za-ptrace_Get_and_set_data_for_VL_2384 skip
13363 12:29:43.131230 arm64_za-ptrace_Set_VL_2400 pass
13364 12:29:43.131318 arm64_za-ptrace_Disabled_ZA_for_VL_2400 skip
13365 12:29:43.131391 arm64_za-ptrace_Get_and_set_data_for_VL_2400 skip
13366 12:29:43.131463 arm64_za-ptrace_Set_VL_2416 pass
13367 12:29:43.131546 arm64_za-ptrace_Disabled_ZA_for_VL_2416 skip
13368 12:29:43.131623 arm64_za-ptrace_Get_and_set_data_for_VL_2416 skip
13369 12:29:43.131706 arm64_za-ptrace_Set_VL_2432 pass
13370 12:29:43.131789 arm64_za-ptrace_Disabled_ZA_for_VL_2432 skip
13371 12:29:43.134158 arm64_za-ptrace_Get_and_set_data_for_VL_2432 skip
13372 12:29:43.134310 arm64_za-ptrace_Set_VL_2448 pass
13373 12:29:43.134407 arm64_za-ptrace_Disabled_ZA_for_VL_2448 skip
13374 12:29:43.134494 arm64_za-ptrace_Get_and_set_data_for_VL_2448 skip
13375 12:29:43.134580 arm64_za-ptrace_Set_VL_2464 pass
13376 12:29:43.134666 arm64_za-ptrace_Disabled_ZA_for_VL_2464 skip
13377 12:29:43.134751 arm64_za-ptrace_Get_and_set_data_for_VL_2464 skip
13378 12:29:43.134837 arm64_za-ptrace_Set_VL_2480 pass
13379 12:29:43.134921 arm64_za-ptrace_Disabled_ZA_for_VL_2480 skip
13380 12:29:43.134998 arm64_za-ptrace_Get_and_set_data_for_VL_2480 skip
13381 12:29:43.135073 arm64_za-ptrace_Set_VL_2496 pass
13382 12:29:43.135146 arm64_za-ptrace_Disabled_ZA_for_VL_2496 skip
13383 12:29:43.135219 arm64_za-ptrace_Get_and_set_data_for_VL_2496 skip
13384 12:29:43.135291 arm64_za-ptrace_Set_VL_2512 pass
13385 12:29:43.135369 arm64_za-ptrace_Disabled_ZA_for_VL_2512 skip
13386 12:29:43.135447 arm64_za-ptrace_Get_and_set_data_for_VL_2512 skip
13387 12:29:43.135521 arm64_za-ptrace_Set_VL_2528 pass
13388 12:29:43.138141 arm64_za-ptrace_Disabled_ZA_for_VL_2528 skip
13389 12:29:43.138261 arm64_za-ptrace_Get_and_set_data_for_VL_2528 skip
13390 12:29:43.138567 arm64_za-ptrace_Set_VL_2544 pass
13391 12:29:43.138673 arm64_za-ptrace_Disabled_ZA_for_VL_2544 skip
13392 12:29:43.138762 arm64_za-ptrace_Get_and_set_data_for_VL_2544 skip
13393 12:29:43.138848 arm64_za-ptrace_Set_VL_2560 pass
13394 12:29:43.138942 arm64_za-ptrace_Disabled_ZA_for_VL_2560 skip
13395 12:29:43.139365 arm64_za-ptrace_Get_and_set_data_for_VL_2560 skip
13396 12:29:43.163362 arm64_za-ptrace_Set_VL_2576 pass
13397 12:29:43.163822 arm64_za-ptrace_Disabled_ZA_for_VL_2576 skip
13398 12:29:43.163940 arm64_za-ptrace_Get_and_set_data_for_VL_2576 skip
13399 12:29:43.164037 arm64_za-ptrace_Set_VL_2592 pass
13400 12:29:43.164126 arm64_za-ptrace_Disabled_ZA_for_VL_2592 skip
13401 12:29:43.164230 arm64_za-ptrace_Get_and_set_data_for_VL_2592 skip
13402 12:29:43.164321 arm64_za-ptrace_Set_VL_2608 pass
13403 12:29:43.164414 arm64_za-ptrace_Disabled_ZA_for_VL_2608 skip
13404 12:29:43.164520 arm64_za-ptrace_Get_and_set_data_for_VL_2608 skip
13405 12:29:43.164613 arm64_za-ptrace_Set_VL_2624 pass
13406 12:29:43.164699 arm64_za-ptrace_Disabled_ZA_for_VL_2624 skip
13407 12:29:43.164786 arm64_za-ptrace_Get_and_set_data_for_VL_2624 skip
13408 12:29:43.164890 arm64_za-ptrace_Set_VL_2640 pass
13409 12:29:43.164980 arm64_za-ptrace_Disabled_ZA_for_VL_2640 skip
13410 12:29:43.165070 arm64_za-ptrace_Get_and_set_data_for_VL_2640 skip
13411 12:29:43.165159 arm64_za-ptrace_Set_VL_2656 pass
13412 12:29:43.165263 arm64_za-ptrace_Disabled_ZA_for_VL_2656 skip
13413 12:29:43.165354 arm64_za-ptrace_Get_and_set_data_for_VL_2656 skip
13414 12:29:43.165445 arm64_za-ptrace_Set_VL_2672 pass
13415 12:29:43.165533 arm64_za-ptrace_Disabled_ZA_for_VL_2672 skip
13416 12:29:43.165639 arm64_za-ptrace_Get_and_set_data_for_VL_2672 skip
13417 12:29:43.165740 arm64_za-ptrace_Set_VL_2688 pass
13418 12:29:43.165828 arm64_za-ptrace_Disabled_ZA_for_VL_2688 skip
13419 12:29:43.165914 arm64_za-ptrace_Get_and_set_data_for_VL_2688 skip
13420 12:29:43.166003 arm64_za-ptrace_Set_VL_2704 pass
13421 12:29:43.166105 arm64_za-ptrace_Disabled_ZA_for_VL_2704 skip
13422 12:29:43.166193 arm64_za-ptrace_Get_and_set_data_for_VL_2704 skip
13423 12:29:43.166282 arm64_za-ptrace_Set_VL_2720 pass
13424 12:29:43.166387 arm64_za-ptrace_Disabled_ZA_for_VL_2720 skip
13425 12:29:43.166477 arm64_za-ptrace_Get_and_set_data_for_VL_2720 skip
13426 12:29:43.166580 arm64_za-ptrace_Set_VL_2736 pass
13427 12:29:43.166669 arm64_za-ptrace_Disabled_ZA_for_VL_2736 skip
13428 12:29:43.166775 arm64_za-ptrace_Get_and_set_data_for_VL_2736 skip
13429 12:29:43.166864 arm64_za-ptrace_Set_VL_2752 pass
13430 12:29:43.166948 arm64_za-ptrace_Disabled_ZA_for_VL_2752 skip
13431 12:29:43.167051 arm64_za-ptrace_Get_and_set_data_for_VL_2752 skip
13432 12:29:43.167140 arm64_za-ptrace_Set_VL_2768 pass
13433 12:29:43.167244 arm64_za-ptrace_Disabled_ZA_for_VL_2768 skip
13434 12:29:43.167335 arm64_za-ptrace_Get_and_set_data_for_VL_2768 skip
13435 12:29:43.167443 arm64_za-ptrace_Set_VL_2784 pass
13436 12:29:43.167546 arm64_za-ptrace_Disabled_ZA_for_VL_2784 skip
13437 12:29:43.167843 arm64_za-ptrace_Get_and_set_data_for_VL_2784 skip
13438 12:29:43.167933 arm64_za-ptrace_Set_VL_2800 pass
13439 12:29:43.168038 arm64_za-ptrace_Disabled_ZA_for_VL_2800 skip
13440 12:29:43.168144 arm64_za-ptrace_Get_and_set_data_for_VL_2800 skip
13441 12:29:43.168233 arm64_za-ptrace_Set_VL_2816 pass
13442 12:29:43.168303 arm64_za-ptrace_Disabled_ZA_for_VL_2816 skip
13443 12:29:43.168368 arm64_za-ptrace_Get_and_set_data_for_VL_2816 skip
13444 12:29:43.168450 arm64_za-ptrace_Set_VL_2832 pass
13445 12:29:43.168542 arm64_za-ptrace_Disabled_ZA_for_VL_2832 skip
13446 12:29:43.168643 arm64_za-ptrace_Get_and_set_data_for_VL_2832 skip
13447 12:29:43.168724 arm64_za-ptrace_Set_VL_2848 pass
13448 12:29:43.168798 arm64_za-ptrace_Disabled_ZA_for_VL_2848 skip
13449 12:29:43.169055 arm64_za-ptrace_Get_and_set_data_for_VL_2848 skip
13450 12:29:43.169139 arm64_za-ptrace_Set_VL_2864 pass
13451 12:29:43.169218 arm64_za-ptrace_Disabled_ZA_for_VL_2864 skip
13452 12:29:43.169295 arm64_za-ptrace_Get_and_set_data_for_VL_2864 skip
13453 12:29:43.169387 arm64_za-ptrace_Set_VL_2880 pass
13454 12:29:43.169689 arm64_za-ptrace_Disabled_ZA_for_VL_2880 skip
13455 12:29:43.169798 arm64_za-ptrace_Get_and_set_data_for_VL_2880 skip
13456 12:29:43.169882 arm64_za-ptrace_Set_VL_2896 pass
13457 12:29:43.178195 arm64_za-ptrace_Disabled_ZA_for_VL_2896 skip
13458 12:29:43.178636 arm64_za-ptrace_Get_and_set_data_for_VL_2896 skip
13459 12:29:43.178720 arm64_za-ptrace_Set_VL_2912 pass
13460 12:29:43.178804 arm64_za-ptrace_Disabled_ZA_for_VL_2912 skip
13461 12:29:43.178888 arm64_za-ptrace_Get_and_set_data_for_VL_2912 skip
13462 12:29:43.178996 arm64_za-ptrace_Set_VL_2928 pass
13463 12:29:43.179104 arm64_za-ptrace_Disabled_ZA_for_VL_2928 skip
13464 12:29:43.179205 arm64_za-ptrace_Get_and_set_data_for_VL_2928 skip
13465 12:29:43.179278 arm64_za-ptrace_Set_VL_2944 pass
13466 12:29:43.179357 arm64_za-ptrace_Disabled_ZA_for_VL_2944 skip
13467 12:29:43.179433 arm64_za-ptrace_Get_and_set_data_for_VL_2944 skip
13468 12:29:43.179507 arm64_za-ptrace_Set_VL_2960 pass
13469 12:29:43.179621 arm64_za-ptrace_Disabled_ZA_for_VL_2960 skip
13470 12:29:43.179716 arm64_za-ptrace_Get_and_set_data_for_VL_2960 skip
13471 12:29:43.179805 arm64_za-ptrace_Set_VL_2976 pass
13472 12:29:43.179873 arm64_za-ptrace_Disabled_ZA_for_VL_2976 skip
13473 12:29:43.179950 arm64_za-ptrace_Get_and_set_data_for_VL_2976 skip
13474 12:29:43.180074 arm64_za-ptrace_Set_VL_2992 pass
13475 12:29:43.180180 arm64_za-ptrace_Disabled_ZA_for_VL_2992 skip
13476 12:29:43.180305 arm64_za-ptrace_Get_and_set_data_for_VL_2992 skip
13477 12:29:43.180426 arm64_za-ptrace_Set_VL_3008 pass
13478 12:29:43.180586 arm64_za-ptrace_Disabled_ZA_for_VL_3008 skip
13479 12:29:43.180900 arm64_za-ptrace_Get_and_set_data_for_VL_3008 skip
13480 12:29:43.181013 arm64_za-ptrace_Set_VL_3024 pass
13481 12:29:43.181111 arm64_za-ptrace_Disabled_ZA_for_VL_3024 skip
13482 12:29:43.181203 arm64_za-ptrace_Get_and_set_data_for_VL_3024 skip
13483 12:29:43.181293 arm64_za-ptrace_Set_VL_3040 pass
13484 12:29:43.181400 arm64_za-ptrace_Disabled_ZA_for_VL_3040 skip
13485 12:29:43.181493 arm64_za-ptrace_Get_and_set_data_for_VL_3040 skip
13486 12:29:43.181587 arm64_za-ptrace_Set_VL_3056 pass
13487 12:29:43.181705 arm64_za-ptrace_Disabled_ZA_for_VL_3056 skip
13488 12:29:43.181797 arm64_za-ptrace_Get_and_set_data_for_VL_3056 skip
13489 12:29:43.181886 arm64_za-ptrace_Set_VL_3072 pass
13490 12:29:43.181992 arm64_za-ptrace_Disabled_ZA_for_VL_3072 skip
13491 12:29:43.182082 arm64_za-ptrace_Get_and_set_data_for_VL_3072 skip
13492 12:29:43.186129 arm64_za-ptrace_Set_VL_3088 pass
13493 12:29:43.186511 arm64_za-ptrace_Disabled_ZA_for_VL_3088 skip
13494 12:29:43.186614 arm64_za-ptrace_Get_and_set_data_for_VL_3088 skip
13495 12:29:43.186706 arm64_za-ptrace_Set_VL_3104 pass
13496 12:29:43.186812 arm64_za-ptrace_Disabled_ZA_for_VL_3104 skip
13497 12:29:43.186907 arm64_za-ptrace_Get_and_set_data_for_VL_3104 skip
13498 12:29:43.187015 arm64_za-ptrace_Set_VL_3120 pass
13499 12:29:43.187123 arm64_za-ptrace_Disabled_ZA_for_VL_3120 skip
13500 12:29:43.187214 arm64_za-ptrace_Get_and_set_data_for_VL_3120 skip
13501 12:29:43.187520 arm64_za-ptrace_Set_VL_3136 pass
13502 12:29:43.187627 arm64_za-ptrace_Disabled_ZA_for_VL_3136 skip
13503 12:29:43.187719 arm64_za-ptrace_Get_and_set_data_for_VL_3136 skip
13504 12:29:43.187808 arm64_za-ptrace_Set_VL_3152 pass
13505 12:29:43.187916 arm64_za-ptrace_Disabled_ZA_for_VL_3152 skip
13506 12:29:43.188011 arm64_za-ptrace_Get_and_set_data_for_VL_3152 skip
13507 12:29:43.188101 arm64_za-ptrace_Set_VL_3168 pass
13508 12:29:43.188188 arm64_za-ptrace_Disabled_ZA_for_VL_3168 skip
13509 12:29:43.188295 arm64_za-ptrace_Get_and_set_data_for_VL_3168 skip
13510 12:29:43.188387 arm64_za-ptrace_Set_VL_3184 pass
13511 12:29:43.188478 arm64_za-ptrace_Disabled_ZA_for_VL_3184 skip
13512 12:29:43.188584 arm64_za-ptrace_Get_and_set_data_for_VL_3184 skip
13513 12:29:43.188676 arm64_za-ptrace_Set_VL_3200 pass
13514 12:29:43.188764 arm64_za-ptrace_Disabled_ZA_for_VL_3200 skip
13515 12:29:43.188869 arm64_za-ptrace_Get_and_set_data_for_VL_3200 skip
13516 12:29:43.188963 arm64_za-ptrace_Set_VL_3216 pass
13517 12:29:43.189071 arm64_za-ptrace_Disabled_ZA_for_VL_3216 skip
13518 12:29:43.189163 arm64_za-ptrace_Get_and_set_data_for_VL_3216 skip
13519 12:29:43.189269 arm64_za-ptrace_Set_VL_3232 pass
13520 12:29:43.189374 arm64_za-ptrace_Disabled_ZA_for_VL_3232 skip
13521 12:29:43.190217 arm64_za-ptrace_Get_and_set_data_for_VL_3232 skip
13522 12:29:43.190320 arm64_za-ptrace_Set_VL_3248 pass
13523 12:29:43.190414 arm64_za-ptrace_Disabled_ZA_for_VL_3248 skip
13524 12:29:43.190506 arm64_za-ptrace_Get_and_set_data_for_VL_3248 skip
13525 12:29:43.194142 arm64_za-ptrace_Set_VL_3264 pass
13526 12:29:43.194540 arm64_za-ptrace_Disabled_ZA_for_VL_3264 skip
13527 12:29:43.194624 arm64_za-ptrace_Get_and_set_data_for_VL_3264 skip
13528 12:29:43.194721 arm64_za-ptrace_Set_VL_3280 pass
13529 12:29:43.194795 arm64_za-ptrace_Disabled_ZA_for_VL_3280 skip
13530 12:29:43.194898 arm64_za-ptrace_Get_and_set_data_for_VL_3280 skip
13531 12:29:43.194976 arm64_za-ptrace_Set_VL_3296 pass
13532 12:29:43.195075 arm64_za-ptrace_Disabled_ZA_for_VL_3296 skip
13533 12:29:43.195160 arm64_za-ptrace_Get_and_set_data_for_VL_3296 skip
13534 12:29:43.195229 arm64_za-ptrace_Set_VL_3312 pass
13535 12:29:43.195306 arm64_za-ptrace_Disabled_ZA_for_VL_3312 skip
13536 12:29:43.195566 arm64_za-ptrace_Get_and_set_data_for_VL_3312 skip
13537 12:29:43.195661 arm64_za-ptrace_Set_VL_3328 pass
13538 12:29:43.195741 arm64_za-ptrace_Disabled_ZA_for_VL_3328 skip
13539 12:29:43.195807 arm64_za-ptrace_Get_and_set_data_for_VL_3328 skip
13540 12:29:43.195911 arm64_za-ptrace_Set_VL_3344 pass
13541 12:29:43.196193 arm64_za-ptrace_Disabled_ZA_for_VL_3344 skip
13542 12:29:43.196304 arm64_za-ptrace_Get_and_set_data_for_VL_3344 skip
13543 12:29:43.196403 arm64_za-ptrace_Set_VL_3360 pass
13544 12:29:43.196481 arm64_za-ptrace_Disabled_ZA_for_VL_3360 skip
13545 12:29:43.196557 arm64_za-ptrace_Get_and_set_data_for_VL_3360 skip
13546 12:29:43.196626 arm64_za-ptrace_Set_VL_3376 pass
13547 12:29:43.196719 arm64_za-ptrace_Disabled_ZA_for_VL_3376 skip
13548 12:29:43.196804 arm64_za-ptrace_Get_and_set_data_for_VL_3376 skip
13549 12:29:43.196871 arm64_za-ptrace_Set_VL_3392 pass
13550 12:29:43.196934 arm64_za-ptrace_Disabled_ZA_for_VL_3392 skip
13551 12:29:43.197009 arm64_za-ptrace_Get_and_set_data_for_VL_3392 skip
13552 12:29:43.197073 arm64_za-ptrace_Set_VL_3408 pass
13553 12:29:43.197148 arm64_za-ptrace_Disabled_ZA_for_VL_3408 skip
13554 12:29:43.197255 arm64_za-ptrace_Get_and_set_data_for_VL_3408 skip
13555 12:29:43.197354 arm64_za-ptrace_Set_VL_3424 pass
13556 12:29:43.197708 arm64_za-ptrace_Disabled_ZA_for_VL_3424 skip
13557 12:29:43.197796 arm64_za-ptrace_Get_and_set_data_for_VL_3424 skip
13558 12:29:43.197889 arm64_za-ptrace_Set_VL_3440 pass
13559 12:29:43.197963 arm64_za-ptrace_Disabled_ZA_for_VL_3440 skip
13560 12:29:43.202243 arm64_za-ptrace_Get_and_set_data_for_VL_3440 skip
13561 12:29:43.202420 arm64_za-ptrace_Set_VL_3456 pass
13562 12:29:43.202720 arm64_za-ptrace_Disabled_ZA_for_VL_3456 skip
13563 12:29:43.202816 arm64_za-ptrace_Get_and_set_data_for_VL_3456 skip
13564 12:29:43.202921 arm64_za-ptrace_Set_VL_3472 pass
13565 12:29:43.203012 arm64_za-ptrace_Disabled_ZA_for_VL_3472 skip
13566 12:29:43.203116 arm64_za-ptrace_Get_and_set_data_for_VL_3472 skip
13567 12:29:43.203217 arm64_za-ptrace_Set_VL_3488 pass
13568 12:29:43.203336 arm64_za-ptrace_Disabled_ZA_for_VL_3488 skip
13569 12:29:43.203428 arm64_za-ptrace_Get_and_set_data_for_VL_3488 skip
13570 12:29:43.203534 arm64_za-ptrace_Set_VL_3504 pass
13571 12:29:43.203648 arm64_za-ptrace_Disabled_ZA_for_VL_3504 skip
13572 12:29:43.203768 arm64_za-ptrace_Get_and_set_data_for_VL_3504 skip
13573 12:29:43.203867 arm64_za-ptrace_Set_VL_3520 pass
13574 12:29:43.203949 arm64_za-ptrace_Disabled_ZA_for_VL_3520 skip
13575 12:29:43.204052 arm64_za-ptrace_Get_and_set_data_for_VL_3520 skip
13576 12:29:43.204139 arm64_za-ptrace_Set_VL_3536 pass
13577 12:29:43.204226 arm64_za-ptrace_Disabled_ZA_for_VL_3536 skip
13578 12:29:43.204329 arm64_za-ptrace_Get_and_set_data_for_VL_3536 skip
13579 12:29:43.204427 arm64_za-ptrace_Set_VL_3552 pass
13580 12:29:43.204510 arm64_za-ptrace_Disabled_ZA_for_VL_3552 skip
13581 12:29:43.204590 arm64_za-ptrace_Get_and_set_data_for_VL_3552 skip
13582 12:29:43.204682 arm64_za-ptrace_Set_VL_3568 pass
13583 12:29:43.204765 arm64_za-ptrace_Disabled_ZA_for_VL_3568 skip
13584 12:29:43.204859 arm64_za-ptrace_Get_and_set_data_for_VL_3568 skip
13585 12:29:43.204940 arm64_za-ptrace_Set_VL_3584 pass
13586 12:29:43.205033 arm64_za-ptrace_Disabled_ZA_for_VL_3584 skip
13587 12:29:43.205127 arm64_za-ptrace_Get_and_set_data_for_VL_3584 skip
13588 12:29:43.235134 arm64_za-ptrace_Set_VL_3600 pass
13589 12:29:43.235372 arm64_za-ptrace_Disabled_ZA_for_VL_3600 skip
13590 12:29:43.235714 arm64_za-ptrace_Get_and_set_data_for_VL_3600 skip
13591 12:29:43.235822 arm64_za-ptrace_Set_VL_3616 pass
13592 12:29:43.235914 arm64_za-ptrace_Disabled_ZA_for_VL_3616 skip
13593 12:29:43.236004 arm64_za-ptrace_Get_and_set_data_for_VL_3616 skip
13594 12:29:43.236094 arm64_za-ptrace_Set_VL_3632 pass
13595 12:29:43.236183 arm64_za-ptrace_Disabled_ZA_for_VL_3632 skip
13596 12:29:43.236269 arm64_za-ptrace_Get_and_set_data_for_VL_3632 skip
13597 12:29:43.236373 arm64_za-ptrace_Set_VL_3648 pass
13598 12:29:43.236463 arm64_za-ptrace_Disabled_ZA_for_VL_3648 skip
13599 12:29:43.236553 arm64_za-ptrace_Get_and_set_data_for_VL_3648 skip
13600 12:29:43.236642 arm64_za-ptrace_Set_VL_3664 pass
13601 12:29:43.236729 arm64_za-ptrace_Disabled_ZA_for_VL_3664 skip
13602 12:29:43.236832 arm64_za-ptrace_Get_and_set_data_for_VL_3664 skip
13603 12:29:43.236922 arm64_za-ptrace_Set_VL_3680 pass
13604 12:29:43.237007 arm64_za-ptrace_Disabled_ZA_for_VL_3680 skip
13605 12:29:43.237112 arm64_za-ptrace_Get_and_set_data_for_VL_3680 skip
13606 12:29:43.237202 arm64_za-ptrace_Set_VL_3696 pass
13607 12:29:43.237288 arm64_za-ptrace_Disabled_ZA_for_VL_3696 skip
13608 12:29:43.237373 arm64_za-ptrace_Get_and_set_data_for_VL_3696 skip
13609 12:29:43.237459 arm64_za-ptrace_Set_VL_3712 pass
13610 12:29:43.237572 arm64_za-ptrace_Disabled_ZA_for_VL_3712 skip
13611 12:29:43.237677 arm64_za-ptrace_Get_and_set_data_for_VL_3712 skip
13612 12:29:43.237765 arm64_za-ptrace_Set_VL_3728 pass
13613 12:29:43.237851 arm64_za-ptrace_Disabled_ZA_for_VL_3728 skip
13614 12:29:43.237938 arm64_za-ptrace_Get_and_set_data_for_VL_3728 skip
13615 12:29:43.238042 arm64_za-ptrace_Set_VL_3744 pass
13616 12:29:43.242658 arm64_za-ptrace_Disabled_ZA_for_VL_3744 skip
13617 12:29:43.243132 arm64_za-ptrace_Get_and_set_data_for_VL_3744 skip
13618 12:29:43.243351 arm64_za-ptrace_Set_VL_3760 pass
13619 12:29:43.243830 arm64_za-ptrace_Disabled_ZA_for_VL_3760 skip
13620 12:29:43.244022 arm64_za-ptrace_Get_and_set_data_for_VL_3760 skip
13621 12:29:43.244207 arm64_za-ptrace_Set_VL_3776 pass
13622 12:29:43.244413 arm64_za-ptrace_Disabled_ZA_for_VL_3776 skip
13623 12:29:43.244620 arm64_za-ptrace_Get_and_set_data_for_VL_3776 skip
13624 12:29:43.244825 arm64_za-ptrace_Set_VL_3792 pass
13625 12:29:43.245007 arm64_za-ptrace_Disabled_ZA_for_VL_3792 skip
13626 12:29:43.245206 arm64_za-ptrace_Get_and_set_data_for_VL_3792 skip
13627 12:29:43.245392 arm64_za-ptrace_Set_VL_3808 pass
13628 12:29:43.245591 arm64_za-ptrace_Disabled_ZA_for_VL_3808 skip
13629 12:29:43.245822 arm64_za-ptrace_Get_and_set_data_for_VL_3808 skip
13630 12:29:43.246000 arm64_za-ptrace_Set_VL_3824 pass
13631 12:29:43.246172 arm64_za-ptrace_Disabled_ZA_for_VL_3824 skip
13632 12:29:43.246298 arm64_za-ptrace_Get_and_set_data_for_VL_3824 skip
13633 12:29:43.246416 arm64_za-ptrace_Set_VL_3840 pass
13634 12:29:43.246534 arm64_za-ptrace_Disabled_ZA_for_VL_3840 skip
13635 12:29:43.246650 arm64_za-ptrace_Get_and_set_data_for_VL_3840 skip
13636 12:29:43.246765 arm64_za-ptrace_Set_VL_3856 pass
13637 12:29:43.246897 arm64_za-ptrace_Disabled_ZA_for_VL_3856 skip
13638 12:29:43.247050 arm64_za-ptrace_Get_and_set_data_for_VL_3856 skip
13639 12:29:43.247170 arm64_za-ptrace_Set_VL_3872 pass
13640 12:29:43.247286 arm64_za-ptrace_Disabled_ZA_for_VL_3872 skip
13641 12:29:43.247401 arm64_za-ptrace_Get_and_set_data_for_VL_3872 skip
13642 12:29:43.247518 arm64_za-ptrace_Set_VL_3888 pass
13643 12:29:43.247635 arm64_za-ptrace_Disabled_ZA_for_VL_3888 skip
13644 12:29:43.247749 arm64_za-ptrace_Get_and_set_data_for_VL_3888 skip
13645 12:29:43.247864 arm64_za-ptrace_Set_VL_3904 pass
13646 12:29:43.247977 arm64_za-ptrace_Disabled_ZA_for_VL_3904 skip
13647 12:29:43.248096 arm64_za-ptrace_Get_and_set_data_for_VL_3904 skip
13648 12:29:43.248211 arm64_za-ptrace_Set_VL_3920 pass
13649 12:29:43.248326 arm64_za-ptrace_Disabled_ZA_for_VL_3920 skip
13650 12:29:43.250364 arm64_za-ptrace_Get_and_set_data_for_VL_3920 skip
13651 12:29:43.250617 arm64_za-ptrace_Set_VL_3936 pass
13652 12:29:43.250792 arm64_za-ptrace_Disabled_ZA_for_VL_3936 skip
13653 12:29:43.251325 arm64_za-ptrace_Get_and_set_data_for_VL_3936 skip
13654 12:29:43.251490 arm64_za-ptrace_Set_VL_3952 pass
13655 12:29:43.251659 arm64_za-ptrace_Disabled_ZA_for_VL_3952 skip
13656 12:29:43.251802 arm64_za-ptrace_Get_and_set_data_for_VL_3952 skip
13657 12:29:43.251919 arm64_za-ptrace_Set_VL_3968 pass
13658 12:29:43.252037 arm64_za-ptrace_Disabled_ZA_for_VL_3968 skip
13659 12:29:43.252166 arm64_za-ptrace_Get_and_set_data_for_VL_3968 skip
13660 12:29:43.252285 arm64_za-ptrace_Set_VL_3984 pass
13661 12:29:43.252431 arm64_za-ptrace_Disabled_ZA_for_VL_3984 skip
13662 12:29:43.252555 arm64_za-ptrace_Get_and_set_data_for_VL_3984 skip
13663 12:29:43.252678 arm64_za-ptrace_Set_VL_4000 pass
13664 12:29:43.252801 arm64_za-ptrace_Disabled_ZA_for_VL_4000 skip
13665 12:29:43.252925 arm64_za-ptrace_Get_and_set_data_for_VL_4000 skip
13666 12:29:43.253043 arm64_za-ptrace_Set_VL_4016 pass
13667 12:29:43.253158 arm64_za-ptrace_Disabled_ZA_for_VL_4016 skip
13668 12:29:43.253284 arm64_za-ptrace_Get_and_set_data_for_VL_4016 skip
13669 12:29:43.253433 arm64_za-ptrace_Set_VL_4032 pass
13670 12:29:43.253564 arm64_za-ptrace_Disabled_ZA_for_VL_4032 skip
13671 12:29:43.253716 arm64_za-ptrace_Get_and_set_data_for_VL_4032 skip
13672 12:29:43.253876 arm64_za-ptrace_Set_VL_4048 pass
13673 12:29:43.253998 arm64_za-ptrace_Disabled_ZA_for_VL_4048 skip
13674 12:29:43.254112 arm64_za-ptrace_Get_and_set_data_for_VL_4048 skip
13675 12:29:43.254225 arm64_za-ptrace_Set_VL_4064 pass
13676 12:29:43.254338 arm64_za-ptrace_Disabled_ZA_for_VL_4064 skip
13677 12:29:43.254452 arm64_za-ptrace_Get_and_set_data_for_VL_4064 skip
13678 12:29:43.254565 arm64_za-ptrace_Set_VL_4080 pass
13679 12:29:43.254680 arm64_za-ptrace_Disabled_ZA_for_VL_4080 skip
13680 12:29:43.254793 arm64_za-ptrace_Get_and_set_data_for_VL_4080 skip
13681 12:29:43.254942 arm64_za-ptrace_Set_VL_4096 pass
13682 12:29:43.255077 arm64_za-ptrace_Disabled_ZA_for_VL_4096 skip
13683 12:29:43.255194 arm64_za-ptrace_Get_and_set_data_for_VL_4096 skip
13684 12:29:43.255338 arm64_za-ptrace_Set_VL_4112 pass
13685 12:29:43.258200 arm64_za-ptrace_Disabled_ZA_for_VL_4112 skip
13686 12:29:43.259070 arm64_za-ptrace_Get_and_set_data_for_VL_4112 skip
13687 12:29:43.259179 arm64_za-ptrace_Set_VL_4128 pass
13688 12:29:43.259272 arm64_za-ptrace_Disabled_ZA_for_VL_4128 skip
13689 12:29:43.259360 arm64_za-ptrace_Get_and_set_data_for_VL_4128 skip
13690 12:29:43.259448 arm64_za-ptrace_Set_VL_4144 pass
13691 12:29:43.259537 arm64_za-ptrace_Disabled_ZA_for_VL_4144 skip
13692 12:29:43.259626 arm64_za-ptrace_Get_and_set_data_for_VL_4144 skip
13693 12:29:43.259715 arm64_za-ptrace_Set_VL_4160 pass
13694 12:29:43.260055 arm64_za-ptrace_Disabled_ZA_for_VL_4160 skip
13695 12:29:43.260159 arm64_za-ptrace_Get_and_set_data_for_VL_4160 skip
13696 12:29:43.260249 arm64_za-ptrace_Set_VL_4176 pass
13697 12:29:43.260337 arm64_za-ptrace_Disabled_ZA_for_VL_4176 skip
13698 12:29:43.260423 arm64_za-ptrace_Get_and_set_data_for_VL_4176 skip
13699 12:29:43.260510 arm64_za-ptrace_Set_VL_4192 pass
13700 12:29:43.260596 arm64_za-ptrace_Disabled_ZA_for_VL_4192 skip
13701 12:29:43.260683 arm64_za-ptrace_Get_and_set_data_for_VL_4192 skip
13702 12:29:43.260774 arm64_za-ptrace_Set_VL_4208 pass
13703 12:29:43.260863 arm64_za-ptrace_Disabled_ZA_for_VL_4208 skip
13704 12:29:43.261179 arm64_za-ptrace_Get_and_set_data_for_VL_4208 skip
13705 12:29:43.261284 arm64_za-ptrace_Set_VL_4224 pass
13706 12:29:43.261375 arm64_za-ptrace_Disabled_ZA_for_VL_4224 skip
13707 12:29:43.261461 arm64_za-ptrace_Get_and_set_data_for_VL_4224 skip
13708 12:29:43.261548 arm64_za-ptrace_Set_VL_4240 pass
13709 12:29:43.261634 arm64_za-ptrace_Disabled_ZA_for_VL_4240 skip
13710 12:29:43.261734 arm64_za-ptrace_Get_and_set_data_for_VL_4240 skip
13711 12:29:43.261821 arm64_za-ptrace_Set_VL_4256 pass
13712 12:29:43.261910 arm64_za-ptrace_Disabled_ZA_for_VL_4256 skip
13713 12:29:43.261997 arm64_za-ptrace_Get_and_set_data_for_VL_4256 skip
13714 12:29:43.262105 arm64_za-ptrace_Set_VL_4272 pass
13715 12:29:43.262194 arm64_za-ptrace_Disabled_ZA_for_VL_4272 skip
13716 12:29:43.262281 arm64_za-ptrace_Get_and_set_data_for_VL_4272 skip
13717 12:29:43.262369 arm64_za-ptrace_Set_VL_4288 pass
13718 12:29:43.262457 arm64_za-ptrace_Disabled_ZA_for_VL_4288 skip
13719 12:29:43.266362 arm64_za-ptrace_Get_and_set_data_for_VL_4288 skip
13720 12:29:43.266816 arm64_za-ptrace_Set_VL_4304 pass
13721 12:29:43.266928 arm64_za-ptrace_Disabled_ZA_for_VL_4304 skip
13722 12:29:43.267233 arm64_za-ptrace_Get_and_set_data_for_VL_4304 skip
13723 12:29:43.267350 arm64_za-ptrace_Set_VL_4320 pass
13724 12:29:43.267681 arm64_za-ptrace_Disabled_ZA_for_VL_4320 skip
13725 12:29:43.267800 arm64_za-ptrace_Get_and_set_data_for_VL_4320 skip
13726 12:29:43.268103 arm64_za-ptrace_Set_VL_4336 pass
13727 12:29:43.268220 arm64_za-ptrace_Disabled_ZA_for_VL_4336 skip
13728 12:29:43.268597 arm64_za-ptrace_Get_and_set_data_for_VL_4336 skip
13729 12:29:43.268769 arm64_za-ptrace_Set_VL_4352 pass
13730 12:29:43.268901 arm64_za-ptrace_Disabled_ZA_for_VL_4352 skip
13731 12:29:43.269056 arm64_za-ptrace_Get_and_set_data_for_VL_4352 skip
13732 12:29:43.269208 arm64_za-ptrace_Set_VL_4368 pass
13733 12:29:43.269588 arm64_za-ptrace_Disabled_ZA_for_VL_4368 skip
13734 12:29:43.269773 arm64_za-ptrace_Get_and_set_data_for_VL_4368 skip
13735 12:29:43.274841 arm64_za-ptrace_Set_VL_4384 pass
13736 12:29:43.275060 arm64_za-ptrace_Disabled_ZA_for_VL_4384 skip
13737 12:29:43.275169 arm64_za-ptrace_Get_and_set_data_for_VL_4384 skip
13738 12:29:43.275264 arm64_za-ptrace_Set_VL_4400 pass
13739 12:29:43.275349 arm64_za-ptrace_Disabled_ZA_for_VL_4400 skip
13740 12:29:43.275668 arm64_za-ptrace_Get_and_set_data_for_VL_4400 skip
13741 12:29:43.275849 arm64_za-ptrace_Set_VL_4416 pass
13742 12:29:43.275947 arm64_za-ptrace_Disabled_ZA_for_VL_4416 skip
13743 12:29:43.276035 arm64_za-ptrace_Get_and_set_data_for_VL_4416 skip
13744 12:29:43.276121 arm64_za-ptrace_Set_VL_4432 pass
13745 12:29:43.276205 arm64_za-ptrace_Disabled_ZA_for_VL_4432 skip
13746 12:29:43.276296 arm64_za-ptrace_Get_and_set_data_for_VL_4432 skip
13747 12:29:43.276417 arm64_za-ptrace_Set_VL_4448 pass
13748 12:29:43.276853 arm64_za-ptrace_Disabled_ZA_for_VL_4448 skip
13749 12:29:43.276982 arm64_za-ptrace_Get_and_set_data_for_VL_4448 skip
13750 12:29:43.277075 arm64_za-ptrace_Set_VL_4464 pass
13751 12:29:43.277257 arm64_za-ptrace_Disabled_ZA_for_VL_4464 skip
13752 12:29:43.277426 arm64_za-ptrace_Get_and_set_data_for_VL_4464 skip
13753 12:29:43.277532 arm64_za-ptrace_Set_VL_4480 pass
13754 12:29:43.277637 arm64_za-ptrace_Disabled_ZA_for_VL_4480 skip
13755 12:29:43.277765 arm64_za-ptrace_Get_and_set_data_for_VL_4480 skip
13756 12:29:43.277853 arm64_za-ptrace_Set_VL_4496 pass
13757 12:29:43.277917 arm64_za-ptrace_Disabled_ZA_for_VL_4496 skip
13758 12:29:43.277977 arm64_za-ptrace_Get_and_set_data_for_VL_4496 skip
13759 12:29:43.278036 arm64_za-ptrace_Set_VL_4512 pass
13760 12:29:43.278095 arm64_za-ptrace_Disabled_ZA_for_VL_4512 skip
13761 12:29:43.278154 arm64_za-ptrace_Get_and_set_data_for_VL_4512 skip
13762 12:29:43.278214 arm64_za-ptrace_Set_VL_4528 pass
13763 12:29:43.282232 arm64_za-ptrace_Disabled_ZA_for_VL_4528 skip
13764 12:29:43.282744 arm64_za-ptrace_Get_and_set_data_for_VL_4528 skip
13765 12:29:43.282852 arm64_za-ptrace_Set_VL_4544 pass
13766 12:29:43.282932 arm64_za-ptrace_Disabled_ZA_for_VL_4544 skip
13767 12:29:43.283025 arm64_za-ptrace_Get_and_set_data_for_VL_4544 skip
13768 12:29:43.283102 arm64_za-ptrace_Set_VL_4560 pass
13769 12:29:43.283176 arm64_za-ptrace_Disabled_ZA_for_VL_4560 skip
13770 12:29:43.283249 arm64_za-ptrace_Get_and_set_data_for_VL_4560 skip
13771 12:29:43.283335 arm64_za-ptrace_Set_VL_4576 pass
13772 12:29:43.283409 arm64_za-ptrace_Disabled_ZA_for_VL_4576 skip
13773 12:29:43.283480 arm64_za-ptrace_Get_and_set_data_for_VL_4576 skip
13774 12:29:43.283569 arm64_za-ptrace_Set_VL_4592 pass
13775 12:29:43.283644 arm64_za-ptrace_Disabled_ZA_for_VL_4592 skip
13776 12:29:43.283728 arm64_za-ptrace_Get_and_set_data_for_VL_4592 skip
13777 12:29:43.283815 arm64_za-ptrace_Set_VL_4608 pass
13778 12:29:43.284162 arm64_za-ptrace_Disabled_ZA_for_VL_4608 skip
13779 12:29:43.284260 arm64_za-ptrace_Get_and_set_data_for_VL_4608 skip
13780 12:29:43.284927 arm64_za-ptrace_Set_VL_4624 pass
13781 12:29:43.318274 arm64_za-ptrace_Disabled_ZA_for_VL_4624 skip
13782 12:29:43.318968 arm64_za-ptrace_Get_and_set_data_for_VL_4624 skip
13783 12:29:43.319095 arm64_za-ptrace_Set_VL_4640 pass
13784 12:29:43.319922 arm64_za-ptrace_Disabled_ZA_for_VL_4640 skip
13785 12:29:43.320189 arm64_za-ptrace_Get_and_set_data_for_VL_4640 skip
13786 12:29:43.320366 arm64_za-ptrace_Set_VL_4656 pass
13787 12:29:43.320536 arm64_za-ptrace_Disabled_ZA_for_VL_4656 skip
13788 12:29:43.320794 arm64_za-ptrace_Get_and_set_data_for_VL_4656 skip
13789 12:29:43.321007 arm64_za-ptrace_Set_VL_4672 pass
13790 12:29:43.321202 arm64_za-ptrace_Disabled_ZA_for_VL_4672 skip
13791 12:29:43.321377 arm64_za-ptrace_Get_and_set_data_for_VL_4672 skip
13792 12:29:43.321533 arm64_za-ptrace_Set_VL_4688 pass
13793 12:29:43.321707 arm64_za-ptrace_Disabled_ZA_for_VL_4688 skip
13794 12:29:43.321845 arm64_za-ptrace_Get_and_set_data_for_VL_4688 skip
13795 12:29:43.321998 arm64_za-ptrace_Set_VL_4704 pass
13796 12:29:43.322118 arm64_za-ptrace_Disabled_ZA_for_VL_4704 skip
13797 12:29:43.322232 arm64_za-ptrace_Get_and_set_data_for_VL_4704 skip
13798 12:29:43.322344 arm64_za-ptrace_Set_VL_4720 pass
13799 12:29:43.322457 arm64_za-ptrace_Disabled_ZA_for_VL_4720 skip
13800 12:29:43.322570 arm64_za-ptrace_Get_and_set_data_for_VL_4720 skip
13801 12:29:43.322685 arm64_za-ptrace_Set_VL_4736 pass
13802 12:29:43.322797 arm64_za-ptrace_Disabled_ZA_for_VL_4736 skip
13803 12:29:43.322909 arm64_za-ptrace_Get_and_set_data_for_VL_4736 skip
13804 12:29:43.323022 arm64_za-ptrace_Set_VL_4752 pass
13805 12:29:43.323134 arm64_za-ptrace_Disabled_ZA_for_VL_4752 skip
13806 12:29:43.323246 arm64_za-ptrace_Get_and_set_data_for_VL_4752 skip
13807 12:29:43.323359 arm64_za-ptrace_Set_VL_4768 pass
13808 12:29:43.323470 arm64_za-ptrace_Disabled_ZA_for_VL_4768 skip
13809 12:29:43.323583 arm64_za-ptrace_Get_and_set_data_for_VL_4768 skip
13810 12:29:43.326228 arm64_za-ptrace_Set_VL_4784 pass
13811 12:29:43.327555 arm64_za-ptrace_Disabled_ZA_for_VL_4784 skip
13812 12:29:43.327770 arm64_za-ptrace_Get_and_set_data_for_VL_4784 skip
13813 12:29:43.327947 arm64_za-ptrace_Set_VL_4800 pass
13814 12:29:43.328119 arm64_za-ptrace_Disabled_ZA_for_VL_4800 skip
13815 12:29:43.328743 arm64_za-ptrace_Get_and_set_data_for_VL_4800 skip
13816 12:29:43.328840 arm64_za-ptrace_Set_VL_4816 pass
13817 12:29:43.328916 arm64_za-ptrace_Disabled_ZA_for_VL_4816 skip
13818 12:29:43.328987 arm64_za-ptrace_Get_and_set_data_for_VL_4816 skip
13819 12:29:43.329057 arm64_za-ptrace_Set_VL_4832 pass
13820 12:29:43.329126 arm64_za-ptrace_Disabled_ZA_for_VL_4832 skip
13821 12:29:43.329194 arm64_za-ptrace_Get_and_set_data_for_VL_4832 skip
13822 12:29:43.329266 arm64_za-ptrace_Set_VL_4848 pass
13823 12:29:43.329338 arm64_za-ptrace_Disabled_ZA_for_VL_4848 skip
13824 12:29:43.329410 arm64_za-ptrace_Get_and_set_data_for_VL_4848 skip
13825 12:29:43.329485 arm64_za-ptrace_Set_VL_4864 pass
13826 12:29:43.329558 arm64_za-ptrace_Disabled_ZA_for_VL_4864 skip
13827 12:29:43.329634 arm64_za-ptrace_Get_and_set_data_for_VL_4864 skip
13828 12:29:43.329728 arm64_za-ptrace_Set_VL_4880 pass
13829 12:29:43.329800 arm64_za-ptrace_Disabled_ZA_for_VL_4880 skip
13830 12:29:43.329871 arm64_za-ptrace_Get_and_set_data_for_VL_4880 skip
13831 12:29:43.329959 arm64_za-ptrace_Set_VL_4896 pass
13832 12:29:43.330034 arm64_za-ptrace_Disabled_ZA_for_VL_4896 skip
13833 12:29:43.330104 arm64_za-ptrace_Get_and_set_data_for_VL_4896 skip
13834 12:29:43.330176 arm64_za-ptrace_Set_VL_4912 pass
13835 12:29:43.330259 arm64_za-ptrace_Disabled_ZA_for_VL_4912 skip
13836 12:29:43.330343 arm64_za-ptrace_Get_and_set_data_for_VL_4912 skip
13837 12:29:43.330427 arm64_za-ptrace_Set_VL_4928 pass
13838 12:29:43.330510 arm64_za-ptrace_Disabled_ZA_for_VL_4928 skip
13839 12:29:43.334156 arm64_za-ptrace_Get_and_set_data_for_VL_4928 skip
13840 12:29:43.334557 arm64_za-ptrace_Set_VL_4944 pass
13841 12:29:43.334663 arm64_za-ptrace_Disabled_ZA_for_VL_4944 skip
13842 12:29:43.334758 arm64_za-ptrace_Get_and_set_data_for_VL_4944 skip
13843 12:29:43.334866 arm64_za-ptrace_Set_VL_4960 pass
13844 12:29:43.334950 arm64_za-ptrace_Disabled_ZA_for_VL_4960 skip
13845 12:29:43.335038 arm64_za-ptrace_Get_and_set_data_for_VL_4960 skip
13846 12:29:43.335114 arm64_za-ptrace_Set_VL_4976 pass
13847 12:29:43.335200 arm64_za-ptrace_Disabled_ZA_for_VL_4976 skip
13848 12:29:43.335286 arm64_za-ptrace_Get_and_set_data_for_VL_4976 skip
13849 12:29:43.335565 arm64_za-ptrace_Set_VL_4992 pass
13850 12:29:43.335658 arm64_za-ptrace_Disabled_ZA_for_VL_4992 skip
13851 12:29:43.335744 arm64_za-ptrace_Get_and_set_data_for_VL_4992 skip
13852 12:29:43.335816 arm64_za-ptrace_Set_VL_5008 pass
13853 12:29:43.336088 arm64_za-ptrace_Disabled_ZA_for_VL_5008 skip
13854 12:29:43.336180 arm64_za-ptrace_Get_and_set_data_for_VL_5008 skip
13855 12:29:43.336253 arm64_za-ptrace_Set_VL_5024 pass
13856 12:29:43.336340 arm64_za-ptrace_Disabled_ZA_for_VL_5024 skip
13857 12:29:43.336423 arm64_za-ptrace_Get_and_set_data_for_VL_5024 skip
13858 12:29:43.336507 arm64_za-ptrace_Set_VL_5040 pass
13859 12:29:43.336590 arm64_za-ptrace_Disabled_ZA_for_VL_5040 skip
13860 12:29:43.337087 arm64_za-ptrace_Get_and_set_data_for_VL_5040 skip
13861 12:29:43.337424 arm64_za-ptrace_Set_VL_5056 pass
13862 12:29:43.337783 arm64_za-ptrace_Disabled_ZA_for_VL_5056 skip
13863 12:29:43.338046 arm64_za-ptrace_Get_and_set_data_for_VL_5056 skip
13864 12:29:43.338196 arm64_za-ptrace_Set_VL_5072 pass
13865 12:29:43.338341 arm64_za-ptrace_Disabled_ZA_for_VL_5072 skip
13866 12:29:43.338484 arm64_za-ptrace_Get_and_set_data_for_VL_5072 skip
13867 12:29:43.338627 arm64_za-ptrace_Set_VL_5088 pass
13868 12:29:43.338770 arm64_za-ptrace_Disabled_ZA_for_VL_5088 skip
13869 12:29:43.342162 arm64_za-ptrace_Get_and_set_data_for_VL_5088 skip
13870 12:29:43.342822 arm64_za-ptrace_Set_VL_5104 pass
13871 12:29:43.343227 arm64_za-ptrace_Disabled_ZA_for_VL_5104 skip
13872 12:29:43.343451 arm64_za-ptrace_Get_and_set_data_for_VL_5104 skip
13873 12:29:43.343660 arm64_za-ptrace_Set_VL_5120 pass
13874 12:29:43.343876 arm64_za-ptrace_Disabled_ZA_for_VL_5120 skip
13875 12:29:43.344142 arm64_za-ptrace_Get_and_set_data_for_VL_5120 skip
13876 12:29:43.344374 arm64_za-ptrace_Set_VL_5136 pass
13877 12:29:43.344975 arm64_za-ptrace_Disabled_ZA_for_VL_5136 skip
13878 12:29:43.345179 arm64_za-ptrace_Get_and_set_data_for_VL_5136 skip
13879 12:29:43.345350 arm64_za-ptrace_Set_VL_5152 pass
13880 12:29:43.345520 arm64_za-ptrace_Disabled_ZA_for_VL_5152 skip
13881 12:29:43.345702 arm64_za-ptrace_Get_and_set_data_for_VL_5152 skip
13882 12:29:43.345883 arm64_za-ptrace_Set_VL_5168 pass
13883 12:29:43.346022 arm64_za-ptrace_Disabled_ZA_for_VL_5168 skip
13884 12:29:43.346175 arm64_za-ptrace_Get_and_set_data_for_VL_5168 skip
13885 12:29:43.346297 arm64_za-ptrace_Set_VL_5184 pass
13886 12:29:43.346410 arm64_za-ptrace_Disabled_ZA_for_VL_5184 skip
13887 12:29:43.346523 arm64_za-ptrace_Get_and_set_data_for_VL_5184 skip
13888 12:29:43.346636 arm64_za-ptrace_Set_VL_5200 pass
13889 12:29:43.346748 arm64_za-ptrace_Disabled_ZA_for_VL_5200 skip
13890 12:29:43.346861 arm64_za-ptrace_Get_and_set_data_for_VL_5200 skip
13891 12:29:43.346982 arm64_za-ptrace_Set_VL_5216 pass
13892 12:29:43.347095 arm64_za-ptrace_Disabled_ZA_for_VL_5216 skip
13893 12:29:43.347206 arm64_za-ptrace_Get_and_set_data_for_VL_5216 skip
13894 12:29:43.347319 arm64_za-ptrace_Set_VL_5232 pass
13895 12:29:43.347430 arm64_za-ptrace_Disabled_ZA_for_VL_5232 skip
13896 12:29:43.350419 arm64_za-ptrace_Get_and_set_data_for_VL_5232 skip
13897 12:29:43.350614 arm64_za-ptrace_Set_VL_5248 pass
13898 12:29:43.350703 arm64_za-ptrace_Disabled_ZA_for_VL_5248 skip
13899 12:29:43.350992 arm64_za-ptrace_Get_and_set_data_for_VL_5248 skip
13900 12:29:43.351089 arm64_za-ptrace_Set_VL_5264 pass
13901 12:29:43.351168 arm64_za-ptrace_Disabled_ZA_for_VL_5264 skip
13902 12:29:43.351260 arm64_za-ptrace_Get_and_set_data_for_VL_5264 skip
13903 12:29:43.351336 arm64_za-ptrace_Set_VL_5280 pass
13904 12:29:43.351408 arm64_za-ptrace_Disabled_ZA_for_VL_5280 skip
13905 12:29:43.351478 arm64_za-ptrace_Get_and_set_data_for_VL_5280 skip
13906 12:29:43.351561 arm64_za-ptrace_Set_VL_5296 pass
13907 12:29:43.351657 arm64_za-ptrace_Disabled_ZA_for_VL_5296 skip
13908 12:29:43.351730 arm64_za-ptrace_Get_and_set_data_for_VL_5296 skip
13909 12:29:43.352170 arm64_za-ptrace_Set_VL_5312 pass
13910 12:29:43.352263 arm64_za-ptrace_Disabled_ZA_for_VL_5312 skip
13911 12:29:43.352336 arm64_za-ptrace_Get_and_set_data_for_VL_5312 skip
13912 12:29:43.352407 arm64_za-ptrace_Set_VL_5328 pass
13913 12:29:43.352488 arm64_za-ptrace_Disabled_ZA_for_VL_5328 skip
13914 12:29:43.352559 arm64_za-ptrace_Get_and_set_data_for_VL_5328 skip
13915 12:29:43.352629 arm64_za-ptrace_Set_VL_5344 pass
13916 12:29:43.352908 arm64_za-ptrace_Disabled_ZA_for_VL_5344 skip
13917 12:29:43.352998 arm64_za-ptrace_Get_and_set_data_for_VL_5344 skip
13918 12:29:43.353070 arm64_za-ptrace_Set_VL_5360 pass
13919 12:29:43.353153 arm64_za-ptrace_Disabled_ZA_for_VL_5360 skip
13920 12:29:43.353225 arm64_za-ptrace_Get_and_set_data_for_VL_5360 skip
13921 12:29:43.353490 arm64_za-ptrace_Set_VL_5376 pass
13922 12:29:43.353570 arm64_za-ptrace_Disabled_ZA_for_VL_5376 skip
13923 12:29:43.353666 arm64_za-ptrace_Get_and_set_data_for_VL_5376 skip
13924 12:29:43.353741 arm64_za-ptrace_Set_VL_5392 pass
13925 12:29:43.358138 arm64_za-ptrace_Disabled_ZA_for_VL_5392 skip
13926 12:29:43.358578 arm64_za-ptrace_Get_and_set_data_for_VL_5392 skip
13927 12:29:43.358676 arm64_za-ptrace_Set_VL_5408 pass
13928 12:29:43.358755 arm64_za-ptrace_Disabled_ZA_for_VL_5408 skip
13929 12:29:43.358831 arm64_za-ptrace_Get_and_set_data_for_VL_5408 skip
13930 12:29:43.358911 arm64_za-ptrace_Set_VL_5424 pass
13931 12:29:43.359004 arm64_za-ptrace_Disabled_ZA_for_VL_5424 skip
13932 12:29:43.359082 arm64_za-ptrace_Get_and_set_data_for_VL_5424 skip
13933 12:29:43.359290 arm64_za-ptrace_Set_VL_5440 pass
13934 12:29:43.359381 arm64_za-ptrace_Disabled_ZA_for_VL_5440 skip
13935 12:29:43.359476 arm64_za-ptrace_Get_and_set_data_for_VL_5440 skip
13936 12:29:43.359553 arm64_za-ptrace_Set_VL_5456 pass
13937 12:29:43.359627 arm64_za-ptrace_Disabled_ZA_for_VL_5456 skip
13938 12:29:43.359701 arm64_za-ptrace_Get_and_set_data_for_VL_5456 skip
13939 12:29:43.359776 arm64_za-ptrace_Set_VL_5472 pass
13940 12:29:43.359852 arm64_za-ptrace_Disabled_ZA_for_VL_5472 skip
13941 12:29:43.359942 arm64_za-ptrace_Get_and_set_data_for_VL_5472 skip
13942 12:29:43.360018 arm64_za-ptrace_Set_VL_5488 pass
13943 12:29:43.360095 arm64_za-ptrace_Disabled_ZA_for_VL_5488 skip
13944 12:29:43.360180 arm64_za-ptrace_Get_and_set_data_for_VL_5488 skip
13945 12:29:43.360261 arm64_za-ptrace_Set_VL_5504 pass
13946 12:29:43.360334 arm64_za-ptrace_Disabled_ZA_for_VL_5504 skip
13947 12:29:43.360421 arm64_za-ptrace_Get_and_set_data_for_VL_5504 skip
13948 12:29:43.360524 arm64_za-ptrace_Set_VL_5520 pass
13949 12:29:43.360602 arm64_za-ptrace_Disabled_ZA_for_VL_5520 skip
13950 12:29:43.360679 arm64_za-ptrace_Get_and_set_data_for_VL_5520 skip
13951 12:29:43.360762 arm64_za-ptrace_Set_VL_5536 pass
13952 12:29:43.360836 arm64_za-ptrace_Disabled_ZA_for_VL_5536 skip
13953 12:29:43.360913 arm64_za-ptrace_Get_and_set_data_for_VL_5536 skip
13954 12:29:43.361010 arm64_za-ptrace_Set_VL_5552 pass
13955 12:29:43.361087 arm64_za-ptrace_Disabled_ZA_for_VL_5552 skip
13956 12:29:43.361165 arm64_za-ptrace_Get_and_set_data_for_VL_5552 skip
13957 12:29:43.361246 arm64_za-ptrace_Set_VL_5568 pass
13958 12:29:43.361326 arm64_za-ptrace_Disabled_ZA_for_VL_5568 skip
13959 12:29:43.361407 arm64_za-ptrace_Get_and_set_data_for_VL_5568 skip
13960 12:29:43.361495 arm64_za-ptrace_Set_VL_5584 pass
13961 12:29:43.361570 arm64_za-ptrace_Disabled_ZA_for_VL_5584 skip
13962 12:29:43.361657 arm64_za-ptrace_Get_and_set_data_for_VL_5584 skip
13963 12:29:43.361741 arm64_za-ptrace_Set_VL_5600 pass
13964 12:29:43.361829 arm64_za-ptrace_Disabled_ZA_for_VL_5600 skip
13965 12:29:43.361931 arm64_za-ptrace_Get_and_set_data_for_VL_5600 skip
13966 12:29:43.362020 arm64_za-ptrace_Set_VL_5616 pass
13967 12:29:43.362105 arm64_za-ptrace_Disabled_ZA_for_VL_5616 skip
13968 12:29:43.366348 arm64_za-ptrace_Get_and_set_data_for_VL_5616 skip
13969 12:29:43.366580 arm64_za-ptrace_Set_VL_5632 pass
13970 12:29:43.366669 arm64_za-ptrace_Disabled_ZA_for_VL_5632 skip
13971 12:29:43.366969 arm64_za-ptrace_Get_and_set_data_for_VL_5632 skip
13972 12:29:43.367065 arm64_za-ptrace_Set_VL_5648 pass
13973 12:29:43.393021 arm64_za-ptrace_Disabled_ZA_for_VL_5648 skip
13974 12:29:43.393275 arm64_za-ptrace_Get_and_set_data_for_VL_5648 skip
13975 12:29:43.393372 arm64_za-ptrace_Set_VL_5664 pass
13976 12:29:43.393686 arm64_za-ptrace_Disabled_ZA_for_VL_5664 skip
13977 12:29:43.393795 arm64_za-ptrace_Get_and_set_data_for_VL_5664 skip
13978 12:29:43.393888 arm64_za-ptrace_Set_VL_5680 pass
13979 12:29:43.393980 arm64_za-ptrace_Disabled_ZA_for_VL_5680 skip
13980 12:29:43.394068 arm64_za-ptrace_Get_and_set_data_for_VL_5680 skip
13981 12:29:43.394150 arm64_za-ptrace_Set_VL_5696 pass
13982 12:29:43.394240 arm64_za-ptrace_Disabled_ZA_for_VL_5696 skip
13983 12:29:43.394351 arm64_za-ptrace_Get_and_set_data_for_VL_5696 skip
13984 12:29:43.394443 arm64_za-ptrace_Set_VL_5712 pass
13985 12:29:43.394532 arm64_za-ptrace_Disabled_ZA_for_VL_5712 skip
13986 12:29:43.394622 arm64_za-ptrace_Get_and_set_data_for_VL_5712 skip
13987 12:29:43.394711 arm64_za-ptrace_Set_VL_5728 pass
13988 12:29:43.394821 arm64_za-ptrace_Disabled_ZA_for_VL_5728 skip
13989 12:29:43.394914 arm64_za-ptrace_Get_and_set_data_for_VL_5728 skip
13990 12:29:43.395002 arm64_za-ptrace_Set_VL_5744 pass
13991 12:29:43.395092 arm64_za-ptrace_Disabled_ZA_for_VL_5744 skip
13992 12:29:43.395180 arm64_za-ptrace_Get_and_set_data_for_VL_5744 skip
13993 12:29:43.395287 arm64_za-ptrace_Set_VL_5760 pass
13994 12:29:43.395382 arm64_za-ptrace_Disabled_ZA_for_VL_5760 skip
13995 12:29:43.395470 arm64_za-ptrace_Get_and_set_data_for_VL_5760 skip
13996 12:29:43.395560 arm64_za-ptrace_Set_VL_5776 pass
13997 12:29:43.395665 arm64_za-ptrace_Disabled_ZA_for_VL_5776 skip
13998 12:29:43.395759 arm64_za-ptrace_Get_and_set_data_for_VL_5776 skip
13999 12:29:43.395856 arm64_za-ptrace_Set_VL_5792 pass
14000 12:29:43.395947 arm64_za-ptrace_Disabled_ZA_for_VL_5792 skip
14001 12:29:43.396036 arm64_za-ptrace_Get_and_set_data_for_VL_5792 skip
14002 12:29:43.396125 arm64_za-ptrace_Set_VL_5808 pass
14003 12:29:43.396232 arm64_za-ptrace_Disabled_ZA_for_VL_5808 skip
14004 12:29:43.396324 arm64_za-ptrace_Get_and_set_data_for_VL_5808 skip
14005 12:29:43.396416 arm64_za-ptrace_Set_VL_5824 pass
14006 12:29:43.396505 arm64_za-ptrace_Disabled_ZA_for_VL_5824 skip
14007 12:29:43.396591 arm64_za-ptrace_Get_and_set_data_for_VL_5824 skip
14008 12:29:43.396697 arm64_za-ptrace_Set_VL_5840 pass
14009 12:29:43.396789 arm64_za-ptrace_Disabled_ZA_for_VL_5840 skip
14010 12:29:43.396880 arm64_za-ptrace_Get_and_set_data_for_VL_5840 skip
14011 12:29:43.397218 arm64_za-ptrace_Set_VL_5856 pass
14012 12:29:43.397326 arm64_za-ptrace_Disabled_ZA_for_VL_5856 skip
14013 12:29:43.397420 arm64_za-ptrace_Get_and_set_data_for_VL_5856 skip
14014 12:29:43.397510 arm64_za-ptrace_Set_VL_5872 pass
14015 12:29:43.397601 arm64_za-ptrace_Disabled_ZA_for_VL_5872 skip
14016 12:29:43.397696 arm64_za-ptrace_Get_and_set_data_for_VL_5872 skip
14017 12:29:43.397784 arm64_za-ptrace_Set_VL_5888 pass
14018 12:29:43.397873 arm64_za-ptrace_Disabled_ZA_for_VL_5888 skip
14019 12:29:43.397964 arm64_za-ptrace_Get_and_set_data_for_VL_5888 skip
14020 12:29:43.398268 arm64_za-ptrace_Set_VL_5904 pass
14021 12:29:43.398377 arm64_za-ptrace_Disabled_ZA_for_VL_5904 skip
14022 12:29:43.398467 arm64_za-ptrace_Get_and_set_data_for_VL_5904 skip
14023 12:29:43.398556 arm64_za-ptrace_Set_VL_5920 pass
14024 12:29:43.398647 arm64_za-ptrace_Disabled_ZA_for_VL_5920 skip
14025 12:29:43.398735 arm64_za-ptrace_Get_and_set_data_for_VL_5920 skip
14026 12:29:43.402205 arm64_za-ptrace_Set_VL_5936 pass
14027 12:29:43.402631 arm64_za-ptrace_Disabled_ZA_for_VL_5936 skip
14028 12:29:43.402734 arm64_za-ptrace_Get_and_set_data_for_VL_5936 skip
14029 12:29:43.402832 arm64_za-ptrace_Set_VL_5952 pass
14030 12:29:43.402936 arm64_za-ptrace_Disabled_ZA_for_VL_5952 skip
14031 12:29:43.403025 arm64_za-ptrace_Get_and_set_data_for_VL_5952 skip
14032 12:29:43.403113 arm64_za-ptrace_Set_VL_5968 pass
14033 12:29:43.403217 arm64_za-ptrace_Disabled_ZA_for_VL_5968 skip
14034 12:29:43.403308 arm64_za-ptrace_Get_and_set_data_for_VL_5968 skip
14035 12:29:43.403395 arm64_za-ptrace_Set_VL_5984 pass
14036 12:29:43.403496 arm64_za-ptrace_Disabled_ZA_for_VL_5984 skip
14037 12:29:43.403600 arm64_za-ptrace_Get_and_set_data_for_VL_5984 skip
14038 12:29:43.403693 arm64_za-ptrace_Set_VL_6000 pass
14039 12:29:43.403800 arm64_za-ptrace_Disabled_ZA_for_VL_6000 skip
14040 12:29:43.403906 arm64_za-ptrace_Get_and_set_data_for_VL_6000 skip
14041 12:29:43.404009 arm64_za-ptrace_Set_VL_6016 pass
14042 12:29:43.404302 arm64_za-ptrace_Disabled_ZA_for_VL_6016 skip
14043 12:29:43.404409 arm64_za-ptrace_Get_and_set_data_for_VL_6016 skip
14044 12:29:43.404499 arm64_za-ptrace_Set_VL_6032 pass
14045 12:29:43.404600 arm64_za-ptrace_Disabled_ZA_for_VL_6032 skip
14046 12:29:43.404692 arm64_za-ptrace_Get_and_set_data_for_VL_6032 skip
14047 12:29:43.404784 arm64_za-ptrace_Set_VL_6048 pass
14048 12:29:43.404896 arm64_za-ptrace_Disabled_ZA_for_VL_6048 skip
14049 12:29:43.405002 arm64_za-ptrace_Get_and_set_data_for_VL_6048 skip
14050 12:29:43.405111 arm64_za-ptrace_Set_VL_6064 pass
14051 12:29:43.405198 arm64_za-ptrace_Disabled_ZA_for_VL_6064 skip
14052 12:29:43.405299 arm64_za-ptrace_Get_and_set_data_for_VL_6064 skip
14053 12:29:43.405387 arm64_za-ptrace_Set_VL_6080 pass
14054 12:29:43.405489 arm64_za-ptrace_Disabled_ZA_for_VL_6080 skip
14055 12:29:43.405593 arm64_za-ptrace_Get_and_set_data_for_VL_6080 skip
14056 12:29:43.405692 arm64_za-ptrace_Set_VL_6096 pass
14057 12:29:43.405794 arm64_za-ptrace_Disabled_ZA_for_VL_6096 skip
14058 12:29:43.405885 arm64_za-ptrace_Get_and_set_data_for_VL_6096 skip
14059 12:29:43.410194 arm64_za-ptrace_Set_VL_6112 pass
14060 12:29:43.410412 arm64_za-ptrace_Disabled_ZA_for_VL_6112 skip
14061 12:29:43.410720 arm64_za-ptrace_Get_and_set_data_for_VL_6112 skip
14062 12:29:43.410831 arm64_za-ptrace_Set_VL_6128 pass
14063 12:29:43.410927 arm64_za-ptrace_Disabled_ZA_for_VL_6128 skip
14064 12:29:43.411015 arm64_za-ptrace_Get_and_set_data_for_VL_6128 skip
14065 12:29:43.411103 arm64_za-ptrace_Set_VL_6144 pass
14066 12:29:43.411211 arm64_za-ptrace_Disabled_ZA_for_VL_6144 skip
14067 12:29:43.411303 arm64_za-ptrace_Get_and_set_data_for_VL_6144 skip
14068 12:29:43.411391 arm64_za-ptrace_Set_VL_6160 pass
14069 12:29:43.411478 arm64_za-ptrace_Disabled_ZA_for_VL_6160 skip
14070 12:29:43.411566 arm64_za-ptrace_Get_and_set_data_for_VL_6160 skip
14071 12:29:43.411671 arm64_za-ptrace_Set_VL_6176 pass
14072 12:29:43.411761 arm64_za-ptrace_Disabled_ZA_for_VL_6176 skip
14073 12:29:43.411854 arm64_za-ptrace_Get_and_set_data_for_VL_6176 skip
14074 12:29:43.411941 arm64_za-ptrace_Set_VL_6192 pass
14075 12:29:43.412027 arm64_za-ptrace_Disabled_ZA_for_VL_6192 skip
14076 12:29:43.412132 arm64_za-ptrace_Get_and_set_data_for_VL_6192 skip
14077 12:29:43.412222 arm64_za-ptrace_Set_VL_6208 pass
14078 12:29:43.412312 arm64_za-ptrace_Disabled_ZA_for_VL_6208 skip
14079 12:29:43.412401 arm64_za-ptrace_Get_and_set_data_for_VL_6208 skip
14080 12:29:43.412488 arm64_za-ptrace_Set_VL_6224 pass
14081 12:29:43.412594 arm64_za-ptrace_Disabled_ZA_for_VL_6224 skip
14082 12:29:43.412683 arm64_za-ptrace_Get_and_set_data_for_VL_6224 skip
14083 12:29:43.412772 arm64_za-ptrace_Set_VL_6240 pass
14084 12:29:43.412866 arm64_za-ptrace_Disabled_ZA_for_VL_6240 skip
14085 12:29:43.412971 arm64_za-ptrace_Get_and_set_data_for_VL_6240 skip
14086 12:29:43.413060 arm64_za-ptrace_Set_VL_6256 pass
14087 12:29:43.413146 arm64_za-ptrace_Disabled_ZA_for_VL_6256 skip
14088 12:29:43.413234 arm64_za-ptrace_Get_and_set_data_for_VL_6256 skip
14089 12:29:43.413324 arm64_za-ptrace_Set_VL_6272 pass
14090 12:29:43.413412 arm64_za-ptrace_Disabled_ZA_for_VL_6272 skip
14091 12:29:43.413515 arm64_za-ptrace_Get_and_set_data_for_VL_6272 skip
14092 12:29:43.413606 arm64_za-ptrace_Set_VL_6288 pass
14093 12:29:43.413704 arm64_za-ptrace_Disabled_ZA_for_VL_6288 skip
14094 12:29:43.413791 arm64_za-ptrace_Get_and_set_data_for_VL_6288 skip
14095 12:29:43.413881 arm64_za-ptrace_Set_VL_6304 pass
14096 12:29:43.413967 arm64_za-ptrace_Disabled_ZA_for_VL_6304 skip
14097 12:29:43.414068 arm64_za-ptrace_Get_and_set_data_for_VL_6304 skip
14098 12:29:43.414150 arm64_za-ptrace_Set_VL_6320 pass
14099 12:29:43.414236 arm64_za-ptrace_Disabled_ZA_for_VL_6320 skip
14100 12:29:43.418346 arm64_za-ptrace_Get_and_set_data_for_VL_6320 skip
14101 12:29:43.418584 arm64_za-ptrace_Set_VL_6336 pass
14102 12:29:43.418892 arm64_za-ptrace_Disabled_ZA_for_VL_6336 skip
14103 12:29:43.419001 arm64_za-ptrace_Get_and_set_data_for_VL_6336 skip
14104 12:29:43.419091 arm64_za-ptrace_Set_VL_6352 pass
14105 12:29:43.419180 arm64_za-ptrace_Disabled_ZA_for_VL_6352 skip
14106 12:29:43.419266 arm64_za-ptrace_Get_and_set_data_for_VL_6352 skip
14107 12:29:43.419370 arm64_za-ptrace_Set_VL_6368 pass
14108 12:29:43.419456 arm64_za-ptrace_Disabled_ZA_for_VL_6368 skip
14109 12:29:43.419543 arm64_za-ptrace_Get_and_set_data_for_VL_6368 skip
14110 12:29:43.419629 arm64_za-ptrace_Set_VL_6384 pass
14111 12:29:43.419730 arm64_za-ptrace_Disabled_ZA_for_VL_6384 skip
14112 12:29:43.419832 arm64_za-ptrace_Get_and_set_data_for_VL_6384 skip
14113 12:29:43.419920 arm64_za-ptrace_Set_VL_6400 pass
14114 12:29:43.420021 arm64_za-ptrace_Disabled_ZA_for_VL_6400 skip
14115 12:29:43.420303 arm64_za-ptrace_Get_and_set_data_for_VL_6400 skip
14116 12:29:43.420396 arm64_za-ptrace_Set_VL_6416 pass
14117 12:29:43.420483 arm64_za-ptrace_Disabled_ZA_for_VL_6416 skip
14118 12:29:43.420585 arm64_za-ptrace_Get_and_set_data_for_VL_6416 skip
14119 12:29:43.420673 arm64_za-ptrace_Set_VL_6432 pass
14120 12:29:43.420774 arm64_za-ptrace_Disabled_ZA_for_VL_6432 skip
14121 12:29:43.420864 arm64_za-ptrace_Get_and_set_data_for_VL_6432 skip
14122 12:29:43.420965 arm64_za-ptrace_Set_VL_6448 pass
14123 12:29:43.421051 arm64_za-ptrace_Disabled_ZA_for_VL_6448 skip
14124 12:29:43.421153 arm64_za-ptrace_Get_and_set_data_for_VL_6448 skip
14125 12:29:43.421253 arm64_za-ptrace_Set_VL_6464 pass
14126 12:29:43.421556 arm64_za-ptrace_Disabled_ZA_for_VL_6464 skip
14127 12:29:43.421656 arm64_za-ptrace_Get_and_set_data_for_VL_6464 skip
14128 12:29:43.421743 arm64_za-ptrace_Set_VL_6480 pass
14129 12:29:43.422014 arm64_za-ptrace_Disabled_ZA_for_VL_6480 skip
14130 12:29:43.426238 arm64_za-ptrace_Get_and_set_data_for_VL_6480 skip
14131 12:29:43.426442 arm64_za-ptrace_Set_VL_6496 pass
14132 12:29:43.426735 arm64_za-ptrace_Disabled_ZA_for_VL_6496 skip
14133 12:29:43.426828 arm64_za-ptrace_Get_and_set_data_for_VL_6496 skip
14134 12:29:43.426919 arm64_za-ptrace_Set_VL_6512 pass
14135 12:29:43.427007 arm64_za-ptrace_Disabled_ZA_for_VL_6512 skip
14136 12:29:43.427109 arm64_za-ptrace_Get_and_set_data_for_VL_6512 skip
14137 12:29:43.427194 arm64_za-ptrace_Set_VL_6528 pass
14138 12:29:43.427277 arm64_za-ptrace_Disabled_ZA_for_VL_6528 skip
14139 12:29:43.427360 arm64_za-ptrace_Get_and_set_data_for_VL_6528 skip
14140 12:29:43.427460 arm64_za-ptrace_Set_VL_6544 pass
14141 12:29:43.427546 arm64_za-ptrace_Disabled_ZA_for_VL_6544 skip
14142 12:29:43.427630 arm64_za-ptrace_Get_and_set_data_for_VL_6544 skip
14143 12:29:43.427727 arm64_za-ptrace_Set_VL_6560 pass
14144 12:29:43.427811 arm64_za-ptrace_Disabled_ZA_for_VL_6560 skip
14145 12:29:43.427913 arm64_za-ptrace_Get_and_set_data_for_VL_6560 skip
14146 12:29:43.428019 arm64_za-ptrace_Set_VL_6576 pass
14147 12:29:43.428316 arm64_za-ptrace_Disabled_ZA_for_VL_6576 skip
14148 12:29:43.428419 arm64_za-ptrace_Get_and_set_data_for_VL_6576 skip
14149 12:29:43.428513 arm64_za-ptrace_Set_VL_6592 pass
14150 12:29:43.428592 arm64_za-ptrace_Disabled_ZA_for_VL_6592 skip
14151 12:29:43.428684 arm64_za-ptrace_Get_and_set_data_for_VL_6592 skip
14152 12:29:43.428768 arm64_za-ptrace_Set_VL_6608 pass
14153 12:29:43.429057 arm64_za-ptrace_Disabled_ZA_for_VL_6608 skip
14154 12:29:43.429150 arm64_za-ptrace_Get_and_set_data_for_VL_6608 skip
14155 12:29:43.429234 arm64_za-ptrace_Set_VL_6624 pass
14156 12:29:43.429320 arm64_za-ptrace_Disabled_ZA_for_VL_6624 skip
14157 12:29:43.429422 arm64_za-ptrace_Get_and_set_data_for_VL_6624 skip
14158 12:29:43.429510 arm64_za-ptrace_Set_VL_6640 pass
14159 12:29:43.429596 arm64_za-ptrace_Disabled_ZA_for_VL_6640 skip
14160 12:29:43.429693 arm64_za-ptrace_Get_and_set_data_for_VL_6640 skip
14161 12:29:43.429796 arm64_za-ptrace_Set_VL_6656 pass
14162 12:29:43.429883 arm64_za-ptrace_Disabled_ZA_for_VL_6656 skip
14163 12:29:43.429977 arm64_za-ptrace_Get_and_set_data_for_VL_6656 skip
14164 12:29:43.430063 arm64_za-ptrace_Set_VL_6672 pass
14165 12:29:43.434495 arm64_za-ptrace_Disabled_ZA_for_VL_6672 skip
14166 12:29:43.456451 arm64_za-ptrace_Get_and_set_data_for_VL_6672 skip
14167 12:29:43.456709 arm64_za-ptrace_Set_VL_6688 pass
14168 12:29:43.456808 arm64_za-ptrace_Disabled_ZA_for_VL_6688 skip
14169 12:29:43.456898 arm64_za-ptrace_Get_and_set_data_for_VL_6688 skip
14170 12:29:43.457287 arm64_za-ptrace_Set_VL_6704 pass
14171 12:29:43.457498 arm64_za-ptrace_Disabled_ZA_for_VL_6704 skip
14172 12:29:43.457666 arm64_za-ptrace_Get_and_set_data_for_VL_6704 skip
14173 12:29:43.457772 arm64_za-ptrace_Set_VL_6720 pass
14174 12:29:43.457864 arm64_za-ptrace_Disabled_ZA_for_VL_6720 skip
14175 12:29:43.457951 arm64_za-ptrace_Get_and_set_data_for_VL_6720 skip
14176 12:29:43.458036 arm64_za-ptrace_Set_VL_6736 pass
14177 12:29:43.458120 arm64_za-ptrace_Disabled_ZA_for_VL_6736 skip
14178 12:29:43.458220 arm64_za-ptrace_Get_and_set_data_for_VL_6736 skip
14179 12:29:43.458308 arm64_za-ptrace_Set_VL_6752 pass
14180 12:29:43.458391 arm64_za-ptrace_Disabled_ZA_for_VL_6752 skip
14181 12:29:43.458489 arm64_za-ptrace_Get_and_set_data_for_VL_6752 skip
14182 12:29:43.458576 arm64_za-ptrace_Set_VL_6768 pass
14183 12:29:43.458677 arm64_za-ptrace_Disabled_ZA_for_VL_6768 skip
14184 12:29:43.458764 arm64_za-ptrace_Get_and_set_data_for_VL_6768 skip
14185 12:29:43.458848 arm64_za-ptrace_Set_VL_6784 pass
14186 12:29:43.458948 arm64_za-ptrace_Disabled_ZA_for_VL_6784 skip
14187 12:29:43.459032 arm64_za-ptrace_Get_and_set_data_for_VL_6784 skip
14188 12:29:43.459128 arm64_za-ptrace_Set_VL_6800 pass
14189 12:29:43.459224 arm64_za-ptrace_Disabled_ZA_for_VL_6800 skip
14190 12:29:43.459556 arm64_za-ptrace_Get_and_set_data_for_VL_6800 skip
14191 12:29:43.459648 arm64_za-ptrace_Set_VL_6816 pass
14192 12:29:43.459731 arm64_za-ptrace_Disabled_ZA_for_VL_6816 skip
14193 12:29:43.460003 arm64_za-ptrace_Get_and_set_data_for_VL_6816 skip
14194 12:29:43.460092 arm64_za-ptrace_Set_VL_6832 pass
14195 12:29:43.460189 arm64_za-ptrace_Disabled_ZA_for_VL_6832 skip
14196 12:29:43.460467 arm64_za-ptrace_Get_and_set_data_for_VL_6832 skip
14197 12:29:43.460557 arm64_za-ptrace_Set_VL_6848 pass
14198 12:29:43.460641 arm64_za-ptrace_Disabled_ZA_for_VL_6848 skip
14199 12:29:43.460724 arm64_za-ptrace_Get_and_set_data_for_VL_6848 skip
14200 12:29:43.460821 arm64_za-ptrace_Set_VL_6864 pass
14201 12:29:43.460906 arm64_za-ptrace_Disabled_ZA_for_VL_6864 skip
14202 12:29:43.461007 arm64_za-ptrace_Get_and_set_data_for_VL_6864 skip
14203 12:29:43.461092 arm64_za-ptrace_Set_VL_6880 pass
14204 12:29:43.461183 arm64_za-ptrace_Disabled_ZA_for_VL_6880 skip
14205 12:29:43.461284 arm64_za-ptrace_Get_and_set_data_for_VL_6880 skip
14206 12:29:43.461372 arm64_za-ptrace_Set_VL_6896 pass
14207 12:29:43.461471 arm64_za-ptrace_Disabled_ZA_for_VL_6896 skip
14208 12:29:43.461772 arm64_za-ptrace_Get_and_set_data_for_VL_6896 skip
14209 12:29:43.461875 arm64_za-ptrace_Set_VL_6912 pass
14210 12:29:43.466130 arm64_za-ptrace_Disabled_ZA_for_VL_6912 skip
14211 12:29:43.466561 arm64_za-ptrace_Get_and_set_data_for_VL_6912 skip
14212 12:29:43.466667 arm64_za-ptrace_Set_VL_6928 pass
14213 12:29:43.466757 arm64_za-ptrace_Disabled_ZA_for_VL_6928 skip
14214 12:29:43.466843 arm64_za-ptrace_Get_and_set_data_for_VL_6928 skip
14215 12:29:43.466945 arm64_za-ptrace_Set_VL_6944 pass
14216 12:29:43.467033 arm64_za-ptrace_Disabled_ZA_for_VL_6944 skip
14217 12:29:43.467133 arm64_za-ptrace_Get_and_set_data_for_VL_6944 skip
14218 12:29:43.467218 arm64_za-ptrace_Set_VL_6960 pass
14219 12:29:43.467316 arm64_za-ptrace_Disabled_ZA_for_VL_6960 skip
14220 12:29:43.467414 arm64_za-ptrace_Get_and_set_data_for_VL_6960 skip
14221 12:29:43.467719 arm64_za-ptrace_Set_VL_6976 pass
14222 12:29:43.467824 arm64_za-ptrace_Disabled_ZA_for_VL_6976 skip
14223 12:29:43.468121 arm64_za-ptrace_Get_and_set_data_for_VL_6976 skip
14224 12:29:43.468225 arm64_za-ptrace_Set_VL_6992 pass
14225 12:29:43.468324 arm64_za-ptrace_Disabled_ZA_for_VL_6992 skip
14226 12:29:43.468410 arm64_za-ptrace_Get_and_set_data_for_VL_6992 skip
14227 12:29:43.468492 arm64_za-ptrace_Set_VL_7008 pass
14228 12:29:43.468589 arm64_za-ptrace_Disabled_ZA_for_VL_7008 skip
14229 12:29:43.468676 arm64_za-ptrace_Get_and_set_data_for_VL_7008 skip
14230 12:29:43.469239 arm64_za-ptrace_Set_VL_7024 pass
14231 12:29:43.469343 arm64_za-ptrace_Disabled_ZA_for_VL_7024 skip
14232 12:29:43.469628 arm64_za-ptrace_Get_and_set_data_for_VL_7024 skip
14233 12:29:43.469742 arm64_za-ptrace_Set_VL_7040 pass
14234 12:29:43.469828 arm64_za-ptrace_Disabled_ZA_for_VL_7040 skip
14235 12:29:43.469925 arm64_za-ptrace_Get_and_set_data_for_VL_7040 skip
14236 12:29:43.470009 arm64_za-ptrace_Set_VL_7056 pass
14237 12:29:43.470091 arm64_za-ptrace_Disabled_ZA_for_VL_7056 skip
14238 12:29:43.470171 arm64_za-ptrace_Get_and_set_data_for_VL_7056 skip
14239 12:29:43.474095 arm64_za-ptrace_Set_VL_7072 pass
14240 12:29:43.474574 arm64_za-ptrace_Disabled_ZA_for_VL_7072 skip
14241 12:29:43.474685 arm64_za-ptrace_Get_and_set_data_for_VL_7072 skip
14242 12:29:43.474777 arm64_za-ptrace_Set_VL_7088 pass
14243 12:29:43.474865 arm64_za-ptrace_Disabled_ZA_for_VL_7088 skip
14244 12:29:43.474966 arm64_za-ptrace_Get_and_set_data_for_VL_7088 skip
14245 12:29:43.475071 arm64_za-ptrace_Set_VL_7104 pass
14246 12:29:43.475158 arm64_za-ptrace_Disabled_ZA_for_VL_7104 skip
14247 12:29:43.475241 arm64_za-ptrace_Get_and_set_data_for_VL_7104 skip
14248 12:29:43.475339 arm64_za-ptrace_Set_VL_7120 pass
14249 12:29:43.475424 arm64_za-ptrace_Disabled_ZA_for_VL_7120 skip
14250 12:29:43.475523 arm64_za-ptrace_Get_and_set_data_for_VL_7120 skip
14251 12:29:43.475622 arm64_za-ptrace_Set_VL_7136 pass
14252 12:29:43.475927 arm64_za-ptrace_Disabled_ZA_for_VL_7136 skip
14253 12:29:43.476053 arm64_za-ptrace_Get_and_set_data_for_VL_7136 skip
14254 12:29:43.476150 arm64_za-ptrace_Set_VL_7152 pass
14255 12:29:43.476256 arm64_za-ptrace_Disabled_ZA_for_VL_7152 skip
14256 12:29:43.476348 arm64_za-ptrace_Get_and_set_data_for_VL_7152 skip
14257 12:29:43.476637 arm64_za-ptrace_Set_VL_7168 pass
14258 12:29:43.476738 arm64_za-ptrace_Disabled_ZA_for_VL_7168 skip
14259 12:29:43.476829 arm64_za-ptrace_Get_and_set_data_for_VL_7168 skip
14260 12:29:43.476923 arm64_za-ptrace_Set_VL_7184 pass
14261 12:29:43.477029 arm64_za-ptrace_Disabled_ZA_for_VL_7184 skip
14262 12:29:43.477121 arm64_za-ptrace_Get_and_set_data_for_VL_7184 skip
14263 12:29:43.477210 arm64_za-ptrace_Set_VL_7200 pass
14264 12:29:43.477297 arm64_za-ptrace_Disabled_ZA_for_VL_7200 skip
14265 12:29:43.477412 arm64_za-ptrace_Get_and_set_data_for_VL_7200 skip
14266 12:29:43.477505 arm64_za-ptrace_Set_VL_7216 pass
14267 12:29:43.477595 arm64_za-ptrace_Disabled_ZA_for_VL_7216 skip
14268 12:29:43.477697 arm64_za-ptrace_Get_and_set_data_for_VL_7216 skip
14269 12:29:43.477804 arm64_za-ptrace_Set_VL_7232 pass
14270 12:29:43.477896 arm64_za-ptrace_Disabled_ZA_for_VL_7232 skip
14271 12:29:43.477986 arm64_za-ptrace_Get_and_set_data_for_VL_7232 skip
14272 12:29:43.478075 arm64_za-ptrace_Set_VL_7248 pass
14273 12:29:43.482068 arm64_za-ptrace_Disabled_ZA_for_VL_7248 skip
14274 12:29:43.482519 arm64_za-ptrace_Get_and_set_data_for_VL_7248 skip
14275 12:29:43.482629 arm64_za-ptrace_Set_VL_7264 pass
14276 12:29:43.482721 arm64_za-ptrace_Disabled_ZA_for_VL_7264 skip
14277 12:29:43.482827 arm64_za-ptrace_Get_and_set_data_for_VL_7264 skip
14278 12:29:43.482918 arm64_za-ptrace_Set_VL_7280 pass
14279 12:29:43.483025 arm64_za-ptrace_Disabled_ZA_for_VL_7280 skip
14280 12:29:43.483114 arm64_za-ptrace_Get_and_set_data_for_VL_7280 skip
14281 12:29:43.483218 arm64_za-ptrace_Set_VL_7296 pass
14282 12:29:43.483320 arm64_za-ptrace_Disabled_ZA_for_VL_7296 skip
14283 12:29:43.483426 arm64_za-ptrace_Get_and_set_data_for_VL_7296 skip
14284 12:29:43.483532 arm64_za-ptrace_Set_VL_7312 pass
14285 12:29:43.483885 arm64_za-ptrace_Disabled_ZA_for_VL_7312 skip
14286 12:29:43.483996 arm64_za-ptrace_Get_and_set_data_for_VL_7312 skip
14287 12:29:43.484300 arm64_za-ptrace_Set_VL_7328 pass
14288 12:29:43.484409 arm64_za-ptrace_Disabled_ZA_for_VL_7328 skip
14289 12:29:43.484506 arm64_za-ptrace_Get_and_set_data_for_VL_7328 skip
14290 12:29:43.484801 arm64_za-ptrace_Set_VL_7344 pass
14291 12:29:43.484911 arm64_za-ptrace_Disabled_ZA_for_VL_7344 skip
14292 12:29:43.485004 arm64_za-ptrace_Get_and_set_data_for_VL_7344 skip
14293 12:29:43.485096 arm64_za-ptrace_Set_VL_7360 pass
14294 12:29:43.485202 arm64_za-ptrace_Disabled_ZA_for_VL_7360 skip
14295 12:29:43.485295 arm64_za-ptrace_Get_and_set_data_for_VL_7360 skip
14296 12:29:43.485401 arm64_za-ptrace_Set_VL_7376 pass
14297 12:29:43.485510 arm64_za-ptrace_Disabled_ZA_for_VL_7376 skip
14298 12:29:43.485619 arm64_za-ptrace_Get_and_set_data_for_VL_7376 skip
14299 12:29:43.485736 arm64_za-ptrace_Set_VL_7392 pass
14300 12:29:43.490253 arm64_za-ptrace_Disabled_ZA_for_VL_7392 skip
14301 12:29:43.490779 arm64_za-ptrace_Get_and_set_data_for_VL_7392 skip
14302 12:29:43.490927 arm64_za-ptrace_Set_VL_7408 pass
14303 12:29:43.491022 arm64_za-ptrace_Disabled_ZA_for_VL_7408 skip
14304 12:29:43.491374 arm64_za-ptrace_Get_and_set_data_for_VL_7408 skip
14305 12:29:43.491476 arm64_za-ptrace_Set_VL_7424 pass
14306 12:29:43.491554 arm64_za-ptrace_Disabled_ZA_for_VL_7424 skip
14307 12:29:43.491665 arm64_za-ptrace_Get_and_set_data_for_VL_7424 skip
14308 12:29:43.491757 arm64_za-ptrace_Set_VL_7440 pass
14309 12:29:43.491833 arm64_za-ptrace_Disabled_ZA_for_VL_7440 skip
14310 12:29:43.491921 arm64_za-ptrace_Get_and_set_data_for_VL_7440 skip
14311 12:29:43.492204 arm64_za-ptrace_Set_VL_7456 pass
14312 12:29:43.492303 arm64_za-ptrace_Disabled_ZA_for_VL_7456 skip
14313 12:29:43.492381 arm64_za-ptrace_Get_and_set_data_for_VL_7456 skip
14314 12:29:43.492458 arm64_za-ptrace_Set_VL_7472 pass
14315 12:29:43.492603 arm64_za-ptrace_Disabled_ZA_for_VL_7472 skip
14316 12:29:43.492685 arm64_za-ptrace_Get_and_set_data_for_VL_7472 skip
14317 12:29:43.492762 arm64_za-ptrace_Set_VL_7488 pass
14318 12:29:43.492862 arm64_za-ptrace_Disabled_ZA_for_VL_7488 skip
14319 12:29:43.492950 arm64_za-ptrace_Get_and_set_data_for_VL_7488 skip
14320 12:29:43.493038 arm64_za-ptrace_Set_VL_7504 pass
14321 12:29:43.493141 arm64_za-ptrace_Disabled_ZA_for_VL_7504 skip
14322 12:29:43.493229 arm64_za-ptrace_Get_and_set_data_for_VL_7504 skip
14323 12:29:43.493313 arm64_za-ptrace_Set_VL_7520 pass
14324 12:29:43.493412 arm64_za-ptrace_Disabled_ZA_for_VL_7520 skip
14325 12:29:43.493498 arm64_za-ptrace_Get_and_set_data_for_VL_7520 skip
14326 12:29:43.493583 arm64_za-ptrace_Set_VL_7536 pass
14327 12:29:43.493695 arm64_za-ptrace_Disabled_ZA_for_VL_7536 skip
14328 12:29:43.493783 arm64_za-ptrace_Get_and_set_data_for_VL_7536 skip
14329 12:29:43.498041 arm64_za-ptrace_Set_VL_7552 pass
14330 12:29:43.498468 arm64_za-ptrace_Disabled_ZA_for_VL_7552 skip
14331 12:29:43.498575 arm64_za-ptrace_Get_and_set_data_for_VL_7552 skip
14332 12:29:43.498664 arm64_za-ptrace_Set_VL_7568 pass
14333 12:29:43.498765 arm64_za-ptrace_Disabled_ZA_for_VL_7568 skip
14334 12:29:43.498859 arm64_za-ptrace_Get_and_set_data_for_VL_7568 skip
14335 12:29:43.498952 arm64_za-ptrace_Set_VL_7584 pass
14336 12:29:43.499256 arm64_za-ptrace_Disabled_ZA_for_VL_7584 skip
14337 12:29:43.499361 arm64_za-ptrace_Get_and_set_data_for_VL_7584 skip
14338 12:29:43.499436 arm64_za-ptrace_Set_VL_7600 pass
14339 12:29:43.499594 arm64_za-ptrace_Disabled_ZA_for_VL_7600 skip
14340 12:29:43.499701 arm64_za-ptrace_Get_and_set_data_for_VL_7600 skip
14341 12:29:43.500042 arm64_za-ptrace_Set_VL_7616 pass
14342 12:29:43.500186 arm64_za-ptrace_Disabled_ZA_for_VL_7616 skip
14343 12:29:43.500587 arm64_za-ptrace_Get_and_set_data_for_VL_7616 skip
14344 12:29:43.500684 arm64_za-ptrace_Set_VL_7632 pass
14345 12:29:43.500759 arm64_za-ptrace_Disabled_ZA_for_VL_7632 skip
14346 12:29:43.500846 arm64_za-ptrace_Get_and_set_data_for_VL_7632 skip
14347 12:29:43.500920 arm64_za-ptrace_Set_VL_7648 pass
14348 12:29:43.500991 arm64_za-ptrace_Disabled_ZA_for_VL_7648 skip
14349 12:29:43.501072 arm64_za-ptrace_Get_and_set_data_for_VL_7648 skip
14350 12:29:43.501370 arm64_za-ptrace_Set_VL_7664 pass
14351 12:29:43.501539 arm64_za-ptrace_Disabled_ZA_for_VL_7664 skip
14352 12:29:43.501625 arm64_za-ptrace_Get_and_set_data_for_VL_7664 skip
14353 12:29:43.501736 arm64_za-ptrace_Set_VL_7680 pass
14354 12:29:43.501824 arm64_za-ptrace_Disabled_ZA_for_VL_7680 skip
14355 12:29:43.510104 arm64_za-ptrace_Get_and_set_data_for_VL_7680 skip
14356 12:29:43.510378 arm64_za-ptrace_Set_VL_7696 pass
14357 12:29:43.510683 arm64_za-ptrace_Disabled_ZA_for_VL_7696 skip
14358 12:29:43.535468 arm64_za-ptrace_Get_and_set_data_for_VL_7696 skip
14359 12:29:43.535697 arm64_za-ptrace_Set_VL_7712 pass
14360 12:29:43.536074 arm64_za-ptrace_Disabled_ZA_for_VL_7712 skip
14361 12:29:43.536178 arm64_za-ptrace_Get_and_set_data_for_VL_7712 skip
14362 12:29:43.536346 arm64_za-ptrace_Set_VL_7728 pass
14363 12:29:43.536426 arm64_za-ptrace_Disabled_ZA_for_VL_7728 skip
14364 12:29:43.536514 arm64_za-ptrace_Get_and_set_data_for_VL_7728 skip
14365 12:29:43.536592 arm64_za-ptrace_Set_VL_7744 pass
14366 12:29:43.536663 arm64_za-ptrace_Disabled_ZA_for_VL_7744 skip
14367 12:29:43.536748 arm64_za-ptrace_Get_and_set_data_for_VL_7744 skip
14368 12:29:43.536821 arm64_za-ptrace_Set_VL_7760 pass
14369 12:29:43.536905 arm64_za-ptrace_Disabled_ZA_for_VL_7760 skip
14370 12:29:43.537187 arm64_za-ptrace_Get_and_set_data_for_VL_7760 skip
14371 12:29:43.537284 arm64_za-ptrace_Set_VL_7776 pass
14372 12:29:43.537359 arm64_za-ptrace_Disabled_ZA_for_VL_7776 skip
14373 12:29:43.537443 arm64_za-ptrace_Get_and_set_data_for_VL_7776 skip
14374 12:29:43.537519 arm64_za-ptrace_Set_VL_7792 pass
14375 12:29:43.537602 arm64_za-ptrace_Disabled_ZA_for_VL_7792 skip
14376 12:29:43.537702 arm64_za-ptrace_Get_and_set_data_for_VL_7792 skip
14377 12:29:43.538008 arm64_za-ptrace_Set_VL_7808 pass
14378 12:29:43.538136 arm64_za-ptrace_Disabled_ZA_for_VL_7808 skip
14379 12:29:43.538460 arm64_za-ptrace_Get_and_set_data_for_VL_7808 skip
14380 12:29:43.538571 arm64_za-ptrace_Set_VL_7824 pass
14381 12:29:43.538674 arm64_za-ptrace_Disabled_ZA_for_VL_7824 skip
14382 12:29:43.538761 arm64_za-ptrace_Get_and_set_data_for_VL_7824 skip
14383 12:29:43.538846 arm64_za-ptrace_Set_VL_7840 pass
14384 12:29:43.539087 arm64_za-ptrace_Disabled_ZA_for_VL_7840 skip
14385 12:29:43.539167 arm64_za-ptrace_Get_and_set_data_for_VL_7840 skip
14386 12:29:43.539240 arm64_za-ptrace_Set_VL_7856 pass
14387 12:29:43.539324 arm64_za-ptrace_Disabled_ZA_for_VL_7856 skip
14388 12:29:43.539410 arm64_za-ptrace_Get_and_set_data_for_VL_7856 skip
14389 12:29:43.539496 arm64_za-ptrace_Set_VL_7872 pass
14390 12:29:43.539781 arm64_za-ptrace_Disabled_ZA_for_VL_7872 skip
14391 12:29:43.539900 arm64_za-ptrace_Get_and_set_data_for_VL_7872 skip
14392 12:29:43.540251 arm64_za-ptrace_Set_VL_7888 pass
14393 12:29:43.540409 arm64_za-ptrace_Disabled_ZA_for_VL_7888 skip
14394 12:29:43.540771 arm64_za-ptrace_Get_and_set_data_for_VL_7888 skip
14395 12:29:43.540894 arm64_za-ptrace_Set_VL_7904 pass
14396 12:29:43.540982 arm64_za-ptrace_Disabled_ZA_for_VL_7904 skip
14397 12:29:43.541067 arm64_za-ptrace_Get_and_set_data_for_VL_7904 skip
14398 12:29:43.541154 arm64_za-ptrace_Set_VL_7920 pass
14399 12:29:43.541237 arm64_za-ptrace_Disabled_ZA_for_VL_7920 skip
14400 12:29:43.541337 arm64_za-ptrace_Get_and_set_data_for_VL_7920 skip
14401 12:29:43.541423 arm64_za-ptrace_Set_VL_7936 pass
14402 12:29:43.541521 arm64_za-ptrace_Disabled_ZA_for_VL_7936 skip
14403 12:29:43.541607 arm64_za-ptrace_Get_and_set_data_for_VL_7936 skip
14404 12:29:43.541716 arm64_za-ptrace_Set_VL_7952 pass
14405 12:29:43.541803 arm64_za-ptrace_Disabled_ZA_for_VL_7952 skip
14406 12:29:43.546160 arm64_za-ptrace_Get_and_set_data_for_VL_7952 skip
14407 12:29:43.546406 arm64_za-ptrace_Set_VL_7968 pass
14408 12:29:43.546729 arm64_za-ptrace_Disabled_ZA_for_VL_7968 skip
14409 12:29:43.546829 arm64_za-ptrace_Get_and_set_data_for_VL_7968 skip
14410 12:29:43.546908 arm64_za-ptrace_Set_VL_7984 pass
14411 12:29:43.546981 arm64_za-ptrace_Disabled_ZA_for_VL_7984 skip
14412 12:29:43.547071 arm64_za-ptrace_Get_and_set_data_for_VL_7984 skip
14413 12:29:43.547480 arm64_za-ptrace_Set_VL_8000 pass
14414 12:29:43.547667 arm64_za-ptrace_Disabled_ZA_for_VL_8000 skip
14415 12:29:43.547838 arm64_za-ptrace_Get_and_set_data_for_VL_8000 skip
14416 12:29:43.548005 arm64_za-ptrace_Set_VL_8016 pass
14417 12:29:43.548171 arm64_za-ptrace_Disabled_ZA_for_VL_8016 skip
14418 12:29:43.548333 arm64_za-ptrace_Get_and_set_data_for_VL_8016 skip
14419 12:29:43.548497 arm64_za-ptrace_Set_VL_8032 pass
14420 12:29:43.548658 arm64_za-ptrace_Disabled_ZA_for_VL_8032 skip
14421 12:29:43.548859 arm64_za-ptrace_Get_and_set_data_for_VL_8032 skip
14422 12:29:43.549026 arm64_za-ptrace_Set_VL_8048 pass
14423 12:29:43.549188 arm64_za-ptrace_Disabled_ZA_for_VL_8048 skip
14424 12:29:43.549349 arm64_za-ptrace_Get_and_set_data_for_VL_8048 skip
14425 12:29:43.549509 arm64_za-ptrace_Set_VL_8064 pass
14426 12:29:43.550140 arm64_za-ptrace_Disabled_ZA_for_VL_8064 skip
14427 12:29:43.550316 arm64_za-ptrace_Get_and_set_data_for_VL_8064 skip
14428 12:29:43.550460 arm64_za-ptrace_Set_VL_8080 pass
14429 12:29:43.550589 arm64_za-ptrace_Disabled_ZA_for_VL_8080 skip
14430 12:29:43.550712 arm64_za-ptrace_Get_and_set_data_for_VL_8080 skip
14431 12:29:43.550830 arm64_za-ptrace_Set_VL_8096 pass
14432 12:29:43.550960 arm64_za-ptrace_Disabled_ZA_for_VL_8096 skip
14433 12:29:43.551087 arm64_za-ptrace_Get_and_set_data_for_VL_8096 skip
14434 12:29:43.551204 arm64_za-ptrace_Set_VL_8112 pass
14435 12:29:43.551365 arm64_za-ptrace_Disabled_ZA_for_VL_8112 skip
14436 12:29:43.551492 arm64_za-ptrace_Get_and_set_data_for_VL_8112 skip
14437 12:29:43.551619 arm64_za-ptrace_Set_VL_8128 pass
14438 12:29:43.551741 arm64_za-ptrace_Disabled_ZA_for_VL_8128 skip
14439 12:29:43.551861 arm64_za-ptrace_Get_and_set_data_for_VL_8128 skip
14440 12:29:43.551992 arm64_za-ptrace_Set_VL_8144 pass
14441 12:29:43.552111 arm64_za-ptrace_Disabled_ZA_for_VL_8144 skip
14442 12:29:43.552233 arm64_za-ptrace_Get_and_set_data_for_VL_8144 skip
14443 12:29:43.552363 arm64_za-ptrace_Set_VL_8160 pass
14444 12:29:43.558195 arm64_za-ptrace_Disabled_ZA_for_VL_8160 skip
14445 12:29:43.558441 arm64_za-ptrace_Get_and_set_data_for_VL_8160 skip
14446 12:29:43.558868 arm64_za-ptrace_Set_VL_8176 pass
14447 12:29:43.559072 arm64_za-ptrace_Disabled_ZA_for_VL_8176 skip
14448 12:29:43.559242 arm64_za-ptrace_Get_and_set_data_for_VL_8176 skip
14449 12:29:43.559408 arm64_za-ptrace_Set_VL_8192 pass
14450 12:29:43.559575 arm64_za-ptrace_Disabled_ZA_for_VL_8192 skip
14451 12:29:43.559773 arm64_za-ptrace_Get_and_set_data_for_VL_8192 skip
14452 12:29:43.559928 arm64_za-ptrace pass
14453 12:29:43.560116 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory pass
14454 12:29:43.560276 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory pass
14455 12:29:43.560448 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory pass
14456 12:29:43.560825 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory pass
14457 12:29:43.560991 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory fail
14458 12:29:43.561188 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory fail
14459 12:29:43.561361 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14460 12:29:43.561702 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory pass
14461 12:29:43.561821 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory pass
14462 12:29:43.561905 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14463 12:29:43.561982 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory fail
14464 12:29:43.566141 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory fail
14465 12:29:43.566453 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory pass
14466 12:29:43.566582 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory fail
14467 12:29:43.566987 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory fail
14468 12:29:43.567628 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory pass
14469 12:29:43.567927 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory pass
14470 12:29:43.568171 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14471 12:29:43.568449 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory pass
14472 12:29:43.568586 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14473 12:29:43.568732 arm64_check_buffer_fill fail
14474 12:29:43.568873 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14475 12:29:43.569050 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14476 12:29:43.569173 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14477 12:29:43.569486 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14478 12:29:43.569595 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14479 12:29:43.569896 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14480 12:29:43.573971 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14481 12:29:43.574333 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14482 12:29:43.574648 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14483 12:29:43.574949 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14484 12:29:43.575238 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14485 12:29:43.575559 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14486 12:29:43.575672 arm64_check_child_memory fail
14487 12:29:43.575757 arm64_check_gcr_el1_cswitch fail
14488 12:29:43.575853 arm64_check_ksm_options fail
14489 12:29:43.576154 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off pass
14490 12:29:43.576467 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14491 12:29:43.576833 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off pass
14492 12:29:43.577143 arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14493 12:29:43.577485 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14494 12:29:43.587082 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14495 12:29:43.587477 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14496 12:29:43.587796 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14497 12:29:43.588172 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14498 12:29:43.588479 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14499 12:29:43.588592 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14500 12:29:43.588699 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14501 12:29:43.588991 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14502 12:29:43.589334 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14503 12:29:43.589696 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14504 12:29:43.594090 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14505 12:29:43.594512 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14506 12:29:43.594904 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14507 12:29:43.595166 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14508 12:29:43.595282 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14509 12:29:43.595570 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory fail
14510 12:29:43.596070 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory fail
14511 12:29:43.596179 arm64_check_mmap_options fail
14512 12:29:43.596272 arm64_check_prctl_check_basic_read pass
14513 12:29:43.596372 arm64_check_prctl_NONE pass
14514 12:29:43.596495 arm64_check_prctl_SYNC pass
14515 12:29:43.596592 arm64_check_prctl_ASYNC pass
14516 12:29:43.596695 arm64_check_prctl_SYNC_ASYNC pass
14517 12:29:43.596809 arm64_check_prctl pass
14518 12:29:43.596933 arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode fail
14519 12:29:43.597039 arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode fail
14520 12:29:43.597149 arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode pass
14521 12:29:43.597295 arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode fail
14522 12:29:43.597387 arm64_check_tags_inclusion fail
14523 12:29:43.597523 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14524 12:29:43.597675 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14525 12:29:43.602119 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14526 12:29:43.602473 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14527 12:29:43.602615 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14528 12:29:43.602952 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14529 12:29:43.603179 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14530 12:29:43.603304 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14531 12:29:43.603440 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14532 12:29:43.603840 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14533 12:29:43.603954 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14534 12:29:43.604254 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14535 12:29:43.604358 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14536 12:29:43.604545 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14537 12:29:43.604672 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14538 12:29:43.605061 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14539 12:29:43.605228 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14540 12:29:43.605412 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14541 12:29:43.605711 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14542 12:29:43.610128 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14543 12:29:43.610459 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14544 12:29:43.610680 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14545 12:29:43.610881 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14546 12:29:43.611138 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14547 12:29:43.611597 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14548 12:29:43.611844 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14549 12:29:43.612086 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14550 12:29:43.612373 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14551 12:29:43.612629 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14552 12:29:43.612904 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14553 12:29:43.613151 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14554 12:29:43.613360 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14555 12:29:43.613571 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14556 12:29:43.613840 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14557 12:29:43.614039 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14558 12:29:43.614222 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14559 12:29:43.618090 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14560 12:29:43.618444 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14561 12:29:43.618667 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14562 12:29:43.618897 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14563 12:29:43.619110 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14564 12:29:43.619303 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14565 12:29:43.619674 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14566 12:29:43.619794 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14567 12:29:43.619967 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14568 12:29:43.620133 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14569 12:29:43.620522 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14570 12:29:43.620626 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14571 12:29:43.620721 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14572 12:29:43.621051 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14573 12:29:43.621246 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14574 12:29:43.621448 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14575 12:29:43.621754 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14576 12:29:43.621977 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14577 12:29:43.626276 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14578 12:29:43.626763 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14579 12:29:43.627539 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14580 12:29:43.627809 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14581 12:29:43.628036 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14582 12:29:43.628188 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14583 12:29:43.628311 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14584 12:29:43.628461 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14585 12:29:43.654875 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14586 12:29:43.655135 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14587 12:29:43.655257 arm64_check_user_mem pass
14588 12:29:43.655564 arm64_btitest_nohint_func_call_using_br_x0 pass
14589 12:29:43.655659 arm64_btitest_nohint_func_call_using_br_x16 pass
14590 12:29:43.655740 arm64_btitest_nohint_func_call_using_blr pass
14591 12:29:43.655814 arm64_btitest_bti_none_func_call_using_br_x0 pass
14592 12:29:43.655899 arm64_btitest_bti_none_func_call_using_br_x16 pass
14593 12:29:43.655988 arm64_btitest_bti_none_func_call_using_blr pass
14594 12:29:43.656063 arm64_btitest_bti_c_func_call_using_br_x0 pass
14595 12:29:43.656148 arm64_btitest_bti_c_func_call_using_br_x16 pass
14596 12:29:43.656232 arm64_btitest_bti_c_func_call_using_blr pass
14597 12:29:43.656318 arm64_btitest_bti_j_func_call_using_br_x0 pass
14598 12:29:43.656402 arm64_btitest_bti_j_func_call_using_br_x16 pass
14599 12:29:43.656483 arm64_btitest_bti_j_func_call_using_blr pass
14600 12:29:43.656547 arm64_btitest_bti_jc_func_call_using_br_x0 pass
14601 12:29:43.656829 arm64_btitest_bti_jc_func_call_using_br_x16 pass
14602 12:29:43.656924 arm64_btitest_bti_jc_func_call_using_blr pass
14603 12:29:43.657013 arm64_btitest_paciasp_func_call_using_br_x0 pass
14604 12:29:43.657121 arm64_btitest_paciasp_func_call_using_br_x16 pass
14605 12:29:43.657208 arm64_btitest_paciasp_func_call_using_blr pass
14606 12:29:43.657293 arm64_btitest pass
14607 12:29:43.657390 arm64_nobtitest_nohint_func_call_using_br_x0 pass
14608 12:29:43.657501 arm64_nobtitest_nohint_func_call_using_br_x16 pass
14609 12:29:43.657592 arm64_nobtitest_nohint_func_call_using_blr pass
14610 12:29:43.657727 arm64_nobtitest_bti_none_func_call_using_br_x0 pass
14611 12:29:43.657817 arm64_nobtitest_bti_none_func_call_using_br_x16 pass
14612 12:29:43.662200 arm64_nobtitest_bti_none_func_call_using_blr pass
14613 12:29:43.662485 arm64_nobtitest_bti_c_func_call_using_br_x0 pass
14614 12:29:43.662582 arm64_nobtitest_bti_c_func_call_using_br_x16 pass
14615 12:29:43.662860 arm64_nobtitest_bti_c_func_call_using_blr pass
14616 12:29:43.662955 arm64_nobtitest_bti_j_func_call_using_br_x0 pass
14617 12:29:43.663033 arm64_nobtitest_bti_j_func_call_using_br_x16 pass
14618 12:29:43.663106 arm64_nobtitest_bti_j_func_call_using_blr pass
14619 12:29:43.663369 arm64_nobtitest_bti_jc_func_call_using_br_x0 pass
14620 12:29:43.663448 arm64_nobtitest_bti_jc_func_call_using_br_x16 pass
14621 12:29:43.663520 arm64_nobtitest_bti_jc_func_call_using_blr pass
14622 12:29:43.663605 arm64_nobtitest_paciasp_func_call_using_br_x0 pass
14623 12:29:43.663893 arm64_nobtitest_paciasp_func_call_using_br_x16 pass
14624 12:29:43.664165 arm64_nobtitest_paciasp_func_call_using_blr pass
14625 12:29:43.664236 arm64_nobtitest pass
14626 12:29:43.664301 arm64_hwcap_cpuinfo_match_RNG pass
14627 12:29:43.664365 arm64_hwcap_sigill_RNG pass
14628 12:29:43.664439 arm64_hwcap_cpuinfo_match_SME pass
14629 12:29:43.664505 arm64_hwcap_sigill_SME pass
14630 12:29:43.664759 arm64_hwcap_cpuinfo_match_SVE pass
14631 12:29:43.664839 arm64_hwcap_sigill_SVE pass
14632 12:29:43.664914 arm64_hwcap_cpuinfo_match_SVE_2 pass
14633 12:29:43.665001 arm64_hwcap_sigill_SVE_2 pass
14634 12:29:43.665075 arm64_hwcap_cpuinfo_match_SVE_AES pass
14635 12:29:43.665138 arm64_hwcap_sigill_SVE_AES pass
14636 12:29:43.665221 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
14637 12:29:43.665304 arm64_hwcap_sigill_SVE2_PMULL pass
14638 12:29:43.665396 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
14639 12:29:43.665474 arm64_hwcap_sigill_SVE2_BITPERM pass
14640 12:29:43.665690 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
14641 12:29:43.665791 arm64_hwcap_sigill_SVE2_SHA3 pass
14642 12:29:43.665861 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
14643 12:29:43.665923 arm64_hwcap_sigill_SVE2_SM4 pass
14644 12:29:43.666010 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
14645 12:29:43.666089 arm64_hwcap_sigill_SVE2_I8MM pass
14646 12:29:43.670220 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
14647 12:29:43.670588 arm64_hwcap_sigill_SVE2_F32MM pass
14648 12:29:43.670681 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
14649 12:29:43.670766 arm64_hwcap_sigill_SVE2_F64MM pass
14650 12:29:43.671033 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
14651 12:29:43.671106 arm64_hwcap_sigill_SVE2_BF16 pass
14652 12:29:43.671173 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
14653 12:29:43.671247 arm64_hwcap_sigill_SVE2_EBF16 skip
14654 12:29:43.671313 arm64_hwcap pass
14655 12:29:43.671388 arm64_ptrace_read_tpidr_one pass
14656 12:29:43.671635 arm64_ptrace_write_tpidr_one pass
14657 12:29:43.671703 arm64_ptrace_verify_tpidr_one pass
14658 12:29:43.671769 arm64_ptrace_count_tpidrs pass
14659 12:29:43.671832 arm64_ptrace_tpidr2_write pass
14660 12:29:43.671931 arm64_ptrace_tpidr2_read pass
14661 12:29:43.672019 arm64_ptrace_write_tpidr_only pass
14662 12:29:43.672104 arm64_ptrace pass
14663 12:29:43.672178 arm64_syscall-abi_getpid_FPSIMD pass
14664 12:29:43.672242 arm64_syscall-abi_getpid_SVE_VL_256 pass
14665 12:29:43.672490 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA pass
14666 12:29:43.672561 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM pass
14667 12:29:43.672637 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA pass
14668 12:29:43.672704 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA pass
14669 12:29:43.672780 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM pass
14670 12:29:43.673026 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA pass
14671 12:29:43.673095 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA pass
14672 12:29:43.673341 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM pass
14673 12:29:43.673715 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA pass
14674 12:29:43.673823 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA pass
14675 12:29:43.673902 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM pass
14676 12:29:43.673992 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA pass
14677 12:29:43.674068 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA pass
14678 12:29:43.674130 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM pass
14679 12:29:43.678255 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA pass
14680 12:29:43.678460 arm64_syscall-abi_getpid_SVE_VL_240 pass
14681 12:29:43.678723 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA pass
14682 12:29:43.678808 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM pass
14683 12:29:43.678892 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA pass
14684 12:29:43.678984 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA pass
14685 12:29:43.679074 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM pass
14686 12:29:43.679357 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA pass
14687 12:29:43.679443 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA pass
14688 12:29:43.679510 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM pass
14689 12:29:43.679769 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA pass
14690 12:29:43.679858 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA pass
14691 12:29:43.679926 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM pass
14692 12:29:43.680001 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA pass
14693 12:29:43.680077 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA pass
14694 12:29:43.680179 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM pass
14695 12:29:43.680441 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA pass
14696 12:29:43.680522 arm64_syscall-abi_getpid_SVE_VL_224 pass
14697 12:29:43.680626 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA pass
14698 12:29:43.680715 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM pass
14699 12:29:43.680781 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA pass
14700 12:29:43.681043 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA pass
14701 12:29:43.681142 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM pass
14702 12:29:43.681228 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA pass
14703 12:29:43.681304 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA pass
14704 12:29:43.681384 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM pass
14705 12:29:43.681658 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA pass
14706 12:29:43.681754 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA pass
14707 12:29:43.681844 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM pass
14708 12:29:43.686132 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA pass
14709 12:29:43.686544 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA pass
14710 12:29:43.686616 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM pass
14711 12:29:43.686680 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA pass
14712 12:29:43.686782 arm64_syscall-abi_getpid_SVE_VL_208 pass
14713 12:29:43.686872 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA pass
14714 12:29:43.686950 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM pass
14715 12:29:43.687065 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA pass
14716 12:29:43.687318 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA pass
14717 12:29:43.687569 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM pass
14718 12:29:43.687821 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA pass
14719 12:29:43.687890 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA pass
14720 12:29:43.687965 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM pass
14721 12:29:43.688044 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA pass
14722 12:29:43.688328 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA pass
14723 12:29:43.688408 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM pass
14724 12:29:43.688485 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA pass
14725 12:29:43.688753 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA pass
14726 12:29:43.689003 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM pass
14727 12:29:43.689100 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA pass
14728 12:29:43.689209 arm64_syscall-abi_getpid_SVE_VL_192 pass
14729 12:29:43.689296 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA pass
14730 12:29:43.689398 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM pass
14731 12:29:43.689700 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA pass
14732 12:29:43.689829 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA pass
14733 12:29:43.694243 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM pass
14734 12:29:43.694718 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA pass
14735 12:29:43.694836 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA pass
14736 12:29:43.694951 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM pass
14737 12:29:43.695059 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA pass
14738 12:29:43.695175 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA pass
14739 12:29:43.695295 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM pass
14740 12:29:43.695396 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA pass
14741 12:29:43.695497 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA pass
14742 12:29:43.695910 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM pass
14743 12:29:43.696007 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA pass
14744 12:29:43.696079 arm64_syscall-abi_getpid_SVE_VL_176 pass
14745 12:29:43.696179 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA pass
14746 12:29:43.696267 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM pass
14747 12:29:43.696581 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA pass
14748 12:29:43.696678 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA pass
14749 12:29:43.696972 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM pass
14750 12:29:43.697072 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA pass
14751 12:29:43.697209 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA pass
14752 12:29:43.697321 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM pass
14753 12:29:43.697440 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA pass
14754 12:29:43.702533 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA pass
14755 12:29:43.715075 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM pass
14756 12:29:43.715573 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA pass
14757 12:29:43.715721 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA pass
14758 12:29:43.715836 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM pass
14759 12:29:43.715941 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA pass
14760 12:29:43.716084 arm64_syscall-abi_getpid_SVE_VL_160 pass
14761 12:29:43.716243 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA pass
14762 12:29:43.716335 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM pass
14763 12:29:43.716416 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA pass
14764 12:29:43.716687 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA pass
14765 12:29:43.716774 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM pass
14766 12:29:43.716854 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA pass
14767 12:29:43.716947 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA pass
14768 12:29:43.717217 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM pass
14769 12:29:43.717412 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA pass
14770 12:29:43.717496 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA pass
14771 12:29:43.717590 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM pass
14772 12:29:43.717850 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA pass
14773 12:29:43.717934 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA pass
14774 12:29:43.718036 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM pass
14775 12:29:43.722135 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA pass
14776 12:29:43.722545 arm64_syscall-abi_getpid_SVE_VL_144 pass
14777 12:29:43.722705 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA pass
14778 12:29:43.722847 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM pass
14779 12:29:43.722975 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA pass
14780 12:29:43.723084 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA pass
14781 12:29:43.723169 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM pass
14782 12:29:43.723270 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA pass
14783 12:29:43.723713 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA pass
14784 12:29:43.723958 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM pass
14785 12:29:43.724054 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA pass
14786 12:29:43.724146 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA pass
14787 12:29:43.724261 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM pass
14788 12:29:43.724342 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA pass
14789 12:29:43.724408 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA pass
14790 12:29:43.724469 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM pass
14791 12:29:43.724546 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA pass
14792 12:29:43.724625 arm64_syscall-abi_getpid_SVE_VL_128 pass
14793 12:29:43.724712 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA pass
14794 12:29:43.724811 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM pass
14795 12:29:43.724891 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA pass
14796 12:29:43.725132 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA pass
14797 12:29:43.725239 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM pass
14798 12:29:43.725557 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA pass
14799 12:29:43.725689 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA pass
14800 12:29:43.725818 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM pass
14801 12:29:43.730172 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA pass
14802 12:29:43.730779 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA pass
14803 12:29:43.730976 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM pass
14804 12:29:43.731137 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA pass
14805 12:29:43.731294 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA pass
14806 12:29:43.731467 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM pass
14807 12:29:43.731615 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA pass
14808 12:29:43.731771 arm64_syscall-abi_getpid_SVE_VL_112 pass
14809 12:29:43.731906 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA pass
14810 12:29:43.732068 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM pass
14811 12:29:43.732232 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA pass
14812 12:29:43.732396 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA pass
14813 12:29:43.732555 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM pass
14814 12:29:43.732709 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA pass
14815 12:29:43.732901 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA pass
14816 12:29:43.733070 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM pass
14817 12:29:43.733232 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA pass
14818 12:29:43.733400 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA pass
14819 12:29:43.733605 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM pass
14820 12:29:43.733973 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA pass
14821 12:29:43.734128 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA pass
14822 12:29:43.734248 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM pass
14823 12:29:43.734399 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA pass
14824 12:29:43.734525 arm64_syscall-abi_getpid_SVE_VL_96 pass
14825 12:29:43.738004 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA pass
14826 12:29:43.738330 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM pass
14827 12:29:43.738432 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA pass
14828 12:29:43.738529 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA pass
14829 12:29:43.738625 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM pass
14830 12:29:43.738957 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA pass
14831 12:29:43.739092 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA pass
14832 12:29:43.739245 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM pass
14833 12:29:43.739341 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA pass
14834 12:29:43.739423 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA pass
14835 12:29:43.739515 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM pass
14836 12:29:43.739609 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA pass
14837 12:29:43.740034 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA pass
14838 12:29:43.740213 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM pass
14839 12:29:43.740324 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA pass
14840 12:29:43.740502 arm64_syscall-abi_getpid_SVE_VL_80 pass
14841 12:29:43.740747 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA pass
14842 12:29:43.740905 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM pass
14843 12:29:43.740990 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA pass
14844 12:29:43.741070 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA pass
14845 12:29:43.741148 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM pass
14846 12:29:43.741241 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA pass
14847 12:29:43.741323 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA pass
14848 12:29:43.741401 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM pass
14849 12:29:43.742108 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA pass
14850 12:29:43.742211 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA pass
14851 12:29:43.742292 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM pass
14852 12:29:43.742568 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA pass
14853 12:29:43.742668 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA pass
14854 12:29:43.742749 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM pass
14855 12:29:43.742827 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA pass
14856 12:29:43.746226 arm64_syscall-abi_getpid_SVE_VL_64 pass
14857 12:29:43.746626 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA pass
14858 12:29:43.746726 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM pass
14859 12:29:43.746801 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA pass
14860 12:29:43.746884 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA pass
14861 12:29:43.746965 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM pass
14862 12:29:43.747298 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA pass
14863 12:29:43.747398 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA pass
14864 12:29:43.747480 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM pass
14865 12:29:43.747577 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA pass
14866 12:29:43.747658 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA pass
14867 12:29:43.747945 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM pass
14868 12:29:43.748095 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA pass
14869 12:29:43.748183 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA pass
14870 12:29:43.748315 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM pass
14871 12:29:43.748713 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA pass
14872 12:29:43.748815 arm64_syscall-abi_getpid_SVE_VL_48 pass
14873 12:29:43.748949 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA pass
14874 12:29:43.749148 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM pass
14875 12:29:43.749382 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA pass
14876 12:29:43.749469 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA pass
14877 12:29:43.749548 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM pass
14878 12:29:43.749627 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA pass
14879 12:29:43.749728 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA pass
14880 12:29:43.749800 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM pass
14881 12:29:43.749874 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA pass
14882 12:29:43.749970 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA pass
14883 12:29:43.754216 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM pass
14884 12:29:43.754414 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA pass
14885 12:29:43.754706 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA pass
14886 12:29:43.754804 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM pass
14887 12:29:43.754893 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA pass
14888 12:29:43.754993 arm64_syscall-abi_getpid_SVE_VL_32 pass
14889 12:29:43.755096 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA pass
14890 12:29:43.755198 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM pass
14891 12:29:43.755297 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA pass
14892 12:29:43.755781 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA pass
14893 12:29:43.755885 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM pass
14894 12:29:43.755992 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA pass
14895 12:29:43.756082 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA pass
14896 12:29:43.756169 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM pass
14897 12:29:43.756256 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA pass
14898 12:29:43.756359 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA pass
14899 12:29:43.756650 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM pass
14900 12:29:43.756750 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA pass
14901 12:29:43.756845 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA pass
14902 12:29:43.756927 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM pass
14903 12:29:43.757019 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA pass
14904 12:29:43.757112 arm64_syscall-abi_getpid_SVE_VL_16 pass
14905 12:29:43.757379 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA pass
14906 12:29:43.757457 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM pass
14907 12:29:43.773142 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA pass
14908 12:29:43.773555 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA pass
14909 12:29:43.773681 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM pass
14910 12:29:43.773763 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA pass
14911 12:29:43.773854 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA pass
14912 12:29:43.773934 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM pass
14913 12:29:43.774214 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA pass
14914 12:29:43.774312 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA pass
14915 12:29:43.774403 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM pass
14916 12:29:43.774494 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA pass
14917 12:29:43.774585 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA pass
14918 12:29:43.774681 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM pass
14919 12:29:43.774972 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA pass
14920 12:29:43.775115 arm64_syscall-abi_sched_yield_FPSIMD pass
14921 12:29:43.775215 arm64_syscall-abi_sched_yield_SVE_VL_256 pass
14922 12:29:43.775573 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA pass
14923 12:29:43.775671 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM pass
14924 12:29:43.775775 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA pass
14925 12:29:43.775915 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA pass
14926 12:29:43.776233 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM pass
14927 12:29:43.776365 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA pass
14928 12:29:43.776480 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA pass
14929 12:29:43.776584 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM pass
14930 12:29:43.776661 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA pass
14931 12:29:43.776733 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA pass
14932 12:29:43.776806 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM pass
14933 12:29:43.776877 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA pass
14934 12:29:43.776965 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA pass
14935 12:29:43.777039 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM pass
14936 12:29:43.777111 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA pass
14937 12:29:43.777183 arm64_syscall-abi_sched_yield_SVE_VL_240 pass
14938 12:29:43.777254 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA pass
14939 12:29:43.777341 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM pass
14940 12:29:43.777416 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA pass
14941 12:29:43.777488 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA pass
14942 12:29:43.777560 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM pass
14943 12:29:43.777830 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA pass
14944 12:29:43.777925 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA pass
14945 12:29:43.778000 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM pass
14946 12:29:43.782073 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA pass
14947 12:29:43.782398 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA pass
14948 12:29:43.782508 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM pass
14949 12:29:43.782623 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA pass
14950 12:29:43.782730 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA pass
14951 12:29:43.782855 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM pass
14952 12:29:43.782973 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA pass
14953 12:29:43.783080 arm64_syscall-abi_sched_yield_SVE_VL_224 pass
14954 12:29:43.783185 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA pass
14955 12:29:43.783491 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM pass
14956 12:29:43.783607 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA pass
14957 12:29:43.783717 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA pass
14958 12:29:43.783814 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM pass
14959 12:29:43.784120 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA pass
14960 12:29:43.784227 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA pass
14961 12:29:43.784333 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM pass
14962 12:29:43.784438 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA pass
14963 12:29:43.784541 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA pass
14964 12:29:43.784650 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM pass
14965 12:29:43.784953 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA pass
14966 12:29:43.785062 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA pass
14967 12:29:43.785169 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM pass
14968 12:29:43.785274 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA pass
14969 12:29:43.785364 arm64_syscall-abi_sched_yield_SVE_VL_208 pass
14970 12:29:43.785478 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA pass
14971 12:29:43.785788 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM pass
14972 12:29:43.785896 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA pass
14973 12:29:43.790229 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA pass
14974 12:29:43.790542 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM pass
14975 12:29:43.790724 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA pass
14976 12:29:43.790875 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA pass
14977 12:29:43.791076 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM pass
14978 12:29:43.791267 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA pass
14979 12:29:43.791495 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA pass
14980 12:29:43.791646 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM pass
14981 12:29:43.791834 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA pass
14982 12:29:43.792050 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA pass
14983 12:29:43.792208 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM pass
14984 12:29:43.792348 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA pass
14985 12:29:43.792538 arm64_syscall-abi_sched_yield_SVE_VL_192 pass
14986 12:29:43.792719 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA pass
14987 12:29:43.792854 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM pass
14988 12:29:43.792982 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA pass
14989 12:29:43.793107 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA pass
14990 12:29:43.793257 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM pass
14991 12:29:43.793389 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA pass
14992 12:29:43.793516 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA pass
14993 12:29:43.794104 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM pass
14994 12:29:43.794329 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA pass
14995 12:29:43.794494 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA pass
14996 12:29:43.794642 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM pass
14997 12:29:43.798387 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA pass
14998 12:29:43.798799 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA pass
14999 12:29:43.798967 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM pass
15000 12:29:43.799132 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA pass
15001 12:29:43.799294 arm64_syscall-abi_sched_yield_SVE_VL_176 pass
15002 12:29:43.799485 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA pass
15003 12:29:43.799657 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM pass
15004 12:29:43.799808 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA pass
15005 12:29:43.800002 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA pass
15006 12:29:43.800158 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM pass
15007 12:29:43.800342 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA pass
15008 12:29:43.800570 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA pass
15009 12:29:43.800783 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM pass
15010 12:29:43.801008 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA pass
15011 12:29:43.801199 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA pass
15012 12:29:43.801458 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM pass
15013 12:29:43.801672 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA pass
15014 12:29:43.801879 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA pass
15015 12:29:43.802023 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM pass
15016 12:29:43.802170 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA pass
15017 12:29:43.802294 arm64_syscall-abi_sched_yield_SVE_VL_160 pass
15018 12:29:43.802413 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA pass
15019 12:29:43.802531 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM pass
15020 12:29:43.806413 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA pass
15021 12:29:43.806827 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA pass
15022 12:29:43.806997 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM pass
15023 12:29:43.807107 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA pass
15024 12:29:43.807189 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA pass
15025 12:29:43.807266 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM pass
15026 12:29:43.807343 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA pass
15027 12:29:43.807433 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA pass
15028 12:29:43.807511 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM pass
15029 12:29:43.807587 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA pass
15030 12:29:43.807867 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA pass
15031 12:29:43.808008 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM pass
15032 12:29:43.808221 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA pass
15033 12:29:43.808327 arm64_syscall-abi_sched_yield_SVE_VL_144 pass
15034 12:29:43.808482 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA pass
15035 12:29:43.808638 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM pass
15036 12:29:43.809024 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA pass
15037 12:29:43.809141 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA pass
15038 12:29:43.809223 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM pass
15039 12:29:43.809301 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA pass
15040 12:29:43.809378 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA pass
15041 12:29:43.809472 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM pass
15042 12:29:43.809603 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA pass
15043 12:29:43.809714 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA pass
15044 12:29:43.809799 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM pass
15045 12:29:43.809879 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA pass
15046 12:29:43.809956 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA pass
15047 12:29:43.824213 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM pass
15048 12:29:43.824429 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA pass
15049 12:29:43.824744 arm64_syscall-abi_sched_yield_SVE_VL_128 pass
15050 12:29:43.824852 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA pass
15051 12:29:43.824943 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM pass
15052 12:29:43.825045 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA pass
15053 12:29:43.825152 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA pass
15054 12:29:43.825242 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM pass
15055 12:29:43.825346 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA pass
15056 12:29:43.825765 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA pass
15057 12:29:43.825867 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM pass
15058 12:29:43.825955 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA pass
15059 12:29:43.826286 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA pass
15060 12:29:43.826400 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM pass
15061 12:29:43.826500 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA pass
15062 12:29:43.826582 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA pass
15063 12:29:43.826677 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM pass
15064 12:29:43.826770 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA pass
15065 12:29:43.826865 arm64_syscall-abi_sched_yield_SVE_VL_112 pass
15066 12:29:43.827150 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA pass
15067 12:29:43.827257 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM pass
15068 12:29:43.827362 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA pass
15069 12:29:43.827446 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA pass
15070 12:29:43.827546 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM pass
15071 12:29:43.827632 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA pass
15072 12:29:43.827732 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA pass
15073 12:29:43.827830 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM pass
15074 12:29:43.828139 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA pass
15075 12:29:43.828257 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA pass
15076 12:29:43.828349 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM pass
15077 12:29:43.828449 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA pass
15078 12:29:43.828750 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA pass
15079 12:29:43.828874 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM pass
15080 12:29:43.828979 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA pass
15081 12:29:43.829308 arm64_syscall-abi_sched_yield_SVE_VL_96 pass
15082 12:29:43.829427 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA pass
15083 12:29:43.829529 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM pass
15084 12:29:43.829827 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA pass
15085 12:29:43.834093 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA pass
15086 12:29:43.834835 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM pass
15087 12:29:43.834948 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA pass
15088 12:29:43.835040 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA pass
15089 12:29:43.835124 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM pass
15090 12:29:43.835207 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA pass
15091 12:29:43.835304 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA pass
15092 12:29:43.835391 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM pass
15093 12:29:43.835478 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA pass
15094 12:29:43.835564 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA pass
15095 12:29:43.835665 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM pass
15096 12:29:43.835753 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA pass
15097 12:29:43.835838 arm64_syscall-abi_sched_yield_SVE_VL_80 pass
15098 12:29:43.836231 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA pass
15099 12:29:43.836327 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM pass
15100 12:29:43.836416 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA pass
15101 12:29:43.836520 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA pass
15102 12:29:43.836610 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM pass
15103 12:29:43.836703 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA pass
15104 12:29:43.836807 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA pass
15105 12:29:43.836897 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM pass
15106 12:29:43.837001 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA pass
15107 12:29:43.837090 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA pass
15108 12:29:43.837195 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM pass
15109 12:29:43.837299 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA pass
15110 12:29:43.837400 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA pass
15111 12:29:43.837501 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM pass
15112 12:29:43.837896 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA pass
15113 12:29:43.838088 arm64_syscall-abi_sched_yield_SVE_VL_64 pass
15114 12:29:43.842225 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA pass
15115 12:29:43.842676 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM pass
15116 12:29:43.842892 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA pass
15117 12:29:43.843116 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA pass
15118 12:29:43.843356 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM pass
15119 12:29:43.843555 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA pass
15120 12:29:43.843731 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA pass
15121 12:29:43.843932 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM pass
15122 12:29:43.844160 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA pass
15123 12:29:43.844391 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA pass
15124 12:29:43.844599 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM pass
15125 12:29:43.844803 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA pass
15126 12:29:43.845005 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA pass
15127 12:29:43.845194 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM pass
15128 12:29:43.845476 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA pass
15129 12:29:43.845706 arm64_syscall-abi_sched_yield_SVE_VL_48 pass
15130 12:29:43.845883 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA pass
15131 12:29:43.846018 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM pass
15132 12:29:43.846138 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA pass
15133 12:29:43.846256 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA pass
15134 12:29:43.846372 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM pass
15135 12:29:43.846490 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA pass
15136 12:29:43.846607 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA pass
15137 12:29:43.846753 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM pass
15138 12:29:43.846879 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA pass
15139 12:29:43.850238 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA pass
15140 12:29:43.850685 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM pass
15141 12:29:43.850929 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA pass
15142 12:29:43.851148 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA pass
15143 12:29:43.851351 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM pass
15144 12:29:43.851605 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA pass
15145 12:29:43.851809 arm64_syscall-abi_sched_yield_SVE_VL_32 pass
15146 12:29:43.852039 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA pass
15147 12:29:43.852258 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM pass
15148 12:29:43.852473 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA pass
15149 12:29:43.852711 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA pass
15150 12:29:43.852924 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM pass
15151 12:29:43.853128 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA pass
15152 12:29:43.853346 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA pass
15153 12:29:43.853563 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM pass
15154 12:29:43.853772 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA pass
15155 12:29:43.853999 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA pass
15156 12:29:43.854140 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM pass
15157 12:29:43.854260 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA pass
15158 12:29:43.854379 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA pass
15159 12:29:43.854497 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM pass
15160 12:29:43.854613 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA pass
15161 12:29:43.854730 arm64_syscall-abi_sched_yield_SVE_VL_16 pass
15162 12:29:43.858200 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA pass
15163 12:29:43.858642 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM pass
15164 12:29:43.858827 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA pass
15165 12:29:43.859231 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA pass
15166 12:29:43.859383 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM pass
15167 12:29:43.859588 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA pass
15168 12:29:43.859786 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA pass
15169 12:29:43.859953 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM pass
15170 12:29:43.860115 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA pass
15171 12:29:43.860276 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA pass
15172 12:29:43.860463 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM pass
15173 12:29:43.860620 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA pass
15174 12:29:43.860779 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA pass
15175 12:29:43.860946 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM pass
15176 12:29:43.861075 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA pass
15177 12:29:43.861223 arm64_syscall-abi pass
15178 12:29:43.861348 arm64_tpidr2_default_value pass
15179 12:29:43.861468 arm64_tpidr2_write_read pass
15180 12:29:43.861586 arm64_tpidr2_write_sleep_read pass
15181 12:29:43.861721 arm64_tpidr2_write_fork_read pass
15182 12:29:43.861881 arm64_tpidr2_write_clone_read pass
15183 12:29:43.862017 arm64_tpidr2 pass
15184 12:29:43.880644 + ../../utils/send-to-lava.sh ./output/result.txt
15185 12:29:43.933276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
15186 12:29:43.934334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
15188 12:29:43.969229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
15190 12:29:43.969876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
15191 12:29:44.007052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
15192 12:29:44.007486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
15194 12:29:44.043506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
15195 12:29:44.043914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
15197 12:29:44.079490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
15199 12:29:44.079955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
15200 12:29:44.119065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
15201 12:29:44.119555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
15203 12:29:44.159671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
15204 12:29:44.160138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
15206 12:29:44.196457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
15208 12:29:44.197030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
15209 12:29:44.233614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass
15211 12:29:44.234210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass>
15212 12:29:44.273797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass
15214 12:29:44.274376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass>
15215 12:29:44.312361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
15217 12:29:44.312939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
15218 12:29:44.349172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
15219 12:29:44.349642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
15221 12:29:44.391432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
15222 12:29:44.391914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
15224 12:29:44.430124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
15226 12:29:44.430803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
15227 12:29:44.467759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
15229 12:29:44.468411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
15230 12:29:44.504349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
15231 12:29:44.504822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
15233 12:29:44.543318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
15234 12:29:44.543797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
15236 12:29:44.580636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
15237 12:29:44.581088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
15239 12:29:44.617486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass>
15240 12:29:44.617980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass
15242 12:29:44.655367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
15243 12:29:44.655782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
15245 12:29:44.692458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
15246 12:29:44.692879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
15248 12:29:44.728734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=pass>
15249 12:29:44.729167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=pass
15251 12:29:44.765364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=pass>
15252 12:29:44.765805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=pass
15254 12:29:44.803582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=pass>
15255 12:29:44.804020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=pass
15257 12:29:44.840868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=pass
15259 12:29:44.841341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=pass>
15260 12:29:44.877532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=pass>
15261 12:29:44.877973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=pass
15263 12:29:44.916128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=pass>
15264 12:29:44.916563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=pass
15266 12:29:44.952887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass>
15267 12:29:44.953399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass
15269 12:29:44.989324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass
15271 12:29:44.989932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass>
15272 12:29:45.027581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass
15274 12:29:45.028213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass>
15275 12:29:45.065405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass>
15276 12:29:45.065819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass
15278 12:29:45.102658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass
15280 12:29:45.103300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass>
15281 12:29:45.139987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass
15283 12:29:45.140620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass>
15284 12:29:45.176469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass>
15285 12:29:45.176975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass
15287 12:29:45.215505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
15288 12:29:45.215959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
15290 12:29:45.252801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
15292 12:29:45.253454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
15293 12:29:45.289607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass
15295 12:29:45.290082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass>
15296 12:29:45.325563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass>
15297 12:29:45.326015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass
15299 12:29:45.363013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass>
15300 12:29:45.363454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass
15302 12:29:45.400365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass>
15303 12:29:45.400795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass
15305 12:29:45.437955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass
15307 12:29:45.438395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass>
15308 12:29:45.475702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass
15310 12:29:45.476133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass>
15311 12:29:45.513682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass>
15312 12:29:45.514104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass
15314 12:29:45.551798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass>
15315 12:29:45.552310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass
15317 12:29:45.591003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass
15319 12:29:45.591636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass>
15320 12:29:45.628502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass
15322 12:29:45.629066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass>
15323 12:29:45.667087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass
15325 12:29:45.667500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass>
15326 12:29:45.705018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass
15328 12:29:45.705432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass>
15329 12:29:45.743377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass
15331 12:29:45.743810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass>
15332 12:29:45.780823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass>
15333 12:29:45.781309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass
15335 12:29:45.820142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass
15337 12:29:45.820625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass>
15338 12:29:45.857277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass>
15339 12:29:45.857683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass
15341 12:29:45.895194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass>
15342 12:29:45.895607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass
15344 12:29:45.932359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass>
15345 12:29:45.932739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass
15347 12:29:45.967919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass
15349 12:29:45.968529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass>
15350 12:29:46.007435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass>
15351 12:29:46.007924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass
15353 12:29:46.047390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass
15355 12:29:46.047878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass>
15356 12:29:46.087410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass>
15357 12:29:46.087836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass
15359 12:29:46.129830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass>
15360 12:29:46.130242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass
15362 12:29:46.166178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass
15364 12:29:46.166616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass>
15365 12:29:46.205237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass
15367 12:29:46.205670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass>
15368 12:29:46.243584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass
15370 12:29:46.244021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass>
15371 12:29:46.281842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
15373 12:29:46.282481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
15374 12:29:46.320343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
15375 12:29:46.320836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
15377 12:29:46.360007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass>
15378 12:29:46.360514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass
15380 12:29:46.399855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
15381 12:29:46.400435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
15383 12:29:46.442731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
15384 12:29:46.443123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
15386 12:29:46.477615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass
15388 12:29:46.478077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass>
15389 12:29:46.514098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass
15391 12:29:46.514567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass>
15392 12:29:46.548710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass>
15393 12:29:46.549122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass
15395 12:29:46.585067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass>
15396 12:29:46.585477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass
15398 12:29:46.621402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass
15400 12:29:46.621859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass>
15401 12:29:46.657245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass
15403 12:29:46.657704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass>
15404 12:29:46.692376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass
15406 12:29:46.692946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass>
15407 12:29:46.728302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass
15409 12:29:46.728756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass>
15410 12:29:46.763716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass>
15411 12:29:46.764127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass
15413 12:29:46.799770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass>
15414 12:29:46.800288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass
15416 12:29:46.835685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass>
15417 12:29:46.836149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass
15419 12:29:46.870719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass>
15420 12:29:46.871139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass
15422 12:29:46.905860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass>
15423 12:29:46.906327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass
15425 12:29:46.942397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass
15427 12:29:46.942992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass>
15428 12:29:46.978873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass
15430 12:29:46.979434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass>
15431 12:29:47.015128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass>
15432 12:29:47.015594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass
15434 12:29:47.051341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass>
15435 12:29:47.051817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass
15437 12:29:47.087951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass>
15438 12:29:47.088345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass
15440 12:29:47.124624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass>
15441 12:29:47.125075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass
15443 12:29:47.160991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass
15445 12:29:47.161542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass>
15446 12:29:47.198927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass>
15447 12:29:47.199387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass
15449 12:29:47.237453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass>
15450 12:29:47.237894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass
15452 12:29:47.275853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass>
15453 12:29:47.276285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass
15455 12:29:47.314342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass
15457 12:29:47.314846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass>
15458 12:29:47.364087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass>
15459 12:29:47.364514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass
15461 12:29:47.400457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass>
15462 12:29:47.400878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass
15464 12:29:47.436582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass>
15465 12:29:47.437007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass
15467 12:29:47.473410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass
15469 12:29:47.473898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass>
15470 12:29:47.510080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass
15472 12:29:47.510534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass>
15473 12:29:47.545622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass>
15474 12:29:47.546039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass
15476 12:29:47.581785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass>
15477 12:29:47.582201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass
15479 12:29:47.617739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass>
15480 12:29:47.618230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass
15482 12:29:47.652296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass>
15483 12:29:47.652729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass
15485 12:29:47.687714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass>
15486 12:29:47.688126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass
15488 12:29:47.722287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass
15490 12:29:47.722735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass>
15491 12:29:47.769400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass
15493 12:29:47.769841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass>
15494 12:29:47.807443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass>
15495 12:29:47.807885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass
15497 12:29:47.844077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass
15499 12:29:47.844532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass>
15500 12:29:47.880385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass>
15501 12:29:47.880795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass
15503 12:29:47.916780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass>
15504 12:29:47.917183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass
15506 12:29:47.951903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass
15508 12:29:47.952488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass>
15509 12:29:47.987527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass
15511 12:29:47.988144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass>
15512 12:29:48.023024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass>
15513 12:29:48.023488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass
15515 12:29:48.059148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass>
15516 12:29:48.059702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass
15518 12:29:48.094829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass
15520 12:29:48.095284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass>
15521 12:29:48.130744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass>
15522 12:29:48.131150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass
15524 12:29:48.165717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass>
15525 12:29:48.166127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass
15527 12:29:48.202183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass
15529 12:29:48.202607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass>
15530 12:29:48.237270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass
15532 12:29:48.237721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass>
15533 12:29:48.272702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass>
15534 12:29:48.273171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass
15536 12:29:48.307820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass>
15537 12:29:48.308267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass
15539 12:29:48.343032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass>
15540 12:29:48.343500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass
15542 12:29:48.378152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass
15544 12:29:48.378750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass>
15545 12:29:48.414204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass
15547 12:29:48.414660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass>
15548 12:29:48.449602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass
15550 12:29:48.450070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass>
15551 12:29:48.485423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass
15553 12:29:48.485896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass>
15554 12:29:48.520834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass>
15555 12:29:48.521269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass
15557 12:29:48.556763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass
15559 12:29:48.557227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass>
15560 12:29:48.591933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass
15562 12:29:48.592394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass>
15563 12:29:48.627345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass>
15564 12:29:48.627748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass
15566 12:29:48.663714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass>
15567 12:29:48.664136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass
15569 12:29:48.699125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass>
15570 12:29:48.699545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass
15572 12:29:48.735319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass>
15573 12:29:48.735853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass
15575 12:29:48.773558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass>
15576 12:29:48.773995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass
15578 12:29:48.810980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass>
15579 12:29:48.811423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass
15581 12:29:48.854311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
15583 12:29:48.854753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
15584 12:29:48.901153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
15585 12:29:48.901572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
15587 12:29:48.948253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
15588 12:29:48.948620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
15590 12:29:48.985548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass
15592 12:29:48.985988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass>
15593 12:29:49.021513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
15594 12:29:49.022004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
15596 12:29:49.057892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
15597 12:29:49.058309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
15599 12:29:49.095248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
15600 12:29:49.095652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
15602 12:29:49.130383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass>
15603 12:29:49.130817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass
15605 12:29:49.167071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
15607 12:29:49.167639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
15608 12:29:49.203206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
15610 12:29:49.203769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
15611 12:29:49.239215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
15612 12:29:49.239649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
15614 12:29:49.275072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass
15616 12:29:49.275546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass>
15617 12:29:49.310008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
15619 12:29:49.310463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
15620 12:29:49.347577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
15621 12:29:49.347981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
15623 12:29:49.384271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
15624 12:29:49.384697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
15626 12:29:49.420482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass>
15627 12:29:49.420916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass
15629 12:29:49.456947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
15630 12:29:49.457350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
15632 12:29:49.493539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
15633 12:29:49.493946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
15635 12:29:49.532346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
15636 12:29:49.532837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
15638 12:29:49.569021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass>
15639 12:29:49.569436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass
15641 12:29:49.607863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
15642 12:29:49.608281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
15644 12:29:49.648859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
15646 12:29:49.649291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
15647 12:29:49.687597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
15648 12:29:49.688010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
15650 12:29:49.732086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass>
15651 12:29:49.732488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass
15653 12:29:49.784396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
15654 12:29:49.784882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
15656 12:29:49.822822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
15658 12:29:49.823433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
15659 12:29:49.860471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
15661 12:29:49.860995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
15662 12:29:49.896735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass>
15663 12:29:49.897104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass
15665 12:29:49.933545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
15667 12:29:49.933955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
15668 12:29:49.973000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
15670 12:29:49.973404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
15671 12:29:50.011570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
15672 12:29:50.011972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
15674 12:29:50.049060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass
15676 12:29:50.049473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass>
15677 12:29:50.085104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
15678 12:29:50.085466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
15680 12:29:50.122195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
15682 12:29:50.122565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
15683 12:29:50.159631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
15684 12:29:50.160042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
15686 12:29:50.196328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass>
15687 12:29:50.196723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass
15689 12:29:50.232506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
15690 12:29:50.232913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
15692 12:29:50.268566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
15693 12:29:50.268951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
15695 12:29:50.305417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
15696 12:29:50.305785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
15698 12:29:50.341533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass>
15699 12:29:50.341938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass
15701 12:29:50.378345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
15703 12:29:50.378790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
15704 12:29:50.415071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
15705 12:29:50.415469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
15707 12:29:50.451745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
15708 12:29:50.452190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
15710 12:29:50.487821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass>
15711 12:29:50.488314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass
15713 12:29:50.524584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
15714 12:29:50.525051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
15716 12:29:50.561490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
15717 12:29:50.561927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
15719 12:29:50.602982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
15720 12:29:50.603362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
15722 12:29:50.640014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass>
15723 12:29:50.640455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass
15725 12:29:50.678018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
15727 12:29:50.678498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
15728 12:29:50.715687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
15730 12:29:50.716143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
15731 12:29:50.754275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
15733 12:29:50.754902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
15734 12:29:50.799979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass>
15735 12:29:50.800420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass
15737 12:29:50.837871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
15739 12:29:50.838312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
15740 12:29:50.883585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
15741 12:29:50.884098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
15743 12:29:50.921136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
15744 12:29:50.921553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
15746 12:29:50.959245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass>
15747 12:29:50.959685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass
15749 12:29:50.997132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
15751 12:29:50.997925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
15752 12:29:51.035145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
15754 12:29:51.035603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
15755 12:29:51.072620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
15757 12:29:51.073077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
15758 12:29:51.109916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass
15760 12:29:51.110365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass>
15761 12:29:51.148028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
15763 12:29:51.148671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
15764 12:29:51.185609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
15766 12:29:51.186265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
15767 12:29:51.224507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
15768 12:29:51.224996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
15770 12:29:51.260942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass>
15771 12:29:51.261420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass
15773 12:29:51.298813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
15774 12:29:51.299254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
15776 12:29:51.339539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
15778 12:29:51.339996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
15779 12:29:51.377239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
15780 12:29:51.377699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
15782 12:29:51.418964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass>
15783 12:29:51.419391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass
15785 12:29:51.456824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
15787 12:29:51.457401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
15788 12:29:51.494960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
15789 12:29:51.495386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
15791 12:29:51.533051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
15793 12:29:51.533623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
15794 12:29:51.570033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass
15796 12:29:51.570610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass>
15797 12:29:51.607804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
15798 12:29:51.608255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
15800 12:29:51.644898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
15802 12:29:51.645330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
15803 12:29:51.683602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
15804 12:29:51.684032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
15806 12:29:51.721271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass
15808 12:29:51.721726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass>
15809 12:29:51.758512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
15810 12:29:51.758956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
15812 12:29:51.796037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
15814 12:29:51.796687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
15815 12:29:51.833716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
15816 12:29:51.834141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
15818 12:29:51.871502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass
15820 12:29:51.871959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass>
15821 12:29:51.908741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
15823 12:29:51.909195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
15824 12:29:51.945713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
15825 12:29:51.946139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
15827 12:29:51.983550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
15829 12:29:51.984128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
15830 12:29:52.020495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass
15832 12:29:52.021072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass>
15833 12:29:52.057373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
15835 12:29:52.057806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
15836 12:29:52.094788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
15838 12:29:52.095379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
15839 12:29:52.132877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
15840 12:29:52.133346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
15842 12:29:52.169291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass>
15843 12:29:52.169692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass
15845 12:29:52.207416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
15847 12:29:52.207888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
15848 12:29:52.245251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
15850 12:29:52.245726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
15851 12:29:52.283232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
15853 12:29:52.283701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
15854 12:29:52.320161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass>
15855 12:29:52.320612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass
15857 12:29:52.376988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
15858 12:29:52.377394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
15860 12:29:52.419241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
15862 12:29:52.419698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
15863 12:29:52.463080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
15864 12:29:52.463527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
15866 12:29:52.504774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass>
15867 12:29:52.505154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass
15869 12:29:52.543834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
15870 12:29:52.544264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
15872 12:29:52.583305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
15873 12:29:52.583723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
15875 12:29:52.620954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
15876 12:29:52.621361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
15878 12:29:52.659357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass>
15879 12:29:52.659782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass
15881 12:29:52.704661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
15882 12:29:52.705075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
15884 12:29:52.744450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
15885 12:29:52.744831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
15887 12:29:52.781902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
15889 12:29:52.782474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
15890 12:29:52.819450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass
15892 12:29:52.820071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass>
15893 12:29:52.856824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
15894 12:29:52.857313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
15896 12:29:52.894268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
15898 12:29:52.894833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
15899 12:29:52.932329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
15901 12:29:52.932888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
15902 12:29:52.969733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass
15904 12:29:52.970300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass>
15905 12:29:53.007367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
15906 12:29:53.007856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
15908 12:29:53.045720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
15909 12:29:53.046199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
15911 12:29:53.084574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
15912 12:29:53.085019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
15914 12:29:53.121308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass
15916 12:29:53.121954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass>
15917 12:29:53.159430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
15918 12:29:53.159898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
15920 12:29:53.198933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
15922 12:29:53.199652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
15923 12:29:53.236792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
15924 12:29:53.237248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
15926 12:29:53.275220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass>
15927 12:29:53.275704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass
15929 12:29:53.314054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
15931 12:29:53.314913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
15932 12:29:53.353430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
15934 12:29:53.354069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
15935 12:29:53.399073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
15936 12:29:53.399545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
15938 12:29:53.435604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass>
15939 12:29:53.436041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass
15941 12:29:53.477112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
15942 12:29:53.477512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
15944 12:29:53.516643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
15946 12:29:53.517130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
15947 12:29:53.554164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
15949 12:29:53.554637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
15950 12:29:53.592465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass
15952 12:29:53.592941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass>
15953 12:29:53.629521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
15955 12:29:53.629992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
15956 12:29:53.667748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
15957 12:29:53.668185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
15959 12:29:53.707345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
15961 12:29:53.707964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
15962 12:29:53.745011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass>
15963 12:29:53.745576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass
15965 12:29:53.784517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
15966 12:29:53.784957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
15968 12:29:53.821978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
15970 12:29:53.822422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
15971 12:29:53.871396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
15972 12:29:53.871791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
15974 12:29:53.914713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass
15976 12:29:53.915105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass>
15977 12:29:53.951378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
15978 12:29:53.951781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
15980 12:29:53.988428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
15981 12:29:53.988810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
15983 12:29:54.027354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
15984 12:29:54.027787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
15986 12:29:54.064607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass>
15987 12:29:54.065040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass
15989 12:29:54.102735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
15990 12:29:54.103142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
15992 12:29:54.140406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
15994 12:29:54.140834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
15995 12:29:54.177390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
15997 12:29:54.177877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
15998 12:29:54.215102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass>
15999 12:29:54.215549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass
16001 12:29:54.252714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
16003 12:29:54.253196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
16004 12:29:54.290643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
16005 12:29:54.291076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
16007 12:29:54.328446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
16008 12:29:54.328856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
16010 12:29:54.365694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass>
16011 12:29:54.366121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass
16013 12:29:54.404001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
16014 12:29:54.404413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
16016 12:29:54.442675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
16017 12:29:54.443108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
16019 12:29:54.480386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
16020 12:29:54.480813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
16022 12:29:54.519168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass>
16023 12:29:54.519582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass
16025 12:29:54.557218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
16027 12:29:54.557708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
16028 12:29:54.595657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
16030 12:29:54.596106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
16031 12:29:54.635461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
16033 12:29:54.635839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
16034 12:29:54.673073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass
16036 12:29:54.673458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass>
16037 12:29:54.710188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
16039 12:29:54.710632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
16040 12:29:54.759799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
16041 12:29:54.760199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
16043 12:29:54.808189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
16045 12:29:54.808653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
16046 12:29:54.849553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass
16048 12:29:54.850020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass>
16049 12:29:54.887719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
16051 12:29:54.888190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
16052 12:29:54.925234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
16054 12:29:54.925921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
16055 12:29:54.964712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
16056 12:29:54.965207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
16058 12:29:55.007023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass
16060 12:29:55.007485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass>
16061 12:29:55.044967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
16062 12:29:55.045402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
16064 12:29:55.083527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
16066 12:29:55.083959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
16067 12:29:55.120262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
16068 12:29:55.120646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
16070 12:29:55.157117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass>
16071 12:29:55.157588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass
16073 12:29:55.202796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
16074 12:29:55.203268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
16076 12:29:55.238586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
16077 12:29:55.239064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
16079 12:29:55.285416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
16080 12:29:55.285900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
16082 12:29:55.324072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass>
16083 12:29:55.324567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass
16085 12:29:55.360396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
16086 12:29:55.360841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
16088 12:29:55.398722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
16089 12:29:55.399167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
16091 12:29:55.440286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
16092 12:29:55.440732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
16094 12:29:55.478803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass>
16095 12:29:55.479228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass
16097 12:29:55.515261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
16098 12:29:55.515691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
16100 12:29:55.551591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
16101 12:29:55.552074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
16103 12:29:55.589042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
16104 12:29:55.589518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
16106 12:29:55.639052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass>
16107 12:29:55.639539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass
16109 12:29:55.675485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
16110 12:29:55.675900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
16112 12:29:55.711571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
16114 12:29:55.712150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
16115 12:29:55.747736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
16117 12:29:55.748107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
16118 12:29:55.785946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass
16120 12:29:55.786511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass>
16121 12:29:55.824385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
16122 12:29:55.824862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
16124 12:29:55.861974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
16126 12:29:55.862433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
16127 12:29:55.899799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
16129 12:29:55.900442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
16130 12:29:55.936930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass>
16131 12:29:55.937414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass
16133 12:29:55.977206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
16134 12:29:55.977713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
16136 12:29:56.012788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
16138 12:29:56.013359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
16139 12:29:56.047976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
16140 12:29:56.048447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
16142 12:29:56.084246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass
16144 12:29:56.084836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass>
16145 12:29:56.121066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
16147 12:29:56.121536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
16148 12:29:56.157546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
16150 12:29:56.158031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
16151 12:29:56.195788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
16152 12:29:56.196240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
16154 12:29:56.231999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass>
16155 12:29:56.232471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass
16157 12:29:56.267965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
16158 12:29:56.268452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
16160 12:29:56.305189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
16161 12:29:56.305686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
16163 12:29:56.345996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
16165 12:29:56.346499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
16166 12:29:56.383548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass
16168 12:29:56.384198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass>
16169 12:29:56.421118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
16170 12:29:56.421606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
16172 12:29:56.458679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
16173 12:29:56.459107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
16175 12:29:56.509132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
16176 12:29:56.509606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
16178 12:29:56.555764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass>
16179 12:29:56.556201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass
16181 12:29:56.594961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
16183 12:29:56.595614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
16184 12:29:56.633256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
16185 12:29:56.633758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
16187 12:29:56.673283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
16189 12:29:56.673910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
16190 12:29:56.715882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass>
16191 12:29:56.716361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass
16193 12:29:56.755357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
16194 12:29:56.755716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
16196 12:29:56.794884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
16198 12:29:56.795354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
16199 12:29:56.834157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
16201 12:29:56.834855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
16202 12:29:56.883776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass
16204 12:29:56.884401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass>
16205 12:29:56.923122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
16206 12:29:56.923537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
16208 12:29:56.960908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
16209 12:29:56.961295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
16211 12:29:56.999559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
16212 12:29:56.999929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
16214 12:29:57.039458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass>
16215 12:29:57.039911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass
16217 12:29:57.079680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
16219 12:29:57.080004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
16220 12:29:57.119133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
16221 12:29:57.119506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
16223 12:29:57.157584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
16224 12:29:57.157886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
16226 12:29:57.196871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass>
16227 12:29:57.197339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass
16229 12:29:57.235745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
16231 12:29:57.236094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
16232 12:29:57.274788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
16233 12:29:57.275080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
16235 12:29:57.313853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
16237 12:29:57.314479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
16238 12:29:57.355533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass>
16239 12:29:57.356021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass
16241 12:29:57.396210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
16242 12:29:57.396687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
16244 12:29:57.437467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
16246 12:29:57.437962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
16247 12:29:57.476615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
16248 12:29:57.477044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
16250 12:29:57.516326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass>
16251 12:29:57.516774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass
16253 12:29:57.556097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
16254 12:29:57.556515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
16256 12:29:57.596766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
16258 12:29:57.597236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
16259 12:29:57.635579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
16260 12:29:57.636011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
16262 12:29:57.674457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass>
16263 12:29:57.674899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass
16265 12:29:57.712648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
16266 12:29:57.713036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
16268 12:29:57.751374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
16269 12:29:57.751793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
16271 12:29:57.789678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
16272 12:29:57.790099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
16274 12:29:57.828933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass
16276 12:29:57.829390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass>
16277 12:29:57.867805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
16279 12:29:57.868254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
16280 12:29:57.907054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
16281 12:29:57.907475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
16283 12:29:57.951665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
16284 12:29:57.952161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
16286 12:29:58.005576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass
16288 12:29:58.006239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass>
16289 12:29:58.057735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
16291 12:29:58.058353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
16292 12:29:58.098604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
16294 12:29:58.099084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
16295 12:29:58.134595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
16296 12:29:58.135047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
16298 12:29:58.172130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass>
16299 12:29:58.172576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass
16301 12:29:58.207827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
16303 12:29:58.208290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
16304 12:29:58.243397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
16306 12:29:58.243846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
16307 12:29:58.279013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
16309 12:29:58.279725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
16310 12:29:58.313264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass>
16311 12:29:58.313692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass
16313 12:29:58.348302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
16315 12:29:58.348850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
16316 12:29:58.383433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
16317 12:29:58.383789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
16319 12:29:58.417711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
16321 12:29:58.418226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
16322 12:29:58.453641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass
16324 12:29:58.454101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass>
16325 12:29:58.491753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
16326 12:29:58.492056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
16328 12:29:58.527018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
16329 12:29:58.527425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
16331 12:29:58.561640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
16332 12:29:58.562101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
16334 12:29:58.596822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass>
16335 12:29:58.597297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass
16337 12:29:58.633012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
16339 12:29:58.633581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
16340 12:29:58.669410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
16341 12:29:58.669916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
16343 12:29:58.706299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
16345 12:29:58.707018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
16346 12:29:58.744945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass
16348 12:29:58.745556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass>
16349 12:29:58.782177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
16351 12:29:58.782649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
16352 12:29:58.818294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
16354 12:29:58.819033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
16355 12:29:58.859006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
16357 12:29:58.859478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
16358 12:29:58.896613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass>
16359 12:29:58.897050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass
16361 12:29:58.931286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
16362 12:29:58.931650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
16364 12:29:58.967099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
16365 12:29:58.967553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
16367 12:29:59.003585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
16368 12:29:59.004091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
16370 12:29:59.039992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass
16372 12:29:59.040574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass>
16373 12:29:59.075110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
16374 12:29:59.075565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
16376 12:29:59.110208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
16378 12:29:59.110685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
16379 12:29:59.145504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
16380 12:29:59.145962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
16382 12:29:59.180611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass>
16383 12:29:59.180991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass
16385 12:29:59.216078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
16386 12:29:59.216541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
16388 12:29:59.251525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
16389 12:29:59.251997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
16391 12:29:59.287635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
16393 12:29:59.288204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
16394 12:29:59.324093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass>
16395 12:29:59.324555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass
16397 12:29:59.359525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
16399 12:29:59.359984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
16400 12:29:59.395957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
16401 12:29:59.396391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
16403 12:29:59.431535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
16404 12:29:59.431978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
16406 12:29:59.467672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass>
16407 12:29:59.468121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass
16409 12:29:59.503539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
16411 12:29:59.504013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
16412 12:29:59.539450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
16414 12:29:59.540022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
16415 12:29:59.575043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
16417 12:29:59.575479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
16418 12:29:59.617788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass>
16419 12:29:59.618271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass
16421 12:29:59.653367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
16423 12:29:59.653854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
16424 12:29:59.688922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
16425 12:29:59.689339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
16427 12:29:59.725412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
16428 12:29:59.725873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
16430 12:29:59.761719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass>
16431 12:29:59.762174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass
16433 12:29:59.797326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
16434 12:29:59.797832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
16436 12:29:59.834579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
16438 12:29:59.835165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
16439 12:29:59.869620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
16440 12:29:59.870113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
16442 12:29:59.906517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass>
16443 12:29:59.906958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass
16445 12:29:59.942936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
16447 12:29:59.943447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
16448 12:29:59.978845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
16449 12:29:59.979263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
16451 12:30:00.014317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
16453 12:30:00.014771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
16454 12:30:00.049810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass
16456 12:30:00.050349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass>
16457 12:30:00.088873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
16458 12:30:00.089301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
16460 12:30:00.125449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
16462 12:30:00.125927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
16463 12:30:00.160634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
16465 12:30:00.161103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
16466 12:30:00.196417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass
16468 12:30:00.196875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass>
16469 12:30:00.231664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
16470 12:30:00.232160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
16472 12:30:00.267943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
16473 12:30:00.268469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
16475 12:30:00.303978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
16477 12:30:00.304588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
16478 12:30:00.339060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass>
16479 12:30:00.339503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass
16481 12:30:00.380485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
16483 12:30:00.381047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
16484 12:30:00.417164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
16485 12:30:00.417555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
16487 12:30:00.455392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
16488 12:30:00.455799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
16490 12:30:00.492669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass>
16491 12:30:00.493100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass
16493 12:30:00.528933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
16495 12:30:00.529492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
16496 12:30:00.565043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
16498 12:30:00.565428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
16499 12:30:00.601488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
16500 12:30:00.601895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
16502 12:30:00.639416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass>
16503 12:30:00.639758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass
16505 12:30:00.676077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
16506 12:30:00.676470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
16508 12:30:00.713582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
16510 12:30:00.714176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
16511 12:30:00.749404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
16512 12:30:00.749849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
16514 12:30:00.793557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass
16516 12:30:00.794058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass>
16517 12:30:00.833084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
16518 12:30:00.833592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
16520 12:30:00.869192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
16521 12:30:00.869710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
16523 12:30:00.905524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
16525 12:30:00.906000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
16526 12:30:00.940635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass>
16527 12:30:00.941104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass
16529 12:30:00.977396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
16531 12:30:00.977869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
16532 12:30:01.015648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
16534 12:30:01.016105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
16535 12:30:01.052458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
16537 12:30:01.052915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
16538 12:30:01.089090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass>
16539 12:30:01.089527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass
16541 12:30:01.125417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
16542 12:30:01.125873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
16544 12:30:01.163469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
16545 12:30:01.163875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
16547 12:30:01.201612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
16548 12:30:01.202166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
16550 12:30:01.238254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass
16552 12:30:01.238744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass>
16553 12:30:01.275559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
16554 12:30:01.275992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
16556 12:30:01.311471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
16557 12:30:01.311881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
16559 12:30:01.350727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
16560 12:30:01.351169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
16562 12:30:01.389125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass>
16563 12:30:01.389531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass
16565 12:30:01.425689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
16566 12:30:01.426062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
16568 12:30:01.462659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
16569 12:30:01.463103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
16571 12:30:01.500394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
16572 12:30:01.500712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
16574 12:30:01.539581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass>
16575 12:30:01.540004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass
16577 12:30:01.577041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
16578 12:30:01.577469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
16580 12:30:01.613417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
16581 12:30:01.613867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
16583 12:30:01.660279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
16585 12:30:01.660777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
16586 12:30:01.703585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass
16588 12:30:01.703978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass>
16589 12:30:01.741323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
16591 12:30:01.741803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
16592 12:30:01.777551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
16593 12:30:01.778015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
16595 12:30:01.814825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
16596 12:30:01.815277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
16598 12:30:01.853542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass>
16599 12:30:01.854011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass
16601 12:30:01.899049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
16602 12:30:01.899499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
16604 12:30:01.938925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
16605 12:30:01.939503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
16607 12:30:01.978339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
16609 12:30:01.978826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
16610 12:30:02.022239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass
16612 12:30:02.022714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass>
16613 12:30:02.059714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
16614 12:30:02.060153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
16616 12:30:02.098915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
16618 12:30:02.099403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
16619 12:30:02.135268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
16621 12:30:02.135754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
16622 12:30:02.172609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass
16624 12:30:02.173351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass>
16625 12:30:02.211024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
16627 12:30:02.211632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
16628 12:30:02.251322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
16630 12:30:02.251710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
16631 12:30:02.285302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
16632 12:30:02.285687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
16634 12:30:02.323408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass
16636 12:30:02.323916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass>
16637 12:30:02.367138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
16638 12:30:02.367658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
16640 12:30:02.410925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
16641 12:30:02.411469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
16643 12:30:02.461772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
16645 12:30:02.462173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
16646 12:30:02.513230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass>
16647 12:30:02.513610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass
16649 12:30:02.566333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
16651 12:30:02.566706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
16652 12:30:02.619349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
16653 12:30:02.619730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
16655 12:30:02.668250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
16656 12:30:02.668632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
16658 12:30:02.705067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass
16660 12:30:02.705539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass>
16661 12:30:02.739276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
16662 12:30:02.739815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
16664 12:30:02.777371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
16666 12:30:02.777995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
16667 12:30:02.812304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
16668 12:30:02.812780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
16670 12:30:02.848096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass>
16671 12:30:02.848595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass
16673 12:30:02.883977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
16675 12:30:02.884631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
16676 12:30:02.921582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
16677 12:30:02.922050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
16679 12:30:02.959557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
16680 12:30:02.960075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
16682 12:30:02.995752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass>
16683 12:30:02.996206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass
16685 12:30:03.031008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
16686 12:30:03.031467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
16688 12:30:03.068057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
16689 12:30:03.068537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
16691 12:30:03.105284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
16692 12:30:03.105749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
16694 12:30:03.144435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass>
16695 12:30:03.144886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass
16697 12:30:03.193505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
16699 12:30:03.194006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
16700 12:30:03.233341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
16701 12:30:03.233787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
16703 12:30:03.270115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
16705 12:30:03.270744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
16706 12:30:03.307214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass
16708 12:30:03.307700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass>
16709 12:30:03.345727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
16710 12:30:03.346175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
16712 12:30:03.380373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
16713 12:30:03.380821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
16715 12:30:03.417906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
16716 12:30:03.418337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
16718 12:30:03.451272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass>
16719 12:30:03.451657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass
16721 12:30:03.486140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
16722 12:30:03.486575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
16724 12:30:03.528033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
16726 12:30:03.528447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
16727 12:30:03.564210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
16728 12:30:03.564607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
16730 12:30:03.599277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass
16732 12:30:03.599719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass>
16733 12:30:03.633622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
16734 12:30:03.634078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
16736 12:30:03.675249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
16737 12:30:03.675681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
16739 12:30:03.716533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
16740 12:30:03.717030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
16742 12:30:03.753708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass>
16743 12:30:03.754070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass
16745 12:30:03.788335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
16746 12:30:03.788756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
16748 12:30:03.824296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
16749 12:30:03.824800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
16751 12:30:03.863931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
16752 12:30:03.864529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
16754 12:30:03.900460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass
16756 12:30:03.900931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass>
16757 12:30:03.937405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
16759 12:30:03.937888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
16760 12:30:03.972342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
16762 12:30:03.972810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
16763 12:30:04.010476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
16765 12:30:04.010896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
16766 12:30:04.048984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass
16768 12:30:04.049392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass>
16769 12:30:04.083927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
16771 12:30:04.084441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
16772 12:30:04.119366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
16773 12:30:04.119822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
16775 12:30:04.154038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
16777 12:30:04.154519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
16778 12:30:04.191181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass
16780 12:30:04.191650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass>
16781 12:30:04.228220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
16782 12:30:04.228643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
16784 12:30:04.263150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
16786 12:30:04.263626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
16787 12:30:04.299535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
16789 12:30:04.299994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
16790 12:30:04.336021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass
16792 12:30:04.336495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass>
16793 12:30:04.375437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
16794 12:30:04.375863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
16796 12:30:04.417207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
16797 12:30:04.417628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
16799 12:30:04.455230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
16800 12:30:04.455670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
16802 12:30:04.492535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass>
16803 12:30:04.492948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass
16805 12:30:04.531043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
16807 12:30:04.531688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
16808 12:30:04.568519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
16810 12:30:04.569179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
16811 12:30:04.605198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
16812 12:30:04.605703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
16814 12:30:04.641472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass>
16815 12:30:04.641939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass
16817 12:30:04.677633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
16818 12:30:04.678113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
16820 12:30:04.717523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
16821 12:30:04.717971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
16823 12:30:04.754181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
16825 12:30:04.754664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
16826 12:30:04.789540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass>
16827 12:30:04.789986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass
16829 12:30:04.824607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
16830 12:30:04.825049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
16832 12:30:04.860267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
16834 12:30:04.860736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
16835 12:30:04.898233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
16837 12:30:04.898712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
16838 12:30:04.942174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass
16840 12:30:04.942692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass>
16841 12:30:04.978009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
16842 12:30:04.978493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
16844 12:30:05.015075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
16845 12:30:05.015598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
16847 12:30:05.051225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
16849 12:30:05.051859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
16850 12:30:05.086918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass>
16851 12:30:05.087333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass
16853 12:30:05.125017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
16854 12:30:05.125461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
16856 12:30:05.159354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
16857 12:30:05.159784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
16859 12:30:05.194742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
16860 12:30:05.195224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
16862 12:30:05.229111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass>
16863 12:30:05.229495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass
16865 12:30:05.262850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
16866 12:30:05.263231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
16868 12:30:05.296133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
16870 12:30:05.296500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
16871 12:30:05.329168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
16872 12:30:05.329583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
16874 12:30:05.363013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass>
16875 12:30:05.363461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass
16877 12:30:05.399003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
16879 12:30:05.399466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
16880 12:30:05.431190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
16882 12:30:05.431596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
16883 12:30:05.464243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
16884 12:30:05.464649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
16886 12:30:05.497885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass
16888 12:30:05.498520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass>
16889 12:30:05.529826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
16890 12:30:05.530296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
16892 12:30:05.562413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
16894 12:30:05.563003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
16895 12:30:05.594927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
16896 12:30:05.595388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
16898 12:30:05.628340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass>
16899 12:30:05.628819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass
16901 12:30:05.663374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
16903 12:30:05.663938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
16904 12:30:05.695713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
16906 12:30:05.696357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
16907 12:30:05.729465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
16908 12:30:05.729862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
16910 12:30:05.765175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass
16912 12:30:05.766057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass>
16913 12:30:05.802252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
16915 12:30:05.802727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
16916 12:30:05.840612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
16917 12:30:05.841036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
16919 12:30:05.877135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
16920 12:30:05.877578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
16922 12:30:05.911279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass>
16923 12:30:05.911734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass
16925 12:30:05.943509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
16926 12:30:05.943887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
16928 12:30:05.975793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
16930 12:30:05.976385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
16931 12:30:06.009108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
16933 12:30:06.009716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
16934 12:30:06.043111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass>
16935 12:30:06.043594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass
16937 12:30:06.080381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
16938 12:30:06.080765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
16940 12:30:06.115411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
16942 12:30:06.115782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
16943 12:30:06.150696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
16944 12:30:06.151080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
16946 12:30:06.186751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass>
16947 12:30:06.187260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass
16949 12:30:06.223304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
16950 12:30:06.223765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
16952 12:30:06.257923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
16953 12:30:06.258393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
16955 12:30:06.291690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
16956 12:30:06.292136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
16958 12:30:06.327687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass>
16959 12:30:06.328139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass
16961 12:30:06.364135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
16963 12:30:06.364604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
16964 12:30:06.400202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
16965 12:30:06.400617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
16967 12:30:06.435637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
16968 12:30:06.436097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
16970 12:30:06.471686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass
16972 12:30:06.472401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass>
16973 12:30:06.507035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
16974 12:30:06.507450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
16976 12:30:06.543700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
16977 12:30:06.544125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
16979 12:30:06.582980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
16981 12:30:06.583444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
16982 12:30:06.617823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass
16984 12:30:06.618319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass>
16985 12:30:06.652063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
16987 12:30:06.652569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
16988 12:30:06.687474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
16989 12:30:06.687902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
16991 12:30:06.723290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
16993 12:30:06.723760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
16994 12:30:06.759708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass
16996 12:30:06.760218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass>
16997 12:30:06.794760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
16998 12:30:06.795245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
17000 12:30:06.838427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
17002 12:30:06.839012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
17003 12:30:06.871006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
17004 12:30:06.871484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
17006 12:30:06.903499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass
17008 12:30:06.904170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass>
17009 12:30:06.940935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
17010 12:30:06.941479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
17012 12:30:06.976073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
17014 12:30:06.976646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
17015 12:30:07.009617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
17016 12:30:07.010140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
17018 12:30:07.048941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass
17020 12:30:07.049416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass>
17021 12:30:07.088911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
17023 12:30:07.089492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
17024 12:30:07.133718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
17025 12:30:07.134135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
17027 12:30:07.172953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
17028 12:30:07.173490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
17030 12:30:07.213685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass>
17031 12:30:07.214195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass
17033 12:30:07.256942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
17035 12:30:07.257447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
17036 12:30:07.298211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
17038 12:30:07.298608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
17039 12:30:07.339150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
17040 12:30:07.339562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
17042 12:30:07.380820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass>
17043 12:30:07.381256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass
17045 12:30:07.421049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
17046 12:30:07.421419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
17048 12:30:07.463675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
17049 12:30:07.464124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
17051 12:30:07.505246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
17053 12:30:07.505738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
17054 12:30:07.546117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass
17056 12:30:07.546608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass>
17057 12:30:07.587493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
17058 12:30:07.587936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
17060 12:30:07.628682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
17062 12:30:07.629071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
17063 12:30:07.667641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
17064 12:30:07.668061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
17066 12:30:07.706899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass>
17067 12:30:07.707328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass
17069 12:30:07.744752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
17071 12:30:07.745416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
17072 12:30:07.783789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
17074 12:30:07.784171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
17075 12:30:07.823297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
17076 12:30:07.823862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
17078 12:30:07.862805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass
17080 12:30:07.863395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass>
17081 12:30:07.900202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
17082 12:30:07.900621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
17084 12:30:07.937956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
17086 12:30:07.938436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
17087 12:30:07.979080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
17088 12:30:07.979489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
17090 12:30:08.017358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass>
17091 12:30:08.017801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass
17093 12:30:08.057455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
17094 12:30:08.057897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
17096 12:30:08.096337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
17097 12:30:08.096710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
17099 12:30:08.134183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
17101 12:30:08.134595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
17102 12:30:08.183974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass>
17103 12:30:08.184456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass
17105 12:30:08.229934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
17106 12:30:08.230325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
17108 12:30:08.269167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
17109 12:30:08.269560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
17111 12:30:08.307918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
17113 12:30:08.308323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
17114 12:30:08.344792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass>
17115 12:30:08.345213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass
17117 12:30:08.384581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
17118 12:30:08.385018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
17120 12:30:08.424933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
17122 12:30:08.425425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
17123 12:30:08.459156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
17124 12:30:08.459563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
17126 12:30:08.493852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass
17128 12:30:08.494356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass>
17129 12:30:08.530968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
17131 12:30:08.531430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
17132 12:30:08.568387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
17133 12:30:08.568806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
17135 12:30:08.603448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
17136 12:30:08.603911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
17138 12:30:08.639423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass
17140 12:30:08.639884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass>
17141 12:30:08.678146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
17143 12:30:08.678925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
17144 12:30:08.714366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
17146 12:30:08.714881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
17147 12:30:08.760826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
17149 12:30:08.761322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
17150 12:30:08.800162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass
17152 12:30:08.800592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass>
17153 12:30:08.838136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
17155 12:30:08.838586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
17156 12:30:08.872297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
17157 12:30:08.872699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
17159 12:30:08.906724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
17160 12:30:08.907177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
17162 12:30:08.940896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass>
17163 12:30:08.941377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass
17165 12:30:08.972685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
17166 12:30:08.973123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
17168 12:30:09.003836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
17169 12:30:09.004214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
17171 12:30:09.037012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
17172 12:30:09.037433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
17174 12:30:09.071933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass>
17175 12:30:09.072393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass
17177 12:30:09.107866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
17179 12:30:09.108458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
17180 12:30:09.144252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
17181 12:30:09.144782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
17183 12:30:09.176829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
17184 12:30:09.177316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
17186 12:30:09.211007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass
17188 12:30:09.211384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass>
17189 12:30:09.244937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
17190 12:30:09.245371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
17192 12:30:09.281519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
17193 12:30:09.281973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
17195 12:30:09.318741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
17196 12:30:09.319202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
17198 12:30:09.355834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass>
17199 12:30:09.356215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass
17201 12:30:09.388812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
17203 12:30:09.389393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
17204 12:30:09.424735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
17206 12:30:09.425312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
17207 12:30:09.464925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
17208 12:30:09.465331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
17210 12:30:09.500614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass>
17211 12:30:09.501000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass
17213 12:30:09.536308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
17215 12:30:09.536688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
17216 12:30:09.568762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
17218 12:30:09.569198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
17219 12:30:09.603660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
17220 12:30:09.604106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
17222 12:30:09.637680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass>
17223 12:30:09.638098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass
17225 12:30:09.671828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
17226 12:30:09.672244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
17228 12:30:09.704852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
17229 12:30:09.705330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
17231 12:30:09.737386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
17232 12:30:09.737870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
17234 12:30:09.769515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass>
17235 12:30:09.769985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass
17237 12:30:09.801243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
17238 12:30:09.801678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
17240 12:30:09.834072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
17242 12:30:09.834542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
17243 12:30:09.867562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
17244 12:30:09.868002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
17246 12:30:09.900418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass>
17247 12:30:09.900852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass
17249 12:30:09.932300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
17250 12:30:09.932710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
17252 12:30:09.969731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
17254 12:30:09.970312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
17255 12:30:10.002989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
17256 12:30:10.003450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
17258 12:30:10.035442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass>
17259 12:30:10.035886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass
17261 12:30:10.066916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
17262 12:30:10.067392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
17264 12:30:10.098897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
17265 12:30:10.099369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
17267 12:30:10.131421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
17268 12:30:10.131914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
17270 12:30:10.166142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass
17272 12:30:10.166609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass>
17273 12:30:10.201849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
17274 12:30:10.202305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
17276 12:30:10.239383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
17278 12:30:10.239876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
17279 12:30:10.273947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
17281 12:30:10.274325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
17282 12:30:10.309203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass
17284 12:30:10.309670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass>
17285 12:30:10.344025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
17286 12:30:10.344497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
17288 12:30:10.383905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
17289 12:30:10.384288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
17291 12:30:10.417729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
17293 12:30:10.418309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
17294 12:30:10.451562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass>
17295 12:30:10.451931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass
17297 12:30:10.483111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
17298 12:30:10.483589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
17300 12:30:10.514812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
17301 12:30:10.515205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
17303 12:30:10.549634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
17304 12:30:10.550057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
17306 12:30:10.582928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass
17308 12:30:10.583373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass>
17309 12:30:10.616084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
17310 12:30:10.616434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
17312 12:30:10.649113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
17313 12:30:10.649509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
17315 12:30:10.683981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
17316 12:30:10.684389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
17318 12:30:10.722662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass>
17319 12:30:10.723113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass
17321 12:30:10.761200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
17323 12:30:10.761972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
17324 12:30:10.797173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
17326 12:30:10.797636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
17327 12:30:10.829783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
17328 12:30:10.830180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
17330 12:30:10.863469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass
17332 12:30:10.863913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass>
17333 12:30:10.897420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
17335 12:30:10.897885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
17336 12:30:10.930677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
17337 12:30:10.931121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
17339 12:30:10.965361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
17340 12:30:10.965743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
17342 12:30:11.001389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass>
17343 12:30:11.001801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass
17345 12:30:11.037361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
17346 12:30:11.037676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
17348 12:30:11.074508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
17349 12:30:11.074809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
17351 12:30:11.111033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
17352 12:30:11.111409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
17354 12:30:11.148632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass>
17355 12:30:11.149026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass
17357 12:30:11.186177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
17359 12:30:11.186605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
17360 12:30:11.234719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
17362 12:30:11.235293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
17363 12:30:11.268216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
17364 12:30:11.268724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
17366 12:30:11.301085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass>
17367 12:30:11.301562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass
17369 12:30:11.333822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
17370 12:30:11.334317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
17372 12:30:11.369235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
17373 12:30:11.369660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
17375 12:30:11.406612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
17376 12:30:11.407151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
17378 12:30:11.444005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass>
17379 12:30:11.444393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass
17381 12:30:11.481598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
17382 12:30:11.482010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
17384 12:30:11.516010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
17385 12:30:11.516491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
17387 12:30:11.548845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
17389 12:30:11.549443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
17390 12:30:11.582549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass>
17391 12:30:11.583024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass
17393 12:30:11.615720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
17395 12:30:11.616290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
17396 12:30:11.649768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
17397 12:30:11.650191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
17399 12:30:11.683153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
17400 12:30:11.683571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
17402 12:30:11.716174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass>
17403 12:30:11.716675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass
17405 12:30:11.751022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
17407 12:30:11.751611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
17408 12:30:11.784250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
17409 12:30:11.784722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
17411 12:30:11.817717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
17412 12:30:11.818180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
17414 12:30:11.852486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass>
17415 12:30:11.852966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass
17417 12:30:11.885611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
17418 12:30:11.886103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
17420 12:30:11.918760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
17421 12:30:11.919180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
17423 12:30:11.950674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
17425 12:30:11.951435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
17426 12:30:11.983737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass>
17427 12:30:11.984300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass
17429 12:30:12.015358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
17431 12:30:12.015829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
17432 12:30:12.048496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
17433 12:30:12.048904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
17435 12:30:12.083292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
17437 12:30:12.083951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
17438 12:30:12.116731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass>
17439 12:30:12.117159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass
17441 12:30:12.149106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
17442 12:30:12.149566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
17444 12:30:12.182694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
17446 12:30:12.183195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
17447 12:30:12.215369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
17449 12:30:12.215836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
17450 12:30:12.247923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass
17452 12:30:12.248305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass>
17453 12:30:12.280501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
17454 12:30:12.280869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
17456 12:30:12.318391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
17458 12:30:12.319051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
17459 12:30:12.351180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
17460 12:30:12.351634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
17462 12:30:12.383038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass
17464 12:30:12.383789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass>
17465 12:30:12.416193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
17466 12:30:12.416615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
17468 12:30:12.452905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
17469 12:30:12.453359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
17471 12:30:12.487184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
17472 12:30:12.487598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
17474 12:30:12.522961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass>
17475 12:30:12.523380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass
17477 12:30:12.557269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
17478 12:30:12.557687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
17480 12:30:12.592795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
17482 12:30:12.593271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
17483 12:30:12.628900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
17484 12:30:12.629379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
17486 12:30:12.665158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass
17488 12:30:12.665753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass>
17489 12:30:12.699986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
17491 12:30:12.700374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
17492 12:30:12.734674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
17493 12:30:12.735024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
17495 12:30:12.767254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
17496 12:30:12.767694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
17498 12:30:12.800410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass>
17499 12:30:12.800816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass
17501 12:30:12.833250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
17502 12:30:12.833690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
17504 12:30:12.868490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
17505 12:30:12.868963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
17507 12:30:12.902121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
17509 12:30:12.902717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
17510 12:30:12.935667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass>
17511 12:30:12.936216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass
17513 12:30:12.967515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
17514 12:30:12.967952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
17516 12:30:13.001592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
17517 12:30:13.002025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
17519 12:30:13.035871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
17521 12:30:13.036303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
17522 12:30:13.070107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass
17524 12:30:13.070514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass>
17525 12:30:13.102913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
17526 12:30:13.103297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
17528 12:30:13.135374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
17529 12:30:13.135830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
17531 12:30:13.168934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
17533 12:30:13.169532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
17534 12:30:13.201734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass
17536 12:30:13.202417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass>
17537 12:30:13.236057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
17539 12:30:13.236507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
17540 12:30:13.287444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
17541 12:30:13.287866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
17543 12:30:13.340758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
17544 12:30:13.341206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
17546 12:30:13.386661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass
17548 12:30:13.387270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass>
17549 12:30:13.422275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
17551 12:30:13.422764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
17552 12:30:13.461507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
17553 12:30:13.461962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
17555 12:30:13.498194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
17557 12:30:13.498667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
17558 12:30:13.534155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass
17560 12:30:13.534625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass>
17561 12:30:13.570893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
17562 12:30:13.571295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
17564 12:30:13.602764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
17565 12:30:13.603226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
17567 12:30:13.634223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
17569 12:30:13.634759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
17570 12:30:13.667002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass
17572 12:30:13.667560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass>
17573 12:30:13.699906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
17575 12:30:13.700607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
17576 12:30:13.732484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
17578 12:30:13.733247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
17579 12:30:13.765788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
17580 12:30:13.766297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
17582 12:30:13.812658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass
17584 12:30:13.813150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass>
17585 12:30:13.848456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
17586 12:30:13.848873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
17588 12:30:13.883329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
17589 12:30:13.883726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
17591 12:30:13.919615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
17592 12:30:13.920097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
17594 12:30:13.955561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass>
17595 12:30:13.955975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass
17597 12:30:13.992867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
17598 12:30:13.993289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
17600 12:30:14.035214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
17601 12:30:14.035685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
17603 12:30:14.071970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
17604 12:30:14.072367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
17606 12:30:14.104682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass>
17607 12:30:14.105094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass
17609 12:30:14.137877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
17610 12:30:14.138298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
17612 12:30:14.171978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
17613 12:30:14.172465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
17615 12:30:14.207735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
17616 12:30:14.208117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
17618 12:30:14.244242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass>
17619 12:30:14.244629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass
17621 12:30:14.279550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
17622 12:30:14.279938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
17624 12:30:14.315331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
17625 12:30:14.315768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
17627 12:30:14.352620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
17629 12:30:14.353153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
17630 12:30:14.395490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass>
17631 12:30:14.395982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass
17633 12:30:14.431588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
17634 12:30:14.432008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
17636 12:30:14.469394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
17638 12:30:14.469887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
17639 12:30:14.512379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
17640 12:30:14.512794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
17642 12:30:14.554028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass
17644 12:30:14.554553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass>
17645 12:30:14.603982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
17646 12:30:14.604369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
17648 12:30:14.656584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
17649 12:30:14.656995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
17651 12:30:14.702877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
17652 12:30:14.703322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
17654 12:30:14.749804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass>
17655 12:30:14.750234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass
17657 12:30:14.790583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
17658 12:30:14.791006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
17660 12:30:14.839566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
17661 12:30:14.839970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
17663 12:30:14.875783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
17664 12:30:14.876216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
17666 12:30:14.915957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass>
17667 12:30:14.916402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass
17669 12:30:14.952219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
17670 12:30:14.952643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
17672 12:30:14.988328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
17673 12:30:14.988721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
17675 12:30:15.028354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
17676 12:30:15.028884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
17678 12:30:15.079992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass
17680 12:30:15.080739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass>
17681 12:30:15.128229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
17683 12:30:15.128657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
17684 12:30:15.173472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
17685 12:30:15.173914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
17687 12:30:15.207416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
17688 12:30:15.207866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
17690 12:30:15.244785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass
17692 12:30:15.245264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass>
17693 12:30:15.293175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
17695 12:30:15.293693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
17696 12:30:15.347772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
17697 12:30:15.348198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
17699 12:30:15.396463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
17700 12:30:15.396943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
17702 12:30:15.430891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass
17704 12:30:15.431348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass>
17705 12:30:15.464084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
17707 12:30:15.464531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
17708 12:30:15.497536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
17709 12:30:15.497957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
17711 12:30:15.530677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
17712 12:30:15.531091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
17714 12:30:15.563739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass>
17715 12:30:15.564228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass
17717 12:30:15.597438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
17719 12:30:15.598056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
17720 12:30:15.630738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
17722 12:30:15.631334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
17723 12:30:15.663445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
17724 12:30:15.663904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
17726 12:30:15.695444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass
17728 12:30:15.695909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass>
17729 12:30:15.729655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
17730 12:30:15.730072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
17732 12:30:15.763050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
17733 12:30:15.763480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
17735 12:30:15.795397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
17736 12:30:15.795807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
17738 12:30:15.828612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass>
17739 12:30:15.829093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass
17741 12:30:15.863089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
17742 12:30:15.863581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
17744 12:30:15.895520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
17745 12:30:15.895967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
17747 12:30:15.928348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
17749 12:30:15.928840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
17750 12:30:15.961585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass
17752 12:30:15.962129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass>
17753 12:30:15.995185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
17754 12:30:15.995769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
17756 12:30:16.027957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
17757 12:30:16.028415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
17759 12:30:16.060939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
17760 12:30:16.061459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
17762 12:30:16.093907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass>
17763 12:30:16.094378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass
17765 12:30:16.127270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
17766 12:30:16.127747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
17768 12:30:16.159515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
17770 12:30:16.160184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
17771 12:30:16.192465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
17773 12:30:16.193060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
17774 12:30:16.225103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass>
17775 12:30:16.225547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass
17777 12:30:16.257278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
17779 12:30:16.257748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
17780 12:30:16.291237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
17782 12:30:16.291680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
17783 12:30:16.323415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
17784 12:30:16.323825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
17786 12:30:16.355624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass>
17787 12:30:16.356031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass
17789 12:30:16.388471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
17790 12:30:16.388883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
17792 12:30:16.420736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
17793 12:30:16.421203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
17795 12:30:16.453852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
17796 12:30:16.454274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
17798 12:30:16.486981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass>
17799 12:30:16.487401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass
17801 12:30:16.519435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
17803 12:30:16.519909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
17804 12:30:16.551826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
17805 12:30:16.552281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
17807 12:30:16.589825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
17808 12:30:16.590368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
17810 12:30:16.623831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass>
17811 12:30:16.624295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass
17813 12:30:16.656359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
17814 12:30:16.656810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
17816 12:30:16.689798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
17818 12:30:16.690536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
17819 12:30:16.722949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
17820 12:30:16.723412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
17822 12:30:16.755245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass>
17823 12:30:16.755739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass
17825 12:30:16.788531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
17827 12:30:16.789100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
17828 12:30:16.820997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
17829 12:30:16.821414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
17831 12:30:16.853617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
17832 12:30:16.854118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
17834 12:30:16.887124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass>
17835 12:30:16.887604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass
17837 12:30:16.919596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
17838 12:30:16.920093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
17840 12:30:16.951942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
17842 12:30:16.952507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
17843 12:30:16.985104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
17844 12:30:16.985588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
17846 12:30:17.017737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass>
17847 12:30:17.018213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass
17849 12:30:17.051023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
17850 12:30:17.051490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
17852 12:30:17.083513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
17853 12:30:17.084027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
17855 12:30:17.117311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
17857 12:30:17.117959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
17858 12:30:17.150658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass>
17859 12:30:17.151134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass
17861 12:30:17.182914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
17862 12:30:17.183372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
17864 12:30:17.215561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
17865 12:30:17.215988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
17867 12:30:17.247776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
17868 12:30:17.248277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
17870 12:30:17.280151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass
17872 12:30:17.280614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass>
17873 12:30:17.312666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
17874 12:30:17.313067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
17876 12:30:17.345351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
17877 12:30:17.345737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
17879 12:30:17.376828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
17880 12:30:17.377211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
17882 12:30:17.408556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass>
17883 12:30:17.409036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass
17885 12:30:17.440888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
17887 12:30:17.441476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
17888 12:30:17.474719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
17890 12:30:17.475197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
17891 12:30:17.507648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
17893 12:30:17.508134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
17894 12:30:17.541100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass
17896 12:30:17.541578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass>
17897 12:30:17.573954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
17898 12:30:17.574380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
17900 12:30:17.607529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
17901 12:30:17.607963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
17903 12:30:17.640537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
17904 12:30:17.640944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
17906 12:30:17.674408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass>
17907 12:30:17.674805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass
17909 12:30:17.706943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
17910 12:30:17.707339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
17912 12:30:17.739121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
17913 12:30:17.739577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
17915 12:30:17.771278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
17916 12:30:17.771685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
17918 12:30:17.802766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass>
17919 12:30:17.803322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass
17921 12:30:17.836259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
17922 12:30:17.836751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
17924 12:30:17.869774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
17925 12:30:17.870188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
17927 12:30:17.903355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
17929 12:30:17.904016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
17930 12:30:17.936465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass
17932 12:30:17.937102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass>
17933 12:30:17.968703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
17934 12:30:17.969112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
17936 12:30:18.000771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
17938 12:30:18.001208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
17939 12:30:18.033281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
17940 12:30:18.033690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
17942 12:30:18.066124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass
17944 12:30:18.066721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass>
17945 12:30:18.099001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
17946 12:30:18.099488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
17948 12:30:18.131858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
17950 12:30:18.132448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
17951 12:30:18.163654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
17952 12:30:18.164135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
17954 12:30:18.196458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass
17956 12:30:18.196980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass>
17957 12:30:18.228772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
17958 12:30:18.229255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
17960 12:30:18.261939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
17962 12:30:18.262584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
17963 12:30:18.294174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
17965 12:30:18.294852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
17966 12:30:18.326971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass
17968 12:30:18.327541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass>
17969 12:30:18.359078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
17970 12:30:18.359534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
17972 12:30:18.392587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
17973 12:30:18.393089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
17975 12:30:18.424932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
17976 12:30:18.425369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
17978 12:30:18.475226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass>
17979 12:30:18.475706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass
17981 12:30:18.507267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
17982 12:30:18.507695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
17984 12:30:18.539713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
17985 12:30:18.540194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
17987 12:30:18.572904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
17989 12:30:18.573352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
17990 12:30:18.605888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass
17992 12:30:18.606527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass>
17993 12:30:18.638693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
17994 12:30:18.639129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
17996 12:30:18.671464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
17997 12:30:18.671959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
17999 12:30:18.716137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
18000 12:30:18.716546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
18002 12:30:18.754956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass>
18003 12:30:18.755389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass
18005 12:30:18.787330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
18007 12:30:18.787785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
18008 12:30:18.821118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
18009 12:30:18.821525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
18011 12:30:18.854471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
18012 12:30:18.854887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
18014 12:30:18.888401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass
18016 12:30:18.888832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass>
18017 12:30:18.921631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
18018 12:30:18.922024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
18020 12:30:18.955512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
18021 12:30:18.955871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
18023 12:30:18.989507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
18024 12:30:18.989997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
18026 12:30:19.023969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass
18028 12:30:19.024439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass>
18029 12:30:19.056405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
18030 12:30:19.056841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
18032 12:30:19.089131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
18034 12:30:19.089706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
18035 12:30:19.121325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
18036 12:30:19.121742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
18038 12:30:19.153666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass>
18039 12:30:19.154088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass
18041 12:30:19.186787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
18043 12:30:19.187270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
18044 12:30:19.219261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
18045 12:30:19.219676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
18047 12:30:19.252499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
18048 12:30:19.252919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
18050 12:30:19.286619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass
18052 12:30:19.287083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass>
18053 12:30:19.319125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
18055 12:30:19.319572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
18056 12:30:19.351674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
18057 12:30:19.352094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
18059 12:30:19.384333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
18060 12:30:19.384770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
18062 12:30:19.417269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass>
18063 12:30:19.417688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass
18065 12:30:19.449729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
18066 12:30:19.450155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
18068 12:30:19.482986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
18069 12:30:19.483415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
18071 12:30:19.516480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
18072 12:30:19.516908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
18074 12:30:19.549167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass>
18075 12:30:19.549591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass
18077 12:30:19.582255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
18079 12:30:19.582665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
18080 12:30:19.617491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
18082 12:30:19.618071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
18083 12:30:19.655184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
18085 12:30:19.655625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
18086 12:30:19.687572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass
18088 12:30:19.688160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass>
18089 12:30:19.720339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
18090 12:30:19.720746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
18092 12:30:19.753258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
18094 12:30:19.753703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
18095 12:30:19.786809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
18097 12:30:19.787291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
18098 12:30:19.820332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass>
18099 12:30:19.820795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass
18101 12:30:19.852856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
18102 12:30:19.853338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
18104 12:30:19.885527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
18105 12:30:19.886038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
18107 12:30:19.918270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
18109 12:30:19.918834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
18110 12:30:19.951024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass>
18111 12:30:19.951503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass
18113 12:30:19.983354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
18114 12:30:19.983825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
18116 12:30:20.016495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
18117 12:30:20.016900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
18119 12:30:20.048506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
18121 12:30:20.048937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
18122 12:30:20.081854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass>
18123 12:30:20.082251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass
18125 12:30:20.115360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
18126 12:30:20.115773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
18128 12:30:20.147829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
18129 12:30:20.148250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
18131 12:30:20.181171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
18132 12:30:20.181599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
18134 12:30:20.213919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass
18136 12:30:20.214398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass>
18137 12:30:20.246852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
18138 12:30:20.247242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
18140 12:30:20.278585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
18142 12:30:20.279042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
18143 12:30:20.310716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
18144 12:30:20.311153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
18146 12:30:20.343537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass>
18147 12:30:20.343982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass
18149 12:30:20.376712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
18150 12:30:20.377126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
18152 12:30:20.409431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
18153 12:30:20.409857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
18155 12:30:20.443544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
18156 12:30:20.443967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
18158 12:30:20.477669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass
18160 12:30:20.478111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass>
18161 12:30:20.511309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
18163 12:30:20.511745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
18164 12:30:20.545432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
18165 12:30:20.545928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
18167 12:30:20.578556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
18169 12:30:20.579120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
18170 12:30:20.615308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass>
18171 12:30:20.615765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass
18173 12:30:20.650748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
18175 12:30:20.651207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
18176 12:30:20.684577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
18177 12:30:20.685009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
18179 12:30:20.717764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
18180 12:30:20.718205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
18182 12:30:20.751222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass>
18183 12:30:20.751658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass
18185 12:30:20.785329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
18186 12:30:20.785766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
18188 12:30:20.820239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
18189 12:30:20.820670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
18191 12:30:20.853652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
18192 12:30:20.854093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
18194 12:30:20.889728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass
18196 12:30:20.890493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass>
18197 12:30:20.927496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
18198 12:30:20.927995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
18200 12:30:20.961602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
18202 12:30:20.962067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
18203 12:30:20.994708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
18204 12:30:20.995099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
18206 12:30:21.028482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass
18208 12:30:21.029154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass>
18209 12:30:21.061329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
18211 12:30:21.062050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
18212 12:30:21.093492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
18214 12:30:21.094068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
18215 12:30:21.126077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
18216 12:30:21.126559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
18218 12:30:21.161324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass>
18219 12:30:21.161738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass
18221 12:30:21.195795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
18222 12:30:21.196288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
18224 12:30:21.239973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
18225 12:30:21.240439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
18227 12:30:21.280974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
18228 12:30:21.281372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
18230 12:30:21.316091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass>
18231 12:30:21.316489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass
18233 12:30:21.352575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
18235 12:30:21.353013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
18236 12:30:21.392058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
18237 12:30:21.392459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
18239 12:30:21.439843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
18240 12:30:21.440311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
18242 12:30:21.479843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass
18244 12:30:21.480222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass>
18245 12:30:21.513298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
18246 12:30:21.513777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
18248 12:30:21.545828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
18249 12:30:21.546305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
18251 12:30:21.579055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
18253 12:30:21.579511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
18254 12:30:21.611097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass>
18255 12:30:21.611531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass
18257 12:30:21.644587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
18258 12:30:21.644994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
18260 12:30:21.683987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
18261 12:30:21.684475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
18263 12:30:21.721310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
18264 12:30:21.721740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
18266 12:30:21.760644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass>
18267 12:30:21.761070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass
18269 12:30:21.797979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
18270 12:30:21.798394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
18272 12:30:21.833555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
18273 12:30:21.833976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
18275 12:30:21.869266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
18276 12:30:21.869693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
18278 12:30:21.906983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass
18280 12:30:21.907442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass>
18281 12:30:21.944243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
18283 12:30:21.944971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
18284 12:30:21.981657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
18285 12:30:21.982056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
18287 12:30:22.019374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
18288 12:30:22.019768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
18290 12:30:22.056787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass>
18291 12:30:22.057192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass
18293 12:30:22.094793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
18294 12:30:22.095212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
18296 12:30:22.132372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
18297 12:30:22.132780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
18299 12:30:22.169705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
18300 12:30:22.170175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
18302 12:30:22.207487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass>
18303 12:30:22.207880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass
18305 12:30:22.244947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
18306 12:30:22.245351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
18308 12:30:22.281201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
18309 12:30:22.281525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
18311 12:30:22.319251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
18313 12:30:22.319630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
18314 12:30:22.357901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass
18316 12:30:22.358228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass>
18317 12:30:22.395612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
18318 12:30:22.395936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
18320 12:30:22.432118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
18322 12:30:22.432587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
18323 12:30:22.470140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
18324 12:30:22.470719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
18326 12:30:22.510863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass
18328 12:30:22.511417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass>
18329 12:30:22.570860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
18330 12:30:22.571286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
18332 12:30:22.631070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
18333 12:30:22.631545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
18335 12:30:22.692289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
18336 12:30:22.692732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
18338 12:30:22.748045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass>
18339 12:30:22.748481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass
18341 12:30:22.790265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
18343 12:30:22.791129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
18344 12:30:22.841284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
18345 12:30:22.841776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
18347 12:30:22.889193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
18348 12:30:22.889607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
18350 12:30:22.935574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass>
18351 12:30:22.936071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass
18353 12:30:22.973638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
18354 12:30:22.974023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
18356 12:30:23.023098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
18357 12:30:23.023580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
18359 12:30:23.068449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
18361 12:30:23.069011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
18362 12:30:23.111545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass
18364 12:30:23.112329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass>
18365 12:30:23.155464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
18366 12:30:23.155891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
18368 12:30:23.196826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
18369 12:30:23.197518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
18371 12:30:23.241711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
18373 12:30:23.242176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
18374 12:30:23.285364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass>
18375 12:30:23.285753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass
18377 12:30:23.339391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
18378 12:30:23.339798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
18380 12:30:23.393465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
18382 12:30:23.394033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
18383 12:30:23.447449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
18384 12:30:23.447898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
18386 12:30:23.503550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass
18388 12:30:23.504093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass>
18389 12:30:23.576518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
18390 12:30:23.576959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
18392 12:30:23.638163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
18394 12:30:23.638599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
18395 12:30:23.689495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
18396 12:30:23.689904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
18398 12:30:23.732391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass
18400 12:30:23.732866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass>
18401 12:30:23.779084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
18402 12:30:23.779450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
18404 12:30:23.831834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
18405 12:30:23.832228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
18407 12:30:23.883523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
18408 12:30:23.883933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
18410 12:30:23.925004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass>
18411 12:30:23.925403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass
18413 12:30:23.969737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
18414 12:30:23.970155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
18416 12:30:24.021774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
18417 12:30:24.022196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
18419 12:30:24.063992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
18420 12:30:24.064397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
18422 12:30:24.108874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass>
18423 12:30:24.109267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass
18425 12:30:24.154883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
18426 12:30:24.155283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
18428 12:30:24.209764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
18429 12:30:24.210166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
18431 12:30:24.246934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
18432 12:30:24.247324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
18434 12:30:24.291410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass>
18435 12:30:24.291882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass
18437 12:30:24.333181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
18438 12:30:24.334318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
18440 12:30:24.376233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
18441 12:30:24.376627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
18443 12:30:24.414881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
18444 12:30:24.415656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
18446 12:30:24.471578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass>
18447 12:30:24.471937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass
18449 12:30:24.516996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
18450 12:30:24.517397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
18452 12:30:24.563149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
18453 12:30:24.563577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
18455 12:30:24.609052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
18456 12:30:24.609481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
18458 12:30:24.651954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass>
18459 12:30:24.652347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass
18461 12:30:24.693214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
18462 12:30:24.693622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
18464 12:30:24.737364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
18465 12:30:24.737765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
18467 12:30:24.781805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
18468 12:30:24.782237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
18470 12:30:24.827217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass
18472 12:30:24.827677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass>
18473 12:30:24.868227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
18474 12:30:24.868663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
18476 12:30:24.909373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
18477 12:30:24.910094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
18479 12:30:24.953076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
18480 12:30:24.954199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
18482 12:30:24.996811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass>
18483 12:30:24.997284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass
18485 12:30:25.033282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
18486 12:30:25.033692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
18488 12:30:25.070760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
18490 12:30:25.071336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
18491 12:30:25.107444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
18492 12:30:25.107894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
18494 12:30:25.145716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass
18496 12:30:25.146281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass>
18497 12:30:25.184405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
18498 12:30:25.184855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
18500 12:30:25.220269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
18501 12:30:25.220742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
18503 12:30:25.257000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
18504 12:30:25.257475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
18506 12:30:25.294165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass
18508 12:30:25.294771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass>
18509 12:30:25.332911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
18510 12:30:25.333380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
18512 12:30:25.372248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
18513 12:30:25.372728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
18515 12:30:25.409012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
18516 12:30:25.409413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
18518 12:30:25.457406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass>
18519 12:30:25.457871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass
18521 12:30:25.516996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
18522 12:30:25.517538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
18524 12:30:25.568644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
18525 12:30:25.569064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
18527 12:30:25.605393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
18528 12:30:25.605794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
18530 12:30:25.647438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass
18532 12:30:25.647872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass>
18533 12:30:25.708410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
18534 12:30:25.708878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
18536 12:30:25.755915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
18538 12:30:25.756383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
18539 12:30:25.807438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
18540 12:30:25.807873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
18542 12:30:25.848923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass
18544 12:30:25.849388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass>
18545 12:30:25.900087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
18547 12:30:25.900504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
18548 12:30:25.952465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
18549 12:30:25.952900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
18551 12:30:25.996420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
18552 12:30:25.996880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
18554 12:30:26.057518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass>
18555 12:30:26.057963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass
18557 12:30:26.102006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
18559 12:30:26.102541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
18560 12:30:26.141292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
18561 12:30:26.141747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
18563 12:30:26.193690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
18564 12:30:26.194124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
18566 12:30:26.236667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass
18568 12:30:26.237134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass>
18569 12:30:26.286220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
18571 12:30:26.286772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
18572 12:30:26.336056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
18573 12:30:26.336485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
18575 12:30:26.379709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
18577 12:30:26.380192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
18578 12:30:26.420041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass>
18579 12:30:26.420495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass
18581 12:30:26.464329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
18583 12:30:26.464814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
18584 12:30:26.518984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
18585 12:30:26.519478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
18587 12:30:26.564683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
18588 12:30:26.565106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
18590 12:30:26.604604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass>
18591 12:30:26.605017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass
18593 12:30:26.642659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
18594 12:30:26.643089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
18596 12:30:26.681269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
18598 12:30:26.681755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
18599 12:30:26.721133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
18600 12:30:26.721551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
18602 12:30:26.764436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass>
18603 12:30:26.764860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass
18605 12:30:26.803418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
18606 12:30:26.803866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
18608 12:30:26.845783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
18609 12:30:26.846224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
18611 12:30:26.899013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
18612 12:30:26.899371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
18614 12:30:26.958102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass
18616 12:30:26.958543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass>
18617 12:30:27.004247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
18619 12:30:27.004670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
18620 12:30:27.052049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
18621 12:30:27.052506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
18623 12:30:27.089775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
18624 12:30:27.090225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
18626 12:30:27.132640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass>
18627 12:30:27.133045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass
18629 12:30:27.169957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
18631 12:30:27.170428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
18632 12:30:27.210956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
18634 12:30:27.211459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
18635 12:30:27.258942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
18636 12:30:27.259374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
18638 12:30:27.300044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass>
18639 12:30:27.300461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass
18641 12:30:27.339847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
18642 12:30:27.340258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
18644 12:30:27.379833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
18645 12:30:27.380234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
18647 12:30:27.419211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
18648 12:30:27.419632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
18650 12:30:27.461391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass>
18651 12:30:27.461815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass
18653 12:30:27.504813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
18654 12:30:27.505279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
18656 12:30:27.545209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
18658 12:30:27.545709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
18659 12:30:27.587804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
18660 12:30:27.588215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
18662 12:30:27.635059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass>
18663 12:30:27.635455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass
18665 12:30:27.675375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
18666 12:30:27.675818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
18668 12:30:27.714048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
18669 12:30:27.714570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
18671 12:30:27.752819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
18672 12:30:27.753260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
18674 12:30:27.807160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass>
18675 12:30:27.807609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass
18677 12:30:27.849108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
18678 12:30:27.849570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
18680 12:30:27.895952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
18681 12:30:27.896359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
18683 12:30:27.935564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
18684 12:30:27.936004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
18686 12:30:27.973192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass>
18687 12:30:27.973627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass
18689 12:30:28.019882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
18690 12:30:28.020274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
18692 12:30:28.069355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
18693 12:30:28.069790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
18695 12:30:28.107266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
18696 12:30:28.107692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
18698 12:30:28.145849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass
18700 12:30:28.146428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass>
18701 12:30:28.185356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
18703 12:30:28.186232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
18704 12:30:28.223825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
18706 12:30:28.224306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
18707 12:30:28.260909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
18709 12:30:28.261370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
18710 12:30:28.299148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass>
18711 12:30:28.299587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass
18713 12:30:28.338878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
18714 12:30:28.339321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
18716 12:30:28.383881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
18717 12:30:28.384341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
18719 12:30:28.425623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
18720 12:30:28.426067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
18722 12:30:28.467107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass>
18723 12:30:28.467513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass
18725 12:30:28.508168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
18726 12:30:28.508621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
18728 12:30:28.552384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
18729 12:30:28.552824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
18731 12:30:28.591651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
18733 12:30:28.592412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
18734 12:30:28.629271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass
18736 12:30:28.629745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass>
18737 12:30:28.676001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
18738 12:30:28.676412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
18740 12:30:28.736958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
18742 12:30:28.737437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
18743 12:30:28.783754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
18744 12:30:28.784187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
18746 12:30:28.844638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass>
18747 12:30:28.845083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass
18749 12:30:28.889104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
18750 12:30:28.889539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
18752 12:30:28.931588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
18753 12:30:28.932097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
18755 12:30:28.971342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
18757 12:30:28.971800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
18758 12:30:29.007570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass>
18759 12:30:29.007994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass
18761 12:30:29.044111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
18763 12:30:29.044698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
18764 12:30:29.081109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
18765 12:30:29.081517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
18767 12:30:29.119706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
18769 12:30:29.120282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
18770 12:30:29.155317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass>
18771 12:30:29.155794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass
18773 12:30:29.191537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
18775 12:30:29.192001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
18776 12:30:29.227663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
18778 12:30:29.228295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
18779 12:30:29.264073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
18781 12:30:29.264544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
18782 12:30:29.300500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass>
18783 12:30:29.300943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass
18785 12:30:29.336288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
18787 12:30:29.336889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
18788 12:30:29.372260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
18790 12:30:29.372856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
18791 12:30:29.407672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
18792 12:30:29.408117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
18794 12:30:29.446569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass>
18795 12:30:29.446981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass
18797 12:30:29.481413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
18799 12:30:29.481902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
18800 12:30:29.517128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
18801 12:30:29.517598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
18803 12:30:29.552420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
18804 12:30:29.552885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
18806 12:30:29.588619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass>
18807 12:30:29.589100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass
18809 12:30:29.624392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
18810 12:30:29.624888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
18812 12:30:29.663837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
18813 12:30:29.664310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
18815 12:30:29.700661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
18817 12:30:29.701249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
18818 12:30:29.737881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass
18820 12:30:29.738560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass>
18821 12:30:29.778082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
18823 12:30:29.778560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
18824 12:30:29.831949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
18825 12:30:29.832453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
18827 12:30:29.885562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
18828 12:30:29.886065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
18830 12:30:29.940511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass
18832 12:30:29.941138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass>
18833 12:30:30.001763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
18834 12:30:30.002320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
18836 12:30:30.048536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
18837 12:30:30.048958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
18839 12:30:30.092626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
18841 12:30:30.093058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
18842 12:30:30.147039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass>
18843 12:30:30.147479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass
18845 12:30:30.209131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
18846 12:30:30.209533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
18848 12:30:30.269766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
18849 12:30:30.270199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
18851 12:30:30.328451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
18852 12:30:30.328845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
18854 12:30:30.380775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass
18856 12:30:30.381529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass>
18857 12:30:30.423136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
18859 12:30:30.423618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
18860 12:30:30.464115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
18861 12:30:30.464536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
18863 12:30:30.509797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
18865 12:30:30.510188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
18866 12:30:30.557601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass
18868 12:30:30.557991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass>
18869 12:30:30.599171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
18870 12:30:30.599566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
18872 12:30:30.641555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
18873 12:30:30.642014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
18875 12:30:30.682974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
18877 12:30:30.683625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
18878 12:30:30.728047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass
18880 12:30:30.728427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass>
18881 12:30:30.784990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
18883 12:30:30.785659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
18884 12:30:30.829559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
18885 12:30:30.829998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
18887 12:30:30.888346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
18889 12:30:30.888719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
18890 12:30:30.949686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass
18892 12:30:30.950132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass>
18893 12:30:31.005642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
18894 12:30:31.006039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
18896 12:30:31.051454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
18897 12:30:31.051918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
18899 12:30:31.087977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
18900 12:30:31.088462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
18902 12:30:31.124273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass>
18903 12:30:31.124704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass
18905 12:30:31.161064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
18907 12:30:31.161547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
18908 12:30:31.198657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
18910 12:30:31.199138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
18911 12:30:31.236895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
18913 12:30:31.237375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
18914 12:30:31.279329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass
18916 12:30:31.279811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass>
18917 12:30:31.319832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
18918 12:30:31.320264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
18920 12:30:31.361660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
18921 12:30:31.362100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
18923 12:30:31.415626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
18924 12:30:31.416065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
18926 12:30:31.455844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass>
18927 12:30:31.456283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass
18929 12:30:31.501849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
18930 12:30:31.502281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
18932 12:30:31.544100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
18933 12:30:31.544547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
18935 12:30:31.584548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
18936 12:30:31.584991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
18938 12:30:31.647052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass>
18939 12:30:31.647498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass
18941 12:30:31.696717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
18942 12:30:31.697104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
18944 12:30:31.754931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
18945 12:30:31.755428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
18947 12:30:31.813062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
18948 12:30:31.813491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
18950 12:30:31.864214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass>
18951 12:30:31.864584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass
18953 12:30:31.904133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
18954 12:30:31.904592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
18956 12:30:31.943868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
18958 12:30:31.944356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
18959 12:30:31.984951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
18961 12:30:31.985724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
18962 12:30:32.029511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass>
18963 12:30:32.029982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass
18965 12:30:32.082881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
18967 12:30:32.083399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
18968 12:30:32.126160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
18969 12:30:32.126561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
18971 12:30:32.165389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
18972 12:30:32.165784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
18974 12:30:32.205074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass>
18975 12:30:32.205481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass
18977 12:30:32.245671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
18979 12:30:32.246163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
18980 12:30:32.285262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
18982 12:30:32.285761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
18983 12:30:32.324201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
18984 12:30:32.324655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
18986 12:30:32.368161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass
18988 12:30:32.368573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass>
18989 12:30:32.410167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
18991 12:30:32.410808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
18992 12:30:32.460693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
18994 12:30:32.461353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
18995 12:30:32.503328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
18996 12:30:32.503753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
18998 12:30:32.561521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass>
18999 12:30:32.561982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass
19001 12:30:32.618065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
19003 12:30:32.618545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
19004 12:30:32.656678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
19005 12:30:32.657063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
19007 12:30:32.705599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
19009 12:30:32.706082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
19010 12:30:32.756792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass
19012 12:30:32.757264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass>
19013 12:30:32.795715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
19014 12:30:32.796115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
19016 12:30:32.836839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
19018 12:30:32.837321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
19019 12:30:32.885160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
19020 12:30:32.885586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
19022 12:30:32.936134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass>
19023 12:30:32.936584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass
19025 12:30:32.980590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
19026 12:30:32.981049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
19028 12:30:33.020021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
19029 12:30:33.020427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
19031 12:30:33.056682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
19033 12:30:33.057349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
19034 12:30:33.095140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass>
19035 12:30:33.095557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass
19037 12:30:33.135424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
19038 12:30:33.135811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
19040 12:30:33.173097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
19041 12:30:33.173537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
19043 12:30:33.212723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
19044 12:30:33.213201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
19046 12:30:33.253996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass
19048 12:30:33.254491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass>
19049 12:30:33.304600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
19050 12:30:33.305153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
19052 12:30:33.342284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
19054 12:30:33.343059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
19055 12:30:33.380473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
19056 12:30:33.380901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
19058 12:30:33.423179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass>
19059 12:30:33.423724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass
19061 12:30:33.460104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
19063 12:30:33.460880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
19064 12:30:33.496684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
19065 12:30:33.497156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
19067 12:30:33.532817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
19068 12:30:33.533309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
19070 12:30:33.567305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass
19072 12:30:33.567792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass>
19073 12:30:33.603236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
19074 12:30:33.603685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
19076 12:30:33.639023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
19078 12:30:33.639508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
19079 12:30:33.675102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
19081 12:30:33.675594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
19082 12:30:33.722145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass
19084 12:30:33.723202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass>
19085 12:30:33.759616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
19086 12:30:33.765753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
19088 12:30:33.821072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
19089 12:30:33.821566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
19091 12:30:33.869747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
19092 12:30:33.870197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
19094 12:30:33.912015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass
19096 12:30:33.912483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass>
19097 12:30:33.951420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
19098 12:30:33.951864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
19100 12:30:34.012407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
19101 12:30:34.012889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
19103 12:30:34.057876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
19104 12:30:34.058286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
19106 12:30:34.108220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass
19108 12:30:34.108721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass>
19109 12:30:34.155776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
19111 12:30:34.156216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
19112 12:30:34.205869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
19113 12:30:34.206278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
19115 12:30:34.255760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
19116 12:30:34.256161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
19118 12:30:34.302775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass
19120 12:30:34.303267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass>
19121 12:30:34.352691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
19122 12:30:34.353122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
19124 12:30:34.400583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
19125 12:30:34.400995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
19127 12:30:34.440215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
19128 12:30:34.440603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
19130 12:30:34.485350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass
19132 12:30:34.485852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass>
19133 12:30:34.528421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
19135 12:30:34.529006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
19136 12:30:34.569710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
19137 12:30:34.570088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
19139 12:30:34.617199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
19140 12:30:34.617623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
19142 12:30:34.667455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass>
19143 12:30:34.667898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass
19145 12:30:34.715649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
19146 12:30:34.716063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
19148 12:30:34.765910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
19149 12:30:34.766346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
19151 12:30:34.828586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
19152 12:30:34.829024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
19154 12:30:34.889333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass>
19155 12:30:34.889791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass
19157 12:30:34.947462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
19158 12:30:34.947878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
19160 12:30:35.004179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
19161 12:30:35.004546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
19163 12:30:35.045539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
19165 12:30:35.046038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
19166 12:30:35.087855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass
19168 12:30:35.088329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass>
19169 12:30:35.127084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
19171 12:30:35.127556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
19172 12:30:35.165276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
19173 12:30:35.165682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
19175 12:30:35.207946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
19177 12:30:35.208432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
19178 12:30:35.262321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass
19180 12:30:35.263052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass>
19181 12:30:35.318325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
19183 12:30:35.319054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
19184 12:30:35.366206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
19186 12:30:35.366631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
19187 12:30:35.423001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
19188 12:30:35.423428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
19190 12:30:35.469957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass>
19191 12:30:35.470398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass
19193 12:30:35.513245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
19194 12:30:35.513690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
19196 12:30:35.556045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
19197 12:30:35.556492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
19199 12:30:35.593633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
19201 12:30:35.594135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
19202 12:30:35.633113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass
19204 12:30:35.633579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass>
19205 12:30:35.672309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
19206 12:30:35.672757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
19208 12:30:35.715876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
19209 12:30:35.716292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
19211 12:30:35.769463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
19212 12:30:35.770051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
19214 12:30:35.822735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass>
19215 12:30:35.823318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass
19217 12:30:35.876199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
19219 12:30:35.876931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
19220 12:30:35.918219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
19222 12:30:35.918700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
19223 12:30:35.960015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
19224 12:30:35.960565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
19226 12:30:36.001585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass>
19227 12:30:36.002133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass
19229 12:30:36.038195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
19231 12:30:36.038784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
19232 12:30:36.081836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
19233 12:30:36.082231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
19235 12:30:36.122258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
19237 12:30:36.122732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
19238 12:30:36.162677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass>
19239 12:30:36.163098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass
19241 12:30:36.207720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
19242 12:30:36.208167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
19244 12:30:36.253472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
19246 12:30:36.253881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
19247 12:30:36.292667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
19249 12:30:36.293297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
19250 12:30:36.337907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass
19252 12:30:36.338564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass>
19253 12:30:36.394047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
19255 12:30:36.394734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
19256 12:30:36.444609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
19258 12:30:36.445083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
19259 12:30:36.482775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
19261 12:30:36.483206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
19262 12:30:36.531517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass>
19263 12:30:36.531968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass
19265 12:30:36.572087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
19266 12:30:36.572487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
19268 12:30:36.611878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
19270 12:30:36.612359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
19271 12:30:36.657349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
19272 12:30:36.657761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
19274 12:30:36.705632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass>
19275 12:30:36.706086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass
19277 12:30:36.743796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
19279 12:30:36.744281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
19280 12:30:36.779842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
19281 12:30:36.780279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
19283 12:30:36.816858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
19284 12:30:36.817635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
19286 12:30:36.865268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass>
19287 12:30:36.865699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass
19289 12:30:36.909374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
19290 12:30:36.909817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
19292 12:30:36.954754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
19293 12:30:36.955190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
19295 12:30:37.000330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
19296 12:30:37.000773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
19298 12:30:37.053539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass>
19299 12:30:37.054006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass
19301 12:30:37.111358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
19302 12:30:37.111787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
19304 12:30:37.156710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
19305 12:30:37.157147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
19307 12:30:37.210058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
19308 12:30:37.210514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
19310 12:30:37.256269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass
19312 12:30:37.256717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass>
19313 12:30:37.297339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
19315 12:30:37.297853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
19316 12:30:37.349419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
19317 12:30:37.349870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
19319 12:30:37.388213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
19320 12:30:37.388650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
19322 12:30:37.433696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass
19324 12:30:37.434152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass>
19325 12:30:37.491910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
19326 12:30:37.492349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
19328 12:30:37.542562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
19329 12:30:37.543017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
19331 12:30:37.585731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
19332 12:30:37.586171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
19334 12:30:37.634794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass>
19335 12:30:37.635225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass
19337 12:30:37.676940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
19338 12:30:37.677370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
19340 12:30:37.722884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
19341 12:30:37.723283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
19343 12:30:37.764103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
19344 12:30:37.764538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
19346 12:30:37.818850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass
19348 12:30:37.819437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass>
19349 12:30:37.868829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
19351 12:30:37.869288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
19352 12:30:37.907529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
19353 12:30:37.907949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
19355 12:30:37.952387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
19356 12:30:37.952805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
19358 12:30:37.996088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass
19360 12:30:37.996551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass>
19361 12:30:38.041346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
19362 12:30:38.041817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
19364 12:30:38.083672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
19365 12:30:38.084116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
19367 12:30:38.126334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
19369 12:30:38.126802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
19370 12:30:38.176599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass
19372 12:30:38.177061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass>
19373 12:30:38.224570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
19374 12:30:38.224962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
19376 12:30:38.273330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
19377 12:30:38.273788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
19379 12:30:38.316995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
19380 12:30:38.317469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
19382 12:30:38.368241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass>
19383 12:30:38.368638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass
19385 12:30:38.415250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
19386 12:30:38.415669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
19388 12:30:38.458094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
19390 12:30:38.458582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
19391 12:30:38.507290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
19393 12:30:38.507744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
19394 12:30:38.556487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass>
19395 12:30:38.556955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass
19397 12:30:38.609536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
19398 12:30:38.609999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
19400 12:30:38.662588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
19401 12:30:38.663047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
19403 12:30:38.701616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
19404 12:30:38.702181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
19406 12:30:38.744895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass>
19407 12:30:38.745355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass
19409 12:30:38.791056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
19410 12:30:38.791477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
19412 12:30:38.837684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
19413 12:30:38.838144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
19415 12:30:38.890922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
19416 12:30:38.891364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
19418 12:30:38.958350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass
19420 12:30:38.958815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass>
19421 12:30:39.009390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
19422 12:30:39.009841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
19424 12:30:39.053665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
19425 12:30:39.054087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
19427 12:30:39.099495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
19428 12:30:39.099942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
19430 12:30:39.140007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass
19432 12:30:39.140496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass>
19433 12:30:39.180413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
19434 12:30:39.180840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
19436 12:30:39.225043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
19437 12:30:39.225503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
19439 12:30:39.264063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
19441 12:30:39.264543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
19442 12:30:39.304330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass
19444 12:30:39.304790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass>
19445 12:30:39.350179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
19447 12:30:39.350659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
19448 12:30:39.401815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
19450 12:30:39.402298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
19451 12:30:39.447383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
19452 12:30:39.447834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
19454 12:30:39.490741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass>
19455 12:30:39.491181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass
19457 12:30:39.534164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
19459 12:30:39.534648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
19460 12:30:39.575660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
19461 12:30:39.576115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
19463 12:30:39.621514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
19464 12:30:39.621961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
19466 12:30:39.669576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass>
19467 12:30:39.670041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass
19469 12:30:39.709774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
19470 12:30:39.710221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
19472 12:30:39.748544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
19473 12:30:39.748975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
19475 12:30:39.787937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
19477 12:30:39.788416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
19478 12:30:39.829110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass>
19479 12:30:39.829575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass
19481 12:30:39.878151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
19483 12:30:39.878667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
19484 12:30:39.928798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
19485 12:30:39.929224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
19487 12:30:39.971413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
19488 12:30:39.971838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
19490 12:30:40.021058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass>
19491 12:30:40.021517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass
19493 12:30:40.058635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
19494 12:30:40.059077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
19496 12:30:40.095729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
19497 12:30:40.096108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
19499 12:30:40.133377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
19500 12:30:40.133810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
19502 12:30:40.176363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass>
19503 12:30:40.176730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass
19505 12:30:40.214953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
19506 12:30:40.215427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
19508 12:30:40.257792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
19509 12:30:40.258224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
19511 12:30:40.299797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
19513 12:30:40.300277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
19514 12:30:40.339277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass
19516 12:30:40.339758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass>
19517 12:30:40.378729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
19519 12:30:40.379199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
19520 12:30:40.416661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
19522 12:30:40.417423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
19523 12:30:40.460189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
19524 12:30:40.460564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
19526 12:30:40.501435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass>
19527 12:30:40.501821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass
19529 12:30:40.541078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
19530 12:30:40.541568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
19532 12:30:40.582750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
19533 12:30:40.583255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
19535 12:30:40.623058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
19536 12:30:40.623497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
19538 12:30:40.664656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass>
19539 12:30:40.665071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass
19541 12:30:40.707275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
19542 12:30:40.707706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
19544 12:30:40.748126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
19545 12:30:40.748617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
19547 12:30:40.787226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
19549 12:30:40.787883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
19550 12:30:40.832502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass
19552 12:30:40.832929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass>
19553 12:30:40.872259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
19554 12:30:40.872651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
19556 12:30:40.914933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
19557 12:30:40.915329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
19559 12:30:40.953051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
19560 12:30:40.953622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
19562 12:30:40.993524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass>
19563 12:30:40.994020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass
19565 12:30:41.032980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
19566 12:30:41.033544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
19568 12:30:41.072855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
19569 12:30:41.073320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
19571 12:30:41.115321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
19572 12:30:41.115869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
19574 12:30:41.153394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass>
19575 12:30:41.153922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass
19577 12:30:41.195363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
19578 12:30:41.195873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
19580 12:30:41.235114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
19581 12:30:41.235584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
19583 12:30:41.274906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
19584 12:30:41.275362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
19586 12:30:41.315738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass>
19587 12:30:41.316191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass
19589 12:30:41.359523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
19590 12:30:41.359952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
19592 12:30:41.413072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
19594 12:30:41.413557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
19595 12:30:41.456802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
19596 12:30:41.457371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
19598 12:30:41.495620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass
19600 12:30:41.496094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass>
19601 12:30:41.536989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
19603 12:30:41.537462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
19604 12:30:41.577332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
19605 12:30:41.577752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
19607 12:30:41.622770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
19608 12:30:41.623193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
19610 12:30:41.665556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass
19612 12:30:41.666061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass>
19613 12:30:41.705361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
19614 12:30:41.705772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
19616 12:30:41.744584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
19617 12:30:41.745018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
19619 12:30:41.781961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
19620 12:30:41.782363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
19622 12:30:41.821889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass>
19623 12:30:41.822287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass
19625 12:30:41.868102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
19626 12:30:41.868542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
19628 12:30:41.912967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
19630 12:30:41.913468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
19631 12:30:41.973733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
19632 12:30:41.974181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
19634 12:30:42.024140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass
19636 12:30:42.024620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass>
19637 12:30:42.073929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
19638 12:30:42.074382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
19640 12:30:42.111528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
19642 12:30:42.112003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
19643 12:30:42.150277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
19645 12:30:42.150918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
19646 12:30:42.186744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass>
19647 12:30:42.187225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass
19649 12:30:42.223903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
19651 12:30:42.224376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
19652 12:30:42.265143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
19653 12:30:42.265720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
19655 12:30:42.311317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
19657 12:30:42.311991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
19658 12:30:42.354821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass
19660 12:30:42.355287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass>
19661 12:30:42.398829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
19663 12:30:42.399548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
19664 12:30:42.439445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
19665 12:30:42.439941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
19667 12:30:42.483167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
19669 12:30:42.483650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
19670 12:30:42.527967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass
19672 12:30:42.528473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass>
19673 12:30:42.579217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
19674 12:30:42.579670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
19676 12:30:42.624872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
19677 12:30:42.625319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
19679 12:30:42.670030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
19680 12:30:42.670461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
19682 12:30:42.708227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass>
19683 12:30:42.708657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass
19685 12:30:42.748242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
19687 12:30:42.748707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
19688 12:30:42.793193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
19690 12:30:42.793803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
19691 12:30:42.838068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
19693 12:30:42.838560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
19694 12:30:42.880254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass
19696 12:30:42.880747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass>
19697 12:30:42.929169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
19699 12:30:42.929626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
19700 12:30:42.970118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
19702 12:30:42.970864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
19703 12:30:43.016815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
19704 12:30:43.017248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
19706 12:30:43.071930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass
19708 12:30:43.072415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass>
19709 12:30:43.112547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
19710 12:30:43.112984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
19712 12:30:43.152589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
19713 12:30:43.153045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
19715 12:30:43.193144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
19717 12:30:43.193624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
19718 12:30:43.237551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass
19720 12:30:43.238057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass>
19721 12:30:43.276847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
19722 12:30:43.277284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
19724 12:30:43.316221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
19725 12:30:43.316643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
19727 12:30:43.361037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
19729 12:30:43.361519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
19730 12:30:43.407400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass>
19731 12:30:43.407866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass
19733 12:30:43.452315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
19734 12:30:43.452751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
19736 12:30:43.494742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
19738 12:30:43.495219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
19739 12:30:43.532248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
19740 12:30:43.532674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
19742 12:30:43.572601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass>
19743 12:30:43.573065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass
19745 12:30:43.613126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
19746 12:30:43.613588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
19748 12:30:43.653396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
19749 12:30:43.653858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
19751 12:30:43.698103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
19753 12:30:43.698594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
19754 12:30:43.740004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass>
19755 12:30:43.740385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass
19757 12:30:43.791486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
19758 12:30:43.791926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
19760 12:30:43.843814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
19761 12:30:43.844274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
19763 12:30:43.887761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
19764 12:30:43.888231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
19766 12:30:43.929724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass>
19767 12:30:43.930238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass
19769 12:30:43.973197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
19770 12:30:43.973644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
19772 12:30:44.016296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
19774 12:30:44.016770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
19775 12:30:44.097379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
19776 12:30:44.097793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
19778 12:30:44.143221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass>
19779 12:30:44.143668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass
19781 12:30:44.188658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
19782 12:30:44.189111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
19784 12:30:44.232125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
19785 12:30:44.232559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
19787 12:30:44.276055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
19788 12:30:44.276484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
19790 12:30:44.324221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass>
19791 12:30:44.324668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass
19793 12:30:44.369721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
19794 12:30:44.370168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
19796 12:30:44.412822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
19797 12:30:44.413260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
19799 12:30:44.454341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
19801 12:30:44.454816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
19802 12:30:44.495860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass>
19803 12:30:44.496319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass
19805 12:30:44.537083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
19806 12:30:44.537629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
19808 12:30:44.580652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
19809 12:30:44.581144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
19811 12:30:44.628751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
19812 12:30:44.629198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
19814 12:30:44.683996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass>
19815 12:30:44.684441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass
19817 12:30:44.746309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
19819 12:30:44.746954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
19820 12:30:44.796516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
19821 12:30:44.796953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
19823 12:30:44.843298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
19824 12:30:44.843737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
19826 12:30:44.895519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass>
19827 12:30:44.895965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass
19829 12:30:44.955280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
19830 12:30:44.955732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
19832 12:30:45.017525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
19833 12:30:45.017974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
19835 12:30:45.072705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
19836 12:30:45.073145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
19838 12:30:45.132543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass>
19839 12:30:45.133008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass
19841 12:30:45.191087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
19842 12:30:45.191455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
19844 12:30:45.248075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
19845 12:30:45.248577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
19847 12:30:45.304517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
19849 12:30:45.305161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
19850 12:30:45.362332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass
19852 12:30:45.363054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass>
19853 12:30:45.419982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
19854 12:30:45.420421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
19856 12:30:45.459131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
19857 12:30:45.459572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
19859 12:30:45.499326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
19861 12:30:45.499782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
19862 12:30:45.539362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass
19864 12:30:45.539848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass>
19865 12:30:45.580199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
19866 12:30:45.580618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
19868 12:30:45.620327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
19869 12:30:45.620749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
19871 12:30:45.679451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
19872 12:30:45.679893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
19874 12:30:45.740289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass>
19875 12:30:45.740745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass
19877 12:30:45.801119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
19878 12:30:45.801536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
19880 12:30:45.861715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
19882 12:30:45.862212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
19883 12:30:45.921956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
19885 12:30:45.922446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
19886 12:30:45.981284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass
19888 12:30:45.981771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass>
19889 12:30:46.043269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
19890 12:30:46.043706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
19892 12:30:46.105136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
19893 12:30:46.105580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
19895 12:30:46.164343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
19896 12:30:46.164771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
19898 12:30:46.222880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass>
19899 12:30:46.223313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass
19901 12:30:46.280796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
19902 12:30:46.281229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
19904 12:30:46.336423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
19905 12:30:46.336848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
19907 12:30:46.379713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
19908 12:30:46.380168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
19910 12:30:46.425425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass>
19911 12:30:46.425864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass
19913 12:30:46.484196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
19915 12:30:46.484670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
19916 12:30:46.542965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
19917 12:30:46.543377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
19919 12:30:46.585589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
19920 12:30:46.586058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
19922 12:30:46.626868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass>
19923 12:30:46.627323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass
19925 12:30:46.665102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
19926 12:30:46.665559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
19928 12:30:46.705697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
19930 12:30:46.706196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
19931 12:30:46.747266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
19932 12:30:46.747720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
19934 12:30:46.797165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass>
19935 12:30:46.797618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass
19937 12:30:46.854362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
19939 12:30:46.854835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
19940 12:30:46.897004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
19941 12:30:46.897454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
19943 12:30:46.939363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
19944 12:30:46.939792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
19946 12:30:46.981571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass
19948 12:30:46.982053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass>
19949 12:30:47.032604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
19951 12:30:47.033054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
19952 12:30:47.093060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
19953 12:30:47.093489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
19955 12:30:47.153914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
19957 12:30:47.154394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
19958 12:30:47.213712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass
19960 12:30:47.214184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass>
19961 12:30:47.261816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
19962 12:30:47.262276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
19964 12:30:47.303956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
19965 12:30:47.304410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
19967 12:30:47.362907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
19968 12:30:47.363340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
19970 12:30:47.421145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass
19972 12:30:47.421607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass>
19973 12:30:47.477390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
19974 12:30:47.477863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
19976 12:30:47.539824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
19978 12:30:47.540286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
19979 12:30:47.593036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
19980 12:30:47.593481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
19982 12:30:47.633958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass
19984 12:30:47.634457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass>
19985 12:30:47.682306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
19987 12:30:47.682925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
19988 12:30:47.744802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
19989 12:30:47.745251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
19991 12:30:47.751453 <47>[ 199.373268] systemd-journald[105]: Sent WATCHDOG=1 notification.
19992 12:30:47.804444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
19993 12:30:47.804898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
19995 12:30:47.855897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass>
19996 12:30:47.856343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass
19998 12:30:47.899801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
20000 12:30:47.900272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
20001 12:30:47.947542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
20003 12:30:47.948027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
20004 12:30:47.992456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
20005 12:30:47.992882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
20007 12:30:48.035785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass>
20008 12:30:48.036183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass
20010 12:30:48.086873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
20011 12:30:48.087293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
20013 12:30:48.145110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
20014 12:30:48.145517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
20016 12:30:48.204312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
20017 12:30:48.204872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
20019 12:30:48.264663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass>
20020 12:30:48.265073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass
20022 12:30:48.324212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
20023 12:30:48.324638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
20025 12:30:48.383268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
20026 12:30:48.383734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
20028 12:30:48.444089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
20029 12:30:48.444551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
20031 12:30:48.505001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass>
20032 12:30:48.505457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass
20034 12:30:48.564354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
20036 12:30:48.564826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
20037 12:30:48.624559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
20038 12:30:48.625015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
20040 12:30:48.684279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
20042 12:30:48.684775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
20043 12:30:48.745504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass
20045 12:30:48.745975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass>
20046 12:30:48.804478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
20047 12:30:48.804846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
20049 12:30:48.864879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
20051 12:30:48.865371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
20052 12:30:48.929231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
20053 12:30:48.929694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
20055 12:30:48.987002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass>
20056 12:30:48.987440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass
20058 12:30:49.047377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
20059 12:30:49.047819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
20061 12:30:49.108991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
20063 12:30:49.109487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
20064 12:30:49.202165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
20066 12:30:49.202577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
20067 12:30:49.263991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass
20069 12:30:49.264480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass>
20070 12:30:49.325442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
20071 12:30:49.325882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
20073 12:30:49.384844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
20074 12:30:49.385323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
20076 12:30:49.445065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
20077 12:30:49.445511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
20079 12:30:49.503988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass
20081 12:30:49.504436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass>
20082 12:30:49.556527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
20084 12:30:49.557013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
20085 12:30:49.620312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
20087 12:30:49.620788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
20088 12:30:49.682260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
20089 12:30:49.682687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
20091 12:30:49.741105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass
20093 12:30:49.741567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass>
20094 12:30:49.800843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
20095 12:30:49.801240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
20097 12:30:49.863996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
20099 12:30:49.864429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
20100 12:30:49.924343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
20102 12:30:49.924827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
20103 12:30:49.985537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass
20105 12:30:49.986019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass>
20106 12:30:50.045113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
20107 12:30:50.045520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
20109 12:30:50.106457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
20111 12:30:50.107012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
20112 12:30:50.168418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
20113 12:30:50.168818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
20115 12:30:50.230923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass>
20116 12:30:50.231324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass
20118 12:30:50.283099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
20119 12:30:50.283533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
20121 12:30:50.321045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
20122 12:30:50.321464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
20124 12:30:50.359665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
20126 12:30:50.360128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
20127 12:30:50.403856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass>
20128 12:30:50.404319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass
20130 12:30:50.459406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
20131 12:30:50.459897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
20133 12:30:50.506633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
20135 12:30:50.507287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
20136 12:30:50.540631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
20138 12:30:50.541186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
20139 12:30:50.583740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass
20141 12:30:50.584178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass>
20142 12:30:50.623304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
20143 12:30:50.623699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
20145 12:30:50.675334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
20146 12:30:50.675772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
20148 12:30:50.713175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
20149 12:30:50.713629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
20151 12:30:50.748096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass
20153 12:30:50.748580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass>
20154 12:30:50.782824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
20156 12:30:50.783297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
20157 12:30:50.818700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
20158 12:30:50.819165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
20160 12:30:50.853551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
20161 12:30:50.853975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
20163 12:30:50.888066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass>
20164 12:30:50.888513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass
20166 12:30:50.923409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
20167 12:30:50.923838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
20169 12:30:50.959125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
20171 12:30:50.959604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
20172 12:30:50.995457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
20173 12:30:50.995889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
20175 12:30:51.035359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass>
20176 12:30:51.035802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass
20178 12:30:51.072895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
20179 12:30:51.073337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
20181 12:30:51.131070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
20182 12:30:51.131627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
20184 12:30:51.182267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
20186 12:30:51.182763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
20187 12:30:51.229011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass>
20188 12:30:51.229473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass
20190 12:30:51.289447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
20191 12:30:51.289909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
20193 12:30:51.343616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
20194 12:30:51.344048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
20196 12:30:51.393145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
20198 12:30:51.393627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
20199 12:30:51.435052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass>
20200 12:30:51.435448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass
20202 12:30:51.481945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
20203 12:30:51.482449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
20205 12:30:51.540911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
20206 12:30:51.541511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
20208 12:30:51.597639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
20209 12:30:51.598094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
20211 12:30:51.651839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass>
20212 12:30:51.652297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass
20214 12:30:51.696572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
20216 12:30:51.697065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
20217 12:30:51.738624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
20218 12:30:51.739065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
20220 12:30:51.776033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
20221 12:30:51.776475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
20223 12:30:51.815675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass>
20224 12:30:51.816140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass
20226 12:30:51.857266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
20228 12:30:51.857702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
20229 12:30:51.909721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
20231 12:30:51.910190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
20232 12:30:51.958353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
20234 12:30:51.958803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
20235 12:30:52.014862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass
20237 12:30:52.015341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass>
20238 12:30:52.061668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
20239 12:30:52.062104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
20241 12:30:52.109990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
20242 12:30:52.110424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
20244 12:30:52.149359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
20246 12:30:52.149861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
20247 12:30:52.191975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass>
20248 12:30:52.192416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass
20250 12:30:52.233457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
20252 12:30:52.233953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
20253 12:30:52.285380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
20254 12:30:52.285862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
20256 12:30:52.334967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
20258 12:30:52.335447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
20259 12:30:52.377080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass
20261 12:30:52.377868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass>
20262 12:30:52.423651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
20263 12:30:52.424039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
20265 12:30:52.469655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
20266 12:30:52.470063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
20268 12:30:52.513309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
20269 12:30:52.513693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
20271 12:30:52.551091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass>
20272 12:30:52.551551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass
20274 12:30:52.595107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
20275 12:30:52.595627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
20277 12:30:52.646308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
20279 12:30:52.646801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
20280 12:30:52.691450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
20281 12:30:52.691903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
20283 12:30:52.739871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass>
20284 12:30:52.740322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass
20286 12:30:52.782068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
20288 12:30:52.782482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
20289 12:30:52.832987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
20291 12:30:52.833418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
20292 12:30:52.876673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
20293 12:30:52.877115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
20295 12:30:52.917261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass>
20296 12:30:52.917747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass
20298 12:30:52.959387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
20299 12:30:52.959828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
20301 12:30:53.003154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
20302 12:30:53.003622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
20304 12:30:53.038745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
20305 12:30:53.039185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
20307 12:30:53.082531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass>
20308 12:30:53.082945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass
20310 12:30:53.119974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
20311 12:30:53.120415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
20313 12:30:53.156360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
20314 12:30:53.156799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
20316 12:30:53.204479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
20318 12:30:53.205235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
20319 12:30:53.244995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass>
20320 12:30:53.245536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass
20322 12:30:53.287749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
20323 12:30:53.288184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
20325 12:30:53.326273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
20327 12:30:53.326749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
20328 12:30:53.367704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
20329 12:30:53.368148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
20331 12:30:53.413940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass>
20332 12:30:53.414501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass
20334 12:30:53.455829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
20335 12:30:53.456275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
20337 12:30:53.512179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
20339 12:30:53.512832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
20340 12:30:53.564026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
20341 12:30:53.564618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
20343 12:30:53.616429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass>
20344 12:30:53.616847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass
20346 12:30:53.655589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
20348 12:30:53.656060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
20349 12:30:53.695162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
20350 12:30:53.695595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
20352 12:30:53.732396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
20353 12:30:53.732826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
20355 12:30:53.776078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass
20357 12:30:53.776564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass>
20358 12:30:53.820361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
20360 12:30:53.821088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
20361 12:30:53.865233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
20362 12:30:53.865686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
20364 12:30:53.909652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
20366 12:30:53.910121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
20367 12:30:53.959253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass>
20368 12:30:53.959705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass
20370 12:30:54.000135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
20371 12:30:54.000518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
20373 12:30:54.039455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
20374 12:30:54.039930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
20376 12:30:54.076619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
20377 12:30:54.077006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
20379 12:30:54.111377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass>
20380 12:30:54.111885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass
20382 12:30:54.147011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
20384 12:30:54.147409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
20385 12:30:54.185341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
20386 12:30:54.185911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
20388 12:30:54.224070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
20390 12:30:54.224549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
20391 12:30:54.260930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass>
20392 12:30:54.261367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass
20394 12:30:54.316621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
20395 12:30:54.317078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
20397 12:30:54.356480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
20398 12:30:54.356920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
20400 12:30:54.392879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
20401 12:30:54.393316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
20403 12:30:54.431799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass>
20404 12:30:54.432222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass
20406 12:30:54.468870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
20408 12:30:54.469359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
20409 12:30:54.506289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
20411 12:30:54.506775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
20412 12:30:54.548016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
20413 12:30:54.548443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
20415 12:30:54.593440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass>
20416 12:30:54.593912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass
20418 12:30:54.645335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
20419 12:30:54.645904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
20421 12:30:54.693111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
20423 12:30:54.693577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
20424 12:30:54.740285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
20426 12:30:54.740754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
20427 12:30:54.781025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass
20429 12:30:54.781520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass>
20430 12:30:54.822933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
20432 12:30:54.823418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
20433 12:30:54.859845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
20434 12:30:54.860271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
20436 12:30:54.915255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
20438 12:30:54.915743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
20439 12:30:54.957759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass
20441 12:30:54.958258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass>
20442 12:30:55.007954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
20443 12:30:55.008364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
20445 12:30:55.060364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
20446 12:30:55.060800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
20448 12:30:55.105348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
20449 12:30:55.105774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
20451 12:30:55.153277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass>
20452 12:30:55.153792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass
20454 12:30:55.196314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
20455 12:30:55.196697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
20457 12:30:55.233496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
20458 12:30:55.233950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
20460 12:30:55.270896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
20461 12:30:55.271443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
20463 12:30:55.309085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass>
20464 12:30:55.309530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass
20466 12:30:55.348734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
20467 12:30:55.349168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
20469 12:30:55.389206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
20470 12:30:55.389684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
20472 12:30:55.424519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
20473 12:30:55.424990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
20475 12:30:55.467199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass>
20476 12:30:55.467658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass
20478 12:30:55.508901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
20479 12:30:55.509359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
20481 12:30:55.545547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
20482 12:30:55.545937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
20484 12:30:55.586752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
20486 12:30:55.587379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
20487 12:30:55.625036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass>
20488 12:30:55.625521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass
20490 12:30:55.663796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
20491 12:30:55.664251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
20493 12:30:55.704733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
20494 12:30:55.705159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
20496 12:30:55.744737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
20497 12:30:55.745187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
20499 12:30:55.785552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass
20501 12:30:55.786155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass>
20502 12:30:55.824770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
20503 12:30:55.825185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
20505 12:30:55.860712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
20506 12:30:55.861159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
20508 12:30:55.899064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
20510 12:30:55.899545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
20511 12:30:55.935850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass>
20512 12:30:55.936299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass
20514 12:30:55.970722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
20515 12:30:55.971162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
20517 12:30:56.009128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
20519 12:30:56.009599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
20520 12:30:56.045494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
20521 12:30:56.045927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
20523 12:30:56.093169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass
20525 12:30:56.093921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass>
20526 12:30:56.129433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
20527 12:30:56.129999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
20529 12:30:56.168203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
20530 12:30:56.168664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
20532 12:30:56.206698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
20533 12:30:56.207126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
20535 12:30:56.244893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass>
20536 12:30:56.245353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass
20538 12:30:56.282728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
20539 12:30:56.283230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
20541 12:30:56.321987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
20543 12:30:56.322525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
20544 12:30:56.359736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
20545 12:30:56.360218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
20547 12:30:56.396887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass
20549 12:30:56.397672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass>
20550 12:30:56.437512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
20551 12:30:56.437924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
20553 12:30:56.478227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
20555 12:30:56.478990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
20556 12:30:56.518108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
20558 12:30:56.518865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
20559 12:30:56.557869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass
20561 12:30:56.558622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass>
20562 12:30:56.597788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
20563 12:30:56.598223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
20565 12:30:56.637284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
20566 12:30:56.637842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
20568 12:30:56.672287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
20569 12:30:56.672755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
20571 12:30:56.717543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass
20573 12:30:56.718304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass>
20574 12:30:56.756496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
20576 12:30:56.757126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
20577 12:30:56.791492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
20578 12:30:56.791976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
20580 12:30:56.835283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
20582 12:30:56.835955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
20583 12:30:56.871873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass>
20584 12:30:56.872369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass
20586 12:30:56.911733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
20587 12:30:56.912151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
20589 12:30:56.951324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
20590 12:30:56.951777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
20592 12:30:56.992566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
20593 12:30:56.992978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
20595 12:30:57.030100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass
20597 12:30:57.030698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass>
20598 12:30:57.080498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
20600 12:30:57.081276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
20601 12:30:57.118102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
20603 12:30:57.118941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
20604 12:30:57.155439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
20605 12:30:57.156011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
20607 12:30:57.191741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass>
20608 12:30:57.192183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass
20610 12:30:57.231192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
20612 12:30:57.231641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
20613 12:30:57.270404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
20614 12:30:57.270817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
20616 12:30:57.306146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
20618 12:30:57.306509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
20619 12:30:57.346879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass>
20620 12:30:57.347331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass
20622 12:30:57.385867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
20623 12:30:57.386306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
20625 12:30:57.423814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
20626 12:30:57.424249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
20628 12:30:57.463901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
20629 12:30:57.464278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
20631 12:30:57.504485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass
20633 12:30:57.504883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass>
20634 12:30:57.549631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
20635 12:30:57.550072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
20637 12:30:57.586660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
20638 12:30:57.587102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
20640 12:30:57.632100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
20642 12:30:57.632557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
20643 12:30:57.691430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass>
20644 12:30:57.691992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass
20646 12:30:57.732169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
20647 12:30:57.732605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
20649 12:30:57.772533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
20650 12:30:57.772938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
20652 12:30:57.813904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
20653 12:30:57.814324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
20655 12:30:57.853718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass
20657 12:30:57.854207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass>
20658 12:30:57.903588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
20660 12:30:57.904012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
20661 12:30:57.949963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
20663 12:30:57.950446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
20664 12:30:57.991479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
20665 12:30:57.991908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
20667 12:30:58.029414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass
20669 12:30:58.029867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass>
20670 12:30:58.074883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
20671 12:30:58.075260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
20673 12:30:58.112667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
20675 12:30:58.113421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
20676 12:30:58.152488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
20677 12:30:58.152882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
20679 12:30:58.189347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass>
20680 12:30:58.189682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass
20682 12:30:58.227394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
20683 12:30:58.227855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
20685 12:30:58.267643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
20686 12:30:58.268018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
20688 12:30:58.308045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
20689 12:30:58.308494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
20691 12:30:58.346609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass>
20692 12:30:58.347056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass
20694 12:30:58.388597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
20696 12:30:58.389068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
20697 12:30:58.434990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
20698 12:30:58.435424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
20700 12:30:58.473293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
20701 12:30:58.473748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
20703 12:30:58.515733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass>
20704 12:30:58.516190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass
20706 12:30:58.559267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
20707 12:30:58.559766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
20709 12:30:58.596822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
20711 12:30:58.597540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
20712 12:30:58.642313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
20714 12:30:58.642973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
20715 12:30:58.691725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass>
20716 12:30:58.692161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass
20718 12:30:58.736025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
20719 12:30:58.736466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
20721 12:30:58.780460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
20722 12:30:58.780976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
20724 12:30:58.819842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
20725 12:30:58.820314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
20727 12:30:58.864323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass>
20728 12:30:58.864792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass
20730 12:30:58.908017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
20732 12:30:58.908506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
20733 12:30:58.961805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
20734 12:30:58.962240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
20736 12:30:59.017514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
20737 12:30:59.017963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
20739 12:30:59.075033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass>
20740 12:30:59.075558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass
20742 12:30:59.127710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
20743 12:30:59.128093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
20745 12:30:59.166384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
20747 12:30:59.166863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
20748 12:30:59.204865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
20749 12:30:59.205343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
20751 12:30:59.247160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass>
20752 12:30:59.247587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass
20754 12:30:59.288075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
20755 12:30:59.288485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
20757 12:30:59.336644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
20758 12:30:59.337085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
20760 12:30:59.400260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
20761 12:30:59.400702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
20763 12:30:59.455640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass>
20764 12:30:59.456036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass
20766 12:30:59.508130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
20768 12:30:59.508750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
20769 12:30:59.544586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
20770 12:30:59.545035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
20772 12:30:59.584343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
20773 12:30:59.584767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
20775 12:30:59.623909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass>
20776 12:30:59.624337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass
20778 12:30:59.662641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
20779 12:30:59.663073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
20781 12:30:59.700425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
20782 12:30:59.700970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
20784 12:30:59.739573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
20785 12:30:59.740027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
20787 12:30:59.779504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass>
20788 12:30:59.779945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass
20790 12:30:59.825811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
20792 12:30:59.826295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
20793 12:30:59.861490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
20794 12:30:59.861917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
20796 12:30:59.910223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
20798 12:30:59.910723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
20799 12:30:59.955264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass>
20800 12:30:59.955722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass
20802 12:30:59.995901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
20803 12:30:59.996302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
20805 12:31:00.035968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
20806 12:31:00.036400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
20808 12:31:00.089852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
20809 12:31:00.090372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
20811 12:31:00.135570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass
20813 12:31:00.136324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass>
20814 12:31:00.172745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
20815 12:31:00.173107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
20817 12:31:00.213026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
20818 12:31:00.213588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
20820 12:31:00.255252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
20821 12:31:00.255752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
20823 12:31:00.299879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass>
20824 12:31:00.300289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass
20826 12:31:00.343411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
20827 12:31:00.343929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
20829 12:31:00.384329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
20830 12:31:00.384734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
20832 12:31:00.429045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
20833 12:31:00.429477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
20835 12:31:00.468593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass>
20836 12:31:00.469050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass
20838 12:31:00.517130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
20840 12:31:00.517727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
20841 12:31:00.564382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
20842 12:31:00.564748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
20844 12:31:00.601359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
20846 12:31:00.602033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
20847 12:31:00.640901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass
20849 12:31:00.641447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass>
20850 12:31:00.686920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
20852 12:31:00.687383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
20853 12:31:00.725659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
20855 12:31:00.726065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
20856 12:31:00.769675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
20858 12:31:00.770070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
20859 12:31:00.815799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass
20861 12:31:00.816479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass>
20862 12:31:00.856687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
20863 12:31:00.857062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
20865 12:31:00.903326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
20866 12:31:00.903738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
20868 12:31:00.951580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
20870 12:31:00.951930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
20871 12:31:00.994818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass
20873 12:31:00.995187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass>
20874 12:31:01.036131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
20876 12:31:01.036624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
20877 12:31:01.076186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
20878 12:31:01.076613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
20880 12:31:01.112677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
20882 12:31:01.113269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
20883 12:31:01.151389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass>
20884 12:31:01.151767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass
20886 12:31:01.191959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
20887 12:31:01.192374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
20889 12:31:01.235672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
20890 12:31:01.236056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
20892 12:31:01.280292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
20894 12:31:01.281061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
20895 12:31:01.322539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass>
20896 12:31:01.323026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass
20898 12:31:01.359066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
20899 12:31:01.359527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
20901 12:31:01.399923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
20902 12:31:01.400392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
20904 12:31:01.437393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
20906 12:31:01.437881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
20907 12:31:01.477240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass>
20908 12:31:01.477692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass
20910 12:31:01.513848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
20911 12:31:01.514289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
20913 12:31:01.555654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
20915 12:31:01.556311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
20916 12:31:01.609614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
20918 12:31:01.610351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
20919 12:31:01.646698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass>
20920 12:31:01.647190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass
20922 12:31:01.685314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
20923 12:31:01.685813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
20925 12:31:01.723383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
20926 12:31:01.723942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
20928 12:31:01.764498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
20929 12:31:01.764910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
20931 12:31:01.804953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass>
20932 12:31:01.805362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass
20934 12:31:01.842986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
20936 12:31:01.843694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
20937 12:31:01.888395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
20938 12:31:01.888947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
20940 12:31:01.944352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
20941 12:31:01.944869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
20943 12:31:01.998086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass
20945 12:31:01.998852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass>
20946 12:31:02.044248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
20947 12:31:02.044684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
20949 12:31:02.089007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
20950 12:31:02.089453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
20952 12:31:02.126033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
20954 12:31:02.126685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
20955 12:31:02.161593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass
20957 12:31:02.162252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass>
20958 12:31:02.197536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
20959 12:31:02.198090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
20961 12:31:02.235839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
20962 12:31:02.236294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
20964 12:31:02.273987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
20966 12:31:02.274460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
20967 12:31:02.312048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass>
20968 12:31:02.312491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass
20970 12:31:02.349247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
20972 12:31:02.349905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
20973 12:31:02.385548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
20974 12:31:02.386069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
20976 12:31:02.426277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
20978 12:31:02.426940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
20979 12:31:02.466495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass>
20980 12:31:02.467043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass
20982 12:31:02.517074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
20983 12:31:02.517542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
20985 12:31:02.568723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
20986 12:31:02.569214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
20988 12:31:02.620111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
20989 12:31:02.620545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
20991 12:31:02.669292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass
20993 12:31:02.670011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass>
20994 12:31:02.716215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
20996 12:31:02.716644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
20997 12:31:02.767496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
20998 12:31:02.767945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
21000 12:31:02.813562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
21002 12:31:02.813961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
21003 12:31:02.874960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass>
21004 12:31:02.875395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass
21006 12:31:02.925540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
21007 12:31:02.925956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
21009 12:31:02.971056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
21010 12:31:02.971454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
21012 12:31:03.024873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
21013 12:31:03.025303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
21015 12:31:03.074160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass
21017 12:31:03.074642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass>
21018 12:31:03.113225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
21019 12:31:03.113677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
21021 12:31:03.170915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
21022 12:31:03.171466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
21024 12:31:03.220591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
21026 12:31:03.221361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
21027 12:31:03.262836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass>
21028 12:31:03.263297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass
21030 12:31:03.300880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
21031 12:31:03.301449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
21033 12:31:03.344161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
21034 12:31:03.344713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
21036 12:31:03.400645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
21037 12:31:03.401096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
21039 12:31:03.449293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass
21041 12:31:03.449810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass>
21042 12:31:03.500273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
21043 12:31:03.500730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
21045 12:31:03.552224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
21046 12:31:03.552638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
21048 12:31:03.601791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
21049 12:31:03.602230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
21051 12:31:03.648112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass>
21052 12:31:03.648556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass
21054 12:31:03.690302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
21056 12:31:03.690796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
21057 12:31:03.744707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
21058 12:31:03.745140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
21060 12:31:03.805224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
21061 12:31:03.805620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
21063 12:31:03.859559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass
21065 12:31:03.860056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass>
21066 12:31:03.918488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
21068 12:31:03.918990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
21069 12:31:03.978417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
21071 12:31:03.978898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
21072 12:31:04.040345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
21074 12:31:04.040789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
21075 12:31:04.095621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass>
21076 12:31:04.096058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass
21078 12:31:04.149496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
21079 12:31:04.149920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
21081 12:31:04.207872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
21082 12:31:04.208310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
21084 12:31:04.264697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
21085 12:31:04.265204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
21087 12:31:04.315842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass>
21088 12:31:04.316281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass
21090 12:31:04.367873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
21091 12:31:04.368278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
21093 12:31:04.418644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
21094 12:31:04.419110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
21096 12:31:04.478317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
21098 12:31:04.478837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
21099 12:31:04.558782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass
21101 12:31:04.559277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass>
21102 12:31:04.609980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
21103 12:31:04.610420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
21105 12:31:04.665638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
21107 12:31:04.666191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
21108 12:31:04.721533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
21110 12:31:04.722029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
21111 12:31:04.774372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass
21113 12:31:04.774881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass>
21114 12:31:04.821726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
21115 12:31:04.822160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
21117 12:31:04.870050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
21119 12:31:04.870541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
21120 12:31:04.928895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
21121 12:31:04.929343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
21123 12:31:04.982974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass>
21124 12:31:04.983412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass
21126 12:31:05.040450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
21127 12:31:05.040862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
21129 12:31:05.095338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
21130 12:31:05.095772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
21132 12:31:05.154332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
21134 12:31:05.154759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
21135 12:31:05.210160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass
21137 12:31:05.210724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass>
21138 12:31:05.265212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
21139 12:31:05.265637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
21141 12:31:05.317284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
21142 12:31:05.317684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
21144 12:31:05.368725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
21145 12:31:05.369163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
21147 12:31:05.420044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass>
21148 12:31:05.420502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass
21150 12:31:05.476536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
21151 12:31:05.476975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
21153 12:31:05.536883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
21155 12:31:05.537369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
21156 12:31:05.600214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
21157 12:31:05.600639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
21159 12:31:05.654865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass
21161 12:31:05.655548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass>
21162 12:31:05.708372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
21163 12:31:05.708781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
21165 12:31:05.763996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
21166 12:31:05.764435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
21168 12:31:05.818266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
21169 12:31:05.818667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
21171 12:31:05.872734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass>
21172 12:31:05.873443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass
21174 12:31:05.927472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
21175 12:31:05.927855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
21177 12:31:05.984845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
21179 12:31:05.985299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
21180 12:31:06.045397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
21181 12:31:06.045868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
21183 12:31:06.105754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass>
21184 12:31:06.106204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass
21186 12:31:06.169135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
21187 12:31:06.169596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
21189 12:31:06.224265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
21190 12:31:06.224697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
21192 12:31:06.281075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
21193 12:31:06.281527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
21195 12:31:06.334386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass
21197 12:31:06.334867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass>
21198 12:31:06.395669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
21199 12:31:06.396131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
21201 12:31:06.455771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
21202 12:31:06.456202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
21204 12:31:06.517767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
21205 12:31:06.518187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
21207 12:31:06.576593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass>
21208 12:31:06.577039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass
21210 12:31:06.637463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
21211 12:31:06.637918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
21213 12:31:06.697807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
21215 12:31:06.698258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
21216 12:31:06.756203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
21218 12:31:06.756680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
21219 12:31:06.812165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass>
21220 12:31:06.812579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass
21222 12:31:06.868309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
21223 12:31:06.868741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
21225 12:31:06.921803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
21226 12:31:06.922263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
21228 12:31:06.983245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
21229 12:31:06.983671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
21231 12:31:07.045035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass>
21232 12:31:07.045489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass
21234 12:31:07.106345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
21236 12:31:07.106844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
21237 12:31:07.169693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
21239 12:31:07.170182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
21240 12:31:07.231881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
21241 12:31:07.232304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
21243 12:31:07.282710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass>
21244 12:31:07.283114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass
21246 12:31:07.343610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
21247 12:31:07.344065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
21249 12:31:07.392551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
21250 12:31:07.393002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
21252 12:31:07.450290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
21254 12:31:07.451362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
21255 12:31:07.506401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass
21257 12:31:07.506888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass>
21258 12:31:07.556165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
21259 12:31:07.556626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
21261 12:31:07.604810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
21262 12:31:07.605255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
21264 12:31:07.651153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
21265 12:31:07.651582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
21267 12:31:07.704488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass>
21268 12:31:07.704892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass
21270 12:31:07.759232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
21272 12:31:07.759711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
21273 12:31:07.808966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
21274 12:31:07.809395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
21276 12:31:07.852922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
21278 12:31:07.853390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
21279 12:31:07.892648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass>
21280 12:31:07.893207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass
21282 12:31:07.936320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
21283 12:31:07.936748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
21285 12:31:07.980519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
21286 12:31:07.980909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
21288 12:31:08.028257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
21289 12:31:08.028685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
21291 12:31:08.084007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass
21293 12:31:08.084486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass>
21294 12:31:08.126800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
21295 12:31:08.127212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
21297 12:31:08.172419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
21298 12:31:08.172898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
21300 12:31:08.213917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
21301 12:31:08.214339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
21303 12:31:08.263140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass
21305 12:31:08.263563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass>
21306 12:31:08.306200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
21308 12:31:08.306802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
21309 12:31:08.355833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
21310 12:31:08.356275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
21312 12:31:08.405783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
21313 12:31:08.406196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
21315 12:31:08.450600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass
21317 12:31:08.451076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass>
21318 12:31:08.496604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
21319 12:31:08.497053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
21321 12:31:08.540636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
21322 12:31:08.541028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
21324 12:31:08.594221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
21326 12:31:08.594699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
21327 12:31:08.639494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass>
21328 12:31:08.639944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass
21330 12:31:08.691915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
21331 12:31:08.692327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
21333 12:31:08.747578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
21335 12:31:08.748059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
21336 12:31:08.798395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
21338 12:31:08.798960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
21339 12:31:08.848583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass
21341 12:31:08.849049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass>
21342 12:31:08.909178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
21343 12:31:08.909655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
21345 12:31:08.969827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
21346 12:31:08.970268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
21348 12:31:09.032177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
21349 12:31:09.032611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
21351 12:31:09.092746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass>
21352 12:31:09.093134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass
21354 12:31:09.153338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
21355 12:31:09.153786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
21357 12:31:09.213574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
21359 12:31:09.214024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
21360 12:31:09.275505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
21361 12:31:09.275918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
21363 12:31:09.336086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass
21365 12:31:09.336542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass>
21366 12:31:09.397541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
21367 12:31:09.397986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
21369 12:31:09.457300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
21370 12:31:09.457690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
21372 12:31:09.517869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
21373 12:31:09.518322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
21375 12:31:09.579808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass>
21376 12:31:09.580244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass
21378 12:31:09.666200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
21380 12:31:09.666627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
21381 12:31:09.724261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
21382 12:31:09.724701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
21384 12:31:09.777291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
21386 12:31:09.777933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
21387 12:31:09.828640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass>
21388 12:31:09.829062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass
21390 12:31:09.886210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
21392 12:31:09.886742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
21393 12:31:09.935617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
21395 12:31:09.936109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
21396 12:31:09.995004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
21397 12:31:09.995467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
21399 12:31:10.046860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass>
21400 12:31:10.047303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass
21402 12:31:10.105202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
21403 12:31:10.105635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
21405 12:31:10.159520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
21407 12:31:10.159992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
21408 12:31:10.213438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
21409 12:31:10.213903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
21411 12:31:10.267953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass
21413 12:31:10.268409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass>
21414 12:31:10.319361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
21415 12:31:10.319799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
21417 12:31:10.368983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
21418 12:31:10.369416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
21420 12:31:10.409947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
21422 12:31:10.410436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
21423 12:31:10.455361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass>
21424 12:31:10.455794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass
21426 12:31:10.505785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
21427 12:31:10.506220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
21429 12:31:10.548565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
21430 12:31:10.548976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
21432 12:31:10.595501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
21434 12:31:10.595934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
21435 12:31:10.639524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass>
21436 12:31:10.639968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass
21438 12:31:10.685918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
21439 12:31:10.686342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
21441 12:31:10.742283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
21443 12:31:10.742914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
21444 12:31:10.784688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
21445 12:31:10.785118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
21447 12:31:10.826301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass
21449 12:31:10.826770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass>
21450 12:31:10.869503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
21451 12:31:10.869882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
21453 12:31:10.908398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
21454 12:31:10.908841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
21456 12:31:10.949355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
21458 12:31:10.949850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
21459 12:31:10.997656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass>
21460 12:31:10.998122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass
21462 12:31:11.041454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
21463 12:31:11.041896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
21465 12:31:11.084490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
21466 12:31:11.084874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
21468 12:31:11.127303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
21469 12:31:11.127744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
21471 12:31:11.171785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass>
21472 12:31:11.172185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass
21474 12:31:11.211445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
21475 12:31:11.211984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
21477 12:31:11.251870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
21478 12:31:11.252348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
21480 12:31:11.290864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
21482 12:31:11.291327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
21483 12:31:11.330851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass>
21484 12:31:11.331243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass
21486 12:31:11.371760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
21487 12:31:11.372191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
21489 12:31:11.411233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
21490 12:31:11.411624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
21492 12:31:11.457163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
21493 12:31:11.457548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
21495 12:31:11.504567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass>
21496 12:31:11.505116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass
21498 12:31:11.543416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
21499 12:31:11.543940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
21501 12:31:11.588349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
21503 12:31:11.588821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
21504 12:31:11.632209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
21505 12:31:11.632646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
21507 12:31:11.680143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass
21509 12:31:11.680633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass>
21510 12:31:11.722831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
21511 12:31:11.723262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
21513 12:31:11.760994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
21514 12:31:11.761446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
21516 12:31:11.801324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
21517 12:31:11.801743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
21519 12:31:11.842249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass
21521 12:31:11.842683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass>
21522 12:31:11.879568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
21523 12:31:11.879993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
21525 12:31:11.924381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
21526 12:31:11.924779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
21528 12:31:11.965339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
21529 12:31:11.965778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
21531 12:31:12.020855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
21532 12:31:12.021286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
21534 12:31:12.075730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass>
21535 12:31:12.076161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass
21537 12:31:12.115771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
21538 12:31:12.116201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
21540 12:31:12.152581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
21541 12:31:12.152998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
21543 12:31:12.191472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass>
21544 12:31:12.191915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass
21546 12:31:12.235137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass>
21547 12:31:12.235580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass
21549 12:31:12.273104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass>
21550 12:31:12.273557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass
21552 12:31:12.312009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass>
21553 12:31:12.312428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass
21555 12:31:12.350866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass>
21556 12:31:12.351309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass
21558 12:31:12.394369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass
21560 12:31:12.394834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass>
21561 12:31:12.432352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass>
21562 12:31:12.432790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass
21564 12:31:12.480848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass>
21565 12:31:12.481276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass
21567 12:31:12.517702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass>
21568 12:31:12.518138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass
21570 12:31:12.571475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip>
21571 12:31:12.572000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip
21573 12:31:12.628533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip>
21574 12:31:12.628948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip
21576 12:31:12.687898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip>
21577 12:31:12.688339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip
21579 12:31:12.748387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass>
21580 12:31:12.748822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass
21582 12:31:12.807244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass>
21583 12:31:12.807689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass
21585 12:31:12.865473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass>
21586 12:31:12.865913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass
21588 12:31:12.923795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass>
21589 12:31:12.924208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass
21591 12:31:12.981472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass
21593 12:31:12.981997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass>
21594 12:31:13.040023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip>
21595 12:31:13.040409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip
21597 12:31:13.097243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip>
21598 12:31:13.097759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip
21600 12:31:13.147516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip>
21601 12:31:13.147946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip
21603 12:31:13.197670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass>
21604 12:31:13.198086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass
21606 12:31:13.250334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip
21608 12:31:13.251024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip>
21609 12:31:13.305293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip>
21610 12:31:13.305732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip
21612 12:31:13.361934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip
21614 12:31:13.362497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip>
21615 12:31:13.411610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass
21617 12:31:13.412100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass>
21618 12:31:13.464433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip>
21619 12:31:13.464865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip
21621 12:31:13.510233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip
21623 12:31:13.510731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip>
21624 12:31:13.561051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip
21626 12:31:13.561504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip>
21627 12:31:13.607127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass>
21628 12:31:13.607517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass
21630 12:31:13.653359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass>
21631 12:31:13.653775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass
21633 12:31:13.699542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass>
21634 12:31:13.699960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass
21636 12:31:13.759251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass>
21637 12:31:13.759699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass
21639 12:31:13.809303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass>
21640 12:31:13.809728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass
21642 12:31:13.861289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip>
21643 12:31:13.861693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip
21645 12:31:13.908716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip
21647 12:31:13.909213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip>
21648 12:31:13.957884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip
21650 12:31:13.958375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip>
21651 12:31:14.009060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass>
21652 12:31:14.009528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass
21654 12:31:14.059636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip
21656 12:31:14.060122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip>
21657 12:31:14.109207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip>
21658 12:31:14.109728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip
21660 12:31:14.152704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip>
21661 12:31:14.153128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip
21663 12:31:14.193880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass>
21664 12:31:14.194336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass
21666 12:31:14.233861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip>
21667 12:31:14.234423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip
21669 12:31:14.281771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip>
21670 12:31:14.282221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip
21672 12:31:14.329426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip>
21673 12:31:14.329870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip
21675 12:31:14.374166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass
21677 12:31:14.374637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass>
21678 12:31:14.420180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip>
21679 12:31:14.420627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip
21681 12:31:14.471566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip>
21682 12:31:14.472002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip
21684 12:31:14.516995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip>
21685 12:31:14.517438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip
21687 12:31:14.557527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass>
21688 12:31:14.557965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass
21690 12:31:14.601311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip
21692 12:31:14.601794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip>
21693 12:31:14.647604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip>
21694 12:31:14.648030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip
21696 12:31:14.695373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip>
21697 12:31:14.695813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip
21699 12:31:14.741479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass>
21700 12:31:14.741931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass
21702 12:31:14.803574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip>
21703 12:31:14.804002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip
21705 12:31:14.844442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip>
21706 12:31:14.844866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip
21708 12:31:14.883800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip>
21709 12:31:14.884229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip
21711 12:31:14.925959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass>
21712 12:31:14.926411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass
21714 12:31:14.967551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip>
21715 12:31:14.968015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip
21717 12:31:15.009111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip>
21718 12:31:15.009553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip
21720 12:31:15.052674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip
21722 12:31:15.053168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip>
21723 12:31:15.099103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass>
21724 12:31:15.099540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass
21726 12:31:15.140786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass>
21727 12:31:15.141197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass
21729 12:31:15.180963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass>
21730 12:31:15.181399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass
21732 12:31:15.223275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass>
21733 12:31:15.223712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass
21735 12:31:15.273084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass
21737 12:31:15.273570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass>
21738 12:31:15.313715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
21739 12:31:15.314271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
21741 12:31:15.352404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
21742 12:31:15.352851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
21744 12:31:15.391108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
21746 12:31:15.391487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
21747 12:31:15.432076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass>
21748 12:31:15.432520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass
21750 12:31:15.479551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
21752 12:31:15.480039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
21753 12:31:15.518862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
21754 12:31:15.519295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
21756 12:31:15.557514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
21757 12:31:15.557988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
21759 12:31:15.595764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass>
21760 12:31:15.596184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass
21762 12:31:15.643281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
21763 12:31:15.643720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
21765 12:31:15.680616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
21766 12:31:15.681034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
21768 12:31:15.718263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
21770 12:31:15.718750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
21771 12:31:15.756288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass>
21772 12:31:15.756729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass
21774 12:31:15.802115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
21776 12:31:15.802602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
21777 12:31:15.850341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
21779 12:31:15.850818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
21780 12:31:15.897625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
21781 12:31:15.898081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
21783 12:31:15.944711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass>
21784 12:31:15.945178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass
21786 12:31:15.994346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
21788 12:31:15.994879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
21789 12:31:16.049134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
21790 12:31:16.049577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
21792 12:31:16.101506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
21793 12:31:16.101967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
21795 12:31:16.150802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass>
21796 12:31:16.151260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass
21798 12:31:16.193018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
21799 12:31:16.193440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
21801 12:31:16.231974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
21802 12:31:16.232360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
21804 12:31:16.277100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
21805 12:31:16.277607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
21807 12:31:16.315776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass
21809 12:31:16.316479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass>
21810 12:31:16.354967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
21811 12:31:16.355381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
21813 12:31:16.395741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
21814 12:31:16.396180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
21816 12:31:16.438000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
21818 12:31:16.438484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
21819 12:31:16.477721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass
21821 12:31:16.478197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass>
21822 12:31:16.524400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
21823 12:31:16.524854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
21825 12:31:16.581454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
21826 12:31:16.581920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
21828 12:31:16.639823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
21829 12:31:16.640231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
21831 12:31:16.702218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass
21833 12:31:16.702656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass>
21834 12:31:16.763331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
21836 12:31:16.763754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
21837 12:31:16.823703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
21838 12:31:16.824162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
21840 12:31:16.885517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
21841 12:31:16.885994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
21843 12:31:16.936117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass>
21844 12:31:16.936561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass
21846 12:31:16.988668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
21848 12:31:16.989146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
21849 12:31:17.047924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
21850 12:31:17.048318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
21852 12:31:17.088082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
21853 12:31:17.088492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
21855 12:31:17.127439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass>
21856 12:31:17.127868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass
21858 12:31:17.168050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
21859 12:31:17.168481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
21861 12:31:17.207981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
21863 12:31:17.208418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
21864 12:31:17.252079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
21865 12:31:17.252514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
21867 12:31:17.291956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass>
21868 12:31:17.292395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass
21870 12:31:17.331832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
21871 12:31:17.332269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
21873 12:31:17.370964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
21874 12:31:17.371393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
21876 12:31:17.412385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
21877 12:31:17.412793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
21879 12:31:17.460323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass
21881 12:31:17.460801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass>
21882 12:31:17.501803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
21883 12:31:17.502225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
21885 12:31:17.543992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
21887 12:31:17.544477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
21888 12:31:17.597024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
21889 12:31:17.597431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
21891 12:31:17.637719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass>
21892 12:31:17.638141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass
21894 12:31:17.680360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
21895 12:31:17.680772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
21897 12:31:17.733360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
21898 12:31:17.733806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
21900 12:31:17.793232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
21901 12:31:17.793682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
21903 12:31:17.844181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass>
21904 12:31:17.844542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass
21906 12:31:17.884830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
21908 12:31:17.885310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
21909 12:31:17.926359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
21911 12:31:17.926820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
21912 12:31:17.977706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
21913 12:31:17.978154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
21915 12:31:18.033050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass>
21916 12:31:18.033481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass
21918 12:31:18.083859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
21919 12:31:18.084296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
21921 12:31:18.137737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
21922 12:31:18.138190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
21924 12:31:18.183216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
21926 12:31:18.183674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
21927 12:31:18.227453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass
21929 12:31:18.228106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass>
21930 12:31:18.266954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
21931 12:31:18.267378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
21933 12:31:18.318217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
21935 12:31:18.318701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
21936 12:31:18.371322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
21938 12:31:18.371797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
21939 12:31:18.423557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass
21941 12:31:18.424017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass>
21942 12:31:18.474228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
21944 12:31:18.474858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
21945 12:31:18.525411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
21946 12:31:18.525767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
21948 12:31:18.579308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
21949 12:31:18.579722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
21951 12:31:18.636149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass>
21952 12:31:18.636636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass
21954 12:31:18.695697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
21956 12:31:18.696180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
21957 12:31:18.753921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
21958 12:31:18.754354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
21960 12:31:18.815133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
21961 12:31:18.815661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
21963 12:31:18.864612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass>
21964 12:31:18.865043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass
21966 12:31:18.914038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
21968 12:31:18.914476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
21969 12:31:18.958234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
21971 12:31:18.958701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
21972 12:31:19.009915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
21973 12:31:19.010309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
21975 12:31:19.063036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass
21977 12:31:19.063547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass>
21978 12:31:19.111665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
21980 12:31:19.112108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
21981 12:31:19.155580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
21982 12:31:19.155956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
21984 12:31:19.199201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
21985 12:31:19.199628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
21987 12:31:19.249511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass
21989 12:31:19.249974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass>
21990 12:31:19.293160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
21991 12:31:19.293594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
21993 12:31:19.335430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
21995 12:31:19.335921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
21996 12:31:19.380759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
21997 12:31:19.381170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
21999 12:31:19.419430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass>
22000 12:31:19.419876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass
22002 12:31:19.465325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
22003 12:31:19.465765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
22005 12:31:19.515980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
22006 12:31:19.516417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
22008 12:31:19.559699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
22009 12:31:19.560134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
22011 12:31:19.599640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass
22013 12:31:19.600133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass>
22014 12:31:19.641344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
22016 12:31:19.642003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
22017 12:31:19.697563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
22018 12:31:19.698139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
22020 12:31:19.750847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
22021 12:31:19.751288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
22023 12:31:19.789078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass
22025 12:31:19.789553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass>
22026 12:31:19.828727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
22027 12:31:19.829179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
22029 12:31:19.882718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
22030 12:31:19.883152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
22032 12:31:19.937215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
22033 12:31:19.937666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
22035 12:31:19.990991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass>
22036 12:31:19.991420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass
22038 12:31:20.036783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
22039 12:31:20.037259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
22041 12:31:20.083355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
22042 12:31:20.083805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
22044 12:31:20.132792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
22046 12:31:20.133291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
22047 12:31:20.176600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass
22049 12:31:20.177037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass>
22050 12:31:20.220229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
22051 12:31:20.220775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
22053 12:31:20.263896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
22054 12:31:20.264294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
22056 12:31:20.313065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
22058 12:31:20.313842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
22059 12:31:20.363175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass>
22060 12:31:20.363584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass
22062 12:31:20.408674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
22064 12:31:20.409102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
22065 12:31:20.449189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
22066 12:31:20.449620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
22068 12:31:20.493022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
22069 12:31:20.493465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
22071 12:31:20.543043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass
22073 12:31:20.543798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass>
22074 12:31:20.599583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
22075 12:31:20.600017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
22077 12:31:20.642899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
22079 12:31:20.643668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
22080 12:31:20.685313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
22081 12:31:20.685739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
22083 12:31:20.735670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass
22085 12:31:20.736148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass>
22086 12:31:20.788630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
22087 12:31:20.789058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
22089 12:31:20.840121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
22090 12:31:20.840554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
22092 12:31:20.883725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
22093 12:31:20.884135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
22095 12:31:20.928725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass
22097 12:31:20.929181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass>
22098 12:31:20.972827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
22099 12:31:20.973229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
22101 12:31:21.020293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
22102 12:31:21.020734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
22104 12:31:21.064770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
22105 12:31:21.065198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
22107 12:31:21.102405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass
22109 12:31:21.102877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass>
22110 12:31:21.145469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
22111 12:31:21.145863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
22113 12:31:21.185765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
22114 12:31:21.186206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
22116 12:31:21.231733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
22117 12:31:21.232148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
22119 12:31:21.280202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass>
22120 12:31:21.280652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass
22122 12:31:21.329201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
22123 12:31:21.329712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
22125 12:31:21.380682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
22126 12:31:21.381119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
22128 12:31:21.426290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
22130 12:31:21.426881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
22131 12:31:21.470638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass>
22132 12:31:21.471116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass
22134 12:31:21.516115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
22136 12:31:21.516591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
22137 12:31:21.565565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
22139 12:31:21.566056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
22140 12:31:21.612462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
22141 12:31:21.612915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
22143 12:31:21.660136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass>
22144 12:31:21.660548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass
22146 12:31:21.701934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
22148 12:31:21.702699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
22149 12:31:21.746697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
22151 12:31:21.747177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
22152 12:31:21.789848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
22153 12:31:21.790301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
22155 12:31:21.835616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass>
22156 12:31:21.836165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass
22158 12:31:21.875871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
22160 12:31:21.876354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
22161 12:31:21.925594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
22162 12:31:21.926022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
22164 12:31:21.976346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
22165 12:31:21.976758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
22167 12:31:22.024842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass>
22168 12:31:22.025308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass
22170 12:31:22.073560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
22171 12:31:22.074036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
22173 12:31:22.126345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
22175 12:31:22.126959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
22176 12:31:22.169690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
22177 12:31:22.170110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
22179 12:31:22.213346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass>
22180 12:31:22.213805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass
22182 12:31:22.254948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
22183 12:31:22.255375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
22185 12:31:22.293552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
22186 12:31:22.293990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
22188 12:31:22.333718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
22189 12:31:22.334152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
22191 12:31:22.375632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass>
22192 12:31:22.376070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass
22194 12:31:22.419446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
22195 12:31:22.419908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
22197 12:31:22.460458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
22198 12:31:22.460898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
22200 12:31:22.503562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
22201 12:31:22.504000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
22203 12:31:22.547459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass>
22204 12:31:22.547857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass
22206 12:31:22.591378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
22207 12:31:22.591793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
22209 12:31:22.637702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
22210 12:31:22.638136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
22212 12:31:22.683605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
22213 12:31:22.684043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
22215 12:31:22.731349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass>
22216 12:31:22.731767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass
22218 12:31:22.776745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
22219 12:31:22.777197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
22221 12:31:22.824035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
22222 12:31:22.824460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
22224 12:31:22.868877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
22225 12:31:22.869306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
22227 12:31:22.914303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass
22229 12:31:22.914834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass>
22230 12:31:22.967755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
22231 12:31:22.968204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
22233 12:31:23.026187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
22235 12:31:23.026641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
22236 12:31:23.075594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
22237 12:31:23.075993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
22239 12:31:23.125888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass
22241 12:31:23.126394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass>
22242 12:31:23.172755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
22243 12:31:23.173179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
22245 12:31:23.217160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
22246 12:31:23.217596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
22248 12:31:23.265123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
22249 12:31:23.265568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
22251 12:31:23.313336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass>
22252 12:31:23.313779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass
22254 12:31:23.358948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
22255 12:31:23.359365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
22257 12:31:23.406851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
22258 12:31:23.407342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
22260 12:31:23.443645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
22261 12:31:23.444060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
22263 12:31:23.483123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass
22265 12:31:23.483795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass>
22266 12:31:23.525505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
22267 12:31:23.525928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
22269 12:31:23.567214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
22270 12:31:23.567625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
22272 12:31:23.607496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
22273 12:31:23.607885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
22275 12:31:23.653562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass>
22276 12:31:23.654010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass
22278 12:31:23.699147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
22279 12:31:23.699547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
22281 12:31:23.739318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
22283 12:31:23.739788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
22284 12:31:23.783777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
22286 12:31:23.784273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
22287 12:31:23.835199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass>
22288 12:31:23.835564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass
22290 12:31:23.881965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
22291 12:31:23.882416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
22293 12:31:23.927136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
22294 12:31:23.927590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
22296 12:31:23.984325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
22297 12:31:23.984725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
22299 12:31:24.039889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass>
22300 12:31:24.040281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass
22302 12:31:24.088482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
22303 12:31:24.088866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
22305 12:31:24.139574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
22306 12:31:24.140010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
22308 12:31:24.192983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
22309 12:31:24.193381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
22311 12:31:24.245155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass>
22312 12:31:24.245568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass
22314 12:31:24.293308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
22315 12:31:24.293692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
22317 12:31:24.342248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
22319 12:31:24.342855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
22320 12:31:24.393274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
22322 12:31:24.393780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
22323 12:31:24.437235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass
22325 12:31:24.437695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass>
22326 12:31:24.485069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
22327 12:31:24.485519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
22329 12:31:24.530324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
22331 12:31:24.530807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
22332 12:31:24.573783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
22333 12:31:24.574230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
22335 12:31:24.618321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass
22337 12:31:24.618791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass>
22338 12:31:24.663376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
22340 12:31:24.663842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
22341 12:31:24.704724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
22342 12:31:24.705147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
22344 12:31:24.743597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
22345 12:31:24.744140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
22347 12:31:24.786086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass
22349 12:31:24.786495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass>
22350 12:31:24.831846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
22351 12:31:24.832263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
22353 12:31:24.882945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
22354 12:31:24.883374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
22356 12:31:24.921684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
22357 12:31:24.922143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
22359 12:31:24.969721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass>
22360 12:31:24.970157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass
22362 12:31:25.051411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
22363 12:31:25.051855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
22365 12:31:25.105854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
22367 12:31:25.106343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
22368 12:31:25.145490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
22369 12:31:25.145928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
22371 12:31:25.187764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass
22373 12:31:25.188204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass>
22374 12:31:25.243586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
22375 12:31:25.243995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
22377 12:31:25.287862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
22378 12:31:25.288352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
22380 12:31:25.331414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
22382 12:31:25.331874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
22383 12:31:25.375108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass>
22384 12:31:25.375551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass
22386 12:31:25.419708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
22387 12:31:25.420141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
22389 12:31:25.466040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
22391 12:31:25.466750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
22392 12:31:25.521333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
22393 12:31:25.521767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
22395 12:31:25.580004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass>
22396 12:31:25.580462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass
22398 12:31:25.638124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
22400 12:31:25.638580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
22401 12:31:25.696901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
22402 12:31:25.697330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
22404 12:31:25.755708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
22405 12:31:25.756145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
22407 12:31:25.813618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass>
22408 12:31:25.814080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass
22410 12:31:25.872236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
22411 12:31:25.872670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
22413 12:31:25.929871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
22414 12:31:25.930259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
22416 12:31:25.988273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
22417 12:31:25.988857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
22419 12:31:26.047311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass>
22420 12:31:26.047806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass
22422 12:31:26.105081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
22423 12:31:26.105506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
22425 12:31:26.164244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
22427 12:31:26.164731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
22428 12:31:26.223052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
22430 12:31:26.223448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
22431 12:31:26.279828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass
22433 12:31:26.280323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass>
22434 12:31:26.328694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
22435 12:31:26.329122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
22437 12:31:26.379758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
22438 12:31:26.380152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
22440 12:31:26.427211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
22441 12:31:26.427608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
22443 12:31:26.477678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass>
22444 12:31:26.478206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass
22446 12:31:26.525635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
22447 12:31:26.525999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
22449 12:31:26.575930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
22451 12:31:26.576366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
22452 12:31:26.635977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
22453 12:31:26.636400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
22455 12:31:26.687989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass>
22456 12:31:26.688431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass
22458 12:31:26.732941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
22459 12:31:26.733328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
22461 12:31:26.780896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
22462 12:31:26.781322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
22464 12:31:26.823935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
22465 12:31:26.824366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
22467 12:31:26.874083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass
22469 12:31:26.874645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass>
22470 12:31:26.924104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
22471 12:31:26.924548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
22473 12:31:26.972745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
22474 12:31:26.973149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
22476 12:31:27.024609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
22478 12:31:27.025299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
22479 12:31:27.075898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass>
22480 12:31:27.076332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass
22482 12:31:27.126847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
22483 12:31:27.127286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
22485 12:31:27.175629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
22486 12:31:27.176081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
22488 12:31:27.225079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
22490 12:31:27.225558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
22491 12:31:27.273905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass
22493 12:31:27.274346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass>
22494 12:31:27.326105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
22496 12:31:27.326590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
22497 12:31:27.374463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
22499 12:31:27.374888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
22500 12:31:27.436182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
22501 12:31:27.436567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
22503 12:31:27.487306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass>
22504 12:31:27.487741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass
22506 12:31:27.533024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
22507 12:31:27.533467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
22509 12:31:27.580160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
22510 12:31:27.580611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
22512 12:31:27.621593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
22513 12:31:27.622024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
22515 12:31:27.665239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass
22517 12:31:27.665692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass>
22518 12:31:27.708565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
22519 12:31:27.709003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
22521 12:31:27.758805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
22523 12:31:27.759300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
22524 12:31:27.806732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
22525 12:31:27.807180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
22527 12:31:27.854784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass>
22528 12:31:27.855187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass
22530 12:31:27.904593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
22531 12:31:27.904947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
22533 12:31:27.963025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
22534 12:31:27.963448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
22536 12:31:28.009099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
22537 12:31:28.009539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
22539 12:31:28.063421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass>
22540 12:31:28.063859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass
22542 12:31:28.110401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
22544 12:31:28.110930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
22545 12:31:28.158668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
22546 12:31:28.159132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
22548 12:31:28.207255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
22550 12:31:28.207746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
22551 12:31:28.259510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass
22553 12:31:28.259965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass>
22554 12:31:28.304989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
22555 12:31:28.305546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
22557 12:31:28.351691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
22558 12:31:28.352103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
22560 12:31:28.395803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
22561 12:31:28.396244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
22563 12:31:28.445377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass>
22564 12:31:28.445765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass
22566 12:31:28.493416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
22567 12:31:28.493822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
22569 12:31:28.540177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
22571 12:31:28.540666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
22572 12:31:28.593990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
22574 12:31:28.594605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
22575 12:31:28.646147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass
22577 12:31:28.646611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass>
22578 12:31:28.699246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
22579 12:31:28.699636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
22581 12:31:28.742294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
22583 12:31:28.742765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
22584 12:31:28.788515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
22585 12:31:28.788937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
22587 12:31:28.831500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass
22589 12:31:28.831974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass>
22590 12:31:28.880304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
22591 12:31:28.880796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
22593 12:31:28.919940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
22594 12:31:28.920386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
22596 12:31:28.966335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
22598 12:31:28.966817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
22599 12:31:29.016441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass
22601 12:31:29.016876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass>
22602 12:31:29.075582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
22603 12:31:29.076017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
22605 12:31:29.133823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
22606 12:31:29.134271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
22608 12:31:29.192801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
22609 12:31:29.193248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
22611 12:31:29.251327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass>
22612 12:31:29.251765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass
22614 12:31:29.308626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
22615 12:31:29.309052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
22617 12:31:29.367026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
22618 12:31:29.367511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
22620 12:31:29.425618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
22621 12:31:29.426067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
22623 12:31:29.484063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass
22625 12:31:29.484546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass>
22626 12:31:29.531617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
22627 12:31:29.532062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
22629 12:31:29.573506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
22630 12:31:29.573950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
22632 12:31:29.616236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
22633 12:31:29.616795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
22635 12:31:29.659756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass>
22636 12:31:29.660198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass
22638 12:31:29.707062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
22640 12:31:29.707532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
22641 12:31:29.747905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
22642 12:31:29.748318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
22644 12:31:29.790990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
22645 12:31:29.791396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
22647 12:31:29.835487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass
22649 12:31:29.835966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass>
22650 12:31:29.879469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
22651 12:31:29.879901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
22653 12:31:29.927348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
22654 12:31:29.927758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
22656 12:31:29.968331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
22657 12:31:29.968764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
22659 12:31:30.013255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass
22661 12:31:30.013752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass>
22662 12:31:30.060495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
22663 12:31:30.060932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
22665 12:31:30.111045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
22666 12:31:30.111440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
22668 12:31:30.192373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
22669 12:31:30.192788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
22671 12:31:30.242857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass>
22672 12:31:30.243311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass
22674 12:31:30.293628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
22676 12:31:30.294153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
22677 12:31:30.347374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
22679 12:31:30.347868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
22680 12:31:30.396206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
22682 12:31:30.396687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
22683 12:31:30.451391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass>
22684 12:31:30.451917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass
22686 12:31:30.503760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
22687 12:31:30.504169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
22689 12:31:30.553453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
22691 12:31:30.553937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
22692 12:31:30.605132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
22693 12:31:30.605579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
22695 12:31:30.655868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass>
22696 12:31:30.656319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass
22698 12:31:30.712197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
22699 12:31:30.712697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
22701 12:31:30.767440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
22702 12:31:30.767926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
22704 12:31:30.812150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
22705 12:31:30.812594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
22707 12:31:30.868121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass>
22708 12:31:30.868578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass
22710 12:31:30.912235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
22712 12:31:30.912719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
22713 12:31:30.960766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
22714 12:31:30.961202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
22716 12:31:31.003628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
22717 12:31:31.004080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
22719 12:31:31.044841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass>
22720 12:31:31.045276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass
22722 12:31:31.087277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
22723 12:31:31.087759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
22725 12:31:31.131941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
22726 12:31:31.132497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
22728 12:31:31.180291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
22730 12:31:31.180785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
22731 12:31:31.227854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass>
22732 12:31:31.228290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass
22734 12:31:31.267095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
22735 12:31:31.267524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
22737 12:31:31.309713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
22739 12:31:31.310142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
22740 12:31:31.358345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
22742 12:31:31.359118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
22743 12:31:31.415967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass
22745 12:31:31.416448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass>
22746 12:31:31.468172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
22747 12:31:31.468622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
22749 12:31:31.517090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
22751 12:31:31.517528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
22752 12:31:31.567451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
22753 12:31:31.567871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
22755 12:31:31.613916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass>
22756 12:31:31.614468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass
22758 12:31:31.665376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
22759 12:31:31.665885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
22761 12:31:31.715573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
22762 12:31:31.716014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
22764 12:31:31.764519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
22765 12:31:31.764964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
22767 12:31:31.816254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass
22769 12:31:31.816686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass>
22770 12:31:31.860307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
22771 12:31:31.860739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
22773 12:31:31.905024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
22774 12:31:31.905411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
22776 12:31:31.953461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
22778 12:31:31.953931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
22779 12:31:31.994917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass>
22780 12:31:31.995370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass
22782 12:31:32.035453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
22784 12:31:32.035912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
22785 12:31:32.092318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
22787 12:31:32.092802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
22788 12:31:32.137940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
22789 12:31:32.138379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
22791 12:31:32.180156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass>
22792 12:31:32.180584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass
22794 12:31:32.222916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
22795 12:31:32.223449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
22797 12:31:32.264831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
22798 12:31:32.265349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
22800 12:31:32.310371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
22802 12:31:32.311184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
22803 12:31:32.347951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass>
22804 12:31:32.348407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass
22806 12:31:32.389068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
22807 12:31:32.389495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
22809 12:31:32.430780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
22810 12:31:32.431220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
22812 12:31:32.478556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
22813 12:31:32.479002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
22815 12:31:32.521338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass>
22816 12:31:32.521728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass
22818 12:31:32.567141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
22819 12:31:32.567566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
22821 12:31:32.614887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
22822 12:31:32.615322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
22824 12:31:32.663425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
22825 12:31:32.663864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
22827 12:31:32.709608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass
22829 12:31:32.710058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass>
22830 12:31:32.757722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
22831 12:31:32.758157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
22833 12:31:32.807361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
22834 12:31:32.807792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
22836 12:31:32.852376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
22838 12:31:32.852838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
22839 12:31:32.898065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass
22841 12:31:32.898768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass>
22842 12:31:32.943561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
22843 12:31:32.944005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
22845 12:31:32.992103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
22846 12:31:32.992539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
22848 12:31:33.033785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
22849 12:31:33.034221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
22851 12:31:33.073616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass
22853 12:31:33.074103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass>
22854 12:31:33.112613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
22856 12:31:33.113090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
22857 12:31:33.160197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
22858 12:31:33.160596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
22860 12:31:33.209014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
22861 12:31:33.209376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
22863 12:31:33.259145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass
22865 12:31:33.259620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass>
22866 12:31:33.304199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
22867 12:31:33.304629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
22869 12:31:33.349049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
22871 12:31:33.349470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
22872 12:31:33.399319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
22873 12:31:33.399756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
22875 12:31:33.444434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass>
22876 12:31:33.444870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass
22878 12:31:33.487874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
22879 12:31:33.488370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
22881 12:31:33.525634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
22882 12:31:33.526207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
22884 12:31:33.572965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
22885 12:31:33.573370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
22887 12:31:33.613640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass>
22888 12:31:33.614080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass
22890 12:31:33.652938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
22892 12:31:33.653399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
22893 12:31:33.691524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
22894 12:31:33.691952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
22896 12:31:33.729714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
22897 12:31:33.730132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
22899 12:31:33.776018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass
22901 12:31:33.776619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass>
22902 12:31:33.815772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
22904 12:31:33.816251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
22905 12:31:33.855094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
22907 12:31:33.855534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
22908 12:31:33.896971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
22909 12:31:33.897357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
22911 12:31:33.944703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass>
22912 12:31:33.945152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass
22914 12:31:33.993575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
22916 12:31:33.994324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
22917 12:31:34.035989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
22918 12:31:34.036460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
22920 12:31:34.093082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
22921 12:31:34.093517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
22923 12:31:34.152153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass
22925 12:31:34.152637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass>
22926 12:31:34.197161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
22927 12:31:34.197599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
22929 12:31:34.252562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
22930 12:31:34.252971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
22932 12:31:34.302272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
22934 12:31:34.302694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
22935 12:31:34.352412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass
22937 12:31:34.352887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass>
22938 12:31:34.405254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
22940 12:31:34.405630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
22941 12:31:34.453060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
22942 12:31:34.453494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
22944 12:31:34.500124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
22945 12:31:34.500574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
22947 12:31:34.544243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass>
22948 12:31:34.544679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass
22950 12:31:34.588085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
22951 12:31:34.588557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
22953 12:31:34.633870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
22954 12:31:34.634289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
22956 12:31:34.691174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
22957 12:31:34.691576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
22959 12:31:34.736808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass
22961 12:31:34.737244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass>
22962 12:31:34.785398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
22963 12:31:34.785834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
22965 12:31:34.840033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
22966 12:31:34.840426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
22968 12:31:34.885794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
22969 12:31:34.886232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
22971 12:31:34.927340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass>
22972 12:31:34.927783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass
22974 12:31:34.968599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
22976 12:31:34.968995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
22977 12:31:35.023808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
22979 12:31:35.024246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
22980 12:31:35.075713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
22981 12:31:35.076141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
22983 12:31:35.125631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass>
22984 12:31:35.126113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass
22986 12:31:35.175802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
22987 12:31:35.176194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
22989 12:31:35.218392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
22991 12:31:35.218810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
22992 12:31:35.286259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
22994 12:31:35.287766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
22995 12:31:35.335955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass>
22996 12:31:35.336534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass
22998 12:31:35.389591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
22999 12:31:35.390099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
23001 12:31:35.440843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
23003 12:31:35.441354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
23004 12:31:35.489834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
23005 12:31:35.490281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
23007 12:31:35.547362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass
23009 12:31:35.547822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass>
23010 12:31:35.604190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
23011 12:31:35.604756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
23013 12:31:35.663324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
23015 12:31:35.663809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
23016 12:31:35.721843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
23017 12:31:35.722255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
23019 12:31:35.781815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass>
23020 12:31:35.782230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass
23022 12:31:35.839169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
23023 12:31:35.839739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
23025 12:31:35.897100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
23026 12:31:35.897657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
23028 12:31:35.956733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
23029 12:31:35.957173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
23031 12:31:36.016005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass>
23032 12:31:36.016462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass
23034 12:31:36.074391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
23036 12:31:36.074880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
23037 12:31:36.132779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
23038 12:31:36.133299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
23040 12:31:36.192574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
23041 12:31:36.192985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
23043 12:31:36.252440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass
23045 12:31:36.252874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass>
23046 12:31:36.310477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
23048 12:31:36.311468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
23049 12:31:36.370312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
23051 12:31:36.370791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
23052 12:31:36.428546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
23053 12:31:36.428980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
23055 12:31:36.487708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass
23057 12:31:36.488212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass>
23058 12:31:36.548222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
23059 12:31:36.548741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
23061 12:31:36.607823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
23062 12:31:36.608173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
23064 12:31:36.666133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
23065 12:31:36.666544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
23067 12:31:36.724529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass>
23068 12:31:36.725103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass
23070 12:31:36.783550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
23071 12:31:36.783976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
23073 12:31:36.840848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
23074 12:31:36.841220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
23076 12:31:36.901773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
23077 12:31:36.902190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
23079 12:31:36.961390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass
23081 12:31:36.961785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass>
23082 12:31:37.020383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
23083 12:31:37.020818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
23085 12:31:37.078878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
23086 12:31:37.079373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
23088 12:31:37.137212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
23090 12:31:37.137688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
23091 12:31:37.196200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass>
23092 12:31:37.196672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass
23094 12:31:37.254816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
23095 12:31:37.255267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
23097 12:31:37.313340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
23098 12:31:37.313738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
23100 12:31:37.373029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
23101 12:31:37.373415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
23103 12:31:37.432107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass>
23104 12:31:37.432530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass
23106 12:31:37.491593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
23107 12:31:37.492039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
23109 12:31:37.549460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
23111 12:31:37.549919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
23112 12:31:37.604861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
23113 12:31:37.605330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
23115 12:31:37.649659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass
23117 12:31:37.650148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass>
23118 12:31:37.691069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
23120 12:31:37.691528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
23121 12:31:37.743616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
23122 12:31:37.744073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
23124 12:31:37.804764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
23125 12:31:37.805227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
23127 12:31:37.866181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass
23129 12:31:37.866663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass>
23130 12:31:37.924719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
23132 12:31:37.925192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
23133 12:31:37.984598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
23134 12:31:37.984986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
23136 12:31:38.031469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
23138 12:31:38.031960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
23139 12:31:38.092248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass>
23140 12:31:38.092684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass
23142 12:31:38.149951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
23144 12:31:38.150428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
23145 12:31:38.191701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
23146 12:31:38.192148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
23148 12:31:38.232112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
23149 12:31:38.232572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
23151 12:31:38.273320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass>
23152 12:31:38.273697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass
23154 12:31:38.316796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
23156 12:31:38.317252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
23157 12:31:38.363712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
23158 12:31:38.364135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
23160 12:31:38.403816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
23161 12:31:38.404238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
23163 12:31:38.447855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass>
23164 12:31:38.448294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass
23166 12:31:38.491264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
23167 12:31:38.491677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
23169 12:31:38.536982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
23171 12:31:38.537452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
23172 12:31:38.579250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
23173 12:31:38.579646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
23175 12:31:38.617106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass>
23176 12:31:38.617902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass
23178 12:31:38.659530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
23179 12:31:38.660088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
23181 12:31:38.704937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
23182 12:31:38.705452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
23184 12:31:38.745823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
23186 12:31:38.746409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
23187 12:31:38.791268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass>
23188 12:31:38.791756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass
23190 12:31:38.829458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
23191 12:31:38.830015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
23193 12:31:38.869181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
23194 12:31:38.869716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
23196 12:31:38.908253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
23197 12:31:38.908684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
23199 12:31:38.949844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass>
23200 12:31:38.950287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass
23202 12:31:39.001394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
23203 12:31:39.001824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
23205 12:31:39.050703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
23206 12:31:39.051108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
23208 12:31:39.093855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
23209 12:31:39.094289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
23211 12:31:39.139211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass>
23212 12:31:39.139596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass
23214 12:31:39.187052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
23216 12:31:39.187535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
23217 12:31:39.236345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
23219 12:31:39.236801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
23220 12:31:39.288242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
23221 12:31:39.288609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
23223 12:31:39.329086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass>
23224 12:31:39.329472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass
23226 12:31:39.373265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
23228 12:31:39.373861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
23229 12:31:39.420183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
23231 12:31:39.420945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
23232 12:31:39.465697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
23233 12:31:39.466121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
23235 12:31:39.511994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass>
23236 12:31:39.512487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass
23238 12:31:39.561324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
23239 12:31:39.561750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
23241 12:31:39.604260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
23243 12:31:39.605004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
23244 12:31:39.642352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
23246 12:31:39.642783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
23247 12:31:39.691534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass
23249 12:31:39.692015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass>
23250 12:31:39.739282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
23251 12:31:39.739776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
23253 12:31:39.780927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
23254 12:31:39.781361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
23256 12:31:39.820732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
23257 12:31:39.821174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
23259 12:31:39.863890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass
23261 12:31:39.864377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass>
23262 12:31:39.920601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
23264 12:31:39.921072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
23265 12:31:39.980021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
23266 12:31:39.980447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
23268 12:31:40.040067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
23269 12:31:40.040507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
23271 12:31:40.096807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass
23273 12:31:40.097254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass>
23274 12:31:40.156823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
23275 12:31:40.157227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
23277 12:31:40.216967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
23278 12:31:40.217406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
23280 12:31:40.277095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
23281 12:31:40.277507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
23283 12:31:40.337206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass>
23284 12:31:40.337604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass
23286 12:31:40.407499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
23287 12:31:40.407890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
23289 12:31:40.453846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
23290 12:31:40.454290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
23292 12:31:40.499633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
23293 12:31:40.500081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
23295 12:31:40.549424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass>
23296 12:31:40.549857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass
23298 12:31:40.608014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
23299 12:31:40.609743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
23301 12:31:40.656572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
23302 12:31:40.656954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
23304 12:31:40.703876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
23306 12:31:40.704331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
23307 12:31:40.753976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass
23309 12:31:40.754452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass>
23310 12:31:40.797812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
23311 12:31:40.798261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
23313 12:31:40.851670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
23314 12:31:40.852244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
23316 12:31:40.909900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
23317 12:31:40.910314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
23319 12:31:40.967764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass>
23320 12:31:40.968197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass
23322 12:31:41.005551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
23323 12:31:41.005973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
23325 12:31:41.049071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
23326 12:31:41.049465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
23328 12:31:41.087556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
23329 12:31:41.087966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
23331 12:31:41.130554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass>
23332 12:31:41.131007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass
23334 12:31:41.171198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
23335 12:31:41.171618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
23337 12:31:41.232471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
23338 12:31:41.232892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
23340 12:31:41.293448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
23341 12:31:41.293919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
23343 12:31:41.348087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass
23345 12:31:41.348579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass>
23346 12:31:41.398213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
23348 12:31:41.398685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
23349 12:31:41.454174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
23351 12:31:41.454631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
23352 12:31:41.511251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
23353 12:31:41.511686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
23355 12:31:41.560128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass>
23356 12:31:41.560594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass
23358 12:31:41.601466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
23359 12:31:41.601895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
23361 12:31:41.654273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
23363 12:31:41.654784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
23364 12:31:41.709209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
23365 12:31:41.709653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
23367 12:31:41.755225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass>
23368 12:31:41.755730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass
23370 12:31:41.807174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
23371 12:31:41.807531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
23373 12:31:41.860254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
23374 12:31:41.860704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
23376 12:31:41.913381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
23377 12:31:41.913928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
23379 12:31:41.956053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass
23381 12:31:41.956516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass>
23382 12:31:41.996771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
23383 12:31:41.997228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
23385 12:31:42.038160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
23387 12:31:42.038646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
23388 12:31:42.079217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
23389 12:31:42.079649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
23391 12:31:42.118767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass>
23392 12:31:42.119222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass
23394 12:31:42.164435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
23395 12:31:42.164888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
23397 12:31:42.216661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
23398 12:31:42.217116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
23400 12:31:42.263611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
23401 12:31:42.264042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
23403 12:31:42.307948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass>
23404 12:31:42.308363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass
23406 12:31:42.364267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
23407 12:31:42.364653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
23409 12:31:42.406298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
23411 12:31:42.406771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
23412 12:31:42.451678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
23414 12:31:42.452121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
23415 12:31:42.497214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass>
23416 12:31:42.497622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass
23418 12:31:42.546923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
23419 12:31:42.547361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
23421 12:31:42.597558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
23422 12:31:42.598000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
23424 12:31:42.646613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
23425 12:31:42.647088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
23427 12:31:42.688099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass>
23428 12:31:42.688520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass
23430 12:31:42.741130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
23431 12:31:42.741559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
23433 12:31:42.787078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
23434 12:31:42.787545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
23436 12:31:42.833269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
23437 12:31:42.833698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
23439 12:31:42.892118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass>
23440 12:31:42.892549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass
23442 12:31:42.931732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
23444 12:31:42.932192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
23445 12:31:42.972750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
23447 12:31:42.973238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
23448 12:31:43.015836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
23450 12:31:43.016432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
23451 12:31:43.068098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass
23453 12:31:43.068526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass>
23454 12:31:43.118765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
23455 12:31:43.119172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
23457 12:31:43.169574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
23458 12:31:43.169994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
23460 12:31:43.230909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
23461 12:31:43.231328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
23463 12:31:43.275467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass>
23464 12:31:43.275818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass
23466 12:31:43.315495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
23467 12:31:43.315930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
23469 12:31:43.360682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
23470 12:31:43.361115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
23472 12:31:43.405212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
23473 12:31:43.405681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
23475 12:31:43.453998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass
23477 12:31:43.454405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass>
23478 12:31:43.503879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
23480 12:31:43.504328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
23481 12:31:43.548402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
23482 12:31:43.548830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
23484 12:31:43.588671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
23485 12:31:43.589112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
23487 12:31:43.629637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass
23489 12:31:43.630130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass>
23490 12:31:43.668784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
23492 12:31:43.669229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
23493 12:31:43.709539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
23494 12:31:43.709978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
23496 12:31:43.753083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
23497 12:31:43.753534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
23499 12:31:43.791693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass>
23500 12:31:43.792208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass
23502 12:31:43.849273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
23503 12:31:43.849776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
23505 12:31:43.907631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
23506 12:31:43.908111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
23508 12:31:43.966974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
23509 12:31:43.967353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
23511 12:31:44.025453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass>
23512 12:31:44.025892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass
23514 12:31:44.083989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
23515 12:31:44.084466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
23517 12:31:44.131037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
23518 12:31:44.131447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
23520 12:31:44.173040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
23522 12:31:44.173505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
23523 12:31:44.221221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass>
23524 12:31:44.221681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass
23526 12:31:44.264671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
23528 12:31:44.265147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
23529 12:31:44.309348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
23531 12:31:44.309794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
23532 12:31:44.359539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
23533 12:31:44.359914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
23535 12:31:44.404903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass>
23536 12:31:44.405349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass
23538 12:31:44.448976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
23539 12:31:44.449416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
23541 12:31:44.496061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
23542 12:31:44.496453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
23544 12:31:44.537220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
23546 12:31:44.537695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
23547 12:31:44.578408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass
23549 12:31:44.579116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass>
23550 12:31:44.624430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
23551 12:31:44.624832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
23553 12:31:44.664847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
23554 12:31:44.665352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
23556 12:31:44.704294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
23557 12:31:44.704679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
23559 12:31:44.742712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass
23561 12:31:44.743463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass>
23562 12:31:44.785683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
23563 12:31:44.786121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
23565 12:31:44.828323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
23566 12:31:44.828755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
23568 12:31:44.875612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
23570 12:31:44.876320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
23571 12:31:44.914768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass>
23572 12:31:44.915216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass
23574 12:31:44.953661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
23575 12:31:44.954118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
23577 12:31:44.997481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
23578 12:31:44.997934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
23580 12:31:45.036981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
23582 12:31:45.037462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
23583 12:31:45.078136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass
23585 12:31:45.078607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass>
23586 12:31:45.120318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
23587 12:31:45.120709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
23589 12:31:45.169882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
23590 12:31:45.170304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
23592 12:31:45.222364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
23594 12:31:45.222836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
23595 12:31:45.271618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass
23597 12:31:45.272083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass>
23598 12:31:45.331744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
23599 12:31:45.332174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
23601 12:31:45.377717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
23602 12:31:45.378138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
23604 12:31:45.418230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
23606 12:31:45.418814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
23607 12:31:45.483811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass>
23608 12:31:45.484259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass
23610 12:31:45.537764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
23611 12:31:45.538222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
23613 12:31:45.582304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
23615 12:31:45.582780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
23616 12:31:45.624308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
23617 12:31:45.624751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
23619 12:31:45.666229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass
23621 12:31:45.666713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass>
23622 12:31:45.711809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
23624 12:31:45.712261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
23625 12:31:45.747794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
23626 12:31:45.748190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
23628 12:31:45.785011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
23629 12:31:45.785456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
23631 12:31:45.824403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass>
23632 12:31:45.824963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass
23634 12:31:45.860200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
23636 12:31:45.860686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
23637 12:31:45.901811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
23638 12:31:45.902236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
23640 12:31:45.941692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
23641 12:31:45.942135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
23643 12:31:45.979951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass>
23644 12:31:45.980497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass
23646 12:31:46.020669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
23647 12:31:46.021027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
23649 12:31:46.066173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
23651 12:31:46.066597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
23652 12:31:46.115682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
23653 12:31:46.116188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
23655 12:31:46.159918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass
23657 12:31:46.160399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass>
23658 12:31:46.203223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
23659 12:31:46.203612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
23661 12:31:46.247873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
23662 12:31:46.248272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
23664 12:31:46.295482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
23665 12:31:46.296014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
23667 12:31:46.337079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass>
23668 12:31:46.337520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass
23670 12:31:46.380280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
23671 12:31:46.380831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
23673 12:31:46.421510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
23675 12:31:46.421918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
23676 12:31:46.473122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
23677 12:31:46.473580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
23679 12:31:46.527600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass
23681 12:31:46.528083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass>
23682 12:31:46.585083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
23684 12:31:46.585560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
23685 12:31:46.633834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
23687 12:31:46.634333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
23688 12:31:46.679994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
23689 12:31:46.680421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
23691 12:31:46.725323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass>
23692 12:31:46.725769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass
23694 12:31:46.767948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
23695 12:31:46.768338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
23697 12:31:46.814954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
23698 12:31:46.815389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
23700 12:31:46.857104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
23702 12:31:46.857500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
23703 12:31:46.906250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass
23705 12:31:46.906687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass>
23706 12:31:46.944670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
23707 12:31:46.945093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
23709 12:31:46.989182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
23711 12:31:46.989668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
23712 12:31:47.034668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
23713 12:31:47.035110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
23715 12:31:47.077068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass>
23716 12:31:47.077480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass
23718 12:31:47.120696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
23719 12:31:47.121130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
23721 12:31:47.164490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
23722 12:31:47.164895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
23724 12:31:47.207665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
23726 12:31:47.208126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
23727 12:31:47.248065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass>
23728 12:31:47.248451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass
23730 12:31:47.299392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
23731 12:31:47.299810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
23733 12:31:47.357213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
23735 12:31:47.357633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
23736 12:31:47.406767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
23737 12:31:47.407173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
23739 12:31:47.445251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass>
23740 12:31:47.445637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass
23742 12:31:47.496067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
23743 12:31:47.496555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
23745 12:31:47.548729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
23747 12:31:47.549196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
23748 12:31:47.595606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
23749 12:31:47.596047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
23751 12:31:47.639157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass
23753 12:31:47.639643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass>
23754 12:31:47.685832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
23755 12:31:47.686232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
23757 12:31:47.736239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
23758 12:31:47.736677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
23760 12:31:47.804083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
23761 12:31:47.804470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
23763 12:31:47.851944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass>
23764 12:31:47.852395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass
23766 12:31:47.903750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
23767 12:31:47.904197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
23769 12:31:47.947339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
23770 12:31:47.947770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
23772 12:31:47.988400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
23773 12:31:47.988808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
23775 12:31:48.025788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass>
23776 12:31:48.026231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass
23778 12:31:48.063747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
23779 12:31:48.064220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
23781 12:31:48.103883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
23783 12:31:48.104353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
23784 12:31:48.145367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
23785 12:31:48.145874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
23787 12:31:48.191449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass>
23788 12:31:48.191871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass
23790 12:31:48.231428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
23791 12:31:48.231845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
23793 12:31:48.276924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
23794 12:31:48.277358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
23796 12:31:48.317341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
23797 12:31:48.317902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
23799 12:31:48.355457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass>
23800 12:31:48.356000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass
23802 12:31:48.400398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
23803 12:31:48.400830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
23805 12:31:48.438904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
23806 12:31:48.439344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
23808 12:31:48.479263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
23809 12:31:48.479696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
23811 12:31:48.521449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass>
23812 12:31:48.521871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass
23814 12:31:48.560173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
23816 12:31:48.560656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
23817 12:31:48.602042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
23819 12:31:48.602501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
23820 12:31:48.644948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
23822 12:31:48.645426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
23823 12:31:48.684305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass>
23824 12:31:48.684725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass
23826 12:31:48.725479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
23827 12:31:48.725938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
23829 12:31:48.768062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
23831 12:31:48.768548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
23832 12:31:48.819338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
23833 12:31:48.819890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
23835 12:31:48.869793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass>
23836 12:31:48.870198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass
23838 12:31:48.921572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
23839 12:31:48.922026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
23841 12:31:48.962858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
23842 12:31:48.963294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
23844 12:31:49.007357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
23845 12:31:49.007753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
23847 12:31:49.056145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass>
23848 12:31:49.056576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass
23850 12:31:49.103474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
23851 12:31:49.103902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
23853 12:31:49.156419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
23854 12:31:49.156865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
23856 12:31:49.212214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
23858 12:31:49.212614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
23859 12:31:49.272497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass
23861 12:31:49.272940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass>
23862 12:31:49.318857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
23863 12:31:49.319251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
23865 12:31:49.359597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
23866 12:31:49.360011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
23868 12:31:49.407997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
23869 12:31:49.408399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
23871 12:31:49.448204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass>
23872 12:31:49.448622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass
23874 12:31:49.488868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
23875 12:31:49.489278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
23877 12:31:49.530126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
23878 12:31:49.530535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
23880 12:31:49.572974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
23882 12:31:49.573464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
23883 12:31:49.617418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass>
23884 12:31:49.617867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass
23886 12:31:49.659381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
23887 12:31:49.659843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
23889 12:31:49.707342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
23891 12:31:49.707833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
23892 12:31:49.755004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
23893 12:31:49.755455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
23895 12:31:49.805023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass>
23896 12:31:49.805444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass
23898 12:31:49.845577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
23899 12:31:49.846080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
23901 12:31:49.894824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
23902 12:31:49.895230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
23904 12:31:49.933614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
23906 12:31:49.934108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
23907 12:31:49.980419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass>
23908 12:31:49.981065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass
23910 12:31:50.028230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
23911 12:31:50.028865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
23913 12:31:50.077492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
23915 12:31:50.077979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
23916 12:31:50.128919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
23917 12:31:50.129486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
23919 12:31:50.183112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass
23921 12:31:50.183855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass>
23922 12:31:50.236695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
23924 12:31:50.237175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
23925 12:31:50.289357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
23926 12:31:50.289799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
23928 12:31:50.341206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
23929 12:31:50.341591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
23931 12:31:50.391934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass>
23932 12:31:50.392372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass
23934 12:31:50.435042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
23935 12:31:50.435483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
23937 12:31:50.491604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
23938 12:31:50.492035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
23940 12:31:50.546511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
23941 12:31:50.546922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
23943 12:31:50.608477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass>
23944 12:31:50.608893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass
23946 12:31:50.676120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
23948 12:31:50.676608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
23949 12:31:50.736553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
23951 12:31:50.737189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
23952 12:31:50.787930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
23953 12:31:50.788410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
23955 12:31:50.832654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass>
23956 12:31:50.833089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass
23958 12:31:50.873468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
23959 12:31:50.873911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
23961 12:31:50.921544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
23962 12:31:50.922006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
23964 12:31:50.968741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
23965 12:31:50.969196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
23967 12:31:51.019342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass>
23968 12:31:51.019754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass
23970 12:31:51.072055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
23972 12:31:51.072723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
23973 12:31:51.128613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
23974 12:31:51.129003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
23976 12:31:51.188286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
23977 12:31:51.188828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
23979 12:31:51.239414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass
23981 12:31:51.239977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass>
23982 12:31:51.279807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
23983 12:31:51.280380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
23985 12:31:51.326841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
23986 12:31:51.327424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
23988 12:31:51.369693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
23989 12:31:51.370254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
23991 12:31:51.425076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass>
23992 12:31:51.425442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass
23994 12:31:51.476050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
23996 12:31:51.476460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
23997 12:31:51.529581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
23998 12:31:51.529986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
24000 12:31:51.580518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
24001 12:31:51.580950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
24003 12:31:51.633267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass
24005 12:31:51.633895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass>
24006 12:31:51.680922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
24007 12:31:51.681370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
24009 12:31:51.720378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
24010 12:31:51.720829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
24012 12:31:51.759809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
24013 12:31:51.760204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
24015 12:31:51.800291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass>
24016 12:31:51.800727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass
24018 12:31:51.843286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
24019 12:31:51.843725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
24021 12:31:51.894980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
24022 12:31:51.895385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
24024 12:31:51.941448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
24025 12:31:51.941919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
24027 12:31:51.985093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass
24029 12:31:51.985580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass>
24030 12:31:52.032506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
24031 12:31:52.032899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
24033 12:31:52.073815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
24035 12:31:52.074254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
24036 12:31:52.120482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
24037 12:31:52.120911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
24039 12:31:52.169252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass>
24040 12:31:52.169686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass
24042 12:31:52.211597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
24043 12:31:52.212021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
24045 12:31:52.266155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
24047 12:31:52.266655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
24048 12:31:52.312567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
24049 12:31:52.313052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
24051 12:31:52.365767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass
24053 12:31:52.366139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass>
24054 12:31:52.422980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
24056 12:31:52.423494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
24057 12:31:52.475804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
24058 12:31:52.476263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
24060 12:31:52.524249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
24061 12:31:52.524703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
24063 12:31:52.574869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass
24065 12:31:52.575340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass>
24066 12:31:52.623236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
24068 12:31:52.623719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
24069 12:31:52.682275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
24071 12:31:52.682826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
24072 12:31:52.741981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
24074 12:31:52.742739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
24075 12:31:52.788459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass
24077 12:31:52.789260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass>
24078 12:31:52.835139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
24079 12:31:52.835588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
24081 12:31:52.882791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
24082 12:31:52.883254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
24084 12:31:52.932323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
24085 12:31:52.932735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
24087 12:31:52.987294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass
24089 12:31:52.987714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass>
24090 12:31:53.028126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
24091 12:31:53.028561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
24093 12:31:53.077103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
24095 12:31:53.077808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
24096 12:31:53.128686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
24097 12:31:53.129142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
24099 12:31:53.180937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass
24101 12:31:53.181415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass>
24102 12:31:53.228035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
24103 12:31:53.228516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
24105 12:31:53.272513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
24106 12:31:53.272937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
24108 12:31:53.321601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
24109 12:31:53.322066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
24111 12:31:53.366159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass
24113 12:31:53.366559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass>
24114 12:31:53.420758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
24115 12:31:53.421199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
24117 12:31:53.474867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
24119 12:31:53.475248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
24120 12:31:53.522188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
24122 12:31:53.522709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
24123 12:31:53.569450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass>
24124 12:31:53.569920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass
24126 12:31:53.613621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
24127 12:31:53.614069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
24129 12:31:53.662838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
24130 12:31:53.663242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
24132 12:31:53.712880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
24133 12:31:53.713276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
24135 12:31:53.764001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass>
24136 12:31:53.764454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass
24138 12:31:53.808722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
24139 12:31:53.809161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
24141 12:31:53.849644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
24142 12:31:53.850077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
24144 12:31:53.902978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
24145 12:31:53.903413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
24147 12:31:53.956622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass>
24148 12:31:53.957125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass
24150 12:31:54.011176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
24151 12:31:54.011734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
24153 12:31:54.063879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
24155 12:31:54.064356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
24156 12:31:54.106889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
24157 12:31:54.107334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
24159 12:31:54.150355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass
24161 12:31:54.150838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass>
24162 12:31:54.203520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
24163 12:31:54.203958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
24165 12:31:54.264277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
24167 12:31:54.264719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
24168 12:31:54.323718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
24169 12:31:54.324147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
24171 12:31:54.383333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass>
24172 12:31:54.383755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass
24174 12:31:54.440996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
24175 12:31:54.441386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
24177 12:31:54.500576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
24179 12:31:54.501002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
24180 12:31:54.558928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
24181 12:31:54.559431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
24183 12:31:54.616330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass>
24184 12:31:54.616770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass
24186 12:31:54.674189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
24188 12:31:54.674674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
24189 12:31:54.733487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
24190 12:31:54.733944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
24192 12:31:54.792038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
24194 12:31:54.792460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
24195 12:31:54.851353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass>
24196 12:31:54.851783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass
24198 12:31:54.909149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
24200 12:31:54.909631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
24201 12:31:54.968154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
24202 12:31:54.968536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
24204 12:31:55.025033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
24205 12:31:55.025437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
24207 12:31:55.080401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass>
24208 12:31:55.080794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass
24210 12:31:55.140604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
24211 12:31:55.140998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
24213 12:31:55.183830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
24214 12:31:55.184279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
24216 12:31:55.233404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
24217 12:31:55.233965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
24219 12:31:55.283793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass
24221 12:31:55.284295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass>
24222 12:31:55.332124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
24223 12:31:55.332567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
24225 12:31:55.384564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
24226 12:31:55.385008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
24228 12:31:55.435218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
24230 12:31:55.435731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
24231 12:31:55.476671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass
24233 12:31:55.477333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass>
24234 12:31:55.520583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
24235 12:31:55.520979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
24237 12:31:55.573901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
24238 12:31:55.574379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
24240 12:31:55.620408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
24241 12:31:55.620781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
24243 12:31:55.669827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass
24245 12:31:55.670286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass>
24246 12:31:55.728627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
24247 12:31:55.729062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
24249 12:31:55.787028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
24250 12:31:55.787478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
24252 12:31:55.829444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
24253 12:31:55.829929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
24255 12:31:55.871856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass
24257 12:31:55.872346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass>
24258 12:31:55.923332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
24259 12:31:55.923753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
24261 12:31:55.971275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
24262 12:31:55.971794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
24264 12:31:56.015067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
24265 12:31:56.015484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
24267 12:31:56.060317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass>
24268 12:31:56.060696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass
24270 12:31:56.105731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
24271 12:31:56.106169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
24273 12:31:56.151851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
24274 12:31:56.152241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
24276 12:31:56.199005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
24277 12:31:56.199426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
24279 12:31:56.240556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass
24281 12:31:56.240983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass>
24282 12:31:56.287957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
24283 12:31:56.288377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
24285 12:31:56.335393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
24286 12:31:56.335851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
24288 12:31:56.385407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
24289 12:31:56.385849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
24291 12:31:56.428777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass>
24292 12:31:56.429194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass
24294 12:31:56.474575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
24296 12:31:56.475098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
24297 12:31:56.521327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
24299 12:31:56.521789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
24300 12:31:56.569786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
24301 12:31:56.570174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
24303 12:31:56.624006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass>
24304 12:31:56.624403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass
24306 12:31:56.672590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
24307 12:31:56.673003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
24309 12:31:56.718270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
24311 12:31:56.718755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
24312 12:31:56.756819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
24313 12:31:56.757244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
24315 12:31:56.801140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass>
24316 12:31:56.801574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass
24318 12:31:56.845528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
24319 12:31:56.845988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
24321 12:31:56.895237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
24322 12:31:56.895678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
24324 12:31:56.945639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
24326 12:31:56.946140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
24327 12:31:56.994010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass
24329 12:31:56.994494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass>
24330 12:31:57.041064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
24331 12:31:57.041475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
24333 12:31:57.096578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
24334 12:31:57.097013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
24336 12:31:57.155732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
24337 12:31:57.156135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
24339 12:31:57.210095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass
24341 12:31:57.210527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass>
24342 12:31:57.253639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
24343 12:31:57.254209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
24345 12:31:57.297132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
24346 12:31:57.297609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
24348 12:31:57.347917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
24349 12:31:57.348356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
24351 12:31:57.388552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass>
24352 12:31:57.388990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass
24354 12:31:57.435682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
24355 12:31:57.436174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
24357 12:31:57.481356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
24358 12:31:57.481745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
24360 12:31:57.526217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
24362 12:31:57.526620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
24363 12:31:57.571449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass
24365 12:31:57.571836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass>
24366 12:31:57.618433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
24368 12:31:57.618930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
24369 12:31:57.659404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
24370 12:31:57.659847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
24372 12:31:57.702718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
24373 12:31:57.703157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
24375 12:31:57.744303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass>
24376 12:31:57.744721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass
24378 12:31:57.792299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
24380 12:31:57.792790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
24381 12:31:57.835499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
24382 12:31:57.835914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
24384 12:31:57.873917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
24385 12:31:57.874385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
24387 12:31:57.919606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass
24389 12:31:57.920121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass>
24390 12:31:57.967753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
24391 12:31:57.968200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
24393 12:31:58.014762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
24394 12:31:58.015159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
24396 12:31:58.060327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
24398 12:31:58.061114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
24399 12:31:58.104326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass
24401 12:31:58.104779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass>
24402 12:31:58.152355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
24404 12:31:58.152795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
24405 12:31:58.198184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
24407 12:31:58.198646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
24408 12:31:58.241106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
24410 12:31:58.241730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
24411 12:31:58.287723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass
24413 12:31:58.288192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass>
24414 12:31:58.332043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
24415 12:31:58.332473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
24417 12:31:58.377234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
24418 12:31:58.377681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
24420 12:31:58.431496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
24421 12:31:58.431954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
24423 12:31:58.485318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass>
24424 12:31:58.485785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass
24426 12:31:58.543986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
24427 12:31:58.544418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
24429 12:31:58.591740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
24430 12:31:58.592180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
24432 12:31:58.640626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
24434 12:31:58.641254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
24435 12:31:58.691644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass>
24436 12:31:58.692076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass
24438 12:31:58.740057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
24439 12:31:58.740456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
24441 12:31:58.792497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
24442 12:31:58.792958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
24444 12:31:58.837084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
24445 12:31:58.837498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
24447 12:31:58.880969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass
24449 12:31:58.881456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass>
24450 12:31:58.923943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
24452 12:31:58.924442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
24453 12:31:58.965815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
24455 12:31:58.966314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
24456 12:31:59.013867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
24457 12:31:59.014322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
24459 12:31:59.065695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass>
24460 12:31:59.066143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass
24462 12:31:59.121908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
24463 12:31:59.125740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
24465 12:31:59.180181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
24466 12:31:59.180624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
24468 12:31:59.231597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
24469 12:31:59.232053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
24471 12:31:59.274837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass>
24472 12:31:59.275273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass
24474 12:31:59.315076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
24475 12:31:59.315517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
24477 12:31:59.355987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
24479 12:31:59.356762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
24480 12:31:59.396383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
24481 12:31:59.396896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
24483 12:31:59.443633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass>
24484 12:31:59.444071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass
24486 12:31:59.493547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
24487 12:31:59.493995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
24489 12:31:59.536790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
24490 12:31:59.537221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
24492 12:31:59.579316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
24493 12:31:59.579724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
24495 12:31:59.619134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass
24497 12:31:59.619607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass>
24498 12:31:59.661121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
24499 12:31:59.661553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
24501 12:31:59.707402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
24502 12:31:59.707819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
24504 12:31:59.758643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
24505 12:31:59.759101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
24507 12:31:59.804435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass>
24508 12:31:59.804825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass
24510 12:31:59.850249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
24512 12:31:59.850708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
24513 12:31:59.893965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
24515 12:31:59.894473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
24516 12:31:59.941038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
24517 12:31:59.941472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
24519 12:31:59.989454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass>
24520 12:31:59.989905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass
24522 12:32:00.035076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
24523 12:32:00.035534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
24525 12:32:00.083638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
24527 12:32:00.084148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
24528 12:32:00.127652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
24529 12:32:00.128201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
24531 12:32:00.169260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass>
24532 12:32:00.169696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass
24534 12:32:00.211621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
24535 12:32:00.212031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
24537 12:32:00.253297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
24538 12:32:00.253687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
24540 12:32:00.305374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
24541 12:32:00.305792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
24543 12:32:00.363175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass>
24544 12:32:00.363620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass
24546 12:32:00.405880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
24548 12:32:00.406325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
24549 12:32:00.449448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
24550 12:32:00.449853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
24552 12:32:00.498763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
24553 12:32:00.499170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
24555 12:32:00.548585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass>
24556 12:32:00.549025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass
24558 12:32:00.592670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
24559 12:32:00.593057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
24561 12:32:00.635663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
24563 12:32:00.636138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
24564 12:32:00.686244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
24566 12:32:00.686685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
24567 12:32:00.727123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass>
24568 12:32:00.727538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass
24570 12:32:00.771399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
24571 12:32:00.771835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
24573 12:32:00.813594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
24575 12:32:00.814091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
24576 12:32:00.890923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
24577 12:32:00.891372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
24579 12:32:00.951563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass>
24580 12:32:00.952100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass
24582 12:32:01.010898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
24583 12:32:01.011297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
24585 12:32:01.071296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
24587 12:32:01.072001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
24588 12:32:01.131819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
24589 12:32:01.132259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
24591 12:32:01.192251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass
24593 12:32:01.192727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass>
24594 12:32:01.253804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
24595 12:32:01.254250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
24597 12:32:01.315904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
24598 12:32:01.316358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
24600 12:32:01.378395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
24602 12:32:01.379182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
24603 12:32:01.441631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass>
24604 12:32:01.442082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass
24606 12:32:01.501462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
24607 12:32:01.501899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
24609 12:32:01.561621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
24610 12:32:01.562065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
24612 12:32:01.623231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
24613 12:32:01.623665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
24615 12:32:01.684140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass>
24616 12:32:01.684579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass
24618 12:32:01.743809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
24619 12:32:01.744268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
24621 12:32:01.787200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
24623 12:32:01.787673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
24624 12:32:01.840465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
24626 12:32:01.840910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
24627 12:32:01.891980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass>
24628 12:32:01.892369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass
24630 12:32:01.943829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
24631 12:32:01.944246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
24633 12:32:01.987276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
24634 12:32:01.987704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
24636 12:32:02.036153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
24637 12:32:02.036604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
24639 12:32:02.082194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass
24641 12:32:02.082838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass>
24642 12:32:02.127801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
24643 12:32:02.128240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
24645 12:32:02.180036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
24646 12:32:02.180425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
24648 12:32:02.233052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
24649 12:32:02.233492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
24651 12:32:02.288651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass
24653 12:32:02.289100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass>
24654 12:32:02.340108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
24655 12:32:02.340558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
24657 12:32:02.386265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
24659 12:32:02.386766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
24660 12:32:02.431036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
24661 12:32:02.431459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
24663 12:32:02.481641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass>
24664 12:32:02.482087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass
24666 12:32:02.527809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
24668 12:32:02.528350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
24669 12:32:02.578166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
24671 12:32:02.578686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
24672 12:32:02.629021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
24673 12:32:02.629480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
24675 12:32:02.672170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass
24677 12:32:02.672557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass>
24678 12:32:02.725624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
24679 12:32:02.726093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
24681 12:32:02.775491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
24682 12:32:02.775921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
24684 12:32:02.820106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
24685 12:32:02.820569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
24687 12:32:02.866867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass
24689 12:32:02.867358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass>
24690 12:32:02.918783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
24692 12:32:02.919263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
24693 12:32:02.973071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
24694 12:32:02.973496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
24696 12:32:03.022261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
24698 12:32:03.022814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
24699 12:32:03.075799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass
24701 12:32:03.076298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass>
24702 12:32:03.119259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
24703 12:32:03.119700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
24705 12:32:03.161225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
24706 12:32:03.161663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
24708 12:32:03.208531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
24710 12:32:03.209007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
24711 12:32:03.253549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass>
24712 12:32:03.253993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass
24714 12:32:03.296872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
24716 12:32:03.297352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
24717 12:32:03.342102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
24719 12:32:03.342579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
24720 12:32:03.386799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
24721 12:32:03.387228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
24723 12:32:03.433930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass
24725 12:32:03.434425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass>
24726 12:32:03.478270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
24728 12:32:03.478745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
24729 12:32:03.517505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
24730 12:32:03.517923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
24732 12:32:03.563829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
24733 12:32:03.564240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
24735 12:32:03.616725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass>
24736 12:32:03.617088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass
24738 12:32:03.669183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
24739 12:32:03.669595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
24741 12:32:03.713100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
24742 12:32:03.713537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
24744 12:32:03.755637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
24745 12:32:03.756036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
24747 12:32:03.803077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass>
24748 12:32:03.803493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass
24750 12:32:03.851651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
24751 12:32:03.852094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
24753 12:32:03.901297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
24754 12:32:03.901691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
24756 12:32:03.941354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
24758 12:32:03.941820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
24759 12:32:03.984445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass
24761 12:32:03.984905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass>
24762 12:32:04.029201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
24764 12:32:04.029927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
24765 12:32:04.076638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
24766 12:32:04.077060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
24768 12:32:04.120477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
24769 12:32:04.120914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
24771 12:32:04.172591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass>
24772 12:32:04.173021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass
24774 12:32:04.226046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
24776 12:32:04.226537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
24777 12:32:04.287187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
24779 12:32:04.287657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
24780 12:32:04.343382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
24781 12:32:04.343819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
24783 12:32:04.387544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass>
24784 12:32:04.387987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass
24786 12:32:04.443758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
24787 12:32:04.444201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
24789 12:32:04.500206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
24790 12:32:04.500647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
24792 12:32:04.560696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
24793 12:32:04.561095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
24795 12:32:04.620414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass>
24796 12:32:04.620875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass
24798 12:32:04.679190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
24799 12:32:04.679631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
24801 12:32:04.737569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
24802 12:32:04.738028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
24804 12:32:04.796475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
24806 12:32:04.796939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
24807 12:32:04.847699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass>
24808 12:32:04.848148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass
24810 12:32:04.898696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
24811 12:32:04.899110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
24813 12:32:04.952471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
24815 12:32:04.952949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
24816 12:32:04.996903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
24817 12:32:04.997338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
24819 12:32:05.041869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass
24821 12:32:05.042328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass>
24822 12:32:05.095132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
24824 12:32:05.095615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
24825 12:32:05.153520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
24826 12:32:05.153952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
24828 12:32:05.215229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
24829 12:32:05.215671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
24831 12:32:05.276088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass>
24832 12:32:05.276538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass
24834 12:32:05.333243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
24835 12:32:05.333675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
24837 12:32:05.386198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
24839 12:32:05.386676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
24840 12:32:05.440510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
24841 12:32:05.440936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
24843 12:32:05.489214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass
24845 12:32:05.489698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass>
24846 12:32:05.541011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
24847 12:32:05.541426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
24849 12:32:05.582182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
24851 12:32:05.582945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
24852 12:32:05.636259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
24853 12:32:05.636676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
24855 12:32:05.677352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass>
24856 12:32:05.677760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass
24858 12:32:05.731387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
24859 12:32:05.731812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
24861 12:32:05.777714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
24862 12:32:05.778162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
24864 12:32:05.822847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
24866 12:32:05.823433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
24867 12:32:05.877436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass>
24868 12:32:05.877852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass
24870 12:32:05.921266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
24871 12:32:05.921698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
24873 12:32:05.997680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
24874 12:32:05.998123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
24876 12:32:06.058444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
24878 12:32:06.058902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
24879 12:32:06.117044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass>
24880 12:32:06.117485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass
24882 12:32:06.177237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
24883 12:32:06.177663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
24885 12:32:06.237919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
24886 12:32:06.238309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
24888 12:32:06.297871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
24890 12:32:06.298358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
24891 12:32:06.348047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass>
24892 12:32:06.348475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass
24894 12:32:06.399522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
24896 12:32:06.399992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
24897 12:32:06.452436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
24898 12:32:06.452834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
24900 12:32:06.497573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
24901 12:32:06.498031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
24903 12:32:06.556893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass>
24904 12:32:06.557326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass
24906 12:32:06.616322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
24907 12:32:06.616763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
24909 12:32:06.661027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
24911 12:32:06.661493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
24912 12:32:06.710885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
24913 12:32:06.711330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
24915 12:32:06.755965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass>
24916 12:32:06.756406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass
24918 12:32:06.804073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
24919 12:32:06.804488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
24921 12:32:06.852577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
24922 12:32:06.853038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
24924 12:32:06.913852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
24925 12:32:06.914313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
24927 12:32:06.965299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass
24929 12:32:06.965827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass>
24930 12:32:07.018134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
24932 12:32:07.018644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
24933 12:32:07.068870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
24934 12:32:07.069304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
24936 12:32:07.114811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
24937 12:32:07.115228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
24939 12:32:07.165981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass
24941 12:32:07.166431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass>
24942 12:32:07.212098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
24943 12:32:07.212526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
24945 12:32:07.260512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
24946 12:32:07.261011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
24948 12:32:07.306954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
24949 12:32:07.307516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
24951 12:32:07.351007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass>
24952 12:32:07.351426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass
24954 12:32:07.402908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
24955 12:32:07.403470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
24957 12:32:07.448165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
24958 12:32:07.448596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
24960 12:32:07.499980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
24961 12:32:07.500356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
24963 12:32:07.557925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass
24965 12:32:07.558403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass>
24966 12:32:07.608771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
24967 12:32:07.609097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
24969 12:32:07.657782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
24970 12:32:07.658241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
24972 12:32:07.697083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
24973 12:32:07.697495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
24975 12:32:07.740286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass>
24976 12:32:07.740677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass
24978 12:32:07.787630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
24979 12:32:07.788045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
24981 12:32:07.840026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
24982 12:32:07.840435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
24984 12:32:07.887366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
24985 12:32:07.887805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
24987 12:32:07.925453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass>
24988 12:32:07.925895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass
24990 12:32:07.967446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
24991 12:32:07.967886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
24993 12:32:08.013572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
24994 12:32:08.013992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
24996 12:32:08.060943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
24997 12:32:08.061337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
24999 12:32:08.105510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass>
25000 12:32:08.105917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass
25002 12:32:08.145557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
25004 12:32:08.146028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
25005 12:32:08.187683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
25006 12:32:08.188101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
25008 12:32:08.232076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
25009 12:32:08.232486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
25011 12:32:08.272746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass>
25012 12:32:08.273148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass
25014 12:32:08.311828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
25015 12:32:08.312261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
25017 12:32:08.351918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
25018 12:32:08.352363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
25020 12:32:08.392066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
25022 12:32:08.392670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
25023 12:32:08.430068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass
25025 12:32:08.430681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass>
25026 12:32:08.468017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
25027 12:32:08.468560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
25029 12:32:08.507578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
25030 12:32:08.508026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
25032 12:32:08.561657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
25033 12:32:08.562088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
25035 12:32:08.611107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass
25037 12:32:08.611750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass>
25038 12:32:08.651587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
25039 12:32:08.652154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
25041 12:32:08.705023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
25043 12:32:08.705519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
25044 12:32:08.755735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
25045 12:32:08.756154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
25047 12:32:08.805121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass>
25048 12:32:08.805601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass
25050 12:32:08.857114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
25051 12:32:08.857551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
25053 12:32:08.909039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
25054 12:32:08.909467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
25056 12:32:08.949894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
25057 12:32:08.950293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
25059 12:32:08.988148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass>
25060 12:32:08.988586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass
25062 12:32:09.027318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
25063 12:32:09.027812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
25065 12:32:09.065719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
25066 12:32:09.066273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
25068 12:32:09.108023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
25069 12:32:09.108426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
25071 12:32:09.149225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass
25073 12:32:09.149714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass>
25074 12:32:09.196422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
25075 12:32:09.196839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
25077 12:32:09.241251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
25078 12:32:09.241718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
25080 12:32:09.288588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
25081 12:32:09.289030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
25083 12:32:09.334362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass
25085 12:32:09.334821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass>
25086 12:32:09.376870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
25087 12:32:09.377295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
25089 12:32:09.421862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
25091 12:32:09.422339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
25092 12:32:09.464786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
25094 12:32:09.465271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
25095 12:32:09.514801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass>
25096 12:32:09.515200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass
25098 12:32:09.564050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
25100 12:32:09.564690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
25101 12:32:09.605875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
25103 12:32:09.606354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
25104 12:32:09.649575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
25105 12:32:09.650015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
25107 12:32:09.702956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass
25109 12:32:09.703555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass>
25110 12:32:09.751834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
25111 12:32:09.752256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
25113 12:32:09.793690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
25114 12:32:09.794143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
25116 12:32:09.837933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
25118 12:32:09.838418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
25119 12:32:09.888749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass
25121 12:32:09.889263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass>
25122 12:32:09.940320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
25123 12:32:09.940722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
25125 12:32:10.001269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
25126 12:32:10.001681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
25128 12:32:10.061308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
25129 12:32:10.061685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
25131 12:32:10.123615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass>
25132 12:32:10.124054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass
25134 12:32:10.178486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
25136 12:32:10.178918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
25137 12:32:10.221883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
25138 12:32:10.222299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
25140 12:32:10.279104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
25141 12:32:10.279531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
25143 12:32:10.332429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass>
25144 12:32:10.332820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass
25146 12:32:10.384777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
25147 12:32:10.385218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
25149 12:32:10.437070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
25151 12:32:10.437561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
25152 12:32:10.487386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
25154 12:32:10.487878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
25155 12:32:10.537120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass>
25156 12:32:10.537522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass
25158 12:32:10.589275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
25159 12:32:10.589693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
25161 12:32:10.636149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
25162 12:32:10.636611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
25164 12:32:10.677745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
25165 12:32:10.678204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
25167 12:32:10.723996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass
25169 12:32:10.724486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass>
25170 12:32:10.781726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
25171 12:32:10.782171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
25173 12:32:10.828339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
25175 12:32:10.828829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
25176 12:32:10.867400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
25177 12:32:10.867809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
25179 12:32:10.913154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass>
25180 12:32:10.913602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass
25182 12:32:10.967740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
25183 12:32:10.968158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
25185 12:32:11.013353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
25186 12:32:11.013820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
25188 12:32:11.066232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
25190 12:32:11.070965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
25191 12:32:11.131908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass
25193 12:32:11.132378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass>
25194 12:32:11.172282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
25196 12:32:11.172753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
25197 12:32:11.213283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
25199 12:32:11.214059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
25200 12:32:11.261703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
25202 12:32:11.262194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
25203 12:32:11.315848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass>
25204 12:32:11.316309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass
25206 12:32:11.376186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
25207 12:32:11.376643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
25209 12:32:11.423590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
25210 12:32:11.424071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
25212 12:32:11.467887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
25214 12:32:11.468377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
25215 12:32:11.513597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass>
25216 12:32:11.514034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass
25218 12:32:11.573159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
25220 12:32:11.573940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
25221 12:32:11.631572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
25222 12:32:11.632014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
25224 12:32:11.680301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
25225 12:32:11.680731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
25227 12:32:11.724898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass
25229 12:32:11.725358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass>
25230 12:32:11.772646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
25231 12:32:11.773075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
25233 12:32:11.816985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
25234 12:32:11.817488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
25236 12:32:11.866818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
25238 12:32:11.867316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
25239 12:32:11.911333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass>
25240 12:32:11.911805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass
25242 12:32:11.961474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
25244 12:32:11.961935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
25245 12:32:12.006854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
25246 12:32:12.007310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
25248 12:32:12.049059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
25249 12:32:12.049442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
25251 12:32:12.096086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass
25253 12:32:12.096506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass>
25254 12:32:12.138908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
25255 12:32:12.139279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
25257 12:32:12.183796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
25258 12:32:12.184188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
25260 12:32:12.224176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
25261 12:32:12.224577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
25263 12:32:12.273364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass>
25264 12:32:12.273763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass
25266 12:32:12.313744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
25267 12:32:12.314209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
25269 12:32:12.355615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
25270 12:32:12.356089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
25272 12:32:12.397276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
25274 12:32:12.397918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
25275 12:32:12.436937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass>
25276 12:32:12.437339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass
25278 12:32:12.476736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
25280 12:32:12.477136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
25281 12:32:12.516156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
25282 12:32:12.516582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
25284 12:32:12.568060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
25285 12:32:12.568452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
25287 12:32:12.620725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass
25289 12:32:12.621151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass>
25290 12:32:12.660393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
25291 12:32:12.660766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
25293 12:32:12.704650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
25295 12:32:12.705069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
25296 12:32:12.756540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
25297 12:32:12.756951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
25299 12:32:12.797116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass
25301 12:32:12.797489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass>
25302 12:32:12.847945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
25303 12:32:12.848406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
25305 12:32:12.896713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
25306 12:32:12.897145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
25308 12:32:12.938957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
25309 12:32:12.939372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
25311 12:32:13.000538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass>
25312 12:32:13.000971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass
25314 12:32:13.063482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
25315 12:32:13.063911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
25317 12:32:13.128073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
25318 12:32:13.128575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
25320 12:32:13.187997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
25321 12:32:13.188437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
25323 12:32:13.248316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass>
25324 12:32:13.248704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass
25326 12:32:13.295140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
25327 12:32:13.295578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
25329 12:32:13.350760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
25330 12:32:13.351180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
25332 12:32:13.410158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
25333 12:32:13.410598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
25335 12:32:13.468869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass>
25336 12:32:13.469284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass
25338 12:32:13.504631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
25339 12:32:13.505068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
25341 12:32:13.546873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
25342 12:32:13.547297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
25344 12:32:13.590152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
25346 12:32:13.590632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
25347 12:32:13.636029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass>
25348 12:32:13.636448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass
25350 12:32:13.677374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
25351 12:32:13.677803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
25353 12:32:13.720974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
25354 12:32:13.721360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
25356 12:32:13.764389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
25357 12:32:13.764879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
25359 12:32:13.817275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass>
25360 12:32:13.817694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass
25362 12:32:13.877530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
25363 12:32:13.878028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
25365 12:32:13.919603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
25366 12:32:13.920132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
25368 12:32:13.959662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
25369 12:32:13.960214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
25371 12:32:14.003726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass
25373 12:32:14.004118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass>
25374 12:32:14.047392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
25375 12:32:14.047971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
25377 12:32:14.089352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
25378 12:32:14.089790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
25380 12:32:14.127358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
25381 12:32:14.127806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
25383 12:32:14.182961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass>
25384 12:32:14.183395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass
25386 12:32:14.241252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
25388 12:32:14.241741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
25389 12:32:14.301113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
25391 12:32:14.301545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
25392 12:32:14.360152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
25393 12:32:14.360592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
25395 12:32:14.408993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass>
25396 12:32:14.409431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass
25398 12:32:14.453452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
25399 12:32:14.453870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
25401 12:32:14.508714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
25402 12:32:14.509155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
25404 12:32:14.569556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
25405 12:32:14.569963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
25407 12:32:14.630375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass
25409 12:32:14.630810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass>
25410 12:32:14.678387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
25412 12:32:14.678832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
25413 12:32:14.721295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
25414 12:32:14.721699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
25416 12:32:14.768779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
25417 12:32:14.769182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
25419 12:32:14.812529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass>
25420 12:32:14.812962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass
25422 12:32:14.854124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
25424 12:32:14.854598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
25425 12:32:14.896744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
25426 12:32:14.897173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
25428 12:32:14.940370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
25429 12:32:14.940779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
25431 12:32:14.983517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass>
25432 12:32:14.983962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass
25434 12:32:15.035446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
25436 12:32:15.035924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
25437 12:32:15.076451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
25438 12:32:15.076900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
25440 12:32:15.120862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
25441 12:32:15.121314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
25443 12:32:15.170974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass
25445 12:32:15.171451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass>
25446 12:32:15.224812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
25447 12:32:15.225215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
25449 12:32:15.276980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
25450 12:32:15.278767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
25452 12:32:15.317843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
25453 12:32:15.318277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
25455 12:32:15.365016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass>
25456 12:32:15.365472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass
25458 12:32:15.411951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
25459 12:32:15.412412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
25461 12:32:15.465348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
25463 12:32:15.465848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
25464 12:32:15.507889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
25465 12:32:15.508288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
25467 12:32:15.560284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass
25469 12:32:15.560760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass>
25470 12:32:15.601725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
25471 12:32:15.602154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
25473 12:32:15.642037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
25474 12:32:15.642610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
25476 12:32:15.687056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
25477 12:32:15.687446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
25479 12:32:15.739363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass
25481 12:32:15.739818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass>
25482 12:32:15.794975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
25483 12:32:15.795362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
25485 12:32:15.836832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
25486 12:32:15.837265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
25488 12:32:15.879924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
25490 12:32:15.880412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
25491 12:32:15.920116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass>
25492 12:32:15.920502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass
25494 12:32:15.973131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
25495 12:32:15.973577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
25497 12:32:16.017342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
25498 12:32:16.017767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
25500 12:32:16.057201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
25501 12:32:16.057624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
25503 12:32:16.108239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass>
25504 12:32:16.108693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass
25506 12:32:16.152610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
25507 12:32:16.153040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
25509 12:32:16.212571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
25511 12:32:16.212986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
25512 12:32:16.272342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
25513 12:32:16.272769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
25515 12:32:16.330773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass>
25516 12:32:16.331216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass
25518 12:32:16.389363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
25520 12:32:16.389796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
25521 12:32:16.448292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
25522 12:32:16.448702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
25524 12:32:16.507712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
25525 12:32:16.508161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
25527 12:32:16.567487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass>
25528 12:32:16.568015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass
25530 12:32:16.607666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
25531 12:32:16.608068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
25533 12:32:16.643453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
25534 12:32:16.643884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
25536 12:32:16.689965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
25538 12:32:16.690439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
25539 12:32:16.740497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass>
25540 12:32:16.740924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass
25542 12:32:16.782169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
25544 12:32:16.782651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
25545 12:32:16.825586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
25546 12:32:16.826016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
25548 12:32:16.877301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
25549 12:32:16.877741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
25551 12:32:16.919361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass>
25552 12:32:16.919776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass
25554 12:32:16.959383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
25555 12:32:16.959877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
25557 12:32:17.003764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
25558 12:32:17.004208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
25560 12:32:17.047163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
25561 12:32:17.047590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
25563 12:32:17.090002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass
25565 12:32:17.090639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass>
25566 12:32:17.142505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
25568 12:32:17.143011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
25569 12:32:17.184478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
25570 12:32:17.184916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
25572 12:32:17.241690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
25573 12:32:17.242121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
25575 12:32:17.290800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass
25577 12:32:17.291246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass>
25578 12:32:17.332923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
25579 12:32:17.333376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
25581 12:32:17.380531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
25583 12:32:17.380998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
25584 12:32:17.428025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
25586 12:32:17.428501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
25587 12:32:17.472421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass>
25588 12:32:17.472855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass
25590 12:32:17.521127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
25591 12:32:17.521585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
25593 12:32:17.572574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
25594 12:32:17.573026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
25596 12:32:17.621778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
25597 12:32:17.622216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
25599 12:32:17.668304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass>
25600 12:32:17.668746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass
25602 12:32:17.719245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
25603 12:32:17.719682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
25605 12:32:17.771232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
25606 12:32:17.771667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
25608 12:32:17.826386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
25610 12:32:17.827119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
25611 12:32:17.876270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass>
25612 12:32:17.876691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass
25614 12:32:17.919806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
25615 12:32:17.920241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
25617 12:32:17.963628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
25618 12:32:17.964024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
25620 12:32:18.015153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
25621 12:32:18.015606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
25623 12:32:18.058255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass
25625 12:32:18.058756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass>
25626 12:32:18.115894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
25628 12:32:18.116367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
25629 12:32:18.164842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
25630 12:32:18.165274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
25632 12:32:18.209047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
25633 12:32:18.209484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
25635 12:32:18.270280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass
25637 12:32:18.270760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass>
25638 12:32:18.325016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
25640 12:32:18.325508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
25641 12:32:18.369593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
25643 12:32:18.370090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
25644 12:32:18.424520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
25645 12:32:18.424947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
25647 12:32:18.474068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass
25649 12:32:18.474548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass>
25650 12:32:18.518833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
25651 12:32:18.519280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
25653 12:32:18.571820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
25654 12:32:18.572269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
25656 12:32:18.622086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
25658 12:32:18.622537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
25659 12:32:18.663849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass>
25660 12:32:18.664220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass
25662 12:32:18.706945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
25663 12:32:18.707352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
25665 12:32:18.757626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
25666 12:32:18.758067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
25668 12:32:18.815113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
25670 12:32:18.815581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
25671 12:32:18.861472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass>
25672 12:32:18.861915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass
25674 12:32:18.908966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
25675 12:32:18.909358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
25677 12:32:18.968012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
25678 12:32:18.968457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
25680 12:32:19.011730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
25682 12:32:19.012217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
25683 12:32:19.055662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass>
25684 12:32:19.056099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass
25686 12:32:19.100351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
25687 12:32:19.100787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
25689 12:32:19.151639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
25690 12:32:19.152067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
25692 12:32:19.212223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
25693 12:32:19.212656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
25695 12:32:19.272065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass>
25696 12:32:19.272493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass
25698 12:32:19.333976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
25699 12:32:19.334376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
25701 12:32:19.397130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
25702 12:32:19.397608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
25704 12:32:19.457851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
25705 12:32:19.458259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
25707 12:32:19.508910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass>
25708 12:32:19.509356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass
25710 12:32:19.556998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
25711 12:32:19.557435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
25713 12:32:19.612881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
25715 12:32:19.613373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
25716 12:32:19.670076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
25718 12:32:19.670561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
25719 12:32:19.737042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass>
25720 12:32:19.737666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass
25722 12:32:19.802261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
25724 12:32:19.802773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
25725 12:32:19.853811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
25726 12:32:19.854247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
25728 12:32:19.899637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
25729 12:32:19.900090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
25731 12:32:19.951979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass>
25732 12:32:19.952443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass
25734 12:32:20.007119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
25735 12:32:20.007570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
25737 12:32:20.056241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
25739 12:32:20.056712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
25740 12:32:20.115545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
25741 12:32:20.115982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
25743 12:32:20.167796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass
25745 12:32:20.168264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass>
25746 12:32:20.219862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
25747 12:32:20.220303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
25749 12:32:20.276542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
25751 12:32:20.276975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
25752 12:32:20.335821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
25753 12:32:20.336273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
25755 12:32:20.393531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass
25757 12:32:20.394027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass>
25758 12:32:20.456223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
25760 12:32:20.456695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
25761 12:32:20.511121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
25762 12:32:20.511567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
25764 12:32:20.567943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
25765 12:32:20.568386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
25767 12:32:20.616687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass>
25768 12:32:20.617122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass
25770 12:32:20.666970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
25772 12:32:20.667437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
25773 12:32:20.721325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
25774 12:32:20.721766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
25776 12:32:20.779758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
25777 12:32:20.780194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
25779 12:32:20.829847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass
25781 12:32:20.830336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass>
25782 12:32:20.880200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
25784 12:32:20.880678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
25785 12:32:20.930115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
25787 12:32:20.930714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
25788 12:32:20.977942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
25789 12:32:20.978375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
25791 12:32:21.030412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass
25793 12:32:21.031049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass>
25794 12:32:21.089053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
25795 12:32:21.089490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
25797 12:32:21.131530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
25798 12:32:21.131971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
25800 12:32:21.175967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
25802 12:32:21.176444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
25803 12:32:21.220516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass>
25804 12:32:21.220928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass
25806 12:32:21.266265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
25808 12:32:21.266739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
25809 12:32:21.344147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
25810 12:32:21.344588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
25812 12:32:21.384295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
25813 12:32:21.384738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
25815 12:32:21.428443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass
25817 12:32:21.429236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass>
25818 12:32:21.476380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
25820 12:32:21.476858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
25821 12:32:21.519914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
25822 12:32:21.520335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
25824 12:32:21.561741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
25826 12:32:21.562222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
25827 12:32:21.601295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass>
25828 12:32:21.601690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass
25830 12:32:21.637860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
25831 12:32:21.638293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
25833 12:32:21.680313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
25834 12:32:21.680807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
25836 12:32:21.725504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
25837 12:32:21.725955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
25839 12:32:21.767999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass>
25840 12:32:21.768392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass
25842 12:32:21.824080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
25843 12:32:21.824488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
25845 12:32:21.873172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
25846 12:32:21.873605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
25848 12:32:21.910501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
25849 12:32:21.910927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
25851 12:32:21.952023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass>
25852 12:32:21.952446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass
25854 12:32:22.005005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
25855 12:32:22.005549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
25857 12:32:22.049434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
25858 12:32:22.049940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
25860 12:32:22.095104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
25862 12:32:22.095524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
25863 12:32:22.137620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass>
25864 12:32:22.138237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass
25866 12:32:22.184175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
25867 12:32:22.184615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
25869 12:32:22.232203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
25871 12:32:22.232746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
25872 12:32:22.277305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
25873 12:32:22.277739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
25875 12:32:22.320151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass
25877 12:32:22.320765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass>
25878 12:32:22.368387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
25879 12:32:22.368821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
25881 12:32:22.418672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
25882 12:32:22.419115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
25884 12:32:22.454929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
25885 12:32:22.455340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
25887 12:32:22.499057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass>
25888 12:32:22.499465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass
25890 12:32:22.548972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
25891 12:32:22.549406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
25893 12:32:22.588917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
25894 12:32:22.589579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
25896 12:32:22.637400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
25897 12:32:22.637823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
25899 12:32:22.688739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass
25901 12:32:22.689177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass>
25902 12:32:22.740479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
25903 12:32:22.740872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
25905 12:32:22.788496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
25906 12:32:22.788954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
25908 12:32:22.829802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
25910 12:32:22.830223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
25911 12:32:22.871104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass
25913 12:32:22.871615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass>
25914 12:32:22.910046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
25916 12:32:22.910513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
25917 12:32:22.957983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
25919 12:32:22.958456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
25920 12:32:23.004272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
25921 12:32:23.004704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
25923 12:32:23.053819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass>
25924 12:32:23.054265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass
25926 12:32:23.113391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
25927 12:32:23.113816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
25929 12:32:23.170339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
25931 12:32:23.170798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
25932 12:32:23.217450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
25933 12:32:23.217931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
25935 12:32:23.266778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass>
25936 12:32:23.267218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass
25938 12:32:23.313232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
25939 12:32:23.313633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
25941 12:32:23.367302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
25942 12:32:23.367723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
25944 12:32:23.419009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
25945 12:32:23.419451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
25947 12:32:23.465084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass>
25948 12:32:23.465527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass
25950 12:32:23.516625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
25951 12:32:23.517021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
25953 12:32:23.563866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
25954 12:32:23.564424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
25956 12:32:23.619042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
25957 12:32:23.619479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
25959 12:32:23.666817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass>
25960 12:32:23.667272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass
25962 12:32:23.717107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
25964 12:32:23.717531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
25965 12:32:23.764142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
25966 12:32:23.764545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
25968 12:32:23.810093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
25970 12:32:23.810586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
25971 12:32:23.867759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass>
25972 12:32:23.868199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass
25974 12:32:23.913806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
25975 12:32:23.914195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
25977 12:32:23.953039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
25979 12:32:23.953463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
25980 12:32:23.995639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
25982 12:32:23.996308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
25983 12:32:24.036361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass>
25984 12:32:24.036773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass
25986 12:32:24.083924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
25987 12:32:24.084359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
25989 12:32:24.131899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
25991 12:32:24.132402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
25992 12:32:24.179847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
25993 12:32:24.180290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
25995 12:32:24.225687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass>
25996 12:32:24.226108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass
25998 12:32:24.264024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
25999 12:32:24.264456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
26001 12:32:24.307064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
26002 12:32:24.307493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
26004 12:32:24.350988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
26005 12:32:24.351427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
26007 12:32:24.396602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass>
26008 12:32:24.397052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass
26010 12:32:24.448884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
26011 12:32:24.449349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
26013 12:32:24.496535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
26014 12:32:24.496930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
26016 12:32:24.539814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
26018 12:32:24.540292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
26019 12:32:24.587252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass>
26020 12:32:24.587725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass
26022 12:32:24.636308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
26023 12:32:24.636761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
26025 12:32:24.680557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
26027 12:32:24.681036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
26028 12:32:24.728667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
26029 12:32:24.729103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
26031 12:32:24.771325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass
26033 12:32:24.771798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass>
26034 12:32:24.809271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
26035 12:32:24.809693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
26037 12:32:24.851393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
26038 12:32:24.851806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
26040 12:32:24.896915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
26041 12:32:24.897349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
26043 12:32:24.951888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass
26045 12:32:24.952384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass>
26046 12:32:24.994129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
26048 12:32:24.994607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
26049 12:32:25.032808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
26050 12:32:25.033245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
26052 12:32:25.070190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
26054 12:32:25.070672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
26055 12:32:25.121089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass>
26056 12:32:25.121527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass
26058 12:32:25.175749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
26059 12:32:25.176177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
26061 12:32:25.228563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
26062 12:32:25.228984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
26064 12:32:25.271560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
26065 12:32:25.272138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
26067 12:32:25.315837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass>
26068 12:32:25.316259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass
26070 12:32:25.363443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
26071 12:32:25.363882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
26073 12:32:25.417294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
26075 12:32:25.417712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
26076 12:32:25.459421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
26077 12:32:25.459865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
26079 12:32:25.506938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass
26081 12:32:25.507427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass>
26082 12:32:25.547755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
26083 12:32:25.548169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
26085 12:32:25.595971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
26086 12:32:25.596474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
26088 12:32:25.643445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
26089 12:32:25.643874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
26091 12:32:25.692759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass>
26092 12:32:25.693199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass
26094 12:32:25.731091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
26095 12:32:25.731491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
26097 12:32:25.769110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
26098 12:32:25.769549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
26100 12:32:25.807356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
26101 12:32:25.807912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
26103 12:32:25.851857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass
26105 12:32:25.852264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass>
26106 12:32:25.893072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
26108 12:32:25.893551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
26109 12:32:25.944237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
26110 12:32:25.944675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
26112 12:32:25.992186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
26113 12:32:25.992661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
26115 12:32:26.038175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass
26117 12:32:26.038840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass>
26118 12:32:26.077711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
26119 12:32:26.078262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
26121 12:32:26.125426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
26123 12:32:26.125907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
26124 12:32:26.169039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
26125 12:32:26.169483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
26127 12:32:26.213792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass
26129 12:32:26.214276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass>
26130 12:32:26.259783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
26131 12:32:26.260248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
26133 12:32:26.307145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
26135 12:32:26.307625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
26136 12:32:26.350276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
26138 12:32:26.350753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
26139 12:32:26.395865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass>
26140 12:32:26.396320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass
26142 12:32:26.454911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
26144 12:32:26.455398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
26145 12:32:26.500966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
26146 12:32:26.501400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
26148 12:32:26.548371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
26149 12:32:26.548765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
26151 12:32:26.596111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass>
26152 12:32:26.596686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass
26154 12:32:26.647617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
26155 12:32:26.648059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
26157 12:32:26.695171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
26159 12:32:26.695646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
26160 12:32:26.739744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
26161 12:32:26.740163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
26163 12:32:26.784474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass>
26164 12:32:26.784958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass
26166 12:32:26.831186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
26167 12:32:26.831637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
26169 12:32:26.879589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
26170 12:32:26.880041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
26172 12:32:26.927460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
26173 12:32:26.927907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
26175 12:32:26.974093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass
26177 12:32:26.974607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass>
26178 12:32:27.013023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
26179 12:32:27.013437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
26181 12:32:27.057323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
26182 12:32:27.057738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
26184 12:32:27.107714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
26185 12:32:27.108144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
26187 12:32:27.153570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass>
26188 12:32:27.154046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass
26190 12:32:27.198836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
26191 12:32:27.199264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
26193 12:32:27.248187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
26194 12:32:27.248753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
26196 12:32:27.289618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
26197 12:32:27.290061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
26199 12:32:27.327641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass>
26200 12:32:27.328083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass
26202 12:32:27.375670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
26203 12:32:27.376121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
26205 12:32:27.419277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
26206 12:32:27.419672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
26208 12:32:27.458302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
26210 12:32:27.458762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
26211 12:32:27.507391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass
26213 12:32:27.507877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass>
26214 12:32:27.563420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
26215 12:32:27.563859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
26217 12:32:27.615781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
26218 12:32:27.616222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
26220 12:32:27.668120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
26222 12:32:27.668534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
26223 12:32:27.719803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass>
26224 12:32:27.720319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass
26226 12:32:27.763668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
26227 12:32:27.764088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
26229 12:32:27.809419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
26230 12:32:27.809866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
26232 12:32:27.850241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
26234 12:32:27.850712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
26235 12:32:27.896806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass
26237 12:32:27.897261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass>
26238 12:32:27.943480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
26239 12:32:27.943905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
26241 12:32:27.990742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
26242 12:32:27.991181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
26244 12:32:28.032721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
26245 12:32:28.033148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
26247 12:32:28.079463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass>
26248 12:32:28.079893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass
26250 12:32:28.133551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
26252 12:32:28.134058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
26253 12:32:28.180765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
26255 12:32:28.181233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
26256 12:32:28.225180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
26257 12:32:28.225631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
26259 12:32:28.268660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass
26261 12:32:28.269122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass>
26262 12:32:28.313453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
26264 12:32:28.313930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
26265 12:32:28.355398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
26266 12:32:28.355809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
26268 12:32:28.404134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
26269 12:32:28.404677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
26271 12:32:28.449733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass>
26272 12:32:28.450220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass
26274 12:32:28.501310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
26275 12:32:28.501763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
26277 12:32:28.547531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
26278 12:32:28.548066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
26280 12:32:28.595733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
26281 12:32:28.596303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
26283 12:32:28.640547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass
26285 12:32:28.641315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass>
26286 12:32:28.690920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
26287 12:32:28.691354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
26289 12:32:28.742947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
26290 12:32:28.743366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
26292 12:32:28.784459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
26293 12:32:28.784892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
26295 12:32:28.824178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass
26297 12:32:28.824651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass>
26298 12:32:28.867162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
26300 12:32:28.867656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
26301 12:32:28.912682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
26302 12:32:28.913091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
26304 12:32:28.955879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
26305 12:32:28.956282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
26307 12:32:29.015403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass>
26308 12:32:29.015830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass
26310 12:32:29.071976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
26311 12:32:29.072422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
26313 12:32:29.129342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
26314 12:32:29.129787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
26316 12:32:29.186421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
26318 12:32:29.186923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
26319 12:32:29.244736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass
26321 12:32:29.245213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass>
26322 12:32:29.302223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
26324 12:32:29.302687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
26325 12:32:29.359590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
26326 12:32:29.360033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
26328 12:32:29.417634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
26329 12:32:29.418169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
26331 12:32:29.479267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass>
26332 12:32:29.479712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass
26334 12:32:29.537016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
26335 12:32:29.537404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
26337 12:32:29.593891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
26338 12:32:29.594276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
26340 12:32:29.651887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
26341 12:32:29.652257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
26343 12:32:29.700125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass>
26344 12:32:29.700566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass
26346 12:32:29.741241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
26347 12:32:29.741681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
26349 12:32:29.783147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
26351 12:32:29.783612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
26352 12:32:29.839673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
26353 12:32:29.840119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
26355 12:32:29.899587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass>
26356 12:32:29.900019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass
26358 12:32:29.956570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
26359 12:32:29.956935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
26361 12:32:29.997736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
26362 12:32:29.998199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
26364 12:32:30.038133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
26366 12:32:30.038605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
26367 12:32:30.084180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass>
26368 12:32:30.084609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass
26370 12:32:30.135236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
26371 12:32:30.135696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
26373 12:32:30.176107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
26374 12:32:30.176554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
26376 12:32:30.225288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
26377 12:32:30.225665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
26379 12:32:30.268136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass>
26380 12:32:30.268566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass
26382 12:32:30.309112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
26383 12:32:30.309503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
26385 12:32:30.358950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
26386 12:32:30.359350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
26388 12:32:30.407184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
26390 12:32:30.407663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
26391 12:32:30.451937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass
26393 12:32:30.452391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass>
26394 12:32:30.496213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
26395 12:32:30.496723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
26397 12:32:30.539490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
26398 12:32:30.539920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
26400 12:32:30.577780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
26401 12:32:30.578204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
26403 12:32:30.616570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass>
26404 12:32:30.616957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass
26406 12:32:30.656484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
26407 12:32:30.656960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
26409 12:32:30.699093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
26410 12:32:30.699576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
26412 12:32:30.739806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
26413 12:32:30.740339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
26415 12:32:30.780102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass>
26416 12:32:30.780655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass
26418 12:32:30.821987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
26419 12:32:30.822385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
26421 12:32:30.863103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
26422 12:32:30.863498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
26424 12:32:30.901096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
26425 12:32:30.901483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
26427 12:32:30.941331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass>
26428 12:32:30.941832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass
26430 12:32:30.981225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
26431 12:32:30.981609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
26433 12:32:31.019889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
26434 12:32:31.020316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
26436 12:32:31.061214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
26437 12:32:31.061782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
26439 12:32:31.104835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass>
26440 12:32:31.105342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass
26442 12:32:31.153379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
26443 12:32:31.153958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
26445 12:32:31.207384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
26446 12:32:31.207827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
26448 12:32:31.244795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
26449 12:32:31.245202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
26451 12:32:31.283253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass
26453 12:32:31.283695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass>
26454 12:32:31.323091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
26455 12:32:31.323515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
26457 12:32:31.364454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
26459 12:32:31.364845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
26460 12:32:31.405406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
26461 12:32:31.405791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
26463 12:32:31.449307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass
26465 12:32:31.449716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass>
26466 12:32:31.491745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
26467 12:32:31.492162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
26469 12:32:31.535924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
26470 12:32:31.536374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
26472 12:32:31.608220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
26473 12:32:31.608625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
26475 12:32:31.662181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass
26477 12:32:31.662592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass>
26478 12:32:31.709242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
26479 12:32:31.709691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
26481 12:32:31.751939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
26482 12:32:31.752367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
26484 12:32:31.804028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
26486 12:32:31.804418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
26487 12:32:31.843311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass>
26488 12:32:31.843745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass
26490 12:32:31.887491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
26492 12:32:31.887975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
26493 12:32:31.935529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
26494 12:32:31.935982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
26496 12:32:31.979489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
26498 12:32:31.980229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
26499 12:32:32.027820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass>
26500 12:32:32.028263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass
26502 12:32:32.075929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
26503 12:32:32.076386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
26505 12:32:32.121164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
26506 12:32:32.121608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
26508 12:32:32.175097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
26509 12:32:32.175597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
26511 12:32:32.228774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass>
26512 12:32:32.229224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass
26514 12:32:32.276811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
26516 12:32:32.277374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
26517 12:32:32.324492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
26518 12:32:32.324980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
26520 12:32:32.369367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
26521 12:32:32.369786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
26523 12:32:32.421930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass>
26524 12:32:32.422322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass
26526 12:32:32.468650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
26527 12:32:32.469948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
26529 12:32:32.520977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
26530 12:32:32.521414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
26532 12:32:32.569312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
26533 12:32:32.569744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
26535 12:32:32.623504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass>
26536 12:32:32.623987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass
26538 12:32:32.676140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
26539 12:32:32.676584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
26541 12:32:32.727614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
26543 12:32:32.728055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
26544 12:32:32.781594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
26545 12:32:32.782037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
26547 12:32:32.835840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass>
26548 12:32:32.836270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass
26550 12:32:32.886378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
26552 12:32:32.886829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
26553 12:32:32.945085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
26554 12:32:32.945675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
26556 12:32:33.003998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
26557 12:32:33.004440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
26559 12:32:33.061797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass>
26560 12:32:33.062259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass
26562 12:32:33.121204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
26564 12:32:33.121673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
26565 12:32:33.181536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
26566 12:32:33.182008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
26568 12:32:33.241778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
26569 12:32:33.242189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
26571 12:32:33.303885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass>
26572 12:32:33.304334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass
26574 12:32:33.363373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
26575 12:32:33.363807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
26577 12:32:33.421802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
26578 12:32:33.422203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
26580 12:32:33.481142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
26581 12:32:33.481571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
26583 12:32:33.540200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass>
26584 12:32:33.540586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass
26586 12:32:33.596425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
26588 12:32:33.596817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
26589 12:32:33.656409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
26590 12:32:33.656844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
26592 12:32:33.700845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
26593 12:32:33.701265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
26595 12:32:33.751264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass>
26596 12:32:33.751663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass
26598 12:32:33.804775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
26599 12:32:33.805207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
26601 12:32:33.861350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
26602 12:32:33.861858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
26604 12:32:33.916589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
26605 12:32:33.917005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
26607 12:32:33.968974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass
26609 12:32:33.969444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass>
26610 12:32:34.008576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
26611 12:32:34.009003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
26613 12:32:34.050170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
26615 12:32:34.050650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
26616 12:32:34.093037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
26617 12:32:34.093468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
26619 12:32:34.133780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass>
26620 12:32:34.134208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass
26622 12:32:34.177991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
26624 12:32:34.178596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
26625 12:32:34.221535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
26626 12:32:34.221991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
26628 12:32:34.264361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
26630 12:32:34.264808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
26631 12:32:34.307938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass>
26632 12:32:34.308378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass
26634 12:32:34.351742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
26636 12:32:34.352211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
26637 12:32:34.396594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
26639 12:32:34.397073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
26640 12:32:34.443487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
26641 12:32:34.444116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
26643 12:32:34.487743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass>
26644 12:32:34.488142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass
26646 12:32:34.539869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
26647 12:32:34.540270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
26649 12:32:34.591392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
26650 12:32:34.591826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
26652 12:32:34.634030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
26654 12:32:34.634418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
26655 12:32:34.679933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass
26657 12:32:34.680328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass>
26658 12:32:34.732162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
26659 12:32:34.732601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
26661 12:32:34.791253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
26662 12:32:34.791684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
26664 12:32:34.834256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
26666 12:32:34.834956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
26667 12:32:34.877055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass
26669 12:32:34.877477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass>
26670 12:32:34.926337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
26672 12:32:34.926762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
26673 12:32:34.979277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
26674 12:32:34.979677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
26676 12:32:35.025739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
26678 12:32:35.026241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
26679 12:32:35.075523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass>
26680 12:32:35.075961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass
26682 12:32:35.117356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
26683 12:32:35.117754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
26685 12:32:35.169339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
26686 12:32:35.169735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
26688 12:32:35.223356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
26689 12:32:35.223801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
26691 12:32:35.276382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass>
26692 12:32:35.276839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass
26694 12:32:35.327773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
26695 12:32:35.328174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
26697 12:32:35.383356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
26698 12:32:35.383749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
26700 12:32:35.431053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
26701 12:32:35.431516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
26703 12:32:35.485966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass
26705 12:32:35.486456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass>
26706 12:32:35.531692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
26707 12:32:35.532126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
26709 12:32:35.583712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
26711 12:32:35.584162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
26712 12:32:35.632956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
26713 12:32:35.633384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
26715 12:32:35.685104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass>
26716 12:32:35.685559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass
26718 12:32:35.737526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
26720 12:32:35.737937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
26721 12:32:35.786299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
26723 12:32:35.786704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
26724 12:32:35.835506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
26725 12:32:35.835881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
26727 12:32:35.884137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass>
26728 12:32:35.884595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass
26730 12:32:35.935355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
26731 12:32:35.935778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
26733 12:32:35.989825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
26734 12:32:35.990251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
26736 12:32:36.049345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
26738 12:32:36.050103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
26739 12:32:36.109081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass>
26740 12:32:36.109510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass
26742 12:32:36.169080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
26743 12:32:36.169657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
26745 12:32:36.229349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
26746 12:32:36.229783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
26748 12:32:36.288505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
26749 12:32:36.288940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
26751 12:32:36.348050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass>
26752 12:32:36.348506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass
26754 12:32:36.407709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
26755 12:32:36.408249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
26757 12:32:36.467581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
26758 12:32:36.467984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
26760 12:32:36.525575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
26761 12:32:36.526037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
26763 12:32:36.570954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass>
26764 12:32:36.571388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass
26766 12:32:36.611354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
26768 12:32:36.612127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
26769 12:32:36.652307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
26771 12:32:36.652889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
26772 12:32:36.717856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
26773 12:32:36.718286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
26775 12:32:36.761251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass
26777 12:32:36.761731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass>
26778 12:32:36.801904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
26779 12:32:36.802341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
26781 12:32:36.844524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
26782 12:32:36.844959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
26784 12:32:36.885273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
26785 12:32:36.885686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
26787 12:32:36.928017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass>
26788 12:32:36.928445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass
26790 12:32:36.985142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
26791 12:32:36.985573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
26793 12:32:37.028460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
26794 12:32:37.028924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
26796 12:32:37.068629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
26798 12:32:37.069114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
26799 12:32:37.110119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass
26801 12:32:37.110552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass>
26802 12:32:37.148486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
26804 12:32:37.149199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
26805 12:32:37.192946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
26806 12:32:37.193352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
26808 12:32:37.244252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
26810 12:32:37.244686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
26811 12:32:37.295350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass>
26812 12:32:37.295776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass
26814 12:32:37.348793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
26816 12:32:37.349237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
26817 12:32:37.399752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
26818 12:32:37.400179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
26820 12:32:37.443323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
26822 12:32:37.443772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
26823 12:32:37.481535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass
26825 12:32:37.482034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass>
26826 12:32:37.523164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
26827 12:32:37.523588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
26829 12:32:37.565194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
26830 12:32:37.565631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
26832 12:32:37.609800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
26833 12:32:37.610256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
26835 12:32:37.653710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass>
26836 12:32:37.654115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass
26838 12:32:37.703384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
26839 12:32:37.703827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
26841 12:32:37.751771 <47>[ 309.373445] systemd-journald[105]: Sent WATCHDOG=1 notification.
26842 12:32:37.768219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
26843 12:32:37.768648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
26845 12:32:37.827182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
26847 12:32:37.827656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
26848 12:32:37.884855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass
26850 12:32:37.885512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass>
26851 12:32:37.943449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
26852 12:32:37.943881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
26854 12:32:38.000911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
26855 12:32:38.001349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
26857 12:32:38.059415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
26859 12:32:38.059898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
26860 12:32:38.119207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass>
26861 12:32:38.119655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass
26863 12:32:38.176824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
26864 12:32:38.177224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
26866 12:32:38.236636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
26868 12:32:38.237037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
26869 12:32:38.295340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
26870 12:32:38.295750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
26872 12:32:38.352483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass>
26873 12:32:38.352939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass
26875 12:32:38.409456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
26876 12:32:38.409920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
26878 12:32:38.468310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
26879 12:32:38.468745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
26881 12:32:38.520444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
26882 12:32:38.520965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
26884 12:32:38.560414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass>
26885 12:32:38.560848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass
26887 12:32:38.601788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
26888 12:32:38.602217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
26890 12:32:38.647025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
26891 12:32:38.647458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
26893 12:32:38.700255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
26895 12:32:38.700910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
26896 12:32:38.748843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass>
26897 12:32:38.749325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass
26899 12:32:38.807786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
26900 12:32:38.808238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
26902 12:32:38.849541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
26904 12:32:38.850026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
26905 12:32:38.891627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
26906 12:32:38.892072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
26908 12:32:38.935497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass>
26909 12:32:38.935930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass
26911 12:32:38.988317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
26913 12:32:38.988864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
26914 12:32:39.031013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
26915 12:32:39.031453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
26917 12:32:39.071396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
26918 12:32:39.071799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
26920 12:32:39.110176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass
26922 12:32:39.110654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass>
26923 12:32:39.149711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
26924 12:32:39.150131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
26926 12:32:39.194757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
26927 12:32:39.195159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
26929 12:32:39.236677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
26930 12:32:39.237115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
26932 12:32:39.280014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass>
26933 12:32:39.280409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass
26935 12:32:39.333378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
26937 12:32:39.333884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
26938 12:32:39.384730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
26939 12:32:39.385134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
26941 12:32:39.430245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
26943 12:32:39.430716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
26944 12:32:39.488158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass
26946 12:32:39.488621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass>
26947 12:32:39.547157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
26948 12:32:39.547539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
26950 12:32:39.604841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
26951 12:32:39.605315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
26953 12:32:39.661332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
26954 12:32:39.661921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
26956 12:32:39.717117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass>
26957 12:32:39.717595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass
26959 12:32:39.759023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
26961 12:32:39.759360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
26962 12:32:39.795873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
26963 12:32:39.796289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
26965 12:32:39.832965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
26967 12:32:39.833427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
26968 12:32:39.877726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass>
26969 12:32:39.878158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass
26971 12:32:39.922878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
26972 12:32:39.923330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
26974 12:32:39.980646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
26975 12:32:39.981091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
26977 12:32:40.026935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
26978 12:32:40.027357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
26980 12:32:40.075491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass
26982 12:32:40.076162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass>
26983 12:32:40.124081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
26985 12:32:40.124548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
26986 12:32:40.164449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
26987 12:32:40.164879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
26989 12:32:40.212631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
26991 12:32:40.213107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
26992 12:32:40.265378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass>
26993 12:32:40.265886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass
26995 12:32:40.320169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
26997 12:32:40.320909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
26998 12:32:40.373253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
26999 12:32:40.373738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
27001 12:32:40.423640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
27002 12:32:40.424100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
27004 12:32:40.472497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass>
27005 12:32:40.472936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass
27007 12:32:40.519477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
27009 12:32:40.519925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
27010 12:32:40.568428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
27011 12:32:40.568800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
27013 12:32:40.610202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
27015 12:32:40.610676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
27016 12:32:40.654936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass>
27017 12:32:40.655424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass
27019 12:32:40.703005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
27020 12:32:40.703459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
27022 12:32:40.756508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
27023 12:32:40.756956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
27025 12:32:40.816002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
27026 12:32:40.816374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
27028 12:32:40.875258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass>
27029 12:32:40.875697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass
27031 12:32:40.932063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
27032 12:32:40.932526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
27034 12:32:40.979476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
27035 12:32:40.979915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
27037 12:32:41.027832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
27038 12:32:41.028312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
27040 12:32:41.064327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass>
27041 12:32:41.064756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass
27043 12:32:41.103520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
27044 12:32:41.103952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
27046 12:32:41.147170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
27047 12:32:41.147613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
27049 12:32:41.188857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
27051 12:32:41.189318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
27052 12:32:41.230045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass
27054 12:32:41.230570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass>
27055 12:32:41.279376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
27056 12:32:41.279762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
27058 12:32:41.329080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
27059 12:32:41.329507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
27061 12:32:41.383509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
27063 12:32:41.383987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
27064 12:32:41.442216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass
27066 12:32:41.442734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass>
27067 12:32:41.494004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
27068 12:32:41.494449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
27070 12:32:41.543727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
27071 12:32:41.544161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
27073 12:32:41.583346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
27074 12:32:41.583765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
27076 12:32:41.624684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass
27078 12:32:41.625146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass>
27079 12:32:41.664854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
27081 12:32:41.665473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
27082 12:32:41.704664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
27083 12:32:41.705098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
27085 12:32:41.745921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
27086 12:32:41.746363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
27088 12:32:41.832256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass
27090 12:32:41.832728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass>
27091 12:32:41.889763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
27092 12:32:41.890242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
27094 12:32:41.949041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
27096 12:32:41.949494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
27097 12:32:42.007421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
27098 12:32:42.007824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
27100 12:32:42.064889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass>
27101 12:32:42.065467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass
27103 12:32:42.123636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
27105 12:32:42.124383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
27106 12:32:42.181374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
27108 12:32:42.181992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
27109 12:32:42.240617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
27110 12:32:42.241045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
27112 12:32:42.299358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass>
27113 12:32:42.299826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass
27115 12:32:42.357262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
27116 12:32:42.357716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
27118 12:32:42.416315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
27119 12:32:42.416792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
27121 12:32:42.470842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
27122 12:32:42.471295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
27124 12:32:42.517375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass
27126 12:32:42.518042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass>
27127 12:32:42.569731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
27128 12:32:42.570191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
27130 12:32:42.614933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
27131 12:32:42.615362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
27133 12:32:42.661012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
27134 12:32:42.661474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
27136 12:32:42.704988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass>
27137 12:32:42.705427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass
27139 12:32:42.751344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
27140 12:32:42.751793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
27142 12:32:42.804316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
27143 12:32:42.804748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
27145 12:32:42.859408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
27146 12:32:42.859815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
27148 12:32:42.914036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass>
27149 12:32:42.914475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass
27151 12:32:42.953814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
27153 12:32:42.954297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
27154 12:32:42.993333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
27156 12:32:42.993809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
27157 12:32:43.053130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
27158 12:32:43.053597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
27160 12:32:43.113729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass>
27161 12:32:43.114138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass
27163 12:32:43.176755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
27164 12:32:43.177201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
27166 12:32:43.233719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
27167 12:32:43.234157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
27169 12:32:43.292340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
27170 12:32:43.292745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
27172 12:32:43.353128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass
27174 12:32:43.353592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass>
27175 12:32:43.412656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
27176 12:32:43.413086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
27178 12:32:43.467617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
27180 12:32:43.468103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
27181 12:32:43.510172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
27183 12:32:43.510654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
27184 12:32:43.560789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass>
27185 12:32:43.561181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass
27187 12:32:43.606587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
27188 12:32:43.607040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
27190 12:32:43.645887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
27191 12:32:43.646452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
27193 12:32:43.702822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
27195 12:32:43.703418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
27196 12:32:43.760065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass
27198 12:32:43.760449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass>
27199 12:32:43.816230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
27201 12:32:43.816990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
27202 12:32:43.873319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
27203 12:32:43.873884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
27205 12:32:43.931629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
27207 12:32:43.932045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
27208 12:32:43.989193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass>
27209 12:32:43.989765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass
27211 12:32:44.047580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
27212 12:32:44.048082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
27214 12:32:44.104524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
27215 12:32:44.105051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
27217 12:32:44.161585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
27218 12:32:44.162172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
27220 12:32:44.220706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass>
27221 12:32:44.221136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass
27223 12:32:44.280955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
27224 12:32:44.281385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
27226 12:32:44.341018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
27228 12:32:44.341442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
27229 12:32:44.399778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
27231 12:32:44.400536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
27232 12:32:44.459486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass>
27233 12:32:44.459941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass
27235 12:32:44.517902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
27236 12:32:44.518304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
27238 12:32:44.576636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
27239 12:32:44.577190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
27241 12:32:44.634943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
27242 12:32:44.635378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
27244 12:32:44.677323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass
27246 12:32:44.677824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass>
27247 12:32:44.720351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
27249 12:32:44.720826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
27250 12:32:44.764699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
27251 12:32:44.765188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
27253 12:32:44.816530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
27254 12:32:44.817093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
27256 12:32:44.866202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass
27258 12:32:44.866638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass>
27259 12:32:44.909018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
27260 12:32:44.909438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
27262 12:32:44.953529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
27263 12:32:44.953975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
27265 12:32:44.995147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
27266 12:32:44.995601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
27268 12:32:45.039734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass
27270 12:32:45.040129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass>
27271 12:32:45.081847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
27273 12:32:45.082427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
27274 12:32:45.127287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
27275 12:32:45.127781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
27277 12:32:45.171503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
27278 12:32:45.171951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
27280 12:32:45.218777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass>
27281 12:32:45.219235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass
27283 12:32:45.267080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
27284 12:32:45.267521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
27286 12:32:45.307683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
27287 12:32:45.308133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
27289 12:32:45.356164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
27290 12:32:45.356576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
27292 12:32:45.403301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass>
27293 12:32:45.403760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass
27295 12:32:45.451715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
27296 12:32:45.452147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
27298 12:32:45.496471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
27299 12:32:45.496913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
27301 12:32:45.538134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
27303 12:32:45.538611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
27304 12:32:45.576494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass
27306 12:32:45.576884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass>
27307 12:32:45.617064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
27308 12:32:45.617425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
27310 12:32:45.664585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
27311 12:32:45.664982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
27313 12:32:45.715461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
27314 12:32:45.715913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
27316 12:32:45.770384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass
27318 12:32:45.770846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass>
27319 12:32:45.824916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
27320 12:32:45.825298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
27322 12:32:45.873508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
27324 12:32:45.873998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
27325 12:32:45.916867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
27326 12:32:45.917311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
27328 12:32:45.956152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass>
27329 12:32:45.956697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass
27331 12:32:45.994462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
27333 12:32:45.995095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
27334 12:32:46.033480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
27335 12:32:46.034054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
27337 12:32:46.072818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
27338 12:32:46.073190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
27340 12:32:46.112707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass>
27341 12:32:46.113111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass
27343 12:32:46.161074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
27344 12:32:46.161462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
27346 12:32:46.200409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
27348 12:32:46.200836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
27349 12:32:46.249249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
27351 12:32:46.250005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
27352 12:32:46.296216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass>
27353 12:32:46.296618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass
27355 12:32:46.334698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
27356 12:32:46.335108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
27358 12:32:46.373719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
27359 12:32:46.374163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
27361 12:32:46.421162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
27362 12:32:46.421596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
27364 12:32:46.462856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass>
27365 12:32:46.463291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass
27367 12:32:46.508666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
27368 12:32:46.509107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
27370 12:32:46.553419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
27371 12:32:46.553836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
27373 12:32:46.603452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
27374 12:32:46.603928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
27376 12:32:46.656281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass>
27377 12:32:46.656784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass
27379 12:32:46.695614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
27380 12:32:46.696174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
27382 12:32:46.737728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
27384 12:32:46.738503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
27385 12:32:46.779293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
27386 12:32:46.779842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
27388 12:32:46.825320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass
27390 12:32:46.825906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass>
27391 12:32:46.866988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
27392 12:32:46.867422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
27394 12:32:46.911627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
27395 12:32:46.912020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
27397 12:32:46.972873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
27398 12:32:46.973428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
27400 12:32:47.011149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass>
27401 12:32:47.011602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass
27403 12:32:47.054898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
27404 12:32:47.055391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
27406 12:32:47.092379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
27407 12:32:47.092847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
27409 12:32:47.141004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
27410 12:32:47.141437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
27412 12:32:47.185159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass>
27413 12:32:47.185568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass
27415 12:32:47.224522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
27416 12:32:47.224956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
27418 12:32:47.272252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
27419 12:32:47.272658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
27421 12:32:47.315812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
27422 12:32:47.316256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
27424 12:32:47.363396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass>
27425 12:32:47.363843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass
27427 12:32:47.408003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
27428 12:32:47.408555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
27430 12:32:47.447574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
27432 12:32:47.448066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
27433 12:32:47.486339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
27435 12:32:47.486824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
27436 12:32:47.540798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass>
27437 12:32:47.541227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass
27439 12:32:47.600997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
27440 12:32:47.601430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
27442 12:32:47.660532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
27443 12:32:47.660955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
27445 12:32:47.720477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
27446 12:32:47.720919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
27448 12:32:47.780586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass>
27449 12:32:47.781019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass
27451 12:32:47.841561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
27452 12:32:47.842012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
27454 12:32:47.901170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
27455 12:32:47.901594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
27457 12:32:47.960601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
27458 12:32:47.961027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
27460 12:32:48.022935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass>
27461 12:32:48.023361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass
27463 12:32:48.082038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
27465 12:32:48.082521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
27466 12:32:48.131600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
27467 12:32:48.132028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
27469 12:32:48.185858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
27470 12:32:48.186281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
27472 12:32:48.231784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass>
27473 12:32:48.232221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass
27475 12:32:48.274222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
27477 12:32:48.274885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
27478 12:32:48.316994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
27479 12:32:48.317420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
27481 12:32:48.358201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
27483 12:32:48.358750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
27484 12:32:48.400616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass>
27485 12:32:48.401073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass
27487 12:32:48.451147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
27489 12:32:48.451623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
27490 12:32:48.493322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
27492 12:32:48.493811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
27493 12:32:48.548932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
27494 12:32:48.549384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
27496 12:32:48.603399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass>
27497 12:32:48.603856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass
27499 12:32:48.653835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
27501 12:32:48.654422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
27502 12:32:48.709437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
27503 12:32:48.709890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
27505 12:32:48.760739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
27506 12:32:48.761174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
27508 12:32:48.812385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass>
27509 12:32:48.812764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass
27511 12:32:48.853485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
27512 12:32:48.853927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
27514 12:32:48.912488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
27515 12:32:48.912945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
27517 12:32:48.967839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
27519 12:32:48.968324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
27520 12:32:49.025499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass>
27521 12:32:49.025915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass
27523 12:32:49.084082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
27524 12:32:49.084549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
27526 12:32:49.141719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
27527 12:32:49.142155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
27529 12:32:49.200144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
27531 12:32:49.200575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
27532 12:32:49.259219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass
27534 12:32:49.259723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass>
27535 12:32:49.315076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
27536 12:32:49.315494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
27538 12:32:49.373378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
27539 12:32:49.373777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
27541 12:32:49.431623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
27542 12:32:49.432052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
27544 12:32:49.488260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass>
27545 12:32:49.488754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass
27547 12:32:49.539952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
27548 12:32:49.540397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
27550 12:32:49.588248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
27551 12:32:49.588702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
27553 12:32:49.637098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
27555 12:32:49.637577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
27556 12:32:49.687827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass>
27557 12:32:49.688283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass
27559 12:32:49.740330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
27560 12:32:49.740778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
27562 12:32:49.789574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
27563 12:32:49.790006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
27565 12:32:49.831909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
27566 12:32:49.832351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
27568 12:32:49.877112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass>
27569 12:32:49.877558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass
27571 12:32:49.927274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
27572 12:32:49.927749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
27574 12:32:49.978472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
27576 12:32:49.978907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
27577 12:32:50.028040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
27578 12:32:50.028482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
27580 12:32:50.084915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass>
27581 12:32:50.085345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass
27583 12:32:50.125971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
27585 12:32:50.126463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
27586 12:32:50.167396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
27587 12:32:50.167809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
27589 12:32:50.209288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
27590 12:32:50.209687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
27592 12:32:50.252875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass
27594 12:32:50.253341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass>
27595 12:32:50.292252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
27596 12:32:50.292690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
27598 12:32:50.351331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
27599 12:32:50.351771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
27601 12:32:50.408129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
27602 12:32:50.408638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
27604 12:32:50.468391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass>
27605 12:32:50.468792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass
27607 12:32:50.529791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
27608 12:32:50.530198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
27610 12:32:50.589264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
27611 12:32:50.589692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
27613 12:32:50.653765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
27614 12:32:50.654174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
27616 12:32:50.709715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass
27618 12:32:50.710170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass>
27619 12:32:50.769271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
27620 12:32:50.769688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
27622 12:32:50.830298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
27624 12:32:50.830890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
27625 12:32:50.890043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
27627 12:32:50.890511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
27628 12:32:50.951350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass>
27629 12:32:50.951752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass
27631 12:32:51.009707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
27632 12:32:51.010082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
27634 12:32:51.069401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
27635 12:32:51.069812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
27637 12:32:51.129540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
27638 12:32:51.129954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
27640 12:32:51.189188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass>
27641 12:32:51.189583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass
27643 12:32:51.248727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
27644 12:32:51.249153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
27646 12:32:51.309236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
27647 12:32:51.309677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
27649 12:32:51.367366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
27650 12:32:51.367807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
27652 12:32:51.414781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass>
27653 12:32:51.415215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass
27655 12:32:51.460346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
27656 12:32:51.460739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
27658 12:32:51.507480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
27659 12:32:51.508027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
27661 12:32:51.565447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
27662 12:32:51.565870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
27664 12:32:51.611919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass>
27665 12:32:51.612361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass
27667 12:32:51.666399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
27668 12:32:51.666803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
27670 12:32:51.709362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
27671 12:32:51.709804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
27673 12:32:51.757798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
27674 12:32:51.758209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
27676 12:32:51.812369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass>
27677 12:32:51.812782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass
27679 12:32:51.861389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
27680 12:32:51.861826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
27682 12:32:51.912916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
27683 12:32:51.913355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
27685 12:32:51.966051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
27686 12:32:51.966464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
27688 12:32:52.012050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=pass
27690 12:32:52.012532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=pass>
27691 12:32:52.092837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass>
27692 12:32:52.093279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass
27694 12:32:52.152517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass>
27695 12:32:52.152987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass
27697 12:32:52.211102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass>
27698 12:32:52.211560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass
27700 12:32:52.269491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass
27702 12:32:52.269968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass>
27703 12:32:52.328414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass>
27704 12:32:52.328817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass
27706 12:32:52.385404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass
27708 12:32:52.385876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass>
27709 12:32:52.444093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass>
27710 12:32:52.444508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass
27712 12:32:52.502099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass>
27713 12:32:52.502507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass
27715 12:32:52.559480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass>
27716 12:32:52.559915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass
27718 12:32:52.617424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass>
27719 12:32:52.617897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass
27721 12:32:52.676288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass>
27722 12:32:52.676739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass
27724 12:32:52.736518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass>
27725 12:32:52.736916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass
27727 12:32:52.792919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass>
27728 12:32:52.793316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass
27730 12:32:52.850914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass>
27731 12:32:52.851324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass
27733 12:32:52.908873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass>
27734 12:32:52.909266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass
27736 12:32:52.968372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass
27738 12:32:52.969003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass>
27739 12:32:53.026967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass>
27740 12:32:53.027400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass
27742 12:32:53.085329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass>
27743 12:32:53.085814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass
27745 12:32:53.144874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass>
27746 12:32:53.145300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass
27748 12:32:53.207003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass
27750 12:32:53.207446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass>
27751 12:32:53.268448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass>
27752 12:32:53.268881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass
27754 12:32:53.327675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass
27756 12:32:53.328068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass>
27757 12:32:53.385558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass>
27758 12:32:53.386009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass
27760 12:32:53.443282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
27761 12:32:53.443737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
27763 12:32:53.500560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass
27765 12:32:53.501045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass>
27766 12:32:53.559689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
27767 12:32:53.560184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
27769 12:32:53.617363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass
27771 12:32:53.617993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass>
27772 12:32:53.676346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass>
27773 12:32:53.676750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass
27775 12:32:53.734814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass>
27776 12:32:53.735318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass
27778 12:32:53.791606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass
27780 12:32:53.792038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass>
27781 12:32:53.845406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass
27783 12:32:53.845900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass>
27784 12:32:53.896041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass
27786 12:32:53.896452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass>
27787 12:32:53.935934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass>
27788 12:32:53.936491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass
27790 12:32:53.977827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip>
27791 12:32:53.978266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip
27793 12:32:54.029796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip
27795 12:32:54.030281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip>
27796 12:32:54.079394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass>
27797 12:32:54.079829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass
27799 12:32:54.128688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass>
27800 12:32:54.129096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass
27802 12:32:54.172961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass>
27803 12:32:54.173536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass
27805 12:32:54.217712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass>
27806 12:32:54.218282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass
27808 12:32:54.269815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip>
27809 12:32:54.270264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip
27811 12:32:54.319537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip>
27812 12:32:54.320166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip
27814 12:32:54.368292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass>
27815 12:32:54.368748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass
27817 12:32:54.415136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip>
27818 12:32:54.415585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip
27820 12:32:54.461726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip>
27821 12:32:54.462191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip
27823 12:32:54.503918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass>
27824 12:32:54.504431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass
27826 12:32:54.556149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip>
27827 12:32:54.556570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip
27829 12:32:54.616857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip>
27830 12:32:54.617253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip
27832 12:32:54.676642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass
27834 12:32:54.677132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass>
27835 12:32:54.727895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass>
27836 12:32:54.728294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass
27838 12:32:54.776181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass
27840 12:32:54.776662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass>
27841 12:32:54.815537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass>
27842 12:32:54.815965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass
27844 12:32:54.860129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip
27846 12:32:54.860515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip>
27847 12:32:54.902866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip>
27848 12:32:54.903263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip
27850 12:32:54.945516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass>
27851 12:32:54.945959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass
27853 12:32:54.997515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip>
27854 12:32:54.997960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip
27856 12:32:55.044797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip>
27857 12:32:55.045243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip
27859 12:32:55.095076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass
27861 12:32:55.095504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass>
27862 12:32:55.143377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip>
27863 12:32:55.143795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip
27865 12:32:55.194050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip
27867 12:32:55.194547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip>
27868 12:32:55.244218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass>
27869 12:32:55.244632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass
27871 12:32:55.295530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip>
27872 12:32:55.295952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip
27874 12:32:55.338960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip>
27875 12:32:55.339394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip
27877 12:32:55.386040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass
27879 12:32:55.386503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass>
27880 12:32:55.428320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip>
27881 12:32:55.428685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip
27883 12:32:55.474471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip
27885 12:32:55.474862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip>
27886 12:32:55.533794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass>
27887 12:32:55.534239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass
27889 12:32:55.593435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip>
27890 12:32:55.593857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip
27892 12:32:55.652514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip>
27893 12:32:55.653054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip
27895 12:32:55.711900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass>
27896 12:32:55.712312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass
27898 12:32:55.766869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip>
27899 12:32:55.767299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip
27901 12:32:55.816392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip>
27902 12:32:55.816821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip
27904 12:32:55.863935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass>
27905 12:32:55.864380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass
27907 12:32:55.909428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass>
27908 12:32:55.909841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass
27910 12:32:55.950859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass
27912 12:32:55.951332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass>
27913 12:32:56.000952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass>
27914 12:32:56.001414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass
27916 12:32:56.048748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip>
27917 12:32:56.049203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip
27919 12:32:56.088774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip>
27920 12:32:56.089234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip
27922 12:32:56.132046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass>
27923 12:32:56.132503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass
27925 12:32:56.181814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip>
27926 12:32:56.182279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip
27928 12:32:56.232276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip
27930 12:32:56.232704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip>
27931 12:32:56.281067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass>
27932 12:32:56.281524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass
27934 12:32:56.333011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip>
27935 12:32:56.333453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip
27937 12:32:56.384049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip
27939 12:32:56.384734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip>
27940 12:32:56.431546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass>
27941 12:32:56.431961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass
27943 12:32:56.474838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip>
27944 12:32:56.475255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip
27946 12:32:56.521722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip>
27947 12:32:56.522153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip
27949 12:32:56.570146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass
27951 12:32:56.570636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass>
27952 12:32:56.618266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip
27954 12:32:56.618733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip>
27955 12:32:56.663437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip>
27956 12:32:56.663889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip
27958 12:32:56.712595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass
27960 12:32:56.713156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass>
27961 12:32:56.754208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip
27963 12:32:56.754637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip>
27964 12:32:56.803695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip
27966 12:32:56.804192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip>
27967 12:32:56.859460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass
27969 12:32:56.859915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass>
27970 12:32:56.917635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip>
27971 12:32:56.918082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip
27973 12:32:56.979015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip>
27974 12:32:56.979415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip
27976 12:32:57.028663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass>
27977 12:32:57.029111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass
27979 12:32:57.077247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip>
27980 12:32:57.077687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip
27982 12:32:57.122201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip
27984 12:32:57.122617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip>
27985 12:32:57.187697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass
27987 12:32:57.188394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass>
27988 12:32:57.234052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip>
27989 12:32:57.234488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip
27991 12:32:57.286046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip
27993 12:32:57.286582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip>
27994 12:32:57.328303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass>
27995 12:32:57.328728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass
27997 12:32:57.374902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip>
27998 12:32:57.375337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip
28000 12:32:57.428554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip>
28001 12:32:57.428974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip
28003 12:32:57.475578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass>
28004 12:32:57.476026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass
28006 12:32:57.525641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip
28008 12:32:57.526060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip>
28009 12:32:57.585524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip>
28010 12:32:57.585963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip
28012 12:32:57.647194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass
28014 12:32:57.647876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass>
28015 12:32:57.707130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip>
28016 12:32:57.707684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip
28018 12:32:57.767114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip>
28019 12:32:57.767546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip
28021 12:32:57.818075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass
28023 12:32:57.818561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass>
28024 12:32:57.862777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip>
28025 12:32:57.863200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip
28027 12:32:57.906075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip
28029 12:32:57.906537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip>
28030 12:32:57.951525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass
28032 12:32:57.951980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass>
28033 12:32:57.994378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip
28035 12:32:57.994870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip>
28036 12:32:58.042276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip
28038 12:32:58.042883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip>
28039 12:32:58.088873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass>
28040 12:32:58.089263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass
28042 12:32:58.140742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip
28044 12:32:58.141136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip>
28045 12:32:58.189532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip>
28046 12:32:58.189944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip
28048 12:32:58.235663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass>
28049 12:32:58.236126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass
28051 12:32:58.287445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip>
28052 12:32:58.287890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip
28054 12:32:58.335940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip
28056 12:32:58.336416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip>
28057 12:32:58.379698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass>
28058 12:32:58.380158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass
28060 12:32:58.422119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip
28062 12:32:58.422596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip>
28063 12:32:58.475153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip>
28064 12:32:58.475588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip
28066 12:32:58.520192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass>
28067 12:32:58.520628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass
28069 12:32:58.567994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip>
28070 12:32:58.568360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip
28072 12:32:58.621341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip>
28073 12:32:58.621805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip
28075 12:32:58.666555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass>
28076 12:32:58.666923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass
28078 12:32:58.708738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip>
28079 12:32:58.709154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip
28081 12:32:58.746958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip>
28082 12:32:58.747522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip
28084 12:32:58.792500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass>
28085 12:32:58.792935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass
28087 12:32:58.835429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip>
28088 12:32:58.836062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip
28090 12:32:58.881968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip
28092 12:32:58.882439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip>
28093 12:32:58.937095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass>
28094 12:32:58.938413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass
28096 12:32:58.987582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip>
28097 12:32:58.988015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip
28099 12:32:59.047183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip>
28100 12:32:59.047569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip
28102 12:32:59.086847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass>
28103 12:32:59.087285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass
28105 12:32:59.135011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip
28107 12:32:59.135495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip>
28108 12:32:59.185353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip
28110 12:32:59.185850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip>
28111 12:32:59.244347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass>
28112 12:32:59.244771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass
28114 12:32:59.295663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip>
28115 12:32:59.296100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip
28117 12:32:59.347292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip>
28118 12:32:59.347784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip
28120 12:32:59.393503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass>
28121 12:32:59.394045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass
28123 12:32:59.443883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip>
28124 12:32:59.444315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip
28126 12:32:59.489720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip
28128 12:32:59.490201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip>
28129 12:32:59.542160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass
28131 12:32:59.542642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass>
28132 12:32:59.596943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip>
28133 12:32:59.597361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip
28135 12:32:59.641328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip>
28136 12:32:59.641767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip
28138 12:32:59.681836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass>
28139 12:32:59.682289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass
28141 12:32:59.727146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip>
28142 12:32:59.727577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip
28144 12:32:59.779152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip>
28145 12:32:59.779584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip
28147 12:32:59.828880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass
28149 12:32:59.829360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass>
28150 12:32:59.875638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip>
28151 12:32:59.876077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip
28153 12:32:59.920698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip>
28154 12:32:59.921179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip
28156 12:32:59.968118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass>
28157 12:32:59.968553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass
28159 12:33:00.014410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip>
28160 12:33:00.015102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip
28162 12:33:00.057906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip
28164 12:33:00.058388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip>
28165 12:33:00.104632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass>
28166 12:33:00.105094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass
28168 12:33:00.155610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip>
28169 12:33:00.156051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip
28171 12:33:00.210229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip>
28172 12:33:00.210719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip
28174 12:33:00.260803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass>
28175 12:33:00.261264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass
28177 12:33:00.320144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip
28179 12:33:00.320889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip>
28180 12:33:00.377546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip
28182 12:33:00.378326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip>
28183 12:33:00.435693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass>
28184 12:33:00.436189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass
28186 12:33:00.493619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip>
28187 12:33:00.494096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip
28189 12:33:00.553114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip>
28190 12:33:00.553563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip
28192 12:33:00.612294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass>
28193 12:33:00.612750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass
28195 12:33:00.670816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip>
28196 12:33:00.671253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip
28198 12:33:00.728566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip>
28199 12:33:00.729001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip
28201 12:33:00.785718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass
28203 12:33:00.786187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass>
28204 12:33:00.845121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip>
28205 12:33:00.845612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip
28207 12:33:00.904616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip>
28208 12:33:00.905064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip
28210 12:33:00.961573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass
28212 12:33:00.962059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass>
28213 12:33:01.019009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip>
28214 12:33:01.019463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip
28216 12:33:01.076352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip>
28217 12:33:01.076795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip
28219 12:33:01.134849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass>
28220 12:33:01.135302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass
28222 12:33:01.192133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip>
28223 12:33:01.192588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip
28225 12:33:01.249663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip>
28226 12:33:01.250130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip
28228 12:33:01.309167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass
28230 12:33:01.309660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass>
28231 12:33:01.366643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip>
28232 12:33:01.367081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip
28234 12:33:01.417553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip>
28235 12:33:01.418030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip
28237 12:33:01.472726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass>
28238 12:33:01.473076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass
28240 12:33:01.519117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip>
28241 12:33:01.519568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip
28243 12:33:01.573013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip>
28244 12:33:01.573429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip
28246 12:33:01.632126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass>
28247 12:33:01.632547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass
28249 12:33:01.688392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip
28251 12:33:01.689141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip>
28252 12:33:01.739317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip>
28253 12:33:01.739759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip
28255 12:33:01.788078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass>
28256 12:33:01.788596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass
28258 12:33:01.832947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip>
28259 12:33:01.833513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip
28261 12:33:01.876127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip>
28262 12:33:01.876555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip
28264 12:33:01.927245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass
28266 12:33:01.927827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass>
28267 12:33:01.971336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip>
28268 12:33:01.971754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip
28270 12:33:02.023675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip>
28271 12:33:02.024126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip
28273 12:33:02.068327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass>
28274 12:33:02.068762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass
28276 12:33:02.117528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip>
28277 12:33:02.117956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip
28279 12:33:02.163266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip
28281 12:33:02.163952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip>
28282 12:33:02.217927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass
28284 12:33:02.218408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass>
28285 12:33:02.264291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip>
28286 12:33:02.264726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip
28288 12:33:02.333282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip>
28289 12:33:02.333694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip
28291 12:33:02.381024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass>
28292 12:33:02.381475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass
28294 12:33:02.427658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip>
28295 12:33:02.428014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip
28297 12:33:02.477365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip>
28298 12:33:02.477788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip
28300 12:33:02.525631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass
28302 12:33:02.526137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass>
28303 12:33:02.585564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip>
28304 12:33:02.586038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip
28306 12:33:02.645537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip>
28307 12:33:02.645980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip
28309 12:33:02.705698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass>
28310 12:33:02.706148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass
28312 12:33:02.760594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip>
28313 12:33:02.761033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip
28315 12:33:02.813349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip>
28316 12:33:02.813734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip
28318 12:33:02.868215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass>
28319 12:33:02.868633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass
28321 12:33:02.913321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip>
28322 12:33:02.913680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip
28324 12:33:02.959206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip
28326 12:33:02.959823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip>
28327 12:33:03.001396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass
28329 12:33:03.002075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass>
28330 12:33:03.047520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip>
28331 12:33:03.048092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip
28333 12:33:03.090663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip>
28334 12:33:03.091117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip
28336 12:33:03.136733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass>
28337 12:33:03.137191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass
28339 12:33:03.181679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip>
28340 12:33:03.182127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip
28342 12:33:03.235643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip>
28343 12:33:03.236047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip
28345 12:33:03.287721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass
28347 12:33:03.288193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass>
28348 12:33:03.343989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip>
28349 12:33:03.344420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip
28351 12:33:03.388192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip
28353 12:33:03.388557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip>
28354 12:33:03.442197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass
28356 12:33:03.442670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass>
28357 12:33:03.492828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip
28359 12:33:03.493388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip>
28360 12:33:03.536854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip>
28361 12:33:03.537411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip
28363 12:33:03.587856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass
28365 12:33:03.588603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass>
28366 12:33:03.632612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip
28368 12:33:03.633096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip>
28369 12:33:03.679850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip
28371 12:33:03.680312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip>
28372 12:33:03.725469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass
28374 12:33:03.725953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass>
28375 12:33:03.775853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip
28377 12:33:03.776313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip>
28378 12:33:03.817765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip>
28379 12:33:03.818272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip
28381 12:33:03.860626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass
28383 12:33:03.861287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass>
28384 12:33:03.917397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip>
28385 12:33:03.917855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip
28387 12:33:03.977233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip
28389 12:33:03.977692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip>
28390 12:33:04.025083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass
28392 12:33:04.025554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass>
28393 12:33:04.068004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip>
28394 12:33:04.068452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip
28396 12:33:04.116835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip>
28397 12:33:04.117292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip
28399 12:33:04.161169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass
28401 12:33:04.161640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass>
28402 12:33:04.209516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip
28404 12:33:04.209969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip>
28405 12:33:04.257325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip>
28406 12:33:04.257734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip
28408 12:33:04.307367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass>
28409 12:33:04.307777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass
28411 12:33:04.360966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip>
28412 12:33:04.361372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip
28414 12:33:04.412397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip>
28415 12:33:04.412889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip
28417 12:33:04.457246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass>
28418 12:33:04.457701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass
28420 12:33:04.506410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip
28422 12:33:04.506896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip>
28423 12:33:04.547850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip>
28424 12:33:04.548274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip
28426 12:33:04.597416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass
28428 12:33:04.597893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass>
28429 12:33:04.642223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip
28431 12:33:04.642785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip>
28432 12:33:04.696978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip>
28433 12:33:04.697419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip
28435 12:33:04.737944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass
28437 12:33:04.738423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass>
28438 12:33:04.786903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip>
28439 12:33:04.787337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip
28441 12:33:04.828248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip
28443 12:33:04.828981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip>
28444 12:33:04.876240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass
28446 12:33:04.876632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass>
28447 12:33:04.919188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip>
28448 12:33:04.919722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip
28450 12:33:04.960190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip>
28451 12:33:04.960735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip
28453 12:33:05.001357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass>
28454 12:33:05.001807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass
28456 12:33:05.052238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip>
28457 12:33:05.052682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip
28459 12:33:05.093144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip>
28460 12:33:05.093660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip
28462 12:33:05.138286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass
28464 12:33:05.138762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass>
28465 12:33:05.182856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip
28467 12:33:05.183323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip>
28468 12:33:05.222916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip>
28469 12:33:05.223406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip
28471 12:33:05.265774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass
28473 12:33:05.266260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass>
28474 12:33:05.315543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip>
28475 12:33:05.315905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip
28477 12:33:05.363760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip
28479 12:33:05.364230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip>
28480 12:33:05.404678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass
28482 12:33:05.405142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass>
28483 12:33:05.452398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip
28485 12:33:05.452870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip>
28486 12:33:05.501654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip>
28487 12:33:05.502097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip
28489 12:33:05.547577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass
28491 12:33:05.548056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass>
28492 12:33:05.591613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip>
28493 12:33:05.592051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip
28495 12:33:05.637619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip
28497 12:33:05.638115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip>
28498 12:33:05.682097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass
28500 12:33:05.682578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass>
28501 12:33:05.732126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip>
28502 12:33:05.732584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip
28504 12:33:05.785418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip>
28505 12:33:05.785880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip
28507 12:33:05.836166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass>
28508 12:33:05.836705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass
28510 12:33:05.882252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip
28512 12:33:05.882981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip>
28513 12:33:05.936463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip>
28514 12:33:05.936917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip
28516 12:33:05.981489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass>
28517 12:33:05.981942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass
28519 12:33:06.029105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip>
28520 12:33:06.029533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip
28522 12:33:06.072346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip>
28523 12:33:06.072798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip
28525 12:33:06.113162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass>
28526 12:33:06.113570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass
28528 12:33:06.159638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip>
28529 12:33:06.160054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip
28531 12:33:06.204214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip>
28532 12:33:06.204625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip
28534 12:33:06.257700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass>
28535 12:33:06.258140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass
28537 12:33:06.301113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip>
28538 12:33:06.301555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip
28540 12:33:06.348017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip>
28541 12:33:06.348448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip
28543 12:33:06.393022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass
28545 12:33:06.393447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass>
28546 12:33:06.445523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip>
28547 12:33:06.445957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip
28549 12:33:06.494155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip>
28550 12:33:06.494601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip
28552 12:33:06.533838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass>
28553 12:33:06.534274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass
28555 12:33:06.573747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip>
28556 12:33:06.574190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip
28558 12:33:06.614900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip>
28559 12:33:06.615335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip
28561 12:33:06.656631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass>
28562 12:33:06.657076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass
28564 12:33:06.705748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip>
28565 12:33:06.706171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip
28567 12:33:06.760714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip
28569 12:33:06.761193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip>
28570 12:33:06.809122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass>
28571 12:33:06.809529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass
28573 12:33:06.851302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip
28575 12:33:06.851782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip>
28576 12:33:06.894829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip>
28577 12:33:06.895273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip
28579 12:33:06.936568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass>
28580 12:33:06.937029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass
28582 12:33:06.976905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip>
28583 12:33:06.977340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip
28585 12:33:07.017334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip>
28586 12:33:07.017843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip
28588 12:33:07.060029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass>
28589 12:33:07.060446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass
28591 12:33:07.120503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip>
28592 12:33:07.120878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip
28594 12:33:07.180018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip
28596 12:33:07.180630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip>
28597 12:33:07.230894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass>
28598 12:33:07.231332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass
28600 12:33:07.281410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip>
28601 12:33:07.281860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip
28603 12:33:07.329260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip>
28604 12:33:07.329659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip
28606 12:33:07.383967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass
28608 12:33:07.384445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass>
28609 12:33:07.444474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip
28611 12:33:07.444943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip>
28612 12:33:07.487855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip>
28613 12:33:07.488345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip
28615 12:33:07.541540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass
28617 12:33:07.542037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass>
28618 12:33:07.595719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip
28620 12:33:07.596461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip>
28621 12:33:07.653644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip>
28622 12:33:07.654050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip
28624 12:33:07.701695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass>
28625 12:33:07.702144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass
28627 12:33:07.745932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip
28629 12:33:07.746383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip>
28630 12:33:07.796385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip>
28631 12:33:07.796812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip
28633 12:33:07.856525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass
28635 12:33:07.857106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass>
28636 12:33:07.916733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip>
28637 12:33:07.917213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip
28639 12:33:07.977168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip>
28640 12:33:07.977695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip
28642 12:33:08.037597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass>
28643 12:33:08.038172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass
28645 12:33:08.099800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip>
28646 12:33:08.100238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip
28648 12:33:08.160161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip>
28649 12:33:08.160538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip
28651 12:33:08.220162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass>
28652 12:33:08.220581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass
28654 12:33:08.273546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip>
28655 12:33:08.273988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip
28657 12:33:08.332612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip>
28658 12:33:08.333006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip
28660 12:33:08.382079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass
28662 12:33:08.382504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass>
28663 12:33:08.441114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip>
28664 12:33:08.441509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip
28666 12:33:08.488306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip>
28667 12:33:08.488714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip
28669 12:33:08.528242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass
28671 12:33:08.528834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass>
28672 12:33:08.573140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip>
28673 12:33:08.573678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip
28675 12:33:08.624865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip>
28676 12:33:08.625226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip
28678 12:33:08.676232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass>
28679 12:33:08.676799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass
28681 12:33:08.729119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip
28683 12:33:08.729595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip>
28684 12:33:08.783046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip>
28685 12:33:08.783626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip
28687 12:33:08.834066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass>
28688 12:33:08.834555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass
28690 12:33:08.885506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip
28692 12:33:08.885997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip>
28693 12:33:08.937355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip
28695 12:33:08.938017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip>
28696 12:33:08.988079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass>
28697 12:33:08.988532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass
28699 12:33:09.039214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip>
28700 12:33:09.039730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip
28702 12:33:09.091305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip>
28703 12:33:09.091894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip
28705 12:33:09.137878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass>
28706 12:33:09.138382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass
28708 12:33:09.180409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip>
28709 12:33:09.180896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip
28711 12:33:09.225787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip>
28712 12:33:09.226260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip
28714 12:33:09.271776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass>
28715 12:33:09.272260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass
28717 12:33:09.314553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip>
28718 12:33:09.314995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip
28720 12:33:09.359810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip>
28721 12:33:09.360220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip
28723 12:33:09.419786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass
28725 12:33:09.420203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass>
28726 12:33:09.480417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip>
28727 12:33:09.480841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip
28729 12:33:09.540593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip>
28730 12:33:09.541022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip
28732 12:33:09.597790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass>
28733 12:33:09.598246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass
28735 12:33:09.644091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip>
28736 12:33:09.644528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip
28738 12:33:09.690307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip
28740 12:33:09.690765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip>
28741 12:33:09.739129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass>
28742 12:33:09.739579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass
28744 12:33:09.782344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip
28746 12:33:09.782954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip>
28747 12:33:09.833449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip>
28748 12:33:09.833912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip
28750 12:33:09.884792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass>
28751 12:33:09.885238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass
28753 12:33:09.935948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip>
28754 12:33:09.936390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip
28756 12:33:09.979665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip
28758 12:33:09.980147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip>
28759 12:33:10.022905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass
28761 12:33:10.023362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass>
28762 12:33:10.075466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip>
28763 12:33:10.076026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip
28765 12:33:10.125710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip
28767 12:33:10.126160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip>
28768 12:33:10.175314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass
28770 12:33:10.175772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass>
28771 12:33:10.215338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip>
28772 12:33:10.215760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip
28774 12:33:10.269977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip>
28775 12:33:10.270421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip
28777 12:33:10.313139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass>
28778 12:33:10.313518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass
28780 12:33:10.358250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip
28782 12:33:10.358696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip>
28783 12:33:10.403082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip>
28784 12:33:10.403500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip
28786 12:33:10.444516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass
28788 12:33:10.445007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass>
28789 12:33:10.490155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip
28791 12:33:10.493798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip>
28792 12:33:10.535845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip>
28793 12:33:10.536296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip
28795 12:33:10.584279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass>
28796 12:33:10.584727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass
28798 12:33:10.633283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip>
28799 12:33:10.633671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip
28801 12:33:10.677123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip>
28802 12:33:10.677506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip
28804 12:33:10.720025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass>
28805 12:33:10.720464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass
28807 12:33:10.767804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip
28809 12:33:10.768186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip>
28810 12:33:10.811441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip>
28811 12:33:10.811868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip
28813 12:33:10.861539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass
28815 12:33:10.862148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass>
28816 12:33:10.907422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip>
28817 12:33:10.907898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip
28819 12:33:10.965375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip>
28820 12:33:10.965957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip
28822 12:33:11.018207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass
28824 12:33:11.019258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass>
28825 12:33:11.066117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip
28827 12:33:11.066865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip>
28828 12:33:11.115965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip>
28829 12:33:11.116442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip
28831 12:33:11.176034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass>
28832 12:33:11.176424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass
28834 12:33:11.233769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip
28836 12:33:11.234315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip>
28837 12:33:11.295111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip>
28838 12:33:11.295614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip
28840 12:33:11.353619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass>
28841 12:33:11.354023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass
28843 12:33:11.413738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip
28845 12:33:11.414335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip>
28846 12:33:11.463122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip>
28847 12:33:11.463575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip
28849 12:33:11.513209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass>
28850 12:33:11.513597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass
28852 12:33:11.555634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip
28854 12:33:11.556107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip>
28855 12:33:11.600271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip>
28856 12:33:11.600722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip
28858 12:33:11.644333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass
28860 12:33:11.644784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass>
28861 12:33:11.685638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip>
28862 12:33:11.686077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip
28864 12:33:11.725392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip
28866 12:33:11.725891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip>
28867 12:33:11.773824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass
28869 12:33:11.774307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass>
28870 12:33:11.815376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip>
28871 12:33:11.815813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip
28873 12:33:11.855914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip
28875 12:33:11.856408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip>
28876 12:33:11.896887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass
28878 12:33:11.897321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass>
28879 12:33:11.937126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip
28881 12:33:11.937542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip>
28882 12:33:11.976460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip
28884 12:33:11.977001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip>
28885 12:33:12.021548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass
28887 12:33:12.022130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass>
28888 12:33:12.072240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip>
28889 12:33:12.072698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip
28891 12:33:12.117085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip>
28892 12:33:12.117518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip
28894 12:33:12.160817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass
28896 12:33:12.161197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass>
28897 12:33:12.202883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip>
28898 12:33:12.203319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip
28900 12:33:12.247363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip
28902 12:33:12.248131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip>
28903 12:33:12.292670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass
28905 12:33:12.293293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass>
28906 12:33:12.335922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip>
28907 12:33:12.336346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip
28909 12:33:12.377322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip>
28910 12:33:12.377766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip
28912 12:33:12.416232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass>
28913 12:33:12.416655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass
28915 12:33:12.458176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip
28917 12:33:12.458653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip>
28918 12:33:12.524552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip>
28919 12:33:12.524977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip
28921 12:33:12.593144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass
28923 12:33:12.593837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass>
28924 12:33:12.652473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip
28926 12:33:12.652958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip>
28927 12:33:12.711968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip>
28928 12:33:12.712328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip
28930 12:33:12.769463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass>
28931 12:33:12.769972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass
28933 12:33:12.829524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip>
28934 12:33:12.829952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip
28936 12:33:12.889247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip>
28937 12:33:12.889612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip
28939 12:33:12.947528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass
28941 12:33:12.948007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass>
28942 12:33:12.990188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip
28944 12:33:12.990566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip>
28945 12:33:13.045240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip
28947 12:33:13.045663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip>
28948 12:33:13.090794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass>
28949 12:33:13.091198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass
28951 12:33:13.133903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip>
28952 12:33:13.134296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip
28954 12:33:13.182721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip
28956 12:33:13.183204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip>
28957 12:33:13.224845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass>
28958 12:33:13.225278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass
28960 12:33:13.269670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip
28962 12:33:13.270180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip>
28963 12:33:13.317638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip
28965 12:33:13.318137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip>
28966 12:33:13.366832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass>
28967 12:33:13.367290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass
28969 12:33:13.413470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip
28971 12:33:13.413953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip>
28972 12:33:13.456465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip>
28973 12:33:13.456890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip
28975 12:33:13.498245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass
28977 12:33:13.498748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass>
28978 12:33:13.558262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip
28980 12:33:13.558744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip>
28981 12:33:13.617331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip
28983 12:33:13.617801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip>
28984 12:33:13.680601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass>
28985 12:33:13.681032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass
28987 12:33:13.739433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip>
28988 12:33:13.739827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip
28990 12:33:13.797073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip>
28991 12:33:13.797517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip
28993 12:33:13.856268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass>
28994 12:33:13.856656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass
28996 12:33:13.911682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip
28998 12:33:13.912151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip>
28999 12:33:13.959055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip
29001 12:33:13.959507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip>
29002 12:33:14.000830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass>
29003 12:33:14.001206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass
29005 12:33:14.049898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip
29007 12:33:14.050385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip>
29008 12:33:14.099232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip>
29009 12:33:14.099653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip
29011 12:33:14.143136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass>
29012 12:33:14.143549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass
29014 12:33:14.191209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip>
29015 12:33:14.191598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip
29017 12:33:14.237403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip>
29018 12:33:14.237766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip
29020 12:33:14.279774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass
29022 12:33:14.280224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass>
29023 12:33:14.328482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip>
29024 12:33:14.328920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip
29026 12:33:14.377252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip>
29027 12:33:14.377694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip
29029 12:33:14.430600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass>
29030 12:33:14.431000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass
29032 12:33:14.475482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip
29034 12:33:14.475965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip>
29035 12:33:14.518751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip>
29036 12:33:14.519288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip
29038 12:33:14.574919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass>
29039 12:33:14.575316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass
29041 12:33:14.633901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip>
29042 12:33:14.634388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip
29044 12:33:14.689324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip>
29045 12:33:14.689884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip
29047 12:33:14.735662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass>
29048 12:33:14.736166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass
29050 12:33:14.784737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip>
29051 12:33:14.785188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip
29053 12:33:14.833034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip>
29054 12:33:14.833439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip
29056 12:33:14.889227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass>
29057 12:33:14.889615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass
29059 12:33:14.949507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip>
29060 12:33:14.950032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip
29062 12:33:15.007918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip>
29063 12:33:15.008316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip
29065 12:33:15.064051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass>
29066 12:33:15.064504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass
29068 12:33:15.121194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip>
29069 12:33:15.121683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip
29071 12:33:15.177745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip
29073 12:33:15.178504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip>
29074 12:33:15.233901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass>
29075 12:33:15.234420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass
29077 12:33:15.280761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip>
29078 12:33:15.281175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip
29080 12:33:15.329768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip
29082 12:33:15.330260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip>
29083 12:33:15.378188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass
29085 12:33:15.378922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass>
29086 12:33:15.431372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip>
29087 12:33:15.431934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip
29089 12:33:15.477484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip
29091 12:33:15.477983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip>
29092 12:33:15.520119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass>
29093 12:33:15.520654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass
29095 12:33:15.564298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip>
29096 12:33:15.564730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip
29098 12:33:15.613432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip>
29099 12:33:15.613936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip
29101 12:33:15.656959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass
29103 12:33:15.657424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass>
29104 12:33:15.702907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip>
29105 12:33:15.703383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip
29107 12:33:15.748448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip>
29108 12:33:15.748882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip
29110 12:33:15.802241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass
29112 12:33:15.802712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass>
29113 12:33:15.847390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip>
29114 12:33:15.847891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip
29116 12:33:15.889342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip>
29117 12:33:15.889911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip
29119 12:33:15.941862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass
29121 12:33:15.942333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass>
29122 12:33:16.001661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip
29124 12:33:16.002088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip>
29125 12:33:16.051942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip>
29126 12:33:16.052349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip
29128 12:33:16.097369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass>
29129 12:33:16.097788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass
29131 12:33:16.146196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip
29133 12:33:16.146679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip>
29134 12:33:16.196810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip>
29135 12:33:16.197233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip
29137 12:33:16.241380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass
29139 12:33:16.242006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass>
29140 12:33:16.281216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip>
29141 12:33:16.281664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip
29143 12:33:16.325101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip
29145 12:33:16.325571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip>
29146 12:33:16.363292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass
29148 12:33:16.363740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass>
29149 12:33:16.417055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip
29151 12:33:16.417531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip>
29152 12:33:16.472098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip>
29153 12:33:16.472594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip
29155 12:33:16.516747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass>
29156 12:33:16.517191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass
29158 12:33:16.561770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip>
29159 12:33:16.562176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip
29161 12:33:16.608705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip
29163 12:33:16.609130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip>
29164 12:33:16.649658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass>
29165 12:33:16.650175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass
29167 12:33:16.688970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip>
29168 12:33:16.689409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip
29170 12:33:16.733262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip>
29171 12:33:16.733703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip
29173 12:33:16.780871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass
29175 12:33:16.781295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass>
29176 12:33:16.820668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip>
29177 12:33:16.821083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip
29179 12:33:16.868222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip>
29180 12:33:16.868658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip
29182 12:33:16.920720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass
29184 12:33:16.921197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass>
29185 12:33:16.960747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip>
29186 12:33:16.961170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip
29188 12:33:17.003739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip>
29189 12:33:17.004168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip
29191 12:33:17.048836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass>
29192 12:33:17.049301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass
29194 12:33:17.099488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip
29196 12:33:17.099962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip>
29197 12:33:17.139502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip>
29198 12:33:17.139962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip
29200 12:33:17.190097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass
29202 12:33:17.190706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass>
29203 12:33:17.241074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip>
29204 12:33:17.241514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip
29206 12:33:17.283992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip
29208 12:33:17.284748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip>
29209 12:33:17.329288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass>
29210 12:33:17.329743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass
29212 12:33:17.369414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip>
29213 12:33:17.369867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip
29215 12:33:17.420896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip
29217 12:33:17.421336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip>
29218 12:33:17.469436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass
29220 12:33:17.469915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass>
29221 12:33:17.519971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip>
29222 12:33:17.520403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip
29224 12:33:17.562225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip
29226 12:33:17.562707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip>
29227 12:33:17.619571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass>
29228 12:33:17.619986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass
29230 12:33:17.688534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip>
29231 12:33:17.688969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip
29233 12:33:17.732592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip>
29234 12:33:17.733027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip
29236 12:33:17.775265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass>
29237 12:33:17.775714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass
29239 12:33:17.827597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip>
29240 12:33:17.828259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip
29242 12:33:17.877937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip>
29243 12:33:17.878362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip
29245 12:33:17.916507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass
29247 12:33:17.917004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass>
29248 12:33:17.963130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip>
29249 12:33:17.963606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip
29251 12:33:18.008571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip>
29252 12:33:18.008997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip
29254 12:33:18.056347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass>
29255 12:33:18.056745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass
29257 12:33:18.101030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip>
29258 12:33:18.101467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip
29260 12:33:18.141787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip>
29261 12:33:18.142220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip
29263 12:33:18.180822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass>
29264 12:33:18.181275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass
29266 12:33:18.224729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip>
29267 12:33:18.225123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip
29269 12:33:18.272670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip
29271 12:33:18.273092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip>
29272 12:33:18.317185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass>
29273 12:33:18.317654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass
29275 12:33:18.368046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip>
29276 12:33:18.368498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip
29278 12:33:18.414821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip>
29279 12:33:18.415204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip
29281 12:33:18.455507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass
29283 12:33:18.456007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass>
29284 12:33:18.498217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip
29286 12:33:18.498695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip>
29287 12:33:18.547639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip>
29288 12:33:18.548063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip
29290 12:33:18.601472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass>
29291 12:33:18.601879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass
29293 12:33:18.660511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip>
29294 12:33:18.660933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip
29296 12:33:18.717288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip>
29297 12:33:18.717684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip
29299 12:33:18.776461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass
29301 12:33:18.776923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass>
29302 12:33:18.836312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip
29304 12:33:18.836762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip>
29305 12:33:18.895007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip>
29306 12:33:18.895430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip
29308 12:33:18.952439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass
29310 12:33:18.952819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass>
29311 12:33:19.009497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip>
29312 12:33:19.009930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip
29314 12:33:19.068594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip>
29315 12:33:19.069023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip
29317 12:33:19.127728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass>
29318 12:33:19.128180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass
29320 12:33:19.185095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip>
29321 12:33:19.185611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip
29323 12:33:19.243347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip>
29324 12:33:19.243778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip
29326 12:33:19.300595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass>
29327 12:33:19.301109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass
29329 12:33:19.359548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip
29331 12:33:19.360031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip>
29332 12:33:19.418187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip
29334 12:33:19.418632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip>
29335 12:33:19.477145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass
29337 12:33:19.477624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass>
29338 12:33:19.535884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip>
29339 12:33:19.536460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip
29341 12:33:19.594319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip
29343 12:33:19.595094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip>
29344 12:33:19.636945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass>
29345 12:33:19.637352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass
29347 12:33:19.683347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip>
29348 12:33:19.683809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip
29350 12:33:19.731543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip
29352 12:33:19.732040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip>
29353 12:33:19.772424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass>
29354 12:33:19.772840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass
29356 12:33:19.813887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip>
29357 12:33:19.814311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip
29359 12:33:19.856360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip>
29360 12:33:19.856751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip
29362 12:33:19.907792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass>
29363 12:33:19.908250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass
29365 12:33:19.955315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip>
29366 12:33:19.955817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip
29368 12:33:20.001156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip>
29369 12:33:20.001634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip
29371 12:33:20.048058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass
29373 12:33:20.048572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass>
29374 12:33:20.100004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip
29376 12:33:20.100412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip>
29377 12:33:20.154816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip>
29378 12:33:20.155277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip
29380 12:33:20.204231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass>
29381 12:33:20.204680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass
29383 12:33:20.256820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip>
29384 12:33:20.257269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip
29386 12:33:20.308699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip>
29387 12:33:20.309089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip
29389 12:33:20.359484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass
29391 12:33:20.360087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass>
29392 12:33:20.399242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip>
29393 12:33:20.399655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip
29395 12:33:20.439298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip>
29396 12:33:20.439708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip
29398 12:33:20.478210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass
29400 12:33:20.478731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass>
29401 12:33:20.519427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip
29403 12:33:20.519892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip>
29404 12:33:20.567809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip>
29405 12:33:20.568256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip
29407 12:33:20.625554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass>
29408 12:33:20.626029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass
29410 12:33:20.680358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip>
29411 12:33:20.680715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip
29413 12:33:20.724889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip>
29414 12:33:20.725308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip
29416 12:33:20.765576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass>
29417 12:33:20.766013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass
29419 12:33:20.808454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip>
29420 12:33:20.808897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip
29422 12:33:20.853583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip>
29423 12:33:20.854020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip
29425 12:33:20.899170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass
29427 12:33:20.899647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass>
29428 12:33:20.936473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip>
29429 12:33:20.936905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip
29431 12:33:20.981661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip
29433 12:33:20.982157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip>
29434 12:33:21.028117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass
29436 12:33:21.028606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass>
29437 12:33:21.077775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip>
29438 12:33:21.078228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip
29440 12:33:21.120361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip>
29441 12:33:21.120752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip
29443 12:33:21.161033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass
29445 12:33:21.161729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass>
29446 12:33:21.203140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip
29448 12:33:21.203868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip>
29449 12:33:21.246308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip
29451 12:33:21.246996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip>
29452 12:33:21.290361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass>
29453 12:33:21.290834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass
29455 12:33:21.336052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip>
29456 12:33:21.336489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip
29458 12:33:21.391093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip>
29459 12:33:21.391563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip
29461 12:33:21.435743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass>
29462 12:33:21.436135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass
29464 12:33:21.483377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip
29466 12:33:21.483853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip>
29467 12:33:21.533691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip
29469 12:33:21.534197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip>
29470 12:33:21.587591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass
29472 12:33:21.588151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass>
29473 12:33:21.634336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip
29475 12:33:21.634806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip>
29476 12:33:21.677988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip>
29477 12:33:21.678428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip
29479 12:33:21.723808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass
29481 12:33:21.724267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass>
29482 12:33:21.763995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip>
29483 12:33:21.764433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip
29485 12:33:21.804948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip
29487 12:33:21.805408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip>
29488 12:33:21.841829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass
29490 12:33:21.842270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass>
29491 12:33:21.895684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip>
29492 12:33:21.896125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip
29494 12:33:21.940973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip>
29495 12:33:21.941396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip
29497 12:33:21.988821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass
29499 12:33:21.989294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass>
29500 12:33:22.040000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip>
29501 12:33:22.040400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip
29503 12:33:22.088404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip
29505 12:33:22.088888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip>
29506 12:33:22.135100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass>
29507 12:33:22.135698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass
29509 12:33:22.183018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip
29511 12:33:22.183782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip>
29512 12:33:22.226043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip
29514 12:33:22.226466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip>
29515 12:33:22.265574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass
29517 12:33:22.266031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass>
29518 12:33:22.305320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip>
29519 12:33:22.305750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip
29521 12:33:22.349671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip>
29522 12:33:22.350127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip
29524 12:33:22.400692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass>
29525 12:33:22.401131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass
29527 12:33:22.448002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip
29529 12:33:22.448443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip>
29530 12:33:22.495493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip
29532 12:33:22.495937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip>
29533 12:33:22.542354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass
29535 12:33:22.542769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass>
29536 12:33:22.588478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip>
29537 12:33:22.588872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip
29539 12:33:22.644417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip>
29540 12:33:22.644918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip
29542 12:33:22.689698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass
29544 12:33:22.690142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass>
29545 12:33:22.741295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip>
29546 12:33:22.741682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip
29548 12:33:22.821758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip>
29549 12:33:22.822337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip
29551 12:33:22.865946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass>
29552 12:33:22.866379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass
29554 12:33:22.912511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip>
29555 12:33:22.912969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip
29557 12:33:22.957415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip>
29558 12:33:22.957855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip
29560 12:33:23.004814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass>
29561 12:33:23.005243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass
29563 12:33:23.050921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip>
29564 12:33:23.051375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip
29566 12:33:23.092985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip
29568 12:33:23.093409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip>
29569 12:33:23.136812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass
29571 12:33:23.137303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass>
29572 12:33:23.182942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip>
29573 12:33:23.183371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip
29575 12:33:23.229785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip>
29576 12:33:23.230240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip
29578 12:33:23.277929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass
29580 12:33:23.278419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass>
29581 12:33:23.318842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip>
29582 12:33:23.319247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip
29584 12:33:23.365491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip>
29585 12:33:23.365939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip
29587 12:33:23.411246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass>
29588 12:33:23.411687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass
29590 12:33:23.459990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip>
29591 12:33:23.460385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip
29593 12:33:23.505613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip
29595 12:33:23.506113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip>
29596 12:33:23.552535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass
29598 12:33:23.552944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass>
29599 12:33:23.601401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip
29601 12:33:23.601844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip>
29602 12:33:23.653723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip
29604 12:33:23.654207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip>
29605 12:33:23.708964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass
29607 12:33:23.709741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass>
29608 12:33:23.763839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip
29610 12:33:23.764529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip>
29611 12:33:23.814246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip
29613 12:33:23.814719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip>
29614 12:33:23.867698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass
29616 12:33:23.868359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass>
29617 12:33:23.916387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip
29619 12:33:23.916863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip>
29620 12:33:23.958196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip
29622 12:33:23.958663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip>
29623 12:33:24.003039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass>
29624 12:33:24.003629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass
29626 12:33:24.051888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip>
29627 12:33:24.052335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip
29629 12:33:24.099918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip>
29630 12:33:24.100447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip
29632 12:33:24.138192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass
29634 12:33:24.138624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass>
29635 12:33:24.183013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip>
29636 12:33:24.183401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip
29638 12:33:24.224962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip>
29639 12:33:24.225362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip
29641 12:33:24.268452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass
29643 12:33:24.268821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass>
29644 12:33:24.307658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip>
29645 12:33:24.308072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip
29647 12:33:24.353555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip>
29648 12:33:24.354028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip
29650 12:33:24.396333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass
29652 12:33:24.396801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass>
29653 12:33:24.435638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip
29655 12:33:24.436316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip>
29656 12:33:24.477845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip>
29657 12:33:24.478280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip
29659 12:33:24.527026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass>
29660 12:33:24.527415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass
29662 12:33:24.569083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip>
29663 12:33:24.569501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip
29665 12:33:24.617543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip>
29666 12:33:24.617957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip
29668 12:33:24.659067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass>
29669 12:33:24.659497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass
29671 12:33:24.711440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip>
29672 12:33:24.711921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip
29674 12:33:24.760868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip
29676 12:33:24.761366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip>
29677 12:33:24.809181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass>
29678 12:33:24.809632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass
29680 12:33:24.856464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip>
29681 12:33:24.856903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip
29683 12:33:24.899025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip>
29684 12:33:24.899523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip
29686 12:33:24.946837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass>
29687 12:33:24.947371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass
29689 12:33:24.988535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip>
29690 12:33:24.989048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip
29692 12:33:25.023856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip>
29693 12:33:25.024339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip
29695 12:33:25.059907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass
29697 12:33:25.060337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass>
29698 12:33:25.104602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip>
29699 12:33:25.105029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip
29701 12:33:25.147163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip>
29702 12:33:25.147589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip
29704 12:33:25.197365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass>
29705 12:33:25.197740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass
29707 12:33:25.252447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip>
29708 12:33:25.252923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip
29710 12:33:25.307627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip>
29711 12:33:25.308046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip
29713 12:33:25.362085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass
29715 12:33:25.362792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass>
29716 12:33:25.417737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip>
29717 12:33:25.418161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip
29719 12:33:25.473206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip>
29720 12:33:25.473708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip
29722 12:33:25.528273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass>
29723 12:33:25.528776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass
29725 12:33:25.584969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip>
29726 12:33:25.585368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip
29728 12:33:25.634407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip
29730 12:33:25.634885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip>
29731 12:33:25.681584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass>
29732 12:33:25.682047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass
29734 12:33:25.728648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip
29736 12:33:25.729118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip>
29737 12:33:25.775251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip>
29738 12:33:25.775689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip
29740 12:33:25.821785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass>
29741 12:33:25.822306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass
29743 12:33:25.869818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip>
29744 12:33:25.870241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip
29746 12:33:25.912342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip
29748 12:33:25.912817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip>
29749 12:33:25.956659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass>
29750 12:33:25.957057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass
29752 12:33:26.004060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip>
29753 12:33:26.004423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip
29755 12:33:26.057286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip>
29756 12:33:26.057689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip
29758 12:33:26.108048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass>
29759 12:33:26.108502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass
29761 12:33:26.156833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip>
29762 12:33:26.157229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip
29764 12:33:26.203323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip>
29765 12:33:26.203728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip
29767 12:33:26.249104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass
29769 12:33:26.249573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass>
29770 12:33:26.296604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip>
29771 12:33:26.297053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip
29773 12:33:26.336842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip
29775 12:33:26.337312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip>
29776 12:33:26.375153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass>
29777 12:33:26.375578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass
29779 12:33:26.421013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip>
29780 12:33:26.421472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip
29782 12:33:26.461821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip>
29783 12:33:26.462268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip
29785 12:33:26.507515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass>
29786 12:33:26.507944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass
29788 12:33:26.556246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip
29790 12:33:26.556679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip>
29791 12:33:26.599495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip
29793 12:33:26.599923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip>
29794 12:33:26.649956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass>
29795 12:33:26.650366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass
29797 12:33:26.695231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip>
29798 12:33:26.695616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip
29800 12:33:26.741661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip
29802 12:33:26.742292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip>
29803 12:33:26.787663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass
29805 12:33:26.788136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass>
29806 12:33:26.829954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip
29808 12:33:26.830432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip>
29809 12:33:26.874095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip
29811 12:33:26.874873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip>
29812 12:33:26.930971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass>
29813 12:33:26.931407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass
29815 12:33:26.981772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip
29817 12:33:26.982244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip>
29818 12:33:27.023772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip>
29819 12:33:27.024231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip
29821 12:33:27.067341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass
29823 12:33:27.067821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass>
29824 12:33:27.109284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip>
29825 12:33:27.109687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip
29827 12:33:27.156023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip>
29828 12:33:27.156411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip
29830 12:33:27.201592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass>
29831 12:33:27.202065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass
29833 12:33:27.249215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip
29835 12:33:27.249706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip>
29836 12:33:27.296346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip>
29837 12:33:27.297191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip
29839 12:33:27.340148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass>
29840 12:33:27.340571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass
29842 12:33:27.381893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip
29844 12:33:27.382283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip>
29845 12:33:27.424421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip>
29846 12:33:27.424878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip
29848 12:33:27.465643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass>
29849 12:33:27.466016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass
29851 12:33:27.519714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip>
29852 12:33:27.520131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip
29854 12:33:27.563633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip
29856 12:33:27.564349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip>
29857 12:33:27.609261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass>
29858 12:33:27.609766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass
29860 12:33:27.654956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip>
29861 12:33:27.655359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip
29863 12:33:27.696578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip
29865 12:33:27.696960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip>
29866 12:33:27.741347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass>
29867 12:33:27.741737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass
29869 12:33:27.784702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip>
29870 12:33:27.785097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip
29872 12:33:27.825663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip>
29873 12:33:27.826159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip
29875 12:33:27.865580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass
29877 12:33:27.866083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass>
29878 12:33:27.923405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip>
29879 12:33:27.923849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip
29881 12:33:27.971584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip>
29882 12:33:27.972029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip
29884 12:33:28.023786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass>
29885 12:33:28.024311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass
29887 12:33:28.066850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip>
29888 12:33:28.067246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip
29890 12:33:28.109403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip
29892 12:33:28.109909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip>
29893 12:33:28.156018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass>
29894 12:33:28.156422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass
29896 12:33:28.199078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip
29898 12:33:28.199476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip>
29899 12:33:28.240816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip>
29900 12:33:28.241270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip
29902 12:33:28.293170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass>
29903 12:33:28.293716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass
29905 12:33:28.347741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip>
29906 12:33:28.348194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip
29908 12:33:28.395667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip>
29909 12:33:28.396121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip
29911 12:33:28.447637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass>
29912 12:33:28.448043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass
29914 12:33:28.495757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip>
29915 12:33:28.496155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip
29917 12:33:28.535782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip>
29918 12:33:28.536225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip
29920 12:33:28.577367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass>
29921 12:33:28.577833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass
29923 12:33:28.618186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip
29925 12:33:28.618758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip>
29926 12:33:28.660353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip>
29927 12:33:28.660738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip
29929 12:33:28.707025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass>
29930 12:33:28.707435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass
29932 12:33:28.755023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip>
29933 12:33:28.755491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip
29935 12:33:28.802147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip
29937 12:33:28.802603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip>
29938 12:33:28.845526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass>
29939 12:33:28.845937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass
29941 12:33:28.895980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip>
29942 12:33:28.896401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip
29944 12:33:28.942223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip
29946 12:33:28.942684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip>
29947 12:33:28.985328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass>
29948 12:33:28.985739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass
29950 12:33:29.024820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip>
29951 12:33:29.025268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip
29953 12:33:29.063000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip>
29954 12:33:29.063442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip
29956 12:33:29.105458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass>
29957 12:33:29.105893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass
29959 12:33:29.149020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip>
29960 12:33:29.149473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip
29962 12:33:29.197367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip>
29963 12:33:29.197769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip
29965 12:33:29.243526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass
29967 12:33:29.243958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass>
29968 12:33:29.287031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip>
29969 12:33:29.287460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip
29971 12:33:29.329720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip>
29972 12:33:29.330140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip
29974 12:33:29.373921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass
29976 12:33:29.374391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass>
29977 12:33:29.420926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip
29979 12:33:29.421414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip>
29980 12:33:29.467213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip>
29981 12:33:29.467647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip
29983 12:33:29.519020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass>
29984 12:33:29.519407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass
29986 12:33:29.556437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip>
29987 12:33:29.556824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip
29989 12:33:29.601148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip>
29990 12:33:29.601588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip
29992 12:33:29.643296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass>
29993 12:33:29.643759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass
29995 12:33:29.689813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip>
29996 12:33:29.690281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip
29998 12:33:29.736228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip>
29999 12:33:29.736672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip
30001 12:33:29.784828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass
30003 12:33:29.785306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass>
30004 12:33:29.831690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip>
30005 12:33:29.832110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip
30007 12:33:29.877918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip>
30008 12:33:29.878315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip
30010 12:33:29.927978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass
30012 12:33:29.928401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass>
30013 12:33:29.971105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip>
30014 12:33:29.971550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip
30016 12:33:30.014002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip
30018 12:33:30.014457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip>
30019 12:33:30.061211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass>
30020 12:33:30.061694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass
30022 12:33:30.108900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip>
30023 12:33:30.109365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip
30025 12:33:30.152678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip>
30026 12:33:30.153122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip
30028 12:33:30.199860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass>
30029 12:33:30.200319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass
30031 12:33:30.243896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip>
30032 12:33:30.244286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip
30034 12:33:30.291689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip>
30035 12:33:30.292140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip
30037 12:33:30.332028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass
30039 12:33:30.332517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass>
30040 12:33:30.371888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip>
30041 12:33:30.372379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip
30043 12:33:30.416586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip>
30044 12:33:30.416952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip
30046 12:33:30.456636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass>
30047 12:33:30.457059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass
30049 12:33:30.500773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip>
30050 12:33:30.501227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip
30052 12:33:30.544883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip>
30053 12:33:30.545303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip
30055 12:33:30.591354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass>
30056 12:33:30.591805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass
30058 12:33:30.644419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip
30060 12:33:30.644847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip>
30061 12:33:30.699408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip>
30062 12:33:30.699847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip
30064 12:33:30.740488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass>
30065 12:33:30.740879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass
30067 12:33:30.788716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip
30069 12:33:30.789120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip>
30070 12:33:30.836301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip>
30071 12:33:30.836803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip
30073 12:33:30.883989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass
30075 12:33:30.884465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass>
30076 12:33:30.931986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip>
30077 12:33:30.932411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip
30079 12:33:30.979788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip
30081 12:33:30.980273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip>
30082 12:33:31.023877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass
30084 12:33:31.024280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass>
30085 12:33:31.072444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip>
30086 12:33:31.072880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip
30088 12:33:31.118372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip
30090 12:33:31.118836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip>
30091 12:33:31.160378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass>
30092 12:33:31.160821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass
30094 12:33:31.206541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip>
30095 12:33:31.207004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip
30097 12:33:31.251388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip>
30098 12:33:31.251915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip
30100 12:33:31.295114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass>
30101 12:33:31.295580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass
30103 12:33:31.343423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip>
30104 12:33:31.343811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip
30106 12:33:31.389360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip>
30107 12:33:31.389770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip
30109 12:33:31.432891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass
30111 12:33:31.433340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass>
30112 12:33:31.481810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip
30114 12:33:31.482298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip>
30115 12:33:31.533487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip>
30116 12:33:31.533941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip
30118 12:33:31.578959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass>
30119 12:33:31.579425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass
30121 12:33:31.625908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip>
30122 12:33:31.626337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip
30124 12:33:31.676250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip>
30125 12:33:31.676685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip
30127 12:33:31.732134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass>
30128 12:33:31.732601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass
30130 12:33:31.785447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip>
30131 12:33:31.785914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip
30133 12:33:31.829077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip>
30134 12:33:31.829523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip
30136 12:33:31.874702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass>
30137 12:33:31.875150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass
30139 12:33:31.931751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip>
30140 12:33:31.932169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip
30142 12:33:31.972949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip>
30143 12:33:31.973365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip
30145 12:33:32.024462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass>
30146 12:33:32.024931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass
30148 12:33:32.080841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip>
30149 12:33:32.081223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip
30151 12:33:32.137175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip>
30152 12:33:32.137620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip
30154 12:33:32.185241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass
30156 12:33:32.185739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass>
30157 12:33:32.231183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip>
30158 12:33:32.231748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip
30160 12:33:32.269604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip
30162 12:33:32.270086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip>
30163 12:33:32.311274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass>
30164 12:33:32.311695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass
30166 12:33:32.357144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip
30168 12:33:32.357626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip>
30169 12:33:32.404000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip
30171 12:33:32.404627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip>
30172 12:33:32.449850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass
30174 12:33:32.450451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass>
30175 12:33:32.492892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip>
30176 12:33:32.493365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip
30178 12:33:32.532332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip>
30179 12:33:32.532750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip
30181 12:33:32.581395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass>
30182 12:33:32.581858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass
30184 12:33:32.624221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip>
30185 12:33:32.624664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip
30187 12:33:32.672155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip>
30188 12:33:32.672575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip
30190 12:33:32.717925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass
30192 12:33:32.718415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass>
30193 12:33:32.768059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip>
30194 12:33:32.768480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip
30196 12:33:32.805824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip>
30197 12:33:32.806257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip
30199 12:33:32.847541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass>
30200 12:33:32.847969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass
30202 12:33:32.899040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip
30204 12:33:32.899466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip>
30205 12:33:32.956548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip>
30206 12:33:32.956947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip
30208 12:33:33.037822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass>
30209 12:33:33.038217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass
30211 12:33:33.084948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip
30213 12:33:33.085435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip>
30214 12:33:33.129035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip
30216 12:33:33.129507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip>
30217 12:33:33.168717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass>
30218 12:33:33.169162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass
30220 12:33:33.209670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip>
30221 12:33:33.210092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip
30223 12:33:33.256819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip>
30224 12:33:33.257252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip
30226 12:33:33.296412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass
30228 12:33:33.296839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass>
30229 12:33:33.347862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip>
30230 12:33:33.348282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip
30232 12:33:33.400842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip>
30233 12:33:33.401421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip
30235 12:33:33.448217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass>
30236 12:33:33.448679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass
30238 12:33:33.496596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip>
30239 12:33:33.497040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip
30241 12:33:33.541129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip>
30242 12:33:33.541563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip
30244 12:33:33.585458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass
30246 12:33:33.585857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass>
30247 12:33:33.629406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip>
30248 12:33:33.629855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip
30250 12:33:33.667424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip>
30251 12:33:33.667861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip
30253 12:33:33.708492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass>
30254 12:33:33.708931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass
30256 12:33:33.747416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip
30258 12:33:33.747909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip>
30259 12:33:33.793805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip>
30260 12:33:33.794306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip
30262 12:33:33.837824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass>
30263 12:33:33.838279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass
30265 12:33:33.877226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip>
30266 12:33:33.877738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip
30268 12:33:33.915743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip>
30269 12:33:33.916189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip
30271 12:33:33.954830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass>
30272 12:33:33.955277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass
30274 12:33:33.996987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip>
30275 12:33:33.997399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip
30277 12:33:34.040332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip>
30278 12:33:34.040739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip
30280 12:33:34.087132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass>
30281 12:33:34.087542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass
30283 12:33:34.140385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip
30285 12:33:34.141061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip>
30286 12:33:34.198890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip
30288 12:33:34.199668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip>
30289 12:33:34.256468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass>
30290 12:33:34.257029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass
30292 12:33:34.315953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip
30294 12:33:34.316629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip>
30295 12:33:34.361042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip>
30296 12:33:34.361474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip
30298 12:33:34.409456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass
30300 12:33:34.409879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass>
30301 12:33:34.456708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip>
30302 12:33:34.457195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip
30304 12:33:34.502765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip>
30305 12:33:34.503153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip
30307 12:33:34.546856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass>
30308 12:33:34.547299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass
30310 12:33:34.590220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip
30312 12:33:34.590686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip>
30313 12:33:34.633062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip>
30314 12:33:34.633505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip
30316 12:33:34.675790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass>
30317 12:33:34.676225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass
30319 12:33:34.726007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip
30321 12:33:34.726490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip>
30322 12:33:34.776441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip>
30323 12:33:34.776856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip
30325 12:33:34.839449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass>
30326 12:33:34.839919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass
30328 12:33:34.901948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip
30330 12:33:34.902423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip>
30331 12:33:34.961202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip
30333 12:33:34.961629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip>
30334 12:33:35.019071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass>
30335 12:33:35.019550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass
30337 12:33:35.076073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip>
30338 12:33:35.076481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip
30340 12:33:35.136109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip
30342 12:33:35.136605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip>
30343 12:33:35.193410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass>
30344 12:33:35.193821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass
30346 12:33:35.252321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip
30348 12:33:35.252750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip>
30349 12:33:35.307632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip>
30350 12:33:35.308074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip
30352 12:33:35.362981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass>
30353 12:33:35.363418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass
30355 12:33:35.419660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip
30357 12:33:35.420152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip>
30358 12:33:35.476871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip>
30359 12:33:35.477309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip
30361 12:33:35.527605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass>
30362 12:33:35.527967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass
30364 12:33:35.570989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip>
30365 12:33:35.571547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip
30367 12:33:35.621713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip>
30368 12:33:35.622147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip
30370 12:33:35.670690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass
30372 12:33:35.671156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass>
30373 12:33:35.720576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip>
30374 12:33:35.720987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip
30376 12:33:35.764813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip>
30377 12:33:35.765203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip
30379 12:33:35.809050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass>
30380 12:33:35.809489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass
30382 12:33:35.848507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip>
30383 12:33:35.848910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip
30385 12:33:35.887414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip>
30386 12:33:35.887809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip
30388 12:33:35.933439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass>
30389 12:33:35.933835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass
30391 12:33:35.977383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip>
30392 12:33:35.977875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip
30394 12:33:36.028056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip>
30395 12:33:36.028433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip
30397 12:33:36.068227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass>
30398 12:33:36.068611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass
30400 12:33:36.117637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip>
30401 12:33:36.118064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip
30403 12:33:36.153889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip>
30404 12:33:36.154586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip
30406 12:33:36.204876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass>
30407 12:33:36.205360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass
30409 12:33:36.258161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip
30411 12:33:36.258644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip>
30412 12:33:36.303761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip>
30413 12:33:36.304198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip
30415 12:33:36.344305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass>
30416 12:33:36.344708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass
30418 12:33:36.381032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip>
30419 12:33:36.381466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip
30421 12:33:36.423473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip>
30422 12:33:36.423975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip
30424 12:33:36.463285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass
30426 12:33:36.463894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass>
30427 12:33:36.500462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip>
30428 12:33:36.500911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip
30430 12:33:36.541504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip
30432 12:33:36.541940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip>
30433 12:33:36.583155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass>
30434 12:33:36.583519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass
30436 12:33:36.624562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip>
30437 12:33:36.624976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip
30439 12:33:36.661542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip>
30440 12:33:36.662007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip
30442 12:33:36.709127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass>
30443 12:33:36.709584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass
30445 12:33:36.759682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip
30447 12:33:36.760167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip>
30448 12:33:36.804951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip>
30449 12:33:36.805439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip
30451 12:33:36.852018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass>
30452 12:33:36.852495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass
30454 12:33:36.909097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip>
30455 12:33:36.909551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip
30457 12:33:36.964470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip>
30458 12:33:36.964939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip
30460 12:33:37.020168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass>
30461 12:33:37.020683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass
30463 12:33:37.065429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip>
30464 12:33:37.065858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip
30466 12:33:37.116909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip
30468 12:33:37.117301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip>
30469 12:33:37.163825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass
30471 12:33:37.164605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass>
30472 12:33:37.203758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip
30474 12:33:37.204241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip>
30475 12:33:37.243248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip>
30476 12:33:37.243704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip
30478 12:33:37.283026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass
30480 12:33:37.283509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass>
30481 12:33:37.321892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip>
30482 12:33:37.322287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip
30484 12:33:37.361380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip>
30485 12:33:37.361914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip
30487 12:33:37.403596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass>
30488 12:33:37.404040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass
30490 12:33:37.445512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip>
30491 12:33:37.445940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip
30493 12:33:37.487483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip>
30494 12:33:37.487934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip
30496 12:33:37.528405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass>
30497 12:33:37.528856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass
30499 12:33:37.567702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip>
30500 12:33:37.568158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip
30502 12:33:37.616736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip>
30503 12:33:37.617127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip
30505 12:33:37.665173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass>
30506 12:33:37.665585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass
30508 12:33:37.704121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip>
30509 12:33:37.704563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip
30511 12:33:37.746894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip>
30512 12:33:37.747341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip
30514 12:33:37.787082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass
30516 12:33:37.787786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass>
30517 12:33:37.836611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip>
30518 12:33:37.837032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip
30520 12:33:37.874945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip>
30521 12:33:37.875361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip
30523 12:33:37.921432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass
30525 12:33:37.921822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass>
30526 12:33:37.968175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip>
30527 12:33:37.968605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip
30529 12:33:38.013694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip>
30530 12:33:38.014150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip
30532 12:33:38.058770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass>
30533 12:33:38.059218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass
30535 12:33:38.115798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip>
30536 12:33:38.116361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip
30538 12:33:38.173588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip>
30539 12:33:38.173992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip
30541 12:33:38.221410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass
30543 12:33:38.222179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass>
30544 12:33:38.265596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip>
30545 12:33:38.266075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip
30547 12:33:38.307361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip>
30548 12:33:38.307757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip
30550 12:33:38.347813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass
30552 12:33:38.348248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass>
30553 12:33:38.394189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip
30555 12:33:38.394671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip>
30556 12:33:38.449582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip>
30557 12:33:38.449972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip
30559 12:33:38.501669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass
30561 12:33:38.502307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass>
30562 12:33:38.541553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip
30564 12:33:38.542008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip>
30565 12:33:38.581715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip
30567 12:33:38.582423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip>
30568 12:33:38.620047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass>
30569 12:33:38.620470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass
30571 12:33:38.657939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip>
30572 12:33:38.658382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip
30574 12:33:38.701834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip>
30575 12:33:38.702225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip
30577 12:33:38.744271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass>
30578 12:33:38.744704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass
30580 12:33:38.788598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip>
30581 12:33:38.789021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip
30583 12:33:38.828591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip>
30584 12:33:38.829032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip
30586 12:33:38.867772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass>
30587 12:33:38.868233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass
30589 12:33:38.925175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip>
30590 12:33:38.925699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip
30592 12:33:38.964956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip>
30593 12:33:38.965452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip
30595 12:33:39.003498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass
30597 12:33:39.004151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass>
30598 12:33:39.043509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip
30600 12:33:39.044180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip>
30601 12:33:39.083083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip>
30602 12:33:39.083593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip
30604 12:33:39.121935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass>
30605 12:33:39.122503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass
30607 12:33:39.160811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip>
30608 12:33:39.161327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip
30610 12:33:39.205899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip>
30611 12:33:39.206384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip
30613 12:33:39.248649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass
30615 12:33:39.249077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass>
30616 12:33:39.287989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip>
30617 12:33:39.288417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip
30619 12:33:39.328938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip
30621 12:33:39.329402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip>
30622 12:33:39.368775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass>
30623 12:33:39.369203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass
30625 12:33:39.412455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip>
30626 12:33:39.412891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip
30628 12:33:39.453243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip>
30629 12:33:39.453686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip
30631 12:33:39.497541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass
30633 12:33:39.497953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass>
30634 12:33:39.543500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip>
30635 12:33:39.543952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip
30637 12:33:39.585501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip
30639 12:33:39.585931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip>
30640 12:33:39.626169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass
30642 12:33:39.626630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass>
30643 12:33:39.665802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip>
30644 12:33:39.666159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip
30646 12:33:39.711362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip>
30647 12:33:39.711851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip
30649 12:33:39.749301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass>
30650 12:33:39.749687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass
30652 12:33:39.804087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip>
30653 12:33:39.804498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip
30655 12:33:39.847987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip>
30656 12:33:39.848390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip
30658 12:33:39.889269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass>
30659 12:33:39.889676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass
30661 12:33:39.933478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip
30663 12:33:39.934283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip>
30664 12:33:39.972318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip>
30665 12:33:39.972735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip
30667 12:33:40.016304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass>
30668 12:33:40.016734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass
30670 12:33:40.060899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip>
30671 12:33:40.061342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip
30673 12:33:40.113979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip>
30674 12:33:40.114480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip
30676 12:33:40.155937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass>
30677 12:33:40.156417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass
30679 12:33:40.198935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip>
30680 12:33:40.199369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip
30682 12:33:40.256938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip
30684 12:33:40.257625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip>
30685 12:33:40.305815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass>
30686 12:33:40.306361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass
30688 12:33:40.346320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip
30690 12:33:40.346794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip>
30691 12:33:40.385366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip>
30692 12:33:40.385803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip
30694 12:33:40.425396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass
30696 12:33:40.425900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass>
30697 12:33:40.472679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip
30699 12:33:40.473147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip>
30700 12:33:40.516333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip
30702 12:33:40.516791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip>
30703 12:33:40.559746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass>
30704 12:33:40.560202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass
30706 12:33:40.603009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip>
30707 12:33:40.603460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip
30709 12:33:40.657746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip>
30710 12:33:40.658221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip
30712 12:33:40.706668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass>
30713 12:33:40.707129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass
30715 12:33:40.758263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip
30717 12:33:40.758701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip>
30718 12:33:40.804488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip
30720 12:33:40.804986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip>
30721 12:33:40.842881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass
30723 12:33:40.843333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass>
30724 12:33:40.882676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip>
30725 12:33:40.883147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip
30727 12:33:40.924213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip>
30728 12:33:40.924741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip
30730 12:33:40.975160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass
30732 12:33:40.975633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass>
30733 12:33:41.014173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip
30735 12:33:41.014650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip>
30736 12:33:41.057782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip>
30737 12:33:41.058205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip
30739 12:33:41.095068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass>
30740 12:33:41.095465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass
30742 12:33:41.148925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip>
30743 12:33:41.149362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip
30745 12:33:41.189300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip>
30746 12:33:41.189675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip
30748 12:33:41.233012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass
30750 12:33:41.233792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass>
30751 12:33:41.275285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip>
30752 12:33:41.275801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip
30754 12:33:41.318930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip>
30755 12:33:41.319336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip
30757 12:33:41.368408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass
30759 12:33:41.368822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass>
30760 12:33:41.410847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip
30762 12:33:41.411256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip>
30763 12:33:41.464430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip>
30764 12:33:41.464818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip
30766 12:33:41.508282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass
30768 12:33:41.508744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass>
30769 12:33:41.560507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip>
30770 12:33:41.560937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip
30772 12:33:41.619570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip>
30773 12:33:41.620026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip
30775 12:33:41.673564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass>
30776 12:33:41.674038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass
30778 12:33:41.716927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip>
30779 12:33:41.717382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip
30781 12:33:41.756063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip>
30782 12:33:41.756486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip
30784 12:33:41.803822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass
30786 12:33:41.804307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass>
30787 12:33:41.853642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip
30789 12:33:41.854128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip>
30790 12:33:41.914326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip
30792 12:33:41.914832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip>
30793 12:33:41.956494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass>
30794 12:33:41.956909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass
30796 12:33:41.997120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip>
30797 12:33:41.997713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip
30799 12:33:42.035564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip>
30800 12:33:42.036134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip
30802 12:33:42.077653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass>
30803 12:33:42.078079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass
30805 12:33:42.115312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip>
30806 12:33:42.115838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip
30808 12:33:42.156062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip>
30809 12:33:42.156684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip
30811 12:33:42.209219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass
30813 12:33:42.209699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass>
30814 12:33:42.258650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip>
30815 12:33:42.259032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip
30817 12:33:42.296870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip
30819 12:33:42.297347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip>
30820 12:33:42.337103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass>
30821 12:33:42.337696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass
30823 12:33:42.379545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip>
30824 12:33:42.379936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip
30826 12:33:42.419837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip>
30827 12:33:42.420395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip
30829 12:33:42.460746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass>
30830 12:33:42.461177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass
30832 12:33:42.500991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip>
30833 12:33:42.501483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip
30835 12:33:42.542927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip>
30836 12:33:42.543419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip
30838 12:33:42.588895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass
30840 12:33:42.589559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass>
30841 12:33:42.641662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip>
30842 12:33:42.642076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip
30844 12:33:42.692416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip
30846 12:33:42.692899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip>
30847 12:33:42.747378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass>
30848 12:33:42.747808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass
30850 12:33:42.793727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip>
30851 12:33:42.794167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip
30853 12:33:42.850200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip
30855 12:33:42.850646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip>
30856 12:33:42.889663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass
30858 12:33:42.890151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass>
30859 12:33:42.941368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip>
30860 12:33:42.941878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip
30862 12:33:42.984937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip>
30863 12:33:42.985426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip
30865 12:33:43.027916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass>
30866 12:33:43.028322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass
30868 12:33:43.081403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip>
30869 12:33:43.081762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip
30871 12:33:43.130139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip
30873 12:33:43.130722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip>
30874 12:33:43.167853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass
30876 12:33:43.168236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass>
30877 12:33:43.210642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip
30879 12:33:43.211035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip>
30880 12:33:43.275783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip>
30881 12:33:43.276224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip
30883 12:33:43.322585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass>
30884 12:33:43.323085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass
30886 12:33:43.367771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip>
30887 12:33:43.368245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip
30889 12:33:43.417309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip
30891 12:33:43.417791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip>
30892 12:33:43.475582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass>
30893 12:33:43.476008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass
30895 12:33:43.519018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip>
30896 12:33:43.519481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip
30898 12:33:43.558742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip
30900 12:33:43.559510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip>
30901 12:33:43.598126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass
30903 12:33:43.598684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass>
30904 12:33:43.645371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip
30906 12:33:43.646153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip>
30907 12:33:43.687862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip>
30908 12:33:43.688249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip
30910 12:33:43.725702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass>
30911 12:33:43.726117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass
30913 12:33:43.764243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip>
30914 12:33:43.764670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip
30916 12:33:43.804171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip
30918 12:33:43.804518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip>
30919 12:33:43.844589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass>
30920 12:33:43.845022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass
30922 12:33:43.888128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip
30924 12:33:43.888605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip>
30925 12:33:43.931338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip>
30926 12:33:43.931763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip
30928 12:33:43.969823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass
30930 12:33:43.970248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass>
30931 12:33:44.008656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip>
30932 12:33:44.009077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip
30934 12:33:44.048245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip>
30935 12:33:44.048686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip
30937 12:33:44.087046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass>
30938 12:33:44.087473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass
30940 12:33:44.128084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip>
30941 12:33:44.128481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip
30943 12:33:44.165786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip
30945 12:33:44.166176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip>
30946 12:33:44.209180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass>
30947 12:33:44.209594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass
30949 12:33:44.255205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip
30951 12:33:44.255639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip>
30952 12:33:44.292689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip
30954 12:33:44.293280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip>
30955 12:33:44.339862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass>
30956 12:33:44.340432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass
30958 12:33:44.377509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip>
30959 12:33:44.377942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip
30961 12:33:44.416772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip>
30962 12:33:44.417226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip
30964 12:33:44.456910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass
30966 12:33:44.457390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass>
30967 12:33:44.501806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip>
30968 12:33:44.502224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip
30970 12:33:44.542746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip>
30971 12:33:44.543173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip
30973 12:33:44.585792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass
30975 12:33:44.586263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass>
30976 12:33:44.633303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip>
30977 12:33:44.633816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip
30979 12:33:44.684004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip
30981 12:33:44.684661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip>
30982 12:33:44.724423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass>
30983 12:33:44.724901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass
30985 12:33:44.764062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip>
30986 12:33:44.764488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip
30988 12:33:44.808934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip
30990 12:33:44.809354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip>
30991 12:33:44.853466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass
30993 12:33:44.853946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass>
30994 12:33:44.897267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip>
30995 12:33:44.897715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip
30997 12:33:44.945015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip
30999 12:33:44.945457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip>
31000 12:33:44.982836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass>
31001 12:33:44.983231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass
31003 12:33:45.021577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip
31005 12:33:45.022055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip>
31006 12:33:45.065180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip>
31007 12:33:45.065604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip
31009 12:33:45.117213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass
31011 12:33:45.117633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass>
31012 12:33:45.172010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip>
31013 12:33:45.172477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip
31015 12:33:45.213818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip
31017 12:33:45.214617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip>
31018 12:33:45.257427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass
31020 12:33:45.258092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass>
31021 12:33:45.305576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip>
31022 12:33:45.306004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip
31024 12:33:45.352204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip>
31025 12:33:45.352678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip
31027 12:33:45.399746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass>
31028 12:33:45.400192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass
31030 12:33:45.448617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip
31032 12:33:45.449097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip>
31033 12:33:45.494733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip>
31034 12:33:45.495186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip
31036 12:33:45.543635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass
31038 12:33:45.544065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass>
31039 12:33:45.583634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip>
31040 12:33:45.584011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip
31042 12:33:45.623317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip>
31043 12:33:45.623815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip
31045 12:33:45.666160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass
31047 12:33:45.666556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass>
31048 12:33:45.711034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip>
31049 12:33:45.711439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip
31051 12:33:45.756105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip>
31052 12:33:45.756523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip
31054 12:33:45.799786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass>
31055 12:33:45.800214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass
31057 12:33:45.841281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip>
31058 12:33:45.841685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip
31060 12:33:45.881143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip
31062 12:33:45.881564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip>
31063 12:33:45.925001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass
31065 12:33:45.925400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass>
31066 12:33:45.964720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip>
31067 12:33:45.965117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip
31069 12:33:46.013261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip>
31070 12:33:46.013678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip
31072 12:33:46.070302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass
31074 12:33:46.070859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass>
31075 12:33:46.127002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip>
31076 12:33:46.127413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip
31078 12:33:46.183859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip
31080 12:33:46.184290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip>
31081 12:33:46.240131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass>
31082 12:33:46.240567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass
31084 12:33:46.289006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip>
31085 12:33:46.289462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip
31087 12:33:46.333105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip>
31088 12:33:46.333551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip
31090 12:33:46.373110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass>
31091 12:33:46.373700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass
31093 12:33:46.412167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip>
31094 12:33:46.412619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip
31096 12:33:46.451737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip
31098 12:33:46.452231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip>
31099 12:33:46.499585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass
31101 12:33:46.500057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass>
31102 12:33:46.545711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip>
31103 12:33:46.546142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip
31105 12:33:46.589403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip>
31106 12:33:46.589815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip
31108 12:33:46.635462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass>
31109 12:33:46.635873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass
31111 12:33:46.683491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip>
31112 12:33:46.683879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip
31114 12:33:46.721076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip
31116 12:33:46.721453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip>
31117 12:33:46.765277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass>
31118 12:33:46.765697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass
31120 12:33:46.806046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip
31122 12:33:46.806426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip>
31123 12:33:46.849157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip>
31124 12:33:46.849598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip
31126 12:33:46.897722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass
31128 12:33:46.898202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass>
31129 12:33:46.935032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip>
31130 12:33:46.935431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip
31132 12:33:46.971881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip>
31133 12:33:46.972304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip
31135 12:33:47.008668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass>
31136 12:33:47.009094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass
31138 12:33:47.047721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip>
31139 12:33:47.048214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip
31141 12:33:47.090791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip>
31142 12:33:47.091243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip
31144 12:33:47.139237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass
31146 12:33:47.139727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass>
31147 12:33:47.187559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip
31149 12:33:47.188034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip>
31150 12:33:47.236120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip>
31151 12:33:47.236542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip
31153 12:33:47.279681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass>
31154 12:33:47.280263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass
31156 12:33:47.316098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip
31158 12:33:47.316632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip>
31159 12:33:47.351846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip>
31160 12:33:47.352264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip
31162 12:33:47.387846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass>
31163 12:33:47.388337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass
31165 12:33:47.425495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip
31167 12:33:47.425975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip>
31168 12:33:47.465276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip
31170 12:33:47.465759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip>
31171 12:33:47.504141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass>
31172 12:33:47.504540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass
31174 12:33:47.543150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip>
31175 12:33:47.543578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip
31177 12:33:47.590792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip
31179 12:33:47.591165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip>
31180 12:33:47.635516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass
31182 12:33:47.636193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass>
31183 12:33:47.678326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip
31185 12:33:47.679061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip>
31186 12:33:47.719589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip>
31187 12:33:47.720029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip
31189 12:33:47.754838 <47>[ 379.376777] systemd-journald[105]: Sent WATCHDOG=1 notification.
31190 12:33:47.795520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass>
31191 12:33:47.795935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass
31193 12:33:47.840841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip>
31194 12:33:47.841288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip
31196 12:33:47.885530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip>
31197 12:33:47.885993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip
31199 12:33:47.927282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass
31201 12:33:47.927744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass>
31202 12:33:47.976125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip>
31203 12:33:47.976574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip
31205 12:33:48.025676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip
31207 12:33:48.026100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip>
31208 12:33:48.061007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass>
31209 12:33:48.061566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass
31211 12:33:48.100192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip>
31212 12:33:48.100626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip
31214 12:33:48.145328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip
31216 12:33:48.146072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip>
31217 12:33:48.193796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass
31219 12:33:48.194292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass>
31220 12:33:48.253004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip
31222 12:33:48.253511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip>
31223 12:33:48.291514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip
31225 12:33:48.291982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip>
31226 12:33:48.329859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass
31228 12:33:48.330320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass>
31229 12:33:48.386158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip
31231 12:33:48.386597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip>
31232 12:33:48.434694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip>
31233 12:33:48.435060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip
31235 12:33:48.483272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass
31237 12:33:48.483657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass>
31238 12:33:48.535534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip>
31239 12:33:48.535949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip
31241 12:33:48.575238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip
31243 12:33:48.575685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip>
31244 12:33:48.613858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass>
31245 12:33:48.614426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass
31247 12:33:48.657663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip>
31248 12:33:48.658210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip
31250 12:33:48.711806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip>
31251 12:33:48.712289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip
31253 12:33:48.759786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass
31255 12:33:48.760271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass>
31256 12:33:48.798684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip>
31257 12:33:48.799139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip
31259 12:33:48.840392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip>
31260 12:33:48.840836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip
31262 12:33:48.878711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass>
31263 12:33:48.879161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass
31265 12:33:48.916959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip>
31266 12:33:48.917414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip
31268 12:33:48.963909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip
31270 12:33:48.964375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip>
31271 12:33:49.003203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass>
31272 12:33:49.003643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass
31274 12:33:49.044041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip>
31275 12:33:49.044482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip
31277 12:33:49.083842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip>
31278 12:33:49.084284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip
31280 12:33:49.139784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass
31282 12:33:49.140201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass>
31283 12:33:49.196846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip
31285 12:33:49.197318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip>
31286 12:33:49.235508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip
31288 12:33:49.235978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip>
31289 12:33:49.276469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass
31291 12:33:49.277078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass>
31292 12:33:49.335484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip>
31293 12:33:49.335929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip
31295 12:33:49.389459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip
31297 12:33:49.390259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip>
31298 12:33:49.428113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass>
31299 12:33:49.428534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass
31301 12:33:49.474936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip>
31302 12:33:49.475382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip
31304 12:33:49.519864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip
31306 12:33:49.520337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip>
31307 12:33:49.569226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass>
31308 12:33:49.569725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass
31310 12:33:49.610845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip
31312 12:33:49.611334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip>
31313 12:33:49.657521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip
31315 12:33:49.658004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip>
31316 12:33:49.700185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass>
31317 12:33:49.700611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass
31319 12:33:49.741255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip>
31320 12:33:49.741653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip
31322 12:33:49.783781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip>
31323 12:33:49.784227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip
31325 12:33:49.831122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass>
31326 12:33:49.831519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass
31328 12:33:49.875672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip>
31329 12:33:49.876166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip
31331 12:33:49.933182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip>
31332 12:33:49.933569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip
31334 12:33:49.985642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass>
31335 12:33:49.986057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass
31337 12:33:50.036550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip>
31338 12:33:50.036978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip
31340 12:33:50.085520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip
31342 12:33:50.086191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip>
31343 12:33:50.128920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass
31345 12:33:50.129380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass>
31346 12:33:50.169835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip>
31347 12:33:50.170266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip
31349 12:33:50.217457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip
31351 12:33:50.218271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip>
31352 12:33:50.256095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass>
31353 12:33:50.256653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass
31355 12:33:50.297952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip>
31356 12:33:50.298428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip
31358 12:33:50.341696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip>
31359 12:33:50.342196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip
31361 12:33:50.383190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass>
31362 12:33:50.383592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass
31364 12:33:50.424042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip>
31365 12:33:50.424494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip
31367 12:33:50.464051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip>
31368 12:33:50.464491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip
31370 12:33:50.512102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass>
31371 12:33:50.512454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass
31373 12:33:50.549370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip
31375 12:33:50.549761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip>
31376 12:33:50.587494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip>
31377 12:33:50.587881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip
31379 12:33:50.624290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass
31381 12:33:50.624670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass>
31382 12:33:50.661435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip
31384 12:33:50.661909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip>
31385 12:33:50.700655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip>
31386 12:33:50.701061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip
31388 12:33:50.743360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass
31390 12:33:50.743832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass>
31391 12:33:50.800291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip>
31392 12:33:50.800728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip
31394 12:33:50.841743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip>
31395 12:33:50.842146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip
31397 12:33:50.880171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass
31399 12:33:50.880671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass>
31400 12:33:50.918880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip
31402 12:33:50.919305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip>
31403 12:33:50.960537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip
31405 12:33:50.961022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip>
31406 12:33:50.999935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass>
31407 12:33:51.000354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass
31409 12:33:51.037658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip>
31410 12:33:51.038094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip
31412 12:33:51.091697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip>
31413 12:33:51.092156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip
31415 12:33:51.131400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass>
31416 12:33:51.131842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass
31418 12:33:51.171502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip>
31419 12:33:51.171879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip
31421 12:33:51.211653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip>
31422 12:33:51.212004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip
31424 12:33:51.251616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass
31426 12:33:51.252106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass>
31427 12:33:51.288554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip>
31428 12:33:51.288981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip
31430 12:33:51.328267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip
31432 12:33:51.328743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip>
31433 12:33:51.366912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass
31435 12:33:51.367398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass>
31436 12:33:51.405064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip
31438 12:33:51.405452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip>
31439 12:33:51.444155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip>
31440 12:33:51.444669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip
31442 12:33:51.498014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass>
31443 12:33:51.498554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass
31445 12:33:51.536277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip>
31446 12:33:51.536673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip
31448 12:33:51.576573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip
31450 12:33:51.577058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip>
31451 12:33:51.619516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass
31453 12:33:51.620011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass>
31454 12:33:51.659251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip>
31455 12:33:51.659655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip
31457 12:33:51.700377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip>
31458 12:33:51.700761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip
31460 12:33:51.751802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass>
31461 12:33:51.752274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass
31463 12:33:51.796345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip
31465 12:33:51.796783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip>
31466 12:33:51.840134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip
31468 12:33:51.840559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip>
31469 12:33:51.883978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass
31471 12:33:51.884458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass>
31472 12:33:51.923894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip>
31473 12:33:51.924338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip
31475 12:33:51.964110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip
31477 12:33:51.964648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip>
31478 12:33:52.007238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass>
31479 12:33:52.007691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass
31481 12:33:52.057796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip
31483 12:33:52.058281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip>
31484 12:33:52.096169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip>
31485 12:33:52.096642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip
31487 12:33:52.139115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass>
31488 12:33:52.139658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass
31490 12:33:52.174621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip>
31491 12:33:52.175049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip
31493 12:33:52.226385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip
31495 12:33:52.226993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip>
31496 12:33:52.268456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass
31498 12:33:52.269182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass>
31499 12:33:52.307743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip
31501 12:33:52.308189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip>
31502 12:33:52.351630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip>
31503 12:33:52.352162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip
31505 12:33:52.395906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass>
31506 12:33:52.396316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass
31508 12:33:52.440954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip>
31509 12:33:52.441394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip
31511 12:33:52.481014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip>
31512 12:33:52.481389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip
31514 12:33:52.520372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass>
31515 12:33:52.520955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass
31517 12:33:52.560934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip
31519 12:33:52.561403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip>
31520 12:33:52.603636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip>
31521 12:33:52.604069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip
31523 12:33:52.647217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass
31525 12:33:52.647700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass>
31526 12:33:52.690827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip>
31527 12:33:52.691379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip
31529 12:33:52.729605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip
31531 12:33:52.730197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip>
31532 12:33:52.775931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass
31534 12:33:52.776423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass>
31535 12:33:52.816347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip
31537 12:33:52.816831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip>
31538 12:33:52.859304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip>
31539 12:33:52.859761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip
31541 12:33:52.898967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass>
31542 12:33:52.899380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass
31544 12:33:52.937688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip>
31545 12:33:52.938165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip
31547 12:33:52.976700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip>
31548 12:33:52.977125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip
31550 12:33:53.014663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass>
31551 12:33:53.015126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass
31553 12:33:53.052565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip
31555 12:33:53.052986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip>
31556 12:33:53.094804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip>
31557 12:33:53.095266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip
31559 12:33:53.132487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass>
31560 12:33:53.132939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass
31562 12:33:53.170833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip>
31563 12:33:53.171311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip
31565 12:33:53.212359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip>
31566 12:33:53.212783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip
31568 12:33:53.250125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass
31570 12:33:53.250539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass>
31571 12:33:53.290009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip
31573 12:33:53.290819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip>
31574 12:33:53.338994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip>
31575 12:33:53.339479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip
31577 12:33:53.383809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass
31579 12:33:53.384186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass>
31580 12:33:53.428417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip>
31581 12:33:53.428828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip
31583 12:33:53.510803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip>
31584 12:33:53.511185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip
31586 12:33:53.567371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass>
31587 12:33:53.567732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass
31589 12:33:53.615490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip>
31590 12:33:53.615912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip
31592 12:33:53.670298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip
31594 12:33:53.670724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip>
31595 12:33:53.719551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass>
31596 12:33:53.719991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass
31598 12:33:53.772102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip>
31599 12:33:53.772504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip
31601 12:33:53.816920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip>
31602 12:33:53.817377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip
31604 12:33:53.860322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass>
31605 12:33:53.860751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass
31607 12:33:53.919717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip>
31608 12:33:53.920083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip
31610 12:33:53.968421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip>
31611 12:33:53.968832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip
31613 12:33:54.009122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass>
31614 12:33:54.009611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass
31616 12:33:54.057004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip>
31617 12:33:54.057377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip
31619 12:33:54.111672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip>
31620 12:33:54.112108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip
31622 12:33:54.155939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass
31624 12:33:54.156319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass>
31625 12:33:54.203626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip>
31626 12:33:54.204064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip
31628 12:33:54.257009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip>
31629 12:33:54.257393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip
31631 12:33:54.308884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass>
31632 12:33:54.309317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass
31634 12:33:54.354065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip
31636 12:33:54.354545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip>
31637 12:33:54.412105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip
31639 12:33:54.412570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip>
31640 12:33:54.450140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass
31642 12:33:54.450570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass>
31643 12:33:54.488919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip>
31644 12:33:54.489361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip
31646 12:33:54.528506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip>
31647 12:33:54.529072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip
31649 12:33:54.566517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass>
31650 12:33:54.566970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass
31652 12:33:54.603873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip>
31653 12:33:54.604314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip
31655 12:33:54.639808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip>
31656 12:33:54.640232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip
31658 12:33:54.676611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass>
31659 12:33:54.677171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass
31661 12:33:54.715900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip>
31662 12:33:54.716334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip
31664 12:33:54.756722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip
31666 12:33:54.757150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip>
31667 12:33:54.807114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass>
31668 12:33:54.807566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass
31670 12:33:54.848611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip
31672 12:33:54.848996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip>
31673 12:33:54.888685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip
31675 12:33:54.889102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip>
31676 12:33:54.929123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass>
31677 12:33:54.929547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass
31679 12:33:54.971227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip>
31680 12:33:54.971591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip
31682 12:33:55.012746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip>
31683 12:33:55.013135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip
31685 12:33:55.053107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass>
31686 12:33:55.053487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass
31688 12:33:55.091164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip>
31689 12:33:55.091586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip
31691 12:33:55.133344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip>
31692 12:33:55.133804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip
31694 12:33:55.172580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass>
31695 12:33:55.172965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass
31697 12:33:55.209910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip>
31698 12:33:55.210403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip
31700 12:33:55.260122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip
31702 12:33:55.260555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip>
31703 12:33:55.303392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass>
31704 12:33:55.303900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass
31706 12:33:55.339815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip>
31707 12:33:55.340215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip
31709 12:33:55.377068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip
31711 12:33:55.377546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip>
31712 12:33:55.415590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass>
31713 12:33:55.415999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass
31715 12:33:55.453577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip>
31716 12:33:55.454123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip
31718 12:33:55.498653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip>
31719 12:33:55.499097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip
31721 12:33:55.537406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass>
31722 12:33:55.537791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass
31724 12:33:55.585994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip
31726 12:33:55.586528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip>
31727 12:33:55.635475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip>
31728 12:33:55.635933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip
31730 12:33:55.673340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass>
31731 12:33:55.673771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass
31733 12:33:55.725275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip
31735 12:33:55.725774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip>
31736 12:33:55.765613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip
31738 12:33:55.766093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip>
31739 12:33:55.808860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass
31741 12:33:55.809316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass>
31742 12:33:55.853251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip>
31743 12:33:55.853666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip
31745 12:33:55.901630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip>
31746 12:33:55.902029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip
31748 12:33:55.946062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass>
31749 12:33:55.946504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass
31751 12:33:55.989844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip>
31752 12:33:55.990277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip
31754 12:33:56.037367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip>
31755 12:33:56.037756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip
31757 12:33:56.096434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass>
31758 12:33:56.096873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass
31760 12:33:56.135810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip>
31761 12:33:56.136239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip
31763 12:33:56.176349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip>
31764 12:33:56.176746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip
31766 12:33:56.219005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass
31768 12:33:56.219479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass>
31769 12:33:56.265059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip>
31770 12:33:56.265508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip
31772 12:33:56.320410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip>
31773 12:33:56.320985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip
31775 12:33:56.364143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass
31777 12:33:56.364607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass>
31778 12:33:56.409066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip
31780 12:33:56.409471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip>
31781 12:33:56.449918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip>
31782 12:33:56.450352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip
31784 12:33:56.488568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass
31786 12:33:56.488988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass>
31787 12:33:56.526951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip
31789 12:33:56.527440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip>
31790 12:33:56.576731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip>
31791 12:33:56.577288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip
31793 12:33:56.620962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass
31795 12:33:56.621380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass>
31796 12:33:56.659647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip>
31797 12:33:56.660194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip
31799 12:33:56.719165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip>
31800 12:33:56.719555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip
31802 12:33:56.766876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass
31804 12:33:56.767389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass>
31805 12:33:56.805800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip>
31806 12:33:56.806221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip
31808 12:33:56.843314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip>
31809 12:33:56.843759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip
31811 12:33:56.882868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass
31813 12:33:56.883356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass>
31814 12:33:56.927523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip>
31815 12:33:56.928111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip
31817 12:33:56.981966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip>
31818 12:33:56.982381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip
31820 12:33:57.023184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass>
31821 12:33:57.023548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass
31823 12:33:57.069741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip
31825 12:33:57.070225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip>
31826 12:33:57.120495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip
31828 12:33:57.120971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip>
31829 12:33:57.170234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass
31831 12:33:57.170704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass>
31832 12:33:57.214750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip
31834 12:33:57.215189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip>
31835 12:33:57.253598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip>
31836 12:33:57.254043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip
31838 12:33:57.294835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass>
31839 12:33:57.295243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass
31841 12:33:57.334907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip>
31842 12:33:57.335312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip
31844 12:33:57.376316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip
31846 12:33:57.376970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip>
31847 12:33:57.415909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass
31849 12:33:57.416404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass>
31850 12:33:57.459756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip>
31851 12:33:57.460197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip
31853 12:33:57.503505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip>
31854 12:33:57.503923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip
31856 12:33:57.553725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass>
31857 12:33:57.554157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass
31859 12:33:57.599445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip>
31860 12:33:57.599893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip
31862 12:33:57.651610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip>
31863 12:33:57.652037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip
31865 12:33:57.700453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass>
31866 12:33:57.700960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass
31868 12:33:57.749171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip>
31869 12:33:57.749685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip
31871 12:33:57.794403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip
31873 12:33:57.794875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip>
31874 12:33:57.839649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass>
31875 12:33:57.840118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass
31877 12:33:57.883641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip>
31878 12:33:57.884071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip
31880 12:33:57.921281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip>
31881 12:33:57.921780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip
31883 12:33:57.960143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass
31885 12:33:57.960722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass>
31886 12:33:58.002785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip>
31887 12:33:58.003168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip
31889 12:33:58.047190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip>
31890 12:33:58.047667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip
31892 12:33:58.092055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass>
31893 12:33:58.092530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass
31895 12:33:58.130889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip>
31896 12:33:58.131340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip
31898 12:33:58.168841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip>
31899 12:33:58.169270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip
31901 12:33:58.206594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass>
31902 12:33:58.207036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass
31904 12:33:58.248308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip>
31905 12:33:58.248721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip
31907 12:33:58.306872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip>
31908 12:33:58.307321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip
31910 12:33:58.349428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass>
31911 12:33:58.349858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass
31913 12:33:58.391410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip>
31914 12:33:58.391817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip
31916 12:33:58.433106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip
31918 12:33:58.433603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip>
31919 12:33:58.476650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass
31921 12:33:58.477076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass>
31922 12:33:58.516243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip
31924 12:33:58.516696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip>
31925 12:33:58.555306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip>
31926 12:33:58.555732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip
31928 12:33:58.623078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass>
31929 12:33:58.623527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass
31931 12:33:58.674196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip
31933 12:33:58.674696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip>
31934 12:33:58.711720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip>
31935 12:33:58.712182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip
31937 12:33:58.751412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass>
31938 12:33:58.751866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass
31940 12:33:58.789618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip>
31941 12:33:58.790061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip
31943 12:33:58.828552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip>
31944 12:33:58.828964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip
31946 12:33:58.867507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass>
31947 12:33:58.867944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass
31949 12:33:58.909685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip>
31950 12:33:58.910117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip
31952 12:33:58.959629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip
31954 12:33:58.960110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip>
31955 12:33:59.001803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass
31957 12:33:59.002290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass>
31958 12:33:59.045739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip>
31959 12:33:59.046243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip
31961 12:33:59.093934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip
31963 12:33:59.094406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip>
31964 12:33:59.134187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass
31966 12:33:59.134669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass>
31967 12:33:59.172954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip
31969 12:33:59.173436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip>
31970 12:33:59.212321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip
31972 12:33:59.212697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip>
31973 12:33:59.251729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass
31975 12:33:59.252231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass>
31976 12:33:59.293601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip>
31977 12:33:59.294047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip
31979 12:33:59.337592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip>
31980 12:33:59.338046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip
31982 12:33:59.387154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass>
31983 12:33:59.387607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass
31985 12:33:59.432515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip
31987 12:33:59.433217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip>
31988 12:33:59.483723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip>
31989 12:33:59.484165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip
31991 12:33:59.528819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass>
31992 12:33:59.529272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass
31994 12:33:59.575730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip>
31995 12:33:59.576136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip
31997 12:33:59.621879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip>
31998 12:33:59.622341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip
32000 12:33:59.675610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass>
32001 12:33:59.676074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass
32003 12:33:59.734253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip
32005 12:33:59.734749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip>
32006 12:33:59.778822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip
32008 12:33:59.779408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip>
32009 12:33:59.816804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass>
32010 12:33:59.817220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass
32012 12:33:59.872082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip>
32013 12:33:59.872522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip
32015 12:33:59.927646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip
32017 12:33:59.928221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip>
32018 12:33:59.975929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass>
32019 12:33:59.976339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass
32021 12:34:00.019008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip
32023 12:34:00.019392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip>
32024 12:34:00.058274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip
32026 12:34:00.058739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip>
32027 12:34:00.098674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass
32029 12:34:00.099310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass>
32030 12:34:00.147636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip>
32031 12:34:00.148155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip
32033 12:34:00.197813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip>
32034 12:34:00.198251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip
32036 12:34:00.239408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass>
32037 12:34:00.239828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass
32039 12:34:00.282675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip>
32040 12:34:00.283096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip
32042 12:34:00.330140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip
32044 12:34:00.330869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip>
32045 12:34:00.384092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass
32047 12:34:00.384546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass>
32048 12:34:00.427013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip
32050 12:34:00.427553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip>
32051 12:34:00.466260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip
32053 12:34:00.466689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip>
32054 12:34:00.508513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass
32056 12:34:00.508980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass>
32057 12:34:00.551964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip>
32058 12:34:00.552422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip
32060 12:34:00.594018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip
32062 12:34:00.594798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip>
32063 12:34:00.637697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass
32065 12:34:00.638167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass>
32066 12:34:00.682147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip
32068 12:34:00.682625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip>
32069 12:34:00.725359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip
32071 12:34:00.726134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip>
32072 12:34:00.773546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass
32074 12:34:00.773956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass>
32075 12:34:00.820514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip>
32076 12:34:00.820913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip
32078 12:34:00.865193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip>
32079 12:34:00.865580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip
32081 12:34:00.903999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass>
32082 12:34:00.904382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass
32084 12:34:00.950152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip
32086 12:34:00.950630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip>
32087 12:34:00.995117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip>
32088 12:34:00.995531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip
32090 12:34:01.032531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass>
32091 12:34:01.033037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass
32093 12:34:01.070735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip>
32094 12:34:01.071189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip
32096 12:34:01.111314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip>
32097 12:34:01.111768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip
32099 12:34:01.155649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass>
32100 12:34:01.156112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass
32102 12:34:01.204392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip>
32103 12:34:01.204827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip
32105 12:34:01.242966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip
32107 12:34:01.243440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip>
32108 12:34:01.281389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass>
32109 12:34:01.281834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass
32111 12:34:01.324304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip>
32112 12:34:01.324733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip
32114 12:34:01.371178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip>
32115 12:34:01.371681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip
32117 12:34:01.417588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass>
32118 12:34:01.417984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass
32120 12:34:01.468605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip>
32121 12:34:01.469023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip
32123 12:34:01.508252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip>
32124 12:34:01.508689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip
32126 12:34:01.556763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass
32128 12:34:01.557572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass>
32129 12:34:01.605415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip>
32130 12:34:01.605927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip
32132 12:34:01.648496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip>
32133 12:34:01.648909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip
32135 12:34:01.691727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass>
32136 12:34:01.692162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass
32138 12:34:01.731751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip>
32139 12:34:01.732185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip
32141 12:34:01.773004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip>
32142 12:34:01.773406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip
32144 12:34:01.817412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass
32146 12:34:01.817898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass>
32147 12:34:01.856288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip>
32148 12:34:01.856696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip
32150 12:34:01.897715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip>
32151 12:34:01.898170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip
32153 12:34:01.935940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass
32155 12:34:01.936584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass>
32156 12:34:01.979832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip
32158 12:34:01.980221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip>
32159 12:34:02.016241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip
32161 12:34:02.016681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip>
32162 12:34:02.052468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass>
32163 12:34:02.052894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass
32165 12:34:02.091441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip>
32166 12:34:02.091860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip
32168 12:34:02.129525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip>
32169 12:34:02.129971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip
32171 12:34:02.168214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass
32173 12:34:02.168608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass>
32174 12:34:02.208909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip>
32175 12:34:02.209348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip
32177 12:34:02.249966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip
32179 12:34:02.250445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip>
32180 12:34:02.290853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass>
32181 12:34:02.291256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass
32183 12:34:02.331465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip
32185 12:34:02.331926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip>
32186 12:34:02.369823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip>
32187 12:34:02.370250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip
32189 12:34:02.412917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass
32191 12:34:02.413404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass>
32192 12:34:02.463414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip>
32193 12:34:02.463847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip
32195 12:34:02.504197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip>
32196 12:34:02.504647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip
32198 12:34:02.551904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass>
32199 12:34:02.552389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass
32201 12:34:02.596407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip>
32202 12:34:02.596892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip
32204 12:34:02.643771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip>
32205 12:34:02.644263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip
32207 12:34:02.684446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass
32209 12:34:02.684920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass>
32210 12:34:02.728997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip>
32211 12:34:02.729374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip
32213 12:34:02.767805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip>
32214 12:34:02.768323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip
32216 12:34:02.817198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass>
32217 12:34:02.817618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass
32219 12:34:02.855004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip>
32220 12:34:02.855450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip
32222 12:34:02.895785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip
32224 12:34:02.896553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip>
32225 12:34:02.933128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass>
32226 12:34:02.933617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass
32228 12:34:02.973139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip>
32229 12:34:02.973571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip
32231 12:34:03.012973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip
32233 12:34:03.013358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip>
32234 12:34:03.060419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass>
32235 12:34:03.060942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass
32237 12:34:03.109005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip>
32238 12:34:03.109448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip
32240 12:34:03.154324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip
32242 12:34:03.154954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip>
32243 12:34:03.204209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass
32245 12:34:03.204862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass>
32246 12:34:03.243353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip
32248 12:34:03.243984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip>
32249 12:34:03.296525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip>
32250 12:34:03.297106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip
32252 12:34:03.344877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass>
32253 12:34:03.345375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass
32255 12:34:03.401371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip>
32256 12:34:03.401771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip
32258 12:34:03.449388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip
32260 12:34:03.449864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip>
32261 12:34:03.487829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass>
32262 12:34:03.488287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass
32264 12:34:03.529564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip>
32265 12:34:03.529974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip
32267 12:34:03.587849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip>
32268 12:34:03.588273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip
32270 12:34:03.642332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass
32272 12:34:03.642746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass>
32273 12:34:03.686403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip
32275 12:34:03.687039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip>
32276 12:34:03.744407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip>
32277 12:34:03.744889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip
32279 12:34:03.783906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass>
32280 12:34:03.784360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass
32282 12:34:03.820931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip
32284 12:34:03.821384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip>
32285 12:34:03.859711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip
32287 12:34:03.860188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip>
32288 12:34:03.896702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass
32290 12:34:03.897185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass>
32291 12:34:03.936047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip
32293 12:34:03.936485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip>
32294 12:34:03.973198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip>
32295 12:34:03.973581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip
32297 12:34:04.009420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass
32299 12:34:04.009865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass>
32300 12:34:04.054248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip
32302 12:34:04.054673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip>
32303 12:34:04.091554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip>
32304 12:34:04.091987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip
32306 12:34:04.132806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass>
32307 12:34:04.133232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass
32309 12:34:04.191494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip>
32310 12:34:04.191941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip
32312 12:34:04.249450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip>
32313 12:34:04.249900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip
32315 12:34:04.287937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass
32317 12:34:04.288490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass>
32318 12:34:04.324219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip
32320 12:34:04.324981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip>
32321 12:34:04.360460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip>
32322 12:34:04.360845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip
32324 12:34:04.397704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass>
32325 12:34:04.398228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass
32327 12:34:04.442190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip
32329 12:34:04.442656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip>
32330 12:34:04.480611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip>
32331 12:34:04.481034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip
32333 12:34:04.532594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass
32335 12:34:04.533269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass>
32336 12:34:04.571097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip>
32337 12:34:04.571474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip
32339 12:34:04.608590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip>
32340 12:34:04.609042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip
32342 12:34:04.650968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass>
32343 12:34:04.651377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass
32345 12:34:04.691086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip>
32346 12:34:04.691484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip
32348 12:34:04.733514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip>
32349 12:34:04.733954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip
32351 12:34:04.771681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass>
32352 12:34:04.772108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass
32354 12:34:04.813656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip
32356 12:34:04.814125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip>
32357 12:34:04.852295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip>
32358 12:34:04.852753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip
32360 12:34:04.899998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass
32362 12:34:04.900357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass>
32363 12:34:04.943887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip
32365 12:34:04.944267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip>
32366 12:34:04.983974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip
32368 12:34:04.984361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip>
32369 12:34:05.030886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass>
32370 12:34:05.031325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass
32372 12:34:05.076021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip>
32373 12:34:05.076450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip
32375 12:34:05.128131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip>
32376 12:34:05.128699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip
32378 12:34:05.167221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=pass>
32379 12:34:05.167719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=pass
32381 12:34:05.211659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass>
32382 12:34:05.212092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass
32384 12:34:05.251598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass>
32385 12:34:05.252067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass
32387 12:34:05.290374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass
32389 12:34:05.290971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass>
32390 12:34:05.332470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass>
32391 12:34:05.332890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass
32393 12:34:05.373100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32395 12:34:05.373552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32396 12:34:05.424331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32397 12:34:05.424763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32399 12:34:05.465206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32400 12:34:05.465698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32402 12:34:05.503641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass>
32403 12:34:05.504075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass
32405 12:34:05.542687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass>
32406 12:34:05.543166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass
32408 12:34:05.580697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32409 12:34:05.581130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32411 12:34:05.620017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32413 12:34:05.620745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32414 12:34:05.659253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32416 12:34:05.659698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32417 12:34:05.698175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass
32419 12:34:05.698647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass>
32420 12:34:05.736714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail
32422 12:34:05.737140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail>
32423 12:34:05.775478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail>
32424 12:34:05.775896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail
32426 12:34:05.831220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass>
32427 12:34:05.831615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass
32429 12:34:05.872443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32430 12:34:05.872954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32432 12:34:05.917146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32433 12:34:05.917581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32435 12:34:05.965258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32436 12:34:05.965685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32438 12:34:06.014395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32440 12:34:06.014830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32441 12:34:06.065526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail>
32442 12:34:06.065936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail
32444 12:34:06.105866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32445 12:34:06.106441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32447 12:34:06.149056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32448 12:34:06.149545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32450 12:34:06.203905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32451 12:34:06.204465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32453 12:34:06.245769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32454 12:34:06.246274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32456 12:34:06.283995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32457 12:34:06.284500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32459 12:34:06.332604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32460 12:34:06.333047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32462 12:34:06.374617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32464 12:34:06.375046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32465 12:34:06.416630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32466 12:34:06.416977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32468 12:34:06.459109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32469 12:34:06.459544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32471 12:34:06.500233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32472 12:34:06.500665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32474 12:34:06.539707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32475 12:34:06.540160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32477 12:34:06.587113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32479 12:34:06.587633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32480 12:34:06.645579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=fail>
32481 12:34:06.646171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=fail
32483 12:34:06.703724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail
32485 12:34:06.704189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail>
32486 12:34:06.747325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=fail>
32487 12:34:06.747768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=fail
32489 12:34:06.788142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32490 12:34:06.788610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32492 12:34:06.828436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32493 12:34:06.828855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32495 12:34:06.878792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32496 12:34:06.879343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32498 12:34:06.925519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32499 12:34:06.926084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32501 12:34:06.968932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32502 12:34:06.969434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32504 12:34:07.009003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32505 12:34:07.009422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32507 12:34:07.049473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32508 12:34:07.049920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32510 12:34:07.089156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32512 12:34:07.089598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32513 12:34:07.140142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32514 12:34:07.140508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32516 12:34:07.177527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32518 12:34:07.177903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32519 12:34:07.216067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32520 12:34:07.216426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32522 12:34:07.261267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32523 12:34:07.261667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32525 12:34:07.306943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32526 12:34:07.307377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32528 12:34:07.345934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32529 12:34:07.346369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32531 12:34:07.383985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32532 12:34:07.384411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32534 12:34:07.423135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32535 12:34:07.423690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32537 12:34:07.469307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32539 12:34:07.469699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32540 12:34:07.516905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32541 12:34:07.517335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32543 12:34:07.556564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32544 12:34:07.556986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32546 12:34:07.597049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32547 12:34:07.597482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32549 12:34:07.639403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail>
32550 12:34:07.639849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail
32552 12:34:07.680622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail>
32553 12:34:07.681109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail
32555 12:34:07.719857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=fail>
32556 12:34:07.720313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=fail
32558 12:34:07.766901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
32560 12:34:07.767362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
32561 12:34:07.813105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
32563 12:34:07.813564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
32564 12:34:07.857577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass>
32565 12:34:07.858038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass
32567 12:34:07.899674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass>
32568 12:34:07.900136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass
32570 12:34:07.945584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass
32572 12:34:07.946070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass>
32573 12:34:07.985229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
32574 12:34:07.985679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
32576 12:34:08.038867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail>
32577 12:34:08.039283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail
32579 12:34:08.077567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail>
32580 12:34:08.078090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail
32582 12:34:08.120530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass>
32583 12:34:08.120951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass
32585 12:34:08.168024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail
32587 12:34:08.168411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail>
32588 12:34:08.212422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail>
32589 12:34:08.212849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail
32591 12:34:08.251121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32592 12:34:08.251559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32594 12:34:08.293403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32595 12:34:08.293946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32597 12:34:08.337886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32598 12:34:08.338354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32600 12:34:08.381486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32601 12:34:08.381877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32603 12:34:08.428723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32604 12:34:08.429108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32606 12:34:08.480778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32607 12:34:08.481222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32609 12:34:08.532829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32610 12:34:08.533267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32612 12:34:08.594821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32613 12:34:08.595265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32615 12:34:08.651444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32616 12:34:08.651871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32618 12:34:08.692957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32619 12:34:08.693367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32621 12:34:08.741457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32622 12:34:08.741868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32624 12:34:08.783842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32625 12:34:08.784257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32627 12:34:08.823771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32629 12:34:08.824246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32630 12:34:08.886182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32632 12:34:08.886673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32633 12:34:08.925003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32634 12:34:08.925424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32636 12:34:08.963210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32637 12:34:08.963632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32639 12:34:09.009619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32640 12:34:09.010062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32642 12:34:09.065335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32643 12:34:09.065684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32645 12:34:09.108439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32646 12:34:09.108826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32648 12:34:09.151612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32650 12:34:09.152094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32651 12:34:09.203888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32652 12:34:09.204325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32654 12:34:09.250890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32655 12:34:09.251320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32657 12:34:09.301600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32658 12:34:09.302050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32660 12:34:09.352320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32661 12:34:09.352793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32663 12:34:09.403468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32664 12:34:09.403868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32666 12:34:09.448979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32667 12:34:09.449451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32669 12:34:09.503951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32670 12:34:09.504407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32672 12:34:09.562768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32673 12:34:09.563178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32675 12:34:09.619445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32676 12:34:09.619834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32678 12:34:09.675641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32679 12:34:09.676149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32681 12:34:09.728803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32682 12:34:09.729225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32684 12:34:09.768483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32686 12:34:09.769069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32687 12:34:09.828217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32688 12:34:09.828767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32690 12:34:09.876122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32691 12:34:09.876547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32693 12:34:09.919426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32695 12:34:09.919929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32696 12:34:09.958243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32698 12:34:09.958712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32699 12:34:10.003592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32700 12:34:10.004030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32702 12:34:10.052094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32703 12:34:10.052680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32705 12:34:10.107391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32706 12:34:10.107836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32708 12:34:10.146785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32710 12:34:10.147232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32711 12:34:10.187195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32713 12:34:10.187668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32714 12:34:10.226709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32715 12:34:10.227151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32717 12:34:10.267893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32718 12:34:10.268295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32720 12:34:10.311755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32721 12:34:10.312248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32723 12:34:10.360165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32724 12:34:10.360593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32726 12:34:10.400672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32727 12:34:10.401093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32729 12:34:10.443082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32731 12:34:10.443556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32732 12:34:10.484320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32734 12:34:10.484788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32735 12:34:10.524580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32736 12:34:10.524975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32738 12:34:10.563795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32739 12:34:10.564208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32741 12:34:10.603382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32742 12:34:10.603806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32744 12:34:10.646136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32746 12:34:10.646603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32747 12:34:10.695591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32748 12:34:10.696034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32750 12:34:10.741790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32751 12:34:10.742223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32753 12:34:10.785674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32755 12:34:10.786102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32756 12:34:10.833730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32758 12:34:10.834354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32759 12:34:10.881600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32760 12:34:10.882018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32762 12:34:10.925233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32763 12:34:10.925620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32765 12:34:10.963917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32766 12:34:10.964319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32768 12:34:11.021544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32769 12:34:11.021959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32771 12:34:11.065848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32772 12:34:11.066333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32774 12:34:11.103326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32776 12:34:11.103779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32777 12:34:11.141020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32778 12:34:11.141543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32780 12:34:11.179027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32781 12:34:11.179479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32783 12:34:11.216347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=pass>
32784 12:34:11.216768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=pass
32786 12:34:11.258399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass
32788 12:34:11.258837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass>
32789 12:34:11.297783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass>
32790 12:34:11.298180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass
32792 12:34:11.341978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass
32794 12:34:11.342467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass>
32795 12:34:11.381134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass>
32796 12:34:11.381556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass
32798 12:34:11.419938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass
32800 12:34:11.420527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass>
32801 12:34:11.459108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass>
32802 12:34:11.459512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass
32804 12:34:11.503553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass
32806 12:34:11.504028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass>
32807 12:34:11.556069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass>
32808 12:34:11.556517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass
32810 12:34:11.600018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass>
32811 12:34:11.600412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass
32813 12:34:11.643170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass
32815 12:34:11.643621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass>
32816 12:34:11.686836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass>
32817 12:34:11.687227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass
32819 12:34:11.724584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass>
32820 12:34:11.725013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass
32822 12:34:11.773937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass
32824 12:34:11.774364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32825 12:34:11.815170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass
32827 12:34:11.815788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32828 12:34:11.851834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass
32830 12:34:11.852304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass>
32831 12:34:11.889061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass>
32832 12:34:11.889621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass
32834 12:34:11.929552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass
32836 12:34:11.930036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass>
32837 12:34:11.968781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass>
32838 12:34:11.969194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass
32840 12:34:12.007087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
32842 12:34:12.007804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
32843 12:34:12.051549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass
32845 12:34:12.052039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass>
32846 12:34:12.107910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass>
32847 12:34:12.108349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass
32849 12:34:12.163831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass>
32850 12:34:12.164267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass
32852 12:34:12.217525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass
32854 12:34:12.218011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass>
32855 12:34:12.272901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass>
32856 12:34:12.273334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass
32858 12:34:12.329559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass
32860 12:34:12.330184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass>
32861 12:34:12.382150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass
32863 12:34:12.382894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass>
32864 12:34:12.420096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass>
32865 12:34:12.420636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass
32867 12:34:12.457452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass
32869 12:34:12.457944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass>
32870 12:34:12.498714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass
32872 12:34:12.499178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass>
32873 12:34:12.546902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass>
32874 12:34:12.547336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass
32876 12:34:12.588356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass
32878 12:34:12.588835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass>
32879 12:34:12.625483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32880 12:34:12.625880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass
32882 12:34:12.681710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass
32884 12:34:12.682482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32885 12:34:12.737505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass>
32886 12:34:12.738011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass
32888 12:34:12.793433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass
32890 12:34:12.793868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass>
32891 12:34:12.849289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass>
32892 12:34:12.849686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass
32894 12:34:12.904359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass
32896 12:34:12.904782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass>
32897 12:34:12.957603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
32899 12:34:12.958032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
32900 12:34:13.015012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
32901 12:34:13.015438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
32903 12:34:13.053323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass
32905 12:34:13.053835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass>
32906 12:34:13.094873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
32907 12:34:13.095271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
32909 12:34:13.145432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
32911 12:34:13.145863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
32912 12:34:13.199535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
32914 12:34:13.199978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
32915 12:34:13.249450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
32916 12:34:13.249896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
32918 12:34:13.287545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
32919 12:34:13.287973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
32921 12:34:13.326059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass
32923 12:34:13.326551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass>
32924 12:34:13.368257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
32926 12:34:13.368735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
32927 12:34:13.413088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass>
32928 12:34:13.413550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass
32930 12:34:13.464656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
32931 12:34:13.465212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
32933 12:34:13.517468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass>
32934 12:34:13.517961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass
32936 12:34:13.555846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
32937 12:34:13.556297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
32939 12:34:13.595485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass>
32940 12:34:13.595959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass
32942 12:34:13.636636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
32943 12:34:13.637008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
32945 12:34:13.688849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass>
32946 12:34:13.689252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass
32948 12:34:13.730449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
32950 12:34:13.731072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
32951 12:34:13.771908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass
32953 12:34:13.772330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass>
32954 12:34:13.813226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
32955 12:34:13.813610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
32957 12:34:13.860232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass>
32958 12:34:13.860664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass
32960 12:34:13.909431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
32961 12:34:13.909868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
32963 12:34:13.951328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass>
32964 12:34:13.951820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass
32966 12:34:14.023733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
32967 12:34:14.024179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
32969 12:34:14.083069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass>
32970 12:34:14.083613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass
32972 12:34:14.142351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
32974 12:34:14.142890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
32975 12:34:14.189156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass>
32976 12:34:14.189702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass
32978 12:34:14.233879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
32980 12:34:14.234381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
32981 12:34:14.289224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
32983 12:34:14.289694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
32984 12:34:14.329265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
32985 12:34:14.329722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
32987 12:34:14.369337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
32989 12:34:14.369804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
32990 12:34:14.409537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
32991 12:34:14.409990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
32993 12:34:14.450788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
32994 12:34:14.451123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
32996 12:34:14.506820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
32997 12:34:14.507179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
32999 12:34:14.567987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
33000 12:34:14.568369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
33002 12:34:14.617202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
33003 12:34:14.617660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
33005 12:34:14.656178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
33006 12:34:14.656575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
33008 12:34:14.697721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
33010 12:34:14.698194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
33011 12:34:14.741264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
33012 12:34:14.741679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
33014 12:34:14.780403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass
33016 12:34:14.780832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass>
33017 12:34:14.823321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33018 12:34:14.823688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33020 12:34:14.872744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33021 12:34:14.873196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass
33023 12:34:14.912575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33024 12:34:14.913003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33026 12:34:14.966183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33028 12:34:14.966660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33029 12:34:15.024027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass
33031 12:34:15.024500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33032 12:34:15.064673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33033 12:34:15.065101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33035 12:34:15.111148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33036 12:34:15.111583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33038 12:34:15.152417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33039 12:34:15.152839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass
33041 12:34:15.191506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33042 12:34:15.191927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33044 12:34:15.231443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33045 12:34:15.231889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33047 12:34:15.271830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass
33049 12:34:15.272317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33050 12:34:15.310228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33052 12:34:15.310715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33053 12:34:15.349372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33054 12:34:15.349797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33056 12:34:15.389813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33057 12:34:15.390249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass
33059 12:34:15.429257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33061 12:34:15.429751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33062 12:34:15.468366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass>
33063 12:34:15.468796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass
33065 12:34:15.507329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33066 12:34:15.507748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33068 12:34:15.546979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33069 12:34:15.547403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass
33071 12:34:15.587288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33072 12:34:15.587721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33074 12:34:15.626280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33076 12:34:15.626820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33077 12:34:15.665180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33078 12:34:15.665625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass
33080 12:34:15.704966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33081 12:34:15.705345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33083 12:34:15.743731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33085 12:34:15.744193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33086 12:34:15.783552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33087 12:34:15.784036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass
33089 12:34:15.825491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33090 12:34:15.825956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33092 12:34:15.871161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33093 12:34:15.871588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33095 12:34:15.919150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33096 12:34:15.919582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass
33098 12:34:15.960826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33099 12:34:15.961277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33101 12:34:16.016407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33102 12:34:16.016820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33104 12:34:16.056547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33105 12:34:16.056952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass
33107 12:34:16.111086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33108 12:34:16.111517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33110 12:34:16.154268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass
33112 12:34:16.154689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass>
33113 12:34:16.195753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33114 12:34:16.196199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33116 12:34:16.245633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33117 12:34:16.246078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass
33119 12:34:16.286243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33121 12:34:16.286714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33122 12:34:16.325733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33123 12:34:16.326179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33125 12:34:16.366387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass
33127 12:34:16.366856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33128 12:34:16.406848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33130 12:34:16.407333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33131 12:34:16.447353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33132 12:34:16.447785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33134 12:34:16.487539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33135 12:34:16.487968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass
33137 12:34:16.527780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33138 12:34:16.528152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33140 12:34:16.567332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33142 12:34:16.567782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33143 12:34:16.606938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33144 12:34:16.607410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass
33146 12:34:16.645675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33148 12:34:16.646259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33149 12:34:16.686090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33151 12:34:16.686696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33152 12:34:16.739393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33153 12:34:16.739847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass
33155 12:34:16.779632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33156 12:34:16.780033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33158 12:34:16.818840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass
33160 12:34:16.819207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass>
33161 12:34:16.865684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33162 12:34:16.866121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33164 12:34:16.917283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33165 12:34:16.917749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass
33167 12:34:16.960889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33169 12:34:16.961479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33170 12:34:17.003711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33172 12:34:17.004162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33173 12:34:17.045521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33174 12:34:17.045887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass
33176 12:34:17.085629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33177 12:34:17.085989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33179 12:34:17.125771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33180 12:34:17.126130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33182 12:34:17.165858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33183 12:34:17.166334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass
33185 12:34:17.213222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33186 12:34:17.213640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33188 12:34:17.255203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33190 12:34:17.255671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33191 12:34:17.300452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33192 12:34:17.300872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass
33194 12:34:17.345016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33195 12:34:17.345448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33197 12:34:17.393244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33198 12:34:17.393638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33200 12:34:17.443353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33201 12:34:17.443788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass
33203 12:34:17.484077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33205 12:34:17.484550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33206 12:34:17.523482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass
33208 12:34:17.523960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass>
33209 12:34:17.562329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
33211 12:34:17.562797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
33212 12:34:17.601259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass>
33213 12:34:17.601684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass
33215 12:34:17.640955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
33216 12:34:17.641380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass
33218 12:34:17.679778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33220 12:34:17.680243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33221 12:34:17.719128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33222 12:34:17.719546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass
33224 12:34:17.758912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33225 12:34:17.759333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33227 12:34:17.799211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
33228 12:34:17.799641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
33230 12:34:17.839426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass>
33231 12:34:17.839884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass
33233 12:34:17.885500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
33234 12:34:17.885950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass
33236 12:34:17.925522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
33238 12:34:17.925966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
33239 12:34:17.966706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass>
33240 12:34:17.967112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass
33242 12:34:18.007743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
33243 12:34:18.008156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass
33245 12:34:18.047720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
33247 12:34:18.048181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
33248 12:34:18.088070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass
33250 12:34:18.088554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass>
33251 12:34:18.130108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass
33253 12:34:18.130544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
33254 12:34:18.169537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass
33256 12:34:18.170110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass>
33257 12:34:18.224448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
33259 12:34:18.224891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
33260 12:34:18.275132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass>
33261 12:34:18.275524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass
33263 12:34:18.317396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
33264 12:34:18.317791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass
33266 12:34:18.364378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
33267 12:34:18.364731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
33269 12:34:18.412968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass>
33270 12:34:18.413402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass
33272 12:34:18.455739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
33273 12:34:18.456206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass
33275 12:34:18.513528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
33277 12:34:18.514171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
33278 12:34:18.572286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass>
33279 12:34:18.572717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass
33281 12:34:18.631366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass
33283 12:34:18.631835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
33284 12:34:18.690209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
33286 12:34:18.690791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
33287 12:34:18.749803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass>
33288 12:34:18.750245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass
33290 12:34:18.809209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
33291 12:34:18.809659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass
33293 12:34:18.864787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
33294 12:34:18.865225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
33296 12:34:18.908749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass>
33297 12:34:18.909191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass
33299 12:34:18.957072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
33300 12:34:18.957494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass
33302 12:34:19.000762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass>
33303 12:34:19.001218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass
33305 12:34:19.040278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
33306 12:34:19.040730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
33308 12:34:19.121493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass>
33309 12:34:19.121967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass
33311 12:34:19.180213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
33312 12:34:19.180645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass
33314 12:34:19.224220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
33315 12:34:19.224734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
33317 12:34:19.261226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass>
33318 12:34:19.261661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass
33320 12:34:19.299687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
33321 12:34:19.300148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass
33323 12:34:19.357076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
33324 12:34:19.357494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
33326 12:34:19.408997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass>
33327 12:34:19.409434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass
33329 12:34:19.447045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
33330 12:34:19.447496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass
33332 12:34:19.501378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
33334 12:34:19.501863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
33335 12:34:19.541833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass>
33336 12:34:19.542267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass
33338 12:34:19.585415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
33339 12:34:19.585811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass
33341 12:34:19.636312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
33343 12:34:19.636746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
33344 12:34:19.679448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass>
33345 12:34:19.679871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass
33347 12:34:19.722566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
33348 12:34:19.723025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass
33350 12:34:19.761532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass
33352 12:34:19.762012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass>
33353 12:34:19.800774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
33354 12:34:19.801216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
33356 12:34:19.843887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass>
33357 12:34:19.844455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass
33359 12:34:19.891186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass
33361 12:34:19.891626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
33362 12:34:19.928226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
33363 12:34:19.928623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
33365 12:34:19.969392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass>
33366 12:34:19.969833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass
33368 12:34:20.011121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
33369 12:34:20.011544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass
33371 12:34:20.055567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
33372 12:34:20.056011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
33374 12:34:20.103954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass
33376 12:34:20.104407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass>
33377 12:34:20.144310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
33378 12:34:20.144745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass
33380 12:34:20.195363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
33381 12:34:20.195858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
33383 12:34:20.244758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass
33385 12:34:20.245231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass>
33386 12:34:20.283957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass
33388 12:34:20.284396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
33389 12:34:20.339937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
33390 12:34:20.340360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
33392 12:34:20.379652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass
33394 12:34:20.380128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass>
33395 12:34:20.419678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
33396 12:34:20.420048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass
33398 12:34:20.463411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass>
33399 12:34:20.463777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass
33401 12:34:20.505721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
33402 12:34:20.506154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
33404 12:34:20.544833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass>
33405 12:34:20.545263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass
33407 12:34:20.587390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
33408 12:34:20.587785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass
33410 12:34:20.646785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
33411 12:34:20.647244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
33413 12:34:20.692403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass
33415 12:34:20.692997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass>
33416 12:34:20.740516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
33417 12:34:20.741001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass
33419 12:34:20.787924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
33420 12:34:20.788351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
33422 12:34:20.831904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass>
33423 12:34:20.832351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass
33425 12:34:20.873762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
33426 12:34:20.874165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass
33428 12:34:20.916813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
33430 12:34:20.917164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
33431 12:34:20.967455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass>
33432 12:34:20.967873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass
33434 12:34:21.013578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass
33436 12:34:21.014051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
33437 12:34:21.062755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
33438 12:34:21.063190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
33440 12:34:21.103081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass>
33441 12:34:21.103487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass
33443 12:34:21.141397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass
33445 12:34:21.141825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
33446 12:34:21.186919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass
33448 12:34:21.187325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass>
33449 12:34:21.225375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
33451 12:34:21.225841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
33452 12:34:21.271283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass>
33453 12:34:21.271704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass
33455 12:34:21.315619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
33456 12:34:21.316081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass
33458 12:34:21.377178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
33459 12:34:21.377695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
33461 12:34:21.425732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass
33463 12:34:21.426228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass>
33464 12:34:21.469319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass
33466 12:34:21.469789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
33467 12:34:21.520309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
33469 12:34:21.520788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
33470 12:34:21.581237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass>
33471 12:34:21.581678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass
33473 12:34:21.641565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
33474 12:34:21.641998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass
33476 12:34:21.699383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
33477 12:34:21.699826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
33479 12:34:21.750118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass
33481 12:34:21.750618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass>
33482 12:34:21.793961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass
33484 12:34:21.794437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
33485 12:34:21.843949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
33486 12:34:21.844368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
33488 12:34:21.888462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass
33490 12:34:21.888880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass>
33491 12:34:21.927632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
33492 12:34:21.928059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass
33494 12:34:21.977043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass>
33495 12:34:21.977469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass
33497 12:34:22.028695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
33499 12:34:22.029160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
33500 12:34:22.075895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass
33502 12:34:22.076384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass>
33503 12:34:22.116549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
33504 12:34:22.116978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass
33506 12:34:22.168199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
33507 12:34:22.168635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
33509 12:34:22.223785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass>
33510 12:34:22.224286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass
33512 12:34:22.276044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass
33514 12:34:22.276478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
33515 12:34:22.319779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
33517 12:34:22.320196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
33518 12:34:22.369402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass>
33519 12:34:22.369955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass
33521 12:34:22.421244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
33522 12:34:22.421794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass
33524 12:34:22.475261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
33525 12:34:22.475681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
33527 12:34:22.524968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass>
33528 12:34:22.525400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass
33530 12:34:22.571253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
33531 12:34:22.571684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass
33533 12:34:22.608938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
33534 12:34:22.609396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
33536 12:34:22.648454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass
33538 12:34:22.648956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass>
33539 12:34:22.694157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass
33541 12:34:22.694656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
33542 12:34:22.734934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass>
33543 12:34:22.735351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass
33545 12:34:22.773261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
33546 12:34:22.773680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
33548 12:34:22.811481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass>
33549 12:34:22.811881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass
33551 12:34:22.849408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
33552 12:34:22.849820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass
33554 12:34:22.886753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
33555 12:34:22.887147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
33557 12:34:22.923158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass>
33558 12:34:22.923572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass
33560 12:34:22.960439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
33561 12:34:22.960858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass
33563 12:34:22.996490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
33564 12:34:22.996915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
33566 12:34:23.032508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass>
33567 12:34:23.032928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass
33569 12:34:23.075241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
33570 12:34:23.075743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass
33572 12:34:23.114129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
33574 12:34:23.114507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
33575 12:34:23.153133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass>
33576 12:34:23.153528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass
33578 12:34:23.192780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
33579 12:34:23.193178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass
33581 12:34:23.232093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
33582 12:34:23.232505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
33584 12:34:23.272741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass
33586 12:34:23.273229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass>
33587 12:34:23.311772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
33588 12:34:23.312219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass
33590 12:34:23.351694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass>
33591 12:34:23.352134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass
33593 12:34:23.392179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
33594 12:34:23.392503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
33596 12:34:23.432659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass>
33597 12:34:23.433047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass
33599 12:34:23.472843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
33600 12:34:23.473342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass
33602 12:34:23.512739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
33604 12:34:23.513199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
33605 12:34:23.551837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass
33607 12:34:23.552269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass>
33608 12:34:23.592816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
33609 12:34:23.593380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass
33611 12:34:23.635445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
33613 12:34:23.635895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
33614 12:34:23.689373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass>
33615 12:34:23.689802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass
33617 12:34:23.744110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
33618 12:34:23.744673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass
33620 12:34:23.795009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
33621 12:34:23.795406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
33623 12:34:23.834086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass
33625 12:34:23.834722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass>
33626 12:34:23.876500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass
33628 12:34:23.877267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
33629 12:34:23.915749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
33630 12:34:23.916200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
33632 12:34:23.967561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass>
33633 12:34:23.967982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass
33635 12:34:24.009721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
33636 12:34:24.010174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass
33638 12:34:24.049688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass>
33639 12:34:24.050138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass
33641 12:34:24.099207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
33642 12:34:24.099643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
33644 12:34:24.138101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass
33646 12:34:24.138517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass>
33647 12:34:24.212667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
33648 12:34:24.213091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass
33650 12:34:24.255388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
33652 12:34:24.255867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
33653 12:34:24.299799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass>
33654 12:34:24.300213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass
33656 12:34:24.355309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
33657 12:34:24.355768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass
33659 12:34:24.394818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
33660 12:34:24.395245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
33662 12:34:24.434849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass>
33663 12:34:24.435272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass
33665 12:34:24.478947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
33666 12:34:24.479476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass
33668 12:34:24.520230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
33669 12:34:24.520680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
33671 12:34:24.560663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass
33673 12:34:24.561129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass>
33674 12:34:24.600147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
33675 12:34:24.600718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass
33677 12:34:24.644928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
33678 12:34:24.645355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
33680 12:34:24.684318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass>
33681 12:34:24.684728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass
33683 12:34:24.725020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
33684 12:34:24.725460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass
33686 12:34:24.767484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass
33688 12:34:24.767912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass>
33689 12:34:24.805988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
33691 12:34:24.806783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
33692 12:34:24.846338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass
33694 12:34:24.846724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass>
33695 12:34:24.883907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
33696 12:34:24.884467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass
33698 12:34:24.922154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
33700 12:34:24.922634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
33701 12:34:24.961335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass
33703 12:34:24.961920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass>
33704 12:34:25.009177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
33705 12:34:25.009702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass
33707 12:34:25.062552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
33708 12:34:25.063013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
33710 12:34:25.103552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass>
33711 12:34:25.103986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass
33713 12:34:25.147147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
33714 12:34:25.147587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass
33716 12:34:25.196044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
33717 12:34:25.196455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
33719 12:34:25.251146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass>
33720 12:34:25.251529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass
33722 12:34:25.306857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
33723 12:34:25.307314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass
33725 12:34:25.355241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
33726 12:34:25.355680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
33728 12:34:25.400301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass>
33729 12:34:25.400733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass
33731 12:34:25.448031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
33732 12:34:25.448471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass
33734 12:34:25.490852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass>
33735 12:34:25.491327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass
33737 12:34:25.540779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
33738 12:34:25.541213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
33740 12:34:25.584137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass>
33741 12:34:25.584595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass
33743 12:34:25.633281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass
33745 12:34:25.633776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
33746 12:34:25.681543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
33747 12:34:25.681988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
33749 12:34:25.729016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass>
33750 12:34:25.729428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass
33752 12:34:25.778200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass
33754 12:34:25.778668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
33755 12:34:25.824037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
33757 12:34:25.824495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
33758 12:34:25.864615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass>
33759 12:34:25.865037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass
33761 12:34:25.921662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
33762 12:34:25.922105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass
33764 12:34:25.964771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
33765 12:34:25.965215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
33767 12:34:25.999735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass
33769 12:34:26.000153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass>
33770 12:34:26.036142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
33771 12:34:26.036545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass
33773 12:34:26.071338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
33774 12:34:26.071769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
33776 12:34:26.119465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass>
33777 12:34:26.119867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass
33779 12:34:26.169219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
33780 12:34:26.169696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass
33782 12:34:26.205577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
33784 12:34:26.206178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
33785 12:34:26.239929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass
33787 12:34:26.240335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass>
33788 12:34:26.288885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33789 12:34:26.289310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33791 12:34:26.325624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33792 12:34:26.326069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass
33794 12:34:26.362225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33796 12:34:26.362647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33797 12:34:26.400196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33798 12:34:26.400582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33800 12:34:26.448268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33801 12:34:26.448628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass
33803 12:34:26.484667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33805 12:34:26.485147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33806 12:34:26.521527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33807 12:34:26.521959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33809 12:34:26.558892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33810 12:34:26.559343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass
33812 12:34:26.597057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33813 12:34:26.597461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33815 12:34:26.637140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33816 12:34:26.637526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33818 12:34:26.683078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass
33820 12:34:26.683774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33821 12:34:26.731605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33822 12:34:26.732151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33824 12:34:26.769160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33825 12:34:26.769579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33827 12:34:26.807227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33828 12:34:26.807722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass
33830 12:34:26.847198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33832 12:34:26.847949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33833 12:34:26.884634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass>
33834 12:34:26.885041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass
33836 12:34:26.933065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33837 12:34:26.933488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33839 12:34:26.982858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33840 12:34:26.983348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass
33842 12:34:27.021218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33843 12:34:27.021706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33845 12:34:27.059562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33846 12:34:27.059979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33848 12:34:27.098925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33849 12:34:27.099502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass
33851 12:34:27.140396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33852 12:34:27.140793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33854 12:34:27.180445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33855 12:34:27.180884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33857 12:34:27.233481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33858 12:34:27.233929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass
33860 12:34:27.280834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33861 12:34:27.281255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33863 12:34:27.327567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33865 12:34:27.328160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33866 12:34:27.369964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass
33868 12:34:27.370550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33869 12:34:27.414784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33870 12:34:27.415239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33872 12:34:27.459141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33873 12:34:27.459631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33875 12:34:27.499814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33876 12:34:27.500311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass
33878 12:34:27.541818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33879 12:34:27.542284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33881 12:34:27.587136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass
33883 12:34:27.587597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass>
33884 12:34:27.625103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33886 12:34:27.625560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33887 12:34:27.663087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33888 12:34:27.663516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass
33890 12:34:27.700365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33891 12:34:27.700896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33893 12:34:27.739844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33895 12:34:27.740350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33896 12:34:27.785497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33897 12:34:27.785997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass
33899 12:34:27.829372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33901 12:34:27.829777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33902 12:34:27.867383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33903 12:34:27.867889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33905 12:34:27.904008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass
33907 12:34:27.904462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33908 12:34:27.949442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33909 12:34:27.949934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33911 12:34:27.990788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33912 12:34:27.991235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33914 12:34:28.029293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33915 12:34:28.029773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass
33917 12:34:28.073628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33918 12:34:28.074096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33920 12:34:28.114324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33922 12:34:28.114922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33923 12:34:28.153731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33924 12:34:28.154144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass
33926 12:34:28.207673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33927 12:34:28.208104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33929 12:34:28.245402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass
33931 12:34:28.246049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass>
33932 12:34:28.296203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33933 12:34:28.296615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33935 12:34:28.347107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33936 12:34:28.347536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass
33938 12:34:28.405340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33939 12:34:28.405751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33941 12:34:28.449924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33942 12:34:28.450409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33944 12:34:28.497896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass
33946 12:34:28.498493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33947 12:34:28.535717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33948 12:34:28.536162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33950 12:34:28.573929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33951 12:34:28.574363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33953 12:34:28.611836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass
33955 12:34:28.612299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33956 12:34:28.657941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33957 12:34:28.658380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33959 12:34:28.701641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33960 12:34:28.702096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33962 12:34:28.750329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass
33964 12:34:28.750801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33965 12:34:28.801273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33966 12:34:28.801687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33968 12:34:28.844421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33969 12:34:28.844876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33971 12:34:28.892611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33972 12:34:28.893064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass
33974 12:34:28.939560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33975 12:34:28.939929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33977 12:34:28.985174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass>
33978 12:34:28.985541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass
33980 12:34:29.028897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
33981 12:34:29.029377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
33983 12:34:29.070207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass
33985 12:34:29.070637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass>
33986 12:34:29.117248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass
33988 12:34:29.117733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
33989 12:34:29.157510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33990 12:34:29.157964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33992 12:34:29.196397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33993 12:34:29.196825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass
33995 12:34:29.236178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33996 12:34:29.236597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33998 12:34:29.275699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
34000 12:34:29.276164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
34001 12:34:29.336190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass>
34002 12:34:29.336622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass
34004 12:34:29.380242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
34005 12:34:29.380680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass
34007 12:34:29.421011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
34008 12:34:29.421426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
34010 12:34:29.464100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass>
34011 12:34:29.464523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass
34013 12:34:29.513820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
34014 12:34:29.514192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass
34016 12:34:29.553743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
34017 12:34:29.554254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
34019 12:34:29.595031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass>
34020 12:34:29.595603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass
34022 12:34:29.645881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
34023 12:34:29.646314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass
34025 12:34:29.687140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass>
34026 12:34:29.687540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass
34028 12:34:29.728946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
34029 12:34:29.729359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
34031 12:34:29.779527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass
34033 12:34:29.779995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass>
34034 12:34:29.833468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
34035 12:34:29.833936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass
34037 12:34:29.884236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
34038 12:34:29.884779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
34040 12:34:29.936876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass>
34041 12:34:29.937331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass
34043 12:34:29.979887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
34044 12:34:29.980320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass
34046 12:34:30.021352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
34047 12:34:30.021782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
34049 12:34:30.063722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass>
34050 12:34:30.064157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass
34052 12:34:30.112843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
34053 12:34:30.113278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass
34055 12:34:30.171677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
34056 12:34:30.172229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
34058 12:34:30.218225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass
34060 12:34:30.218697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass>
34061 12:34:30.259727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass
34063 12:34:30.260206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
34064 12:34:30.305031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
34065 12:34:30.305464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
34067 12:34:30.340372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass>
34068 12:34:30.340812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass
34070 12:34:30.380007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
34071 12:34:30.380387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass
34073 12:34:30.419649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass>
34074 12:34:30.420215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass
34076 12:34:30.465494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
34077 12:34:30.465893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
34079 12:34:30.499522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass
34081 12:34:30.500001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass>
34082 12:34:30.536140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
34083 12:34:30.536596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass
34085 12:34:30.575798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
34086 12:34:30.576381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
34088 12:34:30.624987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass>
34089 12:34:30.625446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass
34091 12:34:30.676121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass
34093 12:34:30.676618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
34094 12:34:30.714754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
34095 12:34:30.715186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
34097 12:34:30.752126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass
34099 12:34:30.752626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass>
34100 12:34:30.799783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
34101 12:34:30.800220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass
34103 12:34:30.843984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
34105 12:34:30.844475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
34106 12:34:30.885449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass>
34107 12:34:30.885892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass
34109 12:34:30.931044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass
34111 12:34:30.931518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
34112 12:34:30.980243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
34113 12:34:30.980663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
34115 12:34:31.027068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass>
34116 12:34:31.027491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass
34118 12:34:31.076602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
34119 12:34:31.077042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass
34121 12:34:31.124125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass>
34122 12:34:31.124561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass
34124 12:34:31.161839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
34125 12:34:31.162275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
34127 12:34:31.207308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass
34129 12:34:31.207790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass>
34130 12:34:31.245642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
34131 12:34:31.246055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass
34133 12:34:31.284319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
34134 12:34:31.284805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
34136 12:34:31.330690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass>
34137 12:34:31.331203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass
34139 12:34:31.369901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
34140 12:34:31.370331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass
34142 12:34:31.419586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
34143 12:34:31.420011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
34145 12:34:31.458636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass>
34146 12:34:31.459053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass
34148 12:34:31.499563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass
34150 12:34:31.500033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
34151 12:34:31.539442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
34152 12:34:31.539890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
34154 12:34:31.584068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass>
34155 12:34:31.584501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass
34157 12:34:31.619637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass
34159 12:34:31.620071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
34160 12:34:31.659139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
34162 12:34:31.659625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
34163 12:34:31.707682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass>
34164 12:34:31.708139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass
34166 12:34:31.756363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
34167 12:34:31.756768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass
34169 12:34:31.801234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass>
34170 12:34:31.801659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass
34172 12:34:31.842843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
34173 12:34:31.843370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
34175 12:34:31.881080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass
34177 12:34:31.881907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass>
34178 12:34:31.919699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass
34180 12:34:31.920189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
34181 12:34:31.961499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
34183 12:34:31.961991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
34184 12:34:32.004606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass>
34185 12:34:32.005022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass
34187 12:34:32.043282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
34188 12:34:32.043740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass
34190 12:34:32.080040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
34192 12:34:32.080522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
34193 12:34:32.119171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass>
34194 12:34:32.119551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass
34196 12:34:32.158904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
34197 12:34:32.159355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass
34199 12:34:32.197719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
34200 12:34:32.198210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
34202 12:34:32.247385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass
34204 12:34:32.248162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass>
34205 12:34:32.285898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass
34207 12:34:32.286481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
34208 12:34:32.332967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
34209 12:34:32.333361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
34211 12:34:32.371264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass
34213 12:34:32.371741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass>
34214 12:34:32.417742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
34215 12:34:32.418149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass
34217 12:34:32.456798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass
34219 12:34:32.457584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass>
34220 12:34:32.499813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
34221 12:34:32.500244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
34223 12:34:32.544785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass
34225 12:34:32.545374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass>
34226 12:34:32.585196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
34227 12:34:32.585589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass
34229 12:34:32.629580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
34231 12:34:32.630282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
34232 12:34:32.669341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass
34234 12:34:32.669800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass>
34235 12:34:32.707504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass
34237 12:34:32.708239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
34238 12:34:32.747727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
34239 12:34:32.748291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
34241 12:34:32.788339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass>
34242 12:34:32.788769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass
34244 12:34:32.832534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass
34246 12:34:32.833126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
34247 12:34:32.878284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
34249 12:34:32.878787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
34250 12:34:32.919459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass>
34251 12:34:32.919937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass
34253 12:34:32.968126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
34254 12:34:32.968561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass
34256 12:34:33.011468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
34258 12:34:33.011930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
34259 12:34:33.052400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass>
34260 12:34:33.052817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass
34262 12:34:33.090008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass
34264 12:34:33.090570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
34265 12:34:33.131897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass
34267 12:34:33.132338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass>
34268 12:34:33.187523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
34269 12:34:33.187934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
34271 12:34:33.241497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass
34273 12:34:33.242111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass>
34274 12:34:33.287479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
34275 12:34:33.287906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass
34277 12:34:33.327569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
34278 12:34:33.328004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
34280 12:34:33.373541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass
34282 12:34:33.373947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass>
34283 12:34:33.419204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
34284 12:34:33.419638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass
34286 12:34:33.467993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
34287 12:34:33.468369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
34289 12:34:33.508980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass
34291 12:34:33.509441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass>
34292 12:34:33.551944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
34293 12:34:33.552358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass
34295 12:34:33.591261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
34297 12:34:33.591744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
34298 12:34:33.635841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass>
34299 12:34:33.636227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass
34301 12:34:33.679007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
34302 12:34:33.679431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass
34304 12:34:33.716143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
34305 12:34:33.716561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
34307 12:34:33.755070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass>
34308 12:34:33.755470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass
34310 12:34:33.793355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass
34312 12:34:33.793835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
34313 12:34:33.833763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass>
34314 12:34:33.834129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass
34316 12:34:33.873269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
34317 12:34:33.873688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
34319 12:34:33.911146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass>
34320 12:34:33.911565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass
34322 12:34:33.951257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass
34324 12:34:33.951721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
34325 12:34:33.986803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
34326 12:34:33.987154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
34328 12:34:34.026691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass>
34329 12:34:34.027069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass
34331 12:34:34.071622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
34332 12:34:34.072055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass
34334 12:34:34.107371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
34336 12:34:34.107831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
34337 12:34:34.143868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass>
34338 12:34:34.144286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass
34340 12:34:34.181521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass
34342 12:34:34.182118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
34343 12:34:34.220617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
34344 12:34:34.221039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
34346 12:34:34.259515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass>
34347 12:34:34.259919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass
34349 12:34:34.301696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass
34351 12:34:34.302174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
34352 12:34:34.352111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
34354 12:34:34.352830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
34355 12:34:34.389001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass
34357 12:34:34.389853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass>
34358 12:34:34.448335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
34359 12:34:34.448792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass
34361 12:34:34.497856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass
34363 12:34:34.498349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass>
34364 12:34:34.546826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
34365 12:34:34.547249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
34367 12:34:34.588145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass>
34368 12:34:34.588623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass
34370 12:34:34.644398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
34371 12:34:34.644860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass
34373 12:34:34.699441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
34374 12:34:34.699846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
34376 12:34:34.748323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass
34378 12:34:34.748732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass>
34379 12:34:34.793086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
34380 12:34:34.793480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass
34382 12:34:34.845410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
34383 12:34:34.845771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
34385 12:34:34.885310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass>
34386 12:34:34.885675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass
34388 12:34:34.923796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass
34390 12:34:34.924345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
34391 12:34:34.963124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
34393 12:34:34.963651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
34394 12:34:35.020076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass
34396 12:34:35.020464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass>
34397 12:34:35.071126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
34398 12:34:35.071501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass
34400 12:34:35.127690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
34401 12:34:35.128141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
34403 12:34:35.185668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass>
34404 12:34:35.186097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass
34406 12:34:35.243987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
34407 12:34:35.244384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass
34409 12:34:35.285301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass
34411 12:34:35.285900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass>
34412 12:34:35.327372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
34414 12:34:35.327927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
34415 12:34:35.377486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass
34417 12:34:35.377985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass>
34418 12:34:35.422931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass
34420 12:34:35.423380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
34421 12:34:35.464826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
34423 12:34:35.465415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
34424 12:34:35.499203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass>
34425 12:34:35.499747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass
34427 12:34:35.534528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
34428 12:34:35.535008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass
34430 12:34:35.572796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
34432 12:34:35.573218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
34433 12:34:35.615771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass
34435 12:34:35.616243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass>
34436 12:34:35.660885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass
34438 12:34:35.661313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
34439 12:34:35.699894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
34440 12:34:35.700447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
34442 12:34:35.749164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass>
34443 12:34:35.749708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass
34445 12:34:35.800031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
34446 12:34:35.800459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass
34448 12:34:35.849308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
34450 12:34:35.849898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
34451 12:34:35.898734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass
34453 12:34:35.899211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass>
34454 12:34:35.938679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
34455 12:34:35.939125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass
34457 12:34:35.987754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass
34459 12:34:35.988206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass>
34460 12:34:36.035753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
34461 12:34:36.036191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
34463 12:34:36.076943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass>
34464 12:34:36.077369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass
34466 12:34:36.116911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass
34468 12:34:36.117400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
34469 12:34:36.152748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
34470 12:34:36.153179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
34472 12:34:36.191184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass>
34473 12:34:36.191620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass
34475 12:34:36.227619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
34476 12:34:36.228136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass
34478 12:34:36.265978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
34480 12:34:36.266456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
34481 12:34:36.301813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass
34483 12:34:36.302289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass>
34484 12:34:36.337942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
34485 12:34:36.338366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass
34487 12:34:36.374979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
34488 12:34:36.375420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
34490 12:34:36.424161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass
34492 12:34:36.424741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass>
34493 12:34:36.461291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass
34495 12:34:36.461731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
34496 12:34:36.497409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
34497 12:34:36.497936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
34499 12:34:36.532440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass>
34500 12:34:36.533696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass
34502 12:34:36.578224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass
34504 12:34:36.578604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
34505 12:34:36.621590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass>
34506 12:34:36.622059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass
34508 12:34:36.660139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
34509 12:34:36.660583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
34511 12:34:36.696492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass>
34512 12:34:36.696981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass
34514 12:34:36.733799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
34515 12:34:36.734209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass
34517 12:34:36.776023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
34518 12:34:36.776356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
34520 12:34:36.822596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass>
34521 12:34:36.822980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass
34523 12:34:36.857277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
34524 12:34:36.857686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass
34526 12:34:36.892450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
34528 12:34:36.892923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
34529 12:34:36.927297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass>
34530 12:34:36.927687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass
34532 12:34:36.964750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
34533 12:34:36.965142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass
34535 12:34:37.012753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
34537 12:34:37.013307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
34538 12:34:37.048599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass
34540 12:34:37.049127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass>
34541 12:34:37.091924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass
34543 12:34:37.092404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
34544 12:34:37.128004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
34545 12:34:37.128410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
34547 12:34:37.161600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass
34549 12:34:37.162087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass>
34550 12:34:37.196035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
34551 12:34:37.196415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass
34553 12:34:37.233663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
34555 12:34:37.234401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
34556 12:34:37.270195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass
34558 12:34:37.270659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass>
34559 12:34:37.308789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass>
34560 12:34:37.309284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass
34562 12:34:37.352215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass>
34563 12:34:37.352753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass
34565 12:34:37.396309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass
34567 12:34:37.396877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass>
34568 12:34:37.440582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass
34570 12:34:37.441148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass>
34571 12:34:37.478921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
34572 12:34:37.479353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
34574 12:34:37.482670 + set +x
34575 12:34:37.482920 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64_qemu 568933_1.1.3.5>
34576 12:34:37.483225 Received signal: <ENDRUN> 1_kselftest-arm64_qemu 568933_1.1.3.5
34577 12:34:37.483352 Ending use of test pattern.
34578 12:34:37.483452 Ending test lava.1_kselftest-arm64_qemu (568933_1.1.3.5), duration 406.05
34580 12:34:37.486091 ok: lava_test_shell seems to have completed
34581 12:34:37.573060 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: pass
arm64_btitest_bti_c_func_call_using_br_x0: pass
arm64_btitest_bti_c_func_call_using_br_x16: pass
arm64_btitest_bti_j_func_call_using_blr: pass
arm64_btitest_bti_j_func_call_using_br_x0: pass
arm64_btitest_bti_j_func_call_using_br_x16: pass
arm64_btitest_bti_jc_func_call_using_blr: pass
arm64_btitest_bti_jc_func_call_using_br_x0: pass
arm64_btitest_bti_jc_func_call_using_br_x16: pass
arm64_btitest_bti_none_func_call_using_blr: pass
arm64_btitest_bti_none_func_call_using_br_x0: pass
arm64_btitest_bti_none_func_call_using_br_x16: pass
arm64_btitest_nohint_func_call_using_blr: pass
arm64_btitest_nohint_func_call_using_br_x0: pass
arm64_btitest_nohint_func_call_using_br_x16: pass
arm64_btitest_paciasp_func_call_using_blr: pass
arm64_btitest_paciasp_func_call_using_br_x0: pass
arm64_btitest_paciasp_func_call_using_br_x16: pass
arm64_check_buffer_fill: fail
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_child_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_gcr_el1_cswitch: fail
arm64_check_ksm_options: fail
arm64_check_mmap_options: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: pass
arm64_check_prctl_SYNC_ASYNC: pass
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: fail
arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode: pass
arm64_check_user_mem: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: pass
arm64_fake_sigreturn_sve_change_vl: pass
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_SSVE-VL-128-0: pass
arm64_fp-stress_SSVE-VL-16-0: pass
arm64_fp-stress_SSVE-VL-256-0: pass
arm64_fp-stress_SSVE-VL-32-0: pass
arm64_fp-stress_SSVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-112-0: pass
arm64_fp-stress_SVE-VL-128-0: pass
arm64_fp-stress_SVE-VL-144-0: pass
arm64_fp-stress_SVE-VL-16-0: pass
arm64_fp-stress_SVE-VL-160-0: pass
arm64_fp-stress_SVE-VL-176-0: pass
arm64_fp-stress_SVE-VL-192-0: pass
arm64_fp-stress_SVE-VL-208-0: pass
arm64_fp-stress_SVE-VL-224-0: pass
arm64_fp-stress_SVE-VL-240-0: pass
arm64_fp-stress_SVE-VL-256-0: pass
arm64_fp-stress_SVE-VL-32-0: pass
arm64_fp-stress_SVE-VL-48-0: pass
arm64_fp-stress_SVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-80-0: pass
arm64_fp-stress_SVE-VL-96-0: pass
arm64_fp-stress_ZA-VL-128-0: pass
arm64_fp-stress_ZA-VL-16-0: pass
arm64_fp-stress_ZA-VL-256-0: pass
arm64_fp-stress_ZA-VL-32-0: pass
arm64_fp-stress_ZA-VL-64-0: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SM4: pass
arm64_hwcap_sigill_SVE_2: pass
arm64_hwcap_sigill_SVE_AES: pass
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: pass
arm64_nobtitest_bti_c_func_call_using_br_x0: pass
arm64_nobtitest_bti_c_func_call_using_br_x16: pass
arm64_nobtitest_bti_j_func_call_using_blr: pass
arm64_nobtitest_bti_j_func_call_using_br_x0: pass
arm64_nobtitest_bti_j_func_call_using_br_x16: pass
arm64_nobtitest_bti_jc_func_call_using_blr: pass
arm64_nobtitest_bti_jc_func_call_using_br_x0: pass
arm64_nobtitest_bti_jc_func_call_using_br_x16: pass
arm64_nobtitest_bti_none_func_call_using_blr: pass
arm64_nobtitest_bti_none_func_call_using_br_x0: pass
arm64_nobtitest_bti_none_func_call_using_br_x16: pass
arm64_nobtitest_nohint_func_call_using_blr: pass
arm64_nobtitest_nohint_func_call_using_br_x0: pass
arm64_nobtitest_nohint_func_call_using_br_x16: pass
arm64_nobtitest_paciasp_func_call_using_blr: pass
arm64_nobtitest_paciasp_func_call_using_br_x0: pass
arm64_nobtitest_paciasp_func_call_using_br_x16: pass
arm64_pac: pass
arm64_pac_global_context_switch_keep_keys: pass
arm64_pac_global_context_switch_keep_keys_generic: pass
arm64_pac_global_corrupt_pac: pass
arm64_pac_global_exec_changed_keys: pass
arm64_pac_global_pac_instructions_not_nop: pass
arm64_pac_global_pac_instructions_not_nop_generic: pass
arm64_pac_global_single_thread_different_keys: pass
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: pass
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: pass
arm64_ssve_regs: pass
arm64_sve-probe-vls: pass
arm64_sve-probe-vls_All_vector_lengths_valid: pass
arm64_sve-probe-vls_Enumerated_16_vector_lengths: pass
arm64_sve-ptrace: pass
arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_1008: pass
arm64_sve-ptrace_Set_SVE_VL_1024: pass
arm64_sve-ptrace_Set_SVE_VL_1040: pass
arm64_sve-ptrace_Set_SVE_VL_1056: pass
arm64_sve-ptrace_Set_SVE_VL_1072: pass
arm64_sve-ptrace_Set_SVE_VL_1088: pass
arm64_sve-ptrace_Set_SVE_VL_1104: pass
arm64_sve-ptrace_Set_SVE_VL_112: pass
arm64_sve-ptrace_Set_SVE_VL_1120: pass
arm64_sve-ptrace_Set_SVE_VL_1136: pass
arm64_sve-ptrace_Set_SVE_VL_1152: pass
arm64_sve-ptrace_Set_SVE_VL_1168: pass
arm64_sve-ptrace_Set_SVE_VL_1184: pass
arm64_sve-ptrace_Set_SVE_VL_1200: pass
arm64_sve-ptrace_Set_SVE_VL_1216: pass
arm64_sve-ptrace_Set_SVE_VL_1232: pass
arm64_sve-ptrace_Set_SVE_VL_1248: pass
arm64_sve-ptrace_Set_SVE_VL_1264: pass
arm64_sve-ptrace_Set_SVE_VL_128: pass
arm64_sve-ptrace_Set_SVE_VL_1280: pass
arm64_sve-ptrace_Set_SVE_VL_1296: pass
arm64_sve-ptrace_Set_SVE_VL_1312: pass
arm64_sve-ptrace_Set_SVE_VL_1328: pass
arm64_sve-ptrace_Set_SVE_VL_1344: pass
arm64_sve-ptrace_Set_SVE_VL_1360: pass
arm64_sve-ptrace_Set_SVE_VL_1376: pass
arm64_sve-ptrace_Set_SVE_VL_1392: pass
arm64_sve-ptrace_Set_SVE_VL_1408: pass
arm64_sve-ptrace_Set_SVE_VL_1424: pass
arm64_sve-ptrace_Set_SVE_VL_144: pass
arm64_sve-ptrace_Set_SVE_VL_1440: pass
arm64_sve-ptrace_Set_SVE_VL_1456: pass
arm64_sve-ptrace_Set_SVE_VL_1472: pass
arm64_sve-ptrace_Set_SVE_VL_1488: pass
arm64_sve-ptrace_Set_SVE_VL_1504: pass
arm64_sve-ptrace_Set_SVE_VL_1520: pass
arm64_sve-ptrace_Set_SVE_VL_1536: pass
arm64_sve-ptrace_Set_SVE_VL_1552: pass
arm64_sve-ptrace_Set_SVE_VL_1568: pass
arm64_sve-ptrace_Set_SVE_VL_1584: pass
arm64_sve-ptrace_Set_SVE_VL_16: pass
arm64_sve-ptrace_Set_SVE_VL_160: pass
arm64_sve-ptrace_Set_SVE_VL_1600: pass
arm64_sve-ptrace_Set_SVE_VL_1616: pass
arm64_sve-ptrace_Set_SVE_VL_1632: pass
arm64_sve-ptrace_Set_SVE_VL_1648: pass
arm64_sve-ptrace_Set_SVE_VL_1664: pass
arm64_sve-ptrace_Set_SVE_VL_1680: pass
arm64_sve-ptrace_Set_SVE_VL_1696: pass
arm64_sve-ptrace_Set_SVE_VL_1712: pass
arm64_sve-ptrace_Set_SVE_VL_1728: pass
arm64_sve-ptrace_Set_SVE_VL_1744: pass
arm64_sve-ptrace_Set_SVE_VL_176: pass
arm64_sve-ptrace_Set_SVE_VL_1760: pass
arm64_sve-ptrace_Set_SVE_VL_1776: pass
arm64_sve-ptrace_Set_SVE_VL_1792: pass
arm64_sve-ptrace_Set_SVE_VL_1808: pass
arm64_sve-ptrace_Set_SVE_VL_1824: pass
arm64_sve-ptrace_Set_SVE_VL_1840: pass
arm64_sve-ptrace_Set_SVE_VL_1856: pass
arm64_sve-ptrace_Set_SVE_VL_1872: pass
arm64_sve-ptrace_Set_SVE_VL_1888: pass
arm64_sve-ptrace_Set_SVE_VL_1904: pass
arm64_sve-ptrace_Set_SVE_VL_192: pass
arm64_sve-ptrace_Set_SVE_VL_1920: pass
arm64_sve-ptrace_Set_SVE_VL_1936: pass
arm64_sve-ptrace_Set_SVE_VL_1952: pass
arm64_sve-ptrace_Set_SVE_VL_1968: pass
arm64_sve-ptrace_Set_SVE_VL_1984: pass
arm64_sve-ptrace_Set_SVE_VL_2000: pass
arm64_sve-ptrace_Set_SVE_VL_2016: pass
arm64_sve-ptrace_Set_SVE_VL_2032: pass
arm64_sve-ptrace_Set_SVE_VL_2048: pass
arm64_sve-ptrace_Set_SVE_VL_2064: pass
arm64_sve-ptrace_Set_SVE_VL_208: pass
arm64_sve-ptrace_Set_SVE_VL_2080: pass
arm64_sve-ptrace_Set_SVE_VL_2096: pass
arm64_sve-ptrace_Set_SVE_VL_2112: pass
arm64_sve-ptrace_Set_SVE_VL_2128: pass
arm64_sve-ptrace_Set_SVE_VL_2144: pass
arm64_sve-ptrace_Set_SVE_VL_2160: pass
arm64_sve-ptrace_Set_SVE_VL_2176: pass
arm64_sve-ptrace_Set_SVE_VL_2192: pass
arm64_sve-ptrace_Set_SVE_VL_2208: pass
arm64_sve-ptrace_Set_SVE_VL_2224: pass
arm64_sve-ptrace_Set_SVE_VL_224: pass
arm64_sve-ptrace_Set_SVE_VL_2240: pass
arm64_sve-ptrace_Set_SVE_VL_2256: pass
arm64_sve-ptrace_Set_SVE_VL_2272: pass
arm64_sve-ptrace_Set_SVE_VL_2288: pass
arm64_sve-ptrace_Set_SVE_VL_2304: pass
arm64_sve-ptrace_Set_SVE_VL_2320: pass
arm64_sve-ptrace_Set_SVE_VL_2336: pass
arm64_sve-ptrace_Set_SVE_VL_2352: pass
arm64_sve-ptrace_Set_SVE_VL_2368: pass
arm64_sve-ptrace_Set_SVE_VL_2384: pass
arm64_sve-ptrace_Set_SVE_VL_240: pass
arm64_sve-ptrace_Set_SVE_VL_2400: pass
arm64_sve-ptrace_Set_SVE_VL_2416: pass
arm64_sve-ptrace_Set_SVE_VL_2432: pass
arm64_sve-ptrace_Set_SVE_VL_2448: pass
arm64_sve-ptrace_Set_SVE_VL_2464: pass
arm64_sve-ptrace_Set_SVE_VL_2480: pass
arm64_sve-ptrace_Set_SVE_VL_2496: pass
arm64_sve-ptrace_Set_SVE_VL_2512: pass
arm64_sve-ptrace_Set_SVE_VL_2528: pass
arm64_sve-ptrace_Set_SVE_VL_2544: pass
arm64_sve-ptrace_Set_SVE_VL_256: pass
arm64_sve-ptrace_Set_SVE_VL_2560: pass
arm64_sve-ptrace_Set_SVE_VL_2576: pass
arm64_sve-ptrace_Set_SVE_VL_2592: pass
arm64_sve-ptrace_Set_SVE_VL_2608: pass
arm64_sve-ptrace_Set_SVE_VL_2624: pass
arm64_sve-ptrace_Set_SVE_VL_2640: pass
arm64_sve-ptrace_Set_SVE_VL_2656: pass
arm64_sve-ptrace_Set_SVE_VL_2672: pass
arm64_sve-ptrace_Set_SVE_VL_2688: pass
arm64_sve-ptrace_Set_SVE_VL_2704: pass
arm64_sve-ptrace_Set_SVE_VL_272: pass
arm64_sve-ptrace_Set_SVE_VL_2720: pass
arm64_sve-ptrace_Set_SVE_VL_2736: pass
arm64_sve-ptrace_Set_SVE_VL_2752: pass
arm64_sve-ptrace_Set_SVE_VL_2768: pass
arm64_sve-ptrace_Set_SVE_VL_2784: pass
arm64_sve-ptrace_Set_SVE_VL_2800: pass
arm64_sve-ptrace_Set_SVE_VL_2816: pass
arm64_sve-ptrace_Set_SVE_VL_2832: pass
arm64_sve-ptrace_Set_SVE_VL_2848: pass
arm64_sve-ptrace_Set_SVE_VL_2864: pass
arm64_sve-ptrace_Set_SVE_VL_288: pass
arm64_sve-ptrace_Set_SVE_VL_2880: pass
arm64_sve-ptrace_Set_SVE_VL_2896: pass
arm64_sve-ptrace_Set_SVE_VL_2912: pass
arm64_sve-ptrace_Set_SVE_VL_2928: pass
arm64_sve-ptrace_Set_SVE_VL_2944: pass
arm64_sve-ptrace_Set_SVE_VL_2960: pass
arm64_sve-ptrace_Set_SVE_VL_2976: pass
arm64_sve-ptrace_Set_SVE_VL_2992: pass
arm64_sve-ptrace_Set_SVE_VL_3008: pass
arm64_sve-ptrace_Set_SVE_VL_3024: pass
arm64_sve-ptrace_Set_SVE_VL_304: pass
arm64_sve-ptrace_Set_SVE_VL_3040: pass
arm64_sve-ptrace_Set_SVE_VL_3056: pass
arm64_sve-ptrace_Set_SVE_VL_3072: pass
arm64_sve-ptrace_Set_SVE_VL_3088: pass
arm64_sve-ptrace_Set_SVE_VL_3104: pass
arm64_sve-ptrace_Set_SVE_VL_3120: pass
arm64_sve-ptrace_Set_SVE_VL_3136: pass
arm64_sve-ptrace_Set_SVE_VL_3152: pass
arm64_sve-ptrace_Set_SVE_VL_3168: pass
arm64_sve-ptrace_Set_SVE_VL_3184: pass
arm64_sve-ptrace_Set_SVE_VL_32: pass
arm64_sve-ptrace_Set_SVE_VL_320: pass
arm64_sve-ptrace_Set_SVE_VL_3200: pass
arm64_sve-ptrace_Set_SVE_VL_3216: pass
arm64_sve-ptrace_Set_SVE_VL_3232: pass
arm64_sve-ptrace_Set_SVE_VL_3248: pass
arm64_sve-ptrace_Set_SVE_VL_3264: pass
arm64_sve-ptrace_Set_SVE_VL_3280: pass
arm64_sve-ptrace_Set_SVE_VL_3296: pass
arm64_sve-ptrace_Set_SVE_VL_3312: pass
arm64_sve-ptrace_Set_SVE_VL_3328: pass
arm64_sve-ptrace_Set_SVE_VL_3344: pass
arm64_sve-ptrace_Set_SVE_VL_336: pass
arm64_sve-ptrace_Set_SVE_VL_3360: pass
arm64_sve-ptrace_Set_SVE_VL_3376: pass
arm64_sve-ptrace_Set_SVE_VL_3392: pass
arm64_sve-ptrace_Set_SVE_VL_3408: pass
arm64_sve-ptrace_Set_SVE_VL_3424: pass
arm64_sve-ptrace_Set_SVE_VL_3440: pass
arm64_sve-ptrace_Set_SVE_VL_3456: pass
arm64_sve-ptrace_Set_SVE_VL_3472: pass
arm64_sve-ptrace_Set_SVE_VL_3488: pass
arm64_sve-ptrace_Set_SVE_VL_3504: pass
arm64_sve-ptrace_Set_SVE_VL_352: pass
arm64_sve-ptrace_Set_SVE_VL_3520: pass
arm64_sve-ptrace_Set_SVE_VL_3536: pass
arm64_sve-ptrace_Set_SVE_VL_3552: pass
arm64_sve-ptrace_Set_SVE_VL_3568: pass
arm64_sve-ptrace_Set_SVE_VL_3584: pass
arm64_sve-ptrace_Set_SVE_VL_3600: pass
arm64_sve-ptrace_Set_SVE_VL_3616: pass
arm64_sve-ptrace_Set_SVE_VL_3632: pass
arm64_sve-ptrace_Set_SVE_VL_3648: pass
arm64_sve-ptrace_Set_SVE_VL_3664: pass
arm64_sve-ptrace_Set_SVE_VL_368: pass
arm64_sve-ptrace_Set_SVE_VL_3680: pass
arm64_sve-ptrace_Set_SVE_VL_3696: pass
arm64_sve-ptrace_Set_SVE_VL_3712: pass
arm64_sve-ptrace_Set_SVE_VL_3728: pass
arm64_sve-ptrace_Set_SVE_VL_3744: pass
arm64_sve-ptrace_Set_SVE_VL_3760: pass
arm64_sve-ptrace_Set_SVE_VL_3776: pass
arm64_sve-ptrace_Set_SVE_VL_3792: pass
arm64_sve-ptrace_Set_SVE_VL_3808: pass
arm64_sve-ptrace_Set_SVE_VL_3824: pass
arm64_sve-ptrace_Set_SVE_VL_384: pass
arm64_sve-ptrace_Set_SVE_VL_3840: pass
arm64_sve-ptrace_Set_SVE_VL_3856: pass
arm64_sve-ptrace_Set_SVE_VL_3872: pass
arm64_sve-ptrace_Set_SVE_VL_3888: pass
arm64_sve-ptrace_Set_SVE_VL_3904: pass
arm64_sve-ptrace_Set_SVE_VL_3920: pass
arm64_sve-ptrace_Set_SVE_VL_3936: pass
arm64_sve-ptrace_Set_SVE_VL_3952: pass
arm64_sve-ptrace_Set_SVE_VL_3968: pass
arm64_sve-ptrace_Set_SVE_VL_3984: pass
arm64_sve-ptrace_Set_SVE_VL_400: pass
arm64_sve-ptrace_Set_SVE_VL_4000: pass
arm64_sve-ptrace_Set_SVE_VL_4016: pass
arm64_sve-ptrace_Set_SVE_VL_4032: pass
arm64_sve-ptrace_Set_SVE_VL_4048: pass
arm64_sve-ptrace_Set_SVE_VL_4064: pass
arm64_sve-ptrace_Set_SVE_VL_4080: pass
arm64_sve-ptrace_Set_SVE_VL_4096: pass
arm64_sve-ptrace_Set_SVE_VL_4112: pass
arm64_sve-ptrace_Set_SVE_VL_4128: pass
arm64_sve-ptrace_Set_SVE_VL_4144: pass
arm64_sve-ptrace_Set_SVE_VL_416: pass
arm64_sve-ptrace_Set_SVE_VL_4160: pass
arm64_sve-ptrace_Set_SVE_VL_4176: pass
arm64_sve-ptrace_Set_SVE_VL_4192: pass
arm64_sve-ptrace_Set_SVE_VL_4208: pass
arm64_sve-ptrace_Set_SVE_VL_4224: pass
arm64_sve-ptrace_Set_SVE_VL_4240: pass
arm64_sve-ptrace_Set_SVE_VL_4256: pass
arm64_sve-ptrace_Set_SVE_VL_4272: pass
arm64_sve-ptrace_Set_SVE_VL_4288: pass
arm64_sve-ptrace_Set_SVE_VL_4304: pass
arm64_sve-ptrace_Set_SVE_VL_432: pass
arm64_sve-ptrace_Set_SVE_VL_4320: pass
arm64_sve-ptrace_Set_SVE_VL_4336: pass
arm64_sve-ptrace_Set_SVE_VL_4352: pass
arm64_sve-ptrace_Set_SVE_VL_4368: pass
arm64_sve-ptrace_Set_SVE_VL_4384: pass
arm64_sve-ptrace_Set_SVE_VL_4400: pass
arm64_sve-ptrace_Set_SVE_VL_4416: pass
arm64_sve-ptrace_Set_SVE_VL_4432: pass
arm64_sve-ptrace_Set_SVE_VL_4448: pass
arm64_sve-ptrace_Set_SVE_VL_4464: pass
arm64_sve-ptrace_Set_SVE_VL_448: pass
arm64_sve-ptrace_Set_SVE_VL_4480: pass
arm64_sve-ptrace_Set_SVE_VL_4496: pass
arm64_sve-ptrace_Set_SVE_VL_4512: pass
arm64_sve-ptrace_Set_SVE_VL_4528: pass
arm64_sve-ptrace_Set_SVE_VL_4544: pass
arm64_sve-ptrace_Set_SVE_VL_4560: pass
arm64_sve-ptrace_Set_SVE_VL_4576: pass
arm64_sve-ptrace_Set_SVE_VL_4592: pass
arm64_sve-ptrace_Set_SVE_VL_4608: pass
arm64_sve-ptrace_Set_SVE_VL_4624: pass
arm64_sve-ptrace_Set_SVE_VL_464: pass
arm64_sve-ptrace_Set_SVE_VL_4640: pass
arm64_sve-ptrace_Set_SVE_VL_4656: pass
arm64_sve-ptrace_Set_SVE_VL_4672: pass
arm64_sve-ptrace_Set_SVE_VL_4688: pass
arm64_sve-ptrace_Set_SVE_VL_4704: pass
arm64_sve-ptrace_Set_SVE_VL_4720: pass
arm64_sve-ptrace_Set_SVE_VL_4736: pass
arm64_sve-ptrace_Set_SVE_VL_4752: pass
arm64_sve-ptrace_Set_SVE_VL_4768: pass
arm64_sve-ptrace_Set_SVE_VL_4784: pass
arm64_sve-ptrace_Set_SVE_VL_48: pass
arm64_sve-ptrace_Set_SVE_VL_480: pass
arm64_sve-ptrace_Set_SVE_VL_4800: pass
arm64_sve-ptrace_Set_SVE_VL_4816: pass
arm64_sve-ptrace_Set_SVE_VL_4832: pass
arm64_sve-ptrace_Set_SVE_VL_4848: pass
arm64_sve-ptrace_Set_SVE_VL_4864: pass
arm64_sve-ptrace_Set_SVE_VL_4880: pass
arm64_sve-ptrace_Set_SVE_VL_4896: pass
arm64_sve-ptrace_Set_SVE_VL_4912: pass
arm64_sve-ptrace_Set_SVE_VL_4928: pass
arm64_sve-ptrace_Set_SVE_VL_4944: pass
arm64_sve-ptrace_Set_SVE_VL_496: pass
arm64_sve-ptrace_Set_SVE_VL_4960: pass
arm64_sve-ptrace_Set_SVE_VL_4976: pass
arm64_sve-ptrace_Set_SVE_VL_4992: pass
arm64_sve-ptrace_Set_SVE_VL_5008: pass
arm64_sve-ptrace_Set_SVE_VL_5024: pass
arm64_sve-ptrace_Set_SVE_VL_5040: pass
arm64_sve-ptrace_Set_SVE_VL_5056: pass
arm64_sve-ptrace_Set_SVE_VL_5072: pass
arm64_sve-ptrace_Set_SVE_VL_5088: pass
arm64_sve-ptrace_Set_SVE_VL_5104: pass
arm64_sve-ptrace_Set_SVE_VL_512: pass
arm64_sve-ptrace_Set_SVE_VL_5120: pass
arm64_sve-ptrace_Set_SVE_VL_5136: pass
arm64_sve-ptrace_Set_SVE_VL_5152: pass
arm64_sve-ptrace_Set_SVE_VL_5168: pass
arm64_sve-ptrace_Set_SVE_VL_5184: pass
arm64_sve-ptrace_Set_SVE_VL_5200: pass
arm64_sve-ptrace_Set_SVE_VL_5216: pass
arm64_sve-ptrace_Set_SVE_VL_5232: pass
arm64_sve-ptrace_Set_SVE_VL_5248: pass
arm64_sve-ptrace_Set_SVE_VL_5264: pass
arm64_sve-ptrace_Set_SVE_VL_528: pass
arm64_sve-ptrace_Set_SVE_VL_5280: pass
arm64_sve-ptrace_Set_SVE_VL_5296: pass
arm64_sve-ptrace_Set_SVE_VL_5312: pass
arm64_sve-ptrace_Set_SVE_VL_5328: pass
arm64_sve-ptrace_Set_SVE_VL_5344: pass
arm64_sve-ptrace_Set_SVE_VL_5360: pass
arm64_sve-ptrace_Set_SVE_VL_5376: pass
arm64_sve-ptrace_Set_SVE_VL_5392: pass
arm64_sve-ptrace_Set_SVE_VL_5408: pass
arm64_sve-ptrace_Set_SVE_VL_5424: pass
arm64_sve-ptrace_Set_SVE_VL_544: pass
arm64_sve-ptrace_Set_SVE_VL_5440: pass
arm64_sve-ptrace_Set_SVE_VL_5456: pass
arm64_sve-ptrace_Set_SVE_VL_5472: pass
arm64_sve-ptrace_Set_SVE_VL_5488: pass
arm64_sve-ptrace_Set_SVE_VL_5504: pass
arm64_sve-ptrace_Set_SVE_VL_5520: pass
arm64_sve-ptrace_Set_SVE_VL_5536: pass
arm64_sve-ptrace_Set_SVE_VL_5552: pass
arm64_sve-ptrace_Set_SVE_VL_5568: pass
arm64_sve-ptrace_Set_SVE_VL_5584: pass
arm64_sve-ptrace_Set_SVE_VL_560: pass
arm64_sve-ptrace_Set_SVE_VL_5600: pass
arm64_sve-ptrace_Set_SVE_VL_5616: pass
arm64_sve-ptrace_Set_SVE_VL_5632: pass
arm64_sve-ptrace_Set_SVE_VL_5648: pass
arm64_sve-ptrace_Set_SVE_VL_5664: pass
arm64_sve-ptrace_Set_SVE_VL_5680: pass
arm64_sve-ptrace_Set_SVE_VL_5696: pass
arm64_sve-ptrace_Set_SVE_VL_5712: pass
arm64_sve-ptrace_Set_SVE_VL_5728: pass
arm64_sve-ptrace_Set_SVE_VL_5744: pass
arm64_sve-ptrace_Set_SVE_VL_576: pass
arm64_sve-ptrace_Set_SVE_VL_5760: pass
arm64_sve-ptrace_Set_SVE_VL_5776: pass
arm64_sve-ptrace_Set_SVE_VL_5792: pass
arm64_sve-ptrace_Set_SVE_VL_5808: pass
arm64_sve-ptrace_Set_SVE_VL_5824: pass
arm64_sve-ptrace_Set_SVE_VL_5840: pass
arm64_sve-ptrace_Set_SVE_VL_5856: pass
arm64_sve-ptrace_Set_SVE_VL_5872: pass
arm64_sve-ptrace_Set_SVE_VL_5888: pass
arm64_sve-ptrace_Set_SVE_VL_5904: pass
arm64_sve-ptrace_Set_SVE_VL_592: pass
arm64_sve-ptrace_Set_SVE_VL_5920: pass
arm64_sve-ptrace_Set_SVE_VL_5936: pass
arm64_sve-ptrace_Set_SVE_VL_5952: pass
arm64_sve-ptrace_Set_SVE_VL_5968: pass
arm64_sve-ptrace_Set_SVE_VL_5984: pass
arm64_sve-ptrace_Set_SVE_VL_6000: pass
arm64_sve-ptrace_Set_SVE_VL_6016: pass
arm64_sve-ptrace_Set_SVE_VL_6032: pass
arm64_sve-ptrace_Set_SVE_VL_6048: pass
arm64_sve-ptrace_Set_SVE_VL_6064: pass
arm64_sve-ptrace_Set_SVE_VL_608: pass
arm64_sve-ptrace_Set_SVE_VL_6080: pass
arm64_sve-ptrace_Set_SVE_VL_6096: pass
arm64_sve-ptrace_Set_SVE_VL_6112: pass
arm64_sve-ptrace_Set_SVE_VL_6128: pass
arm64_sve-ptrace_Set_SVE_VL_6144: pass
arm64_sve-ptrace_Set_SVE_VL_6160: pass
arm64_sve-ptrace_Set_SVE_VL_6176: pass
arm64_sve-ptrace_Set_SVE_VL_6192: pass
arm64_sve-ptrace_Set_SVE_VL_6208: pass
arm64_sve-ptrace_Set_SVE_VL_6224: pass
arm64_sve-ptrace_Set_SVE_VL_624: pass
arm64_sve-ptrace_Set_SVE_VL_6240: pass
arm64_sve-ptrace_Set_SVE_VL_6256: pass
arm64_sve-ptrace_Set_SVE_VL_6272: pass
arm64_sve-ptrace_Set_SVE_VL_6288: pass
arm64_sve-ptrace_Set_SVE_VL_6304: pass
arm64_sve-ptrace_Set_SVE_VL_6320: pass
arm64_sve-ptrace_Set_SVE_VL_6336: pass
arm64_sve-ptrace_Set_SVE_VL_6352: pass
arm64_sve-ptrace_Set_SVE_VL_6368: pass
arm64_sve-ptrace_Set_SVE_VL_6384: pass
arm64_sve-ptrace_Set_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_640: pass
arm64_sve-ptrace_Set_SVE_VL_6400: pass
arm64_sve-ptrace_Set_SVE_VL_6416: pass
arm64_sve-ptrace_Set_SVE_VL_6432: pass
arm64_sve-ptrace_Set_SVE_VL_6448: pass
arm64_sve-ptrace_Set_SVE_VL_6464: pass
arm64_sve-ptrace_Set_SVE_VL_6480: pass
arm64_sve-ptrace_Set_SVE_VL_6496: pass
arm64_sve-ptrace_Set_SVE_VL_6512: pass
arm64_sve-ptrace_Set_SVE_VL_6528: pass
arm64_sve-ptrace_Set_SVE_VL_6544: pass
arm64_sve-ptrace_Set_SVE_VL_656: pass
arm64_sve-ptrace_Set_SVE_VL_6560: pass
arm64_sve-ptrace_Set_SVE_VL_6576: pass
arm64_sve-ptrace_Set_SVE_VL_6592: pass
arm64_sve-ptrace_Set_SVE_VL_6608: pass
arm64_sve-ptrace_Set_SVE_VL_6624: pass
arm64_sve-ptrace_Set_SVE_VL_6640: pass
arm64_sve-ptrace_Set_SVE_VL_6656: pass
arm64_sve-ptrace_Set_SVE_VL_6672: pass
arm64_sve-ptrace_Set_SVE_VL_6688: pass
arm64_sve-ptrace_Set_SVE_VL_6704: pass
arm64_sve-ptrace_Set_SVE_VL_672: pass
arm64_sve-ptrace_Set_SVE_VL_6720: pass
arm64_sve-ptrace_Set_SVE_VL_6736: pass
arm64_sve-ptrace_Set_SVE_VL_6752: pass
arm64_sve-ptrace_Set_SVE_VL_6768: pass
arm64_sve-ptrace_Set_SVE_VL_6784: pass
arm64_sve-ptrace_Set_SVE_VL_6800: pass
arm64_sve-ptrace_Set_SVE_VL_6816: pass
arm64_sve-ptrace_Set_SVE_VL_6832: pass
arm64_sve-ptrace_Set_SVE_VL_6848: pass
arm64_sve-ptrace_Set_SVE_VL_6864: pass
arm64_sve-ptrace_Set_SVE_VL_688: pass
arm64_sve-ptrace_Set_SVE_VL_6880: pass
arm64_sve-ptrace_Set_SVE_VL_6896: pass
arm64_sve-ptrace_Set_SVE_VL_6912: pass
arm64_sve-ptrace_Set_SVE_VL_6928: pass
arm64_sve-ptrace_Set_SVE_VL_6944: pass
arm64_sve-ptrace_Set_SVE_VL_6960: pass
arm64_sve-ptrace_Set_SVE_VL_6976: pass
arm64_sve-ptrace_Set_SVE_VL_6992: pass
arm64_sve-ptrace_Set_SVE_VL_7008: pass
arm64_sve-ptrace_Set_SVE_VL_7024: pass
arm64_sve-ptrace_Set_SVE_VL_704: pass
arm64_sve-ptrace_Set_SVE_VL_7040: pass
arm64_sve-ptrace_Set_SVE_VL_7056: pass
arm64_sve-ptrace_Set_SVE_VL_7072: pass
arm64_sve-ptrace_Set_SVE_VL_7088: pass
arm64_sve-ptrace_Set_SVE_VL_7104: pass
arm64_sve-ptrace_Set_SVE_VL_7120: pass
arm64_sve-ptrace_Set_SVE_VL_7136: pass
arm64_sve-ptrace_Set_SVE_VL_7152: pass
arm64_sve-ptrace_Set_SVE_VL_7168: pass
arm64_sve-ptrace_Set_SVE_VL_7184: pass
arm64_sve-ptrace_Set_SVE_VL_720: pass
arm64_sve-ptrace_Set_SVE_VL_7200: pass
arm64_sve-ptrace_Set_SVE_VL_7216: pass
arm64_sve-ptrace_Set_SVE_VL_7232: pass
arm64_sve-ptrace_Set_SVE_VL_7248: pass
arm64_sve-ptrace_Set_SVE_VL_7264: pass
arm64_sve-ptrace_Set_SVE_VL_7280: pass
arm64_sve-ptrace_Set_SVE_VL_7296: pass
arm64_sve-ptrace_Set_SVE_VL_7312: pass
arm64_sve-ptrace_Set_SVE_VL_7328: pass
arm64_sve-ptrace_Set_SVE_VL_7344: pass
arm64_sve-ptrace_Set_SVE_VL_736: pass
arm64_sve-ptrace_Set_SVE_VL_7360: pass
arm64_sve-ptrace_Set_SVE_VL_7376: pass
arm64_sve-ptrace_Set_SVE_VL_7392: pass
arm64_sve-ptrace_Set_SVE_VL_7408: pass
arm64_sve-ptrace_Set_SVE_VL_7424: pass
arm64_sve-ptrace_Set_SVE_VL_7440: pass
arm64_sve-ptrace_Set_SVE_VL_7456: pass
arm64_sve-ptrace_Set_SVE_VL_7472: pass
arm64_sve-ptrace_Set_SVE_VL_7488: pass
arm64_sve-ptrace_Set_SVE_VL_7504: pass
arm64_sve-ptrace_Set_SVE_VL_752: pass
arm64_sve-ptrace_Set_SVE_VL_7520: pass
arm64_sve-ptrace_Set_SVE_VL_7536: pass
arm64_sve-ptrace_Set_SVE_VL_7552: pass
arm64_sve-ptrace_Set_SVE_VL_7568: pass
arm64_sve-ptrace_Set_SVE_VL_7584: pass
arm64_sve-ptrace_Set_SVE_VL_7600: pass
arm64_sve-ptrace_Set_SVE_VL_7616: pass
arm64_sve-ptrace_Set_SVE_VL_7632: pass
arm64_sve-ptrace_Set_SVE_VL_7648: pass
arm64_sve-ptrace_Set_SVE_VL_7664: pass
arm64_sve-ptrace_Set_SVE_VL_768: pass
arm64_sve-ptrace_Set_SVE_VL_7680: pass
arm64_sve-ptrace_Set_SVE_VL_7696: pass
arm64_sve-ptrace_Set_SVE_VL_7712: pass
arm64_sve-ptrace_Set_SVE_VL_7728: pass
arm64_sve-ptrace_Set_SVE_VL_7744: pass
arm64_sve-ptrace_Set_SVE_VL_7760: pass
arm64_sve-ptrace_Set_SVE_VL_7776: pass
arm64_sve-ptrace_Set_SVE_VL_7792: pass
arm64_sve-ptrace_Set_SVE_VL_7808: pass
arm64_sve-ptrace_Set_SVE_VL_7824: pass
arm64_sve-ptrace_Set_SVE_VL_784: pass
arm64_sve-ptrace_Set_SVE_VL_7840: pass
arm64_sve-ptrace_Set_SVE_VL_7856: pass
arm64_sve-ptrace_Set_SVE_VL_7872: pass
arm64_sve-ptrace_Set_SVE_VL_7888: pass
arm64_sve-ptrace_Set_SVE_VL_7904: pass
arm64_sve-ptrace_Set_SVE_VL_7920: pass
arm64_sve-ptrace_Set_SVE_VL_7936: pass
arm64_sve-ptrace_Set_SVE_VL_7952: pass
arm64_sve-ptrace_Set_SVE_VL_7968: pass
arm64_sve-ptrace_Set_SVE_VL_7984: pass
arm64_sve-ptrace_Set_SVE_VL_80: pass
arm64_sve-ptrace_Set_SVE_VL_800: pass
arm64_sve-ptrace_Set_SVE_VL_8000: pass
arm64_sve-ptrace_Set_SVE_VL_8016: pass
arm64_sve-ptrace_Set_SVE_VL_8032: pass
arm64_sve-ptrace_Set_SVE_VL_8048: pass
arm64_sve-ptrace_Set_SVE_VL_8064: pass
arm64_sve-ptrace_Set_SVE_VL_8080: pass
arm64_sve-ptrace_Set_SVE_VL_8096: pass
arm64_sve-ptrace_Set_SVE_VL_8112: pass
arm64_sve-ptrace_Set_SVE_VL_8128: pass
arm64_sve-ptrace_Set_SVE_VL_8144: pass
arm64_sve-ptrace_Set_SVE_VL_816: pass
arm64_sve-ptrace_Set_SVE_VL_8160: pass
arm64_sve-ptrace_Set_SVE_VL_8176: pass
arm64_sve-ptrace_Set_SVE_VL_8192: pass
arm64_sve-ptrace_Set_SVE_VL_832: pass
arm64_sve-ptrace_Set_SVE_VL_848: pass
arm64_sve-ptrace_Set_SVE_VL_864: pass
arm64_sve-ptrace_Set_SVE_VL_880: pass
arm64_sve-ptrace_Set_SVE_VL_896: pass
arm64_sve-ptrace_Set_SVE_VL_912: pass
arm64_sve-ptrace_Set_SVE_VL_928: pass
arm64_sve-ptrace_Set_SVE_VL_944: pass
arm64_sve-ptrace_Set_SVE_VL_96: pass
arm64_sve-ptrace_Set_SVE_VL_960: pass
arm64_sve-ptrace_Set_SVE_VL_976: pass
arm64_sve-ptrace_Set_SVE_VL_992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_48: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_80: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_96: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_992: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve_regs: pass
arm64_sve_vl: pass
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_getpid_SVE_VL_112: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16: pass
arm64_syscall-abi_getpid_SVE_VL_160: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi_sched_yield_SVE_VL_112: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16: pass
arm64_syscall-abi_sched_yield_SVE_VL_160: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_default_value: pass
arm64_tpidr2_write_clone_read: pass
arm64_tpidr2_write_fork_read: pass
arm64_tpidr2_write_read: pass
arm64_tpidr2_write_sleep_read: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_current_VL_is_32: pass
arm64_vec-syscfg_SME_default_vector_length_32: pass
arm64_vec-syscfg_SME_maximum_vector_length_256: pass
arm64_vec-syscfg_SME_minimum_vector_length_16: pass
arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SME_prctl_set_min_max: pass
arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32: pass
arm64_vec-syscfg_SME_vector_length_set_on_exec: pass
arm64_vec-syscfg_SME_vector_length_used_default: pass
arm64_vec-syscfg_SME_vector_length_was_inherited: pass
arm64_vec-syscfg_SVE_current_VL_is_64: pass
arm64_vec-syscfg_SVE_default_vector_length_64: pass
arm64_vec-syscfg_SVE_maximum_vector_length_256: pass
arm64_vec-syscfg_SVE_minimum_vector_length_16: pass
arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SVE_prctl_set_min_max: pass
arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64: pass
arm64_vec-syscfg_SVE_vector_length_set_on_exec: pass
arm64_vec-syscfg_SVE_vector_length_used_default: pass
arm64_vec-syscfg_SVE_vector_length_was_inherited: pass
arm64_za-fork: pass
arm64_za-fork_fork_test: pass
arm64_za-ptrace: pass
arm64_za-ptrace_Data_match_for_VL_128: pass
arm64_za-ptrace_Data_match_for_VL_16: pass
arm64_za-ptrace_Data_match_for_VL_256: pass
arm64_za-ptrace_Data_match_for_VL_32: pass
arm64_za-ptrace_Data_match_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_128: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_16: pass
arm64_za-ptrace_Disabled_ZA_for_VL_160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_256: pass
arm64_za-ptrace_Disabled_ZA_for_VL_2560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_32: pass
arm64_za-ptrace_Disabled_ZA_for_VL_320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_48: skip
arm64_za-ptrace_Disabled_ZA_for_VL_480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_80: skip
arm64_za-ptrace_Disabled_ZA_for_VL_800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_96: skip
arm64_za-ptrace_Disabled_ZA_for_VL_960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_48: skip
arm64_za-ptrace_Get_and_set_data_for_VL_480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_80: skip
arm64_za-ptrace_Get_and_set_data_for_VL_800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_96: skip
arm64_za-ptrace_Get_and_set_data_for_VL_960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_992: skip
arm64_za-ptrace_Set_VL_1008: pass
arm64_za-ptrace_Set_VL_1024: pass
arm64_za-ptrace_Set_VL_1040: pass
arm64_za-ptrace_Set_VL_1056: pass
arm64_za-ptrace_Set_VL_1072: pass
arm64_za-ptrace_Set_VL_1088: pass
arm64_za-ptrace_Set_VL_1104: pass
arm64_za-ptrace_Set_VL_112: pass
arm64_za-ptrace_Set_VL_1120: pass
arm64_za-ptrace_Set_VL_1136: pass
arm64_za-ptrace_Set_VL_1152: pass
arm64_za-ptrace_Set_VL_1168: pass
arm64_za-ptrace_Set_VL_1184: pass
arm64_za-ptrace_Set_VL_1200: pass
arm64_za-ptrace_Set_VL_1216: pass
arm64_za-ptrace_Set_VL_1232: pass
arm64_za-ptrace_Set_VL_1248: pass
arm64_za-ptrace_Set_VL_1264: pass
arm64_za-ptrace_Set_VL_128: pass
arm64_za-ptrace_Set_VL_1280: pass
arm64_za-ptrace_Set_VL_1296: pass
arm64_za-ptrace_Set_VL_1312: pass
arm64_za-ptrace_Set_VL_1328: pass
arm64_za-ptrace_Set_VL_1344: pass
arm64_za-ptrace_Set_VL_1360: pass
arm64_za-ptrace_Set_VL_1376: pass
arm64_za-ptrace_Set_VL_1392: pass
arm64_za-ptrace_Set_VL_1408: pass
arm64_za-ptrace_Set_VL_1424: pass
arm64_za-ptrace_Set_VL_144: pass
arm64_za-ptrace_Set_VL_1440: pass
arm64_za-ptrace_Set_VL_1456: pass
arm64_za-ptrace_Set_VL_1472: pass
arm64_za-ptrace_Set_VL_1488: pass
arm64_za-ptrace_Set_VL_1504: pass
arm64_za-ptrace_Set_VL_1520: pass
arm64_za-ptrace_Set_VL_1536: pass
arm64_za-ptrace_Set_VL_1552: pass
arm64_za-ptrace_Set_VL_1568: pass
arm64_za-ptrace_Set_VL_1584: pass
arm64_za-ptrace_Set_VL_16: pass
arm64_za-ptrace_Set_VL_160: pass
arm64_za-ptrace_Set_VL_1600: pass
arm64_za-ptrace_Set_VL_1616: pass
arm64_za-ptrace_Set_VL_1632: pass
arm64_za-ptrace_Set_VL_1648: pass
arm64_za-ptrace_Set_VL_1664: pass
arm64_za-ptrace_Set_VL_1680: pass
arm64_za-ptrace_Set_VL_1696: pass
arm64_za-ptrace_Set_VL_1712: pass
arm64_za-ptrace_Set_VL_1728: pass
arm64_za-ptrace_Set_VL_1744: pass
arm64_za-ptrace_Set_VL_176: pass
arm64_za-ptrace_Set_VL_1760: pass
arm64_za-ptrace_Set_VL_1776: pass
arm64_za-ptrace_Set_VL_1792: pass
arm64_za-ptrace_Set_VL_1808: pass
arm64_za-ptrace_Set_VL_1824: pass
arm64_za-ptrace_Set_VL_1840: pass
arm64_za-ptrace_Set_VL_1856: pass
arm64_za-ptrace_Set_VL_1872: pass
arm64_za-ptrace_Set_VL_1888: pass
arm64_za-ptrace_Set_VL_1904: pass
arm64_za-ptrace_Set_VL_192: pass
arm64_za-ptrace_Set_VL_1920: pass
arm64_za-ptrace_Set_VL_1936: pass
arm64_za-ptrace_Set_VL_1952: pass
arm64_za-ptrace_Set_VL_1968: pass
arm64_za-ptrace_Set_VL_1984: pass
arm64_za-ptrace_Set_VL_2000: pass
arm64_za-ptrace_Set_VL_2016: pass
arm64_za-ptrace_Set_VL_2032: pass
arm64_za-ptrace_Set_VL_2048: pass
arm64_za-ptrace_Set_VL_2064: pass
arm64_za-ptrace_Set_VL_208: pass
arm64_za-ptrace_Set_VL_2080: pass
arm64_za-ptrace_Set_VL_2096: pass
arm64_za-ptrace_Set_VL_2112: pass
arm64_za-ptrace_Set_VL_2128: pass
arm64_za-ptrace_Set_VL_2144: pass
arm64_za-ptrace_Set_VL_2160: pass
arm64_za-ptrace_Set_VL_2176: pass
arm64_za-ptrace_Set_VL_2192: pass
arm64_za-ptrace_Set_VL_2208: pass
arm64_za-ptrace_Set_VL_2224: pass
arm64_za-ptrace_Set_VL_224: pass
arm64_za-ptrace_Set_VL_2240: pass
arm64_za-ptrace_Set_VL_2256: pass
arm64_za-ptrace_Set_VL_2272: pass
arm64_za-ptrace_Set_VL_2288: pass
arm64_za-ptrace_Set_VL_2304: pass
arm64_za-ptrace_Set_VL_2320: pass
arm64_za-ptrace_Set_VL_2336: pass
arm64_za-ptrace_Set_VL_2352: pass
arm64_za-ptrace_Set_VL_2368: pass
arm64_za-ptrace_Set_VL_2384: pass
arm64_za-ptrace_Set_VL_240: pass
arm64_za-ptrace_Set_VL_2400: pass
arm64_za-ptrace_Set_VL_2416: pass
arm64_za-ptrace_Set_VL_2432: pass
arm64_za-ptrace_Set_VL_2448: pass
arm64_za-ptrace_Set_VL_2464: pass
arm64_za-ptrace_Set_VL_2480: pass
arm64_za-ptrace_Set_VL_2496: pass
arm64_za-ptrace_Set_VL_2512: pass
arm64_za-ptrace_Set_VL_2528: pass
arm64_za-ptrace_Set_VL_2544: pass
arm64_za-ptrace_Set_VL_256: pass
arm64_za-ptrace_Set_VL_2560: pass
arm64_za-ptrace_Set_VL_2576: pass
arm64_za-ptrace_Set_VL_2592: pass
arm64_za-ptrace_Set_VL_2608: pass
arm64_za-ptrace_Set_VL_2624: pass
arm64_za-ptrace_Set_VL_2640: pass
arm64_za-ptrace_Set_VL_2656: pass
arm64_za-ptrace_Set_VL_2672: pass
arm64_za-ptrace_Set_VL_2688: pass
arm64_za-ptrace_Set_VL_2704: pass
arm64_za-ptrace_Set_VL_272: pass
arm64_za-ptrace_Set_VL_2720: pass
arm64_za-ptrace_Set_VL_2736: pass
arm64_za-ptrace_Set_VL_2752: pass
arm64_za-ptrace_Set_VL_2768: pass
arm64_za-ptrace_Set_VL_2784: pass
arm64_za-ptrace_Set_VL_2800: pass
arm64_za-ptrace_Set_VL_2816: pass
arm64_za-ptrace_Set_VL_2832: pass
arm64_za-ptrace_Set_VL_2848: pass
arm64_za-ptrace_Set_VL_2864: pass
arm64_za-ptrace_Set_VL_288: pass
arm64_za-ptrace_Set_VL_2880: pass
arm64_za-ptrace_Set_VL_2896: pass
arm64_za-ptrace_Set_VL_2912: pass
arm64_za-ptrace_Set_VL_2928: pass
arm64_za-ptrace_Set_VL_2944: pass
arm64_za-ptrace_Set_VL_2960: pass
arm64_za-ptrace_Set_VL_2976: pass
arm64_za-ptrace_Set_VL_2992: pass
arm64_za-ptrace_Set_VL_3008: pass
arm64_za-ptrace_Set_VL_3024: pass
arm64_za-ptrace_Set_VL_304: pass
arm64_za-ptrace_Set_VL_3040: pass
arm64_za-ptrace_Set_VL_3056: pass
arm64_za-ptrace_Set_VL_3072: pass
arm64_za-ptrace_Set_VL_3088: pass
arm64_za-ptrace_Set_VL_3104: pass
arm64_za-ptrace_Set_VL_3120: pass
arm64_za-ptrace_Set_VL_3136: pass
arm64_za-ptrace_Set_VL_3152: pass
arm64_za-ptrace_Set_VL_3168: pass
arm64_za-ptrace_Set_VL_3184: pass
arm64_za-ptrace_Set_VL_32: pass
arm64_za-ptrace_Set_VL_320: pass
arm64_za-ptrace_Set_VL_3200: pass
arm64_za-ptrace_Set_VL_3216: pass
arm64_za-ptrace_Set_VL_3232: pass
arm64_za-ptrace_Set_VL_3248: pass
arm64_za-ptrace_Set_VL_3264: pass
arm64_za-ptrace_Set_VL_3280: pass
arm64_za-ptrace_Set_VL_3296: pass
arm64_za-ptrace_Set_VL_3312: pass
arm64_za-ptrace_Set_VL_3328: pass
arm64_za-ptrace_Set_VL_3344: pass
arm64_za-ptrace_Set_VL_336: pass
arm64_za-ptrace_Set_VL_3360: pass
arm64_za-ptrace_Set_VL_3376: pass
arm64_za-ptrace_Set_VL_3392: pass
arm64_za-ptrace_Set_VL_3408: pass
arm64_za-ptrace_Set_VL_3424: pass
arm64_za-ptrace_Set_VL_3440: pass
arm64_za-ptrace_Set_VL_3456: pass
arm64_za-ptrace_Set_VL_3472: pass
arm64_za-ptrace_Set_VL_3488: pass
arm64_za-ptrace_Set_VL_3504: pass
arm64_za-ptrace_Set_VL_352: pass
arm64_za-ptrace_Set_VL_3520: pass
arm64_za-ptrace_Set_VL_3536: pass
arm64_za-ptrace_Set_VL_3552: pass
arm64_za-ptrace_Set_VL_3568: pass
arm64_za-ptrace_Set_VL_3584: pass
arm64_za-ptrace_Set_VL_3600: pass
arm64_za-ptrace_Set_VL_3616: pass
arm64_za-ptrace_Set_VL_3632: pass
arm64_za-ptrace_Set_VL_3648: pass
arm64_za-ptrace_Set_VL_3664: pass
arm64_za-ptrace_Set_VL_368: pass
arm64_za-ptrace_Set_VL_3680: pass
arm64_za-ptrace_Set_VL_3696: pass
arm64_za-ptrace_Set_VL_3712: pass
arm64_za-ptrace_Set_VL_3728: pass
arm64_za-ptrace_Set_VL_3744: pass
arm64_za-ptrace_Set_VL_3760: pass
arm64_za-ptrace_Set_VL_3776: pass
arm64_za-ptrace_Set_VL_3792: pass
arm64_za-ptrace_Set_VL_3808: pass
arm64_za-ptrace_Set_VL_3824: pass
arm64_za-ptrace_Set_VL_384: pass
arm64_za-ptrace_Set_VL_3840: pass
arm64_za-ptrace_Set_VL_3856: pass
arm64_za-ptrace_Set_VL_3872: pass
arm64_za-ptrace_Set_VL_3888: pass
arm64_za-ptrace_Set_VL_3904: pass
arm64_za-ptrace_Set_VL_3920: pass
arm64_za-ptrace_Set_VL_3936: pass
arm64_za-ptrace_Set_VL_3952: pass
arm64_za-ptrace_Set_VL_3968: pass
arm64_za-ptrace_Set_VL_3984: pass
arm64_za-ptrace_Set_VL_400: pass
arm64_za-ptrace_Set_VL_4000: pass
arm64_za-ptrace_Set_VL_4016: pass
arm64_za-ptrace_Set_VL_4032: pass
arm64_za-ptrace_Set_VL_4048: pass
arm64_za-ptrace_Set_VL_4064: pass
arm64_za-ptrace_Set_VL_4080: pass
arm64_za-ptrace_Set_VL_4096: pass
arm64_za-ptrace_Set_VL_4112: pass
arm64_za-ptrace_Set_VL_4128: pass
arm64_za-ptrace_Set_VL_4144: pass
arm64_za-ptrace_Set_VL_416: pass
arm64_za-ptrace_Set_VL_4160: pass
arm64_za-ptrace_Set_VL_4176: pass
arm64_za-ptrace_Set_VL_4192: pass
arm64_za-ptrace_Set_VL_4208: pass
arm64_za-ptrace_Set_VL_4224: pass
arm64_za-ptrace_Set_VL_4240: pass
arm64_za-ptrace_Set_VL_4256: pass
arm64_za-ptrace_Set_VL_4272: pass
arm64_za-ptrace_Set_VL_4288: pass
arm64_za-ptrace_Set_VL_4304: pass
arm64_za-ptrace_Set_VL_432: pass
arm64_za-ptrace_Set_VL_4320: pass
arm64_za-ptrace_Set_VL_4336: pass
arm64_za-ptrace_Set_VL_4352: pass
arm64_za-ptrace_Set_VL_4368: pass
arm64_za-ptrace_Set_VL_4384: pass
arm64_za-ptrace_Set_VL_4400: pass
arm64_za-ptrace_Set_VL_4416: pass
arm64_za-ptrace_Set_VL_4432: pass
arm64_za-ptrace_Set_VL_4448: pass
arm64_za-ptrace_Set_VL_4464: pass
arm64_za-ptrace_Set_VL_448: pass
arm64_za-ptrace_Set_VL_4480: pass
arm64_za-ptrace_Set_VL_4496: pass
arm64_za-ptrace_Set_VL_4512: pass
arm64_za-ptrace_Set_VL_4528: pass
arm64_za-ptrace_Set_VL_4544: pass
arm64_za-ptrace_Set_VL_4560: pass
arm64_za-ptrace_Set_VL_4576: pass
arm64_za-ptrace_Set_VL_4592: pass
arm64_za-ptrace_Set_VL_4608: pass
arm64_za-ptrace_Set_VL_4624: pass
arm64_za-ptrace_Set_VL_464: pass
arm64_za-ptrace_Set_VL_4640: pass
arm64_za-ptrace_Set_VL_4656: pass
arm64_za-ptrace_Set_VL_4672: pass
arm64_za-ptrace_Set_VL_4688: pass
arm64_za-ptrace_Set_VL_4704: pass
arm64_za-ptrace_Set_VL_4720: pass
arm64_za-ptrace_Set_VL_4736: pass
arm64_za-ptrace_Set_VL_4752: pass
arm64_za-ptrace_Set_VL_4768: pass
arm64_za-ptrace_Set_VL_4784: pass
arm64_za-ptrace_Set_VL_48: pass
arm64_za-ptrace_Set_VL_480: pass
arm64_za-ptrace_Set_VL_4800: pass
arm64_za-ptrace_Set_VL_4816: pass
arm64_za-ptrace_Set_VL_4832: pass
arm64_za-ptrace_Set_VL_4848: pass
arm64_za-ptrace_Set_VL_4864: pass
arm64_za-ptrace_Set_VL_4880: pass
arm64_za-ptrace_Set_VL_4896: pass
arm64_za-ptrace_Set_VL_4912: pass
arm64_za-ptrace_Set_VL_4928: pass
arm64_za-ptrace_Set_VL_4944: pass
arm64_za-ptrace_Set_VL_496: pass
arm64_za-ptrace_Set_VL_4960: pass
arm64_za-ptrace_Set_VL_4976: pass
arm64_za-ptrace_Set_VL_4992: pass
arm64_za-ptrace_Set_VL_5008: pass
arm64_za-ptrace_Set_VL_5024: pass
arm64_za-ptrace_Set_VL_5040: pass
arm64_za-ptrace_Set_VL_5056: pass
arm64_za-ptrace_Set_VL_5072: pass
arm64_za-ptrace_Set_VL_5088: pass
arm64_za-ptrace_Set_VL_5104: pass
arm64_za-ptrace_Set_VL_512: pass
arm64_za-ptrace_Set_VL_5120: pass
arm64_za-ptrace_Set_VL_5136: pass
arm64_za-ptrace_Set_VL_5152: pass
arm64_za-ptrace_Set_VL_5168: pass
arm64_za-ptrace_Set_VL_5184: pass
arm64_za-ptrace_Set_VL_5200: pass
arm64_za-ptrace_Set_VL_5216: pass
arm64_za-ptrace_Set_VL_5232: pass
arm64_za-ptrace_Set_VL_5248: pass
arm64_za-ptrace_Set_VL_5264: pass
arm64_za-ptrace_Set_VL_528: pass
arm64_za-ptrace_Set_VL_5280: pass
arm64_za-ptrace_Set_VL_5296: pass
arm64_za-ptrace_Set_VL_5312: pass
arm64_za-ptrace_Set_VL_5328: pass
arm64_za-ptrace_Set_VL_5344: pass
arm64_za-ptrace_Set_VL_5360: pass
arm64_za-ptrace_Set_VL_5376: pass
arm64_za-ptrace_Set_VL_5392: pass
arm64_za-ptrace_Set_VL_5408: pass
arm64_za-ptrace_Set_VL_5424: pass
arm64_za-ptrace_Set_VL_544: pass
arm64_za-ptrace_Set_VL_5440: pass
arm64_za-ptrace_Set_VL_5456: pass
arm64_za-ptrace_Set_VL_5472: pass
arm64_za-ptrace_Set_VL_5488: pass
arm64_za-ptrace_Set_VL_5504: pass
arm64_za-ptrace_Set_VL_5520: pass
arm64_za-ptrace_Set_VL_5536: pass
arm64_za-ptrace_Set_VL_5552: pass
arm64_za-ptrace_Set_VL_5568: pass
arm64_za-ptrace_Set_VL_5584: pass
arm64_za-ptrace_Set_VL_560: pass
arm64_za-ptrace_Set_VL_5600: pass
arm64_za-ptrace_Set_VL_5616: pass
arm64_za-ptrace_Set_VL_5632: pass
arm64_za-ptrace_Set_VL_5648: pass
arm64_za-ptrace_Set_VL_5664: pass
arm64_za-ptrace_Set_VL_5680: pass
arm64_za-ptrace_Set_VL_5696: pass
arm64_za-ptrace_Set_VL_5712: pass
arm64_za-ptrace_Set_VL_5728: pass
arm64_za-ptrace_Set_VL_5744: pass
arm64_za-ptrace_Set_VL_576: pass
arm64_za-ptrace_Set_VL_5760: pass
arm64_za-ptrace_Set_VL_5776: pass
arm64_za-ptrace_Set_VL_5792: pass
arm64_za-ptrace_Set_VL_5808: pass
arm64_za-ptrace_Set_VL_5824: pass
arm64_za-ptrace_Set_VL_5840: pass
arm64_za-ptrace_Set_VL_5856: pass
arm64_za-ptrace_Set_VL_5872: pass
arm64_za-ptrace_Set_VL_5888: pass
arm64_za-ptrace_Set_VL_5904: pass
arm64_za-ptrace_Set_VL_592: pass
arm64_za-ptrace_Set_VL_5920: pass
arm64_za-ptrace_Set_VL_5936: pass
arm64_za-ptrace_Set_VL_5952: pass
arm64_za-ptrace_Set_VL_5968: pass
arm64_za-ptrace_Set_VL_5984: pass
arm64_za-ptrace_Set_VL_6000: pass
arm64_za-ptrace_Set_VL_6016: pass
arm64_za-ptrace_Set_VL_6032: pass
arm64_za-ptrace_Set_VL_6048: pass
arm64_za-ptrace_Set_VL_6064: pass
arm64_za-ptrace_Set_VL_608: pass
arm64_za-ptrace_Set_VL_6080: pass
arm64_za-ptrace_Set_VL_6096: pass
arm64_za-ptrace_Set_VL_6112: pass
arm64_za-ptrace_Set_VL_6128: pass
arm64_za-ptrace_Set_VL_6144: pass
arm64_za-ptrace_Set_VL_6160: pass
arm64_za-ptrace_Set_VL_6176: pass
arm64_za-ptrace_Set_VL_6192: pass
arm64_za-ptrace_Set_VL_6208: pass
arm64_za-ptrace_Set_VL_6224: pass
arm64_za-ptrace_Set_VL_624: pass
arm64_za-ptrace_Set_VL_6240: pass
arm64_za-ptrace_Set_VL_6256: pass
arm64_za-ptrace_Set_VL_6272: pass
arm64_za-ptrace_Set_VL_6288: pass
arm64_za-ptrace_Set_VL_6304: pass
arm64_za-ptrace_Set_VL_6320: pass
arm64_za-ptrace_Set_VL_6336: pass
arm64_za-ptrace_Set_VL_6352: pass
arm64_za-ptrace_Set_VL_6368: pass
arm64_za-ptrace_Set_VL_6384: pass
arm64_za-ptrace_Set_VL_64: pass
arm64_za-ptrace_Set_VL_640: pass
arm64_za-ptrace_Set_VL_6400: pass
arm64_za-ptrace_Set_VL_6416: pass
arm64_za-ptrace_Set_VL_6432: pass
arm64_za-ptrace_Set_VL_6448: pass
arm64_za-ptrace_Set_VL_6464: pass
arm64_za-ptrace_Set_VL_6480: pass
arm64_za-ptrace_Set_VL_6496: pass
arm64_za-ptrace_Set_VL_6512: pass
arm64_za-ptrace_Set_VL_6528: pass
arm64_za-ptrace_Set_VL_6544: pass
arm64_za-ptrace_Set_VL_656: pass
arm64_za-ptrace_Set_VL_6560: pass
arm64_za-ptrace_Set_VL_6576: pass
arm64_za-ptrace_Set_VL_6592: pass
arm64_za-ptrace_Set_VL_6608: pass
arm64_za-ptrace_Set_VL_6624: pass
arm64_za-ptrace_Set_VL_6640: pass
arm64_za-ptrace_Set_VL_6656: pass
arm64_za-ptrace_Set_VL_6672: pass
arm64_za-ptrace_Set_VL_6688: pass
arm64_za-ptrace_Set_VL_6704: pass
arm64_za-ptrace_Set_VL_672: pass
arm64_za-ptrace_Set_VL_6720: pass
arm64_za-ptrace_Set_VL_6736: pass
arm64_za-ptrace_Set_VL_6752: pass
arm64_za-ptrace_Set_VL_6768: pass
arm64_za-ptrace_Set_VL_6784: pass
arm64_za-ptrace_Set_VL_6800: pass
arm64_za-ptrace_Set_VL_6816: pass
arm64_za-ptrace_Set_VL_6832: pass
arm64_za-ptrace_Set_VL_6848: pass
arm64_za-ptrace_Set_VL_6864: pass
arm64_za-ptrace_Set_VL_688: pass
arm64_za-ptrace_Set_VL_6880: pass
arm64_za-ptrace_Set_VL_6896: pass
arm64_za-ptrace_Set_VL_6912: pass
arm64_za-ptrace_Set_VL_6928: pass
arm64_za-ptrace_Set_VL_6944: pass
arm64_za-ptrace_Set_VL_6960: pass
arm64_za-ptrace_Set_VL_6976: pass
arm64_za-ptrace_Set_VL_6992: pass
arm64_za-ptrace_Set_VL_7008: pass
arm64_za-ptrace_Set_VL_7024: pass
arm64_za-ptrace_Set_VL_704: pass
arm64_za-ptrace_Set_VL_7040: pass
arm64_za-ptrace_Set_VL_7056: pass
arm64_za-ptrace_Set_VL_7072: pass
arm64_za-ptrace_Set_VL_7088: pass
arm64_za-ptrace_Set_VL_7104: pass
arm64_za-ptrace_Set_VL_7120: pass
arm64_za-ptrace_Set_VL_7136: pass
arm64_za-ptrace_Set_VL_7152: pass
arm64_za-ptrace_Set_VL_7168: pass
arm64_za-ptrace_Set_VL_7184: pass
arm64_za-ptrace_Set_VL_720: pass
arm64_za-ptrace_Set_VL_7200: pass
arm64_za-ptrace_Set_VL_7216: pass
arm64_za-ptrace_Set_VL_7232: pass
arm64_za-ptrace_Set_VL_7248: pass
arm64_za-ptrace_Set_VL_7264: pass
arm64_za-ptrace_Set_VL_7280: pass
arm64_za-ptrace_Set_VL_7296: pass
arm64_za-ptrace_Set_VL_7312: pass
arm64_za-ptrace_Set_VL_7328: pass
arm64_za-ptrace_Set_VL_7344: pass
arm64_za-ptrace_Set_VL_736: pass
arm64_za-ptrace_Set_VL_7360: pass
arm64_za-ptrace_Set_VL_7376: pass
arm64_za-ptrace_Set_VL_7392: pass
arm64_za-ptrace_Set_VL_7408: pass
arm64_za-ptrace_Set_VL_7424: pass
arm64_za-ptrace_Set_VL_7440: pass
arm64_za-ptrace_Set_VL_7456: pass
arm64_za-ptrace_Set_VL_7472: pass
arm64_za-ptrace_Set_VL_7488: pass
arm64_za-ptrace_Set_VL_7504: pass
arm64_za-ptrace_Set_VL_752: pass
arm64_za-ptrace_Set_VL_7520: pass
arm64_za-ptrace_Set_VL_7536: pass
arm64_za-ptrace_Set_VL_7552: pass
arm64_za-ptrace_Set_VL_7568: pass
arm64_za-ptrace_Set_VL_7584: pass
arm64_za-ptrace_Set_VL_7600: pass
arm64_za-ptrace_Set_VL_7616: pass
arm64_za-ptrace_Set_VL_7632: pass
arm64_za-ptrace_Set_VL_7648: pass
arm64_za-ptrace_Set_VL_7664: pass
arm64_za-ptrace_Set_VL_768: pass
arm64_za-ptrace_Set_VL_7680: pass
arm64_za-ptrace_Set_VL_7696: pass
arm64_za-ptrace_Set_VL_7712: pass
arm64_za-ptrace_Set_VL_7728: pass
arm64_za-ptrace_Set_VL_7744: pass
arm64_za-ptrace_Set_VL_7760: pass
arm64_za-ptrace_Set_VL_7776: pass
arm64_za-ptrace_Set_VL_7792: pass
arm64_za-ptrace_Set_VL_7808: pass
arm64_za-ptrace_Set_VL_7824: pass
arm64_za-ptrace_Set_VL_784: pass
arm64_za-ptrace_Set_VL_7840: pass
arm64_za-ptrace_Set_VL_7856: pass
arm64_za-ptrace_Set_VL_7872: pass
arm64_za-ptrace_Set_VL_7888: pass
arm64_za-ptrace_Set_VL_7904: pass
arm64_za-ptrace_Set_VL_7920: pass
arm64_za-ptrace_Set_VL_7936: pass
arm64_za-ptrace_Set_VL_7952: pass
arm64_za-ptrace_Set_VL_7968: pass
arm64_za-ptrace_Set_VL_7984: pass
arm64_za-ptrace_Set_VL_80: pass
arm64_za-ptrace_Set_VL_800: pass
arm64_za-ptrace_Set_VL_8000: pass
arm64_za-ptrace_Set_VL_8016: pass
arm64_za-ptrace_Set_VL_8032: pass
arm64_za-ptrace_Set_VL_8048: pass
arm64_za-ptrace_Set_VL_8064: pass
arm64_za-ptrace_Set_VL_8080: pass
arm64_za-ptrace_Set_VL_8096: pass
arm64_za-ptrace_Set_VL_8112: pass
arm64_za-ptrace_Set_VL_8128: pass
arm64_za-ptrace_Set_VL_8144: pass
arm64_za-ptrace_Set_VL_816: pass
arm64_za-ptrace_Set_VL_8160: pass
arm64_za-ptrace_Set_VL_8176: pass
arm64_za-ptrace_Set_VL_8192: pass
arm64_za-ptrace_Set_VL_832: pass
arm64_za-ptrace_Set_VL_848: pass
arm64_za-ptrace_Set_VL_864: pass
arm64_za-ptrace_Set_VL_880: pass
arm64_za-ptrace_Set_VL_896: pass
arm64_za-ptrace_Set_VL_912: pass
arm64_za-ptrace_Set_VL_928: pass
arm64_za-ptrace_Set_VL_944: pass
arm64_za-ptrace_Set_VL_96: pass
arm64_za-ptrace_Set_VL_960: pass
arm64_za-ptrace_Set_VL_976: pass
arm64_za-ptrace_Set_VL_992: pass
arm64_za_no_regs: pass
arm64_za_regs: pass
34582 12:34:37.577605 end: 3.1 lava-test-shell (duration 00:06:48) [common]
34583 12:34:37.577762 end: 3 lava-test-retry (duration 00:06:48) [common]
34584 12:34:37.577872 start: 4 finalize (timeout 00:02:03) [common]
34585 12:34:37.577981 start: 4.1 power-off (timeout 00:00:30) [common]
34586 12:34:37.578080 end: 4.1 power-off (duration 00:00:00) [common]
34587 12:34:37.578178 start: 4.2 read-feedback (timeout 00:02:03) [common]
34589 12:34:37.578668 Listened to connection for namespace 'common' for up to 1s
34590 12:34:38.581772 Finalising connection for namespace 'common'
34592 12:34:38.682894 / # poweroff
34593 12:34:38.683521 Already disconnected
34594 12:34:38.683713 poweroff
34595 12:34:39.085832 end: 4.2 read-feedback (duration 00:00:02) [common]
34596 12:34:39.086124 Already disconnected
34597 12:34:39.086359 end: 4 finalize (duration 00:00:02) [common]
34598 12:34:39.086570 Cleaning after the job
34599 12:34:39.086787 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/568933/deployimages-qs5w04wn/kernel
34600 12:34:39.094389 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/568933/deployimages-qs5w04wn/ramdisk
34601 12:34:39.111803 Stopping the qemu container lava-docker-qemu-568933-2.1.1-58qd14nm3e
34602 12:34:39.778675 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/568933
34603 12:34:39.869191 Job finished correctly