Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 26
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
- Errors: 2
1 10:01:03.010441 lava-dispatcher, installed at version: 2023.05.1
2 10:01:03.010653 start: 0 validate
3 10:01:03.010785 Start time: 2023-06-10 10:01:03.010778+00:00 (UTC)
4 10:01:03.010916 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:01:03.011046 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 10:01:03.278684 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:01:03.278884 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:01:19.848068 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:01:19.848853 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:01:20.109890 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:01:20.110642 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:01:23.873101 validate duration: 20.86
14 10:01:23.873363 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:01:23.873461 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:01:23.873551 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:01:23.873669 Not decompressing ramdisk as can be used compressed.
18 10:01:23.873751 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230527.0/arm64/rootfs.cpio.gz
19 10:01:23.873814 saving as /var/lib/lava/dispatcher/tmp/10670658/tftp-deploy-87q2arux/ramdisk/rootfs.cpio.gz
20 10:01:23.873873 total size: 8186575 (7MB)
21 10:01:24.139322 progress 0% (0MB)
22 10:01:24.141744 progress 5% (0MB)
23 10:01:24.143842 progress 10% (0MB)
24 10:01:24.146102 progress 15% (1MB)
25 10:01:24.148172 progress 20% (1MB)
26 10:01:24.150345 progress 25% (1MB)
27 10:01:24.152498 progress 30% (2MB)
28 10:01:24.154740 progress 35% (2MB)
29 10:01:24.157041 progress 40% (3MB)
30 10:01:24.159235 progress 45% (3MB)
31 10:01:24.161386 progress 50% (3MB)
32 10:01:24.163672 progress 55% (4MB)
33 10:01:24.165899 progress 60% (4MB)
34 10:01:24.168134 progress 65% (5MB)
35 10:01:24.170103 progress 70% (5MB)
36 10:01:24.172983 progress 75% (5MB)
37 10:01:24.175156 progress 80% (6MB)
38 10:01:24.177448 progress 85% (6MB)
39 10:01:24.179638 progress 90% (7MB)
40 10:01:24.181914 progress 95% (7MB)
41 10:01:24.184068 progress 100% (7MB)
42 10:01:24.184444 7MB downloaded in 0.31s (25.14MB/s)
43 10:01:24.184695 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:01:24.185063 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:01:24.185178 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:01:24.185290 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:01:24.185451 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:01:24.185547 saving as /var/lib/lava/dispatcher/tmp/10670658/tftp-deploy-87q2arux/kernel/Image
50 10:01:24.185635 total size: 45746688 (43MB)
51 10:01:24.185740 No compression specified
52 10:01:24.187313 progress 0% (0MB)
53 10:01:24.199305 progress 5% (2MB)
54 10:01:24.210683 progress 10% (4MB)
55 10:01:24.222201 progress 15% (6MB)
56 10:01:24.233469 progress 20% (8MB)
57 10:01:24.245010 progress 25% (10MB)
58 10:01:24.256342 progress 30% (13MB)
59 10:01:24.268104 progress 35% (15MB)
60 10:01:24.279683 progress 40% (17MB)
61 10:01:24.291166 progress 45% (19MB)
62 10:01:24.302697 progress 50% (21MB)
63 10:01:24.314050 progress 55% (24MB)
64 10:01:24.325462 progress 60% (26MB)
65 10:01:24.336936 progress 65% (28MB)
66 10:01:24.348366 progress 70% (30MB)
67 10:01:24.359883 progress 75% (32MB)
68 10:01:24.371503 progress 80% (34MB)
69 10:01:24.383046 progress 85% (37MB)
70 10:01:24.394510 progress 90% (39MB)
71 10:01:24.405848 progress 95% (41MB)
72 10:01:24.417118 progress 100% (43MB)
73 10:01:24.417258 43MB downloaded in 0.23s (188.36MB/s)
74 10:01:24.417406 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:01:24.417638 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:01:24.417728 start: 1.3 download-retry (timeout 00:09:59) [common]
78 10:01:24.417820 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 10:01:24.417956 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:01:24.418026 saving as /var/lib/lava/dispatcher/tmp/10670658/tftp-deploy-87q2arux/dtb/mt8192-asurada-spherion-r0.dtb
81 10:01:24.418088 total size: 46924 (0MB)
82 10:01:24.418148 No compression specified
83 10:01:24.419256 progress 69% (0MB)
84 10:01:24.419568 progress 100% (0MB)
85 10:01:24.419720 0MB downloaded in 0.00s (27.46MB/s)
86 10:01:24.419840 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:01:24.420062 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:01:24.420146 start: 1.4 download-retry (timeout 00:09:59) [common]
90 10:01:24.420229 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 10:01:24.420338 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:01:24.420406 saving as /var/lib/lava/dispatcher/tmp/10670658/tftp-deploy-87q2arux/modules/modules.tar
93 10:01:24.420467 total size: 8540248 (8MB)
94 10:01:24.420527 Using unxz to decompress xz
95 10:01:24.424067 progress 0% (0MB)
96 10:01:24.445827 progress 5% (0MB)
97 10:01:24.476927 progress 10% (0MB)
98 10:01:24.509727 progress 15% (1MB)
99 10:01:24.535400 progress 20% (1MB)
100 10:01:24.559947 progress 25% (2MB)
101 10:01:24.584251 progress 30% (2MB)
102 10:01:24.610623 progress 35% (2MB)
103 10:01:24.635685 progress 40% (3MB)
104 10:01:24.659313 progress 45% (3MB)
105 10:01:24.687589 progress 50% (4MB)
106 10:01:24.713415 progress 55% (4MB)
107 10:01:24.739576 progress 60% (4MB)
108 10:01:24.765663 progress 65% (5MB)
109 10:01:24.791417 progress 70% (5MB)
110 10:01:24.816735 progress 75% (6MB)
111 10:01:24.840938 progress 80% (6MB)
112 10:01:24.867048 progress 85% (6MB)
113 10:01:24.896573 progress 90% (7MB)
114 10:01:24.922184 progress 95% (7MB)
115 10:01:24.947602 progress 100% (8MB)
116 10:01:24.952832 8MB downloaded in 0.53s (15.30MB/s)
117 10:01:24.953129 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:01:24.953424 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:01:24.953533 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:01:24.953649 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:01:24.953748 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:01:24.953854 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:01:24.954089 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o
125 10:01:24.954262 makedir: /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin
126 10:01:24.954406 makedir: /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/tests
127 10:01:24.954546 makedir: /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/results
128 10:01:24.954676 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-add-keys
129 10:01:24.954839 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-add-sources
130 10:01:24.954986 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-background-process-start
131 10:01:24.955134 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-background-process-stop
132 10:01:24.955279 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-common-functions
133 10:01:24.955499 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-echo-ipv4
134 10:01:24.955670 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-install-packages
135 10:01:24.955839 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-installed-packages
136 10:01:24.956006 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-os-build
137 10:01:24.956148 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-probe-channel
138 10:01:24.956291 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-probe-ip
139 10:01:24.956434 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-target-ip
140 10:01:24.956574 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-target-mac
141 10:01:24.956715 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-target-storage
142 10:01:24.956864 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-test-case
143 10:01:24.957034 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-test-event
144 10:01:24.957203 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-test-feedback
145 10:01:24.957373 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-test-raise
146 10:01:24.957542 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-test-reference
147 10:01:24.957685 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-test-runner
148 10:01:24.957825 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-test-set
149 10:01:24.957969 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-test-shell
150 10:01:24.958116 Updating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-install-packages (oe)
151 10:01:24.958315 Updating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/bin/lava-installed-packages (oe)
152 10:01:24.958481 Creating /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/environment
153 10:01:24.958631 LAVA metadata
154 10:01:24.958744 - LAVA_JOB_ID=10670658
155 10:01:24.958849 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:01:24.958998 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:01:24.959100 skipped lava-vland-overlay
158 10:01:24.959222 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:01:24.959351 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:01:24.959492 skipped lava-multinode-overlay
161 10:01:24.959618 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:01:24.959744 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:01:24.959860 Loading test definitions
164 10:01:24.959999 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 10:01:24.960116 Using /lava-10670658 at stage 0
166 10:01:24.960554 uuid=10670658_1.5.2.3.1 testdef=None
167 10:01:24.960681 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:01:24.960811 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 10:01:24.961580 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:01:24.961953 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 10:01:24.962898 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:01:24.963290 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 10:01:24.963995 runner path: /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/0/tests/0_dmesg test_uuid 10670658_1.5.2.3.1
176 10:01:24.964170 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:01:24.964607 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 10:01:24.964723 Using /lava-10670658 at stage 1
180 10:01:24.965156 uuid=10670658_1.5.2.3.5 testdef=None
181 10:01:24.965282 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 10:01:24.965415 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 10:01:24.966177 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 10:01:24.966533 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 10:01:24.967873 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 10:01:24.968109 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 10:01:24.968730 runner path: /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/1/tests/1_bootrr test_uuid 10670658_1.5.2.3.5
190 10:01:24.968884 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 10:01:24.969096 Creating lava-test-runner.conf files
193 10:01:24.969163 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/0 for stage 0
194 10:01:24.969255 - 0_dmesg
195 10:01:24.969343 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10670658/lava-overlay-k08tpx4o/lava-10670658/1 for stage 1
196 10:01:24.969434 - 1_bootrr
197 10:01:24.969529 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 10:01:24.969614 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 10:01:24.977540 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 10:01:24.977666 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 10:01:24.977759 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 10:01:24.977851 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 10:01:24.977944 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 10:01:25.221302 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 10:01:25.221660 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 10:01:25.221784 extracting modules file /var/lib/lava/dispatcher/tmp/10670658/tftp-deploy-87q2arux/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670658/extract-overlay-ramdisk-yisa380d/ramdisk
207 10:01:25.430744 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 10:01:25.430910 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 10:01:25.431006 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670658/compress-overlay-j12_8hhm/overlay-1.5.2.4.tar.gz to ramdisk
210 10:01:25.431083 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670658/compress-overlay-j12_8hhm/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10670658/extract-overlay-ramdisk-yisa380d/ramdisk
211 10:01:25.439200 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 10:01:25.439339 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 10:01:25.439518 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 10:01:25.439615 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 10:01:25.439701 Building ramdisk /var/lib/lava/dispatcher/tmp/10670658/extract-overlay-ramdisk-yisa380d/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10670658/extract-overlay-ramdisk-yisa380d/ramdisk
216 10:01:25.805869 >> 143719 blocks
217 10:01:28.083339 rename /var/lib/lava/dispatcher/tmp/10670658/extract-overlay-ramdisk-yisa380d/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10670658/tftp-deploy-87q2arux/ramdisk/ramdisk.cpio.gz
218 10:01:28.083812 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 10:01:28.083935 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 10:01:28.084041 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 10:01:28.084156 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10670658/tftp-deploy-87q2arux/kernel/Image'
222 10:01:40.661585 Returned 0 in 12 seconds
223 10:01:40.762187 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10670658/tftp-deploy-87q2arux/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10670658/tftp-deploy-87q2arux/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10670658/tftp-deploy-87q2arux/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10670658/tftp-deploy-87q2arux/kernel/image.itb
224 10:01:41.148815 output: FIT description: Kernel Image image with one or more FDT blobs
225 10:01:41.149183 output: Created: Sat Jun 10 11:01:41 2023
226 10:01:41.149265 output: Image 0 (kernel-1)
227 10:01:41.149334 output: Description:
228 10:01:41.149400 output: Created: Sat Jun 10 11:01:41 2023
229 10:01:41.149467 output: Type: Kernel Image
230 10:01:41.149531 output: Compression: lzma compressed
231 10:01:41.149592 output: Data Size: 10087317 Bytes = 9850.90 KiB = 9.62 MiB
232 10:01:41.149653 output: Architecture: AArch64
233 10:01:41.149715 output: OS: Linux
234 10:01:41.149775 output: Load Address: 0x00000000
235 10:01:41.149833 output: Entry Point: 0x00000000
236 10:01:41.149892 output: Hash algo: crc32
237 10:01:41.149947 output: Hash value: c9e456fd
238 10:01:41.150002 output: Image 1 (fdt-1)
239 10:01:41.150056 output: Description: mt8192-asurada-spherion-r0
240 10:01:41.150111 output: Created: Sat Jun 10 11:01:41 2023
241 10:01:41.150165 output: Type: Flat Device Tree
242 10:01:41.150220 output: Compression: uncompressed
243 10:01:41.150274 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
244 10:01:41.150328 output: Architecture: AArch64
245 10:01:41.150382 output: Hash algo: crc32
246 10:01:41.150437 output: Hash value: 1df858fa
247 10:01:41.150490 output: Image 2 (ramdisk-1)
248 10:01:41.150544 output: Description: unavailable
249 10:01:41.150598 output: Created: Sat Jun 10 11:01:41 2023
250 10:01:41.150652 output: Type: RAMDisk Image
251 10:01:41.150705 output: Compression: Unknown Compression
252 10:01:41.150760 output: Data Size: 21217593 Bytes = 20720.31 KiB = 20.23 MiB
253 10:01:41.150816 output: Architecture: AArch64
254 10:01:41.150870 output: OS: Linux
255 10:01:41.150923 output: Load Address: unavailable
256 10:01:41.150977 output: Entry Point: unavailable
257 10:01:41.151032 output: Hash algo: crc32
258 10:01:41.151086 output: Hash value: 548f91c0
259 10:01:41.151140 output: Default Configuration: 'conf-1'
260 10:01:41.151194 output: Configuration 0 (conf-1)
261 10:01:41.151248 output: Description: mt8192-asurada-spherion-r0
262 10:01:41.151303 output: Kernel: kernel-1
263 10:01:41.151368 output: Init Ramdisk: ramdisk-1
264 10:01:41.151425 output: FDT: fdt-1
265 10:01:41.151479 output: Loadables: kernel-1
266 10:01:41.151534 output:
267 10:01:41.151726 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
268 10:01:41.151829 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
269 10:01:41.151937 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
270 10:01:41.152038 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
271 10:01:41.152123 No LXC device requested
272 10:01:41.152203 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 10:01:41.152297 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
274 10:01:41.152379 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 10:01:41.152453 Checking files for TFTP limit of 4294967296 bytes.
276 10:01:41.152959 end: 1 tftp-deploy (duration 00:00:17) [common]
277 10:01:41.153070 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 10:01:41.153163 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 10:01:41.153288 substitutions:
280 10:01:41.153357 - {DTB}: 10670658/tftp-deploy-87q2arux/dtb/mt8192-asurada-spherion-r0.dtb
281 10:01:41.153424 - {INITRD}: 10670658/tftp-deploy-87q2arux/ramdisk/ramdisk.cpio.gz
282 10:01:41.153485 - {KERNEL}: 10670658/tftp-deploy-87q2arux/kernel/Image
283 10:01:41.153545 - {LAVA_MAC}: None
284 10:01:41.153603 - {PRESEED_CONFIG}: None
285 10:01:41.153660 - {PRESEED_LOCAL}: None
286 10:01:41.153716 - {RAMDISK}: 10670658/tftp-deploy-87q2arux/ramdisk/ramdisk.cpio.gz
287 10:01:41.153774 - {ROOT_PART}: None
288 10:01:41.153829 - {ROOT}: None
289 10:01:41.153885 - {SERVER_IP}: 192.168.201.1
290 10:01:41.153941 - {TEE}: None
291 10:01:41.153996 Parsed boot commands:
292 10:01:41.154052 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 10:01:41.154245 Parsed boot commands: tftpboot 192.168.201.1 10670658/tftp-deploy-87q2arux/kernel/image.itb 10670658/tftp-deploy-87q2arux/kernel/cmdline
294 10:01:41.154342 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 10:01:41.154433 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 10:01:41.154528 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 10:01:41.154618 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 10:01:41.154689 Not connected, no need to disconnect.
299 10:01:41.154766 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 10:01:41.154854 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 10:01:41.154925 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
302 10:01:41.159441 Setting prompt string to ['lava-test: # ']
303 10:01:41.160032 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 10:01:41.160141 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 10:01:41.160240 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 10:01:41.160331 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 10:01:41.160547 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
308 10:01:46.299324 >> Command sent successfully.
309 10:01:46.305200 Returned 0 in 5 seconds
310 10:01:46.405604 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 10:01:46.405978 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 10:01:46.406092 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 10:01:46.406192 Setting prompt string to 'Starting depthcharge on Spherion...'
315 10:01:46.406286 Changing prompt to 'Starting depthcharge on Spherion...'
316 10:01:46.406358 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 10:01:46.406625 [Enter `^Ec?' for help]
318 10:01:46.575213
319 10:01:46.575404
320 10:01:46.575479 F0: 102B 0000
321 10:01:46.575543
322 10:01:46.575603 F3: 1001 0000 [0200]
323 10:01:46.578951
324 10:01:46.579035 F3: 1001 0000
325 10:01:46.579104
326 10:01:46.579166 F7: 102D 0000
327 10:01:46.579227
328 10:01:46.582033 F1: 0000 0000
329 10:01:46.582118
330 10:01:46.582186 V0: 0000 0000 [0001]
331 10:01:46.582249
332 10:01:46.585651 00: 0007 8000
333 10:01:46.585741
334 10:01:46.585808 01: 0000 0000
335 10:01:46.585870
336 10:01:46.588820 BP: 0C00 0209 [0000]
337 10:01:46.588904
338 10:01:46.588971 G0: 1182 0000
339 10:01:46.589033
340 10:01:46.592368 EC: 0000 0021 [4000]
341 10:01:46.592452
342 10:01:46.592518 S7: 0000 0000 [0000]
343 10:01:46.592599
344 10:01:46.595991 CC: 0000 0000 [0001]
345 10:01:46.596075
346 10:01:46.596149 T0: 0000 0040 [010F]
347 10:01:46.596216
348 10:01:46.596297 Jump to BL
349 10:01:46.596359
350 10:01:46.621969
351 10:01:46.622108
352 10:01:46.622176
353 10:01:46.628920 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 10:01:46.633160 ARM64: Exception handlers installed.
355 10:01:46.637082 ARM64: Testing exception
356 10:01:46.639950 ARM64: Done test exception
357 10:01:46.646951 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 10:01:46.656947 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 10:01:46.664266 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 10:01:46.673769 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 10:01:46.680528 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 10:01:46.687531 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 10:01:46.699556 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 10:01:46.705988 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 10:01:46.725300 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 10:01:46.728659 WDT: Last reset was cold boot
367 10:01:46.731795 SPI1(PAD0) initialized at 2873684 Hz
368 10:01:46.735559 SPI5(PAD0) initialized at 992727 Hz
369 10:01:46.738525 VBOOT: Loading verstage.
370 10:01:46.745710 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 10:01:46.748414 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 10:01:46.752165 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 10:01:46.755673 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 10:01:46.762604 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 10:01:46.769418 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 10:01:46.780531 read SPI 0x96554 0xa1eb: 4596 us, 9018 KB/s, 72.144 Mbps
377 10:01:46.780618
378 10:01:46.780685
379 10:01:46.790355 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 10:01:46.793861 ARM64: Exception handlers installed.
381 10:01:46.796768 ARM64: Testing exception
382 10:01:46.800018 ARM64: Done test exception
383 10:01:46.803296 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 10:01:46.806682 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 10:01:46.823066 Probing TPM: . done!
386 10:01:46.823170 TPM ready after 0 ms
387 10:01:46.829243 Connected to device vid:did:rid of 1ae0:0028:00
388 10:01:46.836340 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
389 10:01:46.895259 Initialized TPM device CR50 revision 0
390 10:01:46.907001 tlcl_send_startup: Startup return code is 0
391 10:01:46.907107 TPM: setup succeeded
392 10:01:46.918175 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 10:01:46.927471 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 10:01:46.939326 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 10:01:46.948949 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 10:01:46.952328 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 10:01:46.956488 in-header: 03 07 00 00 08 00 00 00
398 10:01:46.959965 in-data: aa e4 47 04 13 02 00 00
399 10:01:46.963665 Chrome EC: UHEPI supported
400 10:01:46.970464 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 10:01:46.974261 in-header: 03 ad 00 00 08 00 00 00
402 10:01:46.977716 in-data: 00 20 20 08 00 00 00 00
403 10:01:46.977802 Phase 1
404 10:01:46.981483 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 10:01:46.989492 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 10:01:46.992153 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 10:01:46.995889 Recovery requested (1009000e)
408 10:01:47.005364 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 10:01:47.011786 tlcl_extend: response is 0
410 10:01:47.021964 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 10:01:47.027955 tlcl_extend: response is 0
412 10:01:47.034351 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 10:01:47.054400 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
414 10:01:47.061490 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 10:01:47.061580
416 10:01:47.061648
417 10:01:47.071975 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 10:01:47.075635 ARM64: Exception handlers installed.
419 10:01:47.075721 ARM64: Testing exception
420 10:01:47.078851 ARM64: Done test exception
421 10:01:47.100433 pmic_efuse_setting: Set efuses in 11 msecs
422 10:01:47.103983 pmwrap_interface_init: Select PMIF_VLD_RDY
423 10:01:47.111043 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 10:01:47.113928 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 10:01:47.117161 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 10:01:47.123991 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 10:01:47.128356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 10:01:47.134738 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 10:01:47.138401 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 10:01:47.142418 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 10:01:47.146015 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 10:01:47.152934 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 10:01:47.157242 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 10:01:47.160843 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 10:01:47.167868 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 10:01:47.171293 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 10:01:47.178690 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 10:01:47.182326 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 10:01:47.190204 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 10:01:47.197638 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 10:01:47.200823 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 10:01:47.208372 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 10:01:47.211752 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 10:01:47.219960 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 10:01:47.222994 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 10:01:47.230751 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 10:01:47.234221 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 10:01:47.241668 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 10:01:47.245351 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 10:01:47.249526 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 10:01:47.257003 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 10:01:47.260281 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 10:01:47.263747 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 10:01:47.270788 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 10:01:47.274670 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 10:01:47.278730 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 10:01:47.285940 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 10:01:47.289592 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 10:01:47.293059 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 10:01:47.300065 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 10:01:47.303711 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 10:01:47.307677 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 10:01:47.310880 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 10:01:47.318967 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 10:01:47.322128 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 10:01:47.326189 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 10:01:47.329929 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 10:01:47.333180 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 10:01:47.340320 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 10:01:47.343833 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 10:01:47.348058 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 10:01:47.351210 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 10:01:47.354968 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 10:01:47.362847 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 10:01:47.372890 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 10:01:47.376506 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 10:01:47.384192 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 10:01:47.394465 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 10:01:47.398253 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 10:01:47.402253 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 10:01:47.405413 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 10:01:47.414212 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xe
483 10:01:47.417500 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 10:01:47.425393 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
485 10:01:47.428536 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 10:01:47.437571 [RTC]rtc_get_frequency_meter,154: input=15, output=790
487 10:01:47.447624 [RTC]rtc_get_frequency_meter,154: input=23, output=978
488 10:01:47.456957 [RTC]rtc_get_frequency_meter,154: input=19, output=883
489 10:01:47.466690 [RTC]rtc_get_frequency_meter,154: input=17, output=836
490 10:01:47.476703 [RTC]rtc_get_frequency_meter,154: input=16, output=813
491 10:01:47.485406 [RTC]rtc_get_frequency_meter,154: input=15, output=790
492 10:01:47.495481 [RTC]rtc_get_frequency_meter,154: input=16, output=813
493 10:01:47.498990 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
494 10:01:47.506392 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
495 10:01:47.509692 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 10:01:47.513418 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 10:01:47.516900 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 10:01:47.521065 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 10:01:47.525014 ADC[4]: Raw value=902066 ID=7
500 10:01:47.528440 ADC[3]: Raw value=213336 ID=1
501 10:01:47.529008 RAM Code: 0x71
502 10:01:47.532655 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 10:01:47.536086 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 10:01:47.547305 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 10:01:47.551228 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 10:01:47.554941 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 10:01:47.558973 in-header: 03 07 00 00 08 00 00 00
508 10:01:47.562692 in-data: aa e4 47 04 13 02 00 00
509 10:01:47.565947 Chrome EC: UHEPI supported
510 10:01:47.572536 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 10:01:47.576680 in-header: 03 ed 00 00 08 00 00 00
512 10:01:47.580400 in-data: 80 20 60 08 00 00 00 00
513 10:01:47.580859 MRC: failed to locate region type 0.
514 10:01:47.587689 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 10:01:47.591628 DRAM-K: Running full calibration
516 10:01:47.598718 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 10:01:47.599157 header.status = 0x0
518 10:01:47.602755 header.version = 0x6 (expected: 0x6)
519 10:01:47.605970 header.size = 0xd00 (expected: 0xd00)
520 10:01:47.606414 header.flags = 0x0
521 10:01:47.613825 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 10:01:47.632453 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
523 10:01:47.639005 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 10:01:47.642418 dram_init: ddr_geometry: 2
525 10:01:47.642849 [EMI] MDL number = 2
526 10:01:47.645768 [EMI] Get MDL freq = 0
527 10:01:47.649632 dram_init: ddr_type: 0
528 10:01:47.650291 is_discrete_lpddr4: 1
529 10:01:47.653347 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 10:01:47.653948
531 10:01:47.654308
532 10:01:47.657016 [Bian_co] ETT version 0.0.0.1
533 10:01:47.660212 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 10:01:47.660766
535 10:01:47.663442 dramc_set_vcore_voltage set vcore to 650000
536 10:01:47.666704 Read voltage for 800, 4
537 10:01:47.667141 Vio18 = 0
538 10:01:47.670605 Vcore = 650000
539 10:01:47.671144 Vdram = 0
540 10:01:47.671551 Vddq = 0
541 10:01:47.671881 Vmddr = 0
542 10:01:47.673863 dram_init: config_dvfs: 1
543 10:01:47.680198 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 10:01:47.683707 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 10:01:47.687009 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
546 10:01:47.693693 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
547 10:01:47.696558 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
548 10:01:47.700255 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
549 10:01:47.700870 MEM_TYPE=3, freq_sel=18
550 10:01:47.703272 sv_algorithm_assistance_LP4_1600
551 10:01:47.710439 ============ PULL DRAM RESETB DOWN ============
552 10:01:47.713657 ========== PULL DRAM RESETB DOWN end =========
553 10:01:47.717380 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 10:01:47.720633 ===================================
555 10:01:47.723537 LPDDR4 DRAM CONFIGURATION
556 10:01:47.726934 ===================================
557 10:01:47.730420 EX_ROW_EN[0] = 0x0
558 10:01:47.730925 EX_ROW_EN[1] = 0x0
559 10:01:47.733742 LP4Y_EN = 0x0
560 10:01:47.734286 WORK_FSP = 0x0
561 10:01:47.737162 WL = 0x2
562 10:01:47.737600 RL = 0x2
563 10:01:47.740528 BL = 0x2
564 10:01:47.740969 RPST = 0x0
565 10:01:47.744003 RD_PRE = 0x0
566 10:01:47.744553 WR_PRE = 0x1
567 10:01:47.747236 WR_PST = 0x0
568 10:01:47.747810 DBI_WR = 0x0
569 10:01:47.750760 DBI_RD = 0x0
570 10:01:47.751270 OTF = 0x1
571 10:01:47.753679 ===================================
572 10:01:47.756924 ===================================
573 10:01:47.760172 ANA top config
574 10:01:47.763615 ===================================
575 10:01:47.764124 DLL_ASYNC_EN = 0
576 10:01:47.767482 ALL_SLAVE_EN = 1
577 10:01:47.770607 NEW_RANK_MODE = 1
578 10:01:47.774087 DLL_IDLE_MODE = 1
579 10:01:47.777143 LP45_APHY_COMB_EN = 1
580 10:01:47.777686 TX_ODT_DIS = 1
581 10:01:47.780487 NEW_8X_MODE = 1
582 10:01:47.783673 ===================================
583 10:01:47.787402 ===================================
584 10:01:47.790801 data_rate = 1600
585 10:01:47.793768 CKR = 1
586 10:01:47.796792 DQ_P2S_RATIO = 8
587 10:01:47.800481 ===================================
588 10:01:47.801114 CA_P2S_RATIO = 8
589 10:01:47.803771 DQ_CA_OPEN = 0
590 10:01:47.806849 DQ_SEMI_OPEN = 0
591 10:01:47.810560 CA_SEMI_OPEN = 0
592 10:01:47.813764 CA_FULL_RATE = 0
593 10:01:47.817114 DQ_CKDIV4_EN = 1
594 10:01:47.817689 CA_CKDIV4_EN = 1
595 10:01:47.820255 CA_PREDIV_EN = 0
596 10:01:47.823954 PH8_DLY = 0
597 10:01:47.826766 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 10:01:47.830702 DQ_AAMCK_DIV = 4
599 10:01:47.831250 CA_AAMCK_DIV = 4
600 10:01:47.834344 CA_ADMCK_DIV = 4
601 10:01:47.837271 DQ_TRACK_CA_EN = 0
602 10:01:47.840710 CA_PICK = 800
603 10:01:47.844123 CA_MCKIO = 800
604 10:01:47.847437 MCKIO_SEMI = 0
605 10:01:47.851258 PLL_FREQ = 3068
606 10:01:47.851801 DQ_UI_PI_RATIO = 32
607 10:01:47.854764 CA_UI_PI_RATIO = 0
608 10:01:47.858012 ===================================
609 10:01:47.861314 ===================================
610 10:01:47.865375 memory_type:LPDDR4
611 10:01:47.865815 GP_NUM : 10
612 10:01:47.868368 SRAM_EN : 1
613 10:01:47.868806 MD32_EN : 0
614 10:01:47.872270 ===================================
615 10:01:47.876340 [ANA_INIT] >>>>>>>>>>>>>>
616 10:01:47.879703 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 10:01:47.883166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 10:01:47.887055 ===================================
619 10:01:47.887631 data_rate = 1600,PCW = 0X7600
620 10:01:47.889806 ===================================
621 10:01:47.893497 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 10:01:47.900097 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 10:01:47.906516 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 10:01:47.910399 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 10:01:47.913492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 10:01:47.916562 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 10:01:47.919669 [ANA_INIT] flow start
628 10:01:47.920109 [ANA_INIT] PLL >>>>>>>>
629 10:01:47.923178 [ANA_INIT] PLL <<<<<<<<
630 10:01:47.926793 [ANA_INIT] MIDPI >>>>>>>>
631 10:01:47.930063 [ANA_INIT] MIDPI <<<<<<<<
632 10:01:47.930596 [ANA_INIT] DLL >>>>>>>>
633 10:01:47.933256 [ANA_INIT] flow end
634 10:01:47.936408 ============ LP4 DIFF to SE enter ============
635 10:01:47.939686 ============ LP4 DIFF to SE exit ============
636 10:01:47.943215 [ANA_INIT] <<<<<<<<<<<<<
637 10:01:47.946919 [Flow] Enable top DCM control >>>>>
638 10:01:47.950377 [Flow] Enable top DCM control <<<<<
639 10:01:47.953553 Enable DLL master slave shuffle
640 10:01:47.960278 ==============================================================
641 10:01:47.960814 Gating Mode config
642 10:01:47.967218 ==============================================================
643 10:01:47.967801 Config description:
644 10:01:47.977243 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 10:01:47.984124 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 10:01:47.989991 SELPH_MODE 0: By rank 1: By Phase
647 10:01:47.993424 ==============================================================
648 10:01:47.996684 GAT_TRACK_EN = 1
649 10:01:47.999995 RX_GATING_MODE = 2
650 10:01:48.003192 RX_GATING_TRACK_MODE = 2
651 10:01:48.006561 SELPH_MODE = 1
652 10:01:48.010219 PICG_EARLY_EN = 1
653 10:01:48.013172 VALID_LAT_VALUE = 1
654 10:01:48.016625 ==============================================================
655 10:01:48.020231 Enter into Gating configuration >>>>
656 10:01:48.023736 Exit from Gating configuration <<<<
657 10:01:48.026963 Enter into DVFS_PRE_config >>>>>
658 10:01:48.040332 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 10:01:48.040899 Exit from DVFS_PRE_config <<<<<
660 10:01:48.043670 Enter into PICG configuration >>>>
661 10:01:48.046465 Exit from PICG configuration <<<<
662 10:01:48.050172 [RX_INPUT] configuration >>>>>
663 10:01:48.053181 [RX_INPUT] configuration <<<<<
664 10:01:48.059949 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 10:01:48.063095 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 10:01:48.070403 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 10:01:48.077429 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 10:01:48.084084 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 10:01:48.090531 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 10:01:48.094215 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 10:01:48.097581 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 10:01:48.100144 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 10:01:48.103766 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 10:01:48.110428 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 10:01:48.113868 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 10:01:48.117187 ===================================
677 10:01:48.120827 LPDDR4 DRAM CONFIGURATION
678 10:01:48.123833 ===================================
679 10:01:48.124291 EX_ROW_EN[0] = 0x0
680 10:01:48.126862 EX_ROW_EN[1] = 0x0
681 10:01:48.127313 LP4Y_EN = 0x0
682 10:01:48.130440 WORK_FSP = 0x0
683 10:01:48.131003 WL = 0x2
684 10:01:48.134210 RL = 0x2
685 10:01:48.134761 BL = 0x2
686 10:01:48.137312 RPST = 0x0
687 10:01:48.140059 RD_PRE = 0x0
688 10:01:48.140513 WR_PRE = 0x1
689 10:01:48.143711 WR_PST = 0x0
690 10:01:48.144270 DBI_WR = 0x0
691 10:01:48.146842 DBI_RD = 0x0
692 10:01:48.147296 OTF = 0x1
693 10:01:48.150348 ===================================
694 10:01:48.153680 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 10:01:48.157215 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 10:01:48.164007 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 10:01:48.166976 ===================================
698 10:01:48.170455 LPDDR4 DRAM CONFIGURATION
699 10:01:48.173870 ===================================
700 10:01:48.174322 EX_ROW_EN[0] = 0x10
701 10:01:48.177006 EX_ROW_EN[1] = 0x0
702 10:01:48.177455 LP4Y_EN = 0x0
703 10:01:48.180342 WORK_FSP = 0x0
704 10:01:48.180793 WL = 0x2
705 10:01:48.183860 RL = 0x2
706 10:01:48.184406 BL = 0x2
707 10:01:48.186973 RPST = 0x0
708 10:01:48.187566 RD_PRE = 0x0
709 10:01:48.190051 WR_PRE = 0x1
710 10:01:48.190500 WR_PST = 0x0
711 10:01:48.193776 DBI_WR = 0x0
712 10:01:48.194386 DBI_RD = 0x0
713 10:01:48.197485 OTF = 0x1
714 10:01:48.200359 ===================================
715 10:01:48.206943 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 10:01:48.210584 nWR fixed to 40
717 10:01:48.213680 [ModeRegInit_LP4] CH0 RK0
718 10:01:48.214179 [ModeRegInit_LP4] CH0 RK1
719 10:01:48.216981 [ModeRegInit_LP4] CH1 RK0
720 10:01:48.219919 [ModeRegInit_LP4] CH1 RK1
721 10:01:48.220394 match AC timing 13
722 10:01:48.227376 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 10:01:48.230714 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 10:01:48.233839 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 10:01:48.240616 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 10:01:48.243486 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 10:01:48.243966 [EMI DOE] emi_dcm 0
728 10:01:48.250522 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 10:01:48.251068 ==
730 10:01:48.253566 Dram Type= 6, Freq= 0, CH_0, rank 0
731 10:01:48.257173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 10:01:48.257658 ==
733 10:01:48.263595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 10:01:48.270776 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 10:01:48.277750 [CA 0] Center 37 (7~68) winsize 62
736 10:01:48.281031 [CA 1] Center 37 (6~68) winsize 63
737 10:01:48.284597 [CA 2] Center 35 (5~66) winsize 62
738 10:01:48.287611 [CA 3] Center 34 (4~65) winsize 62
739 10:01:48.291155 [CA 4] Center 34 (4~64) winsize 61
740 10:01:48.294450 [CA 5] Center 33 (3~64) winsize 62
741 10:01:48.294904
742 10:01:48.297493 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 10:01:48.298031
744 10:01:48.300688 [CATrainingPosCal] consider 1 rank data
745 10:01:48.304153 u2DelayCellTimex100 = 270/100 ps
746 10:01:48.307438 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
747 10:01:48.314498 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
748 10:01:48.317965 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
749 10:01:48.321070 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
750 10:01:48.323917 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
751 10:01:48.327756 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 10:01:48.328209
753 10:01:48.330916 CA PerBit enable=1, Macro0, CA PI delay=33
754 10:01:48.331385
755 10:01:48.334692 [CBTSetCACLKResult] CA Dly = 33
756 10:01:48.335196 CS Dly: 5 (0~36)
757 10:01:48.337765 ==
758 10:01:48.338205 Dram Type= 6, Freq= 0, CH_0, rank 1
759 10:01:48.343832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 10:01:48.344301 ==
761 10:01:48.347458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 10:01:48.354325 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 10:01:48.363916 [CA 0] Center 37 (6~68) winsize 63
764 10:01:48.367131 [CA 1] Center 37 (7~68) winsize 62
765 10:01:48.370580 [CA 2] Center 35 (5~66) winsize 62
766 10:01:48.373809 [CA 3] Center 34 (4~65) winsize 62
767 10:01:48.377199 [CA 4] Center 33 (3~64) winsize 62
768 10:01:48.380943 [CA 5] Center 33 (3~64) winsize 62
769 10:01:48.381508
770 10:01:48.383645 [CmdBusTrainingLP45] Vref(ca) range 1: 32
771 10:01:48.384085
772 10:01:48.387076 [CATrainingPosCal] consider 2 rank data
773 10:01:48.390977 u2DelayCellTimex100 = 270/100 ps
774 10:01:48.394047 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
775 10:01:48.397505 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
776 10:01:48.403934 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
777 10:01:48.407108 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
778 10:01:48.410457 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
779 10:01:48.414073 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 10:01:48.414625
781 10:01:48.417164 CA PerBit enable=1, Macro0, CA PI delay=33
782 10:01:48.417609
783 10:01:48.420742 [CBTSetCACLKResult] CA Dly = 33
784 10:01:48.421189 CS Dly: 5 (0~37)
785 10:01:48.421540
786 10:01:48.423590 ----->DramcWriteLeveling(PI) begin...
787 10:01:48.427442 ==
788 10:01:48.427990 Dram Type= 6, Freq= 0, CH_0, rank 0
789 10:01:48.434963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 10:01:48.435546 ==
791 10:01:48.438714 Write leveling (Byte 0): 29 => 29
792 10:01:48.439157 Write leveling (Byte 1): 29 => 29
793 10:01:48.442958 DramcWriteLeveling(PI) end<-----
794 10:01:48.443436
795 10:01:48.443794 ==
796 10:01:48.445871 Dram Type= 6, Freq= 0, CH_0, rank 0
797 10:01:48.449243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 10:01:48.449692 ==
799 10:01:48.453130 [Gating] SW mode calibration
800 10:01:48.459999 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 10:01:48.467097 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 10:01:48.470153 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 10:01:48.473176 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
804 10:01:48.480281 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
805 10:01:48.483900 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 10:01:48.486859 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 10:01:48.490406 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 10:01:48.496722 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 10:01:48.500317 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 10:01:48.503255 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 10:01:48.509823 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 10:01:48.513111 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 10:01:48.516510 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 10:01:48.523893 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 10:01:48.527225 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 10:01:48.530432 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 10:01:48.536726 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 10:01:48.539813 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 10:01:48.543208 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
820 10:01:48.550264 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
821 10:01:48.553396 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
822 10:01:48.557306 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 10:01:48.563689 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 10:01:48.566296 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 10:01:48.570157 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 10:01:48.576810 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 10:01:48.580139 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 10:01:48.583179 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
829 10:01:48.590366 0 9 12 | B1->B0 | 2727 3131 | 0 0 | (0 0) (0 0)
830 10:01:48.593552 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 10:01:48.596864 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 10:01:48.600347 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 10:01:48.607012 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 10:01:48.610402 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 10:01:48.613809 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
836 10:01:48.619903 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
837 10:01:48.623246 0 10 12 | B1->B0 | 2b2b 2424 | 0 0 | (1 0) (1 1)
838 10:01:48.626843 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 10:01:48.633284 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 10:01:48.636604 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 10:01:48.639911 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 10:01:48.646878 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 10:01:48.650000 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 10:01:48.653702 0 11 8 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
845 10:01:48.660426 0 11 12 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
846 10:01:48.663691 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 10:01:48.667116 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 10:01:48.673421 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 10:01:48.676373 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 10:01:48.679981 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 10:01:48.687138 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 10:01:48.690135 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
853 10:01:48.693014 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
854 10:01:48.696695 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 10:01:48.703268 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 10:01:48.706435 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 10:01:48.710187 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 10:01:48.716270 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 10:01:48.719841 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 10:01:48.723114 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 10:01:48.730143 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 10:01:48.733153 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 10:01:48.736510 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 10:01:48.743032 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 10:01:48.746536 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 10:01:48.750112 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 10:01:48.756704 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
868 10:01:48.760204 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
869 10:01:48.763488 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 10:01:48.766637 Total UI for P1: 0, mck2ui 16
871 10:01:48.769976 best dqsien dly found for B0: ( 0, 14, 8)
872 10:01:48.773142 Total UI for P1: 0, mck2ui 16
873 10:01:48.776350 best dqsien dly found for B1: ( 0, 14, 8)
874 10:01:48.779904 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
875 10:01:48.783052 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
876 10:01:48.783661
877 10:01:48.786239 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
878 10:01:48.793434 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
879 10:01:48.793994 [Gating] SW calibration Done
880 10:01:48.794462 ==
881 10:01:48.796477 Dram Type= 6, Freq= 0, CH_0, rank 0
882 10:01:48.802828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 10:01:48.803308 ==
884 10:01:48.803908 RX Vref Scan: 0
885 10:01:48.804342
886 10:01:48.806332 RX Vref 0 -> 0, step: 1
887 10:01:48.806788
888 10:01:48.809964 RX Delay -130 -> 252, step: 16
889 10:01:48.813207 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
890 10:01:48.816324 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
891 10:01:48.819633 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
892 10:01:48.826578 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
893 10:01:48.830265 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
894 10:01:48.833292 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
895 10:01:48.836598 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
896 10:01:48.839723 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
897 10:01:48.846621 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
898 10:01:48.849463 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
899 10:01:48.852967 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
900 10:01:48.856068 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
901 10:01:48.859614 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
902 10:01:48.866526 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
903 10:01:48.869574 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
904 10:01:48.873086 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
905 10:01:48.873543 ==
906 10:01:48.876223 Dram Type= 6, Freq= 0, CH_0, rank 0
907 10:01:48.880093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 10:01:48.880551 ==
909 10:01:48.883091 DQS Delay:
910 10:01:48.883568 DQS0 = 0, DQS1 = 0
911 10:01:48.886152 DQM Delay:
912 10:01:48.886605 DQM0 = 85, DQM1 = 78
913 10:01:48.887054 DQ Delay:
914 10:01:48.889467 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
915 10:01:48.893287 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
916 10:01:48.896667 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
917 10:01:48.899793 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
918 10:01:48.900246
919 10:01:48.900695
920 10:01:48.901117 ==
921 10:01:48.902777 Dram Type= 6, Freq= 0, CH_0, rank 0
922 10:01:48.910107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 10:01:48.910659 ==
924 10:01:48.911116
925 10:01:48.911644
926 10:01:48.912066 TX Vref Scan disable
927 10:01:48.913271 == TX Byte 0 ==
928 10:01:48.916525 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
929 10:01:48.920226 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
930 10:01:48.923190 == TX Byte 1 ==
931 10:01:48.926950 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
932 10:01:48.930146 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
933 10:01:48.933946 ==
934 10:01:48.936517 Dram Type= 6, Freq= 0, CH_0, rank 0
935 10:01:48.940363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 10:01:48.940920 ==
937 10:01:48.953046 TX Vref=22, minBit 3, minWin=27, winSum=440
938 10:01:48.956044 TX Vref=24, minBit 0, minWin=27, winSum=441
939 10:01:48.959203 TX Vref=26, minBit 0, minWin=27, winSum=444
940 10:01:48.963006 TX Vref=28, minBit 13, minWin=27, winSum=451
941 10:01:48.966115 TX Vref=30, minBit 1, minWin=28, winSum=452
942 10:01:48.969636 TX Vref=32, minBit 2, minWin=28, winSum=451
943 10:01:48.975853 [TxChooseVref] Worse bit 1, Min win 28, Win sum 452, Final Vref 30
944 10:01:48.976299
945 10:01:48.979526 Final TX Range 1 Vref 30
946 10:01:48.980126
947 10:01:48.980519 ==
948 10:01:48.982970 Dram Type= 6, Freq= 0, CH_0, rank 0
949 10:01:48.986170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 10:01:48.986737 ==
951 10:01:48.987210
952 10:01:48.989248
953 10:01:48.989778 TX Vref Scan disable
954 10:01:48.992445 == TX Byte 0 ==
955 10:01:48.995818 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
956 10:01:48.999183 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
957 10:01:49.002666 == TX Byte 1 ==
958 10:01:49.005968 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
959 10:01:49.009035 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
960 10:01:49.012739
961 10:01:49.013272 [DATLAT]
962 10:01:49.013623 Freq=800, CH0 RK0
963 10:01:49.013947
964 10:01:49.015868 DATLAT Default: 0xa
965 10:01:49.016303 0, 0xFFFF, sum = 0
966 10:01:49.019155 1, 0xFFFF, sum = 0
967 10:01:49.019693 2, 0xFFFF, sum = 0
968 10:01:49.022563 3, 0xFFFF, sum = 0
969 10:01:49.023005 4, 0xFFFF, sum = 0
970 10:01:49.026338 5, 0xFFFF, sum = 0
971 10:01:49.026885 6, 0xFFFF, sum = 0
972 10:01:49.029607 7, 0xFFFF, sum = 0
973 10:01:49.030048 8, 0xFFFF, sum = 0
974 10:01:49.032720 9, 0x0, sum = 1
975 10:01:49.033263 10, 0x0, sum = 2
976 10:01:49.035746 11, 0x0, sum = 3
977 10:01:49.036191 12, 0x0, sum = 4
978 10:01:49.039112 best_step = 10
979 10:01:49.039566
980 10:01:49.039914 ==
981 10:01:49.042858 Dram Type= 6, Freq= 0, CH_0, rank 0
982 10:01:49.046307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 10:01:49.046846 ==
984 10:01:49.049683 RX Vref Scan: 1
985 10:01:49.050221
986 10:01:49.050578 Set Vref Range= 32 -> 127
987 10:01:49.050902
988 10:01:49.053095 RX Vref 32 -> 127, step: 1
989 10:01:49.053643
990 10:01:49.055830 RX Delay -95 -> 252, step: 8
991 10:01:49.056269
992 10:01:49.059543 Set Vref, RX VrefLevel [Byte0]: 32
993 10:01:49.063185 [Byte1]: 32
994 10:01:49.063769
995 10:01:49.066347 Set Vref, RX VrefLevel [Byte0]: 33
996 10:01:49.069497 [Byte1]: 33
997 10:01:49.072717
998 10:01:49.073220 Set Vref, RX VrefLevel [Byte0]: 34
999 10:01:49.076004 [Byte1]: 34
1000 10:01:49.080240
1001 10:01:49.080785 Set Vref, RX VrefLevel [Byte0]: 35
1002 10:01:49.083612 [Byte1]: 35
1003 10:01:49.088208
1004 10:01:49.088649 Set Vref, RX VrefLevel [Byte0]: 36
1005 10:01:49.091008 [Byte1]: 36
1006 10:01:49.096063
1007 10:01:49.096609 Set Vref, RX VrefLevel [Byte0]: 37
1008 10:01:49.099164 [Byte1]: 37
1009 10:01:49.103161
1010 10:01:49.103742 Set Vref, RX VrefLevel [Byte0]: 38
1011 10:01:49.106377 [Byte1]: 38
1012 10:01:49.110688
1013 10:01:49.114367 Set Vref, RX VrefLevel [Byte0]: 39
1014 10:01:49.117649 [Byte1]: 39
1015 10:01:49.118092
1016 10:01:49.120745 Set Vref, RX VrefLevel [Byte0]: 40
1017 10:01:49.124565 [Byte1]: 40
1018 10:01:49.125073
1019 10:01:49.128141 Set Vref, RX VrefLevel [Byte0]: 41
1020 10:01:49.131475 [Byte1]: 41
1021 10:01:49.131920
1022 10:01:49.134837 Set Vref, RX VrefLevel [Byte0]: 42
1023 10:01:49.137868 [Byte1]: 42
1024 10:01:49.138328
1025 10:01:49.141304 Set Vref, RX VrefLevel [Byte0]: 43
1026 10:01:49.144737 [Byte1]: 43
1027 10:01:49.148837
1028 10:01:49.149301 Set Vref, RX VrefLevel [Byte0]: 44
1029 10:01:49.152508 [Byte1]: 44
1030 10:01:49.156842
1031 10:01:49.157443 Set Vref, RX VrefLevel [Byte0]: 45
1032 10:01:49.160601 [Byte1]: 45
1033 10:01:49.164323
1034 10:01:49.165029 Set Vref, RX VrefLevel [Byte0]: 46
1035 10:01:49.167204 [Byte1]: 46
1036 10:01:49.171487
1037 10:01:49.171989 Set Vref, RX VrefLevel [Byte0]: 47
1038 10:01:49.174837 [Byte1]: 47
1039 10:01:49.179452
1040 10:01:49.180042 Set Vref, RX VrefLevel [Byte0]: 48
1041 10:01:49.182182 [Byte1]: 48
1042 10:01:49.187078
1043 10:01:49.187730 Set Vref, RX VrefLevel [Byte0]: 49
1044 10:01:49.190252 [Byte1]: 49
1045 10:01:49.194181
1046 10:01:49.194862 Set Vref, RX VrefLevel [Byte0]: 50
1047 10:01:49.197624 [Byte1]: 50
1048 10:01:49.201600
1049 10:01:49.202131 Set Vref, RX VrefLevel [Byte0]: 51
1050 10:01:49.205485 [Byte1]: 51
1051 10:01:49.209516
1052 10:01:49.209954 Set Vref, RX VrefLevel [Byte0]: 52
1053 10:01:49.213118 [Byte1]: 52
1054 10:01:49.216876
1055 10:01:49.217314 Set Vref, RX VrefLevel [Byte0]: 53
1056 10:01:49.220192 [Byte1]: 53
1057 10:01:49.224671
1058 10:01:49.225177 Set Vref, RX VrefLevel [Byte0]: 54
1059 10:01:49.227864 [Byte1]: 54
1060 10:01:49.232826
1061 10:01:49.233376 Set Vref, RX VrefLevel [Byte0]: 55
1062 10:01:49.235775 [Byte1]: 55
1063 10:01:49.239893
1064 10:01:49.240364 Set Vref, RX VrefLevel [Byte0]: 56
1065 10:01:49.243632 [Byte1]: 56
1066 10:01:49.247223
1067 10:01:49.247783 Set Vref, RX VrefLevel [Byte0]: 57
1068 10:01:49.250594 [Byte1]: 57
1069 10:01:49.255465
1070 10:01:49.255997 Set Vref, RX VrefLevel [Byte0]: 58
1071 10:01:49.258424 [Byte1]: 58
1072 10:01:49.262958
1073 10:01:49.263529 Set Vref, RX VrefLevel [Byte0]: 59
1074 10:01:49.266330 [Byte1]: 59
1075 10:01:49.270443
1076 10:01:49.270985 Set Vref, RX VrefLevel [Byte0]: 60
1077 10:01:49.273571 [Byte1]: 60
1078 10:01:49.277770
1079 10:01:49.278206 Set Vref, RX VrefLevel [Byte0]: 61
1080 10:01:49.281364 [Byte1]: 61
1081 10:01:49.285269
1082 10:01:49.285771 Set Vref, RX VrefLevel [Byte0]: 62
1083 10:01:49.288990 [Byte1]: 62
1084 10:01:49.293232
1085 10:01:49.293772 Set Vref, RX VrefLevel [Byte0]: 63
1086 10:01:49.296086 [Byte1]: 63
1087 10:01:49.300583
1088 10:01:49.301122 Set Vref, RX VrefLevel [Byte0]: 64
1089 10:01:49.304097 [Byte1]: 64
1090 10:01:49.308146
1091 10:01:49.308581 Set Vref, RX VrefLevel [Byte0]: 65
1092 10:01:49.311477 [Byte1]: 65
1093 10:01:49.316228
1094 10:01:49.316784 Set Vref, RX VrefLevel [Byte0]: 66
1095 10:01:49.318806 [Byte1]: 66
1096 10:01:49.323262
1097 10:01:49.323843 Set Vref, RX VrefLevel [Byte0]: 67
1098 10:01:49.326862 [Byte1]: 67
1099 10:01:49.330768
1100 10:01:49.334867 Set Vref, RX VrefLevel [Byte0]: 68
1101 10:01:49.335462 [Byte1]: 68
1102 10:01:49.338369
1103 10:01:49.338798 Set Vref, RX VrefLevel [Byte0]: 69
1104 10:01:49.341992 [Byte1]: 69
1105 10:01:49.345827
1106 10:01:49.346257 Set Vref, RX VrefLevel [Byte0]: 70
1107 10:01:49.349632 [Byte1]: 70
1108 10:01:49.354663
1109 10:01:49.355190 Set Vref, RX VrefLevel [Byte0]: 71
1110 10:01:49.357082 [Byte1]: 71
1111 10:01:49.361291
1112 10:01:49.361840 Set Vref, RX VrefLevel [Byte0]: 72
1113 10:01:49.364717 [Byte1]: 72
1114 10:01:49.368918
1115 10:01:49.369448 Set Vref, RX VrefLevel [Byte0]: 73
1116 10:01:49.372400 [Byte1]: 73
1117 10:01:49.376973
1118 10:01:49.377499 Set Vref, RX VrefLevel [Byte0]: 74
1119 10:01:49.379788 [Byte1]: 74
1120 10:01:49.384239
1121 10:01:49.384769 Set Vref, RX VrefLevel [Byte0]: 75
1122 10:01:49.387953 [Byte1]: 75
1123 10:01:49.391701
1124 10:01:49.392230 Set Vref, RX VrefLevel [Byte0]: 76
1125 10:01:49.395800 [Byte1]: 76
1126 10:01:49.399521
1127 10:01:49.400054 Final RX Vref Byte 0 = 59 to rank0
1128 10:01:49.403342 Final RX Vref Byte 1 = 57 to rank0
1129 10:01:49.406181 Final RX Vref Byte 0 = 59 to rank1
1130 10:01:49.409602 Final RX Vref Byte 1 = 57 to rank1==
1131 10:01:49.413099 Dram Type= 6, Freq= 0, CH_0, rank 0
1132 10:01:49.419500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1133 10:01:49.420087 ==
1134 10:01:49.420470 DQS Delay:
1135 10:01:49.421040 DQS0 = 0, DQS1 = 0
1136 10:01:49.422883 DQM Delay:
1137 10:01:49.423315 DQM0 = 86, DQM1 = 79
1138 10:01:49.426414 DQ Delay:
1139 10:01:49.429875 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1140 10:01:49.430380 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1141 10:01:49.432541 DQ8 =68, DQ9 =64, DQ10 =84, DQ11 =76
1142 10:01:49.436017 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1143 10:01:49.439653
1144 10:01:49.440194
1145 10:01:49.446183 [DQSOSCAuto] RK0, (LSB)MR18= 0x240b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 400 ps
1146 10:01:49.449839 CH0 RK0: MR19=606, MR18=240B
1147 10:01:49.456145 CH0_RK0: MR19=0x606, MR18=0x240B, DQSOSC=400, MR23=63, INC=92, DEC=61
1148 10:01:49.456687
1149 10:01:49.459898 ----->DramcWriteLeveling(PI) begin...
1150 10:01:49.460446 ==
1151 10:01:49.462980 Dram Type= 6, Freq= 0, CH_0, rank 1
1152 10:01:49.466665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1153 10:01:49.467207 ==
1154 10:01:49.469562 Write leveling (Byte 0): 30 => 30
1155 10:01:49.472856 Write leveling (Byte 1): 27 => 27
1156 10:01:49.476847 DramcWriteLeveling(PI) end<-----
1157 10:01:49.477403
1158 10:01:49.477857 ==
1159 10:01:49.479139 Dram Type= 6, Freq= 0, CH_0, rank 1
1160 10:01:49.482784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1161 10:01:49.483333 ==
1162 10:01:49.486609 [Gating] SW mode calibration
1163 10:01:49.492656 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1164 10:01:49.499327 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1165 10:01:49.502659 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1166 10:01:49.506433 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1167 10:01:49.553779 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 10:01:49.554335 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 10:01:49.554693 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 10:01:49.555338 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 10:01:49.555729 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 10:01:49.556043 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 10:01:49.556346 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 10:01:49.556640 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 10:01:49.556932 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 10:01:49.557221 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 10:01:49.581357 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 10:01:49.582108 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 10:01:49.582661 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 10:01:49.583326 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 10:01:49.583714 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 10:01:49.584038 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1183 10:01:49.584346 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1184 10:01:49.585079 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 10:01:49.592336 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 10:01:49.595460 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 10:01:49.599305 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 10:01:49.605914 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 10:01:49.609062 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 10:01:49.612031 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 10:01:49.615302 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
1192 10:01:49.621718 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1193 10:01:49.625295 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 10:01:49.628959 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 10:01:49.635288 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 10:01:49.638582 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 10:01:49.642135 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1198 10:01:49.649030 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1199 10:01:49.652185 0 10 8 | B1->B0 | 3131 2424 | 0 0 | (0 1) (1 1)
1200 10:01:49.655430 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1201 10:01:49.662407 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 10:01:49.665553 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 10:01:49.668527 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 10:01:49.674987 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 10:01:49.679668 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 10:01:49.682041 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1207 10:01:49.685399 0 11 8 | B1->B0 | 2424 3e3e | 0 0 | (0 0) (0 0)
1208 10:01:49.693064 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1209 10:01:49.697174 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 10:01:49.699728 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 10:01:49.703459 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 10:01:49.710499 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 10:01:49.714233 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 10:01:49.717053 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1215 10:01:49.723783 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1216 10:01:49.726788 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 10:01:49.730889 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 10:01:49.737313 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 10:01:49.740625 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 10:01:49.743969 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 10:01:49.750415 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 10:01:49.753952 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 10:01:49.757021 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 10:01:49.760941 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 10:01:49.767241 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 10:01:49.770965 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 10:01:49.773667 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 10:01:49.780652 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 10:01:49.783741 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 10:01:49.787535 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1231 10:01:49.790800 Total UI for P1: 0, mck2ui 16
1232 10:01:49.793766 best dqsien dly found for B0: ( 0, 14, 2)
1233 10:01:49.800482 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1234 10:01:49.804276 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1235 10:01:49.807264 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 10:01:49.810587 Total UI for P1: 0, mck2ui 16
1237 10:01:49.813897 best dqsien dly found for B1: ( 0, 14, 10)
1238 10:01:49.817472 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1239 10:01:49.820622 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1240 10:01:49.821149
1241 10:01:49.827148 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1242 10:01:49.830168 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1243 10:01:49.830605 [Gating] SW calibration Done
1244 10:01:49.833934 ==
1245 10:01:49.834363 Dram Type= 6, Freq= 0, CH_0, rank 1
1246 10:01:49.840131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1247 10:01:49.840655 ==
1248 10:01:49.841021 RX Vref Scan: 0
1249 10:01:49.841346
1250 10:01:49.843522 RX Vref 0 -> 0, step: 1
1251 10:01:49.844070
1252 10:01:49.846834 RX Delay -130 -> 252, step: 16
1253 10:01:49.850324 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1254 10:01:49.853809 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1255 10:01:49.856765 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1256 10:01:49.864296 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1257 10:01:49.867311 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1258 10:01:49.870073 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1259 10:01:49.873850 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1260 10:01:49.877512 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1261 10:01:49.883950 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1262 10:01:49.887283 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1263 10:01:49.890776 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1264 10:01:49.894138 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1265 10:01:49.897655 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1266 10:01:49.904331 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1267 10:01:49.907625 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1268 10:01:49.910930 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1269 10:01:49.911494 ==
1270 10:01:49.914724 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 10:01:49.917288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 10:01:49.917722 ==
1273 10:01:49.920436 DQS Delay:
1274 10:01:49.920967 DQS0 = 0, DQS1 = 0
1275 10:01:49.923751 DQM Delay:
1276 10:01:49.924180 DQM0 = 86, DQM1 = 76
1277 10:01:49.924519 DQ Delay:
1278 10:01:49.927212 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1279 10:01:49.930748 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1280 10:01:49.934070 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1281 10:01:49.937254 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1282 10:01:49.937793
1283 10:01:49.938138
1284 10:01:49.940542 ==
1285 10:01:49.943941 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 10:01:49.947247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 10:01:49.947718 ==
1288 10:01:49.948064
1289 10:01:49.948390
1290 10:01:49.950742 TX Vref Scan disable
1291 10:01:49.951177 == TX Byte 0 ==
1292 10:01:49.957048 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1293 10:01:49.960068 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1294 10:01:49.960511 == TX Byte 1 ==
1295 10:01:49.966899 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1296 10:01:49.970647 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1297 10:01:49.971185 ==
1298 10:01:49.974071 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 10:01:49.976704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 10:01:49.977143 ==
1301 10:01:49.990867 TX Vref=22, minBit 2, minWin=27, winSum=440
1302 10:01:49.994501 TX Vref=24, minBit 3, minWin=27, winSum=445
1303 10:01:49.997904 TX Vref=26, minBit 7, minWin=27, winSum=445
1304 10:01:50.000628 TX Vref=28, minBit 9, minWin=27, winSum=453
1305 10:01:50.003889 TX Vref=30, minBit 9, minWin=27, winSum=451
1306 10:01:50.011422 TX Vref=32, minBit 12, minWin=27, winSum=452
1307 10:01:50.014099 [TxChooseVref] Worse bit 9, Min win 27, Win sum 453, Final Vref 28
1308 10:01:50.014618
1309 10:01:50.017159 Final TX Range 1 Vref 28
1310 10:01:50.017588
1311 10:01:50.017927 ==
1312 10:01:50.020572 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 10:01:50.023721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 10:01:50.024422 ==
1315 10:01:50.027064
1316 10:01:50.027521
1317 10:01:50.027854 TX Vref Scan disable
1318 10:01:50.030442 == TX Byte 0 ==
1319 10:01:50.033924 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1320 10:01:50.037035 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1321 10:01:50.040562 == TX Byte 1 ==
1322 10:01:50.044105 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1323 10:01:50.047108 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1324 10:01:50.050686
1325 10:01:50.051214 [DATLAT]
1326 10:01:50.051616 Freq=800, CH0 RK1
1327 10:01:50.051930
1328 10:01:50.053979 DATLAT Default: 0xa
1329 10:01:50.054496 0, 0xFFFF, sum = 0
1330 10:01:50.057504 1, 0xFFFF, sum = 0
1331 10:01:50.057994 2, 0xFFFF, sum = 0
1332 10:01:50.060701 3, 0xFFFF, sum = 0
1333 10:01:50.061211 4, 0xFFFF, sum = 0
1334 10:01:50.064944 5, 0xFFFF, sum = 0
1335 10:01:50.065477 6, 0xFFFF, sum = 0
1336 10:01:50.067707 7, 0xFFFF, sum = 0
1337 10:01:50.070810 8, 0xFFFF, sum = 0
1338 10:01:50.071312 9, 0x0, sum = 1
1339 10:01:50.071689 10, 0x0, sum = 2
1340 10:01:50.073843 11, 0x0, sum = 3
1341 10:01:50.074264 12, 0x0, sum = 4
1342 10:01:50.077663 best_step = 10
1343 10:01:50.078176
1344 10:01:50.078507 ==
1345 10:01:50.080609 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 10:01:50.084250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 10:01:50.084668 ==
1348 10:01:50.088082 RX Vref Scan: 0
1349 10:01:50.088602
1350 10:01:50.088932 RX Vref 0 -> 0, step: 1
1351 10:01:50.089239
1352 10:01:50.091225 RX Delay -95 -> 252, step: 8
1353 10:01:50.097349 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1354 10:01:50.100950 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1355 10:01:50.104246 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1356 10:01:50.107434 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1357 10:01:50.110813 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1358 10:01:50.117726 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1359 10:01:50.120647 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1360 10:01:50.123826 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1361 10:01:50.127597 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1362 10:01:50.130843 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1363 10:01:50.137352 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1364 10:01:50.140970 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1365 10:01:50.143955 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1366 10:01:50.147465 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1367 10:01:50.150687 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1368 10:01:50.158008 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1369 10:01:50.158532 ==
1370 10:01:50.160700 Dram Type= 6, Freq= 0, CH_0, rank 1
1371 10:01:50.164187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 10:01:50.164703 ==
1373 10:01:50.165038 DQS Delay:
1374 10:01:50.167554 DQS0 = 0, DQS1 = 0
1375 10:01:50.167969 DQM Delay:
1376 10:01:50.170885 DQM0 = 87, DQM1 = 78
1377 10:01:50.171442 DQ Delay:
1378 10:01:50.173750 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1379 10:01:50.178037 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1380 10:01:50.180763 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1381 10:01:50.183997 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1382 10:01:50.184531
1383 10:01:50.184864
1384 10:01:50.191546 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1385 10:01:50.194367 CH0 RK1: MR19=606, MR18=2C15
1386 10:01:50.200842 CH0_RK1: MR19=0x606, MR18=0x2C15, DQSOSC=398, MR23=63, INC=93, DEC=62
1387 10:01:50.204297 [RxdqsGatingPostProcess] freq 800
1388 10:01:50.211531 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1389 10:01:50.214678 Pre-setting of DQS Precalculation
1390 10:01:50.217679 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1391 10:01:50.218207 ==
1392 10:01:50.220805 Dram Type= 6, Freq= 0, CH_1, rank 0
1393 10:01:50.224426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 10:01:50.225201 ==
1395 10:01:50.231112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1396 10:01:50.237588 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1397 10:01:50.245850 [CA 0] Center 36 (6~66) winsize 61
1398 10:01:50.249397 [CA 1] Center 36 (6~66) winsize 61
1399 10:01:50.252106 [CA 2] Center 34 (5~64) winsize 60
1400 10:01:50.255703 [CA 3] Center 33 (3~64) winsize 62
1401 10:01:50.259287 [CA 4] Center 34 (4~65) winsize 62
1402 10:01:50.262438 [CA 5] Center 33 (3~64) winsize 62
1403 10:01:50.262960
1404 10:01:50.265850 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1405 10:01:50.266371
1406 10:01:50.269333 [CATrainingPosCal] consider 1 rank data
1407 10:01:50.272140 u2DelayCellTimex100 = 270/100 ps
1408 10:01:50.275702 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1409 10:01:50.282614 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1410 10:01:50.285305 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1411 10:01:50.288968 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1412 10:01:50.292024 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1413 10:01:50.295208 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1414 10:01:50.295695
1415 10:01:50.298160 CA PerBit enable=1, Macro0, CA PI delay=33
1416 10:01:50.298596
1417 10:01:50.302133 [CBTSetCACLKResult] CA Dly = 33
1418 10:01:50.302661 CS Dly: 5 (0~36)
1419 10:01:50.305195 ==
1420 10:01:50.308272 Dram Type= 6, Freq= 0, CH_1, rank 1
1421 10:01:50.312033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 10:01:50.312562 ==
1423 10:01:50.314930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1424 10:01:50.321875 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1425 10:01:50.331948 [CA 0] Center 36 (6~66) winsize 61
1426 10:01:50.335341 [CA 1] Center 36 (6~66) winsize 61
1427 10:01:50.338966 [CA 2] Center 34 (4~64) winsize 61
1428 10:01:50.341790 [CA 3] Center 33 (3~64) winsize 62
1429 10:01:50.344462 [CA 4] Center 34 (4~65) winsize 62
1430 10:01:50.348251 [CA 5] Center 33 (3~64) winsize 62
1431 10:01:50.348787
1432 10:01:50.351936 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1433 10:01:50.352374
1434 10:01:50.355645 [CATrainingPosCal] consider 2 rank data
1435 10:01:50.359607 u2DelayCellTimex100 = 270/100 ps
1436 10:01:50.363461 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1437 10:01:50.366437 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1438 10:01:50.370237 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1439 10:01:50.373919 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1440 10:01:50.377641 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1441 10:01:50.381360 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1442 10:01:50.381795
1443 10:01:50.384921 CA PerBit enable=1, Macro0, CA PI delay=33
1444 10:01:50.385353
1445 10:01:50.388143 [CBTSetCACLKResult] CA Dly = 33
1446 10:01:50.388574 CS Dly: 5 (0~37)
1447 10:01:50.388915
1448 10:01:50.391592 ----->DramcWriteLeveling(PI) begin...
1449 10:01:50.394976 ==
1450 10:01:50.398559 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 10:01:50.401332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 10:01:50.401790 ==
1453 10:01:50.404641 Write leveling (Byte 0): 26 => 26
1454 10:01:50.407914 Write leveling (Byte 1): 28 => 28
1455 10:01:50.411166 DramcWriteLeveling(PI) end<-----
1456 10:01:50.411620
1457 10:01:50.411956 ==
1458 10:01:50.414862 Dram Type= 6, Freq= 0, CH_1, rank 0
1459 10:01:50.418473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1460 10:01:50.418999 ==
1461 10:01:50.421391 [Gating] SW mode calibration
1462 10:01:50.427958 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1463 10:01:50.432005 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1464 10:01:50.438219 0 6 0 | B1->B0 | 2323 2323 | 1 0 | (1 1) (1 1)
1465 10:01:50.441667 0 6 4 | B1->B0 | 2323 2323 | 1 0 | (1 1) (1 0)
1466 10:01:50.444661 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 10:01:50.451977 0 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1468 10:01:50.454894 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 10:01:50.458365 0 6 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1470 10:01:50.464980 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 10:01:50.468364 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 10:01:50.471389 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 10:01:50.478668 0 7 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1474 10:01:50.481448 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1475 10:01:50.485153 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 10:01:50.491959 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 10:01:50.495121 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 10:01:50.498164 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 10:01:50.504867 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 10:01:50.508454 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 10:01:50.511730 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1482 10:01:50.514846 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1483 10:01:50.521988 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1484 10:01:50.524873 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 10:01:50.528417 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 10:01:50.534998 0 8 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1487 10:01:50.538453 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 10:01:50.541910 0 9 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1489 10:01:50.548403 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 10:01:50.551118 0 9 8 | B1->B0 | 2525 2424 | 1 1 | (1 1) (1 1)
1491 10:01:50.554413 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1492 10:01:50.561576 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 10:01:50.565270 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1494 10:01:50.568056 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 10:01:50.575692 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1496 10:01:50.578000 0 10 0 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
1497 10:01:50.581216 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 10:01:50.588352 0 10 8 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
1499 10:01:50.591103 0 10 12 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1500 10:01:50.594760 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 10:01:50.601425 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 10:01:50.604546 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 10:01:50.607758 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 10:01:50.614389 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 10:01:50.618228 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 10:01:50.621401 0 11 8 | B1->B0 | 3130 2c2b | 1 1 | (0 0) (0 0)
1507 10:01:50.625374 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 10:01:50.631710 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 10:01:50.635271 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 10:01:50.638246 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 10:01:50.644895 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 10:01:50.648038 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 10:01:50.651541 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 10:01:50.658563 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1515 10:01:50.662264 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1516 10:01:50.664822 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 10:01:50.671871 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 10:01:50.675004 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 10:01:50.677677 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 10:01:50.684418 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 10:01:50.687649 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 10:01:50.691132 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 10:01:50.697681 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 10:01:50.701150 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 10:01:50.704614 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 10:01:50.711865 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 10:01:50.714604 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 10:01:50.717834 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 10:01:50.724803 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 10:01:50.727789 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 10:01:50.731080 Total UI for P1: 0, mck2ui 16
1532 10:01:50.734911 best dqsien dly found for B0: ( 0, 14, 6)
1533 10:01:50.738133 Total UI for P1: 0, mck2ui 16
1534 10:01:50.741835 best dqsien dly found for B1: ( 0, 14, 6)
1535 10:01:50.744765 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1536 10:01:50.748193 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1537 10:01:50.748618
1538 10:01:50.751429 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1539 10:01:50.754420 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1540 10:01:50.757860 [Gating] SW calibration Done
1541 10:01:50.758351 ==
1542 10:01:50.761529 Dram Type= 6, Freq= 0, CH_1, rank 0
1543 10:01:50.764905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1544 10:01:50.765482 ==
1545 10:01:50.768037 RX Vref Scan: 0
1546 10:01:50.768477
1547 10:01:50.768914 RX Vref 0 -> 0, step: 1
1548 10:01:50.769326
1549 10:01:50.771570 RX Delay -130 -> 252, step: 16
1550 10:01:50.775011 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1551 10:01:50.781365 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1552 10:01:50.784326 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1553 10:01:50.788491 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1554 10:01:50.790936 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1555 10:01:50.794382 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1556 10:01:50.800990 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1557 10:01:50.804889 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1558 10:01:50.808012 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1559 10:01:50.810966 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1560 10:01:50.814742 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1561 10:01:50.821014 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1562 10:01:50.824106 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1563 10:01:50.827469 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1564 10:01:50.831327 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1565 10:01:50.837634 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1566 10:01:50.838289 ==
1567 10:01:50.840736 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 10:01:50.844601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 10:01:50.845167 ==
1570 10:01:50.845549 DQS Delay:
1571 10:01:50.847882 DQS0 = 0, DQS1 = 0
1572 10:01:50.848322 DQM Delay:
1573 10:01:50.851403 DQM0 = 85, DQM1 = 77
1574 10:01:50.851863 DQ Delay:
1575 10:01:50.854168 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1576 10:01:50.857657 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1577 10:01:50.861265 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1578 10:01:50.864191 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1579 10:01:50.864565
1580 10:01:50.864874
1581 10:01:50.865171 ==
1582 10:01:50.867405 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 10:01:50.871213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 10:01:50.871633 ==
1585 10:01:50.871946
1586 10:01:50.872236
1587 10:01:50.874446 TX Vref Scan disable
1588 10:01:50.877613 == TX Byte 0 ==
1589 10:01:50.880818 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1590 10:01:50.884262 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1591 10:01:50.887864 == TX Byte 1 ==
1592 10:01:50.890916 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1593 10:01:50.894117 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1594 10:01:50.894507 ==
1595 10:01:50.897162 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 10:01:50.900569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 10:01:50.903971 ==
1598 10:01:50.915034 TX Vref=22, minBit 1, minWin=27, winSum=437
1599 10:01:50.918933 TX Vref=24, minBit 1, minWin=27, winSum=440
1600 10:01:50.922288 TX Vref=26, minBit 0, minWin=27, winSum=446
1601 10:01:50.925066 TX Vref=28, minBit 1, minWin=28, winSum=451
1602 10:01:50.928814 TX Vref=30, minBit 1, minWin=28, winSum=452
1603 10:01:50.932750 TX Vref=32, minBit 11, minWin=27, winSum=450
1604 10:01:50.939619 [TxChooseVref] Worse bit 1, Min win 28, Win sum 452, Final Vref 30
1605 10:01:50.939702
1606 10:01:50.942709 Final TX Range 1 Vref 30
1607 10:01:50.942792
1608 10:01:50.942857 ==
1609 10:01:50.946889 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 10:01:50.949409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 10:01:50.949492 ==
1612 10:01:50.949557
1613 10:01:50.949616
1614 10:01:50.952823 TX Vref Scan disable
1615 10:01:50.956161 == TX Byte 0 ==
1616 10:01:50.959683 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1617 10:01:50.963220 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1618 10:01:50.966086 == TX Byte 1 ==
1619 10:01:50.970086 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1620 10:01:50.973100 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1621 10:01:50.973183
1622 10:01:50.973247 [DATLAT]
1623 10:01:50.976491 Freq=800, CH1 RK0
1624 10:01:50.976574
1625 10:01:50.979949 DATLAT Default: 0xa
1626 10:01:50.980031 0, 0xFFFF, sum = 0
1627 10:01:50.983048 1, 0xFFFF, sum = 0
1628 10:01:50.983131 2, 0xFFFF, sum = 0
1629 10:01:50.986221 3, 0xFFFF, sum = 0
1630 10:01:50.986304 4, 0xFFFF, sum = 0
1631 10:01:50.989650 5, 0xFFFF, sum = 0
1632 10:01:50.989734 6, 0xFFFF, sum = 0
1633 10:01:50.993011 7, 0xFFFF, sum = 0
1634 10:01:50.993095 8, 0xFFFF, sum = 0
1635 10:01:50.997011 9, 0x0, sum = 1
1636 10:01:50.997095 10, 0x0, sum = 2
1637 10:01:50.999846 11, 0x0, sum = 3
1638 10:01:50.999929 12, 0x0, sum = 4
1639 10:01:50.999995 best_step = 10
1640 10:01:51.003005
1641 10:01:51.003087 ==
1642 10:01:51.006246 Dram Type= 6, Freq= 0, CH_1, rank 0
1643 10:01:51.009953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1644 10:01:51.010036 ==
1645 10:01:51.010101 RX Vref Scan: 1
1646 10:01:51.010162
1647 10:01:51.013239 Set Vref Range= 32 -> 127
1648 10:01:51.013321
1649 10:01:51.016495 RX Vref 32 -> 127, step: 1
1650 10:01:51.016577
1651 10:01:51.019716 RX Delay -95 -> 252, step: 8
1652 10:01:51.019800
1653 10:01:51.023040 Set Vref, RX VrefLevel [Byte0]: 32
1654 10:01:51.026839 [Byte1]: 32
1655 10:01:51.026923
1656 10:01:51.029698 Set Vref, RX VrefLevel [Byte0]: 33
1657 10:01:51.033161 [Byte1]: 33
1658 10:01:51.033245
1659 10:01:51.036343 Set Vref, RX VrefLevel [Byte0]: 34
1660 10:01:51.039329 [Byte1]: 34
1661 10:01:51.043377
1662 10:01:51.046674 Set Vref, RX VrefLevel [Byte0]: 35
1663 10:01:51.046758 [Byte1]: 35
1664 10:01:51.050748
1665 10:01:51.050831 Set Vref, RX VrefLevel [Byte0]: 36
1666 10:01:51.054135 [Byte1]: 36
1667 10:01:51.058544
1668 10:01:51.058627 Set Vref, RX VrefLevel [Byte0]: 37
1669 10:01:51.061961 [Byte1]: 37
1670 10:01:51.065932
1671 10:01:51.066015 Set Vref, RX VrefLevel [Byte0]: 38
1672 10:01:51.069683 [Byte1]: 38
1673 10:01:51.073654
1674 10:01:51.073737 Set Vref, RX VrefLevel [Byte0]: 39
1675 10:01:51.080038 [Byte1]: 39
1676 10:01:51.080122
1677 10:01:51.083508 Set Vref, RX VrefLevel [Byte0]: 40
1678 10:01:51.086754 [Byte1]: 40
1679 10:01:51.086838
1680 10:01:51.090270 Set Vref, RX VrefLevel [Byte0]: 41
1681 10:01:51.093055 [Byte1]: 41
1682 10:01:51.096450
1683 10:01:51.096534 Set Vref, RX VrefLevel [Byte0]: 42
1684 10:01:51.099679 [Byte1]: 42
1685 10:01:51.103906
1686 10:01:51.103989 Set Vref, RX VrefLevel [Byte0]: 43
1687 10:01:51.107328 [Byte1]: 43
1688 10:01:51.111685
1689 10:01:51.111768 Set Vref, RX VrefLevel [Byte0]: 44
1690 10:01:51.114869 [Byte1]: 44
1691 10:01:51.119137
1692 10:01:51.119221 Set Vref, RX VrefLevel [Byte0]: 45
1693 10:01:51.122639 [Byte1]: 45
1694 10:01:51.126994
1695 10:01:51.127077 Set Vref, RX VrefLevel [Byte0]: 46
1696 10:01:51.129958 [Byte1]: 46
1697 10:01:51.134538
1698 10:01:51.134622 Set Vref, RX VrefLevel [Byte0]: 47
1699 10:01:51.137503 [Byte1]: 47
1700 10:01:51.141938
1701 10:01:51.142021 Set Vref, RX VrefLevel [Byte0]: 48
1702 10:01:51.145473 [Byte1]: 48
1703 10:01:51.149405
1704 10:01:51.149488 Set Vref, RX VrefLevel [Byte0]: 49
1705 10:01:51.152618 [Byte1]: 49
1706 10:01:51.156986
1707 10:01:51.157070 Set Vref, RX VrefLevel [Byte0]: 50
1708 10:01:51.160469 [Byte1]: 50
1709 10:01:51.164898
1710 10:01:51.164981 Set Vref, RX VrefLevel [Byte0]: 51
1711 10:01:51.168159 [Byte1]: 51
1712 10:01:51.172646
1713 10:01:51.172730 Set Vref, RX VrefLevel [Byte0]: 52
1714 10:01:51.175890 [Byte1]: 52
1715 10:01:51.179917
1716 10:01:51.180000 Set Vref, RX VrefLevel [Byte0]: 53
1717 10:01:51.183285 [Byte1]: 53
1718 10:01:51.188013
1719 10:01:51.188096 Set Vref, RX VrefLevel [Byte0]: 54
1720 10:01:51.190740 [Byte1]: 54
1721 10:01:51.195237
1722 10:01:51.195352 Set Vref, RX VrefLevel [Byte0]: 55
1723 10:01:51.198838 [Byte1]: 55
1724 10:01:51.202833
1725 10:01:51.202916 Set Vref, RX VrefLevel [Byte0]: 56
1726 10:01:51.206303 [Byte1]: 56
1727 10:01:51.210224
1728 10:01:51.210313 Set Vref, RX VrefLevel [Byte0]: 57
1729 10:01:51.213740 [Byte1]: 57
1730 10:01:51.218186
1731 10:01:51.218270 Set Vref, RX VrefLevel [Byte0]: 58
1732 10:01:51.221478 [Byte1]: 58
1733 10:01:51.225268
1734 10:01:51.225352 Set Vref, RX VrefLevel [Byte0]: 59
1735 10:01:51.228668 [Byte1]: 59
1736 10:01:51.233140
1737 10:01:51.233225 Set Vref, RX VrefLevel [Byte0]: 60
1738 10:01:51.236668 [Byte1]: 60
1739 10:01:51.241233
1740 10:01:51.241316 Set Vref, RX VrefLevel [Byte0]: 61
1741 10:01:51.243657 [Byte1]: 61
1742 10:01:51.248136
1743 10:01:51.248220 Set Vref, RX VrefLevel [Byte0]: 62
1744 10:01:51.251400 [Byte1]: 62
1745 10:01:51.255757
1746 10:01:51.255840 Set Vref, RX VrefLevel [Byte0]: 63
1747 10:01:51.259086 [Byte1]: 63
1748 10:01:51.263320
1749 10:01:51.263430 Set Vref, RX VrefLevel [Byte0]: 64
1750 10:01:51.267183 [Byte1]: 64
1751 10:01:51.271030
1752 10:01:51.271114 Set Vref, RX VrefLevel [Byte0]: 65
1753 10:01:51.274268 [Byte1]: 65
1754 10:01:51.278541
1755 10:01:51.278624 Set Vref, RX VrefLevel [Byte0]: 66
1756 10:01:51.282125 [Byte1]: 66
1757 10:01:51.286511
1758 10:01:51.286594 Set Vref, RX VrefLevel [Byte0]: 67
1759 10:01:51.289384 [Byte1]: 67
1760 10:01:51.294017
1761 10:01:51.294101 Set Vref, RX VrefLevel [Byte0]: 68
1762 10:01:51.297816 [Byte1]: 68
1763 10:01:51.301565
1764 10:01:51.301649 Set Vref, RX VrefLevel [Byte0]: 69
1765 10:01:51.304834 [Byte1]: 69
1766 10:01:51.309040
1767 10:01:51.309124 Set Vref, RX VrefLevel [Byte0]: 70
1768 10:01:51.312534 [Byte1]: 70
1769 10:01:51.316763
1770 10:01:51.316847 Set Vref, RX VrefLevel [Byte0]: 71
1771 10:01:51.319639 [Byte1]: 71
1772 10:01:51.324247
1773 10:01:51.324331 Set Vref, RX VrefLevel [Byte0]: 72
1774 10:01:51.327323 [Byte1]: 72
1775 10:01:51.331905
1776 10:01:51.331989 Set Vref, RX VrefLevel [Byte0]: 73
1777 10:01:51.335260 [Byte1]: 73
1778 10:01:51.339628
1779 10:01:51.339711 Set Vref, RX VrefLevel [Byte0]: 74
1780 10:01:51.342988 [Byte1]: 74
1781 10:01:51.347070
1782 10:01:51.347189 Set Vref, RX VrefLevel [Byte0]: 75
1783 10:01:51.350356 [Byte1]: 75
1784 10:01:51.355496
1785 10:01:51.355580 Set Vref, RX VrefLevel [Byte0]: 76
1786 10:01:51.358115 [Byte1]: 76
1787 10:01:51.362366
1788 10:01:51.362449 Set Vref, RX VrefLevel [Byte0]: 77
1789 10:01:51.365644 [Byte1]: 77
1790 10:01:51.369679
1791 10:01:51.369770 Set Vref, RX VrefLevel [Byte0]: 78
1792 10:01:51.373121 [Byte1]: 78
1793 10:01:51.377734
1794 10:01:51.377818 Set Vref, RX VrefLevel [Byte0]: 79
1795 10:01:51.380539 [Byte1]: 79
1796 10:01:51.384878
1797 10:01:51.384962 Set Vref, RX VrefLevel [Byte0]: 80
1798 10:01:51.388246 [Byte1]: 80
1799 10:01:51.392625
1800 10:01:51.392708 Final RX Vref Byte 0 = 59 to rank0
1801 10:01:51.395721 Final RX Vref Byte 1 = 58 to rank0
1802 10:01:51.399687 Final RX Vref Byte 0 = 59 to rank1
1803 10:01:51.402859 Final RX Vref Byte 1 = 58 to rank1==
1804 10:01:51.406148 Dram Type= 6, Freq= 0, CH_1, rank 0
1805 10:01:51.412764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 10:01:51.412848 ==
1807 10:01:51.412920 DQS Delay:
1808 10:01:51.413005 DQS0 = 0, DQS1 = 0
1809 10:01:51.415694 DQM Delay:
1810 10:01:51.415828 DQM0 = 84, DQM1 = 75
1811 10:01:51.419294 DQ Delay:
1812 10:01:51.422695 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1813 10:01:51.422780 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =80
1814 10:01:51.426120 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
1815 10:01:51.429468 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =80
1816 10:01:51.432629
1817 10:01:51.432705
1818 10:01:51.439133 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a00, (MSB)MR19= 0x606, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
1819 10:01:51.442275 CH1 RK0: MR19=606, MR18=2A00
1820 10:01:51.449003 CH1_RK0: MR19=0x606, MR18=0x2A00, DQSOSC=399, MR23=63, INC=92, DEC=61
1821 10:01:51.449085
1822 10:01:51.452400 ----->DramcWriteLeveling(PI) begin...
1823 10:01:51.452484 ==
1824 10:01:51.455964 Dram Type= 6, Freq= 0, CH_1, rank 1
1825 10:01:51.459397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1826 10:01:51.459481 ==
1827 10:01:51.462648 Write leveling (Byte 0): 26 => 26
1828 10:01:51.466090 Write leveling (Byte 1): 32 => 32
1829 10:01:51.469399 DramcWriteLeveling(PI) end<-----
1830 10:01:51.469481
1831 10:01:51.469546 ==
1832 10:01:51.472272 Dram Type= 6, Freq= 0, CH_1, rank 1
1833 10:01:51.475842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 10:01:51.475931 ==
1835 10:01:51.479105 [Gating] SW mode calibration
1836 10:01:51.485797 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1837 10:01:51.492632 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1838 10:01:51.496050 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1839 10:01:51.498935 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1840 10:01:51.505754 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1841 10:01:51.509328 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 10:01:51.512715 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 10:01:51.519532 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 10:01:51.522278 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 10:01:51.525644 0 6 28 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1846 10:01:51.532418 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 10:01:51.535724 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 10:01:51.539477 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 10:01:51.546094 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 10:01:51.549705 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 10:01:51.552752 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1852 10:01:51.556090 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 10:01:51.562339 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1854 10:01:51.566122 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1855 10:01:51.569388 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1856 10:01:51.576006 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1857 10:01:51.579094 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 10:01:51.582455 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 10:01:51.589299 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 10:01:51.592726 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 10:01:51.596181 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 10:01:51.603092 0 9 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1863 10:01:51.605589 0 9 4 | B1->B0 | 2424 2424 | 0 1 | (0 0) (1 1)
1864 10:01:51.609079 0 9 8 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
1865 10:01:51.615760 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 10:01:51.619186 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 10:01:51.622911 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1868 10:01:51.629264 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1869 10:01:51.632762 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1870 10:01:51.635599 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
1871 10:01:51.642246 0 10 4 | B1->B0 | 3030 2929 | 0 0 | (0 1) (1 0)
1872 10:01:51.645960 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1873 10:01:51.649324 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 10:01:51.652658 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 10:01:51.659210 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 10:01:51.662641 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 10:01:51.665843 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 10:01:51.672238 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 10:01:51.675965 0 11 4 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (0 0)
1880 10:01:51.679151 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1881 10:01:51.685807 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 10:01:51.689654 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 10:01:51.692517 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 10:01:51.698821 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 10:01:51.702363 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 10:01:51.705679 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1887 10:01:51.712545 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1888 10:01:51.716089 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 10:01:51.718870 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 10:01:51.725968 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 10:01:51.728926 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 10:01:51.732517 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 10:01:51.739557 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 10:01:51.742752 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 10:01:51.745979 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 10:01:51.749392 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 10:01:51.756209 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 10:01:51.759756 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 10:01:51.762624 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 10:01:51.769560 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 10:01:51.773007 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 10:01:51.775850 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 10:01:51.782670 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1904 10:01:51.786490 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 10:01:51.789631 Total UI for P1: 0, mck2ui 16
1906 10:01:51.792952 best dqsien dly found for B0: ( 0, 14, 4)
1907 10:01:51.795912 Total UI for P1: 0, mck2ui 16
1908 10:01:51.799461 best dqsien dly found for B1: ( 0, 14, 4)
1909 10:01:51.802725 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1910 10:01:51.806250 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1911 10:01:51.806335
1912 10:01:51.809256 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1913 10:01:51.812666 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1914 10:01:51.816045 [Gating] SW calibration Done
1915 10:01:51.816129 ==
1916 10:01:51.819646 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 10:01:51.822923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 10:01:51.823007 ==
1919 10:01:51.825797 RX Vref Scan: 0
1920 10:01:51.825881
1921 10:01:51.829418 RX Vref 0 -> 0, step: 1
1922 10:01:51.829502
1923 10:01:51.829570 RX Delay -130 -> 252, step: 16
1924 10:01:51.835801 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1925 10:01:51.838978 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1926 10:01:51.842414 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1927 10:01:51.845762 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1928 10:01:51.849505 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1929 10:01:51.855855 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1930 10:01:51.859119 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1931 10:01:51.862697 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1932 10:01:51.866101 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1933 10:01:51.869230 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1934 10:01:51.875698 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1935 10:01:51.878988 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1936 10:01:51.882234 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1937 10:01:51.885976 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1938 10:01:51.892492 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1939 10:01:51.895619 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1940 10:01:51.895703 ==
1941 10:01:51.899343 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 10:01:51.902257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 10:01:51.902343 ==
1944 10:01:51.902410 DQS Delay:
1945 10:01:51.905882 DQS0 = 0, DQS1 = 0
1946 10:01:51.905966 DQM Delay:
1947 10:01:51.908827 DQM0 = 83, DQM1 = 78
1948 10:01:51.908911 DQ Delay:
1949 10:01:51.912278 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1950 10:01:51.915791 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1951 10:01:51.919208 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1952 10:01:51.922528 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1953 10:01:51.922613
1954 10:01:51.922679
1955 10:01:51.922740 ==
1956 10:01:51.925909 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 10:01:51.929561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 10:01:51.932758 ==
1959 10:01:51.932842
1960 10:01:51.932908
1961 10:01:51.932970 TX Vref Scan disable
1962 10:01:51.936098 == TX Byte 0 ==
1963 10:01:51.939066 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1964 10:01:51.942249 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1965 10:01:51.945507 == TX Byte 1 ==
1966 10:01:51.948970 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1967 10:01:51.952301 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1968 10:01:51.952386 ==
1969 10:01:51.955809 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 10:01:51.962599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 10:01:51.962684 ==
1972 10:01:51.975072 TX Vref=22, minBit 1, minWin=27, winSum=441
1973 10:01:51.978371 TX Vref=24, minBit 0, minWin=27, winSum=444
1974 10:01:51.981401 TX Vref=26, minBit 8, minWin=27, winSum=447
1975 10:01:51.985111 TX Vref=28, minBit 8, minWin=27, winSum=448
1976 10:01:51.988281 TX Vref=30, minBit 0, minWin=28, winSum=453
1977 10:01:51.991649 TX Vref=32, minBit 0, minWin=28, winSum=451
1978 10:01:51.998577 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
1979 10:01:51.998662
1980 10:01:52.001974 Final TX Range 1 Vref 30
1981 10:01:52.002059
1982 10:01:52.002125 ==
1983 10:01:52.005422 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 10:01:52.008814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 10:01:52.008899 ==
1986 10:01:52.008966
1987 10:01:52.009027
1988 10:01:52.011616 TX Vref Scan disable
1989 10:01:52.015040 == TX Byte 0 ==
1990 10:01:52.018267 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1991 10:01:52.021713 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1992 10:01:52.025144 == TX Byte 1 ==
1993 10:01:52.028772 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1994 10:01:52.032161 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1995 10:01:52.032252
1996 10:01:52.035117 [DATLAT]
1997 10:01:52.035201 Freq=800, CH1 RK1
1998 10:01:52.035268
1999 10:01:52.038862 DATLAT Default: 0xa
2000 10:01:52.038946 0, 0xFFFF, sum = 0
2001 10:01:52.041648 1, 0xFFFF, sum = 0
2002 10:01:52.041732 2, 0xFFFF, sum = 0
2003 10:01:52.045254 3, 0xFFFF, sum = 0
2004 10:01:52.045340 4, 0xFFFF, sum = 0
2005 10:01:52.048550 5, 0xFFFF, sum = 0
2006 10:01:52.048636 6, 0xFFFF, sum = 0
2007 10:01:52.051906 7, 0xFFFF, sum = 0
2008 10:01:52.051992 8, 0xFFFF, sum = 0
2009 10:01:52.055246 9, 0x0, sum = 1
2010 10:01:52.055331 10, 0x0, sum = 2
2011 10:01:52.059075 11, 0x0, sum = 3
2012 10:01:52.059160 12, 0x0, sum = 4
2013 10:01:52.061849 best_step = 10
2014 10:01:52.061933
2015 10:01:52.061999 ==
2016 10:01:52.065288 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 10:01:52.069010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 10:01:52.069095 ==
2019 10:01:52.071777 RX Vref Scan: 0
2020 10:01:52.071868
2021 10:01:52.071975 RX Vref 0 -> 0, step: 1
2022 10:01:52.072038
2023 10:01:52.074943 RX Delay -95 -> 252, step: 8
2024 10:01:52.081683 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2025 10:01:52.085179 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2026 10:01:52.088327 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2027 10:01:52.091598 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2028 10:01:52.095381 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2029 10:01:52.101816 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2030 10:01:52.105289 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2031 10:01:52.108442 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2032 10:01:52.111760 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2033 10:01:52.115184 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2034 10:01:52.121739 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2035 10:01:52.124900 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2036 10:01:52.128698 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2037 10:01:52.131609 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2038 10:01:52.135297 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2039 10:01:52.141705 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2040 10:01:52.141790 ==
2041 10:01:52.144953 Dram Type= 6, Freq= 0, CH_1, rank 1
2042 10:01:52.148831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2043 10:01:52.148915 ==
2044 10:01:52.148981 DQS Delay:
2045 10:01:52.151915 DQS0 = 0, DQS1 = 0
2046 10:01:52.151998 DQM Delay:
2047 10:01:52.155243 DQM0 = 80, DQM1 = 75
2048 10:01:52.155326 DQ Delay:
2049 10:01:52.158512 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2050 10:01:52.161670 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2051 10:01:52.165187 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2052 10:01:52.168204 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2053 10:01:52.168287
2054 10:01:52.168351
2055 10:01:52.174611 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2056 10:01:52.177922 CH1 RK1: MR19=606, MR18=1F29
2057 10:01:52.185063 CH1_RK1: MR19=0x606, MR18=0x1F29, DQSOSC=399, MR23=63, INC=92, DEC=61
2058 10:01:52.188553 [RxdqsGatingPostProcess] freq 800
2059 10:01:52.194813 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2060 10:01:52.198068 Pre-setting of DQS Precalculation
2061 10:01:52.201709 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2062 10:01:52.207999 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2063 10:01:52.215238 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2064 10:01:52.215327
2065 10:01:52.215404
2066 10:01:52.218645 [Calibration Summary] 1600 Mbps
2067 10:01:52.221976 CH 0, Rank 0
2068 10:01:52.222060 SW Impedance : PASS
2069 10:01:52.225160 DUTY Scan : NO K
2070 10:01:52.228325 ZQ Calibration : PASS
2071 10:01:52.228413 Jitter Meter : NO K
2072 10:01:52.231912 CBT Training : PASS
2073 10:01:52.235154 Write leveling : PASS
2074 10:01:52.235239 RX DQS gating : PASS
2075 10:01:52.238030 RX DQ/DQS(RDDQC) : PASS
2076 10:01:52.238121 TX DQ/DQS : PASS
2077 10:01:52.241404 RX DATLAT : PASS
2078 10:01:52.244845 RX DQ/DQS(Engine): PASS
2079 10:01:52.244931 TX OE : NO K
2080 10:01:52.248384 All Pass.
2081 10:01:52.248468
2082 10:01:52.248535 CH 0, Rank 1
2083 10:01:52.251682 SW Impedance : PASS
2084 10:01:52.251766 DUTY Scan : NO K
2085 10:01:52.255231 ZQ Calibration : PASS
2086 10:01:52.258210 Jitter Meter : NO K
2087 10:01:52.258294 CBT Training : PASS
2088 10:01:52.261913 Write leveling : PASS
2089 10:01:52.265002 RX DQS gating : PASS
2090 10:01:52.265086 RX DQ/DQS(RDDQC) : PASS
2091 10:01:52.268727 TX DQ/DQS : PASS
2092 10:01:52.271517 RX DATLAT : PASS
2093 10:01:52.271600 RX DQ/DQS(Engine): PASS
2094 10:01:52.275461 TX OE : NO K
2095 10:01:52.275545 All Pass.
2096 10:01:52.275611
2097 10:01:52.278704 CH 1, Rank 0
2098 10:01:52.278786 SW Impedance : PASS
2099 10:01:52.281433 DUTY Scan : NO K
2100 10:01:52.284848 ZQ Calibration : PASS
2101 10:01:52.284931 Jitter Meter : NO K
2102 10:01:52.287887 CBT Training : PASS
2103 10:01:52.287971 Write leveling : PASS
2104 10:01:52.291637 RX DQS gating : PASS
2105 10:01:52.294772 RX DQ/DQS(RDDQC) : PASS
2106 10:01:52.294855 TX DQ/DQS : PASS
2107 10:01:52.298471 RX DATLAT : PASS
2108 10:01:52.301619 RX DQ/DQS(Engine): PASS
2109 10:01:52.301703 TX OE : NO K
2110 10:01:52.304722 All Pass.
2111 10:01:52.304805
2112 10:01:52.304872 CH 1, Rank 1
2113 10:01:52.308434 SW Impedance : PASS
2114 10:01:52.308517 DUTY Scan : NO K
2115 10:01:52.311657 ZQ Calibration : PASS
2116 10:01:52.314778 Jitter Meter : NO K
2117 10:01:52.314862 CBT Training : PASS
2118 10:01:52.318226 Write leveling : PASS
2119 10:01:52.321584 RX DQS gating : PASS
2120 10:01:52.321668 RX DQ/DQS(RDDQC) : PASS
2121 10:01:52.324685 TX DQ/DQS : PASS
2122 10:01:52.327994 RX DATLAT : PASS
2123 10:01:52.328077 RX DQ/DQS(Engine): PASS
2124 10:01:52.331856 TX OE : NO K
2125 10:01:52.331941 All Pass.
2126 10:01:52.332008
2127 10:01:52.334907 DramC Write-DBI off
2128 10:01:52.338392 PER_BANK_REFRESH: Hybrid Mode
2129 10:01:52.338465 TX_TRACKING: ON
2130 10:01:52.341260 [GetDramInforAfterCalByMRR] Vendor 6.
2131 10:01:52.344747 [GetDramInforAfterCalByMRR] Revision 606.
2132 10:01:52.348248 [GetDramInforAfterCalByMRR] Revision 2 0.
2133 10:01:52.351250 MR0 0x3b3b
2134 10:01:52.351352 MR8 0x5151
2135 10:01:52.354817 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2136 10:01:52.354923
2137 10:01:52.355014 MR0 0x3b3b
2138 10:01:52.358108 MR8 0x5151
2139 10:01:52.361572 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2140 10:01:52.361655
2141 10:01:52.368269 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2142 10:01:52.371252 [FAST_K] Save calibration result to emmc
2143 10:01:52.377988 [FAST_K] Save calibration result to emmc
2144 10:01:52.378071 dram_init: config_dvfs: 1
2145 10:01:52.381185 dramc_set_vcore_voltage set vcore to 662500
2146 10:01:52.384705 Read voltage for 1200, 2
2147 10:01:52.384788 Vio18 = 0
2148 10:01:52.388333 Vcore = 662500
2149 10:01:52.388416 Vdram = 0
2150 10:01:52.388483 Vddq = 0
2151 10:01:52.391436 Vmddr = 0
2152 10:01:52.395167 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2153 10:01:52.401291 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2154 10:01:52.401374 MEM_TYPE=3, freq_sel=15
2155 10:01:52.404866 sv_algorithm_assistance_LP4_1600
2156 10:01:52.411498 ============ PULL DRAM RESETB DOWN ============
2157 10:01:52.414404 ========== PULL DRAM RESETB DOWN end =========
2158 10:01:52.417965 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2159 10:01:52.421207 ===================================
2160 10:01:52.424615 LPDDR4 DRAM CONFIGURATION
2161 10:01:52.428070 ===================================
2162 10:01:52.428153 EX_ROW_EN[0] = 0x0
2163 10:01:52.431514 EX_ROW_EN[1] = 0x0
2164 10:01:52.434620 LP4Y_EN = 0x0
2165 10:01:52.434703 WORK_FSP = 0x0
2166 10:01:52.437860 WL = 0x4
2167 10:01:52.437944 RL = 0x4
2168 10:01:52.441204 BL = 0x2
2169 10:01:52.441288 RPST = 0x0
2170 10:01:52.444727 RD_PRE = 0x0
2171 10:01:52.444811 WR_PRE = 0x1
2172 10:01:52.447684 WR_PST = 0x0
2173 10:01:52.447768 DBI_WR = 0x0
2174 10:01:52.451198 DBI_RD = 0x0
2175 10:01:52.451281 OTF = 0x1
2176 10:01:52.454608 ===================================
2177 10:01:52.457737 ===================================
2178 10:01:52.461279 ANA top config
2179 10:01:52.464755 ===================================
2180 10:01:52.464838 DLL_ASYNC_EN = 0
2181 10:01:52.467770 ALL_SLAVE_EN = 0
2182 10:01:52.471155 NEW_RANK_MODE = 1
2183 10:01:52.474497 DLL_IDLE_MODE = 1
2184 10:01:52.477714 LP45_APHY_COMB_EN = 1
2185 10:01:52.477797 TX_ODT_DIS = 1
2186 10:01:52.481293 NEW_8X_MODE = 1
2187 10:01:52.484462 ===================================
2188 10:01:52.488432 ===================================
2189 10:01:52.491308 data_rate = 2400
2190 10:01:52.494858 CKR = 1
2191 10:01:52.498184 DQ_P2S_RATIO = 8
2192 10:01:52.501571 ===================================
2193 10:01:52.501656 CA_P2S_RATIO = 8
2194 10:01:52.504693 DQ_CA_OPEN = 0
2195 10:01:52.508083 DQ_SEMI_OPEN = 0
2196 10:01:52.511376 CA_SEMI_OPEN = 0
2197 10:01:52.514920 CA_FULL_RATE = 0
2198 10:01:52.518117 DQ_CKDIV4_EN = 0
2199 10:01:52.518204 CA_CKDIV4_EN = 0
2200 10:01:52.521562 CA_PREDIV_EN = 0
2201 10:01:52.524910 PH8_DLY = 17
2202 10:01:52.528132 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2203 10:01:52.531272 DQ_AAMCK_DIV = 4
2204 10:01:52.535087 CA_AAMCK_DIV = 4
2205 10:01:52.535174 CA_ADMCK_DIV = 4
2206 10:01:52.537741 DQ_TRACK_CA_EN = 0
2207 10:01:52.540906 CA_PICK = 1200
2208 10:01:52.544596 CA_MCKIO = 1200
2209 10:01:52.547820 MCKIO_SEMI = 0
2210 10:01:52.551051 PLL_FREQ = 2366
2211 10:01:52.554593 DQ_UI_PI_RATIO = 32
2212 10:01:52.554680 CA_UI_PI_RATIO = 0
2213 10:01:52.558000 ===================================
2214 10:01:52.561135 ===================================
2215 10:01:52.564864 memory_type:LPDDR4
2216 10:01:52.567930 GP_NUM : 10
2217 10:01:52.568016 SRAM_EN : 1
2218 10:01:52.571319 MD32_EN : 0
2219 10:01:52.574576 ===================================
2220 10:01:52.577591 [ANA_INIT] >>>>>>>>>>>>>>
2221 10:01:52.580969 <<<<<< [CONFIGURE PHASE]: ANA_TX
2222 10:01:52.584257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2223 10:01:52.588137 ===================================
2224 10:01:52.588224 data_rate = 2400,PCW = 0X5b00
2225 10:01:52.591201 ===================================
2226 10:01:52.594637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2227 10:01:52.600872 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2228 10:01:52.607529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2229 10:01:52.610721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2230 10:01:52.614121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2231 10:01:52.617476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2232 10:01:52.620875 [ANA_INIT] flow start
2233 10:01:52.624074 [ANA_INIT] PLL >>>>>>>>
2234 10:01:52.624161 [ANA_INIT] PLL <<<<<<<<
2235 10:01:52.628044 [ANA_INIT] MIDPI >>>>>>>>
2236 10:01:52.630892 [ANA_INIT] MIDPI <<<<<<<<
2237 10:01:52.630979 [ANA_INIT] DLL >>>>>>>>
2238 10:01:52.634711 [ANA_INIT] DLL <<<<<<<<
2239 10:01:52.637683 [ANA_INIT] flow end
2240 10:01:52.640822 ============ LP4 DIFF to SE enter ============
2241 10:01:52.643957 ============ LP4 DIFF to SE exit ============
2242 10:01:52.647711 [ANA_INIT] <<<<<<<<<<<<<
2243 10:01:52.651133 [Flow] Enable top DCM control >>>>>
2244 10:01:52.654227 [Flow] Enable top DCM control <<<<<
2245 10:01:52.657532 Enable DLL master slave shuffle
2246 10:01:52.661007 ==============================================================
2247 10:01:52.664185 Gating Mode config
2248 10:01:52.667687 ==============================================================
2249 10:01:52.670609 Config description:
2250 10:01:52.680392 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2251 10:01:52.687140 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2252 10:01:52.690746 SELPH_MODE 0: By rank 1: By Phase
2253 10:01:52.697336 ==============================================================
2254 10:01:52.700711 GAT_TRACK_EN = 1
2255 10:01:52.704238 RX_GATING_MODE = 2
2256 10:01:52.707299 RX_GATING_TRACK_MODE = 2
2257 10:01:52.710658 SELPH_MODE = 1
2258 10:01:52.713675 PICG_EARLY_EN = 1
2259 10:01:52.717162 VALID_LAT_VALUE = 1
2260 10:01:52.720309 ==============================================================
2261 10:01:52.723827 Enter into Gating configuration >>>>
2262 10:01:52.727211 Exit from Gating configuration <<<<
2263 10:01:52.730388 Enter into DVFS_PRE_config >>>>>
2264 10:01:52.740336 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2265 10:01:52.743723 Exit from DVFS_PRE_config <<<<<
2266 10:01:52.746879 Enter into PICG configuration >>>>
2267 10:01:52.750199 Exit from PICG configuration <<<<
2268 10:01:52.753953 [RX_INPUT] configuration >>>>>
2269 10:01:52.757113 [RX_INPUT] configuration <<<<<
2270 10:01:52.763811 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2271 10:01:52.766730 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2272 10:01:52.773774 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2273 10:01:52.779959 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2274 10:01:52.786895 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2275 10:01:52.793441 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2276 10:01:52.797416 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2277 10:01:52.800189 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2278 10:01:52.803186 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2279 10:01:52.810093 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2280 10:01:52.813708 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2281 10:01:52.816866 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2282 10:01:52.819684 ===================================
2283 10:01:52.823277 LPDDR4 DRAM CONFIGURATION
2284 10:01:52.826697 ===================================
2285 10:01:52.826781 EX_ROW_EN[0] = 0x0
2286 10:01:52.830187 EX_ROW_EN[1] = 0x0
2287 10:01:52.833053 LP4Y_EN = 0x0
2288 10:01:52.833137 WORK_FSP = 0x0
2289 10:01:52.837045 WL = 0x4
2290 10:01:52.837129 RL = 0x4
2291 10:01:52.839704 BL = 0x2
2292 10:01:52.839787 RPST = 0x0
2293 10:01:52.843654 RD_PRE = 0x0
2294 10:01:52.843737 WR_PRE = 0x1
2295 10:01:52.846689 WR_PST = 0x0
2296 10:01:52.846772 DBI_WR = 0x0
2297 10:01:52.849971 DBI_RD = 0x0
2298 10:01:52.850054 OTF = 0x1
2299 10:01:52.853349 ===================================
2300 10:01:52.856260 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2301 10:01:52.863266 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2302 10:01:52.866551 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2303 10:01:52.869500 ===================================
2304 10:01:52.872778 LPDDR4 DRAM CONFIGURATION
2305 10:01:52.876191 ===================================
2306 10:01:52.876275 EX_ROW_EN[0] = 0x10
2307 10:01:52.879367 EX_ROW_EN[1] = 0x0
2308 10:01:52.883172 LP4Y_EN = 0x0
2309 10:01:52.883252 WORK_FSP = 0x0
2310 10:01:52.886225 WL = 0x4
2311 10:01:52.886308 RL = 0x4
2312 10:01:52.889544 BL = 0x2
2313 10:01:52.889625 RPST = 0x0
2314 10:01:52.893251 RD_PRE = 0x0
2315 10:01:52.893332 WR_PRE = 0x1
2316 10:01:52.896080 WR_PST = 0x0
2317 10:01:52.896161 DBI_WR = 0x0
2318 10:01:52.900031 DBI_RD = 0x0
2319 10:01:52.900112 OTF = 0x1
2320 10:01:52.902820 ===================================
2321 10:01:52.909818 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2322 10:01:52.909901 ==
2323 10:01:52.912990 Dram Type= 6, Freq= 0, CH_0, rank 0
2324 10:01:52.916219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2325 10:01:52.916298 ==
2326 10:01:52.919536 [Duty_Offset_Calibration]
2327 10:01:52.922926 B0:2 B1:-1 CA:1
2328 10:01:52.922997
2329 10:01:52.926023 [DutyScan_Calibration_Flow] k_type=0
2330 10:01:52.933886
2331 10:01:52.933969 ==CLK 0==
2332 10:01:52.937100 Final CLK duty delay cell = -4
2333 10:01:52.940518 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2334 10:01:52.943818 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2335 10:01:52.946991 [-4] AVG Duty = 4953%(X100)
2336 10:01:52.947071
2337 10:01:52.950708 CH0 CLK Duty spec in!! Max-Min= 156%
2338 10:01:52.953419 [DutyScan_Calibration_Flow] ====Done====
2339 10:01:52.953499
2340 10:01:52.956857 [DutyScan_Calibration_Flow] k_type=1
2341 10:01:52.972280
2342 10:01:52.972361 ==DQS 0 ==
2343 10:01:52.975713 Final DQS duty delay cell = 0
2344 10:01:52.979214 [0] MAX Duty = 5125%(X100), DQS PI = 48
2345 10:01:52.982384 [0] MIN Duty = 4969%(X100), DQS PI = 14
2346 10:01:52.985780 [0] AVG Duty = 5047%(X100)
2347 10:01:52.985861
2348 10:01:52.985924 ==DQS 1 ==
2349 10:01:52.989118 Final DQS duty delay cell = -4
2350 10:01:52.992266 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2351 10:01:52.995949 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2352 10:01:52.999542 [-4] AVG Duty = 5062%(X100)
2353 10:01:52.999636
2354 10:01:53.002449 CH0 DQS 0 Duty spec in!! Max-Min= 156%
2355 10:01:53.002539
2356 10:01:53.005990 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2357 10:01:53.009413 [DutyScan_Calibration_Flow] ====Done====
2358 10:01:53.009493
2359 10:01:53.012131 [DutyScan_Calibration_Flow] k_type=3
2360 10:01:53.029717
2361 10:01:53.029797 ==DQM 0 ==
2362 10:01:53.032578 Final DQM duty delay cell = 0
2363 10:01:53.035900 [0] MAX Duty = 5000%(X100), DQS PI = 54
2364 10:01:53.038888 [0] MIN Duty = 4907%(X100), DQS PI = 2
2365 10:01:53.042362 [0] AVG Duty = 4953%(X100)
2366 10:01:53.042442
2367 10:01:53.042506 ==DQM 1 ==
2368 10:01:53.045741 Final DQM duty delay cell = 0
2369 10:01:53.048829 [0] MAX Duty = 5124%(X100), DQS PI = 32
2370 10:01:53.051971 [0] MIN Duty = 4969%(X100), DQS PI = 10
2371 10:01:53.055971 [0] AVG Duty = 5046%(X100)
2372 10:01:53.056052
2373 10:01:53.059422 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2374 10:01:53.059503
2375 10:01:53.062486 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2376 10:01:53.065537 [DutyScan_Calibration_Flow] ====Done====
2377 10:01:53.065618
2378 10:01:53.068750 [DutyScan_Calibration_Flow] k_type=2
2379 10:01:53.084656
2380 10:01:53.084737 ==DQ 0 ==
2381 10:01:53.088185 Final DQ duty delay cell = -4
2382 10:01:53.091303 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2383 10:01:53.094714 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2384 10:01:53.098365 [-4] AVG Duty = 4984%(X100)
2385 10:01:53.098445
2386 10:01:53.098509 ==DQ 1 ==
2387 10:01:53.101417 Final DQ duty delay cell = 0
2388 10:01:53.104554 [0] MAX Duty = 5031%(X100), DQS PI = 26
2389 10:01:53.107833 [0] MIN Duty = 4907%(X100), DQS PI = 46
2390 10:01:53.111497 [0] AVG Duty = 4969%(X100)
2391 10:01:53.111578
2392 10:01:53.114710 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2393 10:01:53.114792
2394 10:01:53.118076 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2395 10:01:53.121390 [DutyScan_Calibration_Flow] ====Done====
2396 10:01:53.121463 ==
2397 10:01:53.124449 Dram Type= 6, Freq= 0, CH_1, rank 0
2398 10:01:53.127716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2399 10:01:53.127798 ==
2400 10:01:53.131401 [Duty_Offset_Calibration]
2401 10:01:53.131494 B0:1 B1:1 CA:2
2402 10:01:53.131559
2403 10:01:53.134809 [DutyScan_Calibration_Flow] k_type=0
2404 10:01:53.145035
2405 10:01:53.145119 ==CLK 0==
2406 10:01:53.148336 Final CLK duty delay cell = 0
2407 10:01:53.151805 [0] MAX Duty = 5094%(X100), DQS PI = 56
2408 10:01:53.155048 [0] MIN Duty = 4938%(X100), DQS PI = 8
2409 10:01:53.155130 [0] AVG Duty = 5016%(X100)
2410 10:01:53.158593
2411 10:01:53.158675 CH1 CLK Duty spec in!! Max-Min= 156%
2412 10:01:53.164886 [DutyScan_Calibration_Flow] ====Done====
2413 10:01:53.164970
2414 10:01:53.168258 [DutyScan_Calibration_Flow] k_type=1
2415 10:01:53.184207
2416 10:01:53.184318 ==DQS 0 ==
2417 10:01:53.187823 Final DQS duty delay cell = 0
2418 10:01:53.191162 [0] MAX Duty = 5031%(X100), DQS PI = 50
2419 10:01:53.194230 [0] MIN Duty = 4875%(X100), DQS PI = 46
2420 10:01:53.197390 [0] AVG Duty = 4953%(X100)
2421 10:01:53.197473
2422 10:01:53.197539 ==DQS 1 ==
2423 10:01:53.200907 Final DQS duty delay cell = 0
2424 10:01:53.204084 [0] MAX Duty = 5062%(X100), DQS PI = 26
2425 10:01:53.207569 [0] MIN Duty = 4907%(X100), DQS PI = 0
2426 10:01:53.211056 [0] AVG Duty = 4984%(X100)
2427 10:01:53.211138
2428 10:01:53.213980 CH1 DQS 0 Duty spec in!! Max-Min= 156%
2429 10:01:53.214064
2430 10:01:53.217465 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2431 10:01:53.220894 [DutyScan_Calibration_Flow] ====Done====
2432 10:01:53.220977
2433 10:01:53.224438 [DutyScan_Calibration_Flow] k_type=3
2434 10:01:53.240622
2435 10:01:53.240708 ==DQM 0 ==
2436 10:01:53.244020 Final DQM duty delay cell = 0
2437 10:01:53.247297 [0] MAX Duty = 5093%(X100), DQS PI = 6
2438 10:01:53.250866 [0] MIN Duty = 4907%(X100), DQS PI = 16
2439 10:01:53.250950 [0] AVG Duty = 5000%(X100)
2440 10:01:53.254166
2441 10:01:53.254248 ==DQM 1 ==
2442 10:01:53.257730 Final DQM duty delay cell = 0
2443 10:01:53.260999 [0] MAX Duty = 5156%(X100), DQS PI = 30
2444 10:01:53.264252 [0] MIN Duty = 4938%(X100), DQS PI = 56
2445 10:01:53.264354 [0] AVG Duty = 5047%(X100)
2446 10:01:53.267642
2447 10:01:53.271073 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2448 10:01:53.271156
2449 10:01:53.274062 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2450 10:01:53.277293 [DutyScan_Calibration_Flow] ====Done====
2451 10:01:53.277380
2452 10:01:53.280744 [DutyScan_Calibration_Flow] k_type=2
2453 10:01:53.297865
2454 10:01:53.297952 ==DQ 0 ==
2455 10:01:53.300457 Final DQ duty delay cell = 0
2456 10:01:53.303833 [0] MAX Duty = 5093%(X100), DQS PI = 50
2457 10:01:53.307400 [0] MIN Duty = 4969%(X100), DQS PI = 16
2458 10:01:53.307487 [0] AVG Duty = 5031%(X100)
2459 10:01:53.310664
2460 10:01:53.310766 ==DQ 1 ==
2461 10:01:53.314241 Final DQ duty delay cell = 0
2462 10:01:53.317076 [0] MAX Duty = 5124%(X100), DQS PI = 26
2463 10:01:53.320514 [0] MIN Duty = 5031%(X100), DQS PI = 2
2464 10:01:53.320601 [0] AVG Duty = 5077%(X100)
2465 10:01:53.320669
2466 10:01:53.323907 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2467 10:01:53.327361
2468 10:01:53.330481 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2469 10:01:53.333743 [DutyScan_Calibration_Flow] ====Done====
2470 10:01:53.337165 nWR fixed to 30
2471 10:01:53.337250 [ModeRegInit_LP4] CH0 RK0
2472 10:01:53.340700 [ModeRegInit_LP4] CH0 RK1
2473 10:01:53.343815 [ModeRegInit_LP4] CH1 RK0
2474 10:01:53.343898 [ModeRegInit_LP4] CH1 RK1
2475 10:01:53.347260 match AC timing 7
2476 10:01:53.350761 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2477 10:01:53.354308 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2478 10:01:53.360596 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2479 10:01:53.363581 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2480 10:01:53.370663 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2481 10:01:53.370764 ==
2482 10:01:53.373522 Dram Type= 6, Freq= 0, CH_0, rank 0
2483 10:01:53.376988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2484 10:01:53.377070 ==
2485 10:01:53.383757 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2486 10:01:53.390041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2487 10:01:53.396957 [CA 0] Center 40 (10~71) winsize 62
2488 10:01:53.401062 [CA 1] Center 39 (9~70) winsize 62
2489 10:01:53.403874 [CA 2] Center 36 (6~67) winsize 62
2490 10:01:53.406838 [CA 3] Center 35 (5~66) winsize 62
2491 10:01:53.410513 [CA 4] Center 34 (4~65) winsize 62
2492 10:01:53.413846 [CA 5] Center 34 (4~64) winsize 61
2493 10:01:53.413932
2494 10:01:53.417241 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2495 10:01:53.417325
2496 10:01:53.420805 [CATrainingPosCal] consider 1 rank data
2497 10:01:53.424317 u2DelayCellTimex100 = 270/100 ps
2498 10:01:53.427284 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2499 10:01:53.433651 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2500 10:01:53.437261 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2501 10:01:53.440636 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2502 10:01:53.443496 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2503 10:01:53.446883 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2504 10:01:53.446967
2505 10:01:53.450624 CA PerBit enable=1, Macro0, CA PI delay=34
2506 10:01:53.450707
2507 10:01:53.453801 [CBTSetCACLKResult] CA Dly = 34
2508 10:01:53.453885 CS Dly: 7 (0~38)
2509 10:01:53.457360 ==
2510 10:01:53.457444 Dram Type= 6, Freq= 0, CH_0, rank 1
2511 10:01:53.464515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 10:01:53.464600 ==
2513 10:01:53.467306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2514 10:01:53.473981 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2515 10:01:53.482986 [CA 0] Center 39 (9~70) winsize 62
2516 10:01:53.486196 [CA 1] Center 39 (9~70) winsize 62
2517 10:01:53.489968 [CA 2] Center 36 (6~67) winsize 62
2518 10:01:53.493415 [CA 3] Center 35 (5~66) winsize 62
2519 10:01:53.496592 [CA 4] Center 34 (4~65) winsize 62
2520 10:01:53.499866 [CA 5] Center 34 (4~64) winsize 61
2521 10:01:53.499960
2522 10:01:53.503249 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2523 10:01:53.503402
2524 10:01:53.506263 [CATrainingPosCal] consider 2 rank data
2525 10:01:53.509983 u2DelayCellTimex100 = 270/100 ps
2526 10:01:53.513228 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2527 10:01:53.516524 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2528 10:01:53.522865 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2529 10:01:53.526677 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2530 10:01:53.529780 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2531 10:01:53.532826 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2532 10:01:53.532912
2533 10:01:53.536865 CA PerBit enable=1, Macro0, CA PI delay=34
2534 10:01:53.536949
2535 10:01:53.539714 [CBTSetCACLKResult] CA Dly = 34
2536 10:01:53.539799 CS Dly: 8 (0~41)
2537 10:01:53.539867
2538 10:01:53.543025 ----->DramcWriteLeveling(PI) begin...
2539 10:01:53.546519 ==
2540 10:01:53.549624 Dram Type= 6, Freq= 0, CH_0, rank 0
2541 10:01:53.552998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 10:01:53.553083 ==
2543 10:01:53.556346 Write leveling (Byte 0): 33 => 33
2544 10:01:53.559807 Write leveling (Byte 1): 28 => 28
2545 10:01:53.562816 DramcWriteLeveling(PI) end<-----
2546 10:01:53.562900
2547 10:01:53.562966 ==
2548 10:01:53.566183 Dram Type= 6, Freq= 0, CH_0, rank 0
2549 10:01:53.569517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 10:01:53.569602 ==
2551 10:01:53.572885 [Gating] SW mode calibration
2552 10:01:53.579693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2553 10:01:53.586137 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2554 10:01:53.589335 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 10:01:53.592813 0 15 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
2556 10:01:53.599184 0 15 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2557 10:01:53.602809 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2558 10:01:53.606094 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2559 10:01:53.609871 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2560 10:01:53.615934 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2561 10:01:53.619662 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2562 10:01:53.623113 1 0 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
2563 10:01:53.629385 1 0 4 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
2564 10:01:53.632992 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 10:01:53.635812 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2566 10:01:53.643117 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2567 10:01:53.646367 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2568 10:01:53.649295 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2569 10:01:53.655788 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 10:01:53.659050 1 1 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2571 10:01:53.662553 1 1 4 | B1->B0 | 3a3a 4242 | 1 0 | (0 0) (0 0)
2572 10:01:53.669366 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 10:01:53.672629 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 10:01:53.675756 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 10:01:53.682814 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 10:01:53.686029 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 10:01:53.689305 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 10:01:53.695730 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2579 10:01:53.699155 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2580 10:01:53.702386 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 10:01:53.709288 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 10:01:53.713169 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 10:01:53.716079 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 10:01:53.722161 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 10:01:53.725794 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 10:01:53.728953 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 10:01:53.736057 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 10:01:53.739215 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 10:01:53.742622 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 10:01:53.745536 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 10:01:53.752483 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 10:01:53.755340 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 10:01:53.759224 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 10:01:53.765794 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2595 10:01:53.768780 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2596 10:01:53.772396 Total UI for P1: 0, mck2ui 16
2597 10:01:53.775274 best dqsien dly found for B0: ( 1, 4, 0)
2598 10:01:53.778811 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 10:01:53.782016 Total UI for P1: 0, mck2ui 16
2600 10:01:53.785466 best dqsien dly found for B1: ( 1, 4, 2)
2601 10:01:53.789182 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2602 10:01:53.792667 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2603 10:01:53.792753
2604 10:01:53.798774 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2605 10:01:53.802345 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2606 10:01:53.802430 [Gating] SW calibration Done
2607 10:01:53.805880 ==
2608 10:01:53.805987 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 10:01:53.812605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 10:01:53.812719 ==
2611 10:01:53.812831 RX Vref Scan: 0
2612 10:01:53.812925
2613 10:01:53.815518 RX Vref 0 -> 0, step: 1
2614 10:01:53.815602
2615 10:01:53.818753 RX Delay -40 -> 252, step: 8
2616 10:01:53.822779 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2617 10:01:53.825665 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2618 10:01:53.828930 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2619 10:01:53.835671 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2620 10:01:53.838918 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2621 10:01:53.842197 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2622 10:01:53.845941 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2623 10:01:53.848786 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2624 10:01:53.852239 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2625 10:01:53.859094 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2626 10:01:53.862996 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2627 10:01:53.865785 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2628 10:01:53.869113 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2629 10:01:53.872691 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2630 10:01:53.878957 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2631 10:01:53.882448 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2632 10:01:53.882533 ==
2633 10:01:53.885751 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 10:01:53.889603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 10:01:53.889687 ==
2636 10:01:53.892348 DQS Delay:
2637 10:01:53.892432 DQS0 = 0, DQS1 = 0
2638 10:01:53.892499 DQM Delay:
2639 10:01:53.896062 DQM0 = 115, DQM1 = 107
2640 10:01:53.896146 DQ Delay:
2641 10:01:53.899302 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2642 10:01:53.902559 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2643 10:01:53.905933 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2644 10:01:53.912691 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2645 10:01:53.912801
2646 10:01:53.912928
2647 10:01:53.913018 ==
2648 10:01:53.915758 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 10:01:53.918982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 10:01:53.919067 ==
2651 10:01:53.919134
2652 10:01:53.919195
2653 10:01:53.922424 TX Vref Scan disable
2654 10:01:53.922509 == TX Byte 0 ==
2655 10:01:53.929041 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2656 10:01:53.932373 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2657 10:01:53.932458 == TX Byte 1 ==
2658 10:01:53.939016 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2659 10:01:53.942662 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2660 10:01:53.942747 ==
2661 10:01:53.945723 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 10:01:53.949217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 10:01:53.949303 ==
2664 10:01:53.962061 TX Vref=22, minBit 1, minWin=24, winSum=417
2665 10:01:53.965436 TX Vref=24, minBit 1, minWin=25, winSum=421
2666 10:01:53.968729 TX Vref=26, minBit 0, minWin=26, winSum=427
2667 10:01:53.971896 TX Vref=28, minBit 0, minWin=26, winSum=433
2668 10:01:53.975466 TX Vref=30, minBit 1, minWin=26, winSum=434
2669 10:01:53.982292 TX Vref=32, minBit 0, minWin=26, winSum=431
2670 10:01:53.985609 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 30
2671 10:01:53.985694
2672 10:01:53.989018 Final TX Range 1 Vref 30
2673 10:01:53.989104
2674 10:01:53.989171 ==
2675 10:01:53.991949 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 10:01:53.996030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 10:01:53.996114 ==
2678 10:01:53.996181
2679 10:01:53.998636
2680 10:01:53.998719 TX Vref Scan disable
2681 10:01:54.001816 == TX Byte 0 ==
2682 10:01:54.005774 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2683 10:01:54.008573 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2684 10:01:54.012055 == TX Byte 1 ==
2685 10:01:54.015502 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2686 10:01:54.018877 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2687 10:01:54.022095
2688 10:01:54.022182 [DATLAT]
2689 10:01:54.022250 Freq=1200, CH0 RK0
2690 10:01:54.022313
2691 10:01:54.025650 DATLAT Default: 0xd
2692 10:01:54.025733 0, 0xFFFF, sum = 0
2693 10:01:54.028822 1, 0xFFFF, sum = 0
2694 10:01:54.028908 2, 0xFFFF, sum = 0
2695 10:01:54.032091 3, 0xFFFF, sum = 0
2696 10:01:54.032177 4, 0xFFFF, sum = 0
2697 10:01:54.035507 5, 0xFFFF, sum = 0
2698 10:01:54.038950 6, 0xFFFF, sum = 0
2699 10:01:54.039036 7, 0xFFFF, sum = 0
2700 10:01:54.042159 8, 0xFFFF, sum = 0
2701 10:01:54.042245 9, 0xFFFF, sum = 0
2702 10:01:54.045369 10, 0xFFFF, sum = 0
2703 10:01:54.045454 11, 0xFFFF, sum = 0
2704 10:01:54.048831 12, 0x0, sum = 1
2705 10:01:54.048916 13, 0x0, sum = 2
2706 10:01:54.052146 14, 0x0, sum = 3
2707 10:01:54.052299 15, 0x0, sum = 4
2708 10:01:54.052368 best_step = 13
2709 10:01:54.052430
2710 10:01:54.055468 ==
2711 10:01:54.058440 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 10:01:54.061587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 10:01:54.061673 ==
2714 10:01:54.061740 RX Vref Scan: 1
2715 10:01:54.061803
2716 10:01:54.065099 Set Vref Range= 32 -> 127
2717 10:01:54.065182
2718 10:01:54.068726 RX Vref 32 -> 127, step: 1
2719 10:01:54.068811
2720 10:01:54.071873 RX Delay -21 -> 252, step: 4
2721 10:01:54.071957
2722 10:01:54.075023 Set Vref, RX VrefLevel [Byte0]: 32
2723 10:01:54.078323 [Byte1]: 32
2724 10:01:54.078407
2725 10:01:54.082185 Set Vref, RX VrefLevel [Byte0]: 33
2726 10:01:54.085047 [Byte1]: 33
2727 10:01:54.085131
2728 10:01:54.088608 Set Vref, RX VrefLevel [Byte0]: 34
2729 10:01:54.091866 [Byte1]: 34
2730 10:01:54.096286
2731 10:01:54.096370 Set Vref, RX VrefLevel [Byte0]: 35
2732 10:01:54.099689 [Byte1]: 35
2733 10:01:54.104425
2734 10:01:54.104532 Set Vref, RX VrefLevel [Byte0]: 36
2735 10:01:54.107835 [Byte1]: 36
2736 10:01:54.112354
2737 10:01:54.112438 Set Vref, RX VrefLevel [Byte0]: 37
2738 10:01:54.115438 [Byte1]: 37
2739 10:01:54.120204
2740 10:01:54.120291 Set Vref, RX VrefLevel [Byte0]: 38
2741 10:01:54.123462 [Byte1]: 38
2742 10:01:54.127745
2743 10:01:54.127832 Set Vref, RX VrefLevel [Byte0]: 39
2744 10:01:54.131210 [Byte1]: 39
2745 10:01:54.136102
2746 10:01:54.136186 Set Vref, RX VrefLevel [Byte0]: 40
2747 10:01:54.138934 [Byte1]: 40
2748 10:01:54.143820
2749 10:01:54.143903 Set Vref, RX VrefLevel [Byte0]: 41
2750 10:01:54.147044 [Byte1]: 41
2751 10:01:54.151802
2752 10:01:54.151885 Set Vref, RX VrefLevel [Byte0]: 42
2753 10:01:54.155302 [Byte1]: 42
2754 10:01:54.160426
2755 10:01:54.160510 Set Vref, RX VrefLevel [Byte0]: 43
2756 10:01:54.163272 [Byte1]: 43
2757 10:01:54.167701
2758 10:01:54.167785 Set Vref, RX VrefLevel [Byte0]: 44
2759 10:01:54.170646 [Byte1]: 44
2760 10:01:54.175269
2761 10:01:54.175412 Set Vref, RX VrefLevel [Byte0]: 45
2762 10:01:54.178560 [Byte1]: 45
2763 10:01:54.183688
2764 10:01:54.183798 Set Vref, RX VrefLevel [Byte0]: 46
2765 10:01:54.186571 [Byte1]: 46
2766 10:01:54.191215
2767 10:01:54.191320 Set Vref, RX VrefLevel [Byte0]: 47
2768 10:01:54.194850 [Byte1]: 47
2769 10:01:54.199280
2770 10:01:54.199413 Set Vref, RX VrefLevel [Byte0]: 48
2771 10:01:54.202811 [Byte1]: 48
2772 10:01:54.207489
2773 10:01:54.207572 Set Vref, RX VrefLevel [Byte0]: 49
2774 10:01:54.210557 [Byte1]: 49
2775 10:01:54.215075
2776 10:01:54.215155 Set Vref, RX VrefLevel [Byte0]: 50
2777 10:01:54.218497 [Byte1]: 50
2778 10:01:54.223044
2779 10:01:54.223123 Set Vref, RX VrefLevel [Byte0]: 51
2780 10:01:54.226432 [Byte1]: 51
2781 10:01:54.231001
2782 10:01:54.231107 Set Vref, RX VrefLevel [Byte0]: 52
2783 10:01:54.234591 [Byte1]: 52
2784 10:01:54.239009
2785 10:01:54.239123 Set Vref, RX VrefLevel [Byte0]: 53
2786 10:01:54.242231 [Byte1]: 53
2787 10:01:54.246646
2788 10:01:54.246727 Set Vref, RX VrefLevel [Byte0]: 54
2789 10:01:54.250075 [Byte1]: 54
2790 10:01:54.254680
2791 10:01:54.254762 Set Vref, RX VrefLevel [Byte0]: 55
2792 10:01:54.258271 [Byte1]: 55
2793 10:01:54.262893
2794 10:01:54.262972 Set Vref, RX VrefLevel [Byte0]: 56
2795 10:01:54.266582 [Byte1]: 56
2796 10:01:54.270504
2797 10:01:54.270581 Set Vref, RX VrefLevel [Byte0]: 57
2798 10:01:54.273699 [Byte1]: 57
2799 10:01:54.278698
2800 10:01:54.278802 Set Vref, RX VrefLevel [Byte0]: 58
2801 10:01:54.281953 [Byte1]: 58
2802 10:01:54.286444
2803 10:01:54.286522 Set Vref, RX VrefLevel [Byte0]: 59
2804 10:01:54.289977 [Byte1]: 59
2805 10:01:54.294857
2806 10:01:54.294935 Set Vref, RX VrefLevel [Byte0]: 60
2807 10:01:54.297940 [Byte1]: 60
2808 10:01:54.302237
2809 10:01:54.302339 Set Vref, RX VrefLevel [Byte0]: 61
2810 10:01:54.305626 [Byte1]: 61
2811 10:01:54.310236
2812 10:01:54.310337 Set Vref, RX VrefLevel [Byte0]: 62
2813 10:01:54.313874 [Byte1]: 62
2814 10:01:54.317900
2815 10:01:54.318005 Set Vref, RX VrefLevel [Byte0]: 63
2816 10:01:54.321789 [Byte1]: 63
2817 10:01:54.326037
2818 10:01:54.326116 Set Vref, RX VrefLevel [Byte0]: 64
2819 10:01:54.329594 [Byte1]: 64
2820 10:01:54.334125
2821 10:01:54.334234 Set Vref, RX VrefLevel [Byte0]: 65
2822 10:01:54.337599 [Byte1]: 65
2823 10:01:54.341892
2824 10:01:54.341966 Set Vref, RX VrefLevel [Byte0]: 66
2825 10:01:54.345121 [Byte1]: 66
2826 10:01:54.350256
2827 10:01:54.350358 Set Vref, RX VrefLevel [Byte0]: 67
2828 10:01:54.353112 [Byte1]: 67
2829 10:01:54.357691
2830 10:01:54.357774 Set Vref, RX VrefLevel [Byte0]: 68
2831 10:01:54.361343 [Byte1]: 68
2832 10:01:54.365851
2833 10:01:54.365953 Final RX Vref Byte 0 = 52 to rank0
2834 10:01:54.368889 Final RX Vref Byte 1 = 50 to rank0
2835 10:01:54.372261 Final RX Vref Byte 0 = 52 to rank1
2836 10:01:54.375559 Final RX Vref Byte 1 = 50 to rank1==
2837 10:01:54.379549 Dram Type= 6, Freq= 0, CH_0, rank 0
2838 10:01:54.385746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2839 10:01:54.385830 ==
2840 10:01:54.385897 DQS Delay:
2841 10:01:54.385959 DQS0 = 0, DQS1 = 0
2842 10:01:54.389428 DQM Delay:
2843 10:01:54.389511 DQM0 = 115, DQM1 = 104
2844 10:01:54.392619 DQ Delay:
2845 10:01:54.395830 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2846 10:01:54.399069 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2847 10:01:54.402935 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2848 10:01:54.405684 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2849 10:01:54.405767
2850 10:01:54.405832
2851 10:01:54.412296 [DQSOSCAuto] RK0, (LSB)MR18= 0xfded, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 411 ps
2852 10:01:54.415637 CH0 RK0: MR19=303, MR18=FDED
2853 10:01:54.422626 CH0_RK0: MR19=0x303, MR18=0xFDED, DQSOSC=411, MR23=63, INC=38, DEC=25
2854 10:01:54.422710
2855 10:01:54.426010 ----->DramcWriteLeveling(PI) begin...
2856 10:01:54.426094 ==
2857 10:01:54.428668 Dram Type= 6, Freq= 0, CH_0, rank 1
2858 10:01:54.432385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2859 10:01:54.435791 ==
2860 10:01:54.435875 Write leveling (Byte 0): 31 => 31
2861 10:01:54.439187 Write leveling (Byte 1): 28 => 28
2862 10:01:54.442325 DramcWriteLeveling(PI) end<-----
2863 10:01:54.442408
2864 10:01:54.442474 ==
2865 10:01:54.445745 Dram Type= 6, Freq= 0, CH_0, rank 1
2866 10:01:54.452452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2867 10:01:54.452536 ==
2868 10:01:54.452602 [Gating] SW mode calibration
2869 10:01:54.462726 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2870 10:01:54.465966 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2871 10:01:54.469104 0 15 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2872 10:01:54.475921 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2873 10:01:54.479027 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2874 10:01:54.482485 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2875 10:01:54.488932 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2876 10:01:54.492406 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2877 10:01:54.495914 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2878 10:01:54.502741 0 15 28 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
2879 10:01:54.505836 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2880 10:01:54.508796 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2881 10:01:54.515863 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2882 10:01:54.519249 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2883 10:01:54.522926 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2884 10:01:54.529496 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2885 10:01:54.532717 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2886 10:01:54.535670 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2887 10:01:54.542320 1 1 0 | B1->B0 | 3030 3d3d | 1 0 | (0 0) (0 0)
2888 10:01:54.546124 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 10:01:54.549098 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 10:01:54.552282 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 10:01:54.559226 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 10:01:54.562539 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 10:01:54.565511 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 10:01:54.572222 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2895 10:01:54.575846 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2896 10:01:54.579061 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2897 10:01:54.585518 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 10:01:54.588706 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 10:01:54.592161 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 10:01:54.599002 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 10:01:54.602331 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 10:01:54.605918 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 10:01:54.612375 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 10:01:54.615337 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 10:01:54.619193 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 10:01:54.625605 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 10:01:54.628803 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 10:01:54.632123 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 10:01:54.638820 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 10:01:54.642271 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2911 10:01:54.645741 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2912 10:01:54.648896 Total UI for P1: 0, mck2ui 16
2913 10:01:54.652510 best dqsien dly found for B0: ( 1, 3, 28)
2914 10:01:54.655588 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2915 10:01:54.662449 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 10:01:54.665779 Total UI for P1: 0, mck2ui 16
2917 10:01:54.669165 best dqsien dly found for B1: ( 1, 4, 0)
2918 10:01:54.672399 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2919 10:01:54.675689 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2920 10:01:54.675772
2921 10:01:54.679596 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2922 10:01:54.682261 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2923 10:01:54.685748 [Gating] SW calibration Done
2924 10:01:54.685831 ==
2925 10:01:54.689208 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 10:01:54.693128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 10:01:54.693211 ==
2928 10:01:54.696148 RX Vref Scan: 0
2929 10:01:54.696231
2930 10:01:54.696297 RX Vref 0 -> 0, step: 1
2931 10:01:54.696359
2932 10:01:54.699176 RX Delay -40 -> 252, step: 8
2933 10:01:54.702636 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2934 10:01:54.709512 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2935 10:01:54.712541 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2936 10:01:54.715726 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2937 10:01:54.719568 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2938 10:01:54.722374 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2939 10:01:54.729137 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2940 10:01:54.732403 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2941 10:01:54.735909 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2942 10:01:54.739832 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2943 10:01:54.742960 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2944 10:01:54.745839 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2945 10:01:54.752501 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2946 10:01:54.756224 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2947 10:01:54.759218 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2948 10:01:54.762562 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2949 10:01:54.762645 ==
2950 10:01:54.765872 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 10:01:54.772975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 10:01:54.773058 ==
2953 10:01:54.773124 DQS Delay:
2954 10:01:54.775991 DQS0 = 0, DQS1 = 0
2955 10:01:54.776074 DQM Delay:
2956 10:01:54.776140 DQM0 = 115, DQM1 = 105
2957 10:01:54.779252 DQ Delay:
2958 10:01:54.782651 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2959 10:01:54.785876 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2960 10:01:54.789230 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =95
2961 10:01:54.792625 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2962 10:01:54.792709
2963 10:01:54.792774
2964 10:01:54.792836 ==
2965 10:01:54.795929 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 10:01:54.799410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 10:01:54.802514 ==
2968 10:01:54.802598
2969 10:01:54.802663
2970 10:01:54.802726 TX Vref Scan disable
2971 10:01:54.805784 == TX Byte 0 ==
2972 10:01:54.809308 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2973 10:01:54.812938 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2974 10:01:54.815868 == TX Byte 1 ==
2975 10:01:54.819040 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2976 10:01:54.822251 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2977 10:01:54.822329 ==
2978 10:01:54.825683 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 10:01:54.832003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 10:01:54.832108 ==
2981 10:01:54.843430 TX Vref=22, minBit 5, minWin=25, winSum=427
2982 10:01:54.846553 TX Vref=24, minBit 1, minWin=26, winSum=428
2983 10:01:54.849784 TX Vref=26, minBit 3, minWin=26, winSum=435
2984 10:01:54.853464 TX Vref=28, minBit 0, minWin=27, winSum=440
2985 10:01:54.856752 TX Vref=30, minBit 0, minWin=27, winSum=440
2986 10:01:54.863268 TX Vref=32, minBit 12, minWin=26, winSum=437
2987 10:01:54.866768 [TxChooseVref] Worse bit 0, Min win 27, Win sum 440, Final Vref 28
2988 10:01:54.866841
2989 10:01:54.870195 Final TX Range 1 Vref 28
2990 10:01:54.870292
2991 10:01:54.870382 ==
2992 10:01:54.873603 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 10:01:54.876811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 10:01:54.876880 ==
2995 10:01:54.876941
2996 10:01:54.880069
2997 10:01:54.880162 TX Vref Scan disable
2998 10:01:54.883744 == TX Byte 0 ==
2999 10:01:54.887059 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3000 10:01:54.889865 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3001 10:01:54.893459 == TX Byte 1 ==
3002 10:01:54.896971 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3003 10:01:54.899921 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3004 10:01:54.900005
3005 10:01:54.903517 [DATLAT]
3006 10:01:54.903615 Freq=1200, CH0 RK1
3007 10:01:54.903712
3008 10:01:54.906610 DATLAT Default: 0xd
3009 10:01:54.906696 0, 0xFFFF, sum = 0
3010 10:01:54.910134 1, 0xFFFF, sum = 0
3011 10:01:54.910237 2, 0xFFFF, sum = 0
3012 10:01:54.913442 3, 0xFFFF, sum = 0
3013 10:01:54.913533 4, 0xFFFF, sum = 0
3014 10:01:54.916804 5, 0xFFFF, sum = 0
3015 10:01:54.916881 6, 0xFFFF, sum = 0
3016 10:01:54.920068 7, 0xFFFF, sum = 0
3017 10:01:54.920140 8, 0xFFFF, sum = 0
3018 10:01:54.923342 9, 0xFFFF, sum = 0
3019 10:01:54.927045 10, 0xFFFF, sum = 0
3020 10:01:54.927155 11, 0xFFFF, sum = 0
3021 10:01:54.930090 12, 0x0, sum = 1
3022 10:01:54.930169 13, 0x0, sum = 2
3023 10:01:54.930232 14, 0x0, sum = 3
3024 10:01:54.933345 15, 0x0, sum = 4
3025 10:01:54.933425 best_step = 13
3026 10:01:54.933488
3027 10:01:54.933548 ==
3028 10:01:54.936819 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 10:01:54.943518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 10:01:54.943600 ==
3031 10:01:54.943671 RX Vref Scan: 0
3032 10:01:54.943742
3033 10:01:54.947229 RX Vref 0 -> 0, step: 1
3034 10:01:54.947314
3035 10:01:54.950427 RX Delay -21 -> 252, step: 4
3036 10:01:54.954037 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3037 10:01:54.957072 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3038 10:01:54.963696 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3039 10:01:54.967074 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3040 10:01:54.970761 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3041 10:01:54.973378 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3042 10:01:54.976953 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3043 10:01:54.983946 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3044 10:01:54.987205 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3045 10:01:54.990088 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3046 10:01:54.993761 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3047 10:01:54.997006 iDelay=195, Bit 11, Center 92 (27 ~ 158) 132
3048 10:01:55.000632 iDelay=195, Bit 12, Center 112 (43 ~ 182) 140
3049 10:01:55.007255 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3050 10:01:55.010628 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3051 10:01:55.014133 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3052 10:01:55.014248 ==
3053 10:01:55.017611 Dram Type= 6, Freq= 0, CH_0, rank 1
3054 10:01:55.020535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3055 10:01:55.023640 ==
3056 10:01:55.023723 DQS Delay:
3057 10:01:55.023789 DQS0 = 0, DQS1 = 0
3058 10:01:55.026883 DQM Delay:
3059 10:01:55.026966 DQM0 = 114, DQM1 = 104
3060 10:01:55.030428 DQ Delay:
3061 10:01:55.033955 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3062 10:01:55.036800 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3063 10:01:55.040338 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =92
3064 10:01:55.043752 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =112
3065 10:01:55.043836
3066 10:01:55.043901
3067 10:01:55.050392 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3068 10:01:55.053733 CH0 RK1: MR19=403, MR18=3F5
3069 10:01:55.060478 CH0_RK1: MR19=0x403, MR18=0x3F5, DQSOSC=408, MR23=63, INC=39, DEC=26
3070 10:01:55.064015 [RxdqsGatingPostProcess] freq 1200
3071 10:01:55.066832 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3072 10:01:55.070608 best DQS0 dly(2T, 0.5T) = (0, 12)
3073 10:01:55.073628 best DQS1 dly(2T, 0.5T) = (0, 12)
3074 10:01:55.077298 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3075 10:01:55.080616 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3076 10:01:55.083876 best DQS0 dly(2T, 0.5T) = (0, 11)
3077 10:01:55.087067 best DQS1 dly(2T, 0.5T) = (0, 12)
3078 10:01:55.090552 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3079 10:01:55.093890 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3080 10:01:55.097215 Pre-setting of DQS Precalculation
3081 10:01:55.100676 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3082 10:01:55.100759 ==
3083 10:01:55.103487 Dram Type= 6, Freq= 0, CH_1, rank 0
3084 10:01:55.110777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 10:01:55.110861 ==
3086 10:01:55.113821 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3087 10:01:55.120123 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3088 10:01:55.129039 [CA 0] Center 38 (9~68) winsize 60
3089 10:01:55.132515 [CA 1] Center 38 (8~68) winsize 61
3090 10:01:55.135870 [CA 2] Center 35 (6~65) winsize 60
3091 10:01:55.138990 [CA 3] Center 34 (4~65) winsize 62
3092 10:01:55.142652 [CA 4] Center 34 (4~65) winsize 62
3093 10:01:55.146063 [CA 5] Center 34 (4~64) winsize 61
3094 10:01:55.146140
3095 10:01:55.149087 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3096 10:01:55.149160
3097 10:01:55.152201 [CATrainingPosCal] consider 1 rank data
3098 10:01:55.155474 u2DelayCellTimex100 = 270/100 ps
3099 10:01:55.158889 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3100 10:01:55.162306 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3101 10:01:55.169456 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3102 10:01:55.172306 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3103 10:01:55.175742 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3104 10:01:55.179064 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3105 10:01:55.179148
3106 10:01:55.182518 CA PerBit enable=1, Macro0, CA PI delay=34
3107 10:01:55.182602
3108 10:01:55.185539 [CBTSetCACLKResult] CA Dly = 34
3109 10:01:55.185622 CS Dly: 6 (0~37)
3110 10:01:55.185694 ==
3111 10:01:55.188900 Dram Type= 6, Freq= 0, CH_1, rank 1
3112 10:01:55.195909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 10:01:55.196020 ==
3114 10:01:55.198945 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3115 10:01:55.205388 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3116 10:01:55.214558 [CA 0] Center 38 (8~68) winsize 61
3117 10:01:55.218049 [CA 1] Center 38 (9~68) winsize 60
3118 10:01:55.221260 [CA 2] Center 35 (5~65) winsize 61
3119 10:01:55.224597 [CA 3] Center 34 (4~65) winsize 62
3120 10:01:55.227787 [CA 4] Center 34 (4~65) winsize 62
3121 10:01:55.230947 [CA 5] Center 33 (3~64) winsize 62
3122 10:01:55.231048
3123 10:01:55.234209 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3124 10:01:55.234282
3125 10:01:55.238349 [CATrainingPosCal] consider 2 rank data
3126 10:01:55.241084 u2DelayCellTimex100 = 270/100 ps
3127 10:01:55.244269 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3128 10:01:55.247865 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3129 10:01:55.254343 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3130 10:01:55.257902 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3131 10:01:55.260676 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3132 10:01:55.264069 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3133 10:01:55.264178
3134 10:01:55.268097 CA PerBit enable=1, Macro0, CA PI delay=34
3135 10:01:55.268180
3136 10:01:55.271023 [CBTSetCACLKResult] CA Dly = 34
3137 10:01:55.271107 CS Dly: 7 (0~40)
3138 10:01:55.271173
3139 10:01:55.274494 ----->DramcWriteLeveling(PI) begin...
3140 10:01:55.277566 ==
3141 10:01:55.281448 Dram Type= 6, Freq= 0, CH_1, rank 0
3142 10:01:55.284550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 10:01:55.284661 ==
3144 10:01:55.287530 Write leveling (Byte 0): 25 => 25
3145 10:01:55.290592 Write leveling (Byte 1): 28 => 28
3146 10:01:55.293931 DramcWriteLeveling(PI) end<-----
3147 10:01:55.294032
3148 10:01:55.294122 ==
3149 10:01:55.297477 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 10:01:55.300803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 10:01:55.300901 ==
3152 10:01:55.304516 [Gating] SW mode calibration
3153 10:01:55.310693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3154 10:01:55.317166 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3155 10:01:55.320800 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3156 10:01:55.324464 0 15 4 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)
3157 10:01:55.330306 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3158 10:01:55.333864 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3159 10:01:55.337024 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3160 10:01:55.344009 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3161 10:01:55.347338 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3162 10:01:55.350333 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3163 10:01:55.357328 1 0 0 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
3164 10:01:55.360757 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3165 10:01:55.363873 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3166 10:01:55.366900 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3167 10:01:55.373661 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3168 10:01:55.377078 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 10:01:55.380693 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 10:01:55.386881 1 0 28 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
3171 10:01:55.390481 1 1 0 | B1->B0 | 3c3c 3333 | 0 1 | (1 1) (0 0)
3172 10:01:55.393669 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 10:01:55.400455 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 10:01:55.403983 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 10:01:55.407294 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 10:01:55.413813 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 10:01:55.417362 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 10:01:55.420415 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3179 10:01:55.427043 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3180 10:01:55.429884 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 10:01:55.433271 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 10:01:55.440092 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 10:01:55.443223 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 10:01:55.446865 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 10:01:55.453060 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 10:01:55.456659 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 10:01:55.460025 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 10:01:55.466514 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 10:01:55.469718 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 10:01:55.473554 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 10:01:55.479988 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 10:01:55.483306 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 10:01:55.486351 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 10:01:55.493210 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3195 10:01:55.496728 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 10:01:55.499609 Total UI for P1: 0, mck2ui 16
3197 10:01:55.502967 best dqsien dly found for B0: ( 1, 3, 28)
3198 10:01:55.506346 Total UI for P1: 0, mck2ui 16
3199 10:01:55.509823 best dqsien dly found for B1: ( 1, 3, 30)
3200 10:01:55.513314 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3201 10:01:55.516886 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3202 10:01:55.516965
3203 10:01:55.520131 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3204 10:01:55.523143 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3205 10:01:55.526615 [Gating] SW calibration Done
3206 10:01:55.526699 ==
3207 10:01:55.529717 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 10:01:55.533224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 10:01:55.533306 ==
3210 10:01:55.536321 RX Vref Scan: 0
3211 10:01:55.536431
3212 10:01:55.539866 RX Vref 0 -> 0, step: 1
3213 10:01:55.539950
3214 10:01:55.540017 RX Delay -40 -> 252, step: 8
3215 10:01:55.546873 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3216 10:01:55.549781 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3217 10:01:55.553009 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3218 10:01:55.556056 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3219 10:01:55.559761 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3220 10:01:55.566466 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3221 10:01:55.569815 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3222 10:01:55.572837 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3223 10:01:55.576547 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3224 10:01:55.579331 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3225 10:01:55.586118 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3226 10:01:55.589455 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3227 10:01:55.593133 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3228 10:01:55.596624 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3229 10:01:55.599487 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3230 10:01:55.606299 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3231 10:01:55.606386 ==
3232 10:01:55.609253 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 10:01:55.612518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 10:01:55.612603 ==
3235 10:01:55.612670 DQS Delay:
3236 10:01:55.615965 DQS0 = 0, DQS1 = 0
3237 10:01:55.616049 DQM Delay:
3238 10:01:55.619311 DQM0 = 116, DQM1 = 110
3239 10:01:55.619401 DQ Delay:
3240 10:01:55.622444 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3241 10:01:55.625787 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3242 10:01:55.629291 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3243 10:01:55.632398 DQ12 =123, DQ13 =115, DQ14 =115, DQ15 =115
3244 10:01:55.632499
3245 10:01:55.635899
3246 10:01:55.636025 ==
3247 10:01:55.639310 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 10:01:55.643028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 10:01:55.643115 ==
3250 10:01:55.643219
3251 10:01:55.643318
3252 10:01:55.646090 TX Vref Scan disable
3253 10:01:55.646174 == TX Byte 0 ==
3254 10:01:55.649326 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3255 10:01:55.655739 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3256 10:01:55.655851 == TX Byte 1 ==
3257 10:01:55.662469 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3258 10:01:55.665560 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3259 10:01:55.665644 ==
3260 10:01:55.669551 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 10:01:55.672311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 10:01:55.672397 ==
3263 10:01:55.684937 TX Vref=22, minBit 2, minWin=24, winSum=411
3264 10:01:55.688111 TX Vref=24, minBit 1, minWin=25, winSum=416
3265 10:01:55.691423 TX Vref=26, minBit 0, minWin=25, winSum=417
3266 10:01:55.694840 TX Vref=28, minBit 1, minWin=25, winSum=421
3267 10:01:55.698234 TX Vref=30, minBit 1, minWin=26, winSum=428
3268 10:01:55.701591 TX Vref=32, minBit 1, minWin=26, winSum=426
3269 10:01:55.708034 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
3270 10:01:55.708119
3271 10:01:55.711174 Final TX Range 1 Vref 30
3272 10:01:55.711258
3273 10:01:55.711325 ==
3274 10:01:55.714633 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 10:01:55.718146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 10:01:55.718230 ==
3277 10:01:55.718297
3278 10:01:55.721960
3279 10:01:55.722044 TX Vref Scan disable
3280 10:01:55.724604 == TX Byte 0 ==
3281 10:01:55.728070 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3282 10:01:55.731234 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3283 10:01:55.734555 == TX Byte 1 ==
3284 10:01:55.737990 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3285 10:01:55.741507 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3286 10:01:55.741592
3287 10:01:55.744795 [DATLAT]
3288 10:01:55.744878 Freq=1200, CH1 RK0
3289 10:01:55.744946
3290 10:01:55.748272 DATLAT Default: 0xd
3291 10:01:55.748356 0, 0xFFFF, sum = 0
3292 10:01:55.750999 1, 0xFFFF, sum = 0
3293 10:01:55.751084 2, 0xFFFF, sum = 0
3294 10:01:55.754476 3, 0xFFFF, sum = 0
3295 10:01:55.754561 4, 0xFFFF, sum = 0
3296 10:01:55.757928 5, 0xFFFF, sum = 0
3297 10:01:55.758014 6, 0xFFFF, sum = 0
3298 10:01:55.761379 7, 0xFFFF, sum = 0
3299 10:01:55.765456 8, 0xFFFF, sum = 0
3300 10:01:55.765546 9, 0xFFFF, sum = 0
3301 10:01:55.767667 10, 0xFFFF, sum = 0
3302 10:01:55.767752 11, 0xFFFF, sum = 0
3303 10:01:55.771262 12, 0x0, sum = 1
3304 10:01:55.771356 13, 0x0, sum = 2
3305 10:01:55.774410 14, 0x0, sum = 3
3306 10:01:55.774495 15, 0x0, sum = 4
3307 10:01:55.774562 best_step = 13
3308 10:01:55.774622
3309 10:01:55.777662 ==
3310 10:01:55.780947 Dram Type= 6, Freq= 0, CH_1, rank 0
3311 10:01:55.784730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3312 10:01:55.784832 ==
3313 10:01:55.784899 RX Vref Scan: 1
3314 10:01:55.784960
3315 10:01:55.787927 Set Vref Range= 32 -> 127
3316 10:01:55.788009
3317 10:01:55.791310 RX Vref 32 -> 127, step: 1
3318 10:01:55.791430
3319 10:01:55.794220 RX Delay -21 -> 252, step: 4
3320 10:01:55.794302
3321 10:01:55.798187 Set Vref, RX VrefLevel [Byte0]: 32
3322 10:01:55.801226 [Byte1]: 32
3323 10:01:55.801308
3324 10:01:55.804367 Set Vref, RX VrefLevel [Byte0]: 33
3325 10:01:55.807762 [Byte1]: 33
3326 10:01:55.807844
3327 10:01:55.811176 Set Vref, RX VrefLevel [Byte0]: 34
3328 10:01:55.814055 [Byte1]: 34
3329 10:01:55.818649
3330 10:01:55.818730 Set Vref, RX VrefLevel [Byte0]: 35
3331 10:01:55.821998 [Byte1]: 35
3332 10:01:55.826943
3333 10:01:55.827029 Set Vref, RX VrefLevel [Byte0]: 36
3334 10:01:55.830024 [Byte1]: 36
3335 10:01:55.834968
3336 10:01:55.835050 Set Vref, RX VrefLevel [Byte0]: 37
3337 10:01:55.837948 [Byte1]: 37
3338 10:01:55.842442
3339 10:01:55.842523 Set Vref, RX VrefLevel [Byte0]: 38
3340 10:01:55.845831 [Byte1]: 38
3341 10:01:55.850470
3342 10:01:55.850551 Set Vref, RX VrefLevel [Byte0]: 39
3343 10:01:55.853770 [Byte1]: 39
3344 10:01:55.858376
3345 10:01:55.858457 Set Vref, RX VrefLevel [Byte0]: 40
3346 10:01:55.861597 [Byte1]: 40
3347 10:01:55.866050
3348 10:01:55.866131 Set Vref, RX VrefLevel [Byte0]: 41
3349 10:01:55.869718 [Byte1]: 41
3350 10:01:55.874176
3351 10:01:55.874258 Set Vref, RX VrefLevel [Byte0]: 42
3352 10:01:55.877576 [Byte1]: 42
3353 10:01:55.882019
3354 10:01:55.882100 Set Vref, RX VrefLevel [Byte0]: 43
3355 10:01:55.885498 [Byte1]: 43
3356 10:01:55.890376
3357 10:01:55.890458 Set Vref, RX VrefLevel [Byte0]: 44
3358 10:01:55.893874 [Byte1]: 44
3359 10:01:55.898364
3360 10:01:55.898445 Set Vref, RX VrefLevel [Byte0]: 45
3361 10:01:55.901577 [Byte1]: 45
3362 10:01:55.906154
3363 10:01:55.906236 Set Vref, RX VrefLevel [Byte0]: 46
3364 10:01:55.909299 [Byte1]: 46
3365 10:01:55.913853
3366 10:01:55.913937 Set Vref, RX VrefLevel [Byte0]: 47
3367 10:01:55.917232 [Byte1]: 47
3368 10:01:55.921528
3369 10:01:55.921612 Set Vref, RX VrefLevel [Byte0]: 48
3370 10:01:55.924944 [Byte1]: 48
3371 10:01:55.929574
3372 10:01:55.929658 Set Vref, RX VrefLevel [Byte0]: 49
3373 10:01:55.932889 [Byte1]: 49
3374 10:01:55.937400
3375 10:01:55.937484 Set Vref, RX VrefLevel [Byte0]: 50
3376 10:01:55.940799 [Byte1]: 50
3377 10:01:55.945365
3378 10:01:55.945449 Set Vref, RX VrefLevel [Byte0]: 51
3379 10:01:55.948930 [Byte1]: 51
3380 10:01:55.953128
3381 10:01:55.953211 Set Vref, RX VrefLevel [Byte0]: 52
3382 10:01:55.956581 [Byte1]: 52
3383 10:01:55.961459
3384 10:01:55.961542 Set Vref, RX VrefLevel [Byte0]: 53
3385 10:01:55.964640 [Byte1]: 53
3386 10:01:55.969101
3387 10:01:55.969184 Set Vref, RX VrefLevel [Byte0]: 54
3388 10:01:55.972444 [Byte1]: 54
3389 10:01:55.977803
3390 10:01:55.977886 Set Vref, RX VrefLevel [Byte0]: 55
3391 10:01:55.980735 [Byte1]: 55
3392 10:01:55.984844
3393 10:01:55.984928 Set Vref, RX VrefLevel [Byte0]: 56
3394 10:01:55.988701 [Byte1]: 56
3395 10:01:55.992815
3396 10:01:55.992915 Set Vref, RX VrefLevel [Byte0]: 57
3397 10:01:55.996374 [Byte1]: 57
3398 10:01:56.001013
3399 10:01:56.001103 Set Vref, RX VrefLevel [Byte0]: 58
3400 10:01:56.004007 [Byte1]: 58
3401 10:01:56.008940
3402 10:01:56.009020 Set Vref, RX VrefLevel [Byte0]: 59
3403 10:01:56.012108 [Byte1]: 59
3404 10:01:56.016672
3405 10:01:56.016776 Set Vref, RX VrefLevel [Byte0]: 60
3406 10:01:56.020107 [Byte1]: 60
3407 10:01:56.024894
3408 10:01:56.024997 Set Vref, RX VrefLevel [Byte0]: 61
3409 10:01:56.028331 [Byte1]: 61
3410 10:01:56.032386
3411 10:01:56.032495 Set Vref, RX VrefLevel [Byte0]: 62
3412 10:01:56.035617 [Byte1]: 62
3413 10:01:56.040246
3414 10:01:56.040345 Set Vref, RX VrefLevel [Byte0]: 63
3415 10:01:56.043546 [Byte1]: 63
3416 10:01:56.048151
3417 10:01:56.048228 Set Vref, RX VrefLevel [Byte0]: 64
3418 10:01:56.051535 [Byte1]: 64
3419 10:01:56.056390
3420 10:01:56.056472 Set Vref, RX VrefLevel [Byte0]: 65
3421 10:01:56.059767 [Byte1]: 65
3422 10:01:56.064323
3423 10:01:56.064406 Set Vref, RX VrefLevel [Byte0]: 66
3424 10:01:56.067343 [Byte1]: 66
3425 10:01:56.072202
3426 10:01:56.072284 Set Vref, RX VrefLevel [Byte0]: 67
3427 10:01:56.075387 [Byte1]: 67
3428 10:01:56.079997
3429 10:01:56.080079 Set Vref, RX VrefLevel [Byte0]: 68
3430 10:01:56.083513 [Byte1]: 68
3431 10:01:56.088257
3432 10:01:56.088339 Set Vref, RX VrefLevel [Byte0]: 69
3433 10:01:56.091275 [Byte1]: 69
3434 10:01:56.095583
3435 10:01:56.095665 Set Vref, RX VrefLevel [Byte0]: 70
3436 10:01:56.099577 [Byte1]: 70
3437 10:01:56.104291
3438 10:01:56.104374 Set Vref, RX VrefLevel [Byte0]: 71
3439 10:01:56.107476 [Byte1]: 71
3440 10:01:56.111801
3441 10:01:56.111883 Final RX Vref Byte 0 = 57 to rank0
3442 10:01:56.114900 Final RX Vref Byte 1 = 52 to rank0
3443 10:01:56.118207 Final RX Vref Byte 0 = 57 to rank1
3444 10:01:56.121923 Final RX Vref Byte 1 = 52 to rank1==
3445 10:01:56.125053 Dram Type= 6, Freq= 0, CH_1, rank 0
3446 10:01:56.132133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 10:01:56.132218 ==
3448 10:01:56.132285 DQS Delay:
3449 10:01:56.132349 DQS0 = 0, DQS1 = 0
3450 10:01:56.134997 DQM Delay:
3451 10:01:56.135081 DQM0 = 116, DQM1 = 109
3452 10:01:56.138528 DQ Delay:
3453 10:01:56.141822 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3454 10:01:56.144983 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =114
3455 10:01:56.148416 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3456 10:01:56.151960 DQ12 =116, DQ13 =118, DQ14 =118, DQ15 =114
3457 10:01:56.152042
3458 10:01:56.152106
3459 10:01:56.158404 [DQSOSCAuto] RK0, (LSB)MR18= 0xffe3, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3460 10:01:56.162221 CH1 RK0: MR19=303, MR18=FFE3
3461 10:01:56.168371 CH1_RK0: MR19=0x303, MR18=0xFFE3, DQSOSC=410, MR23=63, INC=39, DEC=26
3462 10:01:56.168447
3463 10:01:56.171974 ----->DramcWriteLeveling(PI) begin...
3464 10:01:56.172048 ==
3465 10:01:56.175072 Dram Type= 6, Freq= 0, CH_1, rank 1
3466 10:01:56.178531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3467 10:01:56.178601 ==
3468 10:01:56.181771 Write leveling (Byte 0): 26 => 26
3469 10:01:56.185129 Write leveling (Byte 1): 29 => 29
3470 10:01:56.188977 DramcWriteLeveling(PI) end<-----
3471 10:01:56.189053
3472 10:01:56.189115 ==
3473 10:01:56.191837 Dram Type= 6, Freq= 0, CH_1, rank 1
3474 10:01:56.195038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3475 10:01:56.199066 ==
3476 10:01:56.199137 [Gating] SW mode calibration
3477 10:01:56.208677 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3478 10:01:56.212287 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3479 10:01:56.215266 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3480 10:01:56.222050 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 10:01:56.225463 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3482 10:01:56.228655 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3483 10:01:56.235200 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 10:01:56.239129 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3485 10:01:56.242159 0 15 24 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 0)
3486 10:01:56.248564 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3487 10:01:56.252104 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 10:01:56.255406 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3489 10:01:56.261755 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 10:01:56.265163 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 10:01:56.268721 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 10:01:56.274977 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 10:01:56.278404 1 0 24 | B1->B0 | 2727 3b3b | 0 0 | (0 0) (1 1)
3494 10:01:56.281891 1 0 28 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
3495 10:01:56.288289 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 10:01:56.291845 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 10:01:56.295111 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 10:01:56.298552 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 10:01:56.304921 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 10:01:56.308302 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 10:01:56.311968 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3502 10:01:56.318383 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3503 10:01:56.321719 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 10:01:56.325129 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 10:01:56.331789 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 10:01:56.334797 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 10:01:56.338589 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 10:01:56.344714 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 10:01:56.348072 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 10:01:56.351423 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 10:01:56.358171 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 10:01:56.361352 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 10:01:56.364837 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 10:01:56.371283 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 10:01:56.375064 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 10:01:56.377982 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 10:01:56.384562 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3518 10:01:56.388130 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3519 10:01:56.391679 Total UI for P1: 0, mck2ui 16
3520 10:01:56.394523 best dqsien dly found for B0: ( 1, 3, 24)
3521 10:01:56.398201 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 10:01:56.401485 Total UI for P1: 0, mck2ui 16
3523 10:01:56.404774 best dqsien dly found for B1: ( 1, 3, 28)
3524 10:01:56.407851 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3525 10:01:56.411080 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3526 10:01:56.411163
3527 10:01:56.418030 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3528 10:01:56.421268 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3529 10:01:56.421352 [Gating] SW calibration Done
3530 10:01:56.424379 ==
3531 10:01:56.427857 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 10:01:56.430840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 10:01:56.430924 ==
3534 10:01:56.430989 RX Vref Scan: 0
3535 10:01:56.431049
3536 10:01:56.434320 RX Vref 0 -> 0, step: 1
3537 10:01:56.434403
3538 10:01:56.437583 RX Delay -40 -> 252, step: 8
3539 10:01:56.440851 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3540 10:01:56.444325 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3541 10:01:56.451154 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3542 10:01:56.454010 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3543 10:01:56.457412 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3544 10:01:56.460876 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3545 10:01:56.464266 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3546 10:01:56.467204 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3547 10:01:56.473934 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3548 10:01:56.477344 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3549 10:01:56.480633 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3550 10:01:56.483794 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3551 10:01:56.490852 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3552 10:01:56.493829 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3553 10:01:56.497530 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3554 10:01:56.501047 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3555 10:01:56.501134 ==
3556 10:01:56.504124 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 10:01:56.507452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 10:01:56.510494 ==
3559 10:01:56.510580 DQS Delay:
3560 10:01:56.510665 DQS0 = 0, DQS1 = 0
3561 10:01:56.513931 DQM Delay:
3562 10:01:56.514017 DQM0 = 113, DQM1 = 110
3563 10:01:56.517285 DQ Delay:
3564 10:01:56.520578 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3565 10:01:56.523695 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3566 10:01:56.526951 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3567 10:01:56.530621 DQ12 =115, DQ13 =123, DQ14 =119, DQ15 =115
3568 10:01:56.530708
3569 10:01:56.530793
3570 10:01:56.530874 ==
3571 10:01:56.534438 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 10:01:56.537378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 10:01:56.537481 ==
3574 10:01:56.537566
3575 10:01:56.540299
3576 10:01:56.540385 TX Vref Scan disable
3577 10:01:56.544243 == TX Byte 0 ==
3578 10:01:56.547391 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3579 10:01:56.550588 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3580 10:01:56.553770 == TX Byte 1 ==
3581 10:01:56.557065 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3582 10:01:56.560286 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3583 10:01:56.560370 ==
3584 10:01:56.564050 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 10:01:56.570408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 10:01:56.570493 ==
3587 10:01:56.581169 TX Vref=22, minBit 1, minWin=25, winSum=413
3588 10:01:56.583982 TX Vref=24, minBit 2, minWin=25, winSum=417
3589 10:01:56.587595 TX Vref=26, minBit 0, minWin=25, winSum=426
3590 10:01:56.591217 TX Vref=28, minBit 3, minWin=25, winSum=428
3591 10:01:56.594298 TX Vref=30, minBit 3, minWin=25, winSum=430
3592 10:01:56.600781 TX Vref=32, minBit 0, minWin=26, winSum=431
3593 10:01:56.604205 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 32
3594 10:01:56.604290
3595 10:01:56.607113 Final TX Range 1 Vref 32
3596 10:01:56.607198
3597 10:01:56.607264 ==
3598 10:01:56.610657 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 10:01:56.614105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 10:01:56.617479 ==
3601 10:01:56.617563
3602 10:01:56.617629
3603 10:01:56.617700 TX Vref Scan disable
3604 10:01:56.620607 == TX Byte 0 ==
3605 10:01:56.623714 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3606 10:01:56.630601 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3607 10:01:56.630685 == TX Byte 1 ==
3608 10:01:56.634678 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3609 10:01:56.640611 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3610 10:01:56.640695
3611 10:01:56.640761 [DATLAT]
3612 10:01:56.640842 Freq=1200, CH1 RK1
3613 10:01:56.640904
3614 10:01:56.643876 DATLAT Default: 0xd
3615 10:01:56.643959 0, 0xFFFF, sum = 0
3616 10:01:56.647259 1, 0xFFFF, sum = 0
3617 10:01:56.647343 2, 0xFFFF, sum = 0
3618 10:01:56.650574 3, 0xFFFF, sum = 0
3619 10:01:56.653672 4, 0xFFFF, sum = 0
3620 10:01:56.653767 5, 0xFFFF, sum = 0
3621 10:01:56.657109 6, 0xFFFF, sum = 0
3622 10:01:56.657189 7, 0xFFFF, sum = 0
3623 10:01:56.660512 8, 0xFFFF, sum = 0
3624 10:01:56.660590 9, 0xFFFF, sum = 0
3625 10:01:56.664186 10, 0xFFFF, sum = 0
3626 10:01:56.664275 11, 0xFFFF, sum = 0
3627 10:01:56.667283 12, 0x0, sum = 1
3628 10:01:56.667416 13, 0x0, sum = 2
3629 10:01:56.670582 14, 0x0, sum = 3
3630 10:01:56.670663 15, 0x0, sum = 4
3631 10:01:56.670728 best_step = 13
3632 10:01:56.674132
3633 10:01:56.674199 ==
3634 10:01:56.677580 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 10:01:56.681393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 10:01:56.681464 ==
3637 10:01:56.681524 RX Vref Scan: 0
3638 10:01:56.681586
3639 10:01:56.683853 RX Vref 0 -> 0, step: 1
3640 10:01:56.683921
3641 10:01:56.687423 RX Delay -21 -> 252, step: 4
3642 10:01:56.690326 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3643 10:01:56.697505 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3644 10:01:56.700649 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3645 10:01:56.703977 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3646 10:01:56.707272 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3647 10:01:56.710407 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3648 10:01:56.716830 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3649 10:01:56.720131 iDelay=191, Bit 7, Center 112 (47 ~ 178) 132
3650 10:01:56.723878 iDelay=191, Bit 8, Center 100 (35 ~ 166) 132
3651 10:01:56.726837 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3652 10:01:56.730129 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3653 10:01:56.737008 iDelay=191, Bit 11, Center 104 (39 ~ 170) 132
3654 10:01:56.740495 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3655 10:01:56.743787 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3656 10:01:56.747030 iDelay=191, Bit 14, Center 116 (51 ~ 182) 132
3657 10:01:56.749975 iDelay=191, Bit 15, Center 118 (51 ~ 186) 136
3658 10:01:56.753828 ==
3659 10:01:56.756908 Dram Type= 6, Freq= 0, CH_1, rank 1
3660 10:01:56.760011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3661 10:01:56.760083 ==
3662 10:01:56.760147 DQS Delay:
3663 10:01:56.763623 DQS0 = 0, DQS1 = 0
3664 10:01:56.763705 DQM Delay:
3665 10:01:56.766514 DQM0 = 114, DQM1 = 109
3666 10:01:56.766585 DQ Delay:
3667 10:01:56.770215 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3668 10:01:56.773626 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =112
3669 10:01:56.776677 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =104
3670 10:01:56.779956 DQ12 =114, DQ13 =118, DQ14 =116, DQ15 =118
3671 10:01:56.780032
3672 10:01:56.780094
3673 10:01:56.790262 [DQSOSCAuto] RK1, (LSB)MR18= 0xf8ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3674 10:01:56.793546 CH1 RK1: MR19=303, MR18=F8FF
3675 10:01:56.796423 CH1_RK1: MR19=0x303, MR18=0xF8FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3676 10:01:56.800228 [RxdqsGatingPostProcess] freq 1200
3677 10:01:56.806605 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3678 10:01:56.809945 best DQS0 dly(2T, 0.5T) = (0, 11)
3679 10:01:56.813142 best DQS1 dly(2T, 0.5T) = (0, 11)
3680 10:01:56.816772 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3681 10:01:56.819576 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3682 10:01:56.822903 best DQS0 dly(2T, 0.5T) = (0, 11)
3683 10:01:56.826368 best DQS1 dly(2T, 0.5T) = (0, 11)
3684 10:01:56.829662 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3685 10:01:56.832773 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3686 10:01:56.836305 Pre-setting of DQS Precalculation
3687 10:01:56.839221 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3688 10:01:56.846239 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3689 10:01:56.855554 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3690 10:01:56.855634
3691 10:01:56.855697
3692 10:01:56.855757 [Calibration Summary] 2400 Mbps
3693 10:01:56.859216 CH 0, Rank 0
3694 10:01:56.862912 SW Impedance : PASS
3695 10:01:56.862994 DUTY Scan : NO K
3696 10:01:56.865910 ZQ Calibration : PASS
3697 10:01:56.865992 Jitter Meter : NO K
3698 10:01:56.869095 CBT Training : PASS
3699 10:01:56.873289 Write leveling : PASS
3700 10:01:56.873371 RX DQS gating : PASS
3701 10:01:56.876009 RX DQ/DQS(RDDQC) : PASS
3702 10:01:56.879182 TX DQ/DQS : PASS
3703 10:01:56.879265 RX DATLAT : PASS
3704 10:01:56.882199 RX DQ/DQS(Engine): PASS
3705 10:01:56.885828 TX OE : NO K
3706 10:01:56.885911 All Pass.
3707 10:01:56.885998
3708 10:01:56.886071 CH 0, Rank 1
3709 10:01:56.889374 SW Impedance : PASS
3710 10:01:56.892225 DUTY Scan : NO K
3711 10:01:56.892307 ZQ Calibration : PASS
3712 10:01:56.895662 Jitter Meter : NO K
3713 10:01:56.898938 CBT Training : PASS
3714 10:01:56.899020 Write leveling : PASS
3715 10:01:56.902104 RX DQS gating : PASS
3716 10:01:56.906126 RX DQ/DQS(RDDQC) : PASS
3717 10:01:56.906208 TX DQ/DQS : PASS
3718 10:01:56.908881 RX DATLAT : PASS
3719 10:01:56.908962 RX DQ/DQS(Engine): PASS
3720 10:01:56.911992 TX OE : NO K
3721 10:01:56.912083 All Pass.
3722 10:01:56.912149
3723 10:01:56.915820 CH 1, Rank 0
3724 10:01:56.915903 SW Impedance : PASS
3725 10:01:56.918811 DUTY Scan : NO K
3726 10:01:56.922213 ZQ Calibration : PASS
3727 10:01:56.922295 Jitter Meter : NO K
3728 10:01:56.925677 CBT Training : PASS
3729 10:01:56.928651 Write leveling : PASS
3730 10:01:56.928733 RX DQS gating : PASS
3731 10:01:56.932365 RX DQ/DQS(RDDQC) : PASS
3732 10:01:56.935319 TX DQ/DQS : PASS
3733 10:01:56.935437 RX DATLAT : PASS
3734 10:01:56.938767 RX DQ/DQS(Engine): PASS
3735 10:01:56.942078 TX OE : NO K
3736 10:01:56.942161 All Pass.
3737 10:01:56.942226
3738 10:01:56.942286 CH 1, Rank 1
3739 10:01:56.945556 SW Impedance : PASS
3740 10:01:56.948948 DUTY Scan : NO K
3741 10:01:56.949030 ZQ Calibration : PASS
3742 10:01:56.951920 Jitter Meter : NO K
3743 10:01:56.955876 CBT Training : PASS
3744 10:01:56.955992 Write leveling : PASS
3745 10:01:56.958854 RX DQS gating : PASS
3746 10:01:56.958937 RX DQ/DQS(RDDQC) : PASS
3747 10:01:56.962223 TX DQ/DQS : PASS
3748 10:01:56.965492 RX DATLAT : PASS
3749 10:01:56.965574 RX DQ/DQS(Engine): PASS
3750 10:01:56.969073 TX OE : NO K
3751 10:01:56.969156 All Pass.
3752 10:01:56.969221
3753 10:01:56.971978 DramC Write-DBI off
3754 10:01:56.975624 PER_BANK_REFRESH: Hybrid Mode
3755 10:01:56.975707 TX_TRACKING: ON
3756 10:01:56.985388 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3757 10:01:56.988617 [FAST_K] Save calibration result to emmc
3758 10:01:56.991902 dramc_set_vcore_voltage set vcore to 650000
3759 10:01:56.995627 Read voltage for 600, 5
3760 10:01:56.995709 Vio18 = 0
3761 10:01:56.998341 Vcore = 650000
3762 10:01:56.998424 Vdram = 0
3763 10:01:56.998488 Vddq = 0
3764 10:01:56.998549 Vmddr = 0
3765 10:01:57.004930 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3766 10:01:57.011596 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3767 10:01:57.011679 MEM_TYPE=3, freq_sel=19
3768 10:01:57.014893 sv_algorithm_assistance_LP4_1600
3769 10:01:57.018634 ============ PULL DRAM RESETB DOWN ============
3770 10:01:57.024784 ========== PULL DRAM RESETB DOWN end =========
3771 10:01:57.028318 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3772 10:01:57.031851 ===================================
3773 10:01:57.035127 LPDDR4 DRAM CONFIGURATION
3774 10:01:57.037954 ===================================
3775 10:01:57.038052 EX_ROW_EN[0] = 0x0
3776 10:01:57.041403 EX_ROW_EN[1] = 0x0
3777 10:01:57.041484 LP4Y_EN = 0x0
3778 10:01:57.045250 WORK_FSP = 0x0
3779 10:01:57.045333 WL = 0x2
3780 10:01:57.048041 RL = 0x2
3781 10:01:57.048123 BL = 0x2
3782 10:01:57.051722 RPST = 0x0
3783 10:01:57.051805 RD_PRE = 0x0
3784 10:01:57.055117 WR_PRE = 0x1
3785 10:01:57.058830 WR_PST = 0x0
3786 10:01:57.058912 DBI_WR = 0x0
3787 10:01:57.061709 DBI_RD = 0x0
3788 10:01:57.061791 OTF = 0x1
3789 10:01:57.065061 ===================================
3790 10:01:57.068456 ===================================
3791 10:01:57.068538 ANA top config
3792 10:01:57.071738 ===================================
3793 10:01:57.075306 DLL_ASYNC_EN = 0
3794 10:01:57.078357 ALL_SLAVE_EN = 1
3795 10:01:57.082394 NEW_RANK_MODE = 1
3796 10:01:57.085013 DLL_IDLE_MODE = 1
3797 10:01:57.085095 LP45_APHY_COMB_EN = 1
3798 10:01:57.088070 TX_ODT_DIS = 1
3799 10:01:57.091495 NEW_8X_MODE = 1
3800 10:01:57.095097 ===================================
3801 10:01:57.098180 ===================================
3802 10:01:57.101248 data_rate = 1200
3803 10:01:57.104542 CKR = 1
3804 10:01:57.104625 DQ_P2S_RATIO = 8
3805 10:01:57.107903 ===================================
3806 10:01:57.111617 CA_P2S_RATIO = 8
3807 10:01:57.114991 DQ_CA_OPEN = 0
3808 10:01:57.118174 DQ_SEMI_OPEN = 0
3809 10:01:57.121074 CA_SEMI_OPEN = 0
3810 10:01:57.124726 CA_FULL_RATE = 0
3811 10:01:57.124808 DQ_CKDIV4_EN = 1
3812 10:01:57.127661 CA_CKDIV4_EN = 1
3813 10:01:57.131288 CA_PREDIV_EN = 0
3814 10:01:57.134539 PH8_DLY = 0
3815 10:01:57.137778 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3816 10:01:57.141083 DQ_AAMCK_DIV = 4
3817 10:01:57.141165 CA_AAMCK_DIV = 4
3818 10:01:57.144436 CA_ADMCK_DIV = 4
3819 10:01:57.148000 DQ_TRACK_CA_EN = 0
3820 10:01:57.151079 CA_PICK = 600
3821 10:01:57.154323 CA_MCKIO = 600
3822 10:01:57.157781 MCKIO_SEMI = 0
3823 10:01:57.161024 PLL_FREQ = 2288
3824 10:01:57.161107 DQ_UI_PI_RATIO = 32
3825 10:01:57.164542 CA_UI_PI_RATIO = 0
3826 10:01:57.167826 ===================================
3827 10:01:57.170957 ===================================
3828 10:01:57.174748 memory_type:LPDDR4
3829 10:01:57.177978 GP_NUM : 10
3830 10:01:57.178060 SRAM_EN : 1
3831 10:01:57.181028 MD32_EN : 0
3832 10:01:57.184610 ===================================
3833 10:01:57.187509 [ANA_INIT] >>>>>>>>>>>>>>
3834 10:01:57.187591 <<<<<< [CONFIGURE PHASE]: ANA_TX
3835 10:01:57.190812 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3836 10:01:57.194300 ===================================
3837 10:01:57.197294 data_rate = 1200,PCW = 0X5800
3838 10:01:57.200593 ===================================
3839 10:01:57.204254 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3840 10:01:57.210571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3841 10:01:57.217504 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3842 10:01:57.220982 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3843 10:01:57.224589 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3844 10:01:57.227282 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3845 10:01:57.230648 [ANA_INIT] flow start
3846 10:01:57.230730 [ANA_INIT] PLL >>>>>>>>
3847 10:01:57.234021 [ANA_INIT] PLL <<<<<<<<
3848 10:01:57.237417 [ANA_INIT] MIDPI >>>>>>>>
3849 10:01:57.240264 [ANA_INIT] MIDPI <<<<<<<<
3850 10:01:57.240346 [ANA_INIT] DLL >>>>>>>>
3851 10:01:57.243608 [ANA_INIT] flow end
3852 10:01:57.247489 ============ LP4 DIFF to SE enter ============
3853 10:01:57.250365 ============ LP4 DIFF to SE exit ============
3854 10:01:57.253604 [ANA_INIT] <<<<<<<<<<<<<
3855 10:01:57.257159 [Flow] Enable top DCM control >>>>>
3856 10:01:57.260581 [Flow] Enable top DCM control <<<<<
3857 10:01:57.263560 Enable DLL master slave shuffle
3858 10:01:57.270732 ==============================================================
3859 10:01:57.270814 Gating Mode config
3860 10:01:57.276717 ==============================================================
3861 10:01:57.276799 Config description:
3862 10:01:57.287352 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3863 10:01:57.293805 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3864 10:01:57.300059 SELPH_MODE 0: By rank 1: By Phase
3865 10:01:57.303385 ==============================================================
3866 10:01:57.306542 GAT_TRACK_EN = 1
3867 10:01:57.309912 RX_GATING_MODE = 2
3868 10:01:57.313580 RX_GATING_TRACK_MODE = 2
3869 10:01:57.316603 SELPH_MODE = 1
3870 10:01:57.320208 PICG_EARLY_EN = 1
3871 10:01:57.323329 VALID_LAT_VALUE = 1
3872 10:01:57.327219 ==============================================================
3873 10:01:57.330311 Enter into Gating configuration >>>>
3874 10:01:57.333676 Exit from Gating configuration <<<<
3875 10:01:57.337015 Enter into DVFS_PRE_config >>>>>
3876 10:01:57.350002 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3877 10:01:57.353373 Exit from DVFS_PRE_config <<<<<
3878 10:01:57.356873 Enter into PICG configuration >>>>
3879 10:01:57.356956 Exit from PICG configuration <<<<
3880 10:01:57.360276 [RX_INPUT] configuration >>>>>
3881 10:01:57.363123 [RX_INPUT] configuration <<<<<
3882 10:01:57.369773 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3883 10:01:57.373518 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3884 10:01:57.380229 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3885 10:01:57.386676 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3886 10:01:57.393437 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3887 10:01:57.400135 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3888 10:01:57.402763 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3889 10:01:57.406450 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3890 10:01:57.413581 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3891 10:01:57.416068 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3892 10:01:57.419416 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3893 10:01:57.422636 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3894 10:01:57.426168 ===================================
3895 10:01:57.429585 LPDDR4 DRAM CONFIGURATION
3896 10:01:57.432838 ===================================
3897 10:01:57.436026 EX_ROW_EN[0] = 0x0
3898 10:01:57.436111 EX_ROW_EN[1] = 0x0
3899 10:01:57.439480 LP4Y_EN = 0x0
3900 10:01:57.439565 WORK_FSP = 0x0
3901 10:01:57.442902 WL = 0x2
3902 10:01:57.442986 RL = 0x2
3903 10:01:57.446323 BL = 0x2
3904 10:01:57.446408 RPST = 0x0
3905 10:01:57.449549 RD_PRE = 0x0
3906 10:01:57.449633 WR_PRE = 0x1
3907 10:01:57.452755 WR_PST = 0x0
3908 10:01:57.452859 DBI_WR = 0x0
3909 10:01:57.456343 DBI_RD = 0x0
3910 10:01:57.459445 OTF = 0x1
3911 10:01:57.459529 ===================================
3912 10:01:57.465734 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3913 10:01:57.469071 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3914 10:01:57.472638 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3915 10:01:57.475907 ===================================
3916 10:01:57.478955 LPDDR4 DRAM CONFIGURATION
3917 10:01:57.482294 ===================================
3918 10:01:57.485870 EX_ROW_EN[0] = 0x10
3919 10:01:57.485954 EX_ROW_EN[1] = 0x0
3920 10:01:57.489187 LP4Y_EN = 0x0
3921 10:01:57.489271 WORK_FSP = 0x0
3922 10:01:57.492480 WL = 0x2
3923 10:01:57.492564 RL = 0x2
3924 10:01:57.495961 BL = 0x2
3925 10:01:57.496045 RPST = 0x0
3926 10:01:57.499142 RD_PRE = 0x0
3927 10:01:57.499225 WR_PRE = 0x1
3928 10:01:57.502287 WR_PST = 0x0
3929 10:01:57.502370 DBI_WR = 0x0
3930 10:01:57.505903 DBI_RD = 0x0
3931 10:01:57.505987 OTF = 0x1
3932 10:01:57.509015 ===================================
3933 10:01:57.516149 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3934 10:01:57.520603 nWR fixed to 30
3935 10:01:57.523918 [ModeRegInit_LP4] CH0 RK0
3936 10:01:57.524002 [ModeRegInit_LP4] CH0 RK1
3937 10:01:57.526938 [ModeRegInit_LP4] CH1 RK0
3938 10:01:57.530462 [ModeRegInit_LP4] CH1 RK1
3939 10:01:57.530546 match AC timing 17
3940 10:01:57.537249 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3941 10:01:57.540445 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3942 10:01:57.543657 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3943 10:01:57.550591 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3944 10:01:57.554195 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3945 10:01:57.554279 ==
3946 10:01:57.557044 Dram Type= 6, Freq= 0, CH_0, rank 0
3947 10:01:57.560600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 10:01:57.560684 ==
3949 10:01:57.567295 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 10:01:57.573660 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3951 10:01:57.576605 [CA 0] Center 36 (6~67) winsize 62
3952 10:01:57.579999 [CA 1] Center 36 (6~66) winsize 61
3953 10:01:57.583291 [CA 2] Center 34 (4~64) winsize 61
3954 10:01:57.586538 [CA 3] Center 34 (4~64) winsize 61
3955 10:01:57.590583 [CA 4] Center 33 (3~64) winsize 62
3956 10:01:57.593441 [CA 5] Center 33 (3~64) winsize 62
3957 10:01:57.593525
3958 10:01:57.596887 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3959 10:01:57.596970
3960 10:01:57.600248 [CATrainingPosCal] consider 1 rank data
3961 10:01:57.603210 u2DelayCellTimex100 = 270/100 ps
3962 10:01:57.606687 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3963 10:01:57.609695 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3964 10:01:57.613054 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3965 10:01:57.616711 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3966 10:01:57.620252 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3967 10:01:57.626515 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3968 10:01:57.626599
3969 10:01:57.629773 CA PerBit enable=1, Macro0, CA PI delay=33
3970 10:01:57.629856
3971 10:01:57.633098 [CBTSetCACLKResult] CA Dly = 33
3972 10:01:57.633182 CS Dly: 5 (0~36)
3973 10:01:57.633250 ==
3974 10:01:57.636346 Dram Type= 6, Freq= 0, CH_0, rank 1
3975 10:01:57.642847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 10:01:57.642932 ==
3977 10:01:57.646251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3978 10:01:57.652769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3979 10:01:57.656309 [CA 0] Center 36 (6~66) winsize 61
3980 10:01:57.659596 [CA 1] Center 36 (6~66) winsize 61
3981 10:01:57.662751 [CA 2] Center 34 (4~65) winsize 62
3982 10:01:57.666328 [CA 3] Center 34 (4~65) winsize 62
3983 10:01:57.669908 [CA 4] Center 33 (3~64) winsize 62
3984 10:01:57.673111 [CA 5] Center 33 (3~64) winsize 62
3985 10:01:57.673196
3986 10:01:57.676096 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3987 10:01:57.676181
3988 10:01:57.679421 [CATrainingPosCal] consider 2 rank data
3989 10:01:57.682567 u2DelayCellTimex100 = 270/100 ps
3990 10:01:57.686006 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3991 10:01:57.689400 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3992 10:01:57.696114 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3993 10:01:57.699540 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3994 10:01:57.703020 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3995 10:01:57.705805 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3996 10:01:57.705889
3997 10:01:57.709490 CA PerBit enable=1, Macro0, CA PI delay=33
3998 10:01:57.709574
3999 10:01:57.712297 [CBTSetCACLKResult] CA Dly = 33
4000 10:01:57.712381 CS Dly: 5 (0~36)
4001 10:01:57.712447
4002 10:01:57.715767 ----->DramcWriteLeveling(PI) begin...
4003 10:01:57.719206 ==
4004 10:01:57.722678 Dram Type= 6, Freq= 0, CH_0, rank 0
4005 10:01:57.725853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4006 10:01:57.725937 ==
4007 10:01:57.729490 Write leveling (Byte 0): 30 => 30
4008 10:01:57.732365 Write leveling (Byte 1): 30 => 30
4009 10:01:57.735496 DramcWriteLeveling(PI) end<-----
4010 10:01:57.735580
4011 10:01:57.735646 ==
4012 10:01:57.739248 Dram Type= 6, Freq= 0, CH_0, rank 0
4013 10:01:57.742369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4014 10:01:57.742480 ==
4015 10:01:57.745638 [Gating] SW mode calibration
4016 10:01:57.752008 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4017 10:01:57.758755 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4018 10:01:57.762556 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4019 10:01:57.765403 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4020 10:01:57.769293 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4021 10:01:57.775693 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4022 10:01:57.778596 0 9 16 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (0 0)
4023 10:01:57.782003 0 9 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4024 10:01:57.788386 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 10:01:57.791809 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 10:01:57.795099 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 10:01:57.802086 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 10:01:57.805415 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 10:01:57.808664 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4030 10:01:57.814817 0 10 16 | B1->B0 | 2f2f 4141 | 1 0 | (0 0) (0 0)
4031 10:01:57.818627 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 10:01:57.822020 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 10:01:57.828474 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 10:01:57.831701 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 10:01:57.835153 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 10:01:57.841537 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 10:01:57.844740 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 10:01:57.847976 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4039 10:01:57.854834 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 10:01:57.858037 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 10:01:57.861155 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 10:01:57.867825 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 10:01:57.871965 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 10:01:57.874548 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 10:01:57.881724 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 10:01:57.884540 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 10:01:57.887808 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 10:01:57.894609 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 10:01:57.897592 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 10:01:57.900923 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 10:01:57.907710 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 10:01:57.910712 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 10:01:57.913759 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 10:01:57.920573 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4055 10:01:57.923829 Total UI for P1: 0, mck2ui 16
4056 10:01:57.927297 best dqsien dly found for B0: ( 0, 13, 14)
4057 10:01:57.930512 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 10:01:57.934109 Total UI for P1: 0, mck2ui 16
4059 10:01:57.937299 best dqsien dly found for B1: ( 0, 13, 16)
4060 10:01:57.940691 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4061 10:01:57.943824 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4062 10:01:57.943908
4063 10:01:57.947548 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4064 10:01:57.950694 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4065 10:01:57.953908 [Gating] SW calibration Done
4066 10:01:57.953991 ==
4067 10:01:57.957595 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 10:01:57.963572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 10:01:57.963656 ==
4070 10:01:57.963723 RX Vref Scan: 0
4071 10:01:57.963787
4072 10:01:57.967142 RX Vref 0 -> 0, step: 1
4073 10:01:57.967243
4074 10:01:57.970171 RX Delay -230 -> 252, step: 16
4075 10:01:57.973781 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4076 10:01:57.977314 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4077 10:01:57.980789 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4078 10:01:57.986699 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4079 10:01:57.990290 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4080 10:01:57.993906 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4081 10:01:57.996765 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4082 10:01:58.003934 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4083 10:01:58.006998 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4084 10:01:58.010338 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4085 10:01:58.013204 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4086 10:01:58.020087 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4087 10:01:58.023511 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4088 10:01:58.026564 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4089 10:01:58.029870 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4090 10:01:58.036777 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4091 10:01:58.036853 ==
4092 10:01:58.039965 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 10:01:58.043866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 10:01:58.043942 ==
4095 10:01:58.044005 DQS Delay:
4096 10:01:58.046262 DQS0 = 0, DQS1 = 0
4097 10:01:58.046334 DQM Delay:
4098 10:01:58.049697 DQM0 = 42, DQM1 = 32
4099 10:01:58.049769 DQ Delay:
4100 10:01:58.053322 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4101 10:01:58.056550 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4102 10:01:58.060118 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4103 10:01:58.063186 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4104 10:01:58.063261
4105 10:01:58.063323
4106 10:01:58.063435 ==
4107 10:01:58.066396 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 10:01:58.070240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 10:01:58.070341 ==
4110 10:01:58.070432
4111 10:01:58.070528
4112 10:01:58.073160 TX Vref Scan disable
4113 10:01:58.076582 == TX Byte 0 ==
4114 10:01:58.080014 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4115 10:01:58.082879 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4116 10:01:58.086625 == TX Byte 1 ==
4117 10:01:58.089722 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4118 10:01:58.093058 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4119 10:01:58.093133 ==
4120 10:01:58.096548 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 10:01:58.103159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 10:01:58.103247 ==
4123 10:01:58.103340
4124 10:01:58.103412
4125 10:01:58.103481 TX Vref Scan disable
4126 10:01:58.106995 == TX Byte 0 ==
4127 10:01:58.110414 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4128 10:01:58.117206 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4129 10:01:58.117282 == TX Byte 1 ==
4130 10:01:58.120392 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4131 10:01:58.127451 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4132 10:01:58.127544
4133 10:01:58.127610 [DATLAT]
4134 10:01:58.127671 Freq=600, CH0 RK0
4135 10:01:58.127730
4136 10:01:58.130963 DATLAT Default: 0x9
4137 10:01:58.131034 0, 0xFFFF, sum = 0
4138 10:01:58.133719 1, 0xFFFF, sum = 0
4139 10:01:58.133792 2, 0xFFFF, sum = 0
4140 10:01:58.137498 3, 0xFFFF, sum = 0
4141 10:01:58.140210 4, 0xFFFF, sum = 0
4142 10:01:58.140291 5, 0xFFFF, sum = 0
4143 10:01:58.143635 6, 0xFFFF, sum = 0
4144 10:01:58.143710 7, 0xFFFF, sum = 0
4145 10:01:58.146976 8, 0x0, sum = 1
4146 10:01:58.147051 9, 0x0, sum = 2
4147 10:01:58.147114 10, 0x0, sum = 3
4148 10:01:58.150113 11, 0x0, sum = 4
4149 10:01:58.150186 best_step = 9
4150 10:01:58.150246
4151 10:01:58.150304 ==
4152 10:01:58.153423 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 10:01:58.160434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 10:01:58.160512 ==
4155 10:01:58.160579 RX Vref Scan: 1
4156 10:01:58.160639
4157 10:01:58.163812 RX Vref 0 -> 0, step: 1
4158 10:01:58.163884
4159 10:01:58.166802 RX Delay -195 -> 252, step: 8
4160 10:01:58.166898
4161 10:01:58.170317 Set Vref, RX VrefLevel [Byte0]: 52
4162 10:01:58.173868 [Byte1]: 50
4163 10:01:58.173945
4164 10:01:58.176579 Final RX Vref Byte 0 = 52 to rank0
4165 10:01:58.180703 Final RX Vref Byte 1 = 50 to rank0
4166 10:01:58.183280 Final RX Vref Byte 0 = 52 to rank1
4167 10:01:58.186730 Final RX Vref Byte 1 = 50 to rank1==
4168 10:01:58.190287 Dram Type= 6, Freq= 0, CH_0, rank 0
4169 10:01:58.193432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 10:01:58.193534 ==
4171 10:01:58.196879 DQS Delay:
4172 10:01:58.196950 DQS0 = 0, DQS1 = 0
4173 10:01:58.200039 DQM Delay:
4174 10:01:58.200108 DQM0 = 42, DQM1 = 34
4175 10:01:58.200169 DQ Delay:
4176 10:01:58.203617 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4177 10:01:58.206779 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4178 10:01:58.210008 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =32
4179 10:01:58.213404 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4180 10:01:58.213502
4181 10:01:58.213591
4182 10:01:58.223839 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f1e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4183 10:01:58.226835 CH0 RK0: MR19=808, MR18=3F1E
4184 10:01:58.233719 CH0_RK0: MR19=0x808, MR18=0x3F1E, DQSOSC=397, MR23=63, INC=166, DEC=110
4185 10:01:58.233822
4186 10:01:58.237073 ----->DramcWriteLeveling(PI) begin...
4187 10:01:58.237150 ==
4188 10:01:58.239684 Dram Type= 6, Freq= 0, CH_0, rank 1
4189 10:01:58.243054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 10:01:58.243151 ==
4191 10:01:58.246660 Write leveling (Byte 0): 31 => 31
4192 10:01:58.249902 Write leveling (Byte 1): 31 => 31
4193 10:01:58.253001 DramcWriteLeveling(PI) end<-----
4194 10:01:58.253085
4195 10:01:58.253147 ==
4196 10:01:58.256378 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 10:01:58.259829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 10:01:58.259899 ==
4199 10:01:58.262818 [Gating] SW mode calibration
4200 10:01:58.269548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4201 10:01:58.276208 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4202 10:01:58.279265 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4203 10:01:58.282694 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4204 10:01:58.289485 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4205 10:01:58.293357 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
4206 10:01:58.296114 0 9 16 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)
4207 10:01:58.302439 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 10:01:58.305881 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 10:01:58.308975 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 10:01:58.315551 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 10:01:58.318871 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 10:01:58.322331 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4213 10:01:58.329208 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
4214 10:01:58.332286 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4215 10:01:58.335707 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 10:01:58.342138 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 10:01:58.345554 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 10:01:58.348998 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 10:01:58.355899 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 10:01:58.359275 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 10:01:58.362430 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 10:01:58.369200 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 10:01:58.372240 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 10:01:58.375685 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 10:01:58.382311 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 10:01:58.385345 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 10:01:58.388629 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 10:01:58.395761 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 10:01:58.398606 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 10:01:58.402247 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 10:01:58.405399 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 10:01:58.412057 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 10:01:58.415604 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 10:01:58.418757 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 10:01:58.425809 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 10:01:58.428707 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4237 10:01:58.432166 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 10:01:58.438716 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 10:01:58.438801 Total UI for P1: 0, mck2ui 16
4240 10:01:58.445564 best dqsien dly found for B0: ( 0, 13, 14)
4241 10:01:58.445649 Total UI for P1: 0, mck2ui 16
4242 10:01:58.452079 best dqsien dly found for B1: ( 0, 13, 14)
4243 10:01:58.455232 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4244 10:01:58.458568 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4245 10:01:58.458680
4246 10:01:58.462096 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4247 10:01:58.465436 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4248 10:01:58.468291 [Gating] SW calibration Done
4249 10:01:58.468375 ==
4250 10:01:58.471590 Dram Type= 6, Freq= 0, CH_0, rank 1
4251 10:01:58.475278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4252 10:01:58.475400 ==
4253 10:01:58.478631 RX Vref Scan: 0
4254 10:01:58.478715
4255 10:01:58.478781 RX Vref 0 -> 0, step: 1
4256 10:01:58.481934
4257 10:01:58.482017 RX Delay -230 -> 252, step: 16
4258 10:01:58.488653 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4259 10:01:58.492433 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4260 10:01:58.495125 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4261 10:01:58.498444 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4262 10:01:58.501947 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4263 10:01:58.508354 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4264 10:01:58.511721 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4265 10:01:58.515080 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4266 10:01:58.518017 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4267 10:01:58.524841 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4268 10:01:58.528627 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4269 10:01:58.531480 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4270 10:01:58.535011 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4271 10:01:58.541222 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4272 10:01:58.544935 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4273 10:01:58.548408 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4274 10:01:58.548524 ==
4275 10:01:58.551247 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 10:01:58.554720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 10:01:58.558138 ==
4278 10:01:58.558222 DQS Delay:
4279 10:01:58.558288 DQS0 = 0, DQS1 = 0
4280 10:01:58.561680 DQM Delay:
4281 10:01:58.561765 DQM0 = 38, DQM1 = 32
4282 10:01:58.564722 DQ Delay:
4283 10:01:58.564806 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4284 10:01:58.568207 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4285 10:01:58.571171 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4286 10:01:58.574623 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4287 10:01:58.578115
4288 10:01:58.578198
4289 10:01:58.578263 ==
4290 10:01:58.581055 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 10:01:58.584423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 10:01:58.584507 ==
4293 10:01:58.584573
4294 10:01:58.584635
4295 10:01:58.587731 TX Vref Scan disable
4296 10:01:58.587815 == TX Byte 0 ==
4297 10:01:58.594155 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4298 10:01:58.597301 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4299 10:01:58.597386 == TX Byte 1 ==
4300 10:01:58.604290 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4301 10:01:58.607538 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4302 10:01:58.607622 ==
4303 10:01:58.610956 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 10:01:58.614159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 10:01:58.614243 ==
4306 10:01:58.614310
4307 10:01:58.614372
4308 10:01:58.617544 TX Vref Scan disable
4309 10:01:58.621027 == TX Byte 0 ==
4310 10:01:58.623901 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4311 10:01:58.630720 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4312 10:01:58.630803 == TX Byte 1 ==
4313 10:01:58.634140 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4314 10:01:58.640344 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4315 10:01:58.640463
4316 10:01:58.640532 [DATLAT]
4317 10:01:58.640594 Freq=600, CH0 RK1
4318 10:01:58.640653
4319 10:01:58.643884 DATLAT Default: 0x9
4320 10:01:58.643973 0, 0xFFFF, sum = 0
4321 10:01:58.647013 1, 0xFFFF, sum = 0
4322 10:01:58.647097 2, 0xFFFF, sum = 0
4323 10:01:58.650941 3, 0xFFFF, sum = 0
4324 10:01:58.653793 4, 0xFFFF, sum = 0
4325 10:01:58.653877 5, 0xFFFF, sum = 0
4326 10:01:58.657057 6, 0xFFFF, sum = 0
4327 10:01:58.657140 7, 0xFFFF, sum = 0
4328 10:01:58.660651 8, 0x0, sum = 1
4329 10:01:58.660734 9, 0x0, sum = 2
4330 10:01:58.660800 10, 0x0, sum = 3
4331 10:01:58.663581 11, 0x0, sum = 4
4332 10:01:58.663664 best_step = 9
4333 10:01:58.663729
4334 10:01:58.663789 ==
4335 10:01:58.667299 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 10:01:58.673591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 10:01:58.673673 ==
4338 10:01:58.673738 RX Vref Scan: 0
4339 10:01:58.673797
4340 10:01:58.676928 RX Vref 0 -> 0, step: 1
4341 10:01:58.677010
4342 10:01:58.680424 RX Delay -179 -> 252, step: 8
4343 10:01:58.683847 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4344 10:01:58.690091 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4345 10:01:58.693804 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4346 10:01:58.696957 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4347 10:01:58.700185 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4348 10:01:58.707243 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4349 10:01:58.710346 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4350 10:01:58.713647 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4351 10:01:58.716689 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4352 10:01:58.720043 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4353 10:01:58.727145 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4354 10:01:58.730317 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4355 10:01:58.733176 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4356 10:01:58.736640 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4357 10:01:58.743267 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4358 10:01:58.747001 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4359 10:01:58.747078 ==
4360 10:01:58.749805 Dram Type= 6, Freq= 0, CH_0, rank 1
4361 10:01:58.753567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 10:01:58.753643 ==
4363 10:01:58.756904 DQS Delay:
4364 10:01:58.756977 DQS0 = 0, DQS1 = 0
4365 10:01:58.757053 DQM Delay:
4366 10:01:58.759826 DQM0 = 39, DQM1 = 33
4367 10:01:58.759908 DQ Delay:
4368 10:01:58.763355 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4369 10:01:58.766739 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4370 10:01:58.769955 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4371 10:01:58.773147 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4372 10:01:58.773221
4373 10:01:58.773283
4374 10:01:58.782821 [DQSOSCAuto] RK1, (LSB)MR18= 0x4426, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4375 10:01:58.785985 CH0 RK1: MR19=808, MR18=4426
4376 10:01:58.792953 CH0_RK1: MR19=0x808, MR18=0x4426, DQSOSC=396, MR23=63, INC=167, DEC=111
4377 10:01:58.793031 [RxdqsGatingPostProcess] freq 600
4378 10:01:58.799241 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4379 10:01:58.802619 Pre-setting of DQS Precalculation
4380 10:01:58.805885 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4381 10:01:58.809637 ==
4382 10:01:58.809721 Dram Type= 6, Freq= 0, CH_1, rank 0
4383 10:01:58.815878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 10:01:58.815959 ==
4385 10:01:58.818922 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4386 10:01:58.825853 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4387 10:01:58.829432 [CA 0] Center 35 (5~65) winsize 61
4388 10:01:58.832732 [CA 1] Center 35 (5~66) winsize 62
4389 10:01:58.836423 [CA 2] Center 34 (4~65) winsize 62
4390 10:01:58.839796 [CA 3] Center 34 (3~65) winsize 63
4391 10:01:58.842788 [CA 4] Center 33 (3~64) winsize 62
4392 10:01:58.846213 [CA 5] Center 33 (3~64) winsize 62
4393 10:01:58.846284
4394 10:01:58.849341 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4395 10:01:58.849412
4396 10:01:58.852965 [CATrainingPosCal] consider 1 rank data
4397 10:01:58.855948 u2DelayCellTimex100 = 270/100 ps
4398 10:01:58.859428 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4399 10:01:58.866262 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4400 10:01:58.869237 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4401 10:01:58.872636 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4402 10:01:58.875866 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4403 10:01:58.879693 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4404 10:01:58.879768
4405 10:01:58.882593 CA PerBit enable=1, Macro0, CA PI delay=33
4406 10:01:58.882662
4407 10:01:58.886193 [CBTSetCACLKResult] CA Dly = 33
4408 10:01:58.886261 CS Dly: 4 (0~35)
4409 10:01:58.889242 ==
4410 10:01:58.889313 Dram Type= 6, Freq= 0, CH_1, rank 1
4411 10:01:58.896338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 10:01:58.896411 ==
4413 10:01:58.899416 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4414 10:01:58.905720 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4415 10:01:58.909488 [CA 0] Center 35 (5~66) winsize 62
4416 10:01:58.912728 [CA 1] Center 36 (6~66) winsize 61
4417 10:01:58.916600 [CA 2] Center 34 (4~65) winsize 62
4418 10:01:58.919965 [CA 3] Center 33 (3~64) winsize 62
4419 10:01:58.923017 [CA 4] Center 34 (3~65) winsize 63
4420 10:01:58.926183 [CA 5] Center 33 (3~64) winsize 62
4421 10:01:58.926295
4422 10:01:58.929963 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4423 10:01:58.930066
4424 10:01:58.932989 [CATrainingPosCal] consider 2 rank data
4425 10:01:58.935980 u2DelayCellTimex100 = 270/100 ps
4426 10:01:58.939687 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4427 10:01:58.943133 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4428 10:01:58.949532 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4429 10:01:58.953375 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4430 10:01:58.955896 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4431 10:01:58.959247 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4432 10:01:58.959343
4433 10:01:58.963050 CA PerBit enable=1, Macro0, CA PI delay=33
4434 10:01:58.963157
4435 10:01:58.965933 [CBTSetCACLKResult] CA Dly = 33
4436 10:01:58.966005 CS Dly: 5 (0~37)
4437 10:01:58.966066
4438 10:01:58.969281 ----->DramcWriteLeveling(PI) begin...
4439 10:01:58.972871 ==
4440 10:01:58.976077 Dram Type= 6, Freq= 0, CH_1, rank 0
4441 10:01:58.979250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 10:01:58.979355 ==
4443 10:01:58.982659 Write leveling (Byte 0): 29 => 29
4444 10:01:58.986103 Write leveling (Byte 1): 29 => 29
4445 10:01:58.989496 DramcWriteLeveling(PI) end<-----
4446 10:01:58.989570
4447 10:01:58.989631 ==
4448 10:01:58.993248 Dram Type= 6, Freq= 0, CH_1, rank 0
4449 10:01:58.996210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 10:01:58.996281 ==
4451 10:01:58.999600 [Gating] SW mode calibration
4452 10:01:59.006516 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4453 10:01:59.009372 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4454 10:01:59.015895 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4455 10:01:59.019566 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4456 10:01:59.023056 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4457 10:01:59.029531 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4458 10:01:59.032546 0 9 16 | B1->B0 | 2d2d 2525 | 0 0 | (1 1) (0 0)
4459 10:01:59.036148 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 10:01:59.042951 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4461 10:01:59.046182 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 10:01:59.049382 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4463 10:01:59.056171 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 10:01:59.059295 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 10:01:59.062712 0 10 12 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
4466 10:01:59.069429 0 10 16 | B1->B0 | 3c3c 4141 | 0 0 | (0 0) (0 0)
4467 10:01:59.072295 0 10 20 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
4468 10:01:59.075644 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 10:01:59.082695 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 10:01:59.085597 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 10:01:59.089127 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 10:01:59.096065 0 11 8 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
4473 10:01:59.099201 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 10:01:59.102616 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4475 10:01:59.108882 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 10:01:59.112397 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 10:01:59.115704 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 10:01:59.122422 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 10:01:59.125675 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 10:01:59.129310 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 10:01:59.132642 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 10:01:59.139153 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 10:01:59.142421 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 10:01:59.145572 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 10:01:59.152453 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 10:01:59.155598 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 10:01:59.158931 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 10:01:59.165781 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 10:01:59.169191 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4490 10:01:59.172170 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 10:01:59.175545 Total UI for P1: 0, mck2ui 16
4492 10:01:59.178877 best dqsien dly found for B0: ( 0, 13, 12)
4493 10:01:59.182398 Total UI for P1: 0, mck2ui 16
4494 10:01:59.185830 best dqsien dly found for B1: ( 0, 13, 12)
4495 10:01:59.189006 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4496 10:01:59.192555 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4497 10:01:59.192624
4498 10:01:59.198871 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4499 10:01:59.202307 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4500 10:01:59.202376 [Gating] SW calibration Done
4501 10:01:59.205815 ==
4502 10:01:59.209106 Dram Type= 6, Freq= 0, CH_1, rank 0
4503 10:01:59.212600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4504 10:01:59.212675 ==
4505 10:01:59.212737 RX Vref Scan: 0
4506 10:01:59.212793
4507 10:01:59.216067 RX Vref 0 -> 0, step: 1
4508 10:01:59.216132
4509 10:01:59.219039 RX Delay -230 -> 252, step: 16
4510 10:01:59.222626 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4511 10:01:59.226106 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4512 10:01:59.232670 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4513 10:01:59.235613 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4514 10:01:59.238903 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4515 10:01:59.242132 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4516 10:01:59.249096 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4517 10:01:59.251968 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4518 10:01:59.255879 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4519 10:01:59.258769 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4520 10:01:59.262585 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4521 10:01:59.268773 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4522 10:01:59.272354 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4523 10:01:59.275261 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4524 10:01:59.278624 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4525 10:01:59.285281 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4526 10:01:59.285355 ==
4527 10:01:59.288782 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 10:01:59.292113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 10:01:59.292189 ==
4530 10:01:59.292251 DQS Delay:
4531 10:01:59.295412 DQS0 = 0, DQS1 = 0
4532 10:01:59.295485 DQM Delay:
4533 10:01:59.298629 DQM0 = 43, DQM1 = 36
4534 10:01:59.298699 DQ Delay:
4535 10:01:59.302162 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4536 10:01:59.305694 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4537 10:01:59.308585 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4538 10:01:59.312018 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4539 10:01:59.312093
4540 10:01:59.312154
4541 10:01:59.312213 ==
4542 10:01:59.315343 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 10:01:59.318965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 10:01:59.319062 ==
4545 10:01:59.322398
4546 10:01:59.322470
4547 10:01:59.322529 TX Vref Scan disable
4548 10:01:59.325312 == TX Byte 0 ==
4549 10:01:59.328401 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4550 10:01:59.332174 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4551 10:01:59.334970 == TX Byte 1 ==
4552 10:01:59.338633 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4553 10:01:59.341900 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4554 10:01:59.345042 ==
4555 10:01:59.345135 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 10:01:59.351861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 10:01:59.351946 ==
4558 10:01:59.352012
4559 10:01:59.352074
4560 10:01:59.355063 TX Vref Scan disable
4561 10:01:59.355145 == TX Byte 0 ==
4562 10:01:59.361620 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4563 10:01:59.365102 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4564 10:01:59.365185 == TX Byte 1 ==
4565 10:01:59.372055 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4566 10:01:59.375221 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4567 10:01:59.375305
4568 10:01:59.375405 [DATLAT]
4569 10:01:59.378719 Freq=600, CH1 RK0
4570 10:01:59.378802
4571 10:01:59.378867 DATLAT Default: 0x9
4572 10:01:59.381646 0, 0xFFFF, sum = 0
4573 10:01:59.381730 1, 0xFFFF, sum = 0
4574 10:01:59.385130 2, 0xFFFF, sum = 0
4575 10:01:59.385214 3, 0xFFFF, sum = 0
4576 10:01:59.388442 4, 0xFFFF, sum = 0
4577 10:01:59.388526 5, 0xFFFF, sum = 0
4578 10:01:59.391554 6, 0xFFFF, sum = 0
4579 10:01:59.391638 7, 0xFFFF, sum = 0
4580 10:01:59.395266 8, 0x0, sum = 1
4581 10:01:59.395374 9, 0x0, sum = 2
4582 10:01:59.398730 10, 0x0, sum = 3
4583 10:01:59.398814 11, 0x0, sum = 4
4584 10:01:59.401721 best_step = 9
4585 10:01:59.401804
4586 10:01:59.401869 ==
4587 10:01:59.405123 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 10:01:59.408154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 10:01:59.408238 ==
4590 10:01:59.411544 RX Vref Scan: 1
4591 10:01:59.411626
4592 10:01:59.411692 RX Vref 0 -> 0, step: 1
4593 10:01:59.411753
4594 10:01:59.415023 RX Delay -179 -> 252, step: 8
4595 10:01:59.415106
4596 10:01:59.418548 Set Vref, RX VrefLevel [Byte0]: 57
4597 10:01:59.421339 [Byte1]: 52
4598 10:01:59.425451
4599 10:01:59.425533 Final RX Vref Byte 0 = 57 to rank0
4600 10:01:59.429072 Final RX Vref Byte 1 = 52 to rank0
4601 10:01:59.431619 Final RX Vref Byte 0 = 57 to rank1
4602 10:01:59.435237 Final RX Vref Byte 1 = 52 to rank1==
4603 10:01:59.438475 Dram Type= 6, Freq= 0, CH_1, rank 0
4604 10:01:59.445322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 10:01:59.445406 ==
4606 10:01:59.445472 DQS Delay:
4607 10:01:59.445532 DQS0 = 0, DQS1 = 0
4608 10:01:59.448638 DQM Delay:
4609 10:01:59.448721 DQM0 = 41, DQM1 = 32
4610 10:01:59.451681 DQ Delay:
4611 10:01:59.455220 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =44
4612 10:01:59.458277 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4613 10:01:59.462095 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24
4614 10:01:59.465254 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4615 10:01:59.465337
4616 10:01:59.465402
4617 10:01:59.472029 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f05, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 397 ps
4618 10:01:59.475268 CH1 RK0: MR19=808, MR18=3F05
4619 10:01:59.481969 CH1_RK0: MR19=0x808, MR18=0x3F05, DQSOSC=397, MR23=63, INC=166, DEC=110
4620 10:01:59.482053
4621 10:01:59.485300 ----->DramcWriteLeveling(PI) begin...
4622 10:01:59.485401 ==
4623 10:01:59.488413 Dram Type= 6, Freq= 0, CH_1, rank 1
4624 10:01:59.491762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4625 10:01:59.491846 ==
4626 10:01:59.495344 Write leveling (Byte 0): 30 => 30
4627 10:01:59.498589 Write leveling (Byte 1): 29 => 29
4628 10:01:59.502176 DramcWriteLeveling(PI) end<-----
4629 10:01:59.502259
4630 10:01:59.502325 ==
4631 10:01:59.505240 Dram Type= 6, Freq= 0, CH_1, rank 1
4632 10:01:59.509095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 10:01:59.509187 ==
4634 10:01:59.512012 [Gating] SW mode calibration
4635 10:01:59.518320 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4636 10:01:59.525277 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4637 10:01:59.528356 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4638 10:01:59.531620 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4639 10:01:59.538212 0 9 8 | B1->B0 | 3534 3434 | 1 1 | (1 1) (1 1)
4640 10:01:59.541705 0 9 12 | B1->B0 | 2f2f 2828 | 0 1 | (0 0) (1 0)
4641 10:01:59.544996 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4642 10:01:59.551274 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4643 10:01:59.554750 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 10:01:59.558456 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 10:01:59.564685 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4646 10:01:59.567944 0 10 4 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
4647 10:01:59.572000 0 10 8 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
4648 10:01:59.578164 0 10 12 | B1->B0 | 3030 3f3f | 0 0 | (0 0) (0 0)
4649 10:01:59.581313 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 10:01:59.584835 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 10:01:59.591226 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 10:01:59.594867 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 10:01:59.598110 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 10:01:59.604812 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 10:01:59.608158 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4656 10:01:59.611493 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4657 10:01:59.617713 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4658 10:01:59.621616 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 10:01:59.624782 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 10:01:59.631627 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 10:01:59.634793 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 10:01:59.637614 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 10:01:59.644553 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 10:01:59.647923 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 10:01:59.651193 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 10:01:59.657583 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 10:01:59.660625 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 10:01:59.664193 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 10:01:59.671114 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 10:01:59.674195 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 10:01:59.677411 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 10:01:59.684308 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4673 10:01:59.684393 Total UI for P1: 0, mck2ui 16
4674 10:01:59.687209 best dqsien dly found for B0: ( 0, 13, 10)
4675 10:01:59.693792 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 10:01:59.697161 Total UI for P1: 0, mck2ui 16
4677 10:01:59.700674 best dqsien dly found for B1: ( 0, 13, 12)
4678 10:01:59.704068 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4679 10:01:59.707249 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4680 10:01:59.707333
4681 10:01:59.710502 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4682 10:01:59.714023 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4683 10:01:59.717497 [Gating] SW calibration Done
4684 10:01:59.717580 ==
4685 10:01:59.720390 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 10:01:59.723948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 10:01:59.724034 ==
4688 10:01:59.727288 RX Vref Scan: 0
4689 10:01:59.727396
4690 10:01:59.731136 RX Vref 0 -> 0, step: 1
4691 10:01:59.731247
4692 10:01:59.734226 RX Delay -230 -> 252, step: 16
4693 10:01:59.737029 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4694 10:01:59.740442 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4695 10:01:59.743793 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4696 10:01:59.746932 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4697 10:01:59.753920 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4698 10:01:59.757098 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4699 10:01:59.760663 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4700 10:01:59.764055 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4701 10:01:59.770309 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4702 10:01:59.773501 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4703 10:01:59.777468 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4704 10:01:59.780500 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4705 10:01:59.786985 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4706 10:01:59.790105 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4707 10:01:59.793689 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4708 10:01:59.797235 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4709 10:01:59.797363 ==
4710 10:01:59.800320 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 10:01:59.806803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 10:01:59.806916 ==
4713 10:01:59.807026 DQS Delay:
4714 10:01:59.807119 DQS0 = 0, DQS1 = 0
4715 10:01:59.809981 DQM Delay:
4716 10:01:59.810080 DQM0 = 42, DQM1 = 38
4717 10:01:59.813777 DQ Delay:
4718 10:01:59.816990 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4719 10:01:59.820006 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4720 10:01:59.820089 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4721 10:01:59.826814 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4722 10:01:59.826898
4723 10:01:59.826965
4724 10:01:59.827027 ==
4725 10:01:59.830271 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 10:01:59.833668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 10:01:59.833747 ==
4728 10:01:59.833810
4729 10:01:59.833870
4730 10:01:59.836520 TX Vref Scan disable
4731 10:01:59.836593 == TX Byte 0 ==
4732 10:01:59.843246 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4733 10:01:59.846532 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4734 10:01:59.846646 == TX Byte 1 ==
4735 10:01:59.853167 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4736 10:01:59.856736 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4737 10:01:59.856842 ==
4738 10:01:59.860548 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 10:01:59.863305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 10:01:59.863435 ==
4741 10:01:59.863512
4742 10:01:59.866656
4743 10:01:59.866759 TX Vref Scan disable
4744 10:01:59.869672 == TX Byte 0 ==
4745 10:01:59.873058 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4746 10:01:59.876473 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4747 10:01:59.880018 == TX Byte 1 ==
4748 10:01:59.883577 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4749 10:01:59.889947 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4750 10:01:59.890073
4751 10:01:59.890185 [DATLAT]
4752 10:01:59.890310 Freq=600, CH1 RK1
4753 10:01:59.890432
4754 10:01:59.893147 DATLAT Default: 0x9
4755 10:01:59.893222 0, 0xFFFF, sum = 0
4756 10:01:59.896685 1, 0xFFFF, sum = 0
4757 10:01:59.896787 2, 0xFFFF, sum = 0
4758 10:01:59.900057 3, 0xFFFF, sum = 0
4759 10:01:59.900141 4, 0xFFFF, sum = 0
4760 10:01:59.903131 5, 0xFFFF, sum = 0
4761 10:01:59.906430 6, 0xFFFF, sum = 0
4762 10:01:59.906561 7, 0xFFFF, sum = 0
4763 10:01:59.906657 8, 0x0, sum = 1
4764 10:01:59.909971 9, 0x0, sum = 2
4765 10:01:59.910090 10, 0x0, sum = 3
4766 10:01:59.913369 11, 0x0, sum = 4
4767 10:01:59.913483 best_step = 9
4768 10:01:59.913579
4769 10:01:59.913669 ==
4770 10:01:59.916534 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 10:01:59.923296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 10:01:59.923443 ==
4773 10:01:59.923544 RX Vref Scan: 0
4774 10:01:59.923639
4775 10:01:59.926905 RX Vref 0 -> 0, step: 1
4776 10:01:59.927040
4777 10:01:59.929920 RX Delay -179 -> 252, step: 8
4778 10:01:59.932789 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4779 10:01:59.939792 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4780 10:01:59.942870 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4781 10:01:59.946230 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4782 10:01:59.949794 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4783 10:01:59.953223 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4784 10:01:59.960115 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4785 10:01:59.962743 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4786 10:01:59.966059 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4787 10:01:59.969708 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4788 10:01:59.975913 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4789 10:01:59.979888 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4790 10:01:59.982521 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4791 10:01:59.985944 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4792 10:01:59.992330 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4793 10:01:59.995677 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4794 10:01:59.995790 ==
4795 10:01:59.999402 Dram Type= 6, Freq= 0, CH_1, rank 1
4796 10:02:00.002622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4797 10:02:00.002732 ==
4798 10:02:00.005737 DQS Delay:
4799 10:02:00.005837 DQS0 = 0, DQS1 = 0
4800 10:02:00.005933 DQM Delay:
4801 10:02:00.009076 DQM0 = 39, DQM1 = 33
4802 10:02:00.009162 DQ Delay:
4803 10:02:00.012558 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4804 10:02:00.015827 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4805 10:02:00.018702 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4806 10:02:00.022356 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4807 10:02:00.022473
4808 10:02:00.022568
4809 10:02:00.032524 [DQSOSCAuto] RK1, (LSB)MR18= 0x3140, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4810 10:02:00.035562 CH1 RK1: MR19=808, MR18=3140
4811 10:02:00.038796 CH1_RK1: MR19=0x808, MR18=0x3140, DQSOSC=397, MR23=63, INC=166, DEC=110
4812 10:02:00.042289 [RxdqsGatingPostProcess] freq 600
4813 10:02:00.049088 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4814 10:02:00.052541 Pre-setting of DQS Precalculation
4815 10:02:00.055385 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4816 10:02:00.062212 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4817 10:02:00.072485 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4818 10:02:00.072586
4819 10:02:00.072654
4820 10:02:00.075615 [Calibration Summary] 1200 Mbps
4821 10:02:00.075737 CH 0, Rank 0
4822 10:02:00.078927 SW Impedance : PASS
4823 10:02:00.079011 DUTY Scan : NO K
4824 10:02:00.082294 ZQ Calibration : PASS
4825 10:02:00.085655 Jitter Meter : NO K
4826 10:02:00.085738 CBT Training : PASS
4827 10:02:00.088794 Write leveling : PASS
4828 10:02:00.092402 RX DQS gating : PASS
4829 10:02:00.092517 RX DQ/DQS(RDDQC) : PASS
4830 10:02:00.095782 TX DQ/DQS : PASS
4831 10:02:00.095909 RX DATLAT : PASS
4832 10:02:00.098759 RX DQ/DQS(Engine): PASS
4833 10:02:00.102136 TX OE : NO K
4834 10:02:00.102211 All Pass.
4835 10:02:00.102288
4836 10:02:00.102353 CH 0, Rank 1
4837 10:02:00.105137 SW Impedance : PASS
4838 10:02:00.108713 DUTY Scan : NO K
4839 10:02:00.108786 ZQ Calibration : PASS
4840 10:02:00.111968 Jitter Meter : NO K
4841 10:02:00.115447 CBT Training : PASS
4842 10:02:00.115526 Write leveling : PASS
4843 10:02:00.119001 RX DQS gating : PASS
4844 10:02:00.121801 RX DQ/DQS(RDDQC) : PASS
4845 10:02:00.121891 TX DQ/DQS : PASS
4846 10:02:00.125139 RX DATLAT : PASS
4847 10:02:00.128542 RX DQ/DQS(Engine): PASS
4848 10:02:00.128626 TX OE : NO K
4849 10:02:00.131835 All Pass.
4850 10:02:00.131909
4851 10:02:00.131979 CH 1, Rank 0
4852 10:02:00.135260 SW Impedance : PASS
4853 10:02:00.135374 DUTY Scan : NO K
4854 10:02:00.138588 ZQ Calibration : PASS
4855 10:02:00.142159 Jitter Meter : NO K
4856 10:02:00.142291 CBT Training : PASS
4857 10:02:00.144870 Write leveling : PASS
4858 10:02:00.148866 RX DQS gating : PASS
4859 10:02:00.148943 RX DQ/DQS(RDDQC) : PASS
4860 10:02:00.151858 TX DQ/DQS : PASS
4861 10:02:00.155012 RX DATLAT : PASS
4862 10:02:00.155094 RX DQ/DQS(Engine): PASS
4863 10:02:00.158269 TX OE : NO K
4864 10:02:00.158349 All Pass.
4865 10:02:00.158412
4866 10:02:00.161754 CH 1, Rank 1
4867 10:02:00.161836 SW Impedance : PASS
4868 10:02:00.165021 DUTY Scan : NO K
4869 10:02:00.165093 ZQ Calibration : PASS
4870 10:02:00.167957 Jitter Meter : NO K
4871 10:02:00.171916 CBT Training : PASS
4872 10:02:00.172029 Write leveling : PASS
4873 10:02:00.175016 RX DQS gating : PASS
4874 10:02:00.177963 RX DQ/DQS(RDDQC) : PASS
4875 10:02:00.178041 TX DQ/DQS : PASS
4876 10:02:00.181808 RX DATLAT : PASS
4877 10:02:00.184554 RX DQ/DQS(Engine): PASS
4878 10:02:00.184635 TX OE : NO K
4879 10:02:00.188090 All Pass.
4880 10:02:00.188168
4881 10:02:00.188239 DramC Write-DBI off
4882 10:02:00.191474 PER_BANK_REFRESH: Hybrid Mode
4883 10:02:00.191576 TX_TRACKING: ON
4884 10:02:00.201424 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4885 10:02:00.204773 [FAST_K] Save calibration result to emmc
4886 10:02:00.207771 dramc_set_vcore_voltage set vcore to 662500
4887 10:02:00.211611 Read voltage for 933, 3
4888 10:02:00.211689 Vio18 = 0
4889 10:02:00.214673 Vcore = 662500
4890 10:02:00.214784 Vdram = 0
4891 10:02:00.214888 Vddq = 0
4892 10:02:00.217941 Vmddr = 0
4893 10:02:00.221302 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4894 10:02:00.227999 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4895 10:02:00.228079 MEM_TYPE=3, freq_sel=17
4896 10:02:00.231533 sv_algorithm_assistance_LP4_1600
4897 10:02:00.238091 ============ PULL DRAM RESETB DOWN ============
4898 10:02:00.240984 ========== PULL DRAM RESETB DOWN end =========
4899 10:02:00.244509 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4900 10:02:00.247814 ===================================
4901 10:02:00.250972 LPDDR4 DRAM CONFIGURATION
4902 10:02:00.254583 ===================================
4903 10:02:00.254696 EX_ROW_EN[0] = 0x0
4904 10:02:00.257652 EX_ROW_EN[1] = 0x0
4905 10:02:00.261105 LP4Y_EN = 0x0
4906 10:02:00.261180 WORK_FSP = 0x0
4907 10:02:00.264176 WL = 0x3
4908 10:02:00.264250 RL = 0x3
4909 10:02:00.267636 BL = 0x2
4910 10:02:00.267711 RPST = 0x0
4911 10:02:00.271361 RD_PRE = 0x0
4912 10:02:00.271468 WR_PRE = 0x1
4913 10:02:00.274863 WR_PST = 0x0
4914 10:02:00.274937 DBI_WR = 0x0
4915 10:02:00.277564 DBI_RD = 0x0
4916 10:02:00.277634 OTF = 0x1
4917 10:02:00.281191 ===================================
4918 10:02:00.284545 ===================================
4919 10:02:00.287880 ANA top config
4920 10:02:00.290724 ===================================
4921 10:02:00.290799 DLL_ASYNC_EN = 0
4922 10:02:00.294144 ALL_SLAVE_EN = 1
4923 10:02:00.297425 NEW_RANK_MODE = 1
4924 10:02:00.301064 DLL_IDLE_MODE = 1
4925 10:02:00.304151 LP45_APHY_COMB_EN = 1
4926 10:02:00.304242 TX_ODT_DIS = 1
4927 10:02:00.307435 NEW_8X_MODE = 1
4928 10:02:00.310959 ===================================
4929 10:02:00.314164 ===================================
4930 10:02:00.317684 data_rate = 1866
4931 10:02:00.321189 CKR = 1
4932 10:02:00.323895 DQ_P2S_RATIO = 8
4933 10:02:00.327454 ===================================
4934 10:02:00.327536 CA_P2S_RATIO = 8
4935 10:02:00.330713 DQ_CA_OPEN = 0
4936 10:02:00.334101 DQ_SEMI_OPEN = 0
4937 10:02:00.337223 CA_SEMI_OPEN = 0
4938 10:02:00.340845 CA_FULL_RATE = 0
4939 10:02:00.344054 DQ_CKDIV4_EN = 1
4940 10:02:00.344143 CA_CKDIV4_EN = 1
4941 10:02:00.347465 CA_PREDIV_EN = 0
4942 10:02:00.350909 PH8_DLY = 0
4943 10:02:00.353788 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4944 10:02:00.357315 DQ_AAMCK_DIV = 4
4945 10:02:00.360455 CA_AAMCK_DIV = 4
4946 10:02:00.360563 CA_ADMCK_DIV = 4
4947 10:02:00.363787 DQ_TRACK_CA_EN = 0
4948 10:02:00.367284 CA_PICK = 933
4949 10:02:00.370194 CA_MCKIO = 933
4950 10:02:00.373817 MCKIO_SEMI = 0
4951 10:02:00.377151 PLL_FREQ = 3732
4952 10:02:00.380014 DQ_UI_PI_RATIO = 32
4953 10:02:00.383586 CA_UI_PI_RATIO = 0
4954 10:02:00.386941 ===================================
4955 10:02:00.390582 ===================================
4956 10:02:00.390659 memory_type:LPDDR4
4957 10:02:00.393690 GP_NUM : 10
4958 10:02:00.393795 SRAM_EN : 1
4959 10:02:00.397034 MD32_EN : 0
4960 10:02:00.400254 ===================================
4961 10:02:00.403807 [ANA_INIT] >>>>>>>>>>>>>>
4962 10:02:00.407178 <<<<<< [CONFIGURE PHASE]: ANA_TX
4963 10:02:00.410487 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4964 10:02:00.413266 ===================================
4965 10:02:00.416681 data_rate = 1866,PCW = 0X8f00
4966 10:02:00.416764 ===================================
4967 10:02:00.423094 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4968 10:02:00.426683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4969 10:02:00.433328 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4970 10:02:00.436818 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4971 10:02:00.439813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4972 10:02:00.443665 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4973 10:02:00.446513 [ANA_INIT] flow start
4974 10:02:00.449661 [ANA_INIT] PLL >>>>>>>>
4975 10:02:00.449744 [ANA_INIT] PLL <<<<<<<<
4976 10:02:00.452898 [ANA_INIT] MIDPI >>>>>>>>
4977 10:02:00.456227 [ANA_INIT] MIDPI <<<<<<<<
4978 10:02:00.456311 [ANA_INIT] DLL >>>>>>>>
4979 10:02:00.459747 [ANA_INIT] flow end
4980 10:02:00.462950 ============ LP4 DIFF to SE enter ============
4981 10:02:00.470186 ============ LP4 DIFF to SE exit ============
4982 10:02:00.470271 [ANA_INIT] <<<<<<<<<<<<<
4983 10:02:00.473163 [Flow] Enable top DCM control >>>>>
4984 10:02:00.476341 [Flow] Enable top DCM control <<<<<
4985 10:02:00.479504 Enable DLL master slave shuffle
4986 10:02:00.486504 ==============================================================
4987 10:02:00.486587 Gating Mode config
4988 10:02:00.492935 ==============================================================
4989 10:02:00.496075 Config description:
4990 10:02:00.502445 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4991 10:02:00.509672 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4992 10:02:00.515988 SELPH_MODE 0: By rank 1: By Phase
4993 10:02:00.522521 ==============================================================
4994 10:02:00.525909 GAT_TRACK_EN = 1
4995 10:02:00.525993 RX_GATING_MODE = 2
4996 10:02:00.529154 RX_GATING_TRACK_MODE = 2
4997 10:02:00.532204 SELPH_MODE = 1
4998 10:02:00.535687 PICG_EARLY_EN = 1
4999 10:02:00.538976 VALID_LAT_VALUE = 1
5000 10:02:00.545957 ==============================================================
5001 10:02:00.549103 Enter into Gating configuration >>>>
5002 10:02:00.552846 Exit from Gating configuration <<<<
5003 10:02:00.555720 Enter into DVFS_PRE_config >>>>>
5004 10:02:00.565781 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5005 10:02:00.568690 Exit from DVFS_PRE_config <<<<<
5006 10:02:00.572368 Enter into PICG configuration >>>>
5007 10:02:00.575296 Exit from PICG configuration <<<<
5008 10:02:00.579222 [RX_INPUT] configuration >>>>>
5009 10:02:00.582591 [RX_INPUT] configuration <<<<<
5010 10:02:00.585621 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5011 10:02:00.592583 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5012 10:02:00.598576 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5013 10:02:00.602225 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5014 10:02:00.608532 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5015 10:02:00.615302 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5016 10:02:00.618272 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5017 10:02:00.625481 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5018 10:02:00.628710 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5019 10:02:00.631690 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5020 10:02:00.635220 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5021 10:02:00.641661 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5022 10:02:00.645223 ===================================
5023 10:02:00.645307 LPDDR4 DRAM CONFIGURATION
5024 10:02:00.649218 ===================================
5025 10:02:00.652046 EX_ROW_EN[0] = 0x0
5026 10:02:00.655208 EX_ROW_EN[1] = 0x0
5027 10:02:00.655318 LP4Y_EN = 0x0
5028 10:02:00.658417 WORK_FSP = 0x0
5029 10:02:00.658500 WL = 0x3
5030 10:02:00.661338 RL = 0x3
5031 10:02:00.661421 BL = 0x2
5032 10:02:00.665000 RPST = 0x0
5033 10:02:00.665083 RD_PRE = 0x0
5034 10:02:00.668014 WR_PRE = 0x1
5035 10:02:00.668096 WR_PST = 0x0
5036 10:02:00.671835 DBI_WR = 0x0
5037 10:02:00.671919 DBI_RD = 0x0
5038 10:02:00.674866 OTF = 0x1
5039 10:02:00.678587 ===================================
5040 10:02:00.681321 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5041 10:02:00.684596 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5042 10:02:00.691479 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5043 10:02:00.694999 ===================================
5044 10:02:00.695082 LPDDR4 DRAM CONFIGURATION
5045 10:02:00.697913 ===================================
5046 10:02:00.701718 EX_ROW_EN[0] = 0x10
5047 10:02:00.704458 EX_ROW_EN[1] = 0x0
5048 10:02:00.704541 LP4Y_EN = 0x0
5049 10:02:00.708295 WORK_FSP = 0x0
5050 10:02:00.708379 WL = 0x3
5051 10:02:00.711216 RL = 0x3
5052 10:02:00.711333 BL = 0x2
5053 10:02:00.715051 RPST = 0x0
5054 10:02:00.715135 RD_PRE = 0x0
5055 10:02:00.717958 WR_PRE = 0x1
5056 10:02:00.718041 WR_PST = 0x0
5057 10:02:00.721237 DBI_WR = 0x0
5058 10:02:00.721321 DBI_RD = 0x0
5059 10:02:00.724911 OTF = 0x1
5060 10:02:00.727815 ===================================
5061 10:02:00.734619 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5062 10:02:00.737804 nWR fixed to 30
5063 10:02:00.737888 [ModeRegInit_LP4] CH0 RK0
5064 10:02:00.741365 [ModeRegInit_LP4] CH0 RK1
5065 10:02:00.744760 [ModeRegInit_LP4] CH1 RK0
5066 10:02:00.747768 [ModeRegInit_LP4] CH1 RK1
5067 10:02:00.747851 match AC timing 9
5068 10:02:00.751439 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5069 10:02:00.754567 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5070 10:02:00.761120 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5071 10:02:00.764620 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5072 10:02:00.772025 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5073 10:02:00.772109 ==
5074 10:02:00.774928 Dram Type= 6, Freq= 0, CH_0, rank 0
5075 10:02:00.778382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5076 10:02:00.778466 ==
5077 10:02:00.784929 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5078 10:02:00.791373 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5079 10:02:00.794493 [CA 0] Center 38 (8~69) winsize 62
5080 10:02:00.797773 [CA 1] Center 38 (7~69) winsize 63
5081 10:02:00.801025 [CA 2] Center 35 (5~66) winsize 62
5082 10:02:00.804601 [CA 3] Center 35 (5~66) winsize 62
5083 10:02:00.807765 [CA 4] Center 34 (4~64) winsize 61
5084 10:02:00.807849 [CA 5] Center 34 (4~64) winsize 61
5085 10:02:00.811265
5086 10:02:00.814089 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5087 10:02:00.814172
5088 10:02:00.817669 [CATrainingPosCal] consider 1 rank data
5089 10:02:00.820968 u2DelayCellTimex100 = 270/100 ps
5090 10:02:00.824030 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5091 10:02:00.828033 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5092 10:02:00.831469 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5093 10:02:00.834239 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5094 10:02:00.837689 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5095 10:02:00.840527 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5096 10:02:00.840609
5097 10:02:00.844634 CA PerBit enable=1, Macro0, CA PI delay=34
5098 10:02:00.847284
5099 10:02:00.847427 [CBTSetCACLKResult] CA Dly = 34
5100 10:02:00.850665 CS Dly: 6 (0~37)
5101 10:02:00.850745 ==
5102 10:02:00.854040 Dram Type= 6, Freq= 0, CH_0, rank 1
5103 10:02:00.857366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 10:02:00.857439 ==
5105 10:02:00.864120 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5106 10:02:00.870719 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5107 10:02:00.874337 [CA 0] Center 38 (8~69) winsize 62
5108 10:02:00.877154 [CA 1] Center 38 (8~69) winsize 62
5109 10:02:00.880641 [CA 2] Center 35 (5~66) winsize 62
5110 10:02:00.883709 [CA 3] Center 35 (5~66) winsize 62
5111 10:02:00.887139 [CA 4] Center 33 (3~64) winsize 62
5112 10:02:00.890584 [CA 5] Center 33 (3~64) winsize 62
5113 10:02:00.890657
5114 10:02:00.893631 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5115 10:02:00.893702
5116 10:02:00.897010 [CATrainingPosCal] consider 2 rank data
5117 10:02:00.900312 u2DelayCellTimex100 = 270/100 ps
5118 10:02:00.903718 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5119 10:02:00.907230 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5120 10:02:00.910474 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5121 10:02:00.913519 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5122 10:02:00.916944 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5123 10:02:00.920208 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5124 10:02:00.920283
5125 10:02:00.927070 CA PerBit enable=1, Macro0, CA PI delay=34
5126 10:02:00.927177
5127 10:02:00.927273 [CBTSetCACLKResult] CA Dly = 34
5128 10:02:00.930479 CS Dly: 7 (0~39)
5129 10:02:00.930578
5130 10:02:00.933753 ----->DramcWriteLeveling(PI) begin...
5131 10:02:00.933829 ==
5132 10:02:00.936720 Dram Type= 6, Freq= 0, CH_0, rank 0
5133 10:02:00.940106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5134 10:02:00.940183 ==
5135 10:02:00.943466 Write leveling (Byte 0): 27 => 27
5136 10:02:00.946829 Write leveling (Byte 1): 26 => 26
5137 10:02:00.950467 DramcWriteLeveling(PI) end<-----
5138 10:02:00.950543
5139 10:02:00.950611 ==
5140 10:02:00.953914 Dram Type= 6, Freq= 0, CH_0, rank 0
5141 10:02:00.960043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5142 10:02:00.960124 ==
5143 10:02:00.960189 [Gating] SW mode calibration
5144 10:02:00.970398 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5145 10:02:00.973342 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5146 10:02:00.977043 0 14 0 | B1->B0 | 2323 2e2e | 1 1 | (1 1) (1 1)
5147 10:02:00.983228 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5148 10:02:00.986868 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 10:02:00.990294 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 10:02:00.996673 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 10:02:01.000163 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 10:02:01.003268 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 10:02:01.010004 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 10:02:01.013315 0 15 0 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 0)
5155 10:02:01.016731 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
5156 10:02:01.023171 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 10:02:01.026374 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 10:02:01.029795 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 10:02:01.036433 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 10:02:01.039716 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 10:02:01.042675 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5162 10:02:01.049614 1 0 0 | B1->B0 | 2f2f 3a3a | 0 0 | (0 0) (0 0)
5163 10:02:01.052848 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 10:02:01.056328 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 10:02:01.062892 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 10:02:01.066195 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 10:02:01.069559 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 10:02:01.076264 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 10:02:01.079469 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 10:02:01.082550 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5171 10:02:01.089896 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5172 10:02:01.092579 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 10:02:01.095963 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 10:02:01.102946 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 10:02:01.105970 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 10:02:01.109226 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 10:02:01.116180 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 10:02:01.119513 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 10:02:01.122653 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 10:02:01.126338 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 10:02:01.132815 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 10:02:01.135693 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 10:02:01.139077 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 10:02:01.145708 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 10:02:01.149335 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5186 10:02:01.152236 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5187 10:02:01.159049 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5188 10:02:01.162200 Total UI for P1: 0, mck2ui 16
5189 10:02:01.165550 best dqsien dly found for B0: ( 1, 2, 30)
5190 10:02:01.169028 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 10:02:01.172065 Total UI for P1: 0, mck2ui 16
5192 10:02:01.175911 best dqsien dly found for B1: ( 1, 3, 4)
5193 10:02:01.178931 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5194 10:02:01.182028 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5195 10:02:01.182139
5196 10:02:01.185632 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5197 10:02:01.189032 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5198 10:02:01.192413 [Gating] SW calibration Done
5199 10:02:01.192507 ==
5200 10:02:01.195323 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 10:02:01.202167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 10:02:01.202253 ==
5203 10:02:01.202339 RX Vref Scan: 0
5204 10:02:01.202420
5205 10:02:01.205538 RX Vref 0 -> 0, step: 1
5206 10:02:01.205623
5207 10:02:01.208762 RX Delay -80 -> 252, step: 8
5208 10:02:01.212260 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5209 10:02:01.215216 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5210 10:02:01.218686 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5211 10:02:01.221981 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5212 10:02:01.228767 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5213 10:02:01.231855 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5214 10:02:01.235216 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5215 10:02:01.238964 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5216 10:02:01.241859 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5217 10:02:01.245159 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5218 10:02:01.251816 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5219 10:02:01.255239 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5220 10:02:01.258352 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5221 10:02:01.261884 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5222 10:02:01.265473 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5223 10:02:01.271750 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5224 10:02:01.271835 ==
5225 10:02:01.274972 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 10:02:01.278915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 10:02:01.279002 ==
5228 10:02:01.279087 DQS Delay:
5229 10:02:01.281486 DQS0 = 0, DQS1 = 0
5230 10:02:01.281571 DQM Delay:
5231 10:02:01.285143 DQM0 = 97, DQM1 = 87
5232 10:02:01.285248 DQ Delay:
5233 10:02:01.288283 DQ0 =95, DQ1 =103, DQ2 =91, DQ3 =91
5234 10:02:01.291527 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5235 10:02:01.295032 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =79
5236 10:02:01.298365 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5237 10:02:01.298450
5238 10:02:01.298534
5239 10:02:01.298614 ==
5240 10:02:01.301598 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 10:02:01.305419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 10:02:01.305504 ==
5243 10:02:01.308689
5244 10:02:01.308773
5245 10:02:01.308857 TX Vref Scan disable
5246 10:02:01.311595 == TX Byte 0 ==
5247 10:02:01.314693 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5248 10:02:01.319536 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5249 10:02:01.321296 == TX Byte 1 ==
5250 10:02:01.324725 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5251 10:02:01.328099 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5252 10:02:01.328185 ==
5253 10:02:01.331460 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 10:02:01.338367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 10:02:01.338454 ==
5256 10:02:01.338538
5257 10:02:01.338638
5258 10:02:01.338737 TX Vref Scan disable
5259 10:02:01.342692 == TX Byte 0 ==
5260 10:02:01.345619 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5261 10:02:01.352334 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5262 10:02:01.352419 == TX Byte 1 ==
5263 10:02:01.355732 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5264 10:02:01.361990 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5265 10:02:01.362076
5266 10:02:01.362179 [DATLAT]
5267 10:02:01.362279 Freq=933, CH0 RK0
5268 10:02:01.362377
5269 10:02:01.365407 DATLAT Default: 0xd
5270 10:02:01.368714 0, 0xFFFF, sum = 0
5271 10:02:01.368801 1, 0xFFFF, sum = 0
5272 10:02:01.372077 2, 0xFFFF, sum = 0
5273 10:02:01.372163 3, 0xFFFF, sum = 0
5274 10:02:01.375230 4, 0xFFFF, sum = 0
5275 10:02:01.375316 5, 0xFFFF, sum = 0
5276 10:02:01.378825 6, 0xFFFF, sum = 0
5277 10:02:01.378929 7, 0xFFFF, sum = 0
5278 10:02:01.382111 8, 0xFFFF, sum = 0
5279 10:02:01.382196 9, 0xFFFF, sum = 0
5280 10:02:01.385055 10, 0x0, sum = 1
5281 10:02:01.385140 11, 0x0, sum = 2
5282 10:02:01.388858 12, 0x0, sum = 3
5283 10:02:01.388943 13, 0x0, sum = 4
5284 10:02:01.392775 best_step = 11
5285 10:02:01.392858
5286 10:02:01.392925 ==
5287 10:02:01.395145 Dram Type= 6, Freq= 0, CH_0, rank 0
5288 10:02:01.398549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 10:02:01.398633 ==
5290 10:02:01.398700 RX Vref Scan: 1
5291 10:02:01.398762
5292 10:02:01.401951 RX Vref 0 -> 0, step: 1
5293 10:02:01.402035
5294 10:02:01.404986 RX Delay -61 -> 252, step: 4
5295 10:02:01.405087
5296 10:02:01.408794 Set Vref, RX VrefLevel [Byte0]: 52
5297 10:02:01.412009 [Byte1]: 50
5298 10:02:01.415188
5299 10:02:01.415315 Final RX Vref Byte 0 = 52 to rank0
5300 10:02:01.418241 Final RX Vref Byte 1 = 50 to rank0
5301 10:02:01.421547 Final RX Vref Byte 0 = 52 to rank1
5302 10:02:01.425252 Final RX Vref Byte 1 = 50 to rank1==
5303 10:02:01.428845 Dram Type= 6, Freq= 0, CH_0, rank 0
5304 10:02:01.435073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 10:02:01.435160 ==
5306 10:02:01.435266 DQS Delay:
5307 10:02:01.435389 DQS0 = 0, DQS1 = 0
5308 10:02:01.438246 DQM Delay:
5309 10:02:01.438353 DQM0 = 96, DQM1 = 90
5310 10:02:01.441662 DQ Delay:
5311 10:02:01.444721 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5312 10:02:01.448101 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =102
5313 10:02:01.451523 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =82
5314 10:02:01.454974 DQ12 =98, DQ13 =94, DQ14 =100, DQ15 =98
5315 10:02:01.455055
5316 10:02:01.455120
5317 10:02:01.461300 [DQSOSCAuto] RK0, (LSB)MR18= 0x1400, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5318 10:02:01.464880 CH0 RK0: MR19=505, MR18=1400
5319 10:02:01.471103 CH0_RK0: MR19=0x505, MR18=0x1400, DQSOSC=415, MR23=63, INC=62, DEC=41
5320 10:02:01.471186
5321 10:02:01.474832 ----->DramcWriteLeveling(PI) begin...
5322 10:02:01.474915 ==
5323 10:02:01.477776 Dram Type= 6, Freq= 0, CH_0, rank 1
5324 10:02:01.481177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 10:02:01.481278 ==
5326 10:02:01.484953 Write leveling (Byte 0): 30 => 30
5327 10:02:01.487772 Write leveling (Byte 1): 29 => 29
5328 10:02:01.491107 DramcWriteLeveling(PI) end<-----
5329 10:02:01.491188
5330 10:02:01.491269 ==
5331 10:02:01.494287 Dram Type= 6, Freq= 0, CH_0, rank 1
5332 10:02:01.497729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 10:02:01.497812 ==
5334 10:02:01.500819 [Gating] SW mode calibration
5335 10:02:01.507632 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5336 10:02:01.514327 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5337 10:02:01.517756 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5338 10:02:01.524628 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 10:02:01.527329 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 10:02:01.530833 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 10:02:01.537844 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 10:02:01.541188 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 10:02:01.544556 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5344 10:02:01.550979 0 14 28 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (0 0)
5345 10:02:01.554385 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5346 10:02:01.557215 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 10:02:01.564214 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 10:02:01.567576 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 10:02:01.570573 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 10:02:01.574323 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 10:02:01.580965 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 10:02:01.583968 0 15 28 | B1->B0 | 2a2a 3333 | 0 1 | (0 0) (0 0)
5353 10:02:01.587850 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5354 10:02:01.593807 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 10:02:01.597417 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 10:02:01.601271 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 10:02:01.607407 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 10:02:01.610866 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 10:02:01.614193 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5360 10:02:01.620561 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5361 10:02:01.623578 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5362 10:02:01.626921 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5363 10:02:01.633825 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 10:02:01.637221 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 10:02:01.640155 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 10:02:01.646997 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 10:02:01.650326 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 10:02:01.653807 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 10:02:01.659912 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 10:02:01.663279 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 10:02:01.666904 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 10:02:01.673166 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 10:02:01.676742 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 10:02:01.680117 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5375 10:02:01.686508 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5376 10:02:01.689713 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5377 10:02:01.693200 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 10:02:01.696648 Total UI for P1: 0, mck2ui 16
5379 10:02:01.699859 best dqsien dly found for B0: ( 1, 2, 24)
5380 10:02:01.703163 Total UI for P1: 0, mck2ui 16
5381 10:02:01.706559 best dqsien dly found for B1: ( 1, 2, 30)
5382 10:02:01.709676 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5383 10:02:01.712910 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5384 10:02:01.712997
5385 10:02:01.720190 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5386 10:02:01.723014 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5387 10:02:01.726292 [Gating] SW calibration Done
5388 10:02:01.726379 ==
5389 10:02:01.729788 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 10:02:01.732756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 10:02:01.732843 ==
5392 10:02:01.732930 RX Vref Scan: 0
5393 10:02:01.733011
5394 10:02:01.736180 RX Vref 0 -> 0, step: 1
5395 10:02:01.736266
5396 10:02:01.739478 RX Delay -80 -> 252, step: 8
5397 10:02:01.742700 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5398 10:02:01.745949 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5399 10:02:01.749381 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5400 10:02:01.756112 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5401 10:02:01.759386 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5402 10:02:01.762798 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5403 10:02:01.765832 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5404 10:02:01.769187 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5405 10:02:01.776065 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5406 10:02:01.778941 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5407 10:02:01.782305 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5408 10:02:01.785897 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5409 10:02:01.789114 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5410 10:02:01.792647 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5411 10:02:01.799444 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5412 10:02:01.802462 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5413 10:02:01.802568 ==
5414 10:02:01.805869 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 10:02:01.808843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 10:02:01.808946 ==
5417 10:02:01.812432 DQS Delay:
5418 10:02:01.812524 DQS0 = 0, DQS1 = 0
5419 10:02:01.812593 DQM Delay:
5420 10:02:01.815227 DQM0 = 96, DQM1 = 87
5421 10:02:01.815335 DQ Delay:
5422 10:02:01.818638 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5423 10:02:01.822447 DQ4 =95, DQ5 =83, DQ6 =107, DQ7 =103
5424 10:02:01.825829 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =75
5425 10:02:01.828539 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5426 10:02:01.828615
5427 10:02:01.828679
5428 10:02:01.828740 ==
5429 10:02:01.831881 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 10:02:01.838944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 10:02:01.839025 ==
5432 10:02:01.839093
5433 10:02:01.839156
5434 10:02:01.839213 TX Vref Scan disable
5435 10:02:01.842319 == TX Byte 0 ==
5436 10:02:01.845404 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5437 10:02:01.852217 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5438 10:02:01.852323 == TX Byte 1 ==
5439 10:02:01.855770 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5440 10:02:01.861959 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5441 10:02:01.862068 ==
5442 10:02:01.865713 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 10:02:01.868633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 10:02:01.868741 ==
5445 10:02:01.868834
5446 10:02:01.868921
5447 10:02:01.872190 TX Vref Scan disable
5448 10:02:01.872263 == TX Byte 0 ==
5449 10:02:01.878837 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5450 10:02:01.882076 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5451 10:02:01.882175 == TX Byte 1 ==
5452 10:02:01.888876 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5453 10:02:01.891966 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5454 10:02:01.892046
5455 10:02:01.892145 [DATLAT]
5456 10:02:01.895106 Freq=933, CH0 RK1
5457 10:02:01.895210
5458 10:02:01.895302 DATLAT Default: 0xb
5459 10:02:01.898538 0, 0xFFFF, sum = 0
5460 10:02:01.898617 1, 0xFFFF, sum = 0
5461 10:02:01.902058 2, 0xFFFF, sum = 0
5462 10:02:01.902158 3, 0xFFFF, sum = 0
5463 10:02:01.905453 4, 0xFFFF, sum = 0
5464 10:02:01.908291 5, 0xFFFF, sum = 0
5465 10:02:01.908394 6, 0xFFFF, sum = 0
5466 10:02:01.911817 7, 0xFFFF, sum = 0
5467 10:02:01.911917 8, 0xFFFF, sum = 0
5468 10:02:01.914927 9, 0xFFFF, sum = 0
5469 10:02:01.915028 10, 0x0, sum = 1
5470 10:02:01.918419 11, 0x0, sum = 2
5471 10:02:01.918495 12, 0x0, sum = 3
5472 10:02:01.918574 13, 0x0, sum = 4
5473 10:02:01.921604 best_step = 11
5474 10:02:01.921714
5475 10:02:01.921826 ==
5476 10:02:01.924919 Dram Type= 6, Freq= 0, CH_0, rank 1
5477 10:02:01.928537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 10:02:01.928640 ==
5479 10:02:01.931552 RX Vref Scan: 0
5480 10:02:01.931634
5481 10:02:01.934765 RX Vref 0 -> 0, step: 1
5482 10:02:01.934862
5483 10:02:01.934953 RX Delay -61 -> 252, step: 4
5484 10:02:01.942936 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5485 10:02:01.945924 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5486 10:02:01.949238 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5487 10:02:01.952518 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5488 10:02:01.955774 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5489 10:02:01.959234 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5490 10:02:01.966017 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5491 10:02:01.969225 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5492 10:02:01.972405 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5493 10:02:01.976165 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5494 10:02:01.978978 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5495 10:02:01.982595 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5496 10:02:01.989382 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5497 10:02:01.992739 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5498 10:02:01.995485 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5499 10:02:01.999221 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5500 10:02:01.999332 ==
5501 10:02:02.002719 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 10:02:02.008807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 10:02:02.008898 ==
5504 10:02:02.008972 DQS Delay:
5505 10:02:02.012248 DQS0 = 0, DQS1 = 0
5506 10:02:02.012324 DQM Delay:
5507 10:02:02.012394 DQM0 = 96, DQM1 = 87
5508 10:02:02.015666 DQ Delay:
5509 10:02:02.018920 DQ0 =96, DQ1 =96, DQ2 =94, DQ3 =94
5510 10:02:02.022134 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =102
5511 10:02:02.025460 DQ8 =82, DQ9 =80, DQ10 =88, DQ11 =80
5512 10:02:02.028947 DQ12 =90, DQ13 =90, DQ14 =98, DQ15 =94
5513 10:02:02.029030
5514 10:02:02.029099
5515 10:02:02.035624 [DQSOSCAuto] RK1, (LSB)MR18= 0x1805, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5516 10:02:02.038905 CH0 RK1: MR19=505, MR18=1805
5517 10:02:02.045786 CH0_RK1: MR19=0x505, MR18=0x1805, DQSOSC=414, MR23=63, INC=63, DEC=42
5518 10:02:02.049175 [RxdqsGatingPostProcess] freq 933
5519 10:02:02.052039 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5520 10:02:02.055539 best DQS0 dly(2T, 0.5T) = (0, 10)
5521 10:02:02.058563 best DQS1 dly(2T, 0.5T) = (0, 11)
5522 10:02:02.062146 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5523 10:02:02.065190 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5524 10:02:02.068599 best DQS0 dly(2T, 0.5T) = (0, 10)
5525 10:02:02.072279 best DQS1 dly(2T, 0.5T) = (0, 10)
5526 10:02:02.075172 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5527 10:02:02.078651 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5528 10:02:02.082199 Pre-setting of DQS Precalculation
5529 10:02:02.085665 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5530 10:02:02.085742 ==
5531 10:02:02.088495 Dram Type= 6, Freq= 0, CH_1, rank 0
5532 10:02:02.095440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 10:02:02.095518 ==
5534 10:02:02.098479 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 10:02:02.105469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5536 10:02:02.108500 [CA 0] Center 37 (7~67) winsize 61
5537 10:02:02.111935 [CA 1] Center 36 (6~67) winsize 62
5538 10:02:02.115240 [CA 2] Center 34 (4~64) winsize 61
5539 10:02:02.118692 [CA 3] Center 33 (3~64) winsize 62
5540 10:02:02.121692 [CA 4] Center 34 (3~65) winsize 63
5541 10:02:02.125385 [CA 5] Center 33 (3~64) winsize 62
5542 10:02:02.125465
5543 10:02:02.128543 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5544 10:02:02.128621
5545 10:02:02.131672 [CATrainingPosCal] consider 1 rank data
5546 10:02:02.135499 u2DelayCellTimex100 = 270/100 ps
5547 10:02:02.138734 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5548 10:02:02.141573 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5549 10:02:02.148492 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5550 10:02:02.151493 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5551 10:02:02.155451 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5552 10:02:02.158504 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5553 10:02:02.158587
5554 10:02:02.161640 CA PerBit enable=1, Macro0, CA PI delay=33
5555 10:02:02.161723
5556 10:02:02.164772 [CBTSetCACLKResult] CA Dly = 33
5557 10:02:02.164855 CS Dly: 4 (0~35)
5558 10:02:02.168097 ==
5559 10:02:02.168181 Dram Type= 6, Freq= 0, CH_1, rank 1
5560 10:02:02.175194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 10:02:02.175279 ==
5562 10:02:02.178296 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5563 10:02:02.185023 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5564 10:02:02.188360 [CA 0] Center 36 (6~67) winsize 62
5565 10:02:02.191747 [CA 1] Center 37 (7~67) winsize 61
5566 10:02:02.195074 [CA 2] Center 33 (3~64) winsize 62
5567 10:02:02.198662 [CA 3] Center 33 (3~64) winsize 62
5568 10:02:02.201802 [CA 4] Center 33 (3~64) winsize 62
5569 10:02:02.204821 [CA 5] Center 32 (2~63) winsize 62
5570 10:02:02.204905
5571 10:02:02.208092 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5572 10:02:02.208175
5573 10:02:02.211337 [CATrainingPosCal] consider 2 rank data
5574 10:02:02.215275 u2DelayCellTimex100 = 270/100 ps
5575 10:02:02.218038 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5576 10:02:02.224926 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5577 10:02:02.228166 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5578 10:02:02.232103 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5579 10:02:02.234757 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5580 10:02:02.238498 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5581 10:02:02.238582
5582 10:02:02.241795 CA PerBit enable=1, Macro0, CA PI delay=33
5583 10:02:02.241880
5584 10:02:02.244913 [CBTSetCACLKResult] CA Dly = 33
5585 10:02:02.244997 CS Dly: 5 (0~38)
5586 10:02:02.245063
5587 10:02:02.248085 ----->DramcWriteLeveling(PI) begin...
5588 10:02:02.251758 ==
5589 10:02:02.255095 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 10:02:02.258385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 10:02:02.258470 ==
5592 10:02:02.261326 Write leveling (Byte 0): 24 => 24
5593 10:02:02.264770 Write leveling (Byte 1): 26 => 26
5594 10:02:02.267991 DramcWriteLeveling(PI) end<-----
5595 10:02:02.268074
5596 10:02:02.268146 ==
5597 10:02:02.271678 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 10:02:02.274698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 10:02:02.274783 ==
5600 10:02:02.278245 [Gating] SW mode calibration
5601 10:02:02.284947 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5602 10:02:02.291342 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5603 10:02:02.294891 0 14 0 | B1->B0 | 2d2d 3030 | 1 1 | (0 0) (1 1)
5604 10:02:02.298275 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 10:02:02.305370 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5606 10:02:02.308002 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5607 10:02:02.311264 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 10:02:02.318250 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 10:02:02.321813 0 14 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5610 10:02:02.324458 0 14 28 | B1->B0 | 3131 3333 | 0 0 | (0 1) (0 1)
5611 10:02:02.327842 0 15 0 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (0 0)
5612 10:02:02.334736 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 10:02:02.337785 0 15 8 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5614 10:02:02.341267 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5615 10:02:02.347616 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5616 10:02:02.350727 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5617 10:02:02.354199 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 10:02:02.360789 0 15 28 | B1->B0 | 3131 2c2c | 0 0 | (0 0) (1 1)
5619 10:02:02.364554 1 0 0 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5620 10:02:02.367801 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 10:02:02.374815 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 10:02:02.378416 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 10:02:02.380931 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 10:02:02.387232 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 10:02:02.390516 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 10:02:02.394004 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5627 10:02:02.401268 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 10:02:02.404186 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 10:02:02.407583 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 10:02:02.414414 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 10:02:02.417667 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 10:02:02.420665 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 10:02:02.427694 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 10:02:02.431454 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 10:02:02.433948 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 10:02:02.440699 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 10:02:02.443888 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 10:02:02.447076 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 10:02:02.454326 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 10:02:02.457283 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 10:02:02.460373 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 10:02:02.467317 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5643 10:02:02.470298 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 10:02:02.473566 Total UI for P1: 0, mck2ui 16
5645 10:02:02.477341 best dqsien dly found for B0: ( 1, 2, 28)
5646 10:02:02.480606 Total UI for P1: 0, mck2ui 16
5647 10:02:02.483753 best dqsien dly found for B1: ( 1, 2, 28)
5648 10:02:02.486948 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5649 10:02:02.490139 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5650 10:02:02.490250
5651 10:02:02.493798 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5652 10:02:02.496998 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5653 10:02:02.500647 [Gating] SW calibration Done
5654 10:02:02.500732 ==
5655 10:02:02.503749 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 10:02:02.507076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 10:02:02.507160 ==
5658 10:02:02.510721 RX Vref Scan: 0
5659 10:02:02.510805
5660 10:02:02.513503 RX Vref 0 -> 0, step: 1
5661 10:02:02.513587
5662 10:02:02.513654 RX Delay -80 -> 252, step: 8
5663 10:02:02.520112 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5664 10:02:02.524118 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5665 10:02:02.527023 iDelay=200, Bit 2, Center 83 (-16 ~ 183) 200
5666 10:02:02.529971 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5667 10:02:02.533403 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5668 10:02:02.536802 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5669 10:02:02.543385 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5670 10:02:02.546598 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5671 10:02:02.550033 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5672 10:02:02.553475 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5673 10:02:02.556999 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5674 10:02:02.563462 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5675 10:02:02.566866 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5676 10:02:02.569950 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5677 10:02:02.573077 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5678 10:02:02.576500 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5679 10:02:02.576582 ==
5680 10:02:02.579914 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 10:02:02.586472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 10:02:02.586559 ==
5683 10:02:02.586655 DQS Delay:
5684 10:02:02.589991 DQS0 = 0, DQS1 = 0
5685 10:02:02.590092 DQM Delay:
5686 10:02:02.590185 DQM0 = 95, DQM1 = 88
5687 10:02:02.593392 DQ Delay:
5688 10:02:02.596467 DQ0 =95, DQ1 =95, DQ2 =83, DQ3 =95
5689 10:02:02.599736 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5690 10:02:02.602986 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5691 10:02:02.606551 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5692 10:02:02.606657
5693 10:02:02.606753
5694 10:02:02.606843 ==
5695 10:02:02.610147 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 10:02:02.612870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 10:02:02.612971 ==
5698 10:02:02.613067
5699 10:02:02.613155
5700 10:02:02.616237 TX Vref Scan disable
5701 10:02:02.616351 == TX Byte 0 ==
5702 10:02:02.623228 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5703 10:02:02.626410 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5704 10:02:02.626489 == TX Byte 1 ==
5705 10:02:02.633225 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5706 10:02:02.636635 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5707 10:02:02.636744 ==
5708 10:02:02.640004 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 10:02:02.642832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 10:02:02.642939 ==
5711 10:02:02.643042
5712 10:02:02.646234
5713 10:02:02.646349 TX Vref Scan disable
5714 10:02:02.649977 == TX Byte 0 ==
5715 10:02:02.653260 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5716 10:02:02.656228 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5717 10:02:02.659821 == TX Byte 1 ==
5718 10:02:02.663186 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5719 10:02:02.666419 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5720 10:02:02.669746
5721 10:02:02.669852 [DATLAT]
5722 10:02:02.669947 Freq=933, CH1 RK0
5723 10:02:02.670049
5724 10:02:02.673242 DATLAT Default: 0xd
5725 10:02:02.673350 0, 0xFFFF, sum = 0
5726 10:02:02.676737 1, 0xFFFF, sum = 0
5727 10:02:02.676817 2, 0xFFFF, sum = 0
5728 10:02:02.679505 3, 0xFFFF, sum = 0
5729 10:02:02.679583 4, 0xFFFF, sum = 0
5730 10:02:02.683162 5, 0xFFFF, sum = 0
5731 10:02:02.683272 6, 0xFFFF, sum = 0
5732 10:02:02.686168 7, 0xFFFF, sum = 0
5733 10:02:02.689294 8, 0xFFFF, sum = 0
5734 10:02:02.689403 9, 0xFFFF, sum = 0
5735 10:02:02.689499 10, 0x0, sum = 1
5736 10:02:02.692914 11, 0x0, sum = 2
5737 10:02:02.692991 12, 0x0, sum = 3
5738 10:02:02.696262 13, 0x0, sum = 4
5739 10:02:02.696339 best_step = 11
5740 10:02:02.696427
5741 10:02:02.696490 ==
5742 10:02:02.699336 Dram Type= 6, Freq= 0, CH_1, rank 0
5743 10:02:02.706209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 10:02:02.706290 ==
5745 10:02:02.706388 RX Vref Scan: 1
5746 10:02:02.706478
5747 10:02:02.709141 RX Vref 0 -> 0, step: 1
5748 10:02:02.709245
5749 10:02:02.712962 RX Delay -69 -> 252, step: 4
5750 10:02:02.713068
5751 10:02:02.715863 Set Vref, RX VrefLevel [Byte0]: 57
5752 10:02:02.719895 [Byte1]: 52
5753 10:02:02.719985
5754 10:02:02.722917 Final RX Vref Byte 0 = 57 to rank0
5755 10:02:02.725839 Final RX Vref Byte 1 = 52 to rank0
5756 10:02:02.729110 Final RX Vref Byte 0 = 57 to rank1
5757 10:02:02.732300 Final RX Vref Byte 1 = 52 to rank1==
5758 10:02:02.735806 Dram Type= 6, Freq= 0, CH_1, rank 0
5759 10:02:02.739271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 10:02:02.739405 ==
5761 10:02:02.742716 DQS Delay:
5762 10:02:02.742788 DQS0 = 0, DQS1 = 0
5763 10:02:02.746287 DQM Delay:
5764 10:02:02.746390 DQM0 = 97, DQM1 = 90
5765 10:02:02.746483 DQ Delay:
5766 10:02:02.748997 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =96
5767 10:02:02.752510 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5768 10:02:02.755689 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =86
5769 10:02:02.758852 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5770 10:02:02.762424
5771 10:02:02.762505
5772 10:02:02.768942 [DQSOSCAuto] RK0, (LSB)MR18= 0x11ee, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5773 10:02:02.772836 CH1 RK0: MR19=504, MR18=11EE
5774 10:02:02.779161 CH1_RK0: MR19=0x504, MR18=0x11EE, DQSOSC=416, MR23=63, INC=62, DEC=41
5775 10:02:02.779263
5776 10:02:02.782628 ----->DramcWriteLeveling(PI) begin...
5777 10:02:02.782701 ==
5778 10:02:02.785620 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 10:02:02.789304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 10:02:02.789378 ==
5781 10:02:02.792303 Write leveling (Byte 0): 27 => 27
5782 10:02:02.796034 Write leveling (Byte 1): 27 => 27
5783 10:02:02.799338 DramcWriteLeveling(PI) end<-----
5784 10:02:02.799419
5785 10:02:02.799481 ==
5786 10:02:02.802384 Dram Type= 6, Freq= 0, CH_1, rank 1
5787 10:02:02.806010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 10:02:02.806110 ==
5789 10:02:02.808987 [Gating] SW mode calibration
5790 10:02:02.815253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5791 10:02:02.822435 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5792 10:02:02.825231 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 10:02:02.828973 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5794 10:02:02.835381 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5795 10:02:02.838855 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5796 10:02:02.842001 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5797 10:02:02.848931 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
5798 10:02:02.852366 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5799 10:02:02.855258 0 14 28 | B1->B0 | 2e2e 2424 | 0 0 | (1 0) (0 0)
5800 10:02:02.861990 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 10:02:02.865368 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5802 10:02:02.868763 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 10:02:02.875485 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5804 10:02:02.878887 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 10:02:02.882449 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 10:02:02.889036 0 15 24 | B1->B0 | 2b2b 3232 | 0 1 | (0 0) (0 0)
5807 10:02:02.892043 0 15 28 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (1 1)
5808 10:02:02.895358 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 10:02:02.902134 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 10:02:02.905125 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 10:02:02.908598 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 10:02:02.915250 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 10:02:02.918797 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5814 10:02:02.921820 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5815 10:02:02.928416 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5816 10:02:02.931672 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 10:02:02.935529 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 10:02:02.938129 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 10:02:02.945196 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 10:02:02.948305 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 10:02:02.951808 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 10:02:02.958558 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 10:02:02.961891 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 10:02:02.965150 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 10:02:02.971582 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 10:02:02.975069 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 10:02:02.978652 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 10:02:02.984718 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 10:02:02.988554 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 10:02:02.991824 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5831 10:02:02.995140 Total UI for P1: 0, mck2ui 16
5832 10:02:02.998250 best dqsien dly found for B0: ( 1, 2, 22)
5833 10:02:03.004849 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5834 10:02:03.008522 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 10:02:03.011573 Total UI for P1: 0, mck2ui 16
5836 10:02:03.014795 best dqsien dly found for B1: ( 1, 2, 26)
5837 10:02:03.018683 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5838 10:02:03.021552 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5839 10:02:03.021634
5840 10:02:03.024881 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5841 10:02:03.028125 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5842 10:02:03.031638 [Gating] SW calibration Done
5843 10:02:03.031720 ==
5844 10:02:03.034667 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 10:02:03.038223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 10:02:03.041061 ==
5847 10:02:03.041143 RX Vref Scan: 0
5848 10:02:03.041209
5849 10:02:03.044539 RX Vref 0 -> 0, step: 1
5850 10:02:03.044622
5851 10:02:03.047798 RX Delay -80 -> 252, step: 8
5852 10:02:03.051504 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5853 10:02:03.054816 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5854 10:02:03.057812 iDelay=200, Bit 2, Center 83 (-16 ~ 183) 200
5855 10:02:03.061018 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5856 10:02:03.064946 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5857 10:02:03.071261 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5858 10:02:03.074392 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5859 10:02:03.077860 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5860 10:02:03.081144 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5861 10:02:03.084256 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5862 10:02:03.090936 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5863 10:02:03.094380 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5864 10:02:03.097717 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5865 10:02:03.101367 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5866 10:02:03.104257 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5867 10:02:03.107518 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5868 10:02:03.110619 ==
5869 10:02:03.110702 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 10:02:03.117534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 10:02:03.117619 ==
5872 10:02:03.117685 DQS Delay:
5873 10:02:03.121056 DQS0 = 0, DQS1 = 0
5874 10:02:03.121167 DQM Delay:
5875 10:02:03.124322 DQM0 = 94, DQM1 = 88
5876 10:02:03.124404 DQ Delay:
5877 10:02:03.127234 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =95
5878 10:02:03.130415 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5879 10:02:03.134234 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5880 10:02:03.137385 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5881 10:02:03.137469
5882 10:02:03.137535
5883 10:02:03.137596 ==
5884 10:02:03.140786 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 10:02:03.144097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 10:02:03.144180 ==
5887 10:02:03.144274
5888 10:02:03.144356
5889 10:02:03.147371 TX Vref Scan disable
5890 10:02:03.150693 == TX Byte 0 ==
5891 10:02:03.154230 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5892 10:02:03.157186 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5893 10:02:03.160322 == TX Byte 1 ==
5894 10:02:03.164021 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5895 10:02:03.168184 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5896 10:02:03.168272 ==
5897 10:02:03.170583 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 10:02:03.177553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 10:02:03.177642 ==
5900 10:02:03.177726
5901 10:02:03.177812
5902 10:02:03.177887 TX Vref Scan disable
5903 10:02:03.181058 == TX Byte 0 ==
5904 10:02:03.184176 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5905 10:02:03.190741 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5906 10:02:03.190823 == TX Byte 1 ==
5907 10:02:03.194130 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5908 10:02:03.200652 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5909 10:02:03.200743
5910 10:02:03.200824 [DATLAT]
5911 10:02:03.200903 Freq=933, CH1 RK1
5912 10:02:03.200981
5913 10:02:03.204215 DATLAT Default: 0xb
5914 10:02:03.204303 0, 0xFFFF, sum = 0
5915 10:02:03.207667 1, 0xFFFF, sum = 0
5916 10:02:03.207746 2, 0xFFFF, sum = 0
5917 10:02:03.210764 3, 0xFFFF, sum = 0
5918 10:02:03.210843 4, 0xFFFF, sum = 0
5919 10:02:03.214435 5, 0xFFFF, sum = 0
5920 10:02:03.217393 6, 0xFFFF, sum = 0
5921 10:02:03.217471 7, 0xFFFF, sum = 0
5922 10:02:03.220863 8, 0xFFFF, sum = 0
5923 10:02:03.220948 9, 0xFFFF, sum = 0
5924 10:02:03.224115 10, 0x0, sum = 1
5925 10:02:03.224200 11, 0x0, sum = 2
5926 10:02:03.224267 12, 0x0, sum = 3
5927 10:02:03.227533 13, 0x0, sum = 4
5928 10:02:03.227617 best_step = 11
5929 10:02:03.227683
5930 10:02:03.227744 ==
5931 10:02:03.231107 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 10:02:03.237416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 10:02:03.237501 ==
5934 10:02:03.237567 RX Vref Scan: 0
5935 10:02:03.237628
5936 10:02:03.240987 RX Vref 0 -> 0, step: 1
5937 10:02:03.241070
5938 10:02:03.244152 RX Delay -61 -> 252, step: 4
5939 10:02:03.247717 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5940 10:02:03.254239 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5941 10:02:03.257540 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5942 10:02:03.260982 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5943 10:02:03.264140 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5944 10:02:03.267717 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5945 10:02:03.270626 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5946 10:02:03.277340 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5947 10:02:03.280784 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5948 10:02:03.284251 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5949 10:02:03.287322 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5950 10:02:03.290597 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5951 10:02:03.297789 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5952 10:02:03.300577 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5953 10:02:03.303881 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5954 10:02:03.307295 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
5955 10:02:03.307383 ==
5956 10:02:03.310903 Dram Type= 6, Freq= 0, CH_1, rank 1
5957 10:02:03.313741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5958 10:02:03.317517 ==
5959 10:02:03.317603 DQS Delay:
5960 10:02:03.317669 DQS0 = 0, DQS1 = 0
5961 10:02:03.320565 DQM Delay:
5962 10:02:03.320648 DQM0 = 95, DQM1 = 91
5963 10:02:03.323980 DQ Delay:
5964 10:02:03.327126 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5965 10:02:03.330772 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =92
5966 10:02:03.330855 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =82
5967 10:02:03.336814 DQ12 =98, DQ13 =100, DQ14 =102, DQ15 =100
5968 10:02:03.336897
5969 10:02:03.336963
5970 10:02:03.343679 [DQSOSCAuto] RK1, (LSB)MR18= 0xc16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 418 ps
5971 10:02:03.346939 CH1 RK1: MR19=505, MR18=C16
5972 10:02:03.353808 CH1_RK1: MR19=0x505, MR18=0xC16, DQSOSC=414, MR23=63, INC=63, DEC=42
5973 10:02:03.357149 [RxdqsGatingPostProcess] freq 933
5974 10:02:03.360144 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5975 10:02:03.363613 best DQS0 dly(2T, 0.5T) = (0, 10)
5976 10:02:03.367179 best DQS1 dly(2T, 0.5T) = (0, 10)
5977 10:02:03.369889 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5978 10:02:03.373333 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5979 10:02:03.376823 best DQS0 dly(2T, 0.5T) = (0, 10)
5980 10:02:03.379982 best DQS1 dly(2T, 0.5T) = (0, 10)
5981 10:02:03.383573 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5982 10:02:03.386391 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5983 10:02:03.390145 Pre-setting of DQS Precalculation
5984 10:02:03.393459 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5985 10:02:03.403266 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5986 10:02:03.409994 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5987 10:02:03.410077
5988 10:02:03.410142
5989 10:02:03.413334 [Calibration Summary] 1866 Mbps
5990 10:02:03.413417 CH 0, Rank 0
5991 10:02:03.416270 SW Impedance : PASS
5992 10:02:03.416353 DUTY Scan : NO K
5993 10:02:03.420018 ZQ Calibration : PASS
5994 10:02:03.423161 Jitter Meter : NO K
5995 10:02:03.423244 CBT Training : PASS
5996 10:02:03.426438 Write leveling : PASS
5997 10:02:03.429557 RX DQS gating : PASS
5998 10:02:03.429640 RX DQ/DQS(RDDQC) : PASS
5999 10:02:03.432912 TX DQ/DQS : PASS
6000 10:02:03.436643 RX DATLAT : PASS
6001 10:02:03.436726 RX DQ/DQS(Engine): PASS
6002 10:02:03.439614 TX OE : NO K
6003 10:02:03.439699 All Pass.
6004 10:02:03.439766
6005 10:02:03.443133 CH 0, Rank 1
6006 10:02:03.443216 SW Impedance : PASS
6007 10:02:03.446289 DUTY Scan : NO K
6008 10:02:03.446372 ZQ Calibration : PASS
6009 10:02:03.449577 Jitter Meter : NO K
6010 10:02:03.453267 CBT Training : PASS
6011 10:02:03.453350 Write leveling : PASS
6012 10:02:03.456655 RX DQS gating : PASS
6013 10:02:03.459799 RX DQ/DQS(RDDQC) : PASS
6014 10:02:03.459893 TX DQ/DQS : PASS
6015 10:02:03.462663 RX DATLAT : PASS
6016 10:02:03.466062 RX DQ/DQS(Engine): PASS
6017 10:02:03.466145 TX OE : NO K
6018 10:02:03.469242 All Pass.
6019 10:02:03.469325
6020 10:02:03.469390 CH 1, Rank 0
6021 10:02:03.472766 SW Impedance : PASS
6022 10:02:03.472849 DUTY Scan : NO K
6023 10:02:03.476256 ZQ Calibration : PASS
6024 10:02:03.479510 Jitter Meter : NO K
6025 10:02:03.479593 CBT Training : PASS
6026 10:02:03.482971 Write leveling : PASS
6027 10:02:03.485804 RX DQS gating : PASS
6028 10:02:03.485887 RX DQ/DQS(RDDQC) : PASS
6029 10:02:03.489369 TX DQ/DQS : PASS
6030 10:02:03.492643 RX DATLAT : PASS
6031 10:02:03.492730 RX DQ/DQS(Engine): PASS
6032 10:02:03.496221 TX OE : NO K
6033 10:02:03.496305 All Pass.
6034 10:02:03.496370
6035 10:02:03.499320 CH 1, Rank 1
6036 10:02:03.499408 SW Impedance : PASS
6037 10:02:03.502809 DUTY Scan : NO K
6038 10:02:03.502892 ZQ Calibration : PASS
6039 10:02:03.505668 Jitter Meter : NO K
6040 10:02:03.508937 CBT Training : PASS
6041 10:02:03.509020 Write leveling : PASS
6042 10:02:03.512319 RX DQS gating : PASS
6043 10:02:03.515642 RX DQ/DQS(RDDQC) : PASS
6044 10:02:03.515726 TX DQ/DQS : PASS
6045 10:02:03.519176 RX DATLAT : PASS
6046 10:02:03.522695 RX DQ/DQS(Engine): PASS
6047 10:02:03.522778 TX OE : NO K
6048 10:02:03.525793 All Pass.
6049 10:02:03.525909
6050 10:02:03.526018 DramC Write-DBI off
6051 10:02:03.529266 PER_BANK_REFRESH: Hybrid Mode
6052 10:02:03.532151 TX_TRACKING: ON
6053 10:02:03.538862 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6054 10:02:03.542560 [FAST_K] Save calibration result to emmc
6055 10:02:03.545498 dramc_set_vcore_voltage set vcore to 650000
6056 10:02:03.548971 Read voltage for 400, 6
6057 10:02:03.549081 Vio18 = 0
6058 10:02:03.552417 Vcore = 650000
6059 10:02:03.552524 Vdram = 0
6060 10:02:03.552618 Vddq = 0
6061 10:02:03.555462 Vmddr = 0
6062 10:02:03.558582 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6063 10:02:03.565571 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6064 10:02:03.565678 MEM_TYPE=3, freq_sel=20
6065 10:02:03.568977 sv_algorithm_assistance_LP4_800
6066 10:02:03.575914 ============ PULL DRAM RESETB DOWN ============
6067 10:02:03.578837 ========== PULL DRAM RESETB DOWN end =========
6068 10:02:03.582612 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6069 10:02:03.585429 ===================================
6070 10:02:03.588565 LPDDR4 DRAM CONFIGURATION
6071 10:02:03.592602 ===================================
6072 10:02:03.592704 EX_ROW_EN[0] = 0x0
6073 10:02:03.595507 EX_ROW_EN[1] = 0x0
6074 10:02:03.598891 LP4Y_EN = 0x0
6075 10:02:03.598990 WORK_FSP = 0x0
6076 10:02:03.601786 WL = 0x2
6077 10:02:03.601892 RL = 0x2
6078 10:02:03.605526 BL = 0x2
6079 10:02:03.605627 RPST = 0x0
6080 10:02:03.608403 RD_PRE = 0x0
6081 10:02:03.608502 WR_PRE = 0x1
6082 10:02:03.611859 WR_PST = 0x0
6083 10:02:03.611934 DBI_WR = 0x0
6084 10:02:03.615086 DBI_RD = 0x0
6085 10:02:03.615190 OTF = 0x1
6086 10:02:03.618384 ===================================
6087 10:02:03.621885 ===================================
6088 10:02:03.625255 ANA top config
6089 10:02:03.628645 ===================================
6090 10:02:03.631551 DLL_ASYNC_EN = 0
6091 10:02:03.631647 ALL_SLAVE_EN = 1
6092 10:02:03.635042 NEW_RANK_MODE = 1
6093 10:02:03.638873 DLL_IDLE_MODE = 1
6094 10:02:03.641820 LP45_APHY_COMB_EN = 1
6095 10:02:03.641927 TX_ODT_DIS = 1
6096 10:02:03.645113 NEW_8X_MODE = 1
6097 10:02:03.648689 ===================================
6098 10:02:03.651506 ===================================
6099 10:02:03.655135 data_rate = 800
6100 10:02:03.658506 CKR = 1
6101 10:02:03.661729 DQ_P2S_RATIO = 4
6102 10:02:03.664942 ===================================
6103 10:02:03.667979 CA_P2S_RATIO = 4
6104 10:02:03.668056 DQ_CA_OPEN = 0
6105 10:02:03.671165 DQ_SEMI_OPEN = 1
6106 10:02:03.674990 CA_SEMI_OPEN = 1
6107 10:02:03.678293 CA_FULL_RATE = 0
6108 10:02:03.681538 DQ_CKDIV4_EN = 0
6109 10:02:03.684807 CA_CKDIV4_EN = 1
6110 10:02:03.684880 CA_PREDIV_EN = 0
6111 10:02:03.688129 PH8_DLY = 0
6112 10:02:03.691493 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6113 10:02:03.694935 DQ_AAMCK_DIV = 0
6114 10:02:03.697815 CA_AAMCK_DIV = 0
6115 10:02:03.701531 CA_ADMCK_DIV = 4
6116 10:02:03.701602 DQ_TRACK_CA_EN = 0
6117 10:02:03.704653 CA_PICK = 800
6118 10:02:03.707880 CA_MCKIO = 400
6119 10:02:03.711749 MCKIO_SEMI = 400
6120 10:02:03.714526 PLL_FREQ = 3016
6121 10:02:03.717814 DQ_UI_PI_RATIO = 32
6122 10:02:03.721195 CA_UI_PI_RATIO = 32
6123 10:02:03.724880 ===================================
6124 10:02:03.728200 ===================================
6125 10:02:03.728284 memory_type:LPDDR4
6126 10:02:03.731034 GP_NUM : 10
6127 10:02:03.734668 SRAM_EN : 1
6128 10:02:03.734772 MD32_EN : 0
6129 10:02:03.738042 ===================================
6130 10:02:03.740989 [ANA_INIT] >>>>>>>>>>>>>>
6131 10:02:03.744552 <<<<<< [CONFIGURE PHASE]: ANA_TX
6132 10:02:03.747511 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6133 10:02:03.750894 ===================================
6134 10:02:03.754144 data_rate = 800,PCW = 0X7400
6135 10:02:03.757554 ===================================
6136 10:02:03.761011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6137 10:02:03.764064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6138 10:02:03.777344 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6139 10:02:03.781636 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6140 10:02:03.784124 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6141 10:02:03.787580 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6142 10:02:03.790971 [ANA_INIT] flow start
6143 10:02:03.793847 [ANA_INIT] PLL >>>>>>>>
6144 10:02:03.793956 [ANA_INIT] PLL <<<<<<<<
6145 10:02:03.797715 [ANA_INIT] MIDPI >>>>>>>>
6146 10:02:03.800567 [ANA_INIT] MIDPI <<<<<<<<
6147 10:02:03.800667 [ANA_INIT] DLL >>>>>>>>
6148 10:02:03.804132 [ANA_INIT] flow end
6149 10:02:03.807334 ============ LP4 DIFF to SE enter ============
6150 10:02:03.810489 ============ LP4 DIFF to SE exit ============
6151 10:02:03.813912 [ANA_INIT] <<<<<<<<<<<<<
6152 10:02:03.817263 [Flow] Enable top DCM control >>>>>
6153 10:02:03.820649 [Flow] Enable top DCM control <<<<<
6154 10:02:03.824051 Enable DLL master slave shuffle
6155 10:02:03.830699 ==============================================================
6156 10:02:03.830805 Gating Mode config
6157 10:02:03.837480 ==============================================================
6158 10:02:03.837587 Config description:
6159 10:02:03.847208 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6160 10:02:03.853654 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6161 10:02:03.860536 SELPH_MODE 0: By rank 1: By Phase
6162 10:02:03.863471 ==============================================================
6163 10:02:03.867204 GAT_TRACK_EN = 0
6164 10:02:03.870310 RX_GATING_MODE = 2
6165 10:02:03.873548 RX_GATING_TRACK_MODE = 2
6166 10:02:03.877084 SELPH_MODE = 1
6167 10:02:03.880684 PICG_EARLY_EN = 1
6168 10:02:03.883490 VALID_LAT_VALUE = 1
6169 10:02:03.890374 ==============================================================
6170 10:02:03.893368 Enter into Gating configuration >>>>
6171 10:02:03.896962 Exit from Gating configuration <<<<
6172 10:02:03.900362 Enter into DVFS_PRE_config >>>>>
6173 10:02:03.910072 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6174 10:02:03.913843 Exit from DVFS_PRE_config <<<<<
6175 10:02:03.916893 Enter into PICG configuration >>>>
6176 10:02:03.920521 Exit from PICG configuration <<<<
6177 10:02:03.920593 [RX_INPUT] configuration >>>>>
6178 10:02:03.923245 [RX_INPUT] configuration <<<<<
6179 10:02:03.930439 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6180 10:02:03.933572 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6181 10:02:03.939898 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6182 10:02:03.947004 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6183 10:02:03.953508 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6184 10:02:03.960334 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6185 10:02:03.963073 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6186 10:02:03.966930 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6187 10:02:03.973233 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6188 10:02:03.976845 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6189 10:02:03.980195 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6190 10:02:03.983239 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6191 10:02:03.987030 ===================================
6192 10:02:03.989921 LPDDR4 DRAM CONFIGURATION
6193 10:02:03.993444 ===================================
6194 10:02:03.996604 EX_ROW_EN[0] = 0x0
6195 10:02:03.996689 EX_ROW_EN[1] = 0x0
6196 10:02:03.999886 LP4Y_EN = 0x0
6197 10:02:03.999969 WORK_FSP = 0x0
6198 10:02:04.003113 WL = 0x2
6199 10:02:04.003197 RL = 0x2
6200 10:02:04.006643 BL = 0x2
6201 10:02:04.006739 RPST = 0x0
6202 10:02:04.010278 RD_PRE = 0x0
6203 10:02:04.010361 WR_PRE = 0x1
6204 10:02:04.013229 WR_PST = 0x0
6205 10:02:04.013312 DBI_WR = 0x0
6206 10:02:04.016502 DBI_RD = 0x0
6207 10:02:04.020038 OTF = 0x1
6208 10:02:04.023195 ===================================
6209 10:02:04.026148 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6210 10:02:04.029671 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6211 10:02:04.032910 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6212 10:02:04.036332 ===================================
6213 10:02:04.039744 LPDDR4 DRAM CONFIGURATION
6214 10:02:04.043240 ===================================
6215 10:02:04.046177 EX_ROW_EN[0] = 0x10
6216 10:02:04.046252 EX_ROW_EN[1] = 0x0
6217 10:02:04.049770 LP4Y_EN = 0x0
6218 10:02:04.049849 WORK_FSP = 0x0
6219 10:02:04.053132 WL = 0x2
6220 10:02:04.053204 RL = 0x2
6221 10:02:04.056542 BL = 0x2
6222 10:02:04.056613 RPST = 0x0
6223 10:02:04.059784 RD_PRE = 0x0
6224 10:02:04.059870 WR_PRE = 0x1
6225 10:02:04.063218 WR_PST = 0x0
6226 10:02:04.063319 DBI_WR = 0x0
6227 10:02:04.066028 DBI_RD = 0x0
6228 10:02:04.066104 OTF = 0x1
6229 10:02:04.069797 ===================================
6230 10:02:04.076330 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6231 10:02:04.080897 nWR fixed to 30
6232 10:02:04.084411 [ModeRegInit_LP4] CH0 RK0
6233 10:02:04.084488 [ModeRegInit_LP4] CH0 RK1
6234 10:02:04.087810 [ModeRegInit_LP4] CH1 RK0
6235 10:02:04.091113 [ModeRegInit_LP4] CH1 RK1
6236 10:02:04.091216 match AC timing 19
6237 10:02:04.097552 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6238 10:02:04.100757 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6239 10:02:04.104047 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6240 10:02:04.110742 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6241 10:02:04.114080 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6242 10:02:04.114153 ==
6243 10:02:04.117444 Dram Type= 6, Freq= 0, CH_0, rank 0
6244 10:02:04.120666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 10:02:04.120739 ==
6246 10:02:04.127767 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6247 10:02:04.134530 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6248 10:02:04.137513 [CA 0] Center 36 (8~64) winsize 57
6249 10:02:04.141063 [CA 1] Center 36 (8~64) winsize 57
6250 10:02:04.143897 [CA 2] Center 36 (8~64) winsize 57
6251 10:02:04.147783 [CA 3] Center 36 (8~64) winsize 57
6252 10:02:04.147867 [CA 4] Center 36 (8~64) winsize 57
6253 10:02:04.150571 [CA 5] Center 36 (8~64) winsize 57
6254 10:02:04.150653
6255 10:02:04.157403 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6256 10:02:04.157485
6257 10:02:04.160701 [CATrainingPosCal] consider 1 rank data
6258 10:02:04.163937 u2DelayCellTimex100 = 270/100 ps
6259 10:02:04.167476 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 10:02:04.170407 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 10:02:04.173889 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 10:02:04.177204 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 10:02:04.180722 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 10:02:04.184230 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 10:02:04.184313
6266 10:02:04.187548 CA PerBit enable=1, Macro0, CA PI delay=36
6267 10:02:04.187631
6268 10:02:04.190445 [CBTSetCACLKResult] CA Dly = 36
6269 10:02:04.193717 CS Dly: 1 (0~32)
6270 10:02:04.193799 ==
6271 10:02:04.197142 Dram Type= 6, Freq= 0, CH_0, rank 1
6272 10:02:04.200348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 10:02:04.200462 ==
6274 10:02:04.206893 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6275 10:02:04.210537 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6276 10:02:04.213619 [CA 0] Center 36 (8~64) winsize 57
6277 10:02:04.217457 [CA 1] Center 36 (8~64) winsize 57
6278 10:02:04.220606 [CA 2] Center 36 (8~64) winsize 57
6279 10:02:04.223830 [CA 3] Center 36 (8~64) winsize 57
6280 10:02:04.227116 [CA 4] Center 36 (8~64) winsize 57
6281 10:02:04.230589 [CA 5] Center 36 (8~64) winsize 57
6282 10:02:04.230673
6283 10:02:04.233982 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6284 10:02:04.234066
6285 10:02:04.237213 [CATrainingPosCal] consider 2 rank data
6286 10:02:04.240417 u2DelayCellTimex100 = 270/100 ps
6287 10:02:04.243775 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 10:02:04.247199 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 10:02:04.253414 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 10:02:04.256766 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 10:02:04.260276 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 10:02:04.263457 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 10:02:04.263541
6294 10:02:04.266652 CA PerBit enable=1, Macro0, CA PI delay=36
6295 10:02:04.266736
6296 10:02:04.270100 [CBTSetCACLKResult] CA Dly = 36
6297 10:02:04.270210 CS Dly: 1 (0~32)
6298 10:02:04.270310
6299 10:02:04.273768 ----->DramcWriteLeveling(PI) begin...
6300 10:02:04.277170 ==
6301 10:02:04.280689 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 10:02:04.283418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 10:02:04.283491 ==
6304 10:02:04.286731 Write leveling (Byte 0): 40 => 8
6305 10:02:04.290401 Write leveling (Byte 1): 32 => 0
6306 10:02:04.293497 DramcWriteLeveling(PI) end<-----
6307 10:02:04.293599
6308 10:02:04.293695 ==
6309 10:02:04.296792 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 10:02:04.300197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 10:02:04.300305 ==
6312 10:02:04.303149 [Gating] SW mode calibration
6313 10:02:04.310122 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6314 10:02:04.313245 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6315 10:02:04.320234 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6316 10:02:04.323106 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6317 10:02:04.326711 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6318 10:02:04.333447 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6319 10:02:04.336419 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6320 10:02:04.339615 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 10:02:04.346382 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 10:02:04.350012 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 10:02:04.353071 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 10:02:04.356517 Total UI for P1: 0, mck2ui 16
6325 10:02:04.359772 best dqsien dly found for B0: ( 0, 14, 24)
6326 10:02:04.363277 Total UI for P1: 0, mck2ui 16
6327 10:02:04.366665 best dqsien dly found for B1: ( 0, 14, 24)
6328 10:02:04.369563 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6329 10:02:04.373055 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6330 10:02:04.376365
6331 10:02:04.379738 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6332 10:02:04.382931 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6333 10:02:04.386285 [Gating] SW calibration Done
6334 10:02:04.386387 ==
6335 10:02:04.389768 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 10:02:04.393143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 10:02:04.393248 ==
6338 10:02:04.393342 RX Vref Scan: 0
6339 10:02:04.396135
6340 10:02:04.396204 RX Vref 0 -> 0, step: 1
6341 10:02:04.396265
6342 10:02:04.399501 RX Delay -410 -> 252, step: 16
6343 10:02:04.402864 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6344 10:02:04.409295 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6345 10:02:04.412623 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6346 10:02:04.415953 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6347 10:02:04.419236 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6348 10:02:04.426056 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6349 10:02:04.429235 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6350 10:02:04.432708 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6351 10:02:04.436070 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6352 10:02:04.443047 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6353 10:02:04.445807 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6354 10:02:04.449193 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6355 10:02:04.452616 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6356 10:02:04.459315 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6357 10:02:04.462880 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6358 10:02:04.465613 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6359 10:02:04.465717 ==
6360 10:02:04.469597 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 10:02:04.475688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 10:02:04.475772 ==
6363 10:02:04.475839 DQS Delay:
6364 10:02:04.479142 DQS0 = 35, DQS1 = 51
6365 10:02:04.479247 DQM Delay:
6366 10:02:04.479368 DQM0 = 7, DQM1 = 10
6367 10:02:04.482573 DQ Delay:
6368 10:02:04.486043 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6369 10:02:04.486144 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6370 10:02:04.489049 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6371 10:02:04.492657 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6372 10:02:04.492734
6373 10:02:04.492798
6374 10:02:04.495788 ==
6375 10:02:04.498675 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 10:02:04.502654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 10:02:04.502767 ==
6378 10:02:04.502861
6379 10:02:04.502950
6380 10:02:04.506134 TX Vref Scan disable
6381 10:02:04.506237 == TX Byte 0 ==
6382 10:02:04.508891 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6383 10:02:04.515741 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6384 10:02:04.515847 == TX Byte 1 ==
6385 10:02:04.519005 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6386 10:02:04.525642 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6387 10:02:04.525747 ==
6388 10:02:04.528649 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 10:02:04.532282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 10:02:04.532387 ==
6391 10:02:04.532484
6392 10:02:04.532574
6393 10:02:04.535543 TX Vref Scan disable
6394 10:02:04.535621 == TX Byte 0 ==
6395 10:02:04.538543 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6396 10:02:04.545355 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6397 10:02:04.545461 == TX Byte 1 ==
6398 10:02:04.548895 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6399 10:02:04.555263 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6400 10:02:04.555402
6401 10:02:04.555471 [DATLAT]
6402 10:02:04.558850 Freq=400, CH0 RK0
6403 10:02:04.558954
6404 10:02:04.559045 DATLAT Default: 0xf
6405 10:02:04.562083 0, 0xFFFF, sum = 0
6406 10:02:04.562185 1, 0xFFFF, sum = 0
6407 10:02:04.565891 2, 0xFFFF, sum = 0
6408 10:02:04.565997 3, 0xFFFF, sum = 0
6409 10:02:04.568767 4, 0xFFFF, sum = 0
6410 10:02:04.568870 5, 0xFFFF, sum = 0
6411 10:02:04.571589 6, 0xFFFF, sum = 0
6412 10:02:04.571694 7, 0xFFFF, sum = 0
6413 10:02:04.574993 8, 0xFFFF, sum = 0
6414 10:02:04.575098 9, 0xFFFF, sum = 0
6415 10:02:04.578526 10, 0xFFFF, sum = 0
6416 10:02:04.578628 11, 0xFFFF, sum = 0
6417 10:02:04.581788 12, 0xFFFF, sum = 0
6418 10:02:04.581898 13, 0x0, sum = 1
6419 10:02:04.585037 14, 0x0, sum = 2
6420 10:02:04.585151 15, 0x0, sum = 3
6421 10:02:04.588227 16, 0x0, sum = 4
6422 10:02:04.588335 best_step = 14
6423 10:02:04.588429
6424 10:02:04.588518 ==
6425 10:02:04.591752 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 10:02:04.598600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 10:02:04.598715 ==
6428 10:02:04.598813 RX Vref Scan: 1
6429 10:02:04.598904
6430 10:02:04.601622 RX Vref 0 -> 0, step: 1
6431 10:02:04.601722
6432 10:02:04.604877 RX Delay -343 -> 252, step: 8
6433 10:02:04.604952
6434 10:02:04.608686 Set Vref, RX VrefLevel [Byte0]: 52
6435 10:02:04.612163 [Byte1]: 50
6436 10:02:04.612244
6437 10:02:04.614794 Final RX Vref Byte 0 = 52 to rank0
6438 10:02:04.618214 Final RX Vref Byte 1 = 50 to rank0
6439 10:02:04.621827 Final RX Vref Byte 0 = 52 to rank1
6440 10:02:04.624984 Final RX Vref Byte 1 = 50 to rank1==
6441 10:02:04.628073 Dram Type= 6, Freq= 0, CH_0, rank 0
6442 10:02:04.631615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 10:02:04.635126 ==
6444 10:02:04.635240 DQS Delay:
6445 10:02:04.635335 DQS0 = 40, DQS1 = 60
6446 10:02:04.638425 DQM Delay:
6447 10:02:04.638532 DQM0 = 7, DQM1 = 16
6448 10:02:04.641399 DQ Delay:
6449 10:02:04.641514 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6450 10:02:04.644998 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6451 10:02:04.648341 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6452 10:02:04.651851 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =28
6453 10:02:04.651961
6454 10:02:04.652063
6455 10:02:04.661826 [DQSOSCAuto] RK0, (LSB)MR18= 0x8957, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6456 10:02:04.664491 CH0 RK0: MR19=C0C, MR18=8957
6457 10:02:04.671471 CH0_RK0: MR19=0xC0C, MR18=0x8957, DQSOSC=392, MR23=63, INC=384, DEC=256
6458 10:02:04.671549 ==
6459 10:02:04.674728 Dram Type= 6, Freq= 0, CH_0, rank 1
6460 10:02:04.678160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 10:02:04.678234 ==
6462 10:02:04.681086 [Gating] SW mode calibration
6463 10:02:04.687826 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6464 10:02:04.691424 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6465 10:02:04.698246 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6466 10:02:04.701395 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6467 10:02:04.704782 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6468 10:02:04.711569 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6469 10:02:04.714735 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6470 10:02:04.718001 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 10:02:04.724932 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 10:02:04.728170 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 10:02:04.731257 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 10:02:04.734713 Total UI for P1: 0, mck2ui 16
6475 10:02:04.738554 best dqsien dly found for B0: ( 0, 14, 24)
6476 10:02:04.740992 Total UI for P1: 0, mck2ui 16
6477 10:02:04.744800 best dqsien dly found for B1: ( 0, 14, 24)
6478 10:02:04.748136 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6479 10:02:04.751458 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6480 10:02:04.751540
6481 10:02:04.757918 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6482 10:02:04.761516 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6483 10:02:04.761622 [Gating] SW calibration Done
6484 10:02:04.764593 ==
6485 10:02:04.768057 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 10:02:04.770952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 10:02:04.771053 ==
6488 10:02:04.771145 RX Vref Scan: 0
6489 10:02:04.771232
6490 10:02:04.774586 RX Vref 0 -> 0, step: 1
6491 10:02:04.774682
6492 10:02:04.777987 RX Delay -410 -> 252, step: 16
6493 10:02:04.780811 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6494 10:02:04.787806 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6495 10:02:04.791041 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6496 10:02:04.794384 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6497 10:02:04.797531 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6498 10:02:04.804378 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6499 10:02:04.807728 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6500 10:02:04.810759 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6501 10:02:04.814110 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6502 10:02:04.820741 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6503 10:02:04.823988 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6504 10:02:04.827453 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6505 10:02:04.830684 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6506 10:02:04.837411 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6507 10:02:04.840705 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6508 10:02:04.843963 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6509 10:02:04.844038 ==
6510 10:02:04.847112 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 10:02:04.850665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 10:02:04.854178 ==
6513 10:02:04.854263 DQS Delay:
6514 10:02:04.854328 DQS0 = 43, DQS1 = 51
6515 10:02:04.857058 DQM Delay:
6516 10:02:04.857140 DQM0 = 11, DQM1 = 10
6517 10:02:04.860646 DQ Delay:
6518 10:02:04.860728 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6519 10:02:04.864275 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6520 10:02:04.867645 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6521 10:02:04.871205 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6522 10:02:04.871310
6523 10:02:04.871405
6524 10:02:04.871504 ==
6525 10:02:04.874195 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 10:02:04.880563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 10:02:04.880647 ==
6528 10:02:04.880712
6529 10:02:04.880773
6530 10:02:04.880831 TX Vref Scan disable
6531 10:02:04.883758 == TX Byte 0 ==
6532 10:02:04.887047 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6533 10:02:04.890432 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6534 10:02:04.894041 == TX Byte 1 ==
6535 10:02:04.897223 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6536 10:02:04.900439 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6537 10:02:04.900526 ==
6538 10:02:04.903685 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 10:02:04.910515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 10:02:04.910599 ==
6541 10:02:04.910664
6542 10:02:04.910725
6543 10:02:04.910784 TX Vref Scan disable
6544 10:02:04.913622 == TX Byte 0 ==
6545 10:02:04.916882 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6546 10:02:04.920205 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6547 10:02:04.923847 == TX Byte 1 ==
6548 10:02:04.926958 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6549 10:02:04.930473 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6550 10:02:04.930584
6551 10:02:04.933797 [DATLAT]
6552 10:02:04.933880 Freq=400, CH0 RK1
6553 10:02:04.933946
6554 10:02:04.937067 DATLAT Default: 0xe
6555 10:02:04.937149 0, 0xFFFF, sum = 0
6556 10:02:04.940472 1, 0xFFFF, sum = 0
6557 10:02:04.940556 2, 0xFFFF, sum = 0
6558 10:02:04.943771 3, 0xFFFF, sum = 0
6559 10:02:04.943855 4, 0xFFFF, sum = 0
6560 10:02:04.947139 5, 0xFFFF, sum = 0
6561 10:02:04.947224 6, 0xFFFF, sum = 0
6562 10:02:04.949940 7, 0xFFFF, sum = 0
6563 10:02:04.953800 8, 0xFFFF, sum = 0
6564 10:02:04.953884 9, 0xFFFF, sum = 0
6565 10:02:04.956839 10, 0xFFFF, sum = 0
6566 10:02:04.956923 11, 0xFFFF, sum = 0
6567 10:02:04.960617 12, 0xFFFF, sum = 0
6568 10:02:04.960702 13, 0x0, sum = 1
6569 10:02:04.963562 14, 0x0, sum = 2
6570 10:02:04.963645 15, 0x0, sum = 3
6571 10:02:04.966886 16, 0x0, sum = 4
6572 10:02:04.966971 best_step = 14
6573 10:02:04.967036
6574 10:02:04.967097 ==
6575 10:02:04.970113 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 10:02:04.973620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 10:02:04.973703 ==
6578 10:02:04.976489 RX Vref Scan: 0
6579 10:02:04.976571
6580 10:02:04.979653 RX Vref 0 -> 0, step: 1
6581 10:02:04.979736
6582 10:02:04.979802 RX Delay -343 -> 252, step: 8
6583 10:02:04.988862 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6584 10:02:04.992290 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6585 10:02:04.995578 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6586 10:02:05.002130 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6587 10:02:05.005636 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6588 10:02:05.008568 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6589 10:02:05.011882 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6590 10:02:05.018357 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6591 10:02:05.021497 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6592 10:02:05.025113 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6593 10:02:05.028279 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6594 10:02:05.035214 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6595 10:02:05.038330 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6596 10:02:05.041869 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6597 10:02:05.044712 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6598 10:02:05.051849 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6599 10:02:05.051933 ==
6600 10:02:05.054916 Dram Type= 6, Freq= 0, CH_0, rank 1
6601 10:02:05.058367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 10:02:05.058450 ==
6603 10:02:05.058516 DQS Delay:
6604 10:02:05.061627 DQS0 = 48, DQS1 = 60
6605 10:02:05.061709 DQM Delay:
6606 10:02:05.064684 DQM0 = 13, DQM1 = 13
6607 10:02:05.064767 DQ Delay:
6608 10:02:05.068285 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6609 10:02:05.071397 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6610 10:02:05.074696 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6611 10:02:05.077985 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6612 10:02:05.078068
6613 10:02:05.078133
6614 10:02:05.084665 [DQSOSCAuto] RK1, (LSB)MR18= 0x9669, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6615 10:02:05.088097 CH0 RK1: MR19=C0C, MR18=9669
6616 10:02:05.094844 CH0_RK1: MR19=0xC0C, MR18=0x9669, DQSOSC=391, MR23=63, INC=386, DEC=257
6617 10:02:05.098003 [RxdqsGatingPostProcess] freq 400
6618 10:02:05.104752 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6619 10:02:05.108139 best DQS0 dly(2T, 0.5T) = (0, 10)
6620 10:02:05.111094 best DQS1 dly(2T, 0.5T) = (0, 10)
6621 10:02:05.114631 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6622 10:02:05.118157 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6623 10:02:05.118240 best DQS0 dly(2T, 0.5T) = (0, 10)
6624 10:02:05.121034 best DQS1 dly(2T, 0.5T) = (0, 10)
6625 10:02:05.124250 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6626 10:02:05.127727 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6627 10:02:05.131183 Pre-setting of DQS Precalculation
6628 10:02:05.137671 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6629 10:02:05.137756 ==
6630 10:02:05.140802 Dram Type= 6, Freq= 0, CH_1, rank 0
6631 10:02:05.144028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 10:02:05.144113 ==
6633 10:02:05.150932 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6634 10:02:05.157903 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6635 10:02:05.160940 [CA 0] Center 36 (8~64) winsize 57
6636 10:02:05.163903 [CA 1] Center 36 (8~64) winsize 57
6637 10:02:05.163988 [CA 2] Center 36 (8~64) winsize 57
6638 10:02:05.167297 [CA 3] Center 36 (8~64) winsize 57
6639 10:02:05.170511 [CA 4] Center 36 (8~64) winsize 57
6640 10:02:05.173786 [CA 5] Center 36 (8~64) winsize 57
6641 10:02:05.173869
6642 10:02:05.177414 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6643 10:02:05.180667
6644 10:02:05.183933 [CATrainingPosCal] consider 1 rank data
6645 10:02:05.187087 u2DelayCellTimex100 = 270/100 ps
6646 10:02:05.190358 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 10:02:05.193595 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 10:02:05.197082 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 10:02:05.200508 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 10:02:05.203272 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 10:02:05.206742 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 10:02:05.206828
6653 10:02:05.210234 CA PerBit enable=1, Macro0, CA PI delay=36
6654 10:02:05.210319
6655 10:02:05.213509 [CBTSetCACLKResult] CA Dly = 36
6656 10:02:05.216847 CS Dly: 1 (0~32)
6657 10:02:05.216933 ==
6658 10:02:05.220313 Dram Type= 6, Freq= 0, CH_1, rank 1
6659 10:02:05.223776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 10:02:05.223863 ==
6661 10:02:05.230299 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6662 10:02:05.233136 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6663 10:02:05.237060 [CA 0] Center 36 (8~64) winsize 57
6664 10:02:05.239956 [CA 1] Center 36 (8~64) winsize 57
6665 10:02:05.243424 [CA 2] Center 36 (8~64) winsize 57
6666 10:02:05.246773 [CA 3] Center 36 (8~64) winsize 57
6667 10:02:05.249766 [CA 4] Center 36 (8~64) winsize 57
6668 10:02:05.253189 [CA 5] Center 36 (8~64) winsize 57
6669 10:02:05.253274
6670 10:02:05.256623 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6671 10:02:05.256709
6672 10:02:05.259585 [CATrainingPosCal] consider 2 rank data
6673 10:02:05.263109 u2DelayCellTimex100 = 270/100 ps
6674 10:02:05.266424 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 10:02:05.269700 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 10:02:05.276274 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 10:02:05.279551 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 10:02:05.283255 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 10:02:05.286389 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 10:02:05.286476
6681 10:02:05.289943 CA PerBit enable=1, Macro0, CA PI delay=36
6682 10:02:05.290029
6683 10:02:05.292966 [CBTSetCACLKResult] CA Dly = 36
6684 10:02:05.293051 CS Dly: 1 (0~32)
6685 10:02:05.293136
6686 10:02:05.299738 ----->DramcWriteLeveling(PI) begin...
6687 10:02:05.299825 ==
6688 10:02:05.302814 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 10:02:05.305900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 10:02:05.305987 ==
6691 10:02:05.309639 Write leveling (Byte 0): 40 => 8
6692 10:02:05.312848 Write leveling (Byte 1): 40 => 8
6693 10:02:05.316406 DramcWriteLeveling(PI) end<-----
6694 10:02:05.316491
6695 10:02:05.316576 ==
6696 10:02:05.319457 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 10:02:05.322654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 10:02:05.322741 ==
6699 10:02:05.326144 [Gating] SW mode calibration
6700 10:02:05.332734 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6701 10:02:05.338969 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6702 10:02:05.342502 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6703 10:02:05.345920 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6704 10:02:05.352744 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6705 10:02:05.355639 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6706 10:02:05.359050 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6707 10:02:05.365931 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 10:02:05.369151 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 10:02:05.372374 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 10:02:05.375811 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 10:02:05.378792 Total UI for P1: 0, mck2ui 16
6712 10:02:05.382041 best dqsien dly found for B0: ( 0, 14, 24)
6713 10:02:05.386140 Total UI for P1: 0, mck2ui 16
6714 10:02:05.388751 best dqsien dly found for B1: ( 0, 14, 24)
6715 10:02:05.391984 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6716 10:02:05.398612 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6717 10:02:05.398689
6718 10:02:05.402704 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6719 10:02:05.405263 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6720 10:02:05.408862 [Gating] SW calibration Done
6721 10:02:05.408945 ==
6722 10:02:05.411933 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 10:02:05.415247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 10:02:05.415330 ==
6725 10:02:05.418611 RX Vref Scan: 0
6726 10:02:05.418693
6727 10:02:05.418757 RX Vref 0 -> 0, step: 1
6728 10:02:05.418850
6729 10:02:05.422133 RX Delay -410 -> 252, step: 16
6730 10:02:05.425525 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6731 10:02:05.431704 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6732 10:02:05.435075 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6733 10:02:05.438660 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6734 10:02:05.441865 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6735 10:02:05.448704 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6736 10:02:05.451668 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6737 10:02:05.455324 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6738 10:02:05.458720 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6739 10:02:05.465502 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6740 10:02:05.468262 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6741 10:02:05.471616 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6742 10:02:05.478667 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6743 10:02:05.481979 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6744 10:02:05.484903 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6745 10:02:05.488079 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6746 10:02:05.488207 ==
6747 10:02:05.491493 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 10:02:05.498475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 10:02:05.498559 ==
6750 10:02:05.498624 DQS Delay:
6751 10:02:05.501572 DQS0 = 51, DQS1 = 59
6752 10:02:05.501655 DQM Delay:
6753 10:02:05.504967 DQM0 = 19, DQM1 = 16
6754 10:02:05.505048 DQ Delay:
6755 10:02:05.508388 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6756 10:02:05.511256 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6757 10:02:05.514986 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6758 10:02:05.518294 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6759 10:02:05.518376
6760 10:02:05.518441
6761 10:02:05.518501 ==
6762 10:02:05.521433 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 10:02:05.524914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 10:02:05.524998 ==
6765 10:02:05.525063
6766 10:02:05.525123
6767 10:02:05.528232 TX Vref Scan disable
6768 10:02:05.528350 == TX Byte 0 ==
6769 10:02:05.534582 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6770 10:02:05.538033 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6771 10:02:05.538115 == TX Byte 1 ==
6772 10:02:05.544535 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 10:02:05.548158 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 10:02:05.548267 ==
6775 10:02:05.551290 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 10:02:05.554639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 10:02:05.554724 ==
6778 10:02:05.554790
6779 10:02:05.554852
6780 10:02:05.558291 TX Vref Scan disable
6781 10:02:05.558373 == TX Byte 0 ==
6782 10:02:05.564567 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6783 10:02:05.568121 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6784 10:02:05.568204 == TX Byte 1 ==
6785 10:02:05.574719 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 10:02:05.578047 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 10:02:05.578130
6788 10:02:05.578195 [DATLAT]
6789 10:02:05.580872 Freq=400, CH1 RK0
6790 10:02:05.580955
6791 10:02:05.581020 DATLAT Default: 0xf
6792 10:02:05.584340 0, 0xFFFF, sum = 0
6793 10:02:05.584426 1, 0xFFFF, sum = 0
6794 10:02:05.587783 2, 0xFFFF, sum = 0
6795 10:02:05.587866 3, 0xFFFF, sum = 0
6796 10:02:05.591023 4, 0xFFFF, sum = 0
6797 10:02:05.591107 5, 0xFFFF, sum = 0
6798 10:02:05.594622 6, 0xFFFF, sum = 0
6799 10:02:05.594706 7, 0xFFFF, sum = 0
6800 10:02:05.597432 8, 0xFFFF, sum = 0
6801 10:02:05.601077 9, 0xFFFF, sum = 0
6802 10:02:05.601161 10, 0xFFFF, sum = 0
6803 10:02:05.604222 11, 0xFFFF, sum = 0
6804 10:02:05.604324 12, 0xFFFF, sum = 0
6805 10:02:05.607408 13, 0x0, sum = 1
6806 10:02:05.607506 14, 0x0, sum = 2
6807 10:02:05.610847 15, 0x0, sum = 3
6808 10:02:05.610932 16, 0x0, sum = 4
6809 10:02:05.610998 best_step = 14
6810 10:02:05.613971
6811 10:02:05.614054 ==
6812 10:02:05.617298 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 10:02:05.620879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 10:02:05.620963 ==
6815 10:02:05.621029 RX Vref Scan: 1
6816 10:02:05.621089
6817 10:02:05.624278 RX Vref 0 -> 0, step: 1
6818 10:02:05.624360
6819 10:02:05.627558 RX Delay -359 -> 252, step: 8
6820 10:02:05.627641
6821 10:02:05.630794 Set Vref, RX VrefLevel [Byte0]: 57
6822 10:02:05.634338 [Byte1]: 52
6823 10:02:05.638122
6824 10:02:05.638204 Final RX Vref Byte 0 = 57 to rank0
6825 10:02:05.641031 Final RX Vref Byte 1 = 52 to rank0
6826 10:02:05.644616 Final RX Vref Byte 0 = 57 to rank1
6827 10:02:05.647903 Final RX Vref Byte 1 = 52 to rank1==
6828 10:02:05.651310 Dram Type= 6, Freq= 0, CH_1, rank 0
6829 10:02:05.657692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 10:02:05.657776 ==
6831 10:02:05.657841 DQS Delay:
6832 10:02:05.661647 DQS0 = 48, DQS1 = 60
6833 10:02:05.661730 DQM Delay:
6834 10:02:05.661796 DQM0 = 12, DQM1 = 13
6835 10:02:05.664859 DQ Delay:
6836 10:02:05.667499 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6837 10:02:05.670915 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6838 10:02:05.670998 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6839 10:02:05.677883 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6840 10:02:05.677966
6841 10:02:05.678032
6842 10:02:05.683969 [DQSOSCAuto] RK0, (LSB)MR18= 0x8129, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6843 10:02:05.687915 CH1 RK0: MR19=C0C, MR18=8129
6844 10:02:05.693981 CH1_RK0: MR19=0xC0C, MR18=0x8129, DQSOSC=393, MR23=63, INC=382, DEC=254
6845 10:02:05.694065 ==
6846 10:02:05.697302 Dram Type= 6, Freq= 0, CH_1, rank 1
6847 10:02:05.700636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 10:02:05.700720 ==
6849 10:02:05.704132 [Gating] SW mode calibration
6850 10:02:05.710482 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6851 10:02:05.717411 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6852 10:02:05.720584 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6853 10:02:05.724479 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6854 10:02:05.730397 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6855 10:02:05.733987 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6856 10:02:05.737325 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6857 10:02:05.744025 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 10:02:05.747210 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 10:02:05.751050 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 10:02:05.756929 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 10:02:05.757013 Total UI for P1: 0, mck2ui 16
6862 10:02:05.763898 best dqsien dly found for B0: ( 0, 14, 24)
6863 10:02:05.763983 Total UI for P1: 0, mck2ui 16
6864 10:02:05.769843 best dqsien dly found for B1: ( 0, 14, 24)
6865 10:02:05.773345 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6866 10:02:05.776672 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6867 10:02:05.776756
6868 10:02:05.779735 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6869 10:02:05.782958 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6870 10:02:05.786572 [Gating] SW calibration Done
6871 10:02:05.786655 ==
6872 10:02:05.790117 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 10:02:05.793081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 10:02:05.793165 ==
6875 10:02:05.796538 RX Vref Scan: 0
6876 10:02:05.796620
6877 10:02:05.796685 RX Vref 0 -> 0, step: 1
6878 10:02:05.800067
6879 10:02:05.800150 RX Delay -410 -> 252, step: 16
6880 10:02:05.806272 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6881 10:02:05.810033 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6882 10:02:05.813287 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6883 10:02:05.816522 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6884 10:02:05.822791 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6885 10:02:05.826187 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6886 10:02:05.829433 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6887 10:02:05.833113 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6888 10:02:05.839597 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6889 10:02:05.842942 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6890 10:02:05.846547 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6891 10:02:05.849652 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6892 10:02:05.856792 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6893 10:02:05.859828 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6894 10:02:05.863061 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6895 10:02:05.869387 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6896 10:02:05.869471 ==
6897 10:02:05.872711 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 10:02:05.876284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 10:02:05.876369 ==
6900 10:02:05.876436 DQS Delay:
6901 10:02:05.879646 DQS0 = 43, DQS1 = 59
6902 10:02:05.879730 DQM Delay:
6903 10:02:05.883070 DQM0 = 11, DQM1 = 17
6904 10:02:05.883154 DQ Delay:
6905 10:02:05.886691 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6906 10:02:05.889555 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6907 10:02:05.892827 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6908 10:02:05.896327 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6909 10:02:05.896411
6910 10:02:05.896477
6911 10:02:05.896538 ==
6912 10:02:05.899489 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 10:02:05.902597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 10:02:05.902682 ==
6915 10:02:05.902748
6916 10:02:05.902810
6917 10:02:05.905950 TX Vref Scan disable
6918 10:02:05.906034 == TX Byte 0 ==
6919 10:02:05.912772 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6920 10:02:05.915835 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6921 10:02:05.915923 == TX Byte 1 ==
6922 10:02:05.922748 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6923 10:02:05.925827 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6924 10:02:05.925911 ==
6925 10:02:05.929090 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 10:02:05.932808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 10:02:05.932892 ==
6928 10:02:05.932959
6929 10:02:05.933021
6930 10:02:05.935833 TX Vref Scan disable
6931 10:02:05.935917 == TX Byte 0 ==
6932 10:02:05.942616 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6933 10:02:05.945775 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6934 10:02:05.945859 == TX Byte 1 ==
6935 10:02:05.952769 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6936 10:02:05.955906 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6937 10:02:05.955990
6938 10:02:05.956057 [DATLAT]
6939 10:02:05.959331 Freq=400, CH1 RK1
6940 10:02:05.959459
6941 10:02:05.959526 DATLAT Default: 0xe
6942 10:02:05.962665 0, 0xFFFF, sum = 0
6943 10:02:05.962750 1, 0xFFFF, sum = 0
6944 10:02:05.966455 2, 0xFFFF, sum = 0
6945 10:02:05.966540 3, 0xFFFF, sum = 0
6946 10:02:05.969097 4, 0xFFFF, sum = 0
6947 10:02:05.969183 5, 0xFFFF, sum = 0
6948 10:02:05.972237 6, 0xFFFF, sum = 0
6949 10:02:05.972322 7, 0xFFFF, sum = 0
6950 10:02:05.976107 8, 0xFFFF, sum = 0
6951 10:02:05.976193 9, 0xFFFF, sum = 0
6952 10:02:05.978868 10, 0xFFFF, sum = 0
6953 10:02:05.978953 11, 0xFFFF, sum = 0
6954 10:02:05.982208 12, 0xFFFF, sum = 0
6955 10:02:05.982293 13, 0x0, sum = 1
6956 10:02:05.986262 14, 0x0, sum = 2
6957 10:02:05.986347 15, 0x0, sum = 3
6958 10:02:05.989226 16, 0x0, sum = 4
6959 10:02:05.989311 best_step = 14
6960 10:02:05.989379
6961 10:02:05.989441 ==
6962 10:02:05.992567 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 10:02:05.998896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 10:02:05.998981 ==
6965 10:02:05.999046 RX Vref Scan: 0
6966 10:02:05.999106
6967 10:02:06.002465 RX Vref 0 -> 0, step: 1
6968 10:02:06.002548
6969 10:02:06.005795 RX Delay -359 -> 252, step: 8
6970 10:02:06.012800 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6971 10:02:06.015740 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6972 10:02:06.018956 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6973 10:02:06.022199 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6974 10:02:06.028993 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6975 10:02:06.032101 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6976 10:02:06.035983 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6977 10:02:06.038814 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6978 10:02:06.045207 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6979 10:02:06.048585 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6980 10:02:06.052152 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6981 10:02:06.059046 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6982 10:02:06.061722 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6983 10:02:06.065041 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6984 10:02:06.068735 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6985 10:02:06.075318 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6986 10:02:06.075447 ==
6987 10:02:06.078565 Dram Type= 6, Freq= 0, CH_1, rank 1
6988 10:02:06.081713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6989 10:02:06.081814 ==
6990 10:02:06.081913 DQS Delay:
6991 10:02:06.085201 DQS0 = 52, DQS1 = 56
6992 10:02:06.085283 DQM Delay:
6993 10:02:06.088646 DQM0 = 13, DQM1 = 9
6994 10:02:06.088756 DQ Delay:
6995 10:02:06.092330 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6996 10:02:06.095521 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6997 10:02:06.098673 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6998 10:02:06.102040 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6999 10:02:06.102144
7000 10:02:06.102238
7001 10:02:06.108425 [DQSOSCAuto] RK1, (LSB)MR18= 0x758c, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
7002 10:02:06.112007 CH1 RK1: MR19=C0C, MR18=758C
7003 10:02:06.118479 CH1_RK1: MR19=0xC0C, MR18=0x758C, DQSOSC=392, MR23=63, INC=384, DEC=256
7004 10:02:06.121927 [RxdqsGatingPostProcess] freq 400
7005 10:02:06.128536 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7006 10:02:06.128642 best DQS0 dly(2T, 0.5T) = (0, 10)
7007 10:02:06.131536 best DQS1 dly(2T, 0.5T) = (0, 10)
7008 10:02:06.135211 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7009 10:02:06.138481 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7010 10:02:06.141582 best DQS0 dly(2T, 0.5T) = (0, 10)
7011 10:02:06.144976 best DQS1 dly(2T, 0.5T) = (0, 10)
7012 10:02:06.148420 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7013 10:02:06.151762 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7014 10:02:06.154748 Pre-setting of DQS Precalculation
7015 10:02:06.158577 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7016 10:02:06.168159 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7017 10:02:06.175013 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7018 10:02:06.175121
7019 10:02:06.175226
7020 10:02:06.178740 [Calibration Summary] 800 Mbps
7021 10:02:06.178857 CH 0, Rank 0
7022 10:02:06.181576 SW Impedance : PASS
7023 10:02:06.181679 DUTY Scan : NO K
7024 10:02:06.185114 ZQ Calibration : PASS
7025 10:02:06.188104 Jitter Meter : NO K
7026 10:02:06.188214 CBT Training : PASS
7027 10:02:06.191495 Write leveling : PASS
7028 10:02:06.194937 RX DQS gating : PASS
7029 10:02:06.195022 RX DQ/DQS(RDDQC) : PASS
7030 10:02:06.198736 TX DQ/DQS : PASS
7031 10:02:06.202049 RX DATLAT : PASS
7032 10:02:06.202153 RX DQ/DQS(Engine): PASS
7033 10:02:06.204814 TX OE : NO K
7034 10:02:06.204904 All Pass.
7035 10:02:06.204986
7036 10:02:06.208648 CH 0, Rank 1
7037 10:02:06.208731 SW Impedance : PASS
7038 10:02:06.211608 DUTY Scan : NO K
7039 10:02:06.214980 ZQ Calibration : PASS
7040 10:02:06.215086 Jitter Meter : NO K
7041 10:02:06.218029 CBT Training : PASS
7042 10:02:06.218139 Write leveling : NO K
7043 10:02:06.221565 RX DQS gating : PASS
7044 10:02:06.224929 RX DQ/DQS(RDDQC) : PASS
7045 10:02:06.225040 TX DQ/DQS : PASS
7046 10:02:06.228440 RX DATLAT : PASS
7047 10:02:06.231658 RX DQ/DQS(Engine): PASS
7048 10:02:06.231762 TX OE : NO K
7049 10:02:06.234550 All Pass.
7050 10:02:06.234628
7051 10:02:06.234714 CH 1, Rank 0
7052 10:02:06.237987 SW Impedance : PASS
7053 10:02:06.238099 DUTY Scan : NO K
7054 10:02:06.241144 ZQ Calibration : PASS
7055 10:02:06.244914 Jitter Meter : NO K
7056 10:02:06.245069 CBT Training : PASS
7057 10:02:06.248049 Write leveling : PASS
7058 10:02:06.251345 RX DQS gating : PASS
7059 10:02:06.251467 RX DQ/DQS(RDDQC) : PASS
7060 10:02:06.254451 TX DQ/DQS : PASS
7061 10:02:06.257731 RX DATLAT : PASS
7062 10:02:06.257845 RX DQ/DQS(Engine): PASS
7063 10:02:06.261066 TX OE : NO K
7064 10:02:06.261184 All Pass.
7065 10:02:06.261282
7066 10:02:06.264267 CH 1, Rank 1
7067 10:02:06.264373 SW Impedance : PASS
7068 10:02:06.267591 DUTY Scan : NO K
7069 10:02:06.271280 ZQ Calibration : PASS
7070 10:02:06.271411 Jitter Meter : NO K
7071 10:02:06.274611 CBT Training : PASS
7072 10:02:06.277719 Write leveling : NO K
7073 10:02:06.277828 RX DQS gating : PASS
7074 10:02:06.281305 RX DQ/DQS(RDDQC) : PASS
7075 10:02:06.281406 TX DQ/DQS : PASS
7076 10:02:06.284627 RX DATLAT : PASS
7077 10:02:06.287756 RX DQ/DQS(Engine): PASS
7078 10:02:06.287837 TX OE : NO K
7079 10:02:06.290993 All Pass.
7080 10:02:06.291094
7081 10:02:06.291186 DramC Write-DBI off
7082 10:02:06.294485 PER_BANK_REFRESH: Hybrid Mode
7083 10:02:06.297575 TX_TRACKING: ON
7084 10:02:06.304734 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7085 10:02:06.307275 [FAST_K] Save calibration result to emmc
7086 10:02:06.314393 dramc_set_vcore_voltage set vcore to 725000
7087 10:02:06.314499 Read voltage for 1600, 0
7088 10:02:06.317229 Vio18 = 0
7089 10:02:06.317330 Vcore = 725000
7090 10:02:06.317427 Vdram = 0
7091 10:02:06.317517 Vddq = 0
7092 10:02:06.321400 Vmddr = 0
7093 10:02:06.324097 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7094 10:02:06.330786 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7095 10:02:06.334113 MEM_TYPE=3, freq_sel=13
7096 10:02:06.334228 sv_algorithm_assistance_LP4_3733
7097 10:02:06.340945 ============ PULL DRAM RESETB DOWN ============
7098 10:02:06.343934 ========== PULL DRAM RESETB DOWN end =========
7099 10:02:06.347035 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7100 10:02:06.350359 ===================================
7101 10:02:06.353836 LPDDR4 DRAM CONFIGURATION
7102 10:02:06.356961 ===================================
7103 10:02:06.360416 EX_ROW_EN[0] = 0x0
7104 10:02:06.360530 EX_ROW_EN[1] = 0x0
7105 10:02:06.363908 LP4Y_EN = 0x0
7106 10:02:06.364019 WORK_FSP = 0x1
7107 10:02:06.367844 WL = 0x5
7108 10:02:06.367947 RL = 0x5
7109 10:02:06.370753 BL = 0x2
7110 10:02:06.370853 RPST = 0x0
7111 10:02:06.374155 RD_PRE = 0x0
7112 10:02:06.374307 WR_PRE = 0x1
7113 10:02:06.377227 WR_PST = 0x1
7114 10:02:06.377336 DBI_WR = 0x0
7115 10:02:06.380295 DBI_RD = 0x0
7116 10:02:06.380397 OTF = 0x1
7117 10:02:06.384347 ===================================
7118 10:02:06.386965 ===================================
7119 10:02:06.390433 ANA top config
7120 10:02:06.394158 ===================================
7121 10:02:06.397205 DLL_ASYNC_EN = 0
7122 10:02:06.397301 ALL_SLAVE_EN = 0
7123 10:02:06.400619 NEW_RANK_MODE = 1
7124 10:02:06.403552 DLL_IDLE_MODE = 1
7125 10:02:06.407009 LP45_APHY_COMB_EN = 1
7126 10:02:06.410535 TX_ODT_DIS = 0
7127 10:02:06.410659 NEW_8X_MODE = 1
7128 10:02:06.413688 ===================================
7129 10:02:06.417107 ===================================
7130 10:02:06.420153 data_rate = 3200
7131 10:02:06.423737 CKR = 1
7132 10:02:06.427237 DQ_P2S_RATIO = 8
7133 10:02:06.430087 ===================================
7134 10:02:06.433335 CA_P2S_RATIO = 8
7135 10:02:06.433436 DQ_CA_OPEN = 0
7136 10:02:06.436645 DQ_SEMI_OPEN = 0
7137 10:02:06.440135 CA_SEMI_OPEN = 0
7138 10:02:06.443562 CA_FULL_RATE = 0
7139 10:02:06.447331 DQ_CKDIV4_EN = 0
7140 10:02:06.450390 CA_CKDIV4_EN = 0
7141 10:02:06.450495 CA_PREDIV_EN = 0
7142 10:02:06.453231 PH8_DLY = 12
7143 10:02:06.457081 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7144 10:02:06.460244 DQ_AAMCK_DIV = 4
7145 10:02:06.463403 CA_AAMCK_DIV = 4
7146 10:02:06.467237 CA_ADMCK_DIV = 4
7147 10:02:06.467342 DQ_TRACK_CA_EN = 0
7148 10:02:06.469883 CA_PICK = 1600
7149 10:02:06.473629 CA_MCKIO = 1600
7150 10:02:06.477032 MCKIO_SEMI = 0
7151 10:02:06.479982 PLL_FREQ = 3068
7152 10:02:06.483222 DQ_UI_PI_RATIO = 32
7153 10:02:06.486886 CA_UI_PI_RATIO = 0
7154 10:02:06.489843 ===================================
7155 10:02:06.493166 ===================================
7156 10:02:06.493277 memory_type:LPDDR4
7157 10:02:06.496607 GP_NUM : 10
7158 10:02:06.499916 SRAM_EN : 1
7159 10:02:06.500021 MD32_EN : 0
7160 10:02:06.503260 ===================================
7161 10:02:06.506788 [ANA_INIT] >>>>>>>>>>>>>>
7162 10:02:06.509641 <<<<<< [CONFIGURE PHASE]: ANA_TX
7163 10:02:06.513103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7164 10:02:06.516377 ===================================
7165 10:02:06.519792 data_rate = 3200,PCW = 0X7600
7166 10:02:06.523190 ===================================
7167 10:02:06.526625 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7168 10:02:06.529701 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7169 10:02:06.536707 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7170 10:02:06.539836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7171 10:02:06.542882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7172 10:02:06.546323 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7173 10:02:06.549543 [ANA_INIT] flow start
7174 10:02:06.553170 [ANA_INIT] PLL >>>>>>>>
7175 10:02:06.553281 [ANA_INIT] PLL <<<<<<<<
7176 10:02:06.556556 [ANA_INIT] MIDPI >>>>>>>>
7177 10:02:06.559525 [ANA_INIT] MIDPI <<<<<<<<
7178 10:02:06.563633 [ANA_INIT] DLL >>>>>>>>
7179 10:02:06.563740 [ANA_INIT] DLL <<<<<<<<
7180 10:02:06.566551 [ANA_INIT] flow end
7181 10:02:06.569481 ============ LP4 DIFF to SE enter ============
7182 10:02:06.572995 ============ LP4 DIFF to SE exit ============
7183 10:02:06.576251 [ANA_INIT] <<<<<<<<<<<<<
7184 10:02:06.579814 [Flow] Enable top DCM control >>>>>
7185 10:02:06.583162 [Flow] Enable top DCM control <<<<<
7186 10:02:06.586694 Enable DLL master slave shuffle
7187 10:02:06.592773 ==============================================================
7188 10:02:06.592884 Gating Mode config
7189 10:02:06.599565 ==============================================================
7190 10:02:06.599650 Config description:
7191 10:02:06.609362 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7192 10:02:06.616765 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7193 10:02:06.622456 SELPH_MODE 0: By rank 1: By Phase
7194 10:02:06.625999 ==============================================================
7195 10:02:06.629442 GAT_TRACK_EN = 1
7196 10:02:06.632463 RX_GATING_MODE = 2
7197 10:02:06.635883 RX_GATING_TRACK_MODE = 2
7198 10:02:06.639599 SELPH_MODE = 1
7199 10:02:06.642543 PICG_EARLY_EN = 1
7200 10:02:06.646004 VALID_LAT_VALUE = 1
7201 10:02:06.649643 ==============================================================
7202 10:02:06.652653 Enter into Gating configuration >>>>
7203 10:02:06.656103 Exit from Gating configuration <<<<
7204 10:02:06.659284 Enter into DVFS_PRE_config >>>>>
7205 10:02:06.672578 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7206 10:02:06.675754 Exit from DVFS_PRE_config <<<<<
7207 10:02:06.679013 Enter into PICG configuration >>>>
7208 10:02:06.682912 Exit from PICG configuration <<<<
7209 10:02:06.683020 [RX_INPUT] configuration >>>>>
7210 10:02:06.685947 [RX_INPUT] configuration <<<<<
7211 10:02:06.692584 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7212 10:02:06.695958 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7213 10:02:06.703010 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7214 10:02:06.709046 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7215 10:02:06.715953 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7216 10:02:06.722700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7217 10:02:06.725995 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7218 10:02:06.729394 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7219 10:02:06.732176 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7220 10:02:06.739019 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7221 10:02:06.742703 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7222 10:02:06.745902 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7223 10:02:06.748868 ===================================
7224 10:02:06.752731 LPDDR4 DRAM CONFIGURATION
7225 10:02:06.755716 ===================================
7226 10:02:06.759269 EX_ROW_EN[0] = 0x0
7227 10:02:06.759400 EX_ROW_EN[1] = 0x0
7228 10:02:06.762535 LP4Y_EN = 0x0
7229 10:02:06.762613 WORK_FSP = 0x1
7230 10:02:06.765963 WL = 0x5
7231 10:02:06.766066 RL = 0x5
7232 10:02:06.769221 BL = 0x2
7233 10:02:06.769331 RPST = 0x0
7234 10:02:06.772201 RD_PRE = 0x0
7235 10:02:06.772309 WR_PRE = 0x1
7236 10:02:06.775722 WR_PST = 0x1
7237 10:02:06.775815 DBI_WR = 0x0
7238 10:02:06.778899 DBI_RD = 0x0
7239 10:02:06.778971 OTF = 0x1
7240 10:02:06.782317 ===================================
7241 10:02:06.789064 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7242 10:02:06.792012 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7243 10:02:06.795774 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7244 10:02:06.798946 ===================================
7245 10:02:06.801772 LPDDR4 DRAM CONFIGURATION
7246 10:02:06.805395 ===================================
7247 10:02:06.808584 EX_ROW_EN[0] = 0x10
7248 10:02:06.808684 EX_ROW_EN[1] = 0x0
7249 10:02:06.812291 LP4Y_EN = 0x0
7250 10:02:06.812367 WORK_FSP = 0x1
7251 10:02:06.815625 WL = 0x5
7252 10:02:06.815727 RL = 0x5
7253 10:02:06.818428 BL = 0x2
7254 10:02:06.818537 RPST = 0x0
7255 10:02:06.822050 RD_PRE = 0x0
7256 10:02:06.822162 WR_PRE = 0x1
7257 10:02:06.825634 WR_PST = 0x1
7258 10:02:06.825738 DBI_WR = 0x0
7259 10:02:06.828547 DBI_RD = 0x0
7260 10:02:06.828654 OTF = 0x1
7261 10:02:06.832591 ===================================
7262 10:02:06.838548 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7263 10:02:06.838667 ==
7264 10:02:06.841884 Dram Type= 6, Freq= 0, CH_0, rank 0
7265 10:02:06.848221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7266 10:02:06.848342 ==
7267 10:02:06.848438 [Duty_Offset_Calibration]
7268 10:02:06.851600 B0:2 B1:-1 CA:1
7269 10:02:06.851721
7270 10:02:06.855156 [DutyScan_Calibration_Flow] k_type=0
7271 10:02:06.863495
7272 10:02:06.863615 ==CLK 0==
7273 10:02:06.867195 Final CLK duty delay cell = -4
7274 10:02:06.870164 [-4] MAX Duty = 5031%(X100), DQS PI = 6
7275 10:02:06.873275 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7276 10:02:06.877246 [-4] AVG Duty = 4937%(X100)
7277 10:02:06.877334
7278 10:02:06.880262 CH0 CLK Duty spec in!! Max-Min= 187%
7279 10:02:06.883297 [DutyScan_Calibration_Flow] ====Done====
7280 10:02:06.883426
7281 10:02:06.887025 [DutyScan_Calibration_Flow] k_type=1
7282 10:02:06.903045
7283 10:02:06.903154 ==DQS 0 ==
7284 10:02:06.906284 Final DQS duty delay cell = 0
7285 10:02:06.909346 [0] MAX Duty = 5125%(X100), DQS PI = 22
7286 10:02:06.912983 [0] MIN Duty = 5000%(X100), DQS PI = 32
7287 10:02:06.915974 [0] AVG Duty = 5062%(X100)
7288 10:02:06.916071
7289 10:02:06.916137 ==DQS 1 ==
7290 10:02:06.919892 Final DQS duty delay cell = -4
7291 10:02:06.922664 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7292 10:02:06.926253 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7293 10:02:06.929821 [-4] AVG Duty = 5046%(X100)
7294 10:02:06.929904
7295 10:02:06.933144 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7296 10:02:06.933227
7297 10:02:06.936310 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7298 10:02:06.939137 [DutyScan_Calibration_Flow] ====Done====
7299 10:02:06.939221
7300 10:02:06.942996 [DutyScan_Calibration_Flow] k_type=3
7301 10:02:06.960928
7302 10:02:06.961030 ==DQM 0 ==
7303 10:02:06.963691 Final DQM duty delay cell = 0
7304 10:02:06.966740 [0] MAX Duty = 5000%(X100), DQS PI = 18
7305 10:02:06.970065 [0] MIN Duty = 4875%(X100), DQS PI = 4
7306 10:02:06.970150 [0] AVG Duty = 4937%(X100)
7307 10:02:06.973882
7308 10:02:06.973967 ==DQM 1 ==
7309 10:02:06.976676 Final DQM duty delay cell = 0
7310 10:02:06.979972 [0] MAX Duty = 5187%(X100), DQS PI = 58
7311 10:02:06.983901 [0] MIN Duty = 4969%(X100), DQS PI = 20
7312 10:02:06.986674 [0] AVG Duty = 5078%(X100)
7313 10:02:06.986757
7314 10:02:06.990032 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7315 10:02:06.990115
7316 10:02:06.993453 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7317 10:02:06.996921 [DutyScan_Calibration_Flow] ====Done====
7318 10:02:06.997004
7319 10:02:06.999790 [DutyScan_Calibration_Flow] k_type=2
7320 10:02:07.016758
7321 10:02:07.016841 ==DQ 0 ==
7322 10:02:07.019758 Final DQ duty delay cell = -4
7323 10:02:07.023079 [-4] MAX Duty = 5062%(X100), DQS PI = 56
7324 10:02:07.026613 [-4] MIN Duty = 4844%(X100), DQS PI = 26
7325 10:02:07.029689 [-4] AVG Duty = 4953%(X100)
7326 10:02:07.029771
7327 10:02:07.029836 ==DQ 1 ==
7328 10:02:07.032817 Final DQ duty delay cell = 0
7329 10:02:07.036263 [0] MAX Duty = 5031%(X100), DQS PI = 30
7330 10:02:07.039839 [0] MIN Duty = 4907%(X100), DQS PI = 18
7331 10:02:07.042820 [0] AVG Duty = 4969%(X100)
7332 10:02:07.042904
7333 10:02:07.046273 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7334 10:02:07.046355
7335 10:02:07.049499 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7336 10:02:07.052948 [DutyScan_Calibration_Flow] ====Done====
7337 10:02:07.053068 ==
7338 10:02:07.056309 Dram Type= 6, Freq= 0, CH_1, rank 0
7339 10:02:07.059617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7340 10:02:07.059700 ==
7341 10:02:07.063101 [Duty_Offset_Calibration]
7342 10:02:07.063211 B0:1 B1:1 CA:2
7343 10:02:07.063275
7344 10:02:07.066724 [DutyScan_Calibration_Flow] k_type=0
7345 10:02:07.076758
7346 10:02:07.076839 ==CLK 0==
7347 10:02:07.080218 Final CLK duty delay cell = 0
7348 10:02:07.083641 [0] MAX Duty = 5187%(X100), DQS PI = 24
7349 10:02:07.086879 [0] MIN Duty = 4938%(X100), DQS PI = 50
7350 10:02:07.086960 [0] AVG Duty = 5062%(X100)
7351 10:02:07.090299
7352 10:02:07.093819 CH1 CLK Duty spec in!! Max-Min= 249%
7353 10:02:07.096625 [DutyScan_Calibration_Flow] ====Done====
7354 10:02:07.096706
7355 10:02:07.100146 [DutyScan_Calibration_Flow] k_type=1
7356 10:02:07.116942
7357 10:02:07.117056 ==DQS 0 ==
7358 10:02:07.119863 Final DQS duty delay cell = 0
7359 10:02:07.123171 [0] MAX Duty = 5062%(X100), DQS PI = 20
7360 10:02:07.126672 [0] MIN Duty = 4813%(X100), DQS PI = 52
7361 10:02:07.130257 [0] AVG Duty = 4937%(X100)
7362 10:02:07.130369
7363 10:02:07.130436 ==DQS 1 ==
7364 10:02:07.133710 Final DQS duty delay cell = 0
7365 10:02:07.136563 [0] MAX Duty = 5062%(X100), DQS PI = 34
7366 10:02:07.140096 [0] MIN Duty = 4938%(X100), DQS PI = 12
7367 10:02:07.143236 [0] AVG Duty = 5000%(X100)
7368 10:02:07.143369
7369 10:02:07.146408 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7370 10:02:07.146491
7371 10:02:07.149907 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7372 10:02:07.153161 [DutyScan_Calibration_Flow] ====Done====
7373 10:02:07.153281
7374 10:02:07.156589 [DutyScan_Calibration_Flow] k_type=3
7375 10:02:07.173669
7376 10:02:07.173751 ==DQM 0 ==
7377 10:02:07.176670 Final DQM duty delay cell = 0
7378 10:02:07.180154 [0] MAX Duty = 5156%(X100), DQS PI = 22
7379 10:02:07.183557 [0] MIN Duty = 4844%(X100), DQS PI = 50
7380 10:02:07.187082 [0] AVG Duty = 5000%(X100)
7381 10:02:07.187164
7382 10:02:07.187230 ==DQM 1 ==
7383 10:02:07.190401 Final DQM duty delay cell = 0
7384 10:02:07.193471 [0] MAX Duty = 5156%(X100), DQS PI = 60
7385 10:02:07.196380 [0] MIN Duty = 4875%(X100), DQS PI = 20
7386 10:02:07.199762 [0] AVG Duty = 5015%(X100)
7387 10:02:07.199846
7388 10:02:07.203075 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7389 10:02:07.203159
7390 10:02:07.206549 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7391 10:02:07.210006 [DutyScan_Calibration_Flow] ====Done====
7392 10:02:07.210089
7393 10:02:07.213085 [DutyScan_Calibration_Flow] k_type=2
7394 10:02:07.230587
7395 10:02:07.230671 ==DQ 0 ==
7396 10:02:07.233897 Final DQ duty delay cell = 0
7397 10:02:07.237123 [0] MAX Duty = 5156%(X100), DQS PI = 22
7398 10:02:07.240545 [0] MIN Duty = 4907%(X100), DQS PI = 52
7399 10:02:07.240628 [0] AVG Duty = 5031%(X100)
7400 10:02:07.240694
7401 10:02:07.244253 ==DQ 1 ==
7402 10:02:07.247242 Final DQ duty delay cell = 0
7403 10:02:07.250559 [0] MAX Duty = 5093%(X100), DQS PI = 6
7404 10:02:07.253764 [0] MIN Duty = 5031%(X100), DQS PI = 0
7405 10:02:07.253840 [0] AVG Duty = 5062%(X100)
7406 10:02:07.253911
7407 10:02:07.257303 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7408 10:02:07.257381
7409 10:02:07.260267 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7410 10:02:07.267016 [DutyScan_Calibration_Flow] ====Done====
7411 10:02:07.270629 nWR fixed to 30
7412 10:02:07.270716 [ModeRegInit_LP4] CH0 RK0
7413 10:02:07.273446 [ModeRegInit_LP4] CH0 RK1
7414 10:02:07.276844 [ModeRegInit_LP4] CH1 RK0
7415 10:02:07.276919 [ModeRegInit_LP4] CH1 RK1
7416 10:02:07.280464 match AC timing 5
7417 10:02:07.283761 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7418 10:02:07.287095 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7419 10:02:07.293538 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7420 10:02:07.297346 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7421 10:02:07.303664 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7422 10:02:07.303741 [MiockJmeterHQA]
7423 10:02:07.303806
7424 10:02:07.307056 [DramcMiockJmeter] u1RxGatingPI = 0
7425 10:02:07.310019 0 : 4366, 4137
7426 10:02:07.310093 4 : 4252, 4027
7427 10:02:07.310176 8 : 4252, 4026
7428 10:02:07.313958 12 : 4257, 4032
7429 10:02:07.314044 16 : 4252, 4027
7430 10:02:07.316994 20 : 4363, 4137
7431 10:02:07.317076 24 : 4363, 4138
7432 10:02:07.320222 28 : 4250, 4027
7433 10:02:07.320299 32 : 4253, 4026
7434 10:02:07.323315 36 : 4361, 4137
7435 10:02:07.323434 40 : 4252, 4027
7436 10:02:07.323500 44 : 4361, 4137
7437 10:02:07.326777 48 : 4252, 4029
7438 10:02:07.326850 52 : 4250, 4026
7439 10:02:07.330191 56 : 4253, 4029
7440 10:02:07.330270 60 : 4252, 4029
7441 10:02:07.333457 64 : 4257, 4032
7442 10:02:07.333535 68 : 4255, 4029
7443 10:02:07.333600 72 : 4250, 4026
7444 10:02:07.336522 76 : 4253, 4026
7445 10:02:07.336595 80 : 4360, 4138
7446 10:02:07.339956 84 : 4252, 4027
7447 10:02:07.340027 88 : 4361, 4137
7448 10:02:07.343549 92 : 4250, 4027
7449 10:02:07.343620 96 : 4250, 3343
7450 10:02:07.346751 100 : 4250, 0
7451 10:02:07.346828 104 : 4368, 0
7452 10:02:07.346892 108 : 4252, 0
7453 10:02:07.350225 112 : 4253, 0
7454 10:02:07.350295 116 : 4250, 0
7455 10:02:07.350355 120 : 4254, 0
7456 10:02:07.353646 124 : 4249, 0
7457 10:02:07.353721 128 : 4250, 0
7458 10:02:07.356678 132 : 4254, 0
7459 10:02:07.356746 136 : 4249, 0
7460 10:02:07.356808 140 : 4253, 0
7461 10:02:07.360346 144 : 4250, 0
7462 10:02:07.360416 148 : 4253, 0
7463 10:02:07.363104 152 : 4361, 0
7464 10:02:07.363173 156 : 4360, 0
7465 10:02:07.363232 160 : 4255, 0
7466 10:02:07.366527 164 : 4250, 0
7467 10:02:07.366596 168 : 4252, 0
7468 10:02:07.369837 172 : 4257, 0
7469 10:02:07.369903 176 : 4254, 0
7470 10:02:07.369963 180 : 4252, 0
7471 10:02:07.373305 184 : 4255, 0
7472 10:02:07.373370 188 : 4363, 0
7473 10:02:07.373433 192 : 4363, 0
7474 10:02:07.377126 196 : 4252, 0
7475 10:02:07.377196 200 : 4250, 0
7476 10:02:07.380077 204 : 4363, 0
7477 10:02:07.380146 208 : 4250, 0
7478 10:02:07.380205 212 : 4252, 206
7479 10:02:07.383169 216 : 4253, 3895
7480 10:02:07.383234 220 : 4361, 4137
7481 10:02:07.386411 224 : 4365, 4140
7482 10:02:07.386524 228 : 4252, 4029
7483 10:02:07.389654 232 : 4250, 4026
7484 10:02:07.389731 236 : 4255, 4029
7485 10:02:07.393754 240 : 4250, 4027
7486 10:02:07.393829 244 : 4257, 4034
7487 10:02:07.396506 248 : 4250, 4027
7488 10:02:07.396592 252 : 4255, 4030
7489 10:02:07.400052 256 : 4255, 4029
7490 10:02:07.400138 260 : 4257, 4031
7491 10:02:07.403134 264 : 4255, 4029
7492 10:02:07.403247 268 : 4250, 4027
7493 10:02:07.403359 272 : 4363, 4140
7494 10:02:07.406631 276 : 4360, 4138
7495 10:02:07.406717 280 : 4252, 4026
7496 10:02:07.410218 284 : 4366, 4142
7497 10:02:07.410347 288 : 4250, 4027
7498 10:02:07.413338 292 : 4250, 4027
7499 10:02:07.413424 296 : 4250, 4026
7500 10:02:07.416386 300 : 4360, 4138
7501 10:02:07.416472 304 : 4253, 4029
7502 10:02:07.419612 308 : 4252, 4027
7503 10:02:07.419702 312 : 4363, 4140
7504 10:02:07.423075 316 : 4254, 4030
7505 10:02:07.423187 320 : 4250, 4027
7506 10:02:07.426160 324 : 4361, 4137
7507 10:02:07.426246 328 : 4252, 4027
7508 10:02:07.426331 332 : 4249, 2786
7509 10:02:07.430261 336 : 4363, 39
7510 10:02:07.430350
7511 10:02:07.433009 MIOCK jitter meter ch=0
7512 10:02:07.433091
7513 10:02:07.433157 1T = (336-100) = 236 dly cells
7514 10:02:07.439946 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7515 10:02:07.440029 ==
7516 10:02:07.442963 Dram Type= 6, Freq= 0, CH_0, rank 0
7517 10:02:07.446462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7518 10:02:07.449600 ==
7519 10:02:07.453231 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7520 10:02:07.456576 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7521 10:02:07.462798 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7522 10:02:07.466294 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7523 10:02:07.477005 [CA 0] Center 44 (14~75) winsize 62
7524 10:02:07.480351 [CA 1] Center 44 (13~75) winsize 63
7525 10:02:07.483267 [CA 2] Center 40 (11~69) winsize 59
7526 10:02:07.486765 [CA 3] Center 39 (10~69) winsize 60
7527 10:02:07.490109 [CA 4] Center 38 (8~68) winsize 61
7528 10:02:07.493829 [CA 5] Center 37 (7~67) winsize 61
7529 10:02:07.493911
7530 10:02:07.496816 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7531 10:02:07.496929
7532 10:02:07.503256 [CATrainingPosCal] consider 1 rank data
7533 10:02:07.503359 u2DelayCellTimex100 = 275/100 ps
7534 10:02:07.510147 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7535 10:02:07.513573 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7536 10:02:07.516934 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7537 10:02:07.520368 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7538 10:02:07.523722 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7539 10:02:07.526965 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7540 10:02:07.527048
7541 10:02:07.530256 CA PerBit enable=1, Macro0, CA PI delay=37
7542 10:02:07.530339
7543 10:02:07.533395 [CBTSetCACLKResult] CA Dly = 37
7544 10:02:07.536969 CS Dly: 10 (0~41)
7545 10:02:07.540259 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7546 10:02:07.543879 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7547 10:02:07.543965 ==
7548 10:02:07.546780 Dram Type= 6, Freq= 0, CH_0, rank 1
7549 10:02:07.553431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 10:02:07.553515 ==
7551 10:02:07.556516 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7552 10:02:07.563220 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7553 10:02:07.566429 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7554 10:02:07.573408 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7555 10:02:07.581149 [CA 0] Center 43 (13~74) winsize 62
7556 10:02:07.584219 [CA 1] Center 43 (13~74) winsize 62
7557 10:02:07.587551 [CA 2] Center 39 (10~69) winsize 60
7558 10:02:07.591218 [CA 3] Center 38 (9~68) winsize 60
7559 10:02:07.594281 [CA 4] Center 37 (7~67) winsize 61
7560 10:02:07.597634 [CA 5] Center 37 (7~67) winsize 61
7561 10:02:07.597717
7562 10:02:07.600728 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7563 10:02:07.600810
7564 10:02:07.604148 [CATrainingPosCal] consider 2 rank data
7565 10:02:07.607491 u2DelayCellTimex100 = 275/100 ps
7566 10:02:07.610951 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7567 10:02:07.617965 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7568 10:02:07.620817 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7569 10:02:07.624329 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7570 10:02:07.627803 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7571 10:02:07.631212 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7572 10:02:07.631310
7573 10:02:07.634147 CA PerBit enable=1, Macro0, CA PI delay=37
7574 10:02:07.634294
7575 10:02:07.637271 [CBTSetCACLKResult] CA Dly = 37
7576 10:02:07.640769 CS Dly: 11 (0~44)
7577 10:02:07.643942 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7578 10:02:07.647240 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7579 10:02:07.647355
7580 10:02:07.650755 ----->DramcWriteLeveling(PI) begin...
7581 10:02:07.650838 ==
7582 10:02:07.654170 Dram Type= 6, Freq= 0, CH_0, rank 0
7583 10:02:07.660787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 10:02:07.660870 ==
7585 10:02:07.663889 Write leveling (Byte 0): 36 => 36
7586 10:02:07.663978 Write leveling (Byte 1): 28 => 28
7587 10:02:07.667247 DramcWriteLeveling(PI) end<-----
7588 10:02:07.667360
7589 10:02:07.670652 ==
7590 10:02:07.670734 Dram Type= 6, Freq= 0, CH_0, rank 0
7591 10:02:07.677108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 10:02:07.677191 ==
7593 10:02:07.680646 [Gating] SW mode calibration
7594 10:02:07.687070 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7595 10:02:07.690533 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7596 10:02:07.696944 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 10:02:07.700803 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 10:02:07.703664 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 10:02:07.710349 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 10:02:07.713916 1 4 16 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7601 10:02:07.716916 1 4 20 | B1->B0 | 2322 3434 | 1 0 | (0 0) (0 0)
7602 10:02:07.723595 1 4 24 | B1->B0 | 302f 3434 | 1 1 | (0 0) (1 1)
7603 10:02:07.726968 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7604 10:02:07.730304 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 10:02:07.737083 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7606 10:02:07.740314 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 10:02:07.743382 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 10:02:07.750466 1 5 16 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7609 10:02:07.753633 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7610 10:02:07.756791 1 5 24 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
7611 10:02:07.763242 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 10:02:07.766538 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 10:02:07.770144 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 10:02:07.773310 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 10:02:07.780275 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 10:02:07.783288 1 6 16 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7617 10:02:07.786933 1 6 20 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
7618 10:02:07.793650 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7619 10:02:07.796685 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 10:02:07.799988 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 10:02:07.806592 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 10:02:07.810004 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 10:02:07.813513 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 10:02:07.820091 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7625 10:02:07.823139 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7626 10:02:07.826421 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7627 10:02:07.833329 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 10:02:07.836764 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 10:02:07.839586 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 10:02:07.846511 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 10:02:07.849958 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 10:02:07.853130 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 10:02:07.859978 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 10:02:07.862931 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 10:02:07.866576 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 10:02:07.872953 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 10:02:07.876198 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 10:02:07.879441 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 10:02:07.886495 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 10:02:07.889847 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7641 10:02:07.893158 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7642 10:02:07.899622 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7643 10:02:07.899713 Total UI for P1: 0, mck2ui 16
7644 10:02:07.902708 best dqsien dly found for B0: ( 1, 9, 18)
7645 10:02:07.909600 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 10:02:07.912754 Total UI for P1: 0, mck2ui 16
7647 10:02:07.916392 best dqsien dly found for B1: ( 1, 9, 20)
7648 10:02:07.919757 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7649 10:02:07.922655 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7650 10:02:07.922738
7651 10:02:07.926207 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7652 10:02:07.929574 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7653 10:02:07.933225 [Gating] SW calibration Done
7654 10:02:07.933308 ==
7655 10:02:07.936595 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 10:02:07.939267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 10:02:07.939370 ==
7658 10:02:07.943137 RX Vref Scan: 0
7659 10:02:07.943219
7660 10:02:07.946033 RX Vref 0 -> 0, step: 1
7661 10:02:07.946115
7662 10:02:07.946180 RX Delay 0 -> 252, step: 8
7663 10:02:07.952838 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7664 10:02:07.955898 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7665 10:02:07.959180 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7666 10:02:07.962547 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7667 10:02:07.965873 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7668 10:02:07.972884 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7669 10:02:07.975760 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7670 10:02:07.979194 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7671 10:02:07.982557 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7672 10:02:07.985908 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7673 10:02:07.992717 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7674 10:02:07.996352 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7675 10:02:07.999054 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7676 10:02:08.002456 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7677 10:02:08.005700 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7678 10:02:08.012297 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7679 10:02:08.012379 ==
7680 10:02:08.015527 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 10:02:08.018811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 10:02:08.018894 ==
7683 10:02:08.018960 DQS Delay:
7684 10:02:08.022224 DQS0 = 0, DQS1 = 0
7685 10:02:08.022306 DQM Delay:
7686 10:02:08.025642 DQM0 = 131, DQM1 = 124
7687 10:02:08.025724 DQ Delay:
7688 10:02:08.029018 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
7689 10:02:08.032433 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7690 10:02:08.035434 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =115
7691 10:02:08.039744 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7692 10:02:08.041942
7693 10:02:08.042023
7694 10:02:08.042087 ==
7695 10:02:08.045345 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 10:02:08.048785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 10:02:08.048868 ==
7698 10:02:08.048932
7699 10:02:08.048992
7700 10:02:08.052190 TX Vref Scan disable
7701 10:02:08.052272 == TX Byte 0 ==
7702 10:02:08.059102 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7703 10:02:08.062300 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7704 10:02:08.062384 == TX Byte 1 ==
7705 10:02:08.068537 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7706 10:02:08.072011 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7707 10:02:08.072094 ==
7708 10:02:08.075183 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 10:02:08.078580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 10:02:08.078663 ==
7711 10:02:08.094714
7712 10:02:08.097982 TX Vref early break, caculate TX vref
7713 10:02:08.101130 TX Vref=16, minBit 1, minWin=21, winSum=366
7714 10:02:08.104356 TX Vref=18, minBit 1, minWin=22, winSum=371
7715 10:02:08.107483 TX Vref=20, minBit 0, minWin=23, winSum=388
7716 10:02:08.111184 TX Vref=22, minBit 7, minWin=23, winSum=394
7717 10:02:08.114694 TX Vref=24, minBit 4, minWin=24, winSum=406
7718 10:02:08.121143 TX Vref=26, minBit 4, minWin=25, winSum=421
7719 10:02:08.124253 TX Vref=28, minBit 4, minWin=25, winSum=428
7720 10:02:08.127781 TX Vref=30, minBit 4, minWin=25, winSum=422
7721 10:02:08.130776 TX Vref=32, minBit 4, minWin=24, winSum=415
7722 10:02:08.134114 TX Vref=34, minBit 0, minWin=24, winSum=409
7723 10:02:08.137709 TX Vref=36, minBit 0, minWin=23, winSum=398
7724 10:02:08.144260 [TxChooseVref] Worse bit 4, Min win 25, Win sum 428, Final Vref 28
7725 10:02:08.144343
7726 10:02:08.147644 Final TX Range 0 Vref 28
7727 10:02:08.147727
7728 10:02:08.147791 ==
7729 10:02:08.150980 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 10:02:08.154774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 10:02:08.154857 ==
7732 10:02:08.154923
7733 10:02:08.157986
7734 10:02:08.158099 TX Vref Scan disable
7735 10:02:08.164712 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7736 10:02:08.164795 == TX Byte 0 ==
7737 10:02:08.167124 u2DelayCellOfst[0]=14 cells (4 PI)
7738 10:02:08.170455 u2DelayCellOfst[1]=17 cells (5 PI)
7739 10:02:08.173777 u2DelayCellOfst[2]=10 cells (3 PI)
7740 10:02:08.177379 u2DelayCellOfst[3]=14 cells (4 PI)
7741 10:02:08.180872 u2DelayCellOfst[4]=7 cells (2 PI)
7742 10:02:08.183702 u2DelayCellOfst[5]=0 cells (0 PI)
7743 10:02:08.187279 u2DelayCellOfst[6]=17 cells (5 PI)
7744 10:02:08.190839 u2DelayCellOfst[7]=17 cells (5 PI)
7745 10:02:08.193916 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7746 10:02:08.197618 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7747 10:02:08.200859 == TX Byte 1 ==
7748 10:02:08.204157 u2DelayCellOfst[8]=0 cells (0 PI)
7749 10:02:08.206995 u2DelayCellOfst[9]=0 cells (0 PI)
7750 10:02:08.210795 u2DelayCellOfst[10]=10 cells (3 PI)
7751 10:02:08.210878 u2DelayCellOfst[11]=3 cells (1 PI)
7752 10:02:08.213893 u2DelayCellOfst[12]=14 cells (4 PI)
7753 10:02:08.217102 u2DelayCellOfst[13]=14 cells (4 PI)
7754 10:02:08.220586 u2DelayCellOfst[14]=17 cells (5 PI)
7755 10:02:08.223885 u2DelayCellOfst[15]=14 cells (4 PI)
7756 10:02:08.230683 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7757 10:02:08.233611 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7758 10:02:08.233739 DramC Write-DBI on
7759 10:02:08.233838 ==
7760 10:02:08.237014 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 10:02:08.243506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 10:02:08.243586 ==
7763 10:02:08.243659
7764 10:02:08.243720
7765 10:02:08.243780 TX Vref Scan disable
7766 10:02:08.248328 == TX Byte 0 ==
7767 10:02:08.251343 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7768 10:02:08.254875 == TX Byte 1 ==
7769 10:02:08.257989 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7770 10:02:08.261169 DramC Write-DBI off
7771 10:02:08.261278
7772 10:02:08.261374 [DATLAT]
7773 10:02:08.261474 Freq=1600, CH0 RK0
7774 10:02:08.261565
7775 10:02:08.264424 DATLAT Default: 0xf
7776 10:02:08.267842 0, 0xFFFF, sum = 0
7777 10:02:08.267916 1, 0xFFFF, sum = 0
7778 10:02:08.271144 2, 0xFFFF, sum = 0
7779 10:02:08.271242 3, 0xFFFF, sum = 0
7780 10:02:08.274468 4, 0xFFFF, sum = 0
7781 10:02:08.274566 5, 0xFFFF, sum = 0
7782 10:02:08.277670 6, 0xFFFF, sum = 0
7783 10:02:08.277772 7, 0xFFFF, sum = 0
7784 10:02:08.280979 8, 0xFFFF, sum = 0
7785 10:02:08.281079 9, 0xFFFF, sum = 0
7786 10:02:08.284532 10, 0xFFFF, sum = 0
7787 10:02:08.284607 11, 0xFFFF, sum = 0
7788 10:02:08.287745 12, 0xFFFF, sum = 0
7789 10:02:08.287818 13, 0xFFFF, sum = 0
7790 10:02:08.290678 14, 0x0, sum = 1
7791 10:02:08.290775 15, 0x0, sum = 2
7792 10:02:08.294090 16, 0x0, sum = 3
7793 10:02:08.294195 17, 0x0, sum = 4
7794 10:02:08.297447 best_step = 15
7795 10:02:08.297545
7796 10:02:08.297614 ==
7797 10:02:08.300835 Dram Type= 6, Freq= 0, CH_0, rank 0
7798 10:02:08.304176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7799 10:02:08.304250 ==
7800 10:02:08.307524 RX Vref Scan: 1
7801 10:02:08.307594
7802 10:02:08.307655 Set Vref Range= 24 -> 127
7803 10:02:08.307715
7804 10:02:08.310997 RX Vref 24 -> 127, step: 1
7805 10:02:08.311104
7806 10:02:08.313826 RX Delay 11 -> 252, step: 4
7807 10:02:08.313931
7808 10:02:08.317513 Set Vref, RX VrefLevel [Byte0]: 24
7809 10:02:08.320781 [Byte1]: 24
7810 10:02:08.320888
7811 10:02:08.324500 Set Vref, RX VrefLevel [Byte0]: 25
7812 10:02:08.327564 [Byte1]: 25
7813 10:02:08.330956
7814 10:02:08.331061 Set Vref, RX VrefLevel [Byte0]: 26
7815 10:02:08.334019 [Byte1]: 26
7816 10:02:08.338373
7817 10:02:08.338467 Set Vref, RX VrefLevel [Byte0]: 27
7818 10:02:08.341751 [Byte1]: 27
7819 10:02:08.345821
7820 10:02:08.345925 Set Vref, RX VrefLevel [Byte0]: 28
7821 10:02:08.349219 [Byte1]: 28
7822 10:02:08.353357
7823 10:02:08.353462 Set Vref, RX VrefLevel [Byte0]: 29
7824 10:02:08.356951 [Byte1]: 29
7825 10:02:08.361178
7826 10:02:08.361256 Set Vref, RX VrefLevel [Byte0]: 30
7827 10:02:08.364319 [Byte1]: 30
7828 10:02:08.368922
7829 10:02:08.369026 Set Vref, RX VrefLevel [Byte0]: 31
7830 10:02:08.372144 [Byte1]: 31
7831 10:02:08.376644
7832 10:02:08.376744 Set Vref, RX VrefLevel [Byte0]: 32
7833 10:02:08.379479 [Byte1]: 32
7834 10:02:08.384078
7835 10:02:08.384176 Set Vref, RX VrefLevel [Byte0]: 33
7836 10:02:08.390546 [Byte1]: 33
7837 10:02:08.390622
7838 10:02:08.393993 Set Vref, RX VrefLevel [Byte0]: 34
7839 10:02:08.397582 [Byte1]: 34
7840 10:02:08.397678
7841 10:02:08.400685 Set Vref, RX VrefLevel [Byte0]: 35
7842 10:02:08.403744 [Byte1]: 35
7843 10:02:08.403830
7844 10:02:08.407110 Set Vref, RX VrefLevel [Byte0]: 36
7845 10:02:08.410324 [Byte1]: 36
7846 10:02:08.414214
7847 10:02:08.414321 Set Vref, RX VrefLevel [Byte0]: 37
7848 10:02:08.417947 [Byte1]: 37
7849 10:02:08.422161
7850 10:02:08.422236 Set Vref, RX VrefLevel [Byte0]: 38
7851 10:02:08.425607 [Byte1]: 38
7852 10:02:08.429668
7853 10:02:08.429741 Set Vref, RX VrefLevel [Byte0]: 39
7854 10:02:08.433002 [Byte1]: 39
7855 10:02:08.437398
7856 10:02:08.437502 Set Vref, RX VrefLevel [Byte0]: 40
7857 10:02:08.440559 [Byte1]: 40
7858 10:02:08.444994
7859 10:02:08.445095 Set Vref, RX VrefLevel [Byte0]: 41
7860 10:02:08.448323 [Byte1]: 41
7861 10:02:08.452416
7862 10:02:08.452516 Set Vref, RX VrefLevel [Byte0]: 42
7863 10:02:08.455857 [Byte1]: 42
7864 10:02:08.460224
7865 10:02:08.460330 Set Vref, RX VrefLevel [Byte0]: 43
7866 10:02:08.463468 [Byte1]: 43
7867 10:02:08.467542
7868 10:02:08.467648 Set Vref, RX VrefLevel [Byte0]: 44
7869 10:02:08.471443 [Byte1]: 44
7870 10:02:08.475291
7871 10:02:08.475425 Set Vref, RX VrefLevel [Byte0]: 45
7872 10:02:08.478765 [Byte1]: 45
7873 10:02:08.483272
7874 10:02:08.483394 Set Vref, RX VrefLevel [Byte0]: 46
7875 10:02:08.486221 [Byte1]: 46
7876 10:02:08.490525
7877 10:02:08.490603 Set Vref, RX VrefLevel [Byte0]: 47
7878 10:02:08.494172 [Byte1]: 47
7879 10:02:08.498618
7880 10:02:08.498719 Set Vref, RX VrefLevel [Byte0]: 48
7881 10:02:08.501649 [Byte1]: 48
7882 10:02:08.505592
7883 10:02:08.505664 Set Vref, RX VrefLevel [Byte0]: 49
7884 10:02:08.509242 [Byte1]: 49
7885 10:02:08.513618
7886 10:02:08.513688 Set Vref, RX VrefLevel [Byte0]: 50
7887 10:02:08.516572 [Byte1]: 50
7888 10:02:08.520814
7889 10:02:08.520923 Set Vref, RX VrefLevel [Byte0]: 51
7890 10:02:08.524581 [Byte1]: 51
7891 10:02:08.528772
7892 10:02:08.528879 Set Vref, RX VrefLevel [Byte0]: 52
7893 10:02:08.532165 [Byte1]: 52
7894 10:02:08.536126
7895 10:02:08.536230 Set Vref, RX VrefLevel [Byte0]: 53
7896 10:02:08.539854 [Byte1]: 53
7897 10:02:08.543735
7898 10:02:08.543813 Set Vref, RX VrefLevel [Byte0]: 54
7899 10:02:08.547170 [Byte1]: 54
7900 10:02:08.551675
7901 10:02:08.551782 Set Vref, RX VrefLevel [Byte0]: 55
7902 10:02:08.554588 [Byte1]: 55
7903 10:02:08.559050
7904 10:02:08.559164 Set Vref, RX VrefLevel [Byte0]: 56
7905 10:02:08.562682 [Byte1]: 56
7906 10:02:08.566796
7907 10:02:08.566880 Set Vref, RX VrefLevel [Byte0]: 57
7908 10:02:08.569796 [Byte1]: 57
7909 10:02:08.574583
7910 10:02:08.574684 Set Vref, RX VrefLevel [Byte0]: 58
7911 10:02:08.577425 [Byte1]: 58
7912 10:02:08.582088
7913 10:02:08.582187 Set Vref, RX VrefLevel [Byte0]: 59
7914 10:02:08.585152 [Byte1]: 59
7915 10:02:08.589810
7916 10:02:08.589888 Set Vref, RX VrefLevel [Byte0]: 60
7917 10:02:08.592840 [Byte1]: 60
7918 10:02:08.597304
7919 10:02:08.597407 Set Vref, RX VrefLevel [Byte0]: 61
7920 10:02:08.600294 [Byte1]: 61
7921 10:02:08.604830
7922 10:02:08.604905 Set Vref, RX VrefLevel [Byte0]: 62
7923 10:02:08.608303 [Byte1]: 62
7924 10:02:08.612399
7925 10:02:08.612486 Set Vref, RX VrefLevel [Byte0]: 63
7926 10:02:08.615501 [Byte1]: 63
7927 10:02:08.620369
7928 10:02:08.620488 Set Vref, RX VrefLevel [Byte0]: 64
7929 10:02:08.623172 [Byte1]: 64
7930 10:02:08.627983
7931 10:02:08.628085 Set Vref, RX VrefLevel [Byte0]: 65
7932 10:02:08.630915 [Byte1]: 65
7933 10:02:08.635037
7934 10:02:08.635139 Set Vref, RX VrefLevel [Byte0]: 66
7935 10:02:08.638377 [Byte1]: 66
7936 10:02:08.642860
7937 10:02:08.642961 Set Vref, RX VrefLevel [Byte0]: 67
7938 10:02:08.646131 [Byte1]: 67
7939 10:02:08.650543
7940 10:02:08.650647 Set Vref, RX VrefLevel [Byte0]: 68
7941 10:02:08.654140 [Byte1]: 68
7942 10:02:08.658120
7943 10:02:08.658204 Set Vref, RX VrefLevel [Byte0]: 69
7944 10:02:08.661477 [Byte1]: 69
7945 10:02:08.665988
7946 10:02:08.666091 Set Vref, RX VrefLevel [Byte0]: 70
7947 10:02:08.669019 [Byte1]: 70
7948 10:02:08.673503
7949 10:02:08.673586 Set Vref, RX VrefLevel [Byte0]: 71
7950 10:02:08.676855 [Byte1]: 71
7951 10:02:08.680953
7952 10:02:08.681035 Set Vref, RX VrefLevel [Byte0]: 72
7953 10:02:08.684337 [Byte1]: 72
7954 10:02:08.689120
7955 10:02:08.689204 Set Vref, RX VrefLevel [Byte0]: 73
7956 10:02:08.692055 [Byte1]: 73
7957 10:02:08.695959
7958 10:02:08.696041 Set Vref, RX VrefLevel [Byte0]: 74
7959 10:02:08.699328 [Byte1]: 74
7960 10:02:08.704301
7961 10:02:08.704383 Set Vref, RX VrefLevel [Byte0]: 75
7962 10:02:08.707313 [Byte1]: 75
7963 10:02:08.711273
7964 10:02:08.711364 Final RX Vref Byte 0 = 60 to rank0
7965 10:02:08.714781 Final RX Vref Byte 1 = 62 to rank0
7966 10:02:08.718214 Final RX Vref Byte 0 = 60 to rank1
7967 10:02:08.721617 Final RX Vref Byte 1 = 62 to rank1==
7968 10:02:08.724777 Dram Type= 6, Freq= 0, CH_0, rank 0
7969 10:02:08.731628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7970 10:02:08.731711 ==
7971 10:02:08.731818 DQS Delay:
7972 10:02:08.731882 DQS0 = 0, DQS1 = 0
7973 10:02:08.734629 DQM Delay:
7974 10:02:08.734712 DQM0 = 129, DQM1 = 122
7975 10:02:08.737762 DQ Delay:
7976 10:02:08.741133 DQ0 =128, DQ1 =132, DQ2 =126, DQ3 =126
7977 10:02:08.744623 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7978 10:02:08.748149 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7979 10:02:08.750927 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =134
7980 10:02:08.751004
7981 10:02:08.751068
7982 10:02:08.751136
7983 10:02:08.754265 [DramC_TX_OE_Calibration] TA2
7984 10:02:08.757627 Original DQ_B0 (3 6) =30, OEN = 27
7985 10:02:08.761292 Original DQ_B1 (3 6) =30, OEN = 27
7986 10:02:08.764356 24, 0x0, End_B0=24 End_B1=24
7987 10:02:08.764443 25, 0x0, End_B0=25 End_B1=25
7988 10:02:08.767936 26, 0x0, End_B0=26 End_B1=26
7989 10:02:08.771369 27, 0x0, End_B0=27 End_B1=27
7990 10:02:08.774676 28, 0x0, End_B0=28 End_B1=28
7991 10:02:08.777547 29, 0x0, End_B0=29 End_B1=29
7992 10:02:08.777631 30, 0x0, End_B0=30 End_B1=30
7993 10:02:08.781036 31, 0x4141, End_B0=30 End_B1=30
7994 10:02:08.784008 Byte0 end_step=30 best_step=27
7995 10:02:08.787671 Byte1 end_step=30 best_step=27
7996 10:02:08.790780 Byte0 TX OE(2T, 0.5T) = (3, 3)
7997 10:02:08.794284 Byte1 TX OE(2T, 0.5T) = (3, 3)
7998 10:02:08.794367
7999 10:02:08.794432
8000 10:02:08.800754 [DQSOSCAuto] RK0, (LSB)MR18= 0x1307, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
8001 10:02:08.804219 CH0 RK0: MR19=303, MR18=1307
8002 10:02:08.810971 CH0_RK0: MR19=0x303, MR18=0x1307, DQSOSC=400, MR23=63, INC=23, DEC=15
8003 10:02:08.811054
8004 10:02:08.813995 ----->DramcWriteLeveling(PI) begin...
8005 10:02:08.814087 ==
8006 10:02:08.817616 Dram Type= 6, Freq= 0, CH_0, rank 1
8007 10:02:08.820533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8008 10:02:08.820617 ==
8009 10:02:08.823976 Write leveling (Byte 0): 35 => 35
8010 10:02:08.827305 Write leveling (Byte 1): 25 => 25
8011 10:02:08.830440 DramcWriteLeveling(PI) end<-----
8012 10:02:08.830522
8013 10:02:08.830586 ==
8014 10:02:08.833786 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 10:02:08.837880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 10:02:08.837964 ==
8017 10:02:08.841189 [Gating] SW mode calibration
8018 10:02:08.847273 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8019 10:02:08.853645 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8020 10:02:08.856702 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 10:02:08.863636 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 10:02:08.866912 1 4 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8023 10:02:08.870526 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8024 10:02:08.876856 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8025 10:02:08.880287 1 4 20 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
8026 10:02:08.883652 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 10:02:08.889963 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 10:02:08.893458 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 10:02:08.896566 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 10:02:08.900263 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
8031 10:02:08.907119 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 1)
8032 10:02:08.910115 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8033 10:02:08.913608 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
8034 10:02:08.920220 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8035 10:02:08.923590 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 10:02:08.927066 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 10:02:08.933636 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 10:02:08.937358 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8039 10:02:08.940289 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8040 10:02:08.947016 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8041 10:02:08.950351 1 6 20 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8042 10:02:08.953344 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 10:02:08.960185 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 10:02:08.963282 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 10:02:08.966849 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 10:02:08.973346 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8047 10:02:08.976685 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8048 10:02:08.980142 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8049 10:02:08.986953 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8050 10:02:08.990058 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8051 10:02:08.993379 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 10:02:08.999668 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 10:02:09.003290 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 10:02:09.006446 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 10:02:09.013133 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 10:02:09.016145 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 10:02:09.019556 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 10:02:09.026461 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 10:02:09.029631 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 10:02:09.033082 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 10:02:09.039986 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8062 10:02:09.042995 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8063 10:02:09.046339 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8064 10:02:09.049659 Total UI for P1: 0, mck2ui 16
8065 10:02:09.053175 best dqsien dly found for B0: ( 1, 9, 6)
8066 10:02:09.056122 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8067 10:02:09.063053 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8068 10:02:09.066409 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 10:02:09.069626 Total UI for P1: 0, mck2ui 16
8070 10:02:09.073114 best dqsien dly found for B1: ( 1, 9, 20)
8071 10:02:09.076525 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8072 10:02:09.079340 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8073 10:02:09.079463
8074 10:02:09.083027 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8075 10:02:09.086390 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8076 10:02:09.089771 [Gating] SW calibration Done
8077 10:02:09.089863 ==
8078 10:02:09.093060 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 10:02:09.099554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 10:02:09.099637 ==
8081 10:02:09.099703 RX Vref Scan: 0
8082 10:02:09.099763
8083 10:02:09.103098 RX Vref 0 -> 0, step: 1
8084 10:02:09.103180
8085 10:02:09.106118 RX Delay 0 -> 252, step: 8
8086 10:02:09.109678 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8087 10:02:09.112887 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8088 10:02:09.116085 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8089 10:02:09.119605 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8090 10:02:09.125836 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8091 10:02:09.129227 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8092 10:02:09.132614 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8093 10:02:09.136036 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8094 10:02:09.139500 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8095 10:02:09.146250 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8096 10:02:09.149311 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8097 10:02:09.152909 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8098 10:02:09.156175 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8099 10:02:09.159395 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8100 10:02:09.165977 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8101 10:02:09.169207 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8102 10:02:09.169294 ==
8103 10:02:09.172610 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 10:02:09.175739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 10:02:09.175855 ==
8106 10:02:09.179257 DQS Delay:
8107 10:02:09.179343 DQS0 = 0, DQS1 = 0
8108 10:02:09.179448 DQM Delay:
8109 10:02:09.182365 DQM0 = 131, DQM1 = 125
8110 10:02:09.182448 DQ Delay:
8111 10:02:09.185946 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =131
8112 10:02:09.189196 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8113 10:02:09.192262 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =119
8114 10:02:09.199249 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8115 10:02:09.199335
8116 10:02:09.199409
8117 10:02:09.199503 ==
8118 10:02:09.202761 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 10:02:09.205983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 10:02:09.206067 ==
8121 10:02:09.206133
8122 10:02:09.206193
8123 10:02:09.208719 TX Vref Scan disable
8124 10:02:09.212500 == TX Byte 0 ==
8125 10:02:09.215997 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8126 10:02:09.219129 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8127 10:02:09.222711 == TX Byte 1 ==
8128 10:02:09.225379 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8129 10:02:09.228814 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8130 10:02:09.228893 ==
8131 10:02:09.232347 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 10:02:09.235590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 10:02:09.235668 ==
8134 10:02:09.252070
8135 10:02:09.255619 TX Vref early break, caculate TX vref
8136 10:02:09.258868 TX Vref=16, minBit 8, minWin=22, winSum=373
8137 10:02:09.262327 TX Vref=18, minBit 9, minWin=22, winSum=383
8138 10:02:09.265359 TX Vref=20, minBit 11, minWin=23, winSum=391
8139 10:02:09.268599 TX Vref=22, minBit 0, minWin=24, winSum=398
8140 10:02:09.272113 TX Vref=24, minBit 4, minWin=24, winSum=404
8141 10:02:09.279127 TX Vref=26, minBit 0, minWin=25, winSum=411
8142 10:02:09.282051 TX Vref=28, minBit 4, minWin=25, winSum=419
8143 10:02:09.285350 TX Vref=30, minBit 4, minWin=25, winSum=416
8144 10:02:09.288527 TX Vref=32, minBit 0, minWin=25, winSum=412
8145 10:02:09.292393 TX Vref=34, minBit 1, minWin=24, winSum=405
8146 10:02:09.295336 TX Vref=36, minBit 0, minWin=24, winSum=396
8147 10:02:09.302100 [TxChooseVref] Worse bit 4, Min win 25, Win sum 419, Final Vref 28
8148 10:02:09.302202
8149 10:02:09.305288 Final TX Range 0 Vref 28
8150 10:02:09.305365
8151 10:02:09.305433 ==
8152 10:02:09.308893 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 10:02:09.311619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 10:02:09.311697 ==
8155 10:02:09.311759
8156 10:02:09.315248
8157 10:02:09.315322 TX Vref Scan disable
8158 10:02:09.321568 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8159 10:02:09.321653 == TX Byte 0 ==
8160 10:02:09.324960 u2DelayCellOfst[0]=14 cells (4 PI)
8161 10:02:09.328399 u2DelayCellOfst[1]=17 cells (5 PI)
8162 10:02:09.332023 u2DelayCellOfst[2]=10 cells (3 PI)
8163 10:02:09.335379 u2DelayCellOfst[3]=14 cells (4 PI)
8164 10:02:09.337942 u2DelayCellOfst[4]=10 cells (3 PI)
8165 10:02:09.341539 u2DelayCellOfst[5]=0 cells (0 PI)
8166 10:02:09.344957 u2DelayCellOfst[6]=17 cells (5 PI)
8167 10:02:09.348165 u2DelayCellOfst[7]=17 cells (5 PI)
8168 10:02:09.351650 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8169 10:02:09.354705 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8170 10:02:09.358216 == TX Byte 1 ==
8171 10:02:09.361506 u2DelayCellOfst[8]=0 cells (0 PI)
8172 10:02:09.364766 u2DelayCellOfst[9]=0 cells (0 PI)
8173 10:02:09.368091 u2DelayCellOfst[10]=3 cells (1 PI)
8174 10:02:09.371253 u2DelayCellOfst[11]=0 cells (0 PI)
8175 10:02:09.371370 u2DelayCellOfst[12]=10 cells (3 PI)
8176 10:02:09.374722 u2DelayCellOfst[13]=10 cells (3 PI)
8177 10:02:09.377927 u2DelayCellOfst[14]=14 cells (4 PI)
8178 10:02:09.381103 u2DelayCellOfst[15]=10 cells (3 PI)
8179 10:02:09.388340 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8180 10:02:09.391594 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8181 10:02:09.391692 DramC Write-DBI on
8182 10:02:09.394716 ==
8183 10:02:09.394801 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 10:02:09.401484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 10:02:09.401585 ==
8186 10:02:09.401651
8187 10:02:09.401713
8188 10:02:09.404562 TX Vref Scan disable
8189 10:02:09.404646 == TX Byte 0 ==
8190 10:02:09.411441 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8191 10:02:09.411563 == TX Byte 1 ==
8192 10:02:09.414956 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8193 10:02:09.418127 DramC Write-DBI off
8194 10:02:09.418210
8195 10:02:09.418275 [DATLAT]
8196 10:02:09.421307 Freq=1600, CH0 RK1
8197 10:02:09.421391
8198 10:02:09.421456 DATLAT Default: 0xf
8199 10:02:09.424950 0, 0xFFFF, sum = 0
8200 10:02:09.425036 1, 0xFFFF, sum = 0
8201 10:02:09.428277 2, 0xFFFF, sum = 0
8202 10:02:09.428362 3, 0xFFFF, sum = 0
8203 10:02:09.431046 4, 0xFFFF, sum = 0
8204 10:02:09.431200 5, 0xFFFF, sum = 0
8205 10:02:09.434404 6, 0xFFFF, sum = 0
8206 10:02:09.434516 7, 0xFFFF, sum = 0
8207 10:02:09.437884 8, 0xFFFF, sum = 0
8208 10:02:09.437968 9, 0xFFFF, sum = 0
8209 10:02:09.440943 10, 0xFFFF, sum = 0
8210 10:02:09.444368 11, 0xFFFF, sum = 0
8211 10:02:09.444451 12, 0xFFFF, sum = 0
8212 10:02:09.447659 13, 0xFFFF, sum = 0
8213 10:02:09.447743 14, 0x0, sum = 1
8214 10:02:09.451147 15, 0x0, sum = 2
8215 10:02:09.451231 16, 0x0, sum = 3
8216 10:02:09.454714 17, 0x0, sum = 4
8217 10:02:09.454799 best_step = 15
8218 10:02:09.454865
8219 10:02:09.454926 ==
8220 10:02:09.457945 Dram Type= 6, Freq= 0, CH_0, rank 1
8221 10:02:09.460989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8222 10:02:09.461099 ==
8223 10:02:09.464462 RX Vref Scan: 0
8224 10:02:09.464545
8225 10:02:09.467720 RX Vref 0 -> 0, step: 1
8226 10:02:09.467803
8227 10:02:09.467869 RX Delay 11 -> 252, step: 4
8228 10:02:09.474439 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8229 10:02:09.478029 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8230 10:02:09.481159 iDelay=195, Bit 2, Center 124 (67 ~ 182) 116
8231 10:02:09.484818 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8232 10:02:09.487985 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8233 10:02:09.494618 iDelay=195, Bit 5, Center 114 (59 ~ 170) 112
8234 10:02:09.498001 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
8235 10:02:09.501525 iDelay=195, Bit 7, Center 134 (79 ~ 190) 112
8236 10:02:09.504665 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8237 10:02:09.508207 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8238 10:02:09.514689 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8239 10:02:09.517984 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
8240 10:02:09.521333 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8241 10:02:09.524674 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8242 10:02:09.531032 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8243 10:02:09.534871 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8244 10:02:09.534976 ==
8245 10:02:09.538349 Dram Type= 6, Freq= 0, CH_0, rank 1
8246 10:02:09.541361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8247 10:02:09.541464 ==
8248 10:02:09.541557 DQS Delay:
8249 10:02:09.544237 DQS0 = 0, DQS1 = 0
8250 10:02:09.544323 DQM Delay:
8251 10:02:09.548156 DQM0 = 127, DQM1 = 122
8252 10:02:09.548229 DQ Delay:
8253 10:02:09.550997 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8254 10:02:09.554728 DQ4 =128, DQ5 =114, DQ6 =136, DQ7 =134
8255 10:02:09.557650 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =118
8256 10:02:09.564914 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8257 10:02:09.565026
8258 10:02:09.565122
8259 10:02:09.565217
8260 10:02:09.565306 [DramC_TX_OE_Calibration] TA2
8261 10:02:09.567885 Original DQ_B0 (3 6) =30, OEN = 27
8262 10:02:09.570847 Original DQ_B1 (3 6) =30, OEN = 27
8263 10:02:09.574203 24, 0x0, End_B0=24 End_B1=24
8264 10:02:09.577868 25, 0x0, End_B0=25 End_B1=25
8265 10:02:09.581119 26, 0x0, End_B0=26 End_B1=26
8266 10:02:09.581224 27, 0x0, End_B0=27 End_B1=27
8267 10:02:09.584108 28, 0x0, End_B0=28 End_B1=28
8268 10:02:09.587758 29, 0x0, End_B0=29 End_B1=29
8269 10:02:09.591241 30, 0x0, End_B0=30 End_B1=30
8270 10:02:09.594283 31, 0x4141, End_B0=30 End_B1=30
8271 10:02:09.597420 Byte0 end_step=30 best_step=27
8272 10:02:09.597527 Byte1 end_step=30 best_step=27
8273 10:02:09.600742 Byte0 TX OE(2T, 0.5T) = (3, 3)
8274 10:02:09.604308 Byte1 TX OE(2T, 0.5T) = (3, 3)
8275 10:02:09.604391
8276 10:02:09.604456
8277 10:02:09.614429 [DQSOSCAuto] RK1, (LSB)MR18= 0x190d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8278 10:02:09.614514 CH0 RK1: MR19=303, MR18=190D
8279 10:02:09.621198 CH0_RK1: MR19=0x303, MR18=0x190D, DQSOSC=397, MR23=63, INC=23, DEC=15
8280 10:02:09.624438 [RxdqsGatingPostProcess] freq 1600
8281 10:02:09.631041 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8282 10:02:09.634211 best DQS0 dly(2T, 0.5T) = (1, 1)
8283 10:02:09.637795 best DQS1 dly(2T, 0.5T) = (1, 1)
8284 10:02:09.640566 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8285 10:02:09.640684 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8286 10:02:09.644074 best DQS0 dly(2T, 0.5T) = (1, 1)
8287 10:02:09.647671 best DQS1 dly(2T, 0.5T) = (1, 1)
8288 10:02:09.650582 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8289 10:02:09.654070 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8290 10:02:09.657099 Pre-setting of DQS Precalculation
8291 10:02:09.663619 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8292 10:02:09.663702 ==
8293 10:02:09.667207 Dram Type= 6, Freq= 0, CH_1, rank 0
8294 10:02:09.670761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8295 10:02:09.670844 ==
8296 10:02:09.677084 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8297 10:02:09.680353 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8298 10:02:09.683809 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8299 10:02:09.690008 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8300 10:02:09.699218 [CA 0] Center 42 (13~71) winsize 59
8301 10:02:09.702347 [CA 1] Center 42 (13~71) winsize 59
8302 10:02:09.705338 [CA 2] Center 37 (9~66) winsize 58
8303 10:02:09.709325 [CA 3] Center 36 (7~66) winsize 60
8304 10:02:09.712233 [CA 4] Center 37 (8~66) winsize 59
8305 10:02:09.716002 [CA 5] Center 36 (7~66) winsize 60
8306 10:02:09.716084
8307 10:02:09.719158 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8308 10:02:09.719241
8309 10:02:09.722229 [CATrainingPosCal] consider 1 rank data
8310 10:02:09.725530 u2DelayCellTimex100 = 275/100 ps
8311 10:02:09.728778 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8312 10:02:09.735298 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8313 10:02:09.738736 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8314 10:02:09.741859 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8315 10:02:09.745390 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8316 10:02:09.748703 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8317 10:02:09.748779
8318 10:02:09.751858 CA PerBit enable=1, Macro0, CA PI delay=36
8319 10:02:09.751934
8320 10:02:09.755476 [CBTSetCACLKResult] CA Dly = 36
8321 10:02:09.758807 CS Dly: 8 (0~39)
8322 10:02:09.761793 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8323 10:02:09.765191 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8324 10:02:09.765269 ==
8325 10:02:09.768859 Dram Type= 6, Freq= 0, CH_1, rank 1
8326 10:02:09.772144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 10:02:09.774946 ==
8328 10:02:09.778454 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8329 10:02:09.781891 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8330 10:02:09.788937 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8331 10:02:09.791491 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8332 10:02:09.802240 [CA 0] Center 43 (14~73) winsize 60
8333 10:02:09.805545 [CA 1] Center 43 (14~72) winsize 59
8334 10:02:09.808515 [CA 2] Center 38 (9~67) winsize 59
8335 10:02:09.812015 [CA 3] Center 36 (7~66) winsize 60
8336 10:02:09.815437 [CA 4] Center 38 (9~68) winsize 60
8337 10:02:09.818601 [CA 5] Center 36 (7~66) winsize 60
8338 10:02:09.818678
8339 10:02:09.822150 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8340 10:02:09.822228
8341 10:02:09.825372 [CATrainingPosCal] consider 2 rank data
8342 10:02:09.828402 u2DelayCellTimex100 = 275/100 ps
8343 10:02:09.834957 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8344 10:02:09.838922 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8345 10:02:09.841524 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8346 10:02:09.844954 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8347 10:02:09.848206 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8348 10:02:09.851619 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8349 10:02:09.851697
8350 10:02:09.855164 CA PerBit enable=1, Macro0, CA PI delay=36
8351 10:02:09.855242
8352 10:02:09.858808 [CBTSetCACLKResult] CA Dly = 36
8353 10:02:09.861895 CS Dly: 11 (0~45)
8354 10:02:09.864717 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8355 10:02:09.868243 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8356 10:02:09.868318
8357 10:02:09.871587 ----->DramcWriteLeveling(PI) begin...
8358 10:02:09.871659 ==
8359 10:02:09.875066 Dram Type= 6, Freq= 0, CH_1, rank 0
8360 10:02:09.881784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 10:02:09.881860 ==
8362 10:02:09.884713 Write leveling (Byte 0): 24 => 24
8363 10:02:09.884789 Write leveling (Byte 1): 30 => 30
8364 10:02:09.888276 DramcWriteLeveling(PI) end<-----
8365 10:02:09.888350
8366 10:02:09.888417 ==
8367 10:02:09.891782 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 10:02:09.897986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 10:02:09.898060 ==
8370 10:02:09.901626 [Gating] SW mode calibration
8371 10:02:09.908097 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8372 10:02:09.911560 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8373 10:02:09.918209 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 10:02:09.921611 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 10:02:09.924732 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 10:02:09.931109 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 10:02:09.934875 1 4 16 | B1->B0 | 2b2b 2525 | 0 0 | (0 0) (0 0)
8378 10:02:09.937970 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 10:02:09.944546 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 10:02:09.947804 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 10:02:09.951565 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 10:02:09.957701 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 10:02:09.960960 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 10:02:09.964211 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8385 10:02:09.971156 1 5 16 | B1->B0 | 2e2e 3131 | 0 0 | (1 0) (0 0)
8386 10:02:09.974200 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 0)
8387 10:02:09.977525 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 10:02:09.984118 1 5 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8389 10:02:09.987483 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 10:02:09.991109 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 10:02:09.997713 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 10:02:10.000850 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 10:02:10.004118 1 6 16 | B1->B0 | 3e3e 3131 | 0 1 | (0 0) (0 0)
8394 10:02:10.007304 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 10:02:10.013926 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 10:02:10.017695 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 10:02:10.020698 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 10:02:10.027501 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 10:02:10.030889 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 10:02:10.034000 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8401 10:02:10.040584 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8402 10:02:10.044224 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 10:02:10.047480 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 10:02:10.053920 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 10:02:10.057686 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 10:02:10.060790 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 10:02:10.067484 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 10:02:10.071053 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 10:02:10.073779 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 10:02:10.080497 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 10:02:10.084003 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 10:02:10.087377 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 10:02:10.094069 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 10:02:10.097382 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 10:02:10.100375 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 10:02:10.107313 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8417 10:02:10.110609 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8418 10:02:10.114168 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 10:02:10.116807 Total UI for P1: 0, mck2ui 16
8420 10:02:10.120319 best dqsien dly found for B0: ( 1, 9, 14)
8421 10:02:10.123565 Total UI for P1: 0, mck2ui 16
8422 10:02:10.127092 best dqsien dly found for B1: ( 1, 9, 14)
8423 10:02:10.130360 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8424 10:02:10.134051 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8425 10:02:10.134199
8426 10:02:10.137208 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8427 10:02:10.144025 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8428 10:02:10.144122 [Gating] SW calibration Done
8429 10:02:10.147081 ==
8430 10:02:10.147164 Dram Type= 6, Freq= 0, CH_1, rank 0
8431 10:02:10.153987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8432 10:02:10.154087 ==
8433 10:02:10.154186 RX Vref Scan: 0
8434 10:02:10.154292
8435 10:02:10.156905 RX Vref 0 -> 0, step: 1
8436 10:02:10.156975
8437 10:02:10.160580 RX Delay 0 -> 252, step: 8
8438 10:02:10.163544 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8439 10:02:10.167269 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8440 10:02:10.171015 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8441 10:02:10.177150 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8442 10:02:10.180475 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8443 10:02:10.183689 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8444 10:02:10.187046 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8445 10:02:10.190778 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8446 10:02:10.193810 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8447 10:02:10.200081 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8448 10:02:10.203600 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8449 10:02:10.207143 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8450 10:02:10.210045 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8451 10:02:10.216615 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8452 10:02:10.219746 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8453 10:02:10.223571 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8454 10:02:10.223653 ==
8455 10:02:10.226756 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 10:02:10.229984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 10:02:10.230067 ==
8458 10:02:10.233457 DQS Delay:
8459 10:02:10.233570 DQS0 = 0, DQS1 = 0
8460 10:02:10.237032 DQM Delay:
8461 10:02:10.237113 DQM0 = 133, DQM1 = 127
8462 10:02:10.237178 DQ Delay:
8463 10:02:10.240218 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8464 10:02:10.246724 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8465 10:02:10.250079 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8466 10:02:10.253388 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =131
8467 10:02:10.253470
8468 10:02:10.253534
8469 10:02:10.253594 ==
8470 10:02:10.256941 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 10:02:10.260320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 10:02:10.260419 ==
8473 10:02:10.260486
8474 10:02:10.260545
8475 10:02:10.263884 TX Vref Scan disable
8476 10:02:10.266622 == TX Byte 0 ==
8477 10:02:10.270088 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8478 10:02:10.273171 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8479 10:02:10.276772 == TX Byte 1 ==
8480 10:02:10.280222 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8481 10:02:10.283670 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8482 10:02:10.283752 ==
8483 10:02:10.286939 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 10:02:10.289870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 10:02:10.293127 ==
8486 10:02:10.306113
8487 10:02:10.309310 TX Vref early break, caculate TX vref
8488 10:02:10.312747 TX Vref=16, minBit 5, minWin=21, winSum=360
8489 10:02:10.315689 TX Vref=18, minBit 8, minWin=22, winSum=371
8490 10:02:10.319409 TX Vref=20, minBit 8, minWin=22, winSum=382
8491 10:02:10.322595 TX Vref=22, minBit 8, minWin=23, winSum=396
8492 10:02:10.325733 TX Vref=24, minBit 8, minWin=23, winSum=401
8493 10:02:10.332563 TX Vref=26, minBit 8, minWin=24, winSum=410
8494 10:02:10.335727 TX Vref=28, minBit 8, minWin=24, winSum=417
8495 10:02:10.339198 TX Vref=30, minBit 1, minWin=25, winSum=415
8496 10:02:10.342399 TX Vref=32, minBit 9, minWin=24, winSum=407
8497 10:02:10.345940 TX Vref=34, minBit 15, minWin=23, winSum=397
8498 10:02:10.349175 TX Vref=36, minBit 8, minWin=23, winSum=386
8499 10:02:10.355862 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 30
8500 10:02:10.355946
8501 10:02:10.359390 Final TX Range 0 Vref 30
8502 10:02:10.359513
8503 10:02:10.359607 ==
8504 10:02:10.362550 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 10:02:10.365730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 10:02:10.365812 ==
8507 10:02:10.365877
8508 10:02:10.365937
8509 10:02:10.369318 TX Vref Scan disable
8510 10:02:10.375536 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8511 10:02:10.375635 == TX Byte 0 ==
8512 10:02:10.379027 u2DelayCellOfst[0]=17 cells (5 PI)
8513 10:02:10.382536 u2DelayCellOfst[1]=14 cells (4 PI)
8514 10:02:10.386112 u2DelayCellOfst[2]=0 cells (0 PI)
8515 10:02:10.389171 u2DelayCellOfst[3]=7 cells (2 PI)
8516 10:02:10.392351 u2DelayCellOfst[4]=7 cells (2 PI)
8517 10:02:10.395814 u2DelayCellOfst[5]=21 cells (6 PI)
8518 10:02:10.399255 u2DelayCellOfst[6]=17 cells (5 PI)
8519 10:02:10.402211 u2DelayCellOfst[7]=7 cells (2 PI)
8520 10:02:10.406055 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8521 10:02:10.409280 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8522 10:02:10.412239 == TX Byte 1 ==
8523 10:02:10.412321 u2DelayCellOfst[8]=0 cells (0 PI)
8524 10:02:10.416005 u2DelayCellOfst[9]=3 cells (1 PI)
8525 10:02:10.419084 u2DelayCellOfst[10]=7 cells (2 PI)
8526 10:02:10.422502 u2DelayCellOfst[11]=3 cells (1 PI)
8527 10:02:10.426015 u2DelayCellOfst[12]=10 cells (3 PI)
8528 10:02:10.429225 u2DelayCellOfst[13]=17 cells (5 PI)
8529 10:02:10.432379 u2DelayCellOfst[14]=17 cells (5 PI)
8530 10:02:10.435850 u2DelayCellOfst[15]=17 cells (5 PI)
8531 10:02:10.439278 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8532 10:02:10.445634 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8533 10:02:10.445718 DramC Write-DBI on
8534 10:02:10.445783 ==
8535 10:02:10.448800 Dram Type= 6, Freq= 0, CH_1, rank 0
8536 10:02:10.452342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8537 10:02:10.455658 ==
8538 10:02:10.455768
8539 10:02:10.455862
8540 10:02:10.455953 TX Vref Scan disable
8541 10:02:10.459085 == TX Byte 0 ==
8542 10:02:10.462219 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8543 10:02:10.465795 == TX Byte 1 ==
8544 10:02:10.469162 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8545 10:02:10.472025 DramC Write-DBI off
8546 10:02:10.472108
8547 10:02:10.472174 [DATLAT]
8548 10:02:10.472235 Freq=1600, CH1 RK0
8549 10:02:10.472295
8550 10:02:10.475499 DATLAT Default: 0xf
8551 10:02:10.479230 0, 0xFFFF, sum = 0
8552 10:02:10.479344 1, 0xFFFF, sum = 0
8553 10:02:10.482302 2, 0xFFFF, sum = 0
8554 10:02:10.482386 3, 0xFFFF, sum = 0
8555 10:02:10.485686 4, 0xFFFF, sum = 0
8556 10:02:10.485770 5, 0xFFFF, sum = 0
8557 10:02:10.488735 6, 0xFFFF, sum = 0
8558 10:02:10.488819 7, 0xFFFF, sum = 0
8559 10:02:10.492163 8, 0xFFFF, sum = 0
8560 10:02:10.492247 9, 0xFFFF, sum = 0
8561 10:02:10.495726 10, 0xFFFF, sum = 0
8562 10:02:10.495810 11, 0xFFFF, sum = 0
8563 10:02:10.498748 12, 0xFFFF, sum = 0
8564 10:02:10.498832 13, 0xFFFF, sum = 0
8565 10:02:10.502010 14, 0x0, sum = 1
8566 10:02:10.502093 15, 0x0, sum = 2
8567 10:02:10.505603 16, 0x0, sum = 3
8568 10:02:10.505687 17, 0x0, sum = 4
8569 10:02:10.508371 best_step = 15
8570 10:02:10.508454
8571 10:02:10.508519 ==
8572 10:02:10.511918 Dram Type= 6, Freq= 0, CH_1, rank 0
8573 10:02:10.515123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8574 10:02:10.515206 ==
8575 10:02:10.518714 RX Vref Scan: 1
8576 10:02:10.518804
8577 10:02:10.518871 Set Vref Range= 24 -> 127
8578 10:02:10.518933
8579 10:02:10.522467 RX Vref 24 -> 127, step: 1
8580 10:02:10.522550
8581 10:02:10.524994 RX Delay 11 -> 252, step: 4
8582 10:02:10.525077
8583 10:02:10.528212 Set Vref, RX VrefLevel [Byte0]: 24
8584 10:02:10.531951 [Byte1]: 24
8585 10:02:10.532034
8586 10:02:10.535176 Set Vref, RX VrefLevel [Byte0]: 25
8587 10:02:10.538236 [Byte1]: 25
8588 10:02:10.541985
8589 10:02:10.542068 Set Vref, RX VrefLevel [Byte0]: 26
8590 10:02:10.545293 [Byte1]: 26
8591 10:02:10.549181
8592 10:02:10.549264 Set Vref, RX VrefLevel [Byte0]: 27
8593 10:02:10.552791 [Byte1]: 27
8594 10:02:10.557496
8595 10:02:10.557579 Set Vref, RX VrefLevel [Byte0]: 28
8596 10:02:10.560503 [Byte1]: 28
8597 10:02:10.564658
8598 10:02:10.564748 Set Vref, RX VrefLevel [Byte0]: 29
8599 10:02:10.567819 [Byte1]: 29
8600 10:02:10.572051
8601 10:02:10.572134 Set Vref, RX VrefLevel [Byte0]: 30
8602 10:02:10.578854 [Byte1]: 30
8603 10:02:10.578951
8604 10:02:10.581967 Set Vref, RX VrefLevel [Byte0]: 31
8605 10:02:10.585363 [Byte1]: 31
8606 10:02:10.585446
8607 10:02:10.588835 Set Vref, RX VrefLevel [Byte0]: 32
8608 10:02:10.592201 [Byte1]: 32
8609 10:02:10.592283
8610 10:02:10.595734 Set Vref, RX VrefLevel [Byte0]: 33
8611 10:02:10.598560 [Byte1]: 33
8612 10:02:10.602690
8613 10:02:10.602773 Set Vref, RX VrefLevel [Byte0]: 34
8614 10:02:10.606106 [Byte1]: 34
8615 10:02:10.610449
8616 10:02:10.610531 Set Vref, RX VrefLevel [Byte0]: 35
8617 10:02:10.613389 [Byte1]: 35
8618 10:02:10.618228
8619 10:02:10.618310 Set Vref, RX VrefLevel [Byte0]: 36
8620 10:02:10.621079 [Byte1]: 36
8621 10:02:10.625700
8622 10:02:10.625786 Set Vref, RX VrefLevel [Byte0]: 37
8623 10:02:10.628572 [Byte1]: 37
8624 10:02:10.632973
8625 10:02:10.633055 Set Vref, RX VrefLevel [Byte0]: 38
8626 10:02:10.636606 [Byte1]: 38
8627 10:02:10.640811
8628 10:02:10.640897 Set Vref, RX VrefLevel [Byte0]: 39
8629 10:02:10.644073 [Byte1]: 39
8630 10:02:10.648882
8631 10:02:10.648964 Set Vref, RX VrefLevel [Byte0]: 40
8632 10:02:10.651552 [Byte1]: 40
8633 10:02:10.655740
8634 10:02:10.655822 Set Vref, RX VrefLevel [Byte0]: 41
8635 10:02:10.659719 [Byte1]: 41
8636 10:02:10.663753
8637 10:02:10.663835 Set Vref, RX VrefLevel [Byte0]: 42
8638 10:02:10.667034 [Byte1]: 42
8639 10:02:10.671465
8640 10:02:10.671547 Set Vref, RX VrefLevel [Byte0]: 43
8641 10:02:10.677833 [Byte1]: 43
8642 10:02:10.677916
8643 10:02:10.681187 Set Vref, RX VrefLevel [Byte0]: 44
8644 10:02:10.684335 [Byte1]: 44
8645 10:02:10.684418
8646 10:02:10.687537 Set Vref, RX VrefLevel [Byte0]: 45
8647 10:02:10.691112 [Byte1]: 45
8648 10:02:10.691194
8649 10:02:10.694575 Set Vref, RX VrefLevel [Byte0]: 46
8650 10:02:10.697875 [Byte1]: 46
8651 10:02:10.701548
8652 10:02:10.701658 Set Vref, RX VrefLevel [Byte0]: 47
8653 10:02:10.704877 [Byte1]: 47
8654 10:02:10.709028
8655 10:02:10.709110 Set Vref, RX VrefLevel [Byte0]: 48
8656 10:02:10.712532 [Byte1]: 48
8657 10:02:10.716686
8658 10:02:10.716773 Set Vref, RX VrefLevel [Byte0]: 49
8659 10:02:10.719983 [Byte1]: 49
8660 10:02:10.724472
8661 10:02:10.724581 Set Vref, RX VrefLevel [Byte0]: 50
8662 10:02:10.728111 [Byte1]: 50
8663 10:02:10.732155
8664 10:02:10.732242 Set Vref, RX VrefLevel [Byte0]: 51
8665 10:02:10.735408 [Byte1]: 51
8666 10:02:10.739485
8667 10:02:10.739568 Set Vref, RX VrefLevel [Byte0]: 52
8668 10:02:10.742793 [Byte1]: 52
8669 10:02:10.747591
8670 10:02:10.747674 Set Vref, RX VrefLevel [Byte0]: 53
8671 10:02:10.750706 [Byte1]: 53
8672 10:02:10.754669
8673 10:02:10.754775 Set Vref, RX VrefLevel [Byte0]: 54
8674 10:02:10.757967 [Byte1]: 54
8675 10:02:10.762437
8676 10:02:10.762545 Set Vref, RX VrefLevel [Byte0]: 55
8677 10:02:10.765783 [Byte1]: 55
8678 10:02:10.770031
8679 10:02:10.770137 Set Vref, RX VrefLevel [Byte0]: 56
8680 10:02:10.773595 [Byte1]: 56
8681 10:02:10.778297
8682 10:02:10.778404 Set Vref, RX VrefLevel [Byte0]: 57
8683 10:02:10.781016 [Byte1]: 57
8684 10:02:10.785301
8685 10:02:10.785407 Set Vref, RX VrefLevel [Byte0]: 58
8686 10:02:10.788540 [Byte1]: 58
8687 10:02:10.793151
8688 10:02:10.793233 Set Vref, RX VrefLevel [Byte0]: 59
8689 10:02:10.796235 [Byte1]: 59
8690 10:02:10.800383
8691 10:02:10.800488 Set Vref, RX VrefLevel [Byte0]: 60
8692 10:02:10.803859 [Byte1]: 60
8693 10:02:10.807961
8694 10:02:10.808070 Set Vref, RX VrefLevel [Byte0]: 61
8695 10:02:10.811367 [Byte1]: 61
8696 10:02:10.816216
8697 10:02:10.816320 Set Vref, RX VrefLevel [Byte0]: 62
8698 10:02:10.818826 [Byte1]: 62
8699 10:02:10.823446
8700 10:02:10.823551 Set Vref, RX VrefLevel [Byte0]: 63
8701 10:02:10.827001 [Byte1]: 63
8702 10:02:10.831016
8703 10:02:10.831119 Set Vref, RX VrefLevel [Byte0]: 64
8704 10:02:10.834492 [Byte1]: 64
8705 10:02:10.838560
8706 10:02:10.838660 Set Vref, RX VrefLevel [Byte0]: 65
8707 10:02:10.841701 [Byte1]: 65
8708 10:02:10.846468
8709 10:02:10.846570 Set Vref, RX VrefLevel [Byte0]: 66
8710 10:02:10.849449 [Byte1]: 66
8711 10:02:10.853908
8712 10:02:10.854007 Set Vref, RX VrefLevel [Byte0]: 67
8713 10:02:10.857261 [Byte1]: 67
8714 10:02:10.861604
8715 10:02:10.861684 Set Vref, RX VrefLevel [Byte0]: 68
8716 10:02:10.864636 [Byte1]: 68
8717 10:02:10.869703
8718 10:02:10.869781 Set Vref, RX VrefLevel [Byte0]: 69
8719 10:02:10.872613 [Byte1]: 69
8720 10:02:10.876858
8721 10:02:10.876931 Set Vref, RX VrefLevel [Byte0]: 70
8722 10:02:10.879990 [Byte1]: 70
8723 10:02:10.884485
8724 10:02:10.884567 Set Vref, RX VrefLevel [Byte0]: 71
8725 10:02:10.887653 [Byte1]: 71
8726 10:02:10.892162
8727 10:02:10.892243 Set Vref, RX VrefLevel [Byte0]: 72
8728 10:02:10.895105 [Byte1]: 72
8729 10:02:10.899342
8730 10:02:10.899460 Set Vref, RX VrefLevel [Byte0]: 73
8731 10:02:10.902692 [Byte1]: 73
8732 10:02:10.907474
8733 10:02:10.907572 Set Vref, RX VrefLevel [Byte0]: 74
8734 10:02:10.910433 [Byte1]: 74
8735 10:02:10.915010
8736 10:02:10.915092 Set Vref, RX VrefLevel [Byte0]: 75
8737 10:02:10.917912 [Byte1]: 75
8738 10:02:10.922506
8739 10:02:10.922587 Final RX Vref Byte 0 = 57 to rank0
8740 10:02:10.925820 Final RX Vref Byte 1 = 56 to rank0
8741 10:02:10.929699 Final RX Vref Byte 0 = 57 to rank1
8742 10:02:10.932321 Final RX Vref Byte 1 = 56 to rank1==
8743 10:02:10.935581 Dram Type= 6, Freq= 0, CH_1, rank 0
8744 10:02:10.942024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 10:02:10.942108 ==
8746 10:02:10.942174 DQS Delay:
8747 10:02:10.945664 DQS0 = 0, DQS1 = 0
8748 10:02:10.945756 DQM Delay:
8749 10:02:10.945825 DQM0 = 131, DQM1 = 124
8750 10:02:10.948633 DQ Delay:
8751 10:02:10.952266 DQ0 =134, DQ1 =124, DQ2 =120, DQ3 =130
8752 10:02:10.955794 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8753 10:02:10.958614 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =118
8754 10:02:10.962161 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8755 10:02:10.962246
8756 10:02:10.962311
8757 10:02:10.962371
8758 10:02:10.965294 [DramC_TX_OE_Calibration] TA2
8759 10:02:10.968777 Original DQ_B0 (3 6) =30, OEN = 27
8760 10:02:10.972346 Original DQ_B1 (3 6) =30, OEN = 27
8761 10:02:10.975713 24, 0x0, End_B0=24 End_B1=24
8762 10:02:10.975790 25, 0x0, End_B0=25 End_B1=25
8763 10:02:10.978869 26, 0x0, End_B0=26 End_B1=26
8764 10:02:10.982112 27, 0x0, End_B0=27 End_B1=27
8765 10:02:10.985542 28, 0x0, End_B0=28 End_B1=28
8766 10:02:10.988967 29, 0x0, End_B0=29 End_B1=29
8767 10:02:10.989051 30, 0x0, End_B0=30 End_B1=30
8768 10:02:10.992199 31, 0x4141, End_B0=30 End_B1=30
8769 10:02:10.995681 Byte0 end_step=30 best_step=27
8770 10:02:10.998750 Byte1 end_step=30 best_step=27
8771 10:02:11.002668 Byte0 TX OE(2T, 0.5T) = (3, 3)
8772 10:02:11.005698 Byte1 TX OE(2T, 0.5T) = (3, 3)
8773 10:02:11.005780
8774 10:02:11.005846
8775 10:02:11.011895 [DQSOSCAuto] RK0, (LSB)MR18= 0x1400, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
8776 10:02:11.015179 CH1 RK0: MR19=303, MR18=1400
8777 10:02:11.021848 CH1_RK0: MR19=0x303, MR18=0x1400, DQSOSC=399, MR23=63, INC=23, DEC=15
8778 10:02:11.021931
8779 10:02:11.025233 ----->DramcWriteLeveling(PI) begin...
8780 10:02:11.025335 ==
8781 10:02:11.028857 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 10:02:11.031696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 10:02:11.031781 ==
8784 10:02:11.035138 Write leveling (Byte 0): 23 => 23
8785 10:02:11.038859 Write leveling (Byte 1): 26 => 26
8786 10:02:11.041879 DramcWriteLeveling(PI) end<-----
8787 10:02:11.041978
8788 10:02:11.042057 ==
8789 10:02:11.045291 Dram Type= 6, Freq= 0, CH_1, rank 1
8790 10:02:11.048649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8791 10:02:11.048728 ==
8792 10:02:11.052103 [Gating] SW mode calibration
8793 10:02:11.058430 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8794 10:02:11.065672 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8795 10:02:11.068686 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 10:02:11.071799 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 10:02:11.078895 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
8798 10:02:11.081922 1 4 12 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 0)
8799 10:02:11.085092 1 4 16 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8800 10:02:11.091455 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 10:02:11.094801 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 10:02:11.098166 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 10:02:11.105048 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 10:02:11.108658 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8805 10:02:11.111813 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8806 10:02:11.118030 1 5 12 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
8807 10:02:11.121475 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 10:02:11.124983 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 10:02:11.131905 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 10:02:11.134714 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 10:02:11.138212 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 10:02:11.144777 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 10:02:11.148250 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
8814 10:02:11.151492 1 6 12 | B1->B0 | 3636 4444 | 0 0 | (0 0) (1 1)
8815 10:02:11.158371 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 10:02:11.161641 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 10:02:11.165105 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 10:02:11.171418 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 10:02:11.175130 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 10:02:11.178128 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8821 10:02:11.184711 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8822 10:02:11.188450 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8823 10:02:11.191552 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 10:02:11.194636 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 10:02:11.201335 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 10:02:11.204598 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 10:02:11.207996 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 10:02:11.214829 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 10:02:11.217776 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 10:02:11.221327 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 10:02:11.228039 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 10:02:11.231550 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 10:02:11.235013 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 10:02:11.241299 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 10:02:11.244792 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 10:02:11.248130 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 10:02:11.254391 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8838 10:02:11.257739 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8839 10:02:11.261400 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8840 10:02:11.264645 Total UI for P1: 0, mck2ui 16
8841 10:02:11.267731 best dqsien dly found for B0: ( 1, 9, 10)
8842 10:02:11.274744 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 10:02:11.274827 Total UI for P1: 0, mck2ui 16
8844 10:02:11.280928 best dqsien dly found for B1: ( 1, 9, 14)
8845 10:02:11.284519 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8846 10:02:11.287782 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8847 10:02:11.287865
8848 10:02:11.290901 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8849 10:02:11.294188 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8850 10:02:11.297717 [Gating] SW calibration Done
8851 10:02:11.297799 ==
8852 10:02:11.300855 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 10:02:11.304317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 10:02:11.304401 ==
8855 10:02:11.307558 RX Vref Scan: 0
8856 10:02:11.307642
8857 10:02:11.307735 RX Vref 0 -> 0, step: 1
8858 10:02:11.307857
8859 10:02:11.310918 RX Delay 0 -> 252, step: 8
8860 10:02:11.314136 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8861 10:02:11.320848 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8862 10:02:11.324143 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8863 10:02:11.327470 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8864 10:02:11.330803 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8865 10:02:11.334123 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8866 10:02:11.340697 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8867 10:02:11.344106 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8868 10:02:11.347981 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8869 10:02:11.350448 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8870 10:02:11.353925 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8871 10:02:11.360486 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8872 10:02:11.364184 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8873 10:02:11.367708 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8874 10:02:11.370587 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8875 10:02:11.373987 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8876 10:02:11.377497 ==
8877 10:02:11.380545 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 10:02:11.383821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 10:02:11.383905 ==
8880 10:02:11.383972 DQS Delay:
8881 10:02:11.387050 DQS0 = 0, DQS1 = 0
8882 10:02:11.387134 DQM Delay:
8883 10:02:11.390829 DQM0 = 132, DQM1 = 127
8884 10:02:11.390912 DQ Delay:
8885 10:02:11.393868 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8886 10:02:11.397130 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8887 10:02:11.400327 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8888 10:02:11.403683 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8889 10:02:11.403766
8890 10:02:11.403832
8891 10:02:11.406840 ==
8892 10:02:11.406923 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 10:02:11.413667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 10:02:11.413750 ==
8895 10:02:11.413817
8896 10:02:11.413883
8897 10:02:11.416711 TX Vref Scan disable
8898 10:02:11.416795 == TX Byte 0 ==
8899 10:02:11.420269 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8900 10:02:11.427527 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8901 10:02:11.427611 == TX Byte 1 ==
8902 10:02:11.430283 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8903 10:02:11.437180 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8904 10:02:11.437266 ==
8905 10:02:11.440008 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 10:02:11.443271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 10:02:11.443362 ==
8908 10:02:11.457526
8909 10:02:11.460887 TX Vref early break, caculate TX vref
8910 10:02:11.464549 TX Vref=16, minBit 0, minWin=23, winSum=382
8911 10:02:11.467965 TX Vref=18, minBit 11, minWin=22, winSum=393
8912 10:02:11.470755 TX Vref=20, minBit 6, minWin=24, winSum=403
8913 10:02:11.474032 TX Vref=22, minBit 15, minWin=24, winSum=413
8914 10:02:11.480308 TX Vref=24, minBit 15, minWin=24, winSum=417
8915 10:02:11.484145 TX Vref=26, minBit 0, minWin=26, winSum=425
8916 10:02:11.487003 TX Vref=28, minBit 3, minWin=26, winSum=428
8917 10:02:11.490299 TX Vref=30, minBit 0, minWin=25, winSum=427
8918 10:02:11.493472 TX Vref=32, minBit 0, minWin=25, winSum=419
8919 10:02:11.497261 TX Vref=34, minBit 0, minWin=25, winSum=412
8920 10:02:11.503832 TX Vref=36, minBit 0, minWin=23, winSum=398
8921 10:02:11.506769 [TxChooseVref] Worse bit 3, Min win 26, Win sum 428, Final Vref 28
8922 10:02:11.506853
8923 10:02:11.510323 Final TX Range 0 Vref 28
8924 10:02:11.510406
8925 10:02:11.510471 ==
8926 10:02:11.513472 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 10:02:11.519982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 10:02:11.520066 ==
8929 10:02:11.520132
8930 10:02:11.520193
8931 10:02:11.520252 TX Vref Scan disable
8932 10:02:11.527232 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8933 10:02:11.527376 == TX Byte 0 ==
8934 10:02:11.530664 u2DelayCellOfst[0]=17 cells (5 PI)
8935 10:02:11.533685 u2DelayCellOfst[1]=14 cells (4 PI)
8936 10:02:11.536980 u2DelayCellOfst[2]=0 cells (0 PI)
8937 10:02:11.539947 u2DelayCellOfst[3]=7 cells (2 PI)
8938 10:02:11.543523 u2DelayCellOfst[4]=7 cells (2 PI)
8939 10:02:11.546986 u2DelayCellOfst[5]=21 cells (6 PI)
8940 10:02:11.549848 u2DelayCellOfst[6]=17 cells (5 PI)
8941 10:02:11.553268 u2DelayCellOfst[7]=3 cells (1 PI)
8942 10:02:11.556745 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8943 10:02:11.560422 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8944 10:02:11.563647 == TX Byte 1 ==
8945 10:02:11.566478 u2DelayCellOfst[8]=0 cells (0 PI)
8946 10:02:11.569764 u2DelayCellOfst[9]=3 cells (1 PI)
8947 10:02:11.573308 u2DelayCellOfst[10]=10 cells (3 PI)
8948 10:02:11.576899 u2DelayCellOfst[11]=7 cells (2 PI)
8949 10:02:11.579892 u2DelayCellOfst[12]=14 cells (4 PI)
8950 10:02:11.579975 u2DelayCellOfst[13]=14 cells (4 PI)
8951 10:02:11.583158 u2DelayCellOfst[14]=17 cells (5 PI)
8952 10:02:11.586463 u2DelayCellOfst[15]=14 cells (4 PI)
8953 10:02:11.593516 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8954 10:02:11.596503 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8955 10:02:11.596587 DramC Write-DBI on
8956 10:02:11.599509 ==
8957 10:02:11.602927 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 10:02:11.606294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 10:02:11.606377 ==
8960 10:02:11.606443
8961 10:02:11.606505
8962 10:02:11.609881 TX Vref Scan disable
8963 10:02:11.609964 == TX Byte 0 ==
8964 10:02:11.616044 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8965 10:02:11.616141 == TX Byte 1 ==
8966 10:02:11.619614 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8967 10:02:11.623464 DramC Write-DBI off
8968 10:02:11.623547
8969 10:02:11.623612 [DATLAT]
8970 10:02:11.626162 Freq=1600, CH1 RK1
8971 10:02:11.626246
8972 10:02:11.626312 DATLAT Default: 0xf
8973 10:02:11.629756 0, 0xFFFF, sum = 0
8974 10:02:11.629871 1, 0xFFFF, sum = 0
8975 10:02:11.633139 2, 0xFFFF, sum = 0
8976 10:02:11.633215 3, 0xFFFF, sum = 0
8977 10:02:11.636268 4, 0xFFFF, sum = 0
8978 10:02:11.636352 5, 0xFFFF, sum = 0
8979 10:02:11.639473 6, 0xFFFF, sum = 0
8980 10:02:11.643021 7, 0xFFFF, sum = 0
8981 10:02:11.643105 8, 0xFFFF, sum = 0
8982 10:02:11.646080 9, 0xFFFF, sum = 0
8983 10:02:11.646183 10, 0xFFFF, sum = 0
8984 10:02:11.649498 11, 0xFFFF, sum = 0
8985 10:02:11.649582 12, 0xFFFF, sum = 0
8986 10:02:11.652436 13, 0xFFFF, sum = 0
8987 10:02:11.652520 14, 0x0, sum = 1
8988 10:02:11.655869 15, 0x0, sum = 2
8989 10:02:11.655953 16, 0x0, sum = 3
8990 10:02:11.659298 17, 0x0, sum = 4
8991 10:02:11.659408 best_step = 15
8992 10:02:11.659474
8993 10:02:11.659535 ==
8994 10:02:11.662543 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 10:02:11.665938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 10:02:11.669293 ==
8997 10:02:11.669390 RX Vref Scan: 0
8998 10:02:11.669455
8999 10:02:11.672849 RX Vref 0 -> 0, step: 1
9000 10:02:11.672931
9001 10:02:11.672997 RX Delay 11 -> 252, step: 4
9002 10:02:11.680316 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9003 10:02:11.683303 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9004 10:02:11.687086 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9005 10:02:11.689950 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9006 10:02:11.692952 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
9007 10:02:11.699809 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9008 10:02:11.703055 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9009 10:02:11.706556 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9010 10:02:11.710012 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9011 10:02:11.713265 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9012 10:02:11.720065 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9013 10:02:11.722963 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
9014 10:02:11.726695 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9015 10:02:11.729940 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9016 10:02:11.736067 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9017 10:02:11.739755 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9018 10:02:11.739841 ==
9019 10:02:11.742881 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 10:02:11.746141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 10:02:11.746230 ==
9022 10:02:11.746298 DQS Delay:
9023 10:02:11.749661 DQS0 = 0, DQS1 = 0
9024 10:02:11.749777 DQM Delay:
9025 10:02:11.752894 DQM0 = 129, DQM1 = 126
9026 10:02:11.752973 DQ Delay:
9027 10:02:11.756313 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9028 10:02:11.759693 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
9029 10:02:11.762744 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9030 10:02:11.769583 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
9031 10:02:11.769692
9032 10:02:11.769792
9033 10:02:11.769885
9034 10:02:11.772721 [DramC_TX_OE_Calibration] TA2
9035 10:02:11.772806 Original DQ_B0 (3 6) =30, OEN = 27
9036 10:02:11.776284 Original DQ_B1 (3 6) =30, OEN = 27
9037 10:02:11.779261 24, 0x0, End_B0=24 End_B1=24
9038 10:02:11.783315 25, 0x0, End_B0=25 End_B1=25
9039 10:02:11.786164 26, 0x0, End_B0=26 End_B1=26
9040 10:02:11.789270 27, 0x0, End_B0=27 End_B1=27
9041 10:02:11.789347 28, 0x0, End_B0=28 End_B1=28
9042 10:02:11.792507 29, 0x0, End_B0=29 End_B1=29
9043 10:02:11.795751 30, 0x0, End_B0=30 End_B1=30
9044 10:02:11.799265 31, 0x4141, End_B0=30 End_B1=30
9045 10:02:11.802120 Byte0 end_step=30 best_step=27
9046 10:02:11.802223 Byte1 end_step=30 best_step=27
9047 10:02:11.805691 Byte0 TX OE(2T, 0.5T) = (3, 3)
9048 10:02:11.809484 Byte1 TX OE(2T, 0.5T) = (3, 3)
9049 10:02:11.809587
9050 10:02:11.809680
9051 10:02:11.818744 [DQSOSCAuto] RK1, (LSB)MR18= 0xd13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
9052 10:02:11.818862 CH1 RK1: MR19=303, MR18=D13
9053 10:02:11.825642 CH1_RK1: MR19=0x303, MR18=0xD13, DQSOSC=400, MR23=63, INC=23, DEC=15
9054 10:02:11.828775 [RxdqsGatingPostProcess] freq 1600
9055 10:02:11.835251 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9056 10:02:11.838587 best DQS0 dly(2T, 0.5T) = (1, 1)
9057 10:02:11.841822 best DQS1 dly(2T, 0.5T) = (1, 1)
9058 10:02:11.845253 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9059 10:02:11.848420 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9060 10:02:11.852315 best DQS0 dly(2T, 0.5T) = (1, 1)
9061 10:02:11.852397 best DQS1 dly(2T, 0.5T) = (1, 1)
9062 10:02:11.854927 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9063 10:02:11.858475 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9064 10:02:11.861968 Pre-setting of DQS Precalculation
9065 10:02:11.868030 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9066 10:02:11.874935 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9067 10:02:11.881684 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9068 10:02:11.881790
9069 10:02:11.881891
9070 10:02:11.884950 [Calibration Summary] 3200 Mbps
9071 10:02:11.885054 CH 0, Rank 0
9072 10:02:11.887818 SW Impedance : PASS
9073 10:02:11.891101 DUTY Scan : NO K
9074 10:02:11.891212 ZQ Calibration : PASS
9075 10:02:11.894581 Jitter Meter : NO K
9076 10:02:11.897902 CBT Training : PASS
9077 10:02:11.898013 Write leveling : PASS
9078 10:02:11.901554 RX DQS gating : PASS
9079 10:02:11.904874 RX DQ/DQS(RDDQC) : PASS
9080 10:02:11.904950 TX DQ/DQS : PASS
9081 10:02:11.907934 RX DATLAT : PASS
9082 10:02:11.911438 RX DQ/DQS(Engine): PASS
9083 10:02:11.911547 TX OE : PASS
9084 10:02:11.914788 All Pass.
9085 10:02:11.914888
9086 10:02:11.914985 CH 0, Rank 1
9087 10:02:11.918457 SW Impedance : PASS
9088 10:02:11.918545 DUTY Scan : NO K
9089 10:02:11.921221 ZQ Calibration : PASS
9090 10:02:11.924446 Jitter Meter : NO K
9091 10:02:11.924547 CBT Training : PASS
9092 10:02:11.928233 Write leveling : PASS
9093 10:02:11.931419 RX DQS gating : PASS
9094 10:02:11.931533 RX DQ/DQS(RDDQC) : PASS
9095 10:02:11.934760 TX DQ/DQS : PASS
9096 10:02:11.934844 RX DATLAT : PASS
9097 10:02:11.937900 RX DQ/DQS(Engine): PASS
9098 10:02:11.941373 TX OE : PASS
9099 10:02:11.941455 All Pass.
9100 10:02:11.941520
9101 10:02:11.941580 CH 1, Rank 0
9102 10:02:11.945024 SW Impedance : PASS
9103 10:02:11.948056 DUTY Scan : NO K
9104 10:02:11.948138 ZQ Calibration : PASS
9105 10:02:11.951257 Jitter Meter : NO K
9106 10:02:11.954227 CBT Training : PASS
9107 10:02:11.954309 Write leveling : PASS
9108 10:02:11.958009 RX DQS gating : PASS
9109 10:02:11.961350 RX DQ/DQS(RDDQC) : PASS
9110 10:02:11.961432 TX DQ/DQS : PASS
9111 10:02:11.964280 RX DATLAT : PASS
9112 10:02:11.967638 RX DQ/DQS(Engine): PASS
9113 10:02:11.967723 TX OE : PASS
9114 10:02:11.971319 All Pass.
9115 10:02:11.971417
9116 10:02:11.971480 CH 1, Rank 1
9117 10:02:11.974421 SW Impedance : PASS
9118 10:02:11.974495 DUTY Scan : NO K
9119 10:02:11.977677 ZQ Calibration : PASS
9120 10:02:11.981293 Jitter Meter : NO K
9121 10:02:11.981364 CBT Training : PASS
9122 10:02:11.984424 Write leveling : PASS
9123 10:02:11.984493 RX DQS gating : PASS
9124 10:02:11.987508 RX DQ/DQS(RDDQC) : PASS
9125 10:02:11.991551 TX DQ/DQS : PASS
9126 10:02:11.991622 RX DATLAT : PASS
9127 10:02:11.994336 RX DQ/DQS(Engine): PASS
9128 10:02:11.997788 TX OE : PASS
9129 10:02:11.997858 All Pass.
9130 10:02:11.997922
9131 10:02:12.001101 DramC Write-DBI on
9132 10:02:12.001171 PER_BANK_REFRESH: Hybrid Mode
9133 10:02:12.004093 TX_TRACKING: ON
9134 10:02:12.014082 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9135 10:02:12.020947 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9136 10:02:12.027611 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9137 10:02:12.030561 [FAST_K] Save calibration result to emmc
9138 10:02:12.034018 sync common calibartion params.
9139 10:02:12.037340 sync cbt_mode0:1, 1:1
9140 10:02:12.037420 dram_init: ddr_geometry: 2
9141 10:02:12.040650 dram_init: ddr_geometry: 2
9142 10:02:12.044343 dram_init: ddr_geometry: 2
9143 10:02:12.047480 0:dram_rank_size:100000000
9144 10:02:12.047554 1:dram_rank_size:100000000
9145 10:02:12.054213 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9146 10:02:12.057169 DFS_SHUFFLE_HW_MODE: ON
9147 10:02:12.060784 dramc_set_vcore_voltage set vcore to 725000
9148 10:02:12.060866 Read voltage for 1600, 0
9149 10:02:12.064181 Vio18 = 0
9150 10:02:12.064259 Vcore = 725000
9151 10:02:12.064355 Vdram = 0
9152 10:02:12.067292 Vddq = 0
9153 10:02:12.067387 Vmddr = 0
9154 10:02:12.071027 switch to 3200 Mbps bootup
9155 10:02:12.071099 [DramcRunTimeConfig]
9156 10:02:12.071162 PHYPLL
9157 10:02:12.073915 DPM_CONTROL_AFTERK: ON
9158 10:02:12.077648 PER_BANK_REFRESH: ON
9159 10:02:12.080765 REFRESH_OVERHEAD_REDUCTION: ON
9160 10:02:12.080835 CMD_PICG_NEW_MODE: OFF
9161 10:02:12.084199 XRTWTW_NEW_MODE: ON
9162 10:02:12.084271 XRTRTR_NEW_MODE: ON
9163 10:02:12.087668 TX_TRACKING: ON
9164 10:02:12.087751 RDSEL_TRACKING: OFF
9165 10:02:12.090569 DQS Precalculation for DVFS: ON
9166 10:02:12.093865 RX_TRACKING: OFF
9167 10:02:12.093947 HW_GATING DBG: ON
9168 10:02:12.097112 ZQCS_ENABLE_LP4: ON
9169 10:02:12.097194 RX_PICG_NEW_MODE: ON
9170 10:02:12.100584 TX_PICG_NEW_MODE: ON
9171 10:02:12.100667 ENABLE_RX_DCM_DPHY: ON
9172 10:02:12.103866 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9173 10:02:12.107488 DUMMY_READ_FOR_TRACKING: OFF
9174 10:02:12.110326 !!! SPM_CONTROL_AFTERK: OFF
9175 10:02:12.113817 !!! SPM could not control APHY
9176 10:02:12.113899 IMPEDANCE_TRACKING: ON
9177 10:02:12.117206 TEMP_SENSOR: ON
9178 10:02:12.117288 HW_SAVE_FOR_SR: OFF
9179 10:02:12.120676 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9180 10:02:12.124437 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9181 10:02:12.127471 Read ODT Tracking: ON
9182 10:02:12.130710 Refresh Rate DeBounce: ON
9183 10:02:12.130791 DFS_NO_QUEUE_FLUSH: ON
9184 10:02:12.133825 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9185 10:02:12.137370 ENABLE_DFS_RUNTIME_MRW: OFF
9186 10:02:12.140788 DDR_RESERVE_NEW_MODE: ON
9187 10:02:12.140870 MR_CBT_SWITCH_FREQ: ON
9188 10:02:12.143605 =========================
9189 10:02:12.162225 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9190 10:02:12.165327 dram_init: ddr_geometry: 2
9191 10:02:12.183576 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9192 10:02:12.187449 dram_init: dram init end (result: 0)
9193 10:02:12.193548 DRAM-K: Full calibration passed in 24591 msecs
9194 10:02:12.196819 MRC: failed to locate region type 0.
9195 10:02:12.196901 DRAM rank0 size:0x100000000,
9196 10:02:12.200373 DRAM rank1 size=0x100000000
9197 10:02:12.210295 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9198 10:02:12.217064 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9199 10:02:12.223519 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9200 10:02:12.229888 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9201 10:02:12.233093 DRAM rank0 size:0x100000000,
9202 10:02:12.236638 DRAM rank1 size=0x100000000
9203 10:02:12.236718 CBMEM:
9204 10:02:12.240022 IMD: root @ 0xfffff000 254 entries.
9205 10:02:12.243041 IMD: root @ 0xffffec00 62 entries.
9206 10:02:12.246460 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9207 10:02:12.253210 WARNING: RO_VPD is uninitialized or empty.
9208 10:02:12.256412 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9209 10:02:12.263860 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9210 10:02:12.276525 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9211 10:02:12.288169 BS: romstage times (exec / console): total (unknown) / 24091 ms
9212 10:02:12.288251
9213 10:02:12.288317
9214 10:02:12.297736 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9215 10:02:12.301552 ARM64: Exception handlers installed.
9216 10:02:12.304426 ARM64: Testing exception
9217 10:02:12.308022 ARM64: Done test exception
9218 10:02:12.308096 Enumerating buses...
9219 10:02:12.311003 Show all devs... Before device enumeration.
9220 10:02:12.314373 Root Device: enabled 1
9221 10:02:12.317883 CPU_CLUSTER: 0: enabled 1
9222 10:02:12.317956 CPU: 00: enabled 1
9223 10:02:12.321625 Compare with tree...
9224 10:02:12.321693 Root Device: enabled 1
9225 10:02:12.324676 CPU_CLUSTER: 0: enabled 1
9226 10:02:12.328116 CPU: 00: enabled 1
9227 10:02:12.328202 Root Device scanning...
9228 10:02:12.330891 scan_static_bus for Root Device
9229 10:02:12.334348 CPU_CLUSTER: 0 enabled
9230 10:02:12.337764 scan_static_bus for Root Device done
9231 10:02:12.341551 scan_bus: bus Root Device finished in 8 msecs
9232 10:02:12.341633 done
9233 10:02:12.347584 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9234 10:02:12.350845 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9235 10:02:12.357608 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9236 10:02:12.360804 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9237 10:02:12.364105 Allocating resources...
9238 10:02:12.367332 Reading resources...
9239 10:02:12.371122 Root Device read_resources bus 0 link: 0
9240 10:02:12.371194 DRAM rank0 size:0x100000000,
9241 10:02:12.373978 DRAM rank1 size=0x100000000
9242 10:02:12.377600 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9243 10:02:12.380919 CPU: 00 missing read_resources
9244 10:02:12.387925 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9245 10:02:12.391045 Root Device read_resources bus 0 link: 0 done
9246 10:02:12.391119 Done reading resources.
9247 10:02:12.397688 Show resources in subtree (Root Device)...After reading.
9248 10:02:12.400968 Root Device child on link 0 CPU_CLUSTER: 0
9249 10:02:12.404318 CPU_CLUSTER: 0 child on link 0 CPU: 00
9250 10:02:12.413909 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9251 10:02:12.413993 CPU: 00
9252 10:02:12.417321 Root Device assign_resources, bus 0 link: 0
9253 10:02:12.420945 CPU_CLUSTER: 0 missing set_resources
9254 10:02:12.427015 Root Device assign_resources, bus 0 link: 0 done
9255 10:02:12.427090 Done setting resources.
9256 10:02:12.434039 Show resources in subtree (Root Device)...After assigning values.
9257 10:02:12.436970 Root Device child on link 0 CPU_CLUSTER: 0
9258 10:02:12.440355 CPU_CLUSTER: 0 child on link 0 CPU: 00
9259 10:02:12.450263 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9260 10:02:12.450374 CPU: 00
9261 10:02:12.453676 Done allocating resources.
9262 10:02:12.459892 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9263 10:02:12.459973 Enabling resources...
9264 10:02:12.460085 done.
9265 10:02:12.466810 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9266 10:02:12.466889 Initializing devices...
9267 10:02:12.470354 Root Device init
9268 10:02:12.470431 init hardware done!
9269 10:02:12.473597 0x00000018: ctrlr->caps
9270 10:02:12.477035 52.000 MHz: ctrlr->f_max
9271 10:02:12.477115 0.400 MHz: ctrlr->f_min
9272 10:02:12.480144 0x40ff8080: ctrlr->voltages
9273 10:02:12.483695 sclk: 390625
9274 10:02:12.483782 Bus Width = 1
9275 10:02:12.483852 sclk: 390625
9276 10:02:12.486924 Bus Width = 1
9277 10:02:12.487010 Early init status = 3
9278 10:02:12.493367 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9279 10:02:12.496545 in-header: 03 fb 00 00 01 00 00 00
9280 10:02:12.500249 in-data: 01
9281 10:02:12.503593 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9282 10:02:12.508391 in-header: 03 fb 00 00 01 00 00 00
9283 10:02:12.511113 in-data: 01
9284 10:02:12.514848 [SSUSB] Setting up USB HOST controller...
9285 10:02:12.518134 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9286 10:02:12.520892 [SSUSB] phy power-on done.
9287 10:02:12.524459 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9288 10:02:12.531123 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9289 10:02:12.534067 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9290 10:02:12.540781 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9291 10:02:12.548117 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9292 10:02:12.554407 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9293 10:02:12.560636 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9294 10:02:12.567505 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9295 10:02:12.570965 SPM: binary array size = 0x9dc
9296 10:02:12.574490 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9297 10:02:12.581021 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9298 10:02:12.587336 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9299 10:02:12.594297 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9300 10:02:12.597505 configure_display: Starting display init
9301 10:02:12.631743 anx7625_power_on_init: Init interface.
9302 10:02:12.634937 anx7625_disable_pd_protocol: Disabled PD feature.
9303 10:02:12.638012 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9304 10:02:12.665813 anx7625_start_dp_work: Secure OCM version=00
9305 10:02:12.668851 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9306 10:02:12.683623 sp_tx_get_edid_block: EDID Block = 1
9307 10:02:12.786560 Extracted contents:
9308 10:02:12.789732 header: 00 ff ff ff ff ff ff 00
9309 10:02:12.793551 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9310 10:02:12.796255 version: 01 04
9311 10:02:12.799741 basic params: 95 1f 11 78 0a
9312 10:02:12.803445 chroma info: 76 90 94 55 54 90 27 21 50 54
9313 10:02:12.806308 established: 00 00 00
9314 10:02:12.813121 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9315 10:02:12.816096 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9316 10:02:12.823074 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9317 10:02:12.829449 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9318 10:02:12.836394 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9319 10:02:12.839469 extensions: 00
9320 10:02:12.839576 checksum: fb
9321 10:02:12.839679
9322 10:02:12.842638 Manufacturer: IVO Model 57d Serial Number 0
9323 10:02:12.846047 Made week 0 of 2020
9324 10:02:12.846127 EDID version: 1.4
9325 10:02:12.849454 Digital display
9326 10:02:12.852986 6 bits per primary color channel
9327 10:02:12.853068 DisplayPort interface
9328 10:02:12.856381 Maximum image size: 31 cm x 17 cm
9329 10:02:12.859568 Gamma: 220%
9330 10:02:12.859649 Check DPMS levels
9331 10:02:12.862660 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9332 10:02:12.866143 First detailed timing is preferred timing
9333 10:02:12.869283 Established timings supported:
9334 10:02:12.872751 Standard timings supported:
9335 10:02:12.876052 Detailed timings
9336 10:02:12.879284 Hex of detail: 383680a07038204018303c0035ae10000019
9337 10:02:12.882355 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9338 10:02:12.888996 0780 0798 07c8 0820 hborder 0
9339 10:02:12.892294 0438 043b 0447 0458 vborder 0
9340 10:02:12.895966 -hsync -vsync
9341 10:02:12.896046 Did detailed timing
9342 10:02:12.902830 Hex of detail: 000000000000000000000000000000000000
9343 10:02:12.902938 Manufacturer-specified data, tag 0
9344 10:02:12.909493 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9345 10:02:12.912541 ASCII string: InfoVision
9346 10:02:12.916025 Hex of detail: 000000fe00523134304e574635205248200a
9347 10:02:12.919084 ASCII string: R140NWF5 RH
9348 10:02:12.919164 Checksum
9349 10:02:12.922278 Checksum: 0xfb (valid)
9350 10:02:12.925763 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9351 10:02:12.929401 DSI data_rate: 832800000 bps
9352 10:02:12.935684 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9353 10:02:12.938951 anx7625_parse_edid: pixelclock(138800).
9354 10:02:12.942093 hactive(1920), hsync(48), hfp(24), hbp(88)
9355 10:02:12.945604 vactive(1080), vsync(12), vfp(3), vbp(17)
9356 10:02:12.949091 anx7625_dsi_config: config dsi.
9357 10:02:12.955286 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9358 10:02:12.968759 anx7625_dsi_config: success to config DSI
9359 10:02:12.971592 anx7625_dp_start: MIPI phy setup OK.
9360 10:02:12.975224 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9361 10:02:12.978567 mtk_ddp_mode_set invalid vrefresh 60
9362 10:02:12.982005 main_disp_path_setup
9363 10:02:12.982086 ovl_layer_smi_id_en
9364 10:02:12.984886 ovl_layer_smi_id_en
9365 10:02:12.984967 ccorr_config
9366 10:02:12.985031 aal_config
9367 10:02:12.988590 gamma_config
9368 10:02:12.988670 postmask_config
9369 10:02:12.991814 dither_config
9370 10:02:12.995273 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9371 10:02:13.001721 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9372 10:02:13.005059 Root Device init finished in 531 msecs
9373 10:02:13.005140 CPU_CLUSTER: 0 init
9374 10:02:13.015023 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9375 10:02:13.018499 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9376 10:02:13.021603 APU_MBOX 0x190000b0 = 0x10001
9377 10:02:13.024886 APU_MBOX 0x190001b0 = 0x10001
9378 10:02:13.028806 APU_MBOX 0x190005b0 = 0x10001
9379 10:02:13.031361 APU_MBOX 0x190006b0 = 0x10001
9380 10:02:13.034670 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9381 10:02:13.048162 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9382 10:02:13.060533 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9383 10:02:13.066592 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9384 10:02:13.077912 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9385 10:02:13.087194 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9386 10:02:13.090635 CPU_CLUSTER: 0 init finished in 81 msecs
9387 10:02:13.094097 Devices initialized
9388 10:02:13.097015 Show all devs... After init.
9389 10:02:13.097097 Root Device: enabled 1
9390 10:02:13.100733 CPU_CLUSTER: 0: enabled 1
9391 10:02:13.103662 CPU: 00: enabled 1
9392 10:02:13.107303 BS: BS_DEV_INIT run times (exec / console): 208 / 428 ms
9393 10:02:13.110666 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9394 10:02:13.114202 ELOG: NV offset 0x57f000 size 0x1000
9395 10:02:13.121240 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9396 10:02:13.127164 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9397 10:02:13.130440 ELOG: Event(17) added with size 13 at 2023-06-10 10:02:15 UTC
9398 10:02:13.136825 out: cmd=0x121: 03 db 21 01 00 00 00 00
9399 10:02:13.140642 in-header: 03 da 00 00 2c 00 00 00
9400 10:02:13.153301 in-data: 85 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9401 10:02:13.156990 ELOG: Event(A1) added with size 10 at 2023-06-10 10:02:15 UTC
9402 10:02:13.163972 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9403 10:02:13.169831 ELOG: Event(A0) added with size 9 at 2023-06-10 10:02:15 UTC
9404 10:02:13.173293 elog_add_boot_reason: Logged dev mode boot
9405 10:02:13.179895 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9406 10:02:13.179978 Finalize devices...
9407 10:02:13.183270 Devices finalized
9408 10:02:13.186437 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9409 10:02:13.189879 Writing coreboot table at 0xffe64000
9410 10:02:13.196715 0. 000000000010a000-0000000000113fff: RAMSTAGE
9411 10:02:13.199919 1. 0000000040000000-00000000400fffff: RAM
9412 10:02:13.203290 2. 0000000040100000-000000004032afff: RAMSTAGE
9413 10:02:13.206545 3. 000000004032b000-00000000545fffff: RAM
9414 10:02:13.210065 4. 0000000054600000-000000005465ffff: BL31
9415 10:02:13.216269 5. 0000000054660000-00000000ffe63fff: RAM
9416 10:02:13.219951 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9417 10:02:13.223072 7. 0000000100000000-000000023fffffff: RAM
9418 10:02:13.226342 Passing 5 GPIOs to payload:
9419 10:02:13.229693 NAME | PORT | POLARITY | VALUE
9420 10:02:13.237088 EC in RW | 0x000000aa | low | undefined
9421 10:02:13.239692 EC interrupt | 0x00000005 | low | undefined
9422 10:02:13.246107 TPM interrupt | 0x000000ab | high | undefined
9423 10:02:13.249516 SD card detect | 0x00000011 | high | undefined
9424 10:02:13.252679 speaker enable | 0x00000093 | high | undefined
9425 10:02:13.259119 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9426 10:02:13.262754 in-header: 03 f9 00 00 02 00 00 00
9427 10:02:13.262861 in-data: 02 00
9428 10:02:13.265945 ADC[4]: Raw value=900590 ID=7
9429 10:02:13.269522 ADC[3]: Raw value=213336 ID=1
9430 10:02:13.269624 RAM Code: 0x71
9431 10:02:13.272386 ADC[6]: Raw value=74557 ID=0
9432 10:02:13.275846 ADC[5]: Raw value=212229 ID=1
9433 10:02:13.275926 SKU Code: 0x1
9434 10:02:13.282426 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9435 10:02:13.285885 coreboot table: 964 bytes.
9436 10:02:13.285959 IMD ROOT 0. 0xfffff000 0x00001000
9437 10:02:13.289422 IMD SMALL 1. 0xffffe000 0x00001000
9438 10:02:13.292557 RO MCACHE 2. 0xffffc000 0x00001104
9439 10:02:13.295965 CONSOLE 3. 0xfff7c000 0x00080000
9440 10:02:13.298938 FMAP 4. 0xfff7b000 0x00000452
9441 10:02:13.302226 TIME STAMP 5. 0xfff7a000 0x00000910
9442 10:02:13.305801 VBOOT WORK 6. 0xfff66000 0x00014000
9443 10:02:13.309027 RAMOOPS 7. 0xffe66000 0x00100000
9444 10:02:13.312382 COREBOOT 8. 0xffe64000 0x00002000
9445 10:02:13.315644 IMD small region:
9446 10:02:13.319052 IMD ROOT 0. 0xffffec00 0x00000400
9447 10:02:13.322789 VPD 1. 0xffffeba0 0x0000004c
9448 10:02:13.325575 MMC STATUS 2. 0xffffeb80 0x00000004
9449 10:02:13.332251 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9450 10:02:13.332327 Probing TPM: done!
9451 10:02:13.339073 Connected to device vid:did:rid of 1ae0:0028:00
9452 10:02:13.345960 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9453 10:02:13.348972 Initialized TPM device CR50 revision 0
9454 10:02:13.352673 Checking cr50 for pending updates
9455 10:02:13.357995 Reading cr50 TPM mode
9456 10:02:13.367132 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9457 10:02:13.373453 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9458 10:02:13.413494 read SPI 0x3990ec 0x4f1b0: 34858 us, 9295 KB/s, 74.360 Mbps
9459 10:02:13.416593 Checking segment from ROM address 0x40100000
9460 10:02:13.420269 Checking segment from ROM address 0x4010001c
9461 10:02:13.426616 Loading segment from ROM address 0x40100000
9462 10:02:13.426719 code (compression=0)
9463 10:02:13.436195 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9464 10:02:13.443227 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9465 10:02:13.443335 it's not compressed!
9466 10:02:13.449548 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9467 10:02:13.456015 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9468 10:02:13.473640 Loading segment from ROM address 0x4010001c
9469 10:02:13.473723 Entry Point 0x80000000
9470 10:02:13.477418 Loaded segments
9471 10:02:13.480140 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9472 10:02:13.486829 Jumping to boot code at 0x80000000(0xffe64000)
9473 10:02:13.493564 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9474 10:02:13.500110 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9475 10:02:13.508025 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9476 10:02:13.511556 Checking segment from ROM address 0x40100000
9477 10:02:13.514863 Checking segment from ROM address 0x4010001c
9478 10:02:13.521144 Loading segment from ROM address 0x40100000
9479 10:02:13.521222 code (compression=1)
9480 10:02:13.527875 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9481 10:02:13.538487 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9482 10:02:13.538571 using LZMA
9483 10:02:13.546475 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9484 10:02:13.553438 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9485 10:02:13.556830 Loading segment from ROM address 0x4010001c
9486 10:02:13.556902 Entry Point 0x54601000
9487 10:02:13.559829 Loaded segments
9488 10:02:13.563053 NOTICE: MT8192 bl31_setup
9489 10:02:13.570164 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9490 10:02:13.573488 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9491 10:02:13.576757 WARNING: region 0:
9492 10:02:13.580388 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 10:02:13.580488 WARNING: region 1:
9494 10:02:13.586505 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9495 10:02:13.590106 WARNING: region 2:
9496 10:02:13.593419 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9497 10:02:13.596775 WARNING: region 3:
9498 10:02:13.600713 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9499 10:02:13.603498 WARNING: region 4:
9500 10:02:13.610425 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9501 10:02:13.610534 WARNING: region 5:
9502 10:02:13.613078 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 10:02:13.616811 WARNING: region 6:
9504 10:02:13.619823 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9505 10:02:13.623132 WARNING: region 7:
9506 10:02:13.626882 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 10:02:13.633653 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9508 10:02:13.637084 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9509 10:02:13.640085 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9510 10:02:13.646495 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9511 10:02:13.649944 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9512 10:02:13.653293 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9513 10:02:13.660251 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9514 10:02:13.663247 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9515 10:02:13.669911 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9516 10:02:13.673075 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9517 10:02:13.676502 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9518 10:02:13.683476 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9519 10:02:13.686732 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9520 10:02:13.690010 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9521 10:02:13.696431 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9522 10:02:13.700289 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9523 10:02:13.707047 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9524 10:02:13.710011 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9525 10:02:13.713351 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9526 10:02:13.720266 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9527 10:02:13.723260 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9528 10:02:13.726552 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9529 10:02:13.733609 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9530 10:02:13.737076 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9531 10:02:13.743478 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9532 10:02:13.746619 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9533 10:02:13.750001 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9534 10:02:13.756727 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9535 10:02:13.760256 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9536 10:02:13.766765 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9537 10:02:13.770220 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9538 10:02:13.773662 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9539 10:02:13.780186 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9540 10:02:13.783582 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9541 10:02:13.787015 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9542 10:02:13.790228 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9543 10:02:13.796956 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9544 10:02:13.800083 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9545 10:02:13.803223 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9546 10:02:13.807012 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9547 10:02:13.810091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9548 10:02:13.817000 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9549 10:02:13.820423 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9550 10:02:13.824072 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9551 10:02:13.826915 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9552 10:02:13.833470 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9553 10:02:13.836669 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9554 10:02:13.840801 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9555 10:02:13.847078 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9556 10:02:13.850340 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9557 10:02:13.857042 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9558 10:02:13.860722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9559 10:02:13.863506 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9560 10:02:13.870654 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9561 10:02:13.873918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9562 10:02:13.880151 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9563 10:02:13.883932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9564 10:02:13.887164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9565 10:02:13.893676 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9566 10:02:13.897293 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9567 10:02:13.903867 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9568 10:02:13.907574 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9569 10:02:13.913749 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9570 10:02:13.917204 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9571 10:02:13.920909 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9572 10:02:13.927359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9573 10:02:13.930311 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9574 10:02:13.936964 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9575 10:02:13.940591 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9576 10:02:13.947163 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9577 10:02:13.950548 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9578 10:02:13.953815 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9579 10:02:13.960539 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9580 10:02:13.964025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9581 10:02:13.970348 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9582 10:02:13.973603 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9583 10:02:13.980321 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9584 10:02:13.983966 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9585 10:02:13.990171 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9586 10:02:13.994087 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9587 10:02:13.997785 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9588 10:02:14.003542 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9589 10:02:14.007266 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9590 10:02:14.013621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9591 10:02:14.017592 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9592 10:02:14.023433 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9593 10:02:14.027244 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9594 10:02:14.030112 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9595 10:02:14.037306 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9596 10:02:14.040121 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9597 10:02:14.047222 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9598 10:02:14.050640 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9599 10:02:14.057210 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9600 10:02:14.060465 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9601 10:02:14.066832 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9602 10:02:14.070466 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9603 10:02:14.073860 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9604 10:02:14.077028 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9605 10:02:14.083833 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9606 10:02:14.087248 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9607 10:02:14.090355 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9608 10:02:14.097005 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9609 10:02:14.100547 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9610 10:02:14.103831 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9611 10:02:14.110666 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9612 10:02:14.113524 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9613 10:02:14.120576 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9614 10:02:14.123936 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9615 10:02:14.126889 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9616 10:02:14.133483 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9617 10:02:14.136867 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9618 10:02:14.143977 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9619 10:02:14.147159 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9620 10:02:14.150590 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9621 10:02:14.156562 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9622 10:02:14.160414 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9623 10:02:14.163700 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9624 10:02:14.170114 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9625 10:02:14.173750 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9626 10:02:14.177048 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9627 10:02:14.183214 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9628 10:02:14.186962 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9629 10:02:14.189844 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9630 10:02:14.193408 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9631 10:02:14.200121 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9632 10:02:14.203921 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9633 10:02:14.206617 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9634 10:02:14.213551 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9635 10:02:14.216546 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9636 10:02:14.223535 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9637 10:02:14.226864 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9638 10:02:14.230431 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9639 10:02:14.236477 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9640 10:02:14.240077 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9641 10:02:14.246905 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9642 10:02:14.250048 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9643 10:02:14.253256 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9644 10:02:14.259827 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9645 10:02:14.263055 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9646 10:02:14.267230 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9647 10:02:14.273655 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9648 10:02:14.276618 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9649 10:02:14.283720 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9650 10:02:14.286798 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9651 10:02:14.290039 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9652 10:02:14.296537 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9653 10:02:14.299885 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9654 10:02:14.306633 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9655 10:02:14.309891 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9656 10:02:14.313015 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9657 10:02:14.319695 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9658 10:02:14.323220 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9659 10:02:14.329972 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9660 10:02:14.333237 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9661 10:02:14.336477 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9662 10:02:14.343763 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9663 10:02:14.346548 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9664 10:02:14.349955 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9665 10:02:14.356543 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9666 10:02:14.359889 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9667 10:02:14.366599 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9668 10:02:14.370106 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9669 10:02:14.373318 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9670 10:02:14.380028 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9671 10:02:14.382966 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9672 10:02:14.389894 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9673 10:02:14.393271 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9674 10:02:14.396388 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9675 10:02:14.403628 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9676 10:02:14.406502 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9677 10:02:14.413187 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9678 10:02:14.416654 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9679 10:02:14.419580 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9680 10:02:14.426552 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9681 10:02:14.429543 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9682 10:02:14.435957 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9683 10:02:14.439622 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9684 10:02:14.442794 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9685 10:02:14.449890 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9686 10:02:14.452767 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9687 10:02:14.455802 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9688 10:02:14.462566 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9689 10:02:14.466335 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9690 10:02:14.472687 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9691 10:02:14.475916 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9692 10:02:14.479509 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9693 10:02:14.486327 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9694 10:02:14.489511 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9695 10:02:14.496229 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9696 10:02:14.499096 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9697 10:02:14.506487 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9698 10:02:14.509023 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9699 10:02:14.512463 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9700 10:02:14.518817 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9701 10:02:14.522333 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9702 10:02:14.528966 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9703 10:02:14.532196 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9704 10:02:14.535680 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9705 10:02:14.542033 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9706 10:02:14.545197 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9707 10:02:14.551832 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9708 10:02:14.555523 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9709 10:02:14.562011 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9710 10:02:14.565651 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9711 10:02:14.568681 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9712 10:02:14.575483 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9713 10:02:14.578668 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9714 10:02:14.584941 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9715 10:02:14.588406 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9716 10:02:14.592025 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9717 10:02:14.598468 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9718 10:02:14.601691 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9719 10:02:14.608046 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9720 10:02:14.611381 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9721 10:02:14.618385 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9722 10:02:14.621561 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9723 10:02:14.624905 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9724 10:02:14.631577 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9725 10:02:14.634935 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9726 10:02:14.641282 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9727 10:02:14.644560 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9728 10:02:14.648357 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9729 10:02:14.654931 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9730 10:02:14.658123 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9731 10:02:14.665224 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9732 10:02:14.668229 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9733 10:02:14.674641 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9734 10:02:14.678385 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9735 10:02:14.681534 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9736 10:02:14.688137 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9737 10:02:14.691081 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9738 10:02:14.694587 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9739 10:02:14.698036 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9740 10:02:14.704490 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9741 10:02:14.707762 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9742 10:02:14.710889 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9743 10:02:14.717904 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9744 10:02:14.721437 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9745 10:02:14.724255 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9746 10:02:14.731422 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9747 10:02:14.734688 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9748 10:02:14.741251 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9749 10:02:14.744906 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9750 10:02:14.747774 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9751 10:02:14.754578 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9752 10:02:14.757750 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9753 10:02:14.760875 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9754 10:02:14.768108 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9755 10:02:14.770862 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9756 10:02:14.774447 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9757 10:02:14.780930 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9758 10:02:14.784503 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9759 10:02:14.791043 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9760 10:02:14.793944 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9761 10:02:14.797558 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9762 10:02:14.803921 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9763 10:02:14.807503 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9764 10:02:14.810690 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9765 10:02:14.817508 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9766 10:02:14.821049 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9767 10:02:14.824752 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9768 10:02:14.830873 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9769 10:02:14.834195 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9770 10:02:14.837099 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9771 10:02:14.844141 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9772 10:02:14.847145 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9773 10:02:14.854134 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9774 10:02:14.856809 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9775 10:02:14.860281 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9776 10:02:14.867362 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9777 10:02:14.870084 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9778 10:02:14.873495 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9779 10:02:14.876768 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9780 10:02:14.880573 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9781 10:02:14.886730 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9782 10:02:14.890421 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9783 10:02:14.893847 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9784 10:02:14.897067 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9785 10:02:14.903464 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9786 10:02:14.906698 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9787 10:02:14.910093 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9788 10:02:14.916810 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9789 10:02:14.920225 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9790 10:02:14.923609 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9791 10:02:14.929970 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9792 10:02:14.933320 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9793 10:02:14.940027 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9794 10:02:14.943249 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9795 10:02:14.949726 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9796 10:02:14.953139 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9797 10:02:14.956607 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9798 10:02:14.963026 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9799 10:02:14.966560 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9800 10:02:14.973125 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9801 10:02:14.976173 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9802 10:02:14.979636 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9803 10:02:14.986071 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9804 10:02:14.989403 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9805 10:02:14.996062 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9806 10:02:14.999731 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9807 10:02:15.002987 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9808 10:02:15.009745 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9809 10:02:15.013263 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9810 10:02:15.019918 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9811 10:02:15.022815 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9812 10:02:15.026159 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9813 10:02:15.033138 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9814 10:02:15.036582 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9815 10:02:15.043633 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9816 10:02:15.046405 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9817 10:02:15.052726 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9818 10:02:15.056074 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9819 10:02:15.059521 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9820 10:02:15.065846 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9821 10:02:15.069297 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9822 10:02:15.076045 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9823 10:02:15.079333 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9824 10:02:15.083244 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9825 10:02:15.089191 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9826 10:02:15.092478 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9827 10:02:15.099207 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9828 10:02:15.102554 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9829 10:02:15.106188 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9830 10:02:15.112292 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9831 10:02:15.116086 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9832 10:02:15.122607 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9833 10:02:15.126201 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9834 10:02:15.132438 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9835 10:02:15.135483 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9836 10:02:15.138846 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9837 10:02:15.145940 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9838 10:02:15.148621 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9839 10:02:15.155516 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9840 10:02:15.158921 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9841 10:02:15.162349 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9842 10:02:15.168753 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9843 10:02:15.172114 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9844 10:02:15.178786 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9845 10:02:15.182295 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9846 10:02:15.185682 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9847 10:02:15.192257 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9848 10:02:15.195494 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9849 10:02:15.202004 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9850 10:02:15.205535 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9851 10:02:15.208623 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9852 10:02:15.215484 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9853 10:02:15.218438 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9854 10:02:15.225177 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9855 10:02:15.228544 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9856 10:02:15.231801 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9857 10:02:15.238714 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9858 10:02:15.241731 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9859 10:02:15.248689 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9860 10:02:15.251648 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9861 10:02:15.255023 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9862 10:02:15.261860 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9863 10:02:15.265092 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9864 10:02:15.272111 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9865 10:02:15.275848 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9866 10:02:15.281546 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9867 10:02:15.285083 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9868 10:02:15.288577 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9869 10:02:15.295057 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9870 10:02:15.298522 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9871 10:02:15.304744 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9872 10:02:15.308496 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9873 10:02:15.314682 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9874 10:02:15.318713 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9875 10:02:15.324681 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9876 10:02:15.328244 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9877 10:02:15.331325 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9878 10:02:15.337711 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9879 10:02:15.341089 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9880 10:02:15.347883 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9881 10:02:15.351249 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9882 10:02:15.357767 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9883 10:02:15.361073 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9884 10:02:15.367938 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9885 10:02:15.371278 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9886 10:02:15.374415 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9887 10:02:15.381273 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9888 10:02:15.384182 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9889 10:02:15.391116 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9890 10:02:15.394132 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9891 10:02:15.400977 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9892 10:02:15.404205 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9893 10:02:15.410825 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9894 10:02:15.414136 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9895 10:02:15.417687 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9896 10:02:15.424556 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9897 10:02:15.427645 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9898 10:02:15.434351 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9899 10:02:15.437413 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9900 10:02:15.444244 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9901 10:02:15.447693 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9902 10:02:15.450490 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9903 10:02:15.457562 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9904 10:02:15.460368 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9905 10:02:15.467542 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9906 10:02:15.470341 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9907 10:02:15.477339 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9908 10:02:15.480469 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9909 10:02:15.484152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9910 10:02:15.490577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9911 10:02:15.494069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9912 10:02:15.500433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9913 10:02:15.503918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9914 10:02:15.510892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9915 10:02:15.513708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9916 10:02:15.520120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9917 10:02:15.523557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9918 10:02:15.530424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9919 10:02:15.533470 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9920 10:02:15.540256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9921 10:02:15.543638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9922 10:02:15.550040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9923 10:02:15.553530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9924 10:02:15.560084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9925 10:02:15.563499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9926 10:02:15.566494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9927 10:02:15.573418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9928 10:02:15.576639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9929 10:02:15.583241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9930 10:02:15.586607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9931 10:02:15.593395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9932 10:02:15.596679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9933 10:02:15.602988 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9934 10:02:15.606376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9935 10:02:15.613026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9936 10:02:15.619672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9937 10:02:15.622983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9938 10:02:15.629729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9939 10:02:15.633048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9940 10:02:15.640108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9941 10:02:15.642943 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9942 10:02:15.643026 INFO: [APUAPC] vio 0
9943 10:02:15.650195 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9944 10:02:15.653424 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9945 10:02:15.656990 INFO: [APUAPC] D0_APC_0: 0x400510
9946 10:02:15.660115 INFO: [APUAPC] D0_APC_1: 0x0
9947 10:02:15.663330 INFO: [APUAPC] D0_APC_2: 0x1540
9948 10:02:15.666941 INFO: [APUAPC] D0_APC_3: 0x0
9949 10:02:15.670212 INFO: [APUAPC] D1_APC_0: 0xffffffff
9950 10:02:15.673617 INFO: [APUAPC] D1_APC_1: 0xffffffff
9951 10:02:15.676499 INFO: [APUAPC] D1_APC_2: 0x3fffff
9952 10:02:15.679910 INFO: [APUAPC] D1_APC_3: 0x0
9953 10:02:15.683554 INFO: [APUAPC] D2_APC_0: 0xffffffff
9954 10:02:15.686730 INFO: [APUAPC] D2_APC_1: 0xffffffff
9955 10:02:15.690330 INFO: [APUAPC] D2_APC_2: 0x3fffff
9956 10:02:15.693182 INFO: [APUAPC] D2_APC_3: 0x0
9957 10:02:15.696539 INFO: [APUAPC] D3_APC_0: 0xffffffff
9958 10:02:15.699874 INFO: [APUAPC] D3_APC_1: 0xffffffff
9959 10:02:15.703280 INFO: [APUAPC] D3_APC_2: 0x3fffff
9960 10:02:15.706870 INFO: [APUAPC] D3_APC_3: 0x0
9961 10:02:15.709932 INFO: [APUAPC] D4_APC_0: 0xffffffff
9962 10:02:15.712965 INFO: [APUAPC] D4_APC_1: 0xffffffff
9963 10:02:15.716515 INFO: [APUAPC] D4_APC_2: 0x3fffff
9964 10:02:15.716591 INFO: [APUAPC] D4_APC_3: 0x0
9965 10:02:15.723214 INFO: [APUAPC] D5_APC_0: 0xffffffff
9966 10:02:15.726207 INFO: [APUAPC] D5_APC_1: 0xffffffff
9967 10:02:15.729852 INFO: [APUAPC] D5_APC_2: 0x3fffff
9968 10:02:15.729928 INFO: [APUAPC] D5_APC_3: 0x0
9969 10:02:15.732845 INFO: [APUAPC] D6_APC_0: 0xffffffff
9970 10:02:15.736020 INFO: [APUAPC] D6_APC_1: 0xffffffff
9971 10:02:15.739537 INFO: [APUAPC] D6_APC_2: 0x3fffff
9972 10:02:15.742830 INFO: [APUAPC] D6_APC_3: 0x0
9973 10:02:15.746403 INFO: [APUAPC] D7_APC_0: 0xffffffff
9974 10:02:15.749453 INFO: [APUAPC] D7_APC_1: 0xffffffff
9975 10:02:15.752999 INFO: [APUAPC] D7_APC_2: 0x3fffff
9976 10:02:15.756063 INFO: [APUAPC] D7_APC_3: 0x0
9977 10:02:15.759409 INFO: [APUAPC] D8_APC_0: 0xffffffff
9978 10:02:15.762773 INFO: [APUAPC] D8_APC_1: 0xffffffff
9979 10:02:15.766379 INFO: [APUAPC] D8_APC_2: 0x3fffff
9980 10:02:15.769173 INFO: [APUAPC] D8_APC_3: 0x0
9981 10:02:15.772601 INFO: [APUAPC] D9_APC_0: 0xffffffff
9982 10:02:15.776035 INFO: [APUAPC] D9_APC_1: 0xffffffff
9983 10:02:15.779884 INFO: [APUAPC] D9_APC_2: 0x3fffff
9984 10:02:15.782844 INFO: [APUAPC] D9_APC_3: 0x0
9985 10:02:15.785739 INFO: [APUAPC] D10_APC_0: 0xffffffff
9986 10:02:15.789534 INFO: [APUAPC] D10_APC_1: 0xffffffff
9987 10:02:15.792779 INFO: [APUAPC] D10_APC_2: 0x3fffff
9988 10:02:15.795703 INFO: [APUAPC] D10_APC_3: 0x0
9989 10:02:15.799238 INFO: [APUAPC] D11_APC_0: 0xffffffff
9990 10:02:15.802315 INFO: [APUAPC] D11_APC_1: 0xffffffff
9991 10:02:15.805756 INFO: [APUAPC] D11_APC_2: 0x3fffff
9992 10:02:15.809109 INFO: [APUAPC] D11_APC_3: 0x0
9993 10:02:15.812502 INFO: [APUAPC] D12_APC_0: 0xffffffff
9994 10:02:15.815302 INFO: [APUAPC] D12_APC_1: 0xffffffff
9995 10:02:15.819009 INFO: [APUAPC] D12_APC_2: 0x3fffff
9996 10:02:15.822238 INFO: [APUAPC] D12_APC_3: 0x0
9997 10:02:15.825669 INFO: [APUAPC] D13_APC_0: 0xffffffff
9998 10:02:15.828746 INFO: [APUAPC] D13_APC_1: 0xffffffff
9999 10:02:15.832503 INFO: [APUAPC] D13_APC_2: 0x3fffff
10000 10:02:15.835336 INFO: [APUAPC] D13_APC_3: 0x0
10001 10:02:15.839156 INFO: [APUAPC] D14_APC_0: 0xffffffff
10002 10:02:15.842164 INFO: [APUAPC] D14_APC_1: 0xffffffff
10003 10:02:15.845361 INFO: [APUAPC] D14_APC_2: 0x3fffff
10004 10:02:15.848957 INFO: [APUAPC] D14_APC_3: 0x0
10005 10:02:15.852050 INFO: [APUAPC] D15_APC_0: 0xffffffff
10006 10:02:15.855875 INFO: [APUAPC] D15_APC_1: 0xffffffff
10007 10:02:15.859066 INFO: [APUAPC] D15_APC_2: 0x3fffff
10008 10:02:15.861965 INFO: [APUAPC] D15_APC_3: 0x0
10009 10:02:15.865501 INFO: [APUAPC] APC_CON: 0x4
10010 10:02:15.868731 INFO: [NOCDAPC] D0_APC_0: 0x0
10011 10:02:15.871651 INFO: [NOCDAPC] D0_APC_1: 0x0
10012 10:02:15.875203 INFO: [NOCDAPC] D1_APC_0: 0x0
10013 10:02:15.878330 INFO: [NOCDAPC] D1_APC_1: 0xfff
10014 10:02:15.882066 INFO: [NOCDAPC] D2_APC_0: 0x0
10015 10:02:15.885314 INFO: [NOCDAPC] D2_APC_1: 0xfff
10016 10:02:15.885409 INFO: [NOCDAPC] D3_APC_0: 0x0
10017 10:02:15.888615 INFO: [NOCDAPC] D3_APC_1: 0xfff
10018 10:02:15.891777 INFO: [NOCDAPC] D4_APC_0: 0x0
10019 10:02:15.895120 INFO: [NOCDAPC] D4_APC_1: 0xfff
10020 10:02:15.898615 INFO: [NOCDAPC] D5_APC_0: 0x0
10021 10:02:15.901738 INFO: [NOCDAPC] D5_APC_1: 0xfff
10022 10:02:15.905396 INFO: [NOCDAPC] D6_APC_0: 0x0
10023 10:02:15.908200 INFO: [NOCDAPC] D6_APC_1: 0xfff
10024 10:02:15.911703 INFO: [NOCDAPC] D7_APC_0: 0x0
10025 10:02:15.915154 INFO: [NOCDAPC] D7_APC_1: 0xfff
10026 10:02:15.918033 INFO: [NOCDAPC] D8_APC_0: 0x0
10027 10:02:15.921298 INFO: [NOCDAPC] D8_APC_1: 0xfff
10028 10:02:15.921372 INFO: [NOCDAPC] D9_APC_0: 0x0
10029 10:02:15.924712 INFO: [NOCDAPC] D9_APC_1: 0xfff
10030 10:02:15.928264 INFO: [NOCDAPC] D10_APC_0: 0x0
10031 10:02:15.931910 INFO: [NOCDAPC] D10_APC_1: 0xfff
10032 10:02:15.934802 INFO: [NOCDAPC] D11_APC_0: 0x0
10033 10:02:15.938092 INFO: [NOCDAPC] D11_APC_1: 0xfff
10034 10:02:15.941628 INFO: [NOCDAPC] D12_APC_0: 0x0
10035 10:02:15.945127 INFO: [NOCDAPC] D12_APC_1: 0xfff
10036 10:02:15.948529 INFO: [NOCDAPC] D13_APC_0: 0x0
10037 10:02:15.951845 INFO: [NOCDAPC] D13_APC_1: 0xfff
10038 10:02:15.954946 INFO: [NOCDAPC] D14_APC_0: 0x0
10039 10:02:15.958019 INFO: [NOCDAPC] D14_APC_1: 0xfff
10040 10:02:15.962100 INFO: [NOCDAPC] D15_APC_0: 0x0
10041 10:02:15.965052 INFO: [NOCDAPC] D15_APC_1: 0xfff
10042 10:02:15.965139 INFO: [NOCDAPC] APC_CON: 0x4
10043 10:02:15.968396 INFO: [APUAPC] set_apusys_apc done
10044 10:02:15.971830 INFO: [DEVAPC] devapc_init done
10045 10:02:15.978159 INFO: GICv3 without legacy support detected.
10046 10:02:15.981694 INFO: ARM GICv3 driver initialized in EL3
10047 10:02:15.984566 INFO: Maximum SPI INTID supported: 639
10048 10:02:15.987938 INFO: BL31: Initializing runtime services
10049 10:02:15.994781 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10050 10:02:15.998322 INFO: SPM: enable CPC mode
10051 10:02:16.001320 INFO: mcdi ready for mcusys-off-idle and system suspend
10052 10:02:16.007639 INFO: BL31: Preparing for EL3 exit to normal world
10053 10:02:16.010868 INFO: Entry point address = 0x80000000
10054 10:02:16.010951 INFO: SPSR = 0x8
10055 10:02:16.018245
10056 10:02:16.018327
10057 10:02:16.018393
10058 10:02:16.022127 Starting depthcharge on Spherion...
10059 10:02:16.022211
10060 10:02:16.022275 Wipe memory regions:
10061 10:02:16.022336
10062 10:02:16.022964 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10063 10:02:16.023067 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10064 10:02:16.023153 Setting prompt string to ['asurada:']
10065 10:02:16.023236 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10066 10:02:16.024655 [0x00000040000000, 0x00000054600000)
10067 10:02:16.146769
10068 10:02:16.149931 [0x00000054660000, 0x00000080000000)
10069 10:02:16.407629
10070 10:02:16.407814 [0x000000821a7280, 0x000000ffe64000)
10071 10:02:17.152508
10072 10:02:17.152662 [0x00000100000000, 0x00000240000000)
10073 10:02:19.042023
10074 10:02:19.045244 Initializing XHCI USB controller at 0x11200000.
10075 10:02:20.084231
10076 10:02:20.087391 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10077 10:02:20.087482
10078 10:02:20.087548
10079 10:02:20.087609
10080 10:02:20.087921 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10082 10:02:20.188263 asurada: tftpboot 192.168.201.1 10670658/tftp-deploy-87q2arux/kernel/image.itb 10670658/tftp-deploy-87q2arux/kernel/cmdline
10083 10:02:20.188393 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10084 10:02:20.188482 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10085 10:02:20.192819 tftpboot 192.168.201.1 10670658/tftp-deploy-87q2arux/kernel/image.itp-deploy-87q2arux/kernel/cmdline
10086 10:02:20.192908
10087 10:02:20.192977 Waiting for link
10088 10:02:20.353740
10089 10:02:20.353873 R8152: Initializing
10090 10:02:20.353954
10091 10:02:20.356707 Version 6 (ocp_data = 5c30)
10092 10:02:20.356782
10093 10:02:20.359545 R8152: Done initializing
10094 10:02:20.359632
10095 10:02:20.359700 Adding net device
10096 10:02:22.325502
10097 10:02:22.325673 done.
10098 10:02:22.325783
10099 10:02:22.325877 MAC: 00:24:32:30:78:52
10100 10:02:22.325968
10101 10:02:22.328553 Sending DHCP discover... done.
10102 10:02:22.328632
10103 10:02:32.067961 Waiting for reply... R8152: Bulk read error 0xffffffbf
10104 10:02:32.068123
10105 10:02:32.071557 Receive failed.
10106 10:02:32.071680
10107 10:02:32.071746 done.
10108 10:02:32.071808
10109 10:02:32.074864 Sending DHCP request... done.
10110 10:02:32.074948
10111 10:02:32.078127 Waiting for reply... done.
10112 10:02:32.078228
10113 10:02:32.081397 My ip is 192.168.201.14
10114 10:02:32.081483
10115 10:02:32.084304 The DHCP server ip is 192.168.201.1
10116 10:02:32.084392
10117 10:02:32.088190 TFTP server IP predefined by user: 192.168.201.1
10118 10:02:32.088294
10119 10:02:32.094671 Bootfile predefined by user: 10670658/tftp-deploy-87q2arux/kernel/image.itb
10120 10:02:32.094762
10121 10:02:32.097672 Sending tftp read request... done.
10122 10:02:32.097781
10123 10:02:32.100821 Waiting for the transfer...
10124 10:02:32.100902
10125 10:02:32.623512 00000000 ################################################################
10126 10:02:32.623660
10127 10:02:33.138104 00080000 ################################################################
10128 10:02:33.138257
10129 10:02:33.651826 00100000 ################################################################
10130 10:02:33.651977
10131 10:02:34.165442 00180000 ################################################################
10132 10:02:34.165592
10133 10:02:34.679393 00200000 ################################################################
10134 10:02:34.679540
10135 10:02:35.193398 00280000 ################################################################
10136 10:02:35.193556
10137 10:02:35.706370 00300000 ################################################################
10138 10:02:35.706521
10139 10:02:36.221043 00380000 ################################################################
10140 10:02:36.221224
10141 10:02:36.735320 00400000 ################################################################
10142 10:02:36.735519
10143 10:02:37.248385 00480000 ################################################################
10144 10:02:37.248561
10145 10:02:37.768374 00500000 ################################################################
10146 10:02:37.768559
10147 10:02:38.283688 00580000 ################################################################
10148 10:02:38.283828
10149 10:02:38.849446 00600000 ################################################################
10150 10:02:38.849593
10151 10:02:39.412004 00680000 ################################################################
10152 10:02:39.412177
10153 10:02:39.973752 00700000 ################################################################
10154 10:02:39.973901
10155 10:02:40.524573 00780000 ################################################################
10156 10:02:40.524733
10157 10:02:41.089388 00800000 ################################################################
10158 10:02:41.089525
10159 10:02:41.658413 00880000 ################################################################
10160 10:02:41.658551
10161 10:02:42.208268 00900000 ################################################################
10162 10:02:42.208432
10163 10:02:42.766819 00980000 ################################################################
10164 10:02:42.766957
10165 10:02:43.317476 00a00000 ################################################################
10166 10:02:43.317620
10167 10:02:43.891226 00a80000 ################################################################
10168 10:02:43.891403
10169 10:02:44.453687 00b00000 ################################################################
10170 10:02:44.453829
10171 10:02:45.008785 00b80000 ################################################################
10172 10:02:45.008925
10173 10:02:45.560497 00c00000 ################################################################
10174 10:02:45.560634
10175 10:02:46.135250 00c80000 ################################################################
10176 10:02:46.135429
10177 10:02:46.707564 00d00000 ################################################################
10178 10:02:46.707712
10179 10:02:47.274864 00d80000 ################################################################
10180 10:02:47.275007
10181 10:02:47.852244 00e00000 ################################################################
10182 10:02:47.852392
10183 10:02:48.408035 00e80000 ################################################################
10184 10:02:48.408192
10185 10:02:48.978675 00f00000 ################################################################
10186 10:02:48.978824
10187 10:02:49.565316 00f80000 ################################################################
10188 10:02:49.565493
10189 10:02:50.132419 01000000 ################################################################
10190 10:02:50.132596
10191 10:02:50.716539 01080000 ################################################################
10192 10:02:50.716703
10193 10:02:51.283774 01100000 ################################################################
10194 10:02:51.283927
10195 10:02:51.841008 01180000 ################################################################
10196 10:02:51.841166
10197 10:02:52.420808 01200000 ################################################################
10198 10:02:52.420960
10199 10:02:52.997608 01280000 ################################################################
10200 10:02:52.997766
10201 10:02:53.575228 01300000 ################################################################
10202 10:02:53.575418
10203 10:02:54.145983 01380000 ################################################################
10204 10:02:54.146171
10205 10:02:54.716719 01400000 ################################################################
10206 10:02:54.716878
10207 10:02:55.273310 01480000 ################################################################
10208 10:02:55.273471
10209 10:02:55.831143 01500000 ################################################################
10210 10:02:55.831328
10211 10:02:56.416156 01580000 ################################################################
10212 10:02:56.416318
10213 10:02:56.975373 01600000 ################################################################
10214 10:02:56.975544
10215 10:02:57.542579 01680000 ################################################################
10216 10:02:57.542737
10217 10:02:58.110567 01700000 ################################################################
10218 10:02:58.110713
10219 10:02:58.669682 01780000 ################################################################
10220 10:02:58.669848
10221 10:02:59.232667 01800000 ################################################################
10222 10:02:59.232805
10223 10:02:59.797945 01880000 ################################################################
10224 10:02:59.798093
10225 10:03:00.366807 01900000 ################################################################
10226 10:03:00.366950
10227 10:03:00.942990 01980000 ################################################################
10228 10:03:00.943144
10229 10:03:01.522903 01a00000 ################################################################
10230 10:03:01.523059
10231 10:03:02.130986 01a80000 ################################################################
10232 10:03:02.131135
10233 10:03:02.730364 01b00000 ################################################################
10234 10:03:02.730522
10235 10:03:03.307554 01b80000 ################################################################
10236 10:03:03.307835
10237 10:03:03.924946 01c00000 ################################################################
10238 10:03:03.925502
10239 10:03:04.670080 01c80000 ################################################################
10240 10:03:04.670639
10241 10:03:05.418350 01d00000 ################################################################
10242 10:03:05.418922
10243 10:03:06.030701 01d80000 #################################################### done.
10244 10:03:06.031254
10245 10:03:06.034320 The bootfile was 31353870 bytes long.
10246 10:03:06.034856
10247 10:03:06.037653 Sending tftp read request... done.
10248 10:03:06.038197
10249 10:03:06.040693 Waiting for the transfer...
10250 10:03:06.041124
10251 10:03:06.041470 00000000 # done.
10252 10:03:06.041804
10253 10:03:06.048025 Command line loaded dynamically from TFTP file: 10670658/tftp-deploy-87q2arux/kernel/cmdline
10254 10:03:06.050840
10255 10:03:06.060696 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10256 10:03:06.061158
10257 10:03:06.061501 Loading FIT.
10258 10:03:06.061826
10259 10:03:06.064192 Image ramdisk-1 has 21217593 bytes.
10260 10:03:06.064626
10261 10:03:06.067084 Image fdt-1 has 46924 bytes.
10262 10:03:06.067589
10263 10:03:06.070899 Image kernel-1 has 10087317 bytes.
10264 10:03:06.071380
10265 10:03:06.080628 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10266 10:03:06.081240
10267 10:03:06.097540 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10268 10:03:06.098220
10269 10:03:06.100724 Choosing best match conf-1 for compat google,spherion-rev2.
10270 10:03:06.104165
10271 10:03:06.107739 Connected to device vid:did:rid of 1ae0:0028:00
10272 10:03:06.118383
10273 10:03:06.121486 tpm_get_response: command 0x17b, return code 0x0
10274 10:03:06.122029
10275 10:03:06.124216 ec_init: CrosEC protocol v3 supported (256, 248)
10276 10:03:06.128341
10277 10:03:06.131737 tpm_cleanup: add release locality here.
10278 10:03:06.132348
10279 10:03:06.132711 Shutting down all USB controllers.
10280 10:03:06.135016
10281 10:03:06.135479 Removing current net device
10282 10:03:06.135832
10283 10:03:06.141959 Exiting depthcharge with code 4 at timestamp: 79515442
10284 10:03:06.142529
10285 10:03:06.145030 LZMA decompressing kernel-1 to 0x821a6718
10286 10:03:06.145462
10287 10:03:06.148594 LZMA decompressing kernel-1 to 0x40000000
10288 10:03:07.415425
10289 10:03:07.415596 jumping to kernel
10290 10:03:07.416034 end: 2.2.4 bootloader-commands (duration 00:00:51) [common]
10291 10:03:07.416147 start: 2.2.5 auto-login-action (timeout 00:03:34) [common]
10292 10:03:07.416250 Setting prompt string to ['Linux version [0-9]']
10293 10:03:07.416329 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10294 10:03:07.416407 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10295 10:03:07.497304
10296 10:03:07.500446 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10297 10:03:07.504683 start: 2.2.5.1 login-action (timeout 00:03:34) [common]
10298 10:03:07.505246 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10299 10:03:07.505817 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10300 10:03:07.506324 Using line separator: #'\n'#
10301 10:03:07.506662 No login prompt set.
10302 10:03:07.507002 Parsing kernel messages
10303 10:03:07.507306 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10304 10:03:07.507893 [login-action] Waiting for messages, (timeout 00:03:34)
10305 10:03:07.524092 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j19381-arm64-gcc-10-defconfig-arm64-chromebook-d6qsg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023
10306 10:03:07.527834 [ 0.000000] random: crng init done
10307 10:03:07.530945 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10308 10:03:07.534422 [ 0.000000] efi: UEFI not found.
10309 10:03:07.544617 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10310 10:03:07.551063 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10311 10:03:07.560952 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10312 10:03:07.570686 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10313 10:03:07.576953 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10314 10:03:07.580019 [ 0.000000] printk: bootconsole [mtk8250] enabled
10315 10:03:07.589068 [ 0.000000] NUMA: No NUMA configuration found
10316 10:03:07.595907 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10317 10:03:07.602783 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10318 10:03:07.603316 [ 0.000000] Zone ranges:
10319 10:03:07.609048 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10320 10:03:07.612204 [ 0.000000] DMA32 empty
10321 10:03:07.618478 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10322 10:03:07.622179 [ 0.000000] Movable zone start for each node
10323 10:03:07.625349 [ 0.000000] Early memory node ranges
10324 10:03:07.632013 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10325 10:03:07.638731 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10326 10:03:07.645326 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10327 10:03:07.651939 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10328 10:03:07.658862 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10329 10:03:07.665393 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10330 10:03:07.721432 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10331 10:03:07.727874 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10332 10:03:07.734302 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10333 10:03:07.737489 [ 0.000000] psci: probing for conduit method from DT.
10334 10:03:07.744330 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10335 10:03:07.747830 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10336 10:03:07.754903 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10337 10:03:07.757807 [ 0.000000] psci: SMC Calling Convention v1.2
10338 10:03:07.764540 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10339 10:03:07.767507 [ 0.000000] Detected VIPT I-cache on CPU0
10340 10:03:07.774857 [ 0.000000] CPU features: detected: GIC system register CPU interface
10341 10:03:07.781234 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10342 10:03:07.787773 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10343 10:03:07.794197 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10344 10:03:07.801294 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10345 10:03:07.808303 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10346 10:03:07.814505 [ 0.000000] alternatives: applying boot alternatives
10347 10:03:07.817180 [ 0.000000] Fallback order for Node 0: 0
10348 10:03:07.824423 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10349 10:03:07.827151 [ 0.000000] Policy zone: Normal
10350 10:03:07.840554 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10351 10:03:07.850752 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10352 10:03:07.863139 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10353 10:03:07.873389 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10354 10:03:07.880050 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10355 10:03:07.883285 <6>[ 0.000000] software IO TLB: area num 8.
10356 10:03:07.939992 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10357 10:03:08.088688 <6>[ 0.000000] Memory: 7952220K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 400548K reserved, 32768K cma-reserved)
10358 10:03:08.095976 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10359 10:03:08.101888 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10360 10:03:08.105135 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10361 10:03:08.112206 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10362 10:03:08.118708 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10363 10:03:08.122148 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10364 10:03:08.132058 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10365 10:03:08.138177 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10366 10:03:08.144905 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10367 10:03:08.151331 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10368 10:03:08.154848 <6>[ 0.000000] GICv3: 608 SPIs implemented
10369 10:03:08.158243 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10370 10:03:08.164508 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10371 10:03:08.167901 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10372 10:03:08.174887 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10373 10:03:08.187791 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10374 10:03:08.200882 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10375 10:03:08.207781 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10376 10:03:08.216077 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10377 10:03:08.228648 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10378 10:03:08.235699 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10379 10:03:08.242104 <6>[ 0.009171] Console: colour dummy device 80x25
10380 10:03:08.251970 <6>[ 0.013899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10381 10:03:08.258994 <6>[ 0.024342] pid_max: default: 32768 minimum: 301
10382 10:03:08.261559 <6>[ 0.029216] LSM: Security Framework initializing
10383 10:03:08.267890 <6>[ 0.034186] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10384 10:03:08.278407 <6>[ 0.042050] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10385 10:03:08.288664 <6>[ 0.051481] cblist_init_generic: Setting adjustable number of callback queues.
10386 10:03:08.291155 <6>[ 0.058934] cblist_init_generic: Setting shift to 3 and lim to 1.
10387 10:03:08.297681 <6>[ 0.065273] cblist_init_generic: Setting shift to 3 and lim to 1.
10388 10:03:08.304698 <6>[ 0.071719] rcu: Hierarchical SRCU implementation.
10389 10:03:08.311714 <6>[ 0.076764] rcu: Max phase no-delay instances is 1000.
10390 10:03:08.314956 <6>[ 0.083784] EFI services will not be available.
10391 10:03:08.321620 <6>[ 0.088783] smp: Bringing up secondary CPUs ...
10392 10:03:08.328499 <6>[ 0.093836] Detected VIPT I-cache on CPU1
10393 10:03:08.335033 <6>[ 0.093909] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10394 10:03:08.342097 <6>[ 0.093938] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10395 10:03:08.344853 <6>[ 0.094271] Detected VIPT I-cache on CPU2
10396 10:03:08.355072 <6>[ 0.094318] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10397 10:03:08.361932 <6>[ 0.094333] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10398 10:03:08.364921 <6>[ 0.094588] Detected VIPT I-cache on CPU3
10399 10:03:08.371327 <6>[ 0.094640] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10400 10:03:08.378272 <6>[ 0.094653] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10401 10:03:08.384758 <6>[ 0.094956] CPU features: detected: Spectre-v4
10402 10:03:08.388136 <6>[ 0.094962] CPU features: detected: Spectre-BHB
10403 10:03:08.391179 <6>[ 0.094968] Detected PIPT I-cache on CPU4
10404 10:03:08.397763 <6>[ 0.095026] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10405 10:03:08.405298 <6>[ 0.095043] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10406 10:03:08.411228 <6>[ 0.095334] Detected PIPT I-cache on CPU5
10407 10:03:08.417649 <6>[ 0.095396] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10408 10:03:08.424766 <6>[ 0.095413] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10409 10:03:08.428182 <6>[ 0.095695] Detected PIPT I-cache on CPU6
10410 10:03:08.434908 <6>[ 0.095761] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10411 10:03:08.441142 <6>[ 0.095777] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10412 10:03:08.448056 <6>[ 0.096072] Detected PIPT I-cache on CPU7
10413 10:03:08.454813 <6>[ 0.096136] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10414 10:03:08.461346 <6>[ 0.096152] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10415 10:03:08.464312 <6>[ 0.096200] smp: Brought up 1 node, 8 CPUs
10416 10:03:08.470909 <6>[ 0.237442] SMP: Total of 8 processors activated.
10417 10:03:08.474637 <6>[ 0.242393] CPU features: detected: 32-bit EL0 Support
10418 10:03:08.484441 <6>[ 0.247757] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10419 10:03:08.490967 <6>[ 0.256556] CPU features: detected: Common not Private translations
10420 10:03:08.497758 <6>[ 0.263032] CPU features: detected: CRC32 instructions
10421 10:03:08.500850 <6>[ 0.268383] CPU features: detected: RCpc load-acquire (LDAPR)
10422 10:03:08.507712 <6>[ 0.274343] CPU features: detected: LSE atomic instructions
10423 10:03:08.513869 <6>[ 0.280124] CPU features: detected: Privileged Access Never
10424 10:03:08.520952 <6>[ 0.285904] CPU features: detected: RAS Extension Support
10425 10:03:08.527582 <6>[ 0.291547] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10426 10:03:08.531177 <6>[ 0.298813] CPU: All CPU(s) started at EL2
10427 10:03:08.537543 <6>[ 0.303156] alternatives: applying system-wide alternatives
10428 10:03:08.546640 <6>[ 0.313869] devtmpfs: initialized
10429 10:03:08.558798 <6>[ 0.322612] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10430 10:03:08.568700 <6>[ 0.332577] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10431 10:03:08.575103 <6>[ 0.340724] pinctrl core: initialized pinctrl subsystem
10432 10:03:08.578380 <6>[ 0.347385] DMI not present or invalid.
10433 10:03:08.585831 <6>[ 0.351760] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10434 10:03:08.594931 <6>[ 0.358628] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10435 10:03:08.601536 <6>[ 0.366210] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10436 10:03:08.611757 <6>[ 0.374432] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10437 10:03:08.615106 <6>[ 0.382676] audit: initializing netlink subsys (disabled)
10438 10:03:08.624670 <5>[ 0.388370] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10439 10:03:08.631537 <6>[ 0.389077] thermal_sys: Registered thermal governor 'step_wise'
10440 10:03:08.638435 <6>[ 0.396334] thermal_sys: Registered thermal governor 'power_allocator'
10441 10:03:08.641609 <6>[ 0.402591] cpuidle: using governor menu
10442 10:03:08.648536 <6>[ 0.413547] NET: Registered PF_QIPCRTR protocol family
10443 10:03:08.654809 <6>[ 0.419023] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10444 10:03:08.658414 <6>[ 0.426126] ASID allocator initialised with 32768 entries
10445 10:03:08.665132 <6>[ 0.432687] Serial: AMBA PL011 UART driver
10446 10:03:08.673608 <4>[ 0.441333] Trying to register duplicate clock ID: 134
10447 10:03:08.726952 <6>[ 0.498098] KASLR enabled
10448 10:03:08.741822 <6>[ 0.505815] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10449 10:03:08.748122 <6>[ 0.512826] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10450 10:03:08.754876 <6>[ 0.519315] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10451 10:03:08.761115 <6>[ 0.526317] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10452 10:03:08.768069 <6>[ 0.532804] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10453 10:03:08.774742 <6>[ 0.539808] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10454 10:03:08.781241 <6>[ 0.546295] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10455 10:03:08.788200 <6>[ 0.553299] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10456 10:03:08.791288 <6>[ 0.560814] ACPI: Interpreter disabled.
10457 10:03:08.799414 <6>[ 0.567197] iommu: Default domain type: Translated
10458 10:03:08.806438 <6>[ 0.572310] iommu: DMA domain TLB invalidation policy: strict mode
10459 10:03:08.809281 <5>[ 0.578966] SCSI subsystem initialized
10460 10:03:08.815954 <6>[ 0.583130] usbcore: registered new interface driver usbfs
10461 10:03:08.822887 <6>[ 0.588863] usbcore: registered new interface driver hub
10462 10:03:08.826353 <6>[ 0.594411] usbcore: registered new device driver usb
10463 10:03:08.833203 <6>[ 0.600496] pps_core: LinuxPPS API ver. 1 registered
10464 10:03:08.843727 <6>[ 0.605688] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10465 10:03:08.846751 <6>[ 0.615032] PTP clock support registered
10466 10:03:08.849295 <6>[ 0.619265] EDAC MC: Ver: 3.0.0
10467 10:03:08.857025 <6>[ 0.624404] FPGA manager framework
10468 10:03:08.863798 <6>[ 0.628084] Advanced Linux Sound Architecture Driver Initialized.
10469 10:03:08.867025 <6>[ 0.634851] vgaarb: loaded
10470 10:03:08.873358 <6>[ 0.638020] clocksource: Switched to clocksource arch_sys_counter
10471 10:03:08.876983 <5>[ 0.644459] VFS: Disk quotas dquot_6.6.0
10472 10:03:08.883494 <6>[ 0.648645] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10473 10:03:08.886860 <6>[ 0.655829] pnp: PnP ACPI: disabled
10474 10:03:08.895316 <6>[ 0.662540] NET: Registered PF_INET protocol family
10475 10:03:08.904796 <6>[ 0.668137] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10476 10:03:08.915933 <6>[ 0.680441] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10477 10:03:08.926140 <6>[ 0.689255] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10478 10:03:08.932768 <6>[ 0.697224] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10479 10:03:08.942740 <6>[ 0.705921] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10480 10:03:08.949084 <6>[ 0.715662] TCP: Hash tables configured (established 65536 bind 65536)
10481 10:03:08.955747 <6>[ 0.722518] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10482 10:03:08.966086 <6>[ 0.729715] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10483 10:03:08.969515 <6>[ 0.737416] NET: Registered PF_UNIX/PF_LOCAL protocol family
10484 10:03:08.976036 <6>[ 0.743576] RPC: Registered named UNIX socket transport module.
10485 10:03:08.982566 <6>[ 0.749732] RPC: Registered udp transport module.
10486 10:03:08.986297 <6>[ 0.754665] RPC: Registered tcp transport module.
10487 10:03:08.993278 <6>[ 0.759599] RPC: Registered tcp NFSv4.1 backchannel transport module.
10488 10:03:08.999227 <6>[ 0.766270] PCI: CLS 0 bytes, default 64
10489 10:03:09.002951 <6>[ 0.770512] Unpacking initramfs...
10490 10:03:09.009074 <6>[ 0.774626] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10491 10:03:09.019179 <6>[ 0.783271] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10492 10:03:09.026079 <6>[ 0.792115] kvm [1]: IPA Size Limit: 40 bits
10493 10:03:09.029066 <6>[ 0.796642] kvm [1]: GICv3: no GICV resource entry
10494 10:03:09.032374 <6>[ 0.801663] kvm [1]: disabling GICv2 emulation
10495 10:03:09.038998 <6>[ 0.806348] kvm [1]: GIC system register CPU interface enabled
10496 10:03:09.045703 <6>[ 0.812509] kvm [1]: vgic interrupt IRQ18
10497 10:03:09.048887 <6>[ 0.816865] kvm [1]: VHE mode initialized successfully
10498 10:03:09.055604 <5>[ 0.823241] Initialise system trusted keyrings
10499 10:03:09.062394 <6>[ 0.828026] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10500 10:03:09.070946 <6>[ 0.837930] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10501 10:03:09.077692 <5>[ 0.844319] NFS: Registering the id_resolver key type
10502 10:03:09.080047 <5>[ 0.849617] Key type id_resolver registered
10503 10:03:09.087751 <5>[ 0.854033] Key type id_legacy registered
10504 10:03:09.093932 <6>[ 0.858318] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10505 10:03:09.100221 <6>[ 0.865245] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10506 10:03:09.106839 <6>[ 0.872948] 9p: Installing v9fs 9p2000 file system support
10507 10:03:09.143084 <5>[ 0.910467] Key type asymmetric registered
10508 10:03:09.146082 <5>[ 0.914800] Asymmetric key parser 'x509' registered
10509 10:03:09.156307 <6>[ 0.919948] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10510 10:03:09.159806 <6>[ 0.927564] io scheduler mq-deadline registered
10511 10:03:09.163123 <6>[ 0.932323] io scheduler kyber registered
10512 10:03:09.182275 <6>[ 0.949306] EINJ: ACPI disabled.
10513 10:03:09.214310 <4>[ 0.975270] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10514 10:03:09.224550 <4>[ 0.985907] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10515 10:03:09.239425 <6>[ 1.006778] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10516 10:03:09.247496 <6>[ 1.014782] printk: console [ttyS0] disabled
10517 10:03:09.275404 <6>[ 1.039428] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10518 10:03:09.282187 <6>[ 1.048907] printk: console [ttyS0] enabled
10519 10:03:09.285128 <6>[ 1.048907] printk: console [ttyS0] enabled
10520 10:03:09.291907 <6>[ 1.057802] printk: bootconsole [mtk8250] disabled
10521 10:03:09.295157 <6>[ 1.057802] printk: bootconsole [mtk8250] disabled
10522 10:03:09.301576 <6>[ 1.069105] SuperH (H)SCI(F) driver initialized
10523 10:03:09.305497 <6>[ 1.074402] msm_serial: driver initialized
10524 10:03:09.319092 <6>[ 1.083467] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10525 10:03:09.329528 <6>[ 1.092024] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10526 10:03:09.336270 <6>[ 1.100566] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10527 10:03:09.345959 <6>[ 1.109194] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10528 10:03:09.355505 <6>[ 1.117905] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10529 10:03:09.362528 <6>[ 1.126625] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10530 10:03:09.371971 <6>[ 1.135167] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10531 10:03:09.378506 <6>[ 1.143973] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10532 10:03:09.389133 <6>[ 1.152518] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10533 10:03:09.400831 <6>[ 1.168272] loop: module loaded
10534 10:03:09.407269 <6>[ 1.173963] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10535 10:03:09.429764 <4>[ 1.197283] mtk-pmic-keys: Failed to locate of_node [id: -1]
10536 10:03:09.436543 <6>[ 1.204095] megasas: 07.719.03.00-rc1
10537 10:03:09.446044 <6>[ 1.213668] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10538 10:03:09.454085 <6>[ 1.221395] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10539 10:03:09.470578 <6>[ 1.238110] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10540 10:03:09.531517 <6>[ 1.292254] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10541 10:03:09.930091 <6>[ 1.697776] Freeing initrd memory: 20716K
10542 10:03:09.945991 <6>[ 1.713562] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10543 10:03:09.957096 <6>[ 1.724626] tun: Universal TUN/TAP device driver, 1.6
10544 10:03:09.960125 <6>[ 1.730699] thunder_xcv, ver 1.0
10545 10:03:09.963724 <6>[ 1.734202] thunder_bgx, ver 1.0
10546 10:03:09.966683 <6>[ 1.737691] nicpf, ver 1.0
10547 10:03:09.977270 <6>[ 1.741699] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10548 10:03:09.980474 <6>[ 1.749175] hns3: Copyright (c) 2017 Huawei Corporation.
10549 10:03:09.986872 <6>[ 1.754763] hclge is initializing
10550 10:03:09.990090 <6>[ 1.758343] e1000: Intel(R) PRO/1000 Network Driver
10551 10:03:09.996956 <6>[ 1.763473] e1000: Copyright (c) 1999-2006 Intel Corporation.
10552 10:03:10.000778 <6>[ 1.769487] e1000e: Intel(R) PRO/1000 Network Driver
10553 10:03:10.006837 <6>[ 1.774703] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10554 10:03:10.013750 <6>[ 1.780889] igb: Intel(R) Gigabit Ethernet Network Driver
10555 10:03:10.020170 <6>[ 1.786539] igb: Copyright (c) 2007-2014 Intel Corporation.
10556 10:03:10.026738 <6>[ 1.792374] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10557 10:03:10.033481 <6>[ 1.798893] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10558 10:03:10.036836 <6>[ 1.805357] sky2: driver version 1.30
10559 10:03:10.043636 <6>[ 1.810339] VFIO - User Level meta-driver version: 0.3
10560 10:03:10.050740 <6>[ 1.818572] usbcore: registered new interface driver usb-storage
10561 10:03:10.057309 <6>[ 1.825016] usbcore: registered new device driver onboard-usb-hub
10562 10:03:10.067031 <6>[ 1.834161] mt6397-rtc mt6359-rtc: registered as rtc0
10563 10:03:10.076654 <6>[ 1.839626] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-10T10:03:12 UTC (1686391392)
10564 10:03:10.080345 <6>[ 1.849204] i2c_dev: i2c /dev entries driver
10565 10:03:10.096455 <6>[ 1.860894] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10566 10:03:10.103613 <6>[ 1.871150] sdhci: Secure Digital Host Controller Interface driver
10567 10:03:10.110610 <6>[ 1.877587] sdhci: Copyright(c) Pierre Ossman
10568 10:03:10.116967 <6>[ 1.882978] Synopsys Designware Multimedia Card Interface Driver
10569 10:03:10.119974 <6>[ 1.889580] mmc0: CQHCI version 5.10
10570 10:03:10.127168 <6>[ 1.890127] sdhci-pltfm: SDHCI platform and OF driver helper
10571 10:03:10.134294 <6>[ 1.901728] ledtrig-cpu: registered to indicate activity on CPUs
10572 10:03:10.144930 <6>[ 1.909248] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10573 10:03:10.148398 <6>[ 1.916668] usbcore: registered new interface driver usbhid
10574 10:03:10.155503 <6>[ 1.922502] usbhid: USB HID core driver
10575 10:03:10.161640 <6>[ 1.926725] spi_master spi0: will run message pump with realtime priority
10576 10:03:10.203454 <6>[ 1.964512] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10577 10:03:10.221885 <6>[ 1.979459] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10578 10:03:10.225285 <6>[ 1.993069] mmc0: Command Queue Engine enabled
10579 10:03:10.232144 <6>[ 1.997847] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10580 10:03:10.238483 <6>[ 2.005119] mmcblk0: mmc0:0001 DA4128 116 GiB
10581 10:03:10.241593 <6>[ 2.010053] cros-ec-spi spi0.0: Chrome EC device registered
10582 10:03:10.250519 <6>[ 2.018494] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10583 10:03:10.258041 <6>[ 2.025654] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10584 10:03:10.264841 <6>[ 2.031670] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10585 10:03:10.271448 <6>[ 2.037440] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10586 10:03:10.288270 <6>[ 2.052875] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10587 10:03:10.296215 <6>[ 2.064279] NET: Registered PF_PACKET protocol family
10588 10:03:10.299741 <6>[ 2.069713] 9pnet: Installing 9P2000 support
10589 10:03:10.306809 <5>[ 2.074286] Key type dns_resolver registered
10590 10:03:10.309626 <6>[ 2.079331] registered taskstats version 1
10591 10:03:10.316186 <5>[ 2.083733] Loading compiled-in X.509 certificates
10592 10:03:10.349547 <4>[ 2.110432] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10593 10:03:10.359311 <4>[ 2.121126] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 10:03:10.369139 <3>[ 2.133809] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10595 10:03:10.381558 <6>[ 2.149255] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10596 10:03:10.388712 <6>[ 2.156019] xhci-mtk 11200000.usb: xHCI Host Controller
10597 10:03:10.394795 <6>[ 2.161518] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10598 10:03:10.405427 <6>[ 2.169365] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10599 10:03:10.411575 <6>[ 2.178796] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10600 10:03:10.418069 <6>[ 2.184960] xhci-mtk 11200000.usb: xHCI Host Controller
10601 10:03:10.424621 <6>[ 2.190540] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10602 10:03:10.431395 <6>[ 2.198230] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10603 10:03:10.438863 <6>[ 2.206180] hub 1-0:1.0: USB hub found
10604 10:03:10.442004 <6>[ 2.210227] hub 1-0:1.0: 1 port detected
10605 10:03:10.451577 <6>[ 2.214567] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10606 10:03:10.454971 <6>[ 2.223374] hub 2-0:1.0: USB hub found
10607 10:03:10.458412 <6>[ 2.227410] hub 2-0:1.0: 1 port detected
10608 10:03:10.466876 <6>[ 2.234577] mtk-msdc 11f70000.mmc: Got CD GPIO
10609 10:03:10.483427 <6>[ 2.247678] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10610 10:03:10.490101 <6>[ 2.255711] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10611 10:03:10.500070 <4>[ 2.263695] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10612 10:03:10.510092 <6>[ 2.273352] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10613 10:03:10.516650 <6>[ 2.281434] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10614 10:03:10.523678 <6>[ 2.289454] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10615 10:03:10.533175 <6>[ 2.297372] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10616 10:03:10.540164 <6>[ 2.305192] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10617 10:03:10.549492 <6>[ 2.313014] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10618 10:03:10.559512 <6>[ 2.323689] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10619 10:03:10.566951 <6>[ 2.332056] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10620 10:03:10.576809 <6>[ 2.340409] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10621 10:03:10.582660 <6>[ 2.348753] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10622 10:03:10.592927 <6>[ 2.357096] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10623 10:03:10.599231 <6>[ 2.365439] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10624 10:03:10.609679 <6>[ 2.373783] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10625 10:03:10.619035 <6>[ 2.382127] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10626 10:03:10.626023 <6>[ 2.390471] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10627 10:03:10.636665 <6>[ 2.398815] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10628 10:03:10.643012 <6>[ 2.407159] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10629 10:03:10.653158 <6>[ 2.415504] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10630 10:03:10.659170 <6>[ 2.423847] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10631 10:03:10.669149 <6>[ 2.432190] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10632 10:03:10.675872 <6>[ 2.440536] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10633 10:03:10.682814 <6>[ 2.449498] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10634 10:03:10.689703 <6>[ 2.456994] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10635 10:03:10.696289 <6>[ 2.464126] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10636 10:03:10.706944 <6>[ 2.471296] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10637 10:03:10.713637 <6>[ 2.478641] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10638 10:03:10.723374 <6>[ 2.485545] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10639 10:03:10.730292 <6>[ 2.494695] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10640 10:03:10.740374 <6>[ 2.503822] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10641 10:03:10.750236 <6>[ 2.513123] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10642 10:03:10.759451 <6>[ 2.522601] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10643 10:03:10.770293 <6>[ 2.532075] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10644 10:03:10.776049 <6>[ 2.541203] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10645 10:03:10.786064 <6>[ 2.550680] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10646 10:03:10.796133 <6>[ 2.559808] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10647 10:03:10.806102 <6>[ 2.569109] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10648 10:03:10.815884 <6>[ 2.579276] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10649 10:03:10.826075 <6>[ 2.590722] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10650 10:03:10.849824 <6>[ 2.614265] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10651 10:03:10.877109 <6>[ 2.644856] hub 2-1:1.0: USB hub found
10652 10:03:10.880399 <6>[ 2.649262] hub 2-1:1.0: 3 ports detected
10653 10:03:11.001589 <6>[ 2.766290] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10654 10:03:11.156366 <6>[ 2.924012] hub 1-1:1.0: USB hub found
10655 10:03:11.159406 <6>[ 2.928473] hub 1-1:1.0: 4 ports detected
10656 10:03:11.238465 <6>[ 3.002530] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10657 10:03:11.481506 <6>[ 3.246290] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10658 10:03:11.614457 <6>[ 3.382576] hub 1-1.4:1.0: USB hub found
10659 10:03:11.617826 <6>[ 3.387230] hub 1-1.4:1.0: 2 ports detected
10660 10:03:11.917719 <6>[ 3.682291] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10661 10:03:12.109391 <6>[ 3.874319] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10662 10:03:23.117755 <6>[ 14.890843] ALSA device list:
10663 10:03:23.124351 <6>[ 14.894100] No soundcards found.
10664 10:03:23.137059 <6>[ 14.906489] Freeing unused kernel memory: 8384K
10665 10:03:23.140233 <6>[ 14.911402] Run /init as init process
10666 10:03:23.164730 Starting syslogd: OK
10667 10:03:23.169079 Starting klogd: OK
10668 10:03:23.178410 Running sysctl: OK
10669 10:03:23.187875 Populating /dev using udev: <30>[ 14.956346] udevd[185]: starting version 3.2.9
10670 10:03:23.194519 <27>[ 14.964330] udevd[185]: specified user 'tss' unknown
10671 10:03:23.201154 <27>[ 14.969747] udevd[185]: specified group 'tss' unknown
10672 10:03:23.207812 <30>[ 14.976335] udevd[186]: starting eudev-3.2.9
10673 10:03:23.237790 <27>[ 15.007332] udevd[186]: specified user 'tss' unknown
10674 10:03:23.244203 <27>[ 15.012721] udevd[186]: specified group 'tss' unknown
10675 10:03:23.420595 <6>[ 15.186979] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10676 10:03:23.447043 <6>[ 15.213151] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10677 10:03:23.450776 <6>[ 15.214441] remoteproc remoteproc0: scp is available
10678 10:03:23.460459 <6>[ 15.220815] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10679 10:03:23.470242 <4>[ 15.228446] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10680 10:03:23.480329 <6>[ 15.234741] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10681 10:03:23.483242 <6>[ 15.253536] remoteproc remoteproc0: powering up scp
10682 10:03:23.493282 <4>[ 15.258935] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10683 10:03:23.499874 <3>[ 15.268878] remoteproc remoteproc0: request_firmware failed: -2
10684 10:03:23.508223 <6>[ 15.277909] mc: Linux media interface: v0.10
10685 10:03:23.514884 <6>[ 15.281511] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10686 10:03:23.521542 <6>[ 15.285353] usbcore: registered new interface driver r8152
10687 10:03:23.528147 <4>[ 15.287569] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10688 10:03:23.534466 <4>[ 15.287708] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10689 10:03:23.545278 <3>[ 15.311734] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 10:03:23.555272 <3>[ 15.320306] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 10:03:23.561640 <3>[ 15.328622] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 10:03:23.571351 <3>[ 15.337151] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 10:03:23.574909 <6>[ 15.337649] videodev: Linux video capture interface: v2.00
10694 10:03:23.585050 <3>[ 15.345471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 10:03:23.591584 <6>[ 15.355341] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10696 10:03:23.598086 <3>[ 15.359240] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 10:03:23.604363 <6>[ 15.366271] pci_bus 0000:00: root bus resource [bus 00-ff]
10698 10:03:23.614223 <3>[ 15.374424] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 10:03:23.621635 <6>[ 15.380036] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10700 10:03:23.628006 <3>[ 15.388145] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 10:03:23.638013 <4>[ 15.394675] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10702 10:03:23.641571 <4>[ 15.394675] Fallback method does not support PEC.
10703 10:03:23.651852 <6>[ 15.395238] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10704 10:03:23.658225 <6>[ 15.395314] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10705 10:03:23.668495 <6>[ 15.399872] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10706 10:03:23.675062 <6>[ 15.403676] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10707 10:03:23.681562 <3>[ 15.404216] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 10:03:23.691635 <3>[ 15.404275] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 10:03:23.697809 <3>[ 15.404283] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 10:03:23.707702 <3>[ 15.404290] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 10:03:23.714789 <3>[ 15.404353] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 10:03:23.724156 <3>[ 15.404361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 10:03:23.730988 <3>[ 15.404367] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 10:03:23.740694 <3>[ 15.404374] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 10:03:23.747567 <3>[ 15.404380] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 10:03:23.757338 <3>[ 15.404407] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 10:03:23.764290 <6>[ 15.417068] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10718 10:03:23.770731 <3>[ 15.418353] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10719 10:03:23.783846 <6>[ 15.426572] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10720 10:03:23.790932 <6>[ 15.427306] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10721 10:03:23.797152 <6>[ 15.433736] pci 0000:00:00.0: supports D1 D2
10722 10:03:23.803937 <3>[ 15.449292] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10723 10:03:23.810177 <6>[ 15.449789] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10724 10:03:23.820572 <4>[ 15.463814] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10725 10:03:23.830305 <6>[ 15.469369] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10726 10:03:23.837041 <4>[ 15.474048] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10727 10:03:23.843326 <6>[ 15.474489] usbcore: registered new interface driver cdc_ether
10728 10:03:23.849862 <6>[ 15.482276] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10729 10:03:23.856647 <6>[ 15.483016] usbcore: registered new interface driver r8153_ecm
10730 10:03:23.860498 <6>[ 15.483052] Bluetooth: Core ver 2.22
10731 10:03:23.863208 <6>[ 15.483188] NET: Registered PF_BLUETOOTH protocol family
10732 10:03:23.869722 <6>[ 15.483191] Bluetooth: HCI device and connection manager initialized
10733 10:03:23.876764 <6>[ 15.483222] Bluetooth: HCI socket layer initialized
10734 10:03:23.883273 <6>[ 15.483227] Bluetooth: L2CAP socket layer initialized
10735 10:03:23.886424 <6>[ 15.483240] Bluetooth: SCO socket layer initialized
10736 10:03:23.893179 <6>[ 15.507885] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10737 10:03:23.899483 <6>[ 15.514499] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10738 10:03:23.912645 <6>[ 15.524141] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10739 10:03:23.922497 <6>[ 15.530683] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10740 10:03:23.926034 <6>[ 15.532004] usbcore: registered new interface driver btusb
10741 10:03:23.936257 <4>[ 15.532898] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10742 10:03:23.942835 <3>[ 15.532908] Bluetooth: hci0: Failed to load firmware file (-2)
10743 10:03:23.949100 <3>[ 15.532912] Bluetooth: hci0: Failed to set up firmware (-2)
10744 10:03:23.959322 <4>[ 15.532916] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10745 10:03:23.965604 <6>[ 15.538756] usbcore: registered new interface driver uvcvideo
10746 10:03:23.972848 <6>[ 15.539032] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10747 10:03:23.979112 <6>[ 15.543903] remoteproc remoteproc0: powering up scp
10748 10:03:23.985810 <4>[ 15.543942] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10749 10:03:23.992360 <3>[ 15.543950] remoteproc remoteproc0: request_firmware failed: -2
10750 10:03:24.002236 <3>[ 15.543953] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10751 10:03:24.005492 <6>[ 15.546285] r8152 2-1.3:1.0 eth0: v1.12.13
10752 10:03:24.012212 <6>[ 15.546933] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10753 10:03:24.019330 <6>[ 15.787592] pci 0000:01:00.0: supports D1 D2
10754 10:03:24.025539 <6>[ 15.792126] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10755 10:03:24.048078 <6>[ 15.814266] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10756 10:03:24.054321 <6>[ 15.821224] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10757 10:03:24.061097 <6>[ 15.829316] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10758 10:03:24.070996 <6>[ 15.837321] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10759 10:03:24.077474 <6>[ 15.845332] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10760 10:03:24.087495 <6>[ 15.853339] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10761 10:03:24.090951 <6>[ 15.861346] pci 0000:00:00.0: PCI bridge to [bus 01]
10762 10:03:24.101070 <6>[ 15.866567] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10763 10:03:24.107553 <6>[ 15.874807] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10764 10:03:24.113753 <6>[ 15.882086] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10765 10:03:24.120799 <6>[ 15.888583] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10766 10:03:24.138500 <5>[ 15.905077] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10767 10:03:24.171227 <5>[ 15.937978] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10768 10:03:24.178268 <4>[ 15.944913] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10769 10:03:24.184695 <6>[ 15.953809] cfg80211: failed to load regulatory.db
10770 10:03:24.229577 <6>[ 15.995542] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10771 10:03:24.235688 <6>[ 16.003063] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10772 10:03:24.260394 <6>[ 16.029988] mt7921e 0000:01:00.0: ASIC revision: 79610010
10773 10:03:24.366087 <4>[ 16.129595] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 10:03:24.386276 done
10775 10:03:24.395388 Saving random seed: OK
10776 10:03:24.411164 Starting network: OK
10777 10:03:24.450124 Starting dropbear sshd: <6>[ 16.220016] NET: Registered PF_INET6 protocol family
10778 10:03:24.457009 <6>[ 16.226215] Segment Routing with IPv6
10779 10:03:24.460231 <6>[ 16.230228] In-situ OAM (IOAM) with IPv6
10780 10:03:24.468212 OK
10781 10:03:24.487554 <4>[ 16.250876] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 10:03:24.495223 /bin/sh: can't access tty; job control turned off
10783 10:03:24.495525 Matched prompt #10: / #
10785 10:03:24.495729 Setting prompt string to ['/ #']
10786 10:03:24.495821 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10788 10:03:24.496011 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10789 10:03:24.496096 start: 2.2.6 expect-shell-connection (timeout 00:03:17) [common]
10790 10:03:24.496170 Setting prompt string to ['/ #']
10791 10:03:24.496232 Forcing a shell prompt, looking for ['/ #']
10793 10:03:24.546443 / #
10794 10:03:24.546548 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10795 10:03:24.546625 Waiting using forced prompt support (timeout 00:02:30)
10796 10:03:24.551636
10797 10:03:24.551909 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10798 10:03:24.552004 start: 2.2.7 export-device-env (timeout 00:03:17) [common]
10799 10:03:24.552098 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10800 10:03:24.552183 end: 2.2 depthcharge-retry (duration 00:01:43) [common]
10801 10:03:24.552266 end: 2 depthcharge-action (duration 00:01:43) [common]
10802 10:03:24.552355 start: 3 lava-test-retry (timeout 00:01:00) [common]
10803 10:03:24.552443 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10804 10:03:24.552518 Using namespace: common
10806 10:03:24.652818 / # #
10807 10:03:24.652945 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10808 10:03:24.653054 <4>[ 16.368396] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 10:03:24.658388 #
10810 10:03:24.658653 Using /lava-10670658
10812 10:03:24.758981 / # export SHELL=/bin/sh
10813 10:03:24.759129 export SHELL=/bin/<4>[ 16.488437] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10814 10:03:24.764052 sh
10816 10:03:24.864538 / # . /lava-10670658/environment
10817 10:03:24.864685 . /lava-10670658/environment<4>[ 16.608393] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10818 10:03:24.870277
10820 10:03:24.970921 / # /lava-10670658/bin/lava-test-runner /lava-10670658/0
10821 10:03:24.971066 Test shell timeout: 10s (minimum of the action and connection timeout)
10822 10:03:24.971436 /lava-10670658/bin/lava-test-runner /lava-10670658/0<4>[ 16.728461] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10823 10:03:24.976591
10824 10:03:25.019438 + export 'TESTRUN_ID=0_dmesg'
10825 10:03:25.019527 +<8>[ 16.773806] <LAVA_SIGNAL_STARTRUN 0_dmesg 10670658_1.5.2.3.1>
10826 10:03:25.019772 Received signal: <STARTRUN> 0_dmesg 10670658_1.5.2.3.1
10827 10:03:25.019845 Starting test lava.0_dmesg (10670658_1.5.2.3.1)
10828 10:03:25.019928 Skipping test definition patterns.
10829 10:03:25.020028 cd /lava-10670658/0/tests/0_dmesg
10830 10:03:25.020092 + cat uuid
10831 10:03:25.020154 + UUID=10670658_1.5.2.3.1
10832 10:03:25.020212 + set +x
10833 10:03:25.020269 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10834 10:03:25.028810 <8>[ 16.793559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10835 10:03:25.029063 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10837 10:03:25.046544 <8>[ 16.813093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10838 10:03:25.046797 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10840 10:03:25.067543 <8>[ 16.833669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10841 10:03:25.067797 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10843 10:03:25.071590 + set +x
10844 10:03:25.075102 Received signal: <ENDRUN> 0_dmesg 10670658_1.5.2.3.1
10845 10:03:25.075198 Ending use of test pattern.
10846 10:03:25.075265 Ending test lava.0_dmesg (10670658_1.5.2.3.1), duration 0.06
10848 10:03:25.078022 <8>[ 16.844806] <LAVA_SIGNAL_ENDRUN 0_dmesg 10670658_1.5.2.3.1>
10849 10:03:25.087735 <4>[ 16.848951] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10850 10:03:25.090985 <LAVA_TEST_RUNNER EXIT>
10851 10:03:25.091236 ok: lava_test_shell seems to have completed
10852 10:03:25.091340 alert: pass
crit: pass
emerg: pass
10853 10:03:25.091468 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10854 10:03:25.091552 end: 3 lava-test-retry (duration 00:00:01) [common]
10855 10:03:25.091638 start: 4 lava-test-retry (timeout 00:01:00) [common]
10856 10:03:25.091720 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10857 10:03:25.091786 Using namespace: common
10859 10:03:25.192107 / # #
10860 10:03:25.192230 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10861 10:03:25.192336 Using /lava-10670658
10863 10:03:25.292658 export SHELL=/bin/sh
10864 10:03:25.292800 #<4>[ 16.968533] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10865 10:03:25.292874
10867 10:03:25.393374 / # export SHELL=/bin/sh. /lava-10670658/environment
10868 10:03:25.393520
10869 10:03:25.393595 / # <4>[ 17.088699] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10871 10:03:25.494074 . /lava-10670658/environment/lava-10670658/bin/lava-test-runner /lava-10670658/1
10872 10:03:25.494193 Test shell timeout: 10s (minimum of the action and connection timeout)
10873 10:03:25.494304
10874 10:03:25.494372 / # <4>[ 17.208223] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10875 10:03:25.499022 /lava-10670658/bin/lava-test-runner /lava-10670658/1
10876 10:03:25.543499 + export 'TESTRUN_ID=1_bootrr'
10877 10:03:25.543589 <8>[ 17.291925] <LAVA_SIGNAL_STARTRUN 1_bootrr 10670658_1.5.2.3.5>
10878 10:03:25.543657 + cd /lava-10670658/1/tests/1_bootrr
10879 10:03:25.543722 + cat uuid
10880 10:03:25.543782 + UUID=10670658_1.5.2.3.5
10881 10:03:25.543842 + set +x
10882 10:03:25.544077 Received signal: <STARTRUN> 1_bootrr 10670658_1.5.2.3.5
10883 10:03:25.544146 Starting test lava.1_bootrr (10670658_1.5.2.3.5)
10884 10:03:25.544225 Skipping test definition patterns.
10885 10:03:25.546512 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10670658/1/../bin:/sbin:/usr/sbin<8>[ 17.313326] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10886 10:03:25.546770 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10888 10:03:25.549926 :/bin:/usr/bin'
10889 10:03:25.550010 + cd /opt/bootrr/libexec/bootrr
10890 10:03:25.556260 + sh helpers/b<3>[ 17.327334] mt7921e 0000:01:00.0: hardware init failed
10891 10:03:25.559842 ootrr-auto
10892 10:03:25.562637 /lava-10670658/1/../bin/lava-test-case
10893 10:03:25.569713 /lava-106706<8>[ 17.337858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10894 10:03:25.569968 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10896 10:03:25.572792 58/1/../bin/lava-test-case
10897 10:03:25.576127 /usr/bin/tpm2_getcap
10898 10:03:25.612541 /lava-10670658/1/../bin/lava-test-case
10899 10:03:25.618867 <8>[ 17.386036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10900 10:03:25.619126 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10902 10:03:25.636082 /lava-10670658/1/../bin/lava-test-case
10903 10:03:25.642535 <8>[ 17.409952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10904 10:03:25.642791 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10906 10:03:25.654519 /lava-10670658/1/../bin/lava-test-case
10907 10:03:25.661324 <8>[ 17.427785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10908 10:03:25.661579 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10910 10:03:25.672585 /lava-10670658/1/../bin/lava-test-case
10911 10:03:25.678524 <8>[ 17.446052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10912 10:03:25.678780 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10914 10:03:25.690435 /lava-10670658/1/../bin/lava-test-case
10915 10:03:25.697610 <8>[ 17.463970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10916 10:03:25.697865 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10918 10:03:25.709197 /lava-10670658/1/../bin/lava-test-case
10919 10:03:25.715193 <8>[ 17.481885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10920 10:03:25.715450 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10922 10:03:25.724959 /lava-10670658/1/../bin/lava-test-case
10923 10:03:25.731322 <8>[ 17.498237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10924 10:03:25.731615 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10926 10:03:25.742596 /lava-10670658/1/../bin/lava-test-case
10927 10:03:25.749391 <8>[ 17.516303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10928 10:03:25.749646 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10930 10:03:25.759150 /lava-10670658/1/../bin/lava-test-case
10931 10:03:25.765439 <8>[ 17.532062] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10932 10:03:25.765695 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10934 10:03:25.777753 /lava-10670658/1/../bin/lava-test-case
10935 10:03:25.784546 <8>[ 17.551130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10936 10:03:25.784802 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10938 10:03:25.795806 /lava-10670658/1/../bin/lava-test-case
10939 10:03:25.802531 <8>[ 17.569175] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10940 10:03:25.802786 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10942 10:03:25.814489 /lava-10670658/1/../bin/lava-test-case
10943 10:03:25.820604 <8>[ 17.587401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10944 10:03:25.820899 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10946 10:03:25.833226 /lava-10670658/1/../bin/lava-test-case
10947 10:03:25.839583 <8>[ 17.606488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10948 10:03:25.839843 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10950 10:03:25.850461 /lava-10670658/1/../bin/lava-test-case
10951 10:03:25.856309 <8>[ 17.622718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10952 10:03:25.856585 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10954 10:03:25.867980 /lava-10670658/1/../bin/lava-test-case
10955 10:03:25.874410 <8>[ 17.641273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10956 10:03:25.874658 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10958 10:03:25.883173 /lava-10670658/1/../bin/lava-test-case
10959 10:03:25.890346 <8>[ 17.656976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10960 10:03:25.890598 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10962 10:03:25.901802 /lava-10670658/1/../bin/lava-test-case
10963 10:03:25.908119 <8>[ 17.675452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10964 10:03:25.908404 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10966 10:03:25.917621 /lava-10670658/1/../bin/lava-test-case
10967 10:03:25.924469 <8>[ 17.691078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10968 10:03:25.924757 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10970 10:03:25.935821 /lava-10670658/1/../bin/lava-test-case
10971 10:03:25.942140 <8>[ 17.709141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10972 10:03:25.942426 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10974 10:03:25.951465 /lava-10670658/1/../bin/lava-test-case
10975 10:03:25.958054 <8>[ 17.724908] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10976 10:03:25.958303 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10978 10:03:25.969695 /lava-10670658/1/../bin/lava-test-case
10979 10:03:25.976173 <8>[ 17.743167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10980 10:03:25.976419 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10982 10:03:25.985312 /lava-10670658/1/../bin/lava-test-case
10983 10:03:25.991988 <8>[ 17.758760] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10984 10:03:25.992231 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10986 10:03:26.004008 /lava-10670658/1/../bin/lava-test-case
10987 10:03:26.010307 <8>[ 17.776974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10988 10:03:26.010586 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10990 10:03:26.022799 /lava-10670658/1/../bin/lava-test-case
10991 10:03:26.029183 <8>[ 17.795822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10992 10:03:26.029458 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10994 10:03:26.038657 /lava-10670658/1/../bin/lava-test-case
10995 10:03:26.045680 <8>[ 17.811966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10996 10:03:26.045909 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10998 10:03:26.056951 /lava-10670658/1/../bin/lava-test-case
10999 10:03:26.063713 <8>[ 17.829768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11000 10:03:26.063991 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11002 10:03:26.073155 /lava-10670658/1/../bin/lava-test-case
11003 10:03:26.079331 <8>[ 17.845885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11004 10:03:26.079605 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11006 10:03:26.091805 /lava-10670658/1/../bin/lava-test-case
11007 10:03:26.098452 <8>[ 17.864782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11008 10:03:26.098717 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11010 10:03:26.109574 /lava-10670658/1/../bin/lava-test-case
11011 10:03:26.116668 <8>[ 17.882933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11012 10:03:26.117031 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11014 10:03:26.127382 /lava-10670658/1/../bin/lava-test-case
11015 10:03:26.134332 <8>[ 17.900603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11016 10:03:26.134623 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11018 10:03:26.145312 /lava-10670658/1/../bin/lava-test-case
11019 10:03:26.152469 <8>[ 17.918461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11020 10:03:26.152730 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11022 10:03:26.162224 /lava-10670658/1/../bin/lava-test-case
11023 10:03:26.168656 <8>[ 17.935408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11024 10:03:26.168920 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11026 10:03:26.180738 /lava-10670658/1/../bin/lava-test-case
11027 10:03:26.187844 <8>[ 17.954155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11028 10:03:26.188116 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11030 10:03:26.198589 /lava-10670658/1/../bin/lava-test-case
11031 10:03:26.205067 <8>[ 17.971889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11032 10:03:26.205344 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11034 10:03:26.214260 /lava-10670658/1/../bin/lava-test-case
11035 10:03:26.220826 <8>[ 17.988001] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11036 10:03:26.221108 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11038 10:03:26.232907 /lava-10670658/1/../bin/lava-test-case
11039 10:03:26.239268 <8>[ 18.005833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11040 10:03:26.239581 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11042 10:03:26.248915 /lava-10670658/1/../bin/lava-test-case
11043 10:03:26.255575 <8>[ 18.021952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11044 10:03:26.255828 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11046 10:03:26.268063 /lava-10670658/1/../bin/lava-test-case
11047 10:03:26.274444 <8>[ 18.041785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11048 10:03:26.274696 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11050 10:03:26.284652 /lava-10670658/1/../bin/lava-test-case
11051 10:03:26.291242 <8>[ 18.057571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11052 10:03:26.291528 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11054 10:03:26.302870 /lava-10670658/1/../bin/lava-test-case
11055 10:03:26.309328 <8>[ 18.076270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11056 10:03:26.309582 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11058 10:03:26.318365 /lava-10670658/1/../bin/lava-test-case
11059 10:03:26.325194 <8>[ 18.091445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11060 10:03:26.325448 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11062 10:03:26.338131 /lava-10670658/1/../bin/lava-test-case
11063 10:03:26.344390 <8>[ 18.110819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11064 10:03:26.344645 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11066 10:03:26.354788 /lava-10670658/1/../bin/lava-test-case
11067 10:03:26.360821 <8>[ 18.127517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11068 10:03:26.361066 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11070 10:03:26.372923 /lava-10670658/1/../bin/lava-test-case
11071 10:03:26.379555 <8>[ 18.146311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11072 10:03:26.379803 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11074 10:03:26.388410 /lava-10670658/1/../bin/lava-test-case
11075 10:03:26.395538 <8>[ 18.161482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11076 10:03:26.395779 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11078 10:03:26.405891 /lava-10670658/1/../bin/lava-test-case
11079 10:03:26.412380 <8>[ 18.179065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11080 10:03:26.412634 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11082 10:03:26.421465 /lava-10670658/1/../bin/lava-test-case
11083 10:03:26.428404 <8>[ 18.194742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11084 10:03:26.428655 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11086 10:03:26.439370 /lava-10670658/1/../bin/lava-test-case
11087 10:03:26.446239 <8>[ 18.212910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11088 10:03:26.446492 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11090 10:03:26.458220 /lava-10670658/1/../bin/lava-test-case
11091 10:03:26.464196 <8>[ 18.230765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11092 10:03:26.464448 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11094 10:03:27.475437 /lava-10670658/1/../bin/lava-test-case
11095 10:03:27.482725 <8>[ 19.250241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11096 10:03:27.482991 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11098 10:03:28.495518 /lava-10670658/1/../bin/lava-test-case
11099 10:03:28.501802 <8>[ 20.268991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11100 10:03:28.502301 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11101 10:03:28.502392 Bad test result: blocked
11102 10:03:28.511480 /lava-10670658/1/../bin/lava-test-case
11103 10:03:28.518259 <8>[ 20.285483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11104 10:03:28.518622 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11106 10:03:28.530808 /lava-10670658/1/../bin/lava-test-case
11107 10:03:28.537119 <8>[ 20.304163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11108 10:03:28.537546 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11110 10:03:28.548162 /lava-10670658/1/../bin/lava-test-case
11111 10:03:28.554700 <8>[ 20.321563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11112 10:03:28.555268 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11114 10:03:28.566239 /lava-10670658/1/../bin/lava-test-case
11115 10:03:28.573138 <8>[ 20.339583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11116 10:03:28.573980 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11118 10:03:28.583935 /lava-10670658/1/../bin/lava-test-case
11119 10:03:28.590614 <8>[ 20.356758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11120 10:03:28.591471 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11122 10:03:28.601644 /lava-10670658/1/../bin/lava-test-case
11123 10:03:28.607784 <8>[ 20.374004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11124 10:03:28.608619 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11126 10:03:28.616419 /lava-10670658/1/../bin/lava-test-case
11127 10:03:28.622975 <8>[ 20.389026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11128 10:03:28.623906 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11130 10:03:28.633806 /lava-10670658/1/../bin/lava-test-case
11131 10:03:28.640286 <8>[ 20.406839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11132 10:03:28.641121 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11134 10:03:28.651089 /lava-10670658/1/../bin/lava-test-case
11135 10:03:28.657598 <8>[ 20.424508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11136 10:03:28.658450 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11138 10:03:28.666589 /lava-10670658/1/../bin/lava-test-case
11139 10:03:28.673039 <8>[ 20.439977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11140 10:03:28.673942 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11142 10:03:28.685666 /lava-10670658/1/../bin/lava-test-case
11143 10:03:28.692279 <8>[ 20.458814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11144 10:03:28.693296 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11146 10:03:28.701753 /lava-10670658/1/../bin/lava-test-case
11147 10:03:28.708343 <8>[ 20.474575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11148 10:03:28.709171 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11150 10:03:28.719812 /lava-10670658/1/../bin/lava-test-case
11151 10:03:28.726978 <8>[ 20.493049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11152 10:03:28.727691 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11154 10:03:28.735485 /lava-10670658/1/../bin/lava-test-case
11155 10:03:28.742462 <8>[ 20.508624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11156 10:03:28.743311 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11158 10:03:28.753813 /lava-10670658/1/../bin/lava-test-case
11159 10:03:28.760378 <8>[ 20.527910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11160 10:03:28.761210 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11162 10:03:28.772256 /lava-10670658/1/../bin/lava-test-case
11163 10:03:28.778952 <8>[ 20.545886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11164 10:03:28.779841 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11166 10:03:28.791453 /lava-10670658/1/../bin/lava-test-case
11167 10:03:28.797919 <8>[ 20.564552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11168 10:03:28.798757 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11170 10:03:28.808622 /lava-10670658/1/../bin/lava-test-case
11171 10:03:28.815318 <8>[ 20.582415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11172 10:03:28.816199 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11174 10:03:28.827696 /lava-10670658/1/../bin/lava-test-case
11175 10:03:28.834128 <8>[ 20.600634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11176 10:03:28.834951 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11178 10:03:28.845676 /lava-10670658/1/../bin/lava-test-case
11179 10:03:28.852111 <8>[ 20.619270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11180 10:03:28.852836 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11182 10:03:28.864581 /lava-10670658/1/../bin/lava-test-case
11183 10:03:28.870755 <8>[ 20.637441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11184 10:03:28.871564 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11186 10:03:28.883594 /lava-10670658/1/../bin/lava-test-case
11187 10:03:28.889544 <8>[ 20.656257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11188 10:03:28.890404 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11190 10:03:28.901523 /lava-10670658/1/../bin/lava-test-case
11191 10:03:28.908417 <8>[ 20.674481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11192 10:03:28.909340 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11194 10:03:28.919192 /lava-10670658/1/../bin/lava-test-case
11195 10:03:28.925759 <8>[ 20.692259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11196 10:03:28.926641 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11198 10:03:28.937497 /lava-10670658/1/../bin/lava-test-case
11199 10:03:28.943825 <8>[ 20.710811] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11200 10:03:28.944683 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11202 10:03:28.955321 /lava-10670658/1/../bin/lava-test-case
11203 10:03:28.962487 <8>[ 20.728733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11204 10:03:28.963344 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11206 10:03:28.974044 /lava-10670658/1/../bin/lava-test-case
11207 10:03:28.980173 <8>[ 20.746773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11208 10:03:28.980879 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11210 10:03:28.991936 /lava-10670658/1/../bin/lava-test-case
11211 10:03:28.998473 <8>[ 20.764807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11212 10:03:28.999291 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11214 10:03:29.010575 /lava-10670658/1/../bin/lava-test-case
11215 10:03:29.016692 <8>[ 20.782896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11216 10:03:29.017555 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11218 10:03:29.026065 /lava-10670658/1/../bin/lava-test-case
11219 10:03:29.032413 <8>[ 20.799049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11220 10:03:29.033203 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11222 10:03:29.043777 /lava-10670658/1/../bin/lava-test-case
11223 10:03:29.050102 <8>[ 20.816456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11224 10:03:29.050939 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11226 10:03:29.059006 /lava-10670658/1/../bin/lava-test-case
11227 10:03:29.065645 <8>[ 20.832005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11228 10:03:29.066516 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11230 10:03:29.077903 /lava-10670658/1/../bin/lava-test-case
11231 10:03:29.083510 <8>[ 20.849833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11232 10:03:29.084336 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11234 10:03:29.093656 /lava-10670658/1/../bin/lava-test-case
11235 10:03:29.100231 <8>[ 20.866156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11236 10:03:29.101036 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11238 10:03:29.111644 /lava-10670658/1/../bin/lava-test-case
11239 10:03:29.117938 <8>[ 20.884600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11240 10:03:29.118637 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11242 10:03:29.127641 /lava-10670658/1/../bin/lava-test-case
11243 10:03:29.133784 <8>[ 20.900335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11244 10:03:29.134592 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11246 10:03:29.146198 /lava-10670658/1/../bin/lava-test-case
11247 10:03:29.153134 <8>[ 20.919223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11248 10:03:29.153926 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11250 10:03:29.162621 /lava-10670658/1/../bin/lava-test-case
11251 10:03:29.169089 <8>[ 20.935120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11252 10:03:29.169946 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11254 10:03:29.179990 /lava-10670658/1/../bin/lava-test-case
11255 10:03:29.187012 <8>[ 20.952749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11256 10:03:29.187855 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11258 10:03:29.195920 /lava-10670658/1/../bin/lava-test-case
11259 10:03:29.202265 <8>[ 20.968613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11260 10:03:29.203069 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11262 10:03:29.214194 /lava-10670658/1/../bin/lava-test-case
11263 10:03:29.220312 <8>[ 20.987107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11264 10:03:29.221014 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11266 10:03:29.232417 /lava-10670658/1/../bin/lava-test-case
11267 10:03:29.239786 <8>[ 21.005511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11268 10:03:29.240736 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11270 10:03:29.249268 /lava-10670658/1/../bin/lava-test-case
11271 10:03:29.254929 <8>[ 21.021239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11272 10:03:29.255649 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11274 10:03:29.266761 /lava-10670658/1/../bin/lava-test-case
11275 10:03:29.273129 <8>[ 21.039748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11276 10:03:29.273934 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11278 10:03:29.282792 /lava-10670658/1/../bin/lava-test-case
11279 10:03:29.289754 <8>[ 21.055720] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11280 10:03:29.290618 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11282 10:03:29.301319 /lava-10670658/1/../bin/lava-test-case
11283 10:03:29.307901 <8>[ 21.074125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11284 10:03:29.308817 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11286 10:03:29.316254 /lava-10670658/1/../bin/lava-test-case
11287 10:03:29.322583 <8>[ 21.088797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11288 10:03:29.323491 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11290 10:03:30.335548 /lava-10670658/1/../bin/lava-test-case
11291 10:03:30.341691 <8>[ 22.109662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11292 10:03:30.342000 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11294 10:03:30.350657 /lava-10670658/1/../bin/lava-test-case
11295 10:03:30.357382 <8>[ 22.125142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11296 10:03:30.357777 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11298 10:03:31.371410 /lava-10670658/1/../bin/lava-test-case
11299 10:03:31.377854 <8>[ 23.145843] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11300 10:03:31.378120 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11302 10:03:31.386940 /lava-10670658/1/../bin/lava-test-case
11303 10:03:31.393604 <8>[ 23.160879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11304 10:03:31.393856 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11306 10:03:32.409303 /lava-10670658/1/../bin/lava-test-case
11307 10:03:32.415247 <8>[ 24.182969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11308 10:03:32.415977 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11310 10:03:32.424890 /lava-10670658/1/../bin/lava-test-case
11311 10:03:32.431620 <8>[ 24.198824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11312 10:03:32.432621 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11314 10:03:33.445724 /lava-10670658/1/../bin/lava-test-case
11315 10:03:33.452306 <8>[ 25.219566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11316 10:03:33.453103 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11318 10:03:33.461290 /lava-10670658/1/../bin/lava-test-case
11319 10:03:33.467851 <8>[ 25.234977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11320 10:03:33.468673 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11322 10:03:34.481232 /lava-10670658/1/../bin/lava-test-case
11323 10:03:34.487534 <8>[ 26.255652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11324 10:03:34.488395 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11326 10:03:34.496837 /lava-10670658/1/../bin/lava-test-case
11327 10:03:34.503761 <8>[ 26.270979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11328 10:03:34.504558 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11330 10:03:35.518291 /lava-10670658/1/../bin/lava-test-case
11331 10:03:35.525046 <8>[ 27.292894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11332 10:03:35.525886 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11334 10:03:35.534990 /lava-10670658/1/../bin/lava-test-case
11335 10:03:35.541200 <8>[ 27.308523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11336 10:03:35.542015 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11338 10:03:36.555127 /lava-10670658/1/../bin/lava-test-case
11339 10:03:36.561724 <8>[ 28.329718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11340 10:03:36.562530 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11342 10:03:36.571425 /lava-10670658/1/../bin/lava-test-case
11343 10:03:36.578095 <8>[ 28.345721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11344 10:03:36.578896 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11346 10:03:36.587614 /lava-10670658/1/../bin/lava-test-case
11347 10:03:36.594084 <8>[ 28.361508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11348 10:03:36.594908 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11350 10:03:37.608213 /lava-10670658/1/../bin/lava-test-case
11351 10:03:37.614649 <8>[ 29.382965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11352 10:03:37.615477 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11354 10:03:37.625503 /lava-10670658/1/../bin/lava-test-case
11355 10:03:37.632269 <8>[ 29.399847] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11356 10:03:37.633090 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11358 10:03:37.644456 /lava-10670658/1/../bin/lava-test-case
11359 10:03:37.651166 <8>[ 29.418810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11360 10:03:37.652006 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11362 10:03:37.660637 /lava-10670658/1/../bin/lava-test-case
11363 10:03:37.667240 <8>[ 29.435122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11364 10:03:37.668083 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11366 10:03:37.679612 /lava-10670658/1/../bin/lava-test-case
11367 10:03:37.686194 <8>[ 29.453574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11368 10:03:37.686994 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11370 10:03:37.698092 /lava-10670658/1/../bin/lava-test-case
11371 10:03:37.704754 <8>[ 29.472233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11372 10:03:37.705560 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11374 10:03:37.716335 /lava-10670658/1/../bin/lava-test-case
11375 10:03:37.722852 <8>[ 29.490550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11376 10:03:37.723690 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11378 10:03:37.733342 /lava-10670658/1/../bin/lava-test-case
11379 10:03:37.739423 <8>[ 29.507170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11380 10:03:37.740195 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11382 10:03:37.751663 /lava-10670658/1/../bin/lava-test-case
11383 10:03:37.758615 <8>[ 29.525630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11384 10:03:37.759452 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11386 10:03:37.770212 /lava-10670658/1/../bin/lava-test-case
11387 10:03:37.776668 <8>[ 29.544053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11388 10:03:37.777356 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11390 10:03:37.785897 /lava-10670658/1/../bin/lava-test-case
11391 10:03:37.792498 <8>[ 29.560347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11392 10:03:37.793326 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11394 10:03:37.805397 /lava-10670658/1/../bin/lava-test-case
11395 10:03:37.811993 <8>[ 29.579251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11396 10:03:37.812798 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11398 10:03:37.821749 /lava-10670658/1/../bin/lava-test-case
11399 10:03:37.827853 <8>[ 29.595519] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11400 10:03:37.828541 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11402 10:03:37.839922 /lava-10670658/1/../bin/lava-test-case
11403 10:03:37.846276 <8>[ 29.613699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11404 10:03:37.846968 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11406 10:03:37.856229 /lava-10670658/1/../bin/lava-test-case
11407 10:03:37.862164 <8>[ 29.629417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11408 10:03:37.863063 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11410 10:03:37.874644 /lava-10670658/1/../bin/lava-test-case
11411 10:03:37.881593 <8>[ 29.648387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11412 10:03:37.882383 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11414 10:03:37.890675 /lava-10670658/1/../bin/lava-test-case
11415 10:03:37.897288 <8>[ 29.664224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11416 10:03:37.898108 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11418 10:03:37.909882 /lava-10670658/1/../bin/lava-test-case
11419 10:03:37.916782 <8>[ 29.683602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11420 10:03:37.917589 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11422 10:03:37.925979 /lava-10670658/1/../bin/lava-test-case
11423 10:03:37.932280 <8>[ 29.699562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11424 10:03:37.933168 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11426 10:03:37.944065 /lava-10670658/1/../bin/lava-test-case
11427 10:03:37.950478 <8>[ 29.717927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11428 10:03:37.951292 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11430 10:03:37.959639 /lava-10670658/1/../bin/lava-test-case
11431 10:03:37.966043 <8>[ 29.733610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11432 10:03:37.966866 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11434 10:03:38.980257 /lava-10670658/1/../bin/lava-test-case
11435 10:03:38.986265 <8>[ 30.755047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11436 10:03:38.987066 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11438 10:03:40.000967 /lava-10670658/1/../bin/lava-test-case
11439 10:03:40.007358 <8>[ 31.776341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11440 10:03:40.007664 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11442 10:03:40.017976 /lava-10670658/1/../bin/lava-test-case
11443 10:03:40.025421 <8>[ 31.792608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11444 10:03:40.026224 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11446 10:03:40.036148 /lava-10670658/1/../bin/lava-test-case
11447 10:03:40.043304 <8>[ 31.810349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11448 10:03:40.044135 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11450 10:03:40.052018 /lava-10670658/1/../bin/lava-test-case
11451 10:03:40.059126 <8>[ 31.826275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11452 10:03:40.059979 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11454 10:03:40.070211 /lava-10670658/1/../bin/lava-test-case
11455 10:03:40.076897 <8>[ 31.844666] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11456 10:03:40.077753 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11458 10:03:40.086166 /lava-10670658/1/../bin/lava-test-case
11459 10:03:40.093198 <8>[ 31.860487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11460 10:03:40.094075 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11462 10:03:40.103994 /lava-10670658/1/../bin/lava-test-case
11463 10:03:40.110817 <8>[ 31.878466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11464 10:03:40.111650 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11466 10:03:40.119707 /lava-10670658/1/../bin/lava-test-case
11467 10:03:40.126294 <8>[ 31.894041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11468 10:03:40.127080 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11470 10:03:40.137402 /lava-10670658/1/../bin/lava-test-case
11471 10:03:40.143776 <8>[ 31.912267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11472 10:03:40.144566 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11474 10:03:40.153925 /lava-10670658/1/../bin/lava-test-case
11475 10:03:40.160268 <8>[ 31.928025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11476 10:03:40.161052 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11478 10:03:40.172286 /lava-10670658/1/../bin/lava-test-case
11479 10:03:40.178881 <8>[ 31.946830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11480 10:03:40.179558 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11482 10:03:40.188410 /lava-10670658/1/../bin/lava-test-case
11483 10:03:40.194647 <8>[ 31.962432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11484 10:03:40.195331 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11486 10:03:40.207199 /lava-10670658/1/../bin/lava-test-case
11487 10:03:40.213198 <8>[ 31.981657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11488 10:03:40.213892 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11490 10:03:40.223190 /lava-10670658/1/../bin/lava-test-case
11491 10:03:40.229177 <8>[ 31.997167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11492 10:03:40.229865 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11494 10:03:40.240321 /lava-10670658/1/../bin/lava-test-case
11495 10:03:40.246815 <8>[ 32.015368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11496 10:03:40.247585 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11498 10:03:40.256490 /lava-10670658/1/../bin/lava-test-case
11499 10:03:40.263163 <8>[ 32.030873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11500 10:03:40.263993 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11502 10:03:40.275290 /lava-10670658/1/../bin/lava-test-case
11503 10:03:40.281133 <8>[ 32.049144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11504 10:03:40.281929 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11506 10:03:40.290824 /lava-10670658/1/../bin/lava-test-case
11507 10:03:40.296606 <8>[ 32.064485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11508 10:03:40.297294 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11510 10:03:40.308300 /lava-10670658/1/../bin/lava-test-case
11511 10:03:40.314557 <8>[ 32.082594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11512 10:03:40.315321 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11514 10:03:40.323754 /lava-10670658/1/../bin/lava-test-case
11515 10:03:40.330190 <8>[ 32.098478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11516 10:03:40.330983 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11518 10:03:40.343327 /lava-10670658/1/../bin/lava-test-case
11519 10:03:40.349728 <8>[ 32.117428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11520 10:03:40.350547 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11522 10:03:41.360899 /lava-10670658/1/../bin/lava-test-case
11523 10:03:41.367988 <8>[ 33.136940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11524 10:03:41.368704 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11526 10:03:42.381634 /lava-10670658/1/../bin/lava-test-case
11527 10:03:42.387697 <8>[ 34.157184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11528 10:03:42.388594 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11529 10:03:42.389068 Bad test result: blocked
11530 10:03:42.398376 /lava-10670658/1/../bin/lava-test-case
11531 10:03:42.404993 <8>[ 34.173179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11532 10:03:42.405786 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11534 10:03:43.418609 /lava-10670658/1/../bin/lava-test-case
11535 10:03:43.426277 <8>[ 35.194945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11536 10:03:43.427081 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11538 10:03:43.435326 /lava-10670658/1/../bin/lava-test-case
11539 10:03:43.442185 <8>[ 35.210324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11540 10:03:43.442979 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11542 10:03:43.454306 /lava-10670658/1/../bin/lava-test-case
11543 10:03:43.460597 <8>[ 35.228959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11544 10:03:43.461413 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11546 10:03:43.471699 /lava-10670658/1/../bin/lava-test-case
11547 10:03:43.478152 <8>[ 35.246365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11548 10:03:43.478942 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11550 10:03:43.486687 /lava-10670658/1/../bin/lava-test-case
11551 10:03:43.493872 <8>[ 35.262180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11552 10:03:43.494924 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11554 10:03:43.505483 /lava-10670658/1/../bin/lava-test-case
11555 10:03:43.511594 <8>[ 35.280277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11556 10:03:43.512373 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11558 10:03:43.521319 /lava-10670658/1/../bin/lava-test-case
11559 10:03:43.527756 <8>[ 35.296326] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11560 10:03:43.528559 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11562 10:03:44.541188 /lava-10670658/1/../bin/lava-test-case
11563 10:03:44.547700 <8>[ 36.316608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11564 10:03:44.548517 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11566 10:03:44.557834 /lava-10670658/1/../bin/lava-test-case
11567 10:03:44.564006 <8>[ 36.332169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11568 10:03:44.564822 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11570 10:03:45.577652 /lava-10670658/1/../bin/lava-test-case
11571 10:03:45.584118 <8>[ 37.352999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11572 10:03:45.584796 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11574 10:03:45.593708 /lava-10670658/1/../bin/lava-test-case
11575 10:03:45.600092 <8>[ 37.368961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11576 10:03:45.600895 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11578 10:03:46.613749 /lava-10670658/1/../bin/lava-test-case
11579 10:03:46.620367 <8>[ 38.390445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11580 10:03:46.621189 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11582 10:03:46.630575 /lava-10670658/1/../bin/lava-test-case
11583 10:03:46.637085 <8>[ 38.406406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11584 10:03:46.637808 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11586 10:03:47.652166 /lava-10670658/1/../bin/lava-test-case
11587 10:03:47.658502 <8>[ 39.427834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11588 10:03:47.659318 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11590 10:03:47.668507 /lava-10670658/1/../bin/lava-test-case
11591 10:03:47.675400 <8>[ 39.443872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11592 10:03:47.676229 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11594 10:03:47.686811 /lava-10670658/1/../bin/lava-test-case
11595 10:03:47.693086 <8>[ 39.461619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11596 10:03:47.693887 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11598 10:03:47.704022 /lava-10670658/1/../bin/lava-test-case
11599 10:03:47.710646 <8>[ 39.479455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11600 10:03:47.711468 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11602 10:03:47.719338 /lava-10670658/1/../bin/lava-test-case
11603 10:03:47.726381 <8>[ 39.495060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11604 10:03:47.727185 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11606 10:03:47.738223 /lava-10670658/1/../bin/lava-test-case
11607 10:03:47.744892 <8>[ 39.513363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11608 10:03:47.745694 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11610 10:03:47.753656 /lava-10670658/1/../bin/lava-test-case
11611 10:03:47.759752 <8>[ 39.528793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11612 10:03:47.760479 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11614 10:03:47.772602 /lava-10670658/1/../bin/lava-test-case
11615 10:03:47.779196 <8>[ 39.547883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11616 10:03:47.780072 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11618 10:03:47.788764 /lava-10670658/1/../bin/lava-test-case
11619 10:03:47.795027 <8>[ 39.563602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11620 10:03:47.795898 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11622 10:03:48.809926 /lava-10670658/1/../bin/lava-test-case
11623 10:03:48.816259 <8>[ 40.585915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11624 10:03:48.817097 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11626 10:03:48.820620 + set +x
11627 10:03:48.824054 Received signal: <ENDRUN> 1_bootrr 10670658_1.5.2.3.5
11628 10:03:48.824671 Ending use of test pattern.
11629 10:03:48.825026 Ending test lava.1_bootrr (10670658_1.5.2.3.5), duration 23.28
11631 10:03:48.826820 <8>[ 40.596049] <LAVA_SIGNAL_ENDRUN 1_bootrr 10670658_1.5.2.3.5>
11632 10:03:48.827254 <LAVA_TEST_RUNNER EXIT>
11633 10:03:48.827886 ok: lava_test_shell seems to have completed
11634 10:03:48.830403 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11635 10:03:48.830544 end: 4.1 lava-test-shell (duration 00:00:24) [common]
11636 10:03:48.830630 end: 4 lava-test-retry (duration 00:00:24) [common]
11637 10:03:48.830716 start: 5 finalize (timeout 00:07:35) [common]
11638 10:03:48.830802 start: 5.1 power-off (timeout 00:00:30) [common]
11639 10:03:48.830953 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11640 10:03:48.909286 >> Command sent successfully.
11641 10:03:48.914183 Returned 0 in 0 seconds
11642 10:03:49.014913 end: 5.1 power-off (duration 00:00:00) [common]
11644 10:03:49.015809 start: 5.2 read-feedback (timeout 00:07:35) [common]
11645 10:03:49.016422 Listened to connection for namespace 'common' for up to 1s
11646 10:03:49.016906 Listened to connection for namespace 'common' for up to 1s
11647 10:03:50.017372 Finalising connection for namespace 'common'
11648 10:03:50.018008 Disconnecting from shell: Finalise
11649 10:03:50.018394 / #
11650 10:03:50.119295 end: 5.2 read-feedback (duration 00:00:01) [common]
11651 10:03:50.119943 end: 5 finalize (duration 00:00:01) [common]
11652 10:03:50.120529 Cleaning after the job
11653 10:03:50.121059 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670658/tftp-deploy-87q2arux/ramdisk
11654 10:03:50.131873 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670658/tftp-deploy-87q2arux/kernel
11655 10:03:50.154973 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670658/tftp-deploy-87q2arux/dtb
11656 10:03:50.155436 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670658/tftp-deploy-87q2arux/modules
11657 10:03:50.166136 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10670658
11658 10:03:50.208203 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10670658
11659 10:03:50.208381 Job finished correctly