Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 43
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 34
- Errors: 2
1 10:01:08.668486 lava-dispatcher, installed at version: 2023.05.1
2 10:01:08.668735 start: 0 validate
3 10:01:08.668866 Start time: 2023-06-10 10:01:08.668859+00:00 (UTC)
4 10:01:08.668988 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:01:08.669114 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 10:01:08.938915 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:01:08.939705 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:01:23.217740 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:01:23.218483 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:01:23.481013 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:01:23.481735 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:01:24.003982 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:01:24.004836 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:01:27.017309 validate duration: 18.35
16 10:01:27.017563 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:01:27.017662 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:01:27.017746 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:01:27.017872 Not decompressing ramdisk as can be used compressed.
20 10:01:27.017955 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/initrd.cpio.gz
21 10:01:27.018018 saving as /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/ramdisk/initrd.cpio.gz
22 10:01:27.018076 total size: 4665395 (4MB)
23 10:01:27.275389 progress 0% (0MB)
24 10:01:27.276889 progress 5% (0MB)
25 10:01:27.278137 progress 10% (0MB)
26 10:01:27.279331 progress 15% (0MB)
27 10:01:27.280668 progress 20% (0MB)
28 10:01:27.281859 progress 25% (1MB)
29 10:01:27.283075 progress 30% (1MB)
30 10:01:27.284323 progress 35% (1MB)
31 10:01:27.285628 progress 40% (1MB)
32 10:01:27.287026 progress 45% (2MB)
33 10:01:27.288292 progress 50% (2MB)
34 10:01:27.289549 progress 55% (2MB)
35 10:01:27.290757 progress 60% (2MB)
36 10:01:27.291983 progress 65% (2MB)
37 10:01:27.293278 progress 70% (3MB)
38 10:01:27.294550 progress 75% (3MB)
39 10:01:27.295791 progress 80% (3MB)
40 10:01:27.297157 progress 85% (3MB)
41 10:01:27.298419 progress 90% (4MB)
42 10:01:27.299590 progress 95% (4MB)
43 10:01:27.300858 progress 100% (4MB)
44 10:01:27.301036 4MB downloaded in 0.28s (15.72MB/s)
45 10:01:27.301211 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:01:27.301494 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:01:27.301613 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:01:27.301739 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:01:27.301901 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:01:27.301973 saving as /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/kernel/Image
52 10:01:27.302034 total size: 45746688 (43MB)
53 10:01:27.302094 No compression specified
54 10:01:27.309809 progress 0% (0MB)
55 10:01:27.321126 progress 5% (2MB)
56 10:01:27.332554 progress 10% (4MB)
57 10:01:27.343914 progress 15% (6MB)
58 10:01:27.355360 progress 20% (8MB)
59 10:01:27.367008 progress 25% (10MB)
60 10:01:27.378571 progress 30% (13MB)
61 10:01:27.390232 progress 35% (15MB)
62 10:01:27.401999 progress 40% (17MB)
63 10:01:27.413706 progress 45% (19MB)
64 10:01:27.425322 progress 50% (21MB)
65 10:01:27.436645 progress 55% (24MB)
66 10:01:27.448138 progress 60% (26MB)
67 10:01:27.460015 progress 65% (28MB)
68 10:01:27.471598 progress 70% (30MB)
69 10:01:27.483204 progress 75% (32MB)
70 10:01:27.494652 progress 80% (34MB)
71 10:01:27.506225 progress 85% (37MB)
72 10:01:27.517882 progress 90% (39MB)
73 10:01:27.529322 progress 95% (41MB)
74 10:01:27.540606 progress 100% (43MB)
75 10:01:27.540761 43MB downloaded in 0.24s (182.75MB/s)
76 10:01:27.540914 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:01:27.541152 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:01:27.541240 start: 1.3 download-retry (timeout 00:09:59) [common]
80 10:01:27.541328 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 10:01:27.541463 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:01:27.541532 saving as /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/dtb/mt8192-asurada-spherion-r0.dtb
83 10:01:27.541594 total size: 46924 (0MB)
84 10:01:27.541653 No compression specified
85 10:01:27.542759 progress 69% (0MB)
86 10:01:27.543034 progress 100% (0MB)
87 10:01:27.543187 0MB downloaded in 0.00s (28.13MB/s)
88 10:01:27.543308 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:01:27.543529 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:01:27.543613 start: 1.4 download-retry (timeout 00:09:59) [common]
92 10:01:27.543695 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 10:01:27.543804 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/full.rootfs.tar.xz
94 10:01:27.543871 saving as /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/nfsrootfs/full.rootfs.tar
95 10:01:27.543932 total size: 125267308 (119MB)
96 10:01:27.543991 Using unxz to decompress xz
97 10:01:27.547565 progress 0% (0MB)
98 10:01:27.868151 progress 5% (6MB)
99 10:01:28.199532 progress 10% (11MB)
100 10:01:28.523357 progress 15% (17MB)
101 10:01:28.716066 progress 20% (23MB)
102 10:01:28.892110 progress 25% (29MB)
103 10:01:29.238370 progress 30% (35MB)
104 10:01:29.589128 progress 35% (41MB)
105 10:01:29.970312 progress 40% (47MB)
106 10:01:30.346568 progress 45% (53MB)
107 10:01:30.742855 progress 50% (59MB)
108 10:01:31.105806 progress 55% (65MB)
109 10:01:31.460485 progress 60% (71MB)
110 10:01:31.795472 progress 65% (77MB)
111 10:01:32.154277 progress 70% (83MB)
112 10:01:32.530047 progress 75% (89MB)
113 10:01:32.943132 progress 80% (95MB)
114 10:01:33.354366 progress 85% (101MB)
115 10:01:33.589533 progress 90% (107MB)
116 10:01:33.926933 progress 95% (113MB)
117 10:01:34.304799 progress 100% (119MB)
118 10:01:34.310989 119MB downloaded in 6.77s (17.65MB/s)
119 10:01:34.311409 end: 1.4.1 http-download (duration 00:00:07) [common]
121 10:01:34.311941 end: 1.4 download-retry (duration 00:00:07) [common]
122 10:01:34.312102 start: 1.5 download-retry (timeout 00:09:53) [common]
123 10:01:34.312260 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 10:01:34.312488 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:01:34.312621 saving as /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/modules/modules.tar
126 10:01:34.312746 total size: 8540248 (8MB)
127 10:01:34.312869 Using unxz to decompress xz
128 10:01:34.582673 progress 0% (0MB)
129 10:01:34.605212 progress 5% (0MB)
130 10:01:34.629226 progress 10% (0MB)
131 10:01:34.652378 progress 15% (1MB)
132 10:01:34.677112 progress 20% (1MB)
133 10:01:34.701294 progress 25% (2MB)
134 10:01:34.724118 progress 30% (2MB)
135 10:01:34.749490 progress 35% (2MB)
136 10:01:34.774226 progress 40% (3MB)
137 10:01:34.797970 progress 45% (3MB)
138 10:01:34.825426 progress 50% (4MB)
139 10:01:34.849964 progress 55% (4MB)
140 10:01:34.875489 progress 60% (4MB)
141 10:01:34.901082 progress 65% (5MB)
142 10:01:34.926134 progress 70% (5MB)
143 10:01:34.950047 progress 75% (6MB)
144 10:01:34.973269 progress 80% (6MB)
145 10:01:34.997202 progress 85% (6MB)
146 10:01:35.026356 progress 90% (7MB)
147 10:01:35.051578 progress 95% (7MB)
148 10:01:35.076519 progress 100% (8MB)
149 10:01:35.081802 8MB downloaded in 0.77s (10.59MB/s)
150 10:01:35.082088 end: 1.5.1 http-download (duration 00:00:01) [common]
152 10:01:35.082403 end: 1.5 download-retry (duration 00:00:01) [common]
153 10:01:35.082501 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 10:01:35.082592 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 10:01:37.095218 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10670640/extract-nfsrootfs-yyvetb3c
156 10:01:37.095429 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 10:01:37.095532 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 10:01:37.095698 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf
159 10:01:37.095827 makedir: /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin
160 10:01:37.095933 makedir: /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/tests
161 10:01:37.096032 makedir: /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/results
162 10:01:37.096138 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-add-keys
163 10:01:37.096279 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-add-sources
164 10:01:37.096407 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-background-process-start
165 10:01:37.096669 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-background-process-stop
166 10:01:37.096799 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-common-functions
167 10:01:37.096923 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-echo-ipv4
168 10:01:37.097046 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-install-packages
169 10:01:37.097168 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-installed-packages
170 10:01:37.097289 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-os-build
171 10:01:37.097412 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-probe-channel
172 10:01:37.097534 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-probe-ip
173 10:01:37.097655 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-target-ip
174 10:01:37.097778 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-target-mac
175 10:01:37.097899 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-target-storage
176 10:01:37.098026 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-test-case
177 10:01:37.098148 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-test-event
178 10:01:37.098268 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-test-feedback
179 10:01:37.098390 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-test-raise
180 10:01:37.098511 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-test-reference
181 10:01:37.098632 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-test-runner
182 10:01:37.098754 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-test-set
183 10:01:37.098876 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-test-shell
184 10:01:37.098999 Updating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-install-packages (oe)
185 10:01:37.099149 Updating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/bin/lava-installed-packages (oe)
186 10:01:37.099271 Creating /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/environment
187 10:01:37.099366 LAVA metadata
188 10:01:37.099437 - LAVA_JOB_ID=10670640
189 10:01:37.099501 - LAVA_DISPATCHER_IP=192.168.201.1
190 10:01:37.099602 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 10:01:37.099669 skipped lava-vland-overlay
192 10:01:37.099745 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 10:01:37.099825 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 10:01:37.099887 skipped lava-multinode-overlay
195 10:01:37.099961 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 10:01:37.100041 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 10:01:37.100115 Loading test definitions
198 10:01:37.100208 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 10:01:37.100280 Using /lava-10670640 at stage 0
200 10:01:37.100602 uuid=10670640_1.6.2.3.1 testdef=None
201 10:01:37.100693 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 10:01:37.100780 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 10:01:37.101275 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 10:01:37.101497 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 10:01:37.102124 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 10:01:37.102358 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 10:01:37.102963 runner path: /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/0/tests/0_dmesg test_uuid 10670640_1.6.2.3.1
210 10:01:37.103116 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 10:01:37.103349 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 10:01:37.103423 Using /lava-10670640 at stage 1
214 10:01:37.103718 uuid=10670640_1.6.2.3.5 testdef=None
215 10:01:37.103807 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 10:01:37.103894 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 10:01:37.104347 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 10:01:37.104609 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 10:01:37.105330 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 10:01:37.105563 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 10:01:37.106179 runner path: /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/1/tests/1_bootrr test_uuid 10670640_1.6.2.3.5
224 10:01:37.106330 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 10:01:37.106537 Creating lava-test-runner.conf files
227 10:01:37.106601 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/0 for stage 0
228 10:01:37.106693 - 0_dmesg
229 10:01:37.106773 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10670640/lava-overlay-p_ey41pf/lava-10670640/1 for stage 1
230 10:01:37.106864 - 1_bootrr
231 10:01:37.106959 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 10:01:37.107046 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 10:01:37.114597 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 10:01:37.114758 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 10:01:37.114852 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 10:01:37.114941 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 10:01:37.115028 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 10:01:37.230334 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 10:01:37.230713 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 10:01:37.230834 extracting modules file /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670640/extract-nfsrootfs-yyvetb3c
241 10:01:37.441151 extracting modules file /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670640/extract-overlay-ramdisk-7bimvraw/ramdisk
242 10:01:37.652152 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 10:01:37.652333 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 10:01:37.652426 [common] Applying overlay to NFS
245 10:01:37.652500 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670640/compress-overlay-40ms1rju/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10670640/extract-nfsrootfs-yyvetb3c
246 10:01:37.660327 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 10:01:37.660503 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 10:01:37.660642 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 10:01:37.660734 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 10:01:37.660821 Building ramdisk /var/lib/lava/dispatcher/tmp/10670640/extract-overlay-ramdisk-7bimvraw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10670640/extract-overlay-ramdisk-7bimvraw/ramdisk
251 10:01:37.961870 >> 117806 blocks
252 10:01:39.855581 rename /var/lib/lava/dispatcher/tmp/10670640/extract-overlay-ramdisk-7bimvraw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/ramdisk/ramdisk.cpio.gz
253 10:01:39.856016 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 10:01:39.856147 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 10:01:39.856287 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 10:01:39.856427 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/kernel/Image'
257 10:01:52.099304 Returned 0 in 12 seconds
258 10:01:52.199940 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/kernel/image.itb
259 10:01:52.529313 output: FIT description: Kernel Image image with one or more FDT blobs
260 10:01:52.529677 output: Created: Sat Jun 10 11:01:52 2023
261 10:01:52.529752 output: Image 0 (kernel-1)
262 10:01:52.529819 output: Description:
263 10:01:52.529883 output: Created: Sat Jun 10 11:01:52 2023
264 10:01:52.529941 output: Type: Kernel Image
265 10:01:52.530003 output: Compression: lzma compressed
266 10:01:52.530061 output: Data Size: 10087317 Bytes = 9850.90 KiB = 9.62 MiB
267 10:01:52.530122 output: Architecture: AArch64
268 10:01:52.530180 output: OS: Linux
269 10:01:52.530235 output: Load Address: 0x00000000
270 10:01:52.530290 output: Entry Point: 0x00000000
271 10:01:52.530347 output: Hash algo: crc32
272 10:01:52.530402 output: Hash value: c9e456fd
273 10:01:52.530455 output: Image 1 (fdt-1)
274 10:01:52.530508 output: Description: mt8192-asurada-spherion-r0
275 10:01:52.530561 output: Created: Sat Jun 10 11:01:52 2023
276 10:01:52.530614 output: Type: Flat Device Tree
277 10:01:52.530667 output: Compression: uncompressed
278 10:01:52.530719 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
279 10:01:52.530772 output: Architecture: AArch64
280 10:01:52.530825 output: Hash algo: crc32
281 10:01:52.530877 output: Hash value: 1df858fa
282 10:01:52.530929 output: Image 2 (ramdisk-1)
283 10:01:52.530980 output: Description: unavailable
284 10:01:52.531032 output: Created: Sat Jun 10 11:01:52 2023
285 10:01:52.531085 output: Type: RAMDisk Image
286 10:01:52.531137 output: Compression: Unknown Compression
287 10:01:52.531189 output: Data Size: 17647103 Bytes = 17233.50 KiB = 16.83 MiB
288 10:01:52.531242 output: Architecture: AArch64
289 10:01:52.531295 output: OS: Linux
290 10:01:52.531347 output: Load Address: unavailable
291 10:01:52.531399 output: Entry Point: unavailable
292 10:01:52.531452 output: Hash algo: crc32
293 10:01:52.531504 output: Hash value: a79dc1d5
294 10:01:52.531556 output: Default Configuration: 'conf-1'
295 10:01:52.531608 output: Configuration 0 (conf-1)
296 10:01:52.531660 output: Description: mt8192-asurada-spherion-r0
297 10:01:52.531712 output: Kernel: kernel-1
298 10:01:52.531764 output: Init Ramdisk: ramdisk-1
299 10:01:52.531816 output: FDT: fdt-1
300 10:01:52.531868 output: Loadables: kernel-1
301 10:01:52.531920 output:
302 10:01:52.532118 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 10:01:52.532218 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 10:01:52.532320 end: 1.6 prepare-tftp-overlay (duration 00:00:17) [common]
305 10:01:52.532411 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
306 10:01:52.532490 No LXC device requested
307 10:01:52.532609 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 10:01:52.532694 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
309 10:01:52.532772 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 10:01:52.532839 Checking files for TFTP limit of 4294967296 bytes.
311 10:01:52.533345 end: 1 tftp-deploy (duration 00:00:26) [common]
312 10:01:52.533446 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 10:01:52.533536 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 10:01:52.533659 substitutions:
315 10:01:52.533726 - {DTB}: 10670640/tftp-deploy-knu8rojz/dtb/mt8192-asurada-spherion-r0.dtb
316 10:01:52.533790 - {INITRD}: 10670640/tftp-deploy-knu8rojz/ramdisk/ramdisk.cpio.gz
317 10:01:52.533849 - {KERNEL}: 10670640/tftp-deploy-knu8rojz/kernel/Image
318 10:01:52.533906 - {LAVA_MAC}: None
319 10:01:52.533961 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10670640/extract-nfsrootfs-yyvetb3c
320 10:01:52.534017 - {NFS_SERVER_IP}: 192.168.201.1
321 10:01:52.534071 - {PRESEED_CONFIG}: None
322 10:01:52.534125 - {PRESEED_LOCAL}: None
323 10:01:52.534179 - {RAMDISK}: 10670640/tftp-deploy-knu8rojz/ramdisk/ramdisk.cpio.gz
324 10:01:52.534233 - {ROOT_PART}: None
325 10:01:52.534286 - {ROOT}: None
326 10:01:52.534340 - {SERVER_IP}: 192.168.201.1
327 10:01:52.534393 - {TEE}: None
328 10:01:52.534448 Parsed boot commands:
329 10:01:52.534501 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 10:01:52.534675 Parsed boot commands: tftpboot 192.168.201.1 10670640/tftp-deploy-knu8rojz/kernel/image.itb 10670640/tftp-deploy-knu8rojz/kernel/cmdline
331 10:01:52.534764 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 10:01:52.534848 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 10:01:52.534954 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 10:01:52.535039 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 10:01:52.535110 Not connected, no need to disconnect.
336 10:01:52.535184 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 10:01:52.535263 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 10:01:52.535328 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
339 10:01:52.538749 Setting prompt string to ['lava-test: # ']
340 10:01:52.539084 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 10:01:52.539192 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 10:01:52.539288 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 10:01:52.539381 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 10:01:52.539579 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
345 10:01:57.668447 >> Command sent successfully.
346 10:01:57.674046 Returned 0 in 5 seconds
347 10:01:57.774987 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 10:01:57.776173 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 10:01:57.776652 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 10:01:57.777045 Setting prompt string to 'Starting depthcharge on Spherion...'
352 10:01:57.777344 Changing prompt to 'Starting depthcharge on Spherion...'
353 10:01:57.777635 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 10:01:57.778622 [Enter `^Ec?' for help]
355 10:01:57.946806
356 10:01:57.947336
357 10:01:57.947752 F0: 102B 0000
358 10:01:57.948253
359 10:01:57.948773 F3: 1001 0000 [0200]
360 10:01:57.949154
361 10:01:57.950671 F3: 1001 0000
362 10:01:57.951284
363 10:01:57.951783 F7: 102D 0000
364 10:01:57.952258
365 10:01:57.952747 F1: 0000 0000
366 10:01:57.954267
367 10:01:57.954713 V0: 0000 0000 [0001]
368 10:01:57.955064
369 10:01:57.955418 00: 0007 8000
370 10:01:57.955839
371 10:01:57.957584 01: 0000 0000
372 10:01:57.958026
373 10:01:57.958366 BP: 0C00 0209 [0000]
374 10:01:57.958686
375 10:01:57.960718 G0: 1182 0000
376 10:01:57.961158
377 10:01:57.961546 EC: 0000 0021 [4000]
378 10:01:57.961863
379 10:01:57.963934 S7: 0000 0000 [0000]
380 10:01:57.964414
381 10:01:57.964837 CC: 0000 0000 [0001]
382 10:01:57.965161
383 10:01:57.967473 T0: 0000 0040 [010F]
384 10:01:57.968086
385 10:01:57.968452 Jump to BL
386 10:01:57.968888
387 10:01:57.993505
388 10:01:57.993954
389 10:01:57.994304
390 10:01:58.001067 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 10:01:58.004195 ARM64: Exception handlers installed.
392 10:01:58.007653 ARM64: Testing exception
393 10:01:58.011259 ARM64: Done test exception
394 10:01:58.018252 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 10:01:58.029582 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 10:01:58.036093 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 10:01:58.043969 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 10:01:58.050362 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 10:01:58.060614 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 10:01:58.070696 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 10:01:58.076931 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 10:01:58.095952 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 10:01:58.099350 WDT: Last reset was cold boot
404 10:01:58.102857 SPI1(PAD0) initialized at 2873684 Hz
405 10:01:58.106225 SPI5(PAD0) initialized at 992727 Hz
406 10:01:58.109482 VBOOT: Loading verstage.
407 10:01:58.116035 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 10:01:58.119239 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 10:01:58.123356 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 10:01:58.125888 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 10:01:58.133638 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 10:01:58.139930 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 10:01:58.151153 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 10:01:58.151803
415 10:01:58.152297
416 10:01:58.160864 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 10:01:58.164686 ARM64: Exception handlers installed.
418 10:01:58.167575 ARM64: Testing exception
419 10:01:58.168075 ARM64: Done test exception
420 10:01:58.174550 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 10:01:58.178358 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 10:01:58.192085 Probing TPM: . done!
423 10:01:58.192710 TPM ready after 0 ms
424 10:01:58.199091 Connected to device vid:did:rid of 1ae0:0028:00
425 10:01:58.205626 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
426 10:01:58.247516 Initialized TPM device CR50 revision 0
427 10:01:58.259381 tlcl_send_startup: Startup return code is 0
428 10:01:58.260003 TPM: setup succeeded
429 10:01:58.271659 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 10:01:58.280266 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 10:01:58.287069 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 10:01:58.300868 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 10:01:58.304071 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 10:01:58.307172 in-header: 03 07 00 00 08 00 00 00
435 10:01:58.310055 in-data: aa e4 47 04 13 02 00 00
436 10:01:58.313757 Chrome EC: UHEPI supported
437 10:01:58.320414 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 10:01:58.323704 in-header: 03 ad 00 00 08 00 00 00
439 10:01:58.327276 in-data: 00 20 20 08 00 00 00 00
440 10:01:58.327868 Phase 1
441 10:01:58.330477 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 10:01:58.336810 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 10:01:58.343216 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 10:01:58.346557 Recovery requested (1009000e)
445 10:01:58.351158 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 10:01:58.359218 tlcl_extend: response is 0
447 10:01:58.367357 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 10:01:58.372395 tlcl_extend: response is 0
449 10:01:58.379157 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 10:01:58.399848 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 10:01:58.406844 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 10:01:58.407557
453 10:01:58.407968
454 10:01:58.417191 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 10:01:58.420600 ARM64: Exception handlers installed.
456 10:01:58.421181 ARM64: Testing exception
457 10:01:58.424282 ARM64: Done test exception
458 10:01:58.445307 pmic_efuse_setting: Set efuses in 11 msecs
459 10:01:58.448875 pmwrap_interface_init: Select PMIF_VLD_RDY
460 10:01:58.452616 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 10:01:58.459546 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 10:01:58.462644 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 10:01:58.469715 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 10:01:58.473108 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 10:01:58.479388 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 10:01:58.482820 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 10:01:58.489344 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 10:01:58.493016 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 10:01:58.496107 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 10:01:58.502791 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 10:01:58.506096 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 10:01:58.512257 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 10:01:58.519076 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 10:01:58.522644 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 10:01:58.528952 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 10:01:58.535756 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 10:01:58.539238 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 10:01:58.545689 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 10:01:58.552742 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 10:01:58.555583 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 10:01:58.562861 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 10:01:58.570094 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 10:01:58.573638 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 10:01:58.576842 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 10:01:58.583684 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 10:01:58.590828 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 10:01:58.594111 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 10:01:58.598059 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 10:01:58.605132 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 10:01:58.608484 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 10:01:58.614669 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 10:01:58.618283 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 10:01:58.624633 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 10:01:58.628114 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 10:01:58.635010 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 10:01:58.638184 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 10:01:58.645423 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 10:01:58.648854 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 10:01:58.652878 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 10:01:58.656575 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 10:01:58.663494 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 10:01:58.666656 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 10:01:58.669930 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 10:01:58.673344 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 10:01:58.679736 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 10:01:58.683615 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 10:01:58.686492 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 10:01:58.693331 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 10:01:58.696979 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 10:01:58.699992 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 10:01:58.709428 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 10:01:58.716232 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 10:01:58.719826 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 10:01:58.729947 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 10:01:58.736576 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 10:01:58.742662 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 10:01:58.746788 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 10:01:58.749571 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 10:01:58.757501 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x13
520 10:01:58.764551 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 10:01:58.767443 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
522 10:01:58.774404 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 10:01:58.782714 [RTC]rtc_get_frequency_meter,154: input=15, output=836
524 10:01:58.791834 [RTC]rtc_get_frequency_meter,154: input=7, output=709
525 10:01:58.801179 [RTC]rtc_get_frequency_meter,154: input=11, output=772
526 10:01:58.810612 [RTC]rtc_get_frequency_meter,154: input=13, output=803
527 10:01:58.820590 [RTC]rtc_get_frequency_meter,154: input=12, output=788
528 10:01:58.829495 [RTC]rtc_get_frequency_meter,154: input=12, output=788
529 10:01:58.839134 [RTC]rtc_get_frequency_meter,154: input=13, output=803
530 10:01:58.842524 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
531 10:01:58.850032 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
532 10:01:58.853842 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 10:01:58.856208 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 10:01:58.862780 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 10:01:58.866875 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 10:01:58.869932 ADC[4]: Raw value=903400 ID=7
537 10:01:58.870450 ADC[3]: Raw value=213652 ID=1
538 10:01:58.873102 RAM Code: 0x71
539 10:01:58.876422 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 10:01:58.883365 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 10:01:58.889662 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 10:01:58.896279 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 10:01:58.899591 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 10:01:58.903010 in-header: 03 07 00 00 08 00 00 00
545 10:01:58.906189 in-data: aa e4 47 04 13 02 00 00
546 10:01:58.909824 Chrome EC: UHEPI supported
547 10:01:58.916080 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 10:01:58.919467 in-header: 03 dd 00 00 08 00 00 00
549 10:01:58.922616 in-data: 90 20 60 08 00 00 00 00
550 10:01:58.926176 MRC: failed to locate region type 0.
551 10:01:58.932938 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 10:01:58.935947 DRAM-K: Running full calibration
553 10:01:58.942451 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 10:01:58.942950 header.status = 0x0
555 10:01:58.945603 header.version = 0x6 (expected: 0x6)
556 10:01:58.949538 header.size = 0xd00 (expected: 0xd00)
557 10:01:58.952856 header.flags = 0x0
558 10:01:58.959229 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 10:01:58.976318 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
560 10:01:58.982933 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 10:01:58.986419 dram_init: ddr_geometry: 2
562 10:01:58.990047 [EMI] MDL number = 2
563 10:01:58.990631 [EMI] Get MDL freq = 0
564 10:01:58.993363 dram_init: ddr_type: 0
565 10:01:58.993836 is_discrete_lpddr4: 1
566 10:01:58.996142 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 10:01:58.996653
568 10:01:58.997034
569 10:01:58.999881 [Bian_co] ETT version 0.0.0.1
570 10:01:59.006702 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 10:01:59.007296
572 10:01:59.009512 dramc_set_vcore_voltage set vcore to 650000
573 10:01:59.010026 Read voltage for 800, 4
574 10:01:59.012649 Vio18 = 0
575 10:01:59.013119 Vcore = 650000
576 10:01:59.013494 Vdram = 0
577 10:01:59.015993 Vddq = 0
578 10:01:59.016465 Vmddr = 0
579 10:01:59.019767 dram_init: config_dvfs: 1
580 10:01:59.023030 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 10:01:59.029335 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 10:01:59.033059 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
583 10:01:59.035980 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
584 10:01:59.039317 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
585 10:01:59.042731 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
586 10:01:59.045851 MEM_TYPE=3, freq_sel=18
587 10:01:59.049182 sv_algorithm_assistance_LP4_1600
588 10:01:59.053048 ============ PULL DRAM RESETB DOWN ============
589 10:01:59.056261 ========== PULL DRAM RESETB DOWN end =========
590 10:01:59.063178 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 10:01:59.066026 ===================================
592 10:01:59.069063 LPDDR4 DRAM CONFIGURATION
593 10:01:59.072384 ===================================
594 10:01:59.072970 EX_ROW_EN[0] = 0x0
595 10:01:59.076342 EX_ROW_EN[1] = 0x0
596 10:01:59.076853 LP4Y_EN = 0x0
597 10:01:59.079285 WORK_FSP = 0x0
598 10:01:59.079756 WL = 0x2
599 10:01:59.083623 RL = 0x2
600 10:01:59.084215 BL = 0x2
601 10:01:59.086008 RPST = 0x0
602 10:01:59.086480 RD_PRE = 0x0
603 10:01:59.089231 WR_PRE = 0x1
604 10:01:59.089706 WR_PST = 0x0
605 10:01:59.092732 DBI_WR = 0x0
606 10:01:59.093204 DBI_RD = 0x0
607 10:01:59.095917 OTF = 0x1
608 10:01:59.099649 ===================================
609 10:01:59.102258 ===================================
610 10:01:59.102735 ANA top config
611 10:01:59.106014 ===================================
612 10:01:59.109612 DLL_ASYNC_EN = 0
613 10:01:59.112607 ALL_SLAVE_EN = 1
614 10:01:59.116071 NEW_RANK_MODE = 1
615 10:01:59.116692 DLL_IDLE_MODE = 1
616 10:01:59.119449 LP45_APHY_COMB_EN = 1
617 10:01:59.122382 TX_ODT_DIS = 1
618 10:01:59.125618 NEW_8X_MODE = 1
619 10:01:59.128875 ===================================
620 10:01:59.132736 ===================================
621 10:01:59.135468 data_rate = 1600
622 10:01:59.138986 CKR = 1
623 10:01:59.139470 DQ_P2S_RATIO = 8
624 10:01:59.142489 ===================================
625 10:01:59.145615 CA_P2S_RATIO = 8
626 10:01:59.148980 DQ_CA_OPEN = 0
627 10:01:59.152244 DQ_SEMI_OPEN = 0
628 10:01:59.155654 CA_SEMI_OPEN = 0
629 10:01:59.158968 CA_FULL_RATE = 0
630 10:01:59.159548 DQ_CKDIV4_EN = 1
631 10:01:59.162414 CA_CKDIV4_EN = 1
632 10:01:59.165477 CA_PREDIV_EN = 0
633 10:01:59.168874 PH8_DLY = 0
634 10:01:59.172228 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 10:01:59.172737 DQ_AAMCK_DIV = 4
636 10:01:59.175727 CA_AAMCK_DIV = 4
637 10:01:59.179550 CA_ADMCK_DIV = 4
638 10:01:59.182277 DQ_TRACK_CA_EN = 0
639 10:01:59.185661 CA_PICK = 800
640 10:01:59.189117 CA_MCKIO = 800
641 10:01:59.192197 MCKIO_SEMI = 0
642 10:01:59.192717 PLL_FREQ = 3068
643 10:01:59.195522 DQ_UI_PI_RATIO = 32
644 10:01:59.199138 CA_UI_PI_RATIO = 0
645 10:01:59.202502 ===================================
646 10:01:59.205595 ===================================
647 10:01:59.209274 memory_type:LPDDR4
648 10:01:59.209855 GP_NUM : 10
649 10:01:59.212062 SRAM_EN : 1
650 10:01:59.215963 MD32_EN : 0
651 10:01:59.218696 ===================================
652 10:01:59.219283 [ANA_INIT] >>>>>>>>>>>>>>
653 10:01:59.222251 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 10:01:59.225475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 10:01:59.229152 ===================================
656 10:01:59.232830 data_rate = 1600,PCW = 0X7600
657 10:01:59.235851 ===================================
658 10:01:59.239130 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 10:01:59.245731 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 10:01:59.249050 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 10:01:59.255244 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 10:01:59.258695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 10:01:59.262423 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 10:01:59.262946 [ANA_INIT] flow start
665 10:01:59.265521 [ANA_INIT] PLL >>>>>>>>
666 10:01:59.269033 [ANA_INIT] PLL <<<<<<<<
667 10:01:59.272630 [ANA_INIT] MIDPI >>>>>>>>
668 10:01:59.273158 [ANA_INIT] MIDPI <<<<<<<<
669 10:01:59.275521 [ANA_INIT] DLL >>>>>>>>
670 10:01:59.275997 [ANA_INIT] flow end
671 10:01:59.282604 ============ LP4 DIFF to SE enter ============
672 10:01:59.286221 ============ LP4 DIFF to SE exit ============
673 10:01:59.289070 [ANA_INIT] <<<<<<<<<<<<<
674 10:01:59.292558 [Flow] Enable top DCM control >>>>>
675 10:01:59.295587 [Flow] Enable top DCM control <<<<<
676 10:01:59.298791 Enable DLL master slave shuffle
677 10:01:59.302387 ==============================================================
678 10:01:59.305498 Gating Mode config
679 10:01:59.309307 ==============================================================
680 10:01:59.311975 Config description:
681 10:01:59.321917 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 10:01:59.328492 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 10:01:59.331972 SELPH_MODE 0: By rank 1: By Phase
684 10:01:59.338828 ==============================================================
685 10:01:59.341915 GAT_TRACK_EN = 1
686 10:01:59.344963 RX_GATING_MODE = 2
687 10:01:59.348376 RX_GATING_TRACK_MODE = 2
688 10:01:59.351948 SELPH_MODE = 1
689 10:01:59.355087 PICG_EARLY_EN = 1
690 10:01:59.355639 VALID_LAT_VALUE = 1
691 10:01:59.361868 ==============================================================
692 10:01:59.365351 Enter into Gating configuration >>>>
693 10:01:59.368194 Exit from Gating configuration <<<<
694 10:01:59.371416 Enter into DVFS_PRE_config >>>>>
695 10:01:59.381625 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 10:01:59.385138 Exit from DVFS_PRE_config <<<<<
697 10:01:59.388309 Enter into PICG configuration >>>>
698 10:01:59.391789 Exit from PICG configuration <<<<
699 10:01:59.394812 [RX_INPUT] configuration >>>>>
700 10:01:59.398010 [RX_INPUT] configuration <<<<<
701 10:01:59.405156 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 10:01:59.409030 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 10:01:59.416048 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 10:01:59.419158 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 10:01:59.426563 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 10:01:59.433570 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 10:01:59.437599 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 10:01:59.441063 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 10:01:59.444403 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 10:01:59.448347 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 10:01:59.452005 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 10:01:59.459531 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 10:01:59.463201 ===================================
714 10:01:59.463633 LPDDR4 DRAM CONFIGURATION
715 10:01:59.466510 ===================================
716 10:01:59.469748 EX_ROW_EN[0] = 0x0
717 10:01:59.470223 EX_ROW_EN[1] = 0x0
718 10:01:59.472934 LP4Y_EN = 0x0
719 10:01:59.473364 WORK_FSP = 0x0
720 10:01:59.476876 WL = 0x2
721 10:01:59.477305 RL = 0x2
722 10:01:59.480328 BL = 0x2
723 10:01:59.480877 RPST = 0x0
724 10:01:59.484644 RD_PRE = 0x0
725 10:01:59.485109 WR_PRE = 0x1
726 10:01:59.488148 WR_PST = 0x0
727 10:01:59.488718 DBI_WR = 0x0
728 10:01:59.492611 DBI_RD = 0x0
729 10:01:59.493170 OTF = 0x1
730 10:01:59.495759 ===================================
731 10:01:59.499544 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 10:01:59.502834 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 10:01:59.506689 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 10:01:59.509963 ===================================
735 10:01:59.513614 LPDDR4 DRAM CONFIGURATION
736 10:01:59.517119 ===================================
737 10:01:59.517676 EX_ROW_EN[0] = 0x10
738 10:01:59.520670 EX_ROW_EN[1] = 0x0
739 10:01:59.521128 LP4Y_EN = 0x0
740 10:01:59.524571 WORK_FSP = 0x0
741 10:01:59.525164 WL = 0x2
742 10:01:59.528806 RL = 0x2
743 10:01:59.529351 BL = 0x2
744 10:01:59.531972 RPST = 0x0
745 10:01:59.532494 RD_PRE = 0x0
746 10:01:59.535389 WR_PRE = 0x1
747 10:01:59.535880 WR_PST = 0x0
748 10:01:59.539214 DBI_WR = 0x0
749 10:01:59.539759 DBI_RD = 0x0
750 10:01:59.542722 OTF = 0x1
751 10:01:59.543155 ===================================
752 10:01:59.550188 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 10:01:59.554711 nWR fixed to 40
754 10:01:59.558431 [ModeRegInit_LP4] CH0 RK0
755 10:01:59.558979 [ModeRegInit_LP4] CH0 RK1
756 10:01:59.561841 [ModeRegInit_LP4] CH1 RK0
757 10:01:59.565421 [ModeRegInit_LP4] CH1 RK1
758 10:01:59.565848 match AC timing 13
759 10:01:59.568617 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 10:01:59.572639 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 10:01:59.578975 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 10:01:59.582585 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 10:01:59.589457 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 10:01:59.590123 [EMI DOE] emi_dcm 0
765 10:01:59.592366 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 10:01:59.592952 ==
767 10:01:59.596059 Dram Type= 6, Freq= 0, CH_0, rank 0
768 10:01:59.602659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 10:01:59.603252 ==
770 10:01:59.605704 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 10:01:59.612631 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 10:01:59.622041 [CA 0] Center 37 (6~68) winsize 63
773 10:01:59.625576 [CA 1] Center 36 (6~67) winsize 62
774 10:01:59.628506 [CA 2] Center 34 (4~65) winsize 62
775 10:01:59.632166 [CA 3] Center 34 (4~65) winsize 62
776 10:01:59.635420 [CA 4] Center 33 (3~64) winsize 62
777 10:01:59.638621 [CA 5] Center 33 (3~64) winsize 62
778 10:01:59.639255
779 10:01:59.641992 [CmdBusTrainingLP45] Vref(ca) range 1: 32
780 10:01:59.642477
781 10:01:59.645445 [CATrainingPosCal] consider 1 rank data
782 10:01:59.648723 u2DelayCellTimex100 = 270/100 ps
783 10:01:59.651980 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
784 10:01:59.655148 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
785 10:01:59.662001 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
786 10:01:59.665335 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
787 10:01:59.668799 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
788 10:01:59.671916 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 10:01:59.672356
790 10:01:59.675326 CA PerBit enable=1, Macro0, CA PI delay=33
791 10:01:59.675903
792 10:01:59.678524 [CBTSetCACLKResult] CA Dly = 33
793 10:01:59.679103 CS Dly: 7 (0~38)
794 10:01:59.682116 ==
795 10:01:59.682705 Dram Type= 6, Freq= 0, CH_0, rank 1
796 10:01:59.688474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 10:01:59.689003 ==
798 10:01:59.691870 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 10:01:59.699038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 10:01:59.708864 [CA 0] Center 37 (6~68) winsize 63
801 10:01:59.712331 [CA 1] Center 37 (7~68) winsize 62
802 10:01:59.714826 [CA 2] Center 34 (4~65) winsize 62
803 10:01:59.717816 [CA 3] Center 34 (4~65) winsize 62
804 10:01:59.722208 [CA 4] Center 33 (3~64) winsize 62
805 10:01:59.724838 [CA 5] Center 33 (3~64) winsize 62
806 10:01:59.725318
807 10:01:59.728035 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 10:01:59.728512
809 10:01:59.731482 [CATrainingPosCal] consider 2 rank data
810 10:01:59.735196 u2DelayCellTimex100 = 270/100 ps
811 10:01:59.738290 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
812 10:01:59.741848 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
813 10:01:59.745338 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
814 10:01:59.752211 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
815 10:01:59.755720 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
816 10:01:59.758922 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 10:01:59.759400
818 10:01:59.762422 CA PerBit enable=1, Macro0, CA PI delay=33
819 10:01:59.762906
820 10:01:59.766848 [CBTSetCACLKResult] CA Dly = 33
821 10:01:59.767504 CS Dly: 7 (0~38)
822 10:01:59.768093
823 10:01:59.769673 ----->DramcWriteLeveling(PI) begin...
824 10:01:59.770283 ==
825 10:01:59.773302 Dram Type= 6, Freq= 0, CH_0, rank 0
826 10:01:59.777253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 10:01:59.777727 ==
828 10:01:59.780347 Write leveling (Byte 0): 36 => 36
829 10:01:59.783902 Write leveling (Byte 1): 29 => 29
830 10:01:59.787258 DramcWriteLeveling(PI) end<-----
831 10:01:59.787795
832 10:01:59.788132 ==
833 10:01:59.790480 Dram Type= 6, Freq= 0, CH_0, rank 0
834 10:01:59.793949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 10:01:59.794469 ==
836 10:01:59.796837 [Gating] SW mode calibration
837 10:01:59.803777 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 10:01:59.810345 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 10:01:59.813698 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 10:01:59.816747 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
841 10:01:59.823667 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
842 10:01:59.826664 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
843 10:01:59.830177 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 10:01:59.836620 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 10:01:59.840293 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 10:01:59.843547 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 10:01:59.850407 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 10:01:59.853921 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 10:01:59.856578 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 10:01:59.862622 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 10:01:59.865928 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 10:01:59.869264 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 10:01:59.876043 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 10:01:59.879122 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 10:01:59.882622 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 10:01:59.889474 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
857 10:01:59.892723 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
858 10:01:59.895961 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 10:01:59.902345 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:01:59.906193 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:01:59.909228 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 10:01:59.915891 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 10:01:59.919576 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 10:01:59.922885 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 10:01:59.929339 0 9 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
866 10:01:59.932836 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
867 10:01:59.935807 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 10:01:59.942673 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 10:01:59.945594 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 10:01:59.949043 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 10:01:59.955496 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 10:01:59.958950 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
873 10:01:59.963301 0 10 8 | B1->B0 | 3232 2727 | 1 0 | (1 0) (1 0)
874 10:01:59.965586 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
875 10:01:59.972501 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 10:01:59.975965 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 10:01:59.979353 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 10:01:59.986001 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 10:01:59.989280 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 10:01:59.992839 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
881 10:01:59.999257 0 11 8 | B1->B0 | 2525 3a3a | 0 0 | (0 0) (0 0)
882 10:02:00.002518 0 11 12 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
883 10:02:00.005698 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 10:02:00.012199 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 10:02:00.015500 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 10:02:00.019069 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 10:02:00.025671 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 10:02:00.029264 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 10:02:00.032589 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
890 10:02:00.038863 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
891 10:02:00.042409 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 10:02:00.046087 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 10:02:00.052413 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 10:02:00.056172 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 10:02:00.059201 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 10:02:00.066158 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 10:02:00.069319 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 10:02:00.072682 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 10:02:00.079160 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 10:02:00.082398 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 10:02:00.086360 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 10:02:00.088838 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 10:02:00.095725 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 10:02:00.098980 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 10:02:00.102594 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
906 10:02:00.108905 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
907 10:02:00.112848 Total UI for P1: 0, mck2ui 16
908 10:02:00.115938 best dqsien dly found for B0: ( 0, 14, 8)
909 10:02:00.116606 Total UI for P1: 0, mck2ui 16
910 10:02:00.122969 best dqsien dly found for B1: ( 0, 14, 10)
911 10:02:00.126341 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
912 10:02:00.130538 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
913 10:02:00.131030
914 10:02:00.134472 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
915 10:02:00.137289 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
916 10:02:00.137744 [Gating] SW calibration Done
917 10:02:00.138220 ==
918 10:02:00.141268 Dram Type= 6, Freq= 0, CH_0, rank 0
919 10:02:00.144966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 10:02:00.145416 ==
921 10:02:00.148745 RX Vref Scan: 0
922 10:02:00.149293
923 10:02:00.152249 RX Vref 0 -> 0, step: 1
924 10:02:00.152829
925 10:02:00.153275 RX Delay -130 -> 252, step: 16
926 10:02:00.155812 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
927 10:02:00.163325 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
928 10:02:00.166729 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
929 10:02:00.170441 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
930 10:02:00.174204 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
931 10:02:00.177888 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
932 10:02:00.181730 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
933 10:02:00.185446 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
934 10:02:00.188446 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
935 10:02:00.192342 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
936 10:02:00.195275 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
937 10:02:00.201901 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
938 10:02:00.205235 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
939 10:02:00.208624 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
940 10:02:00.211986 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
941 10:02:00.218280 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
942 10:02:00.218718 ==
943 10:02:00.222042 Dram Type= 6, Freq= 0, CH_0, rank 0
944 10:02:00.225860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 10:02:00.226272 ==
946 10:02:00.226626 DQS Delay:
947 10:02:00.229524 DQS0 = 0, DQS1 = 0
948 10:02:00.229918 DQM Delay:
949 10:02:00.230243 DQM0 = 86, DQM1 = 77
950 10:02:00.232818 DQ Delay:
951 10:02:00.236476 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
952 10:02:00.239841 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
953 10:02:00.240278 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
954 10:02:00.243465 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
955 10:02:00.247255
956 10:02:00.247685
957 10:02:00.248024 ==
958 10:02:00.251056 Dram Type= 6, Freq= 0, CH_0, rank 0
959 10:02:00.253969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 10:02:00.254401 ==
961 10:02:00.254742
962 10:02:00.255056
963 10:02:00.255357 TX Vref Scan disable
964 10:02:00.257874 == TX Byte 0 ==
965 10:02:00.261319 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
966 10:02:00.267711 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
967 10:02:00.268143 == TX Byte 1 ==
968 10:02:00.271122 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
969 10:02:00.277641 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
970 10:02:00.278075 ==
971 10:02:00.280965 Dram Type= 6, Freq= 0, CH_0, rank 0
972 10:02:00.283939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 10:02:00.284369 ==
974 10:02:00.298012 TX Vref=22, minBit 4, minWin=27, winSum=438
975 10:02:00.301014 TX Vref=24, minBit 1, minWin=27, winSum=440
976 10:02:00.303906 TX Vref=26, minBit 6, minWin=27, winSum=445
977 10:02:00.307286 TX Vref=28, minBit 8, minWin=27, winSum=445
978 10:02:00.310566 TX Vref=30, minBit 4, minWin=27, winSum=442
979 10:02:00.317557 TX Vref=32, minBit 0, minWin=27, winSum=437
980 10:02:00.320624 [TxChooseVref] Worse bit 6, Min win 27, Win sum 445, Final Vref 26
981 10:02:00.321064
982 10:02:00.324104 Final TX Range 1 Vref 26
983 10:02:00.324567
984 10:02:00.324917 ==
985 10:02:00.327566 Dram Type= 6, Freq= 0, CH_0, rank 0
986 10:02:00.330712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 10:02:00.331151 ==
988 10:02:00.333854
989 10:02:00.334349
990 10:02:00.334700 TX Vref Scan disable
991 10:02:00.337446 == TX Byte 0 ==
992 10:02:00.340761 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
993 10:02:00.347319 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
994 10:02:00.347757 == TX Byte 1 ==
995 10:02:00.350703 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
996 10:02:00.357662 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
997 10:02:00.358103
998 10:02:00.358448 [DATLAT]
999 10:02:00.358769 Freq=800, CH0 RK0
1000 10:02:00.359080
1001 10:02:00.360757 DATLAT Default: 0xa
1002 10:02:00.361192 0, 0xFFFF, sum = 0
1003 10:02:00.364182 1, 0xFFFF, sum = 0
1004 10:02:00.367265 2, 0xFFFF, sum = 0
1005 10:02:00.367707 3, 0xFFFF, sum = 0
1006 10:02:00.370520 4, 0xFFFF, sum = 0
1007 10:02:00.370964 5, 0xFFFF, sum = 0
1008 10:02:00.374446 6, 0xFFFF, sum = 0
1009 10:02:00.374887 7, 0xFFFF, sum = 0
1010 10:02:00.377146 8, 0xFFFF, sum = 0
1011 10:02:00.377591 9, 0x0, sum = 1
1012 10:02:00.380168 10, 0x0, sum = 2
1013 10:02:00.380253 11, 0x0, sum = 3
1014 10:02:00.380320 12, 0x0, sum = 4
1015 10:02:00.383561 best_step = 10
1016 10:02:00.383645
1017 10:02:00.383711 ==
1018 10:02:00.386957 Dram Type= 6, Freq= 0, CH_0, rank 0
1019 10:02:00.390343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1020 10:02:00.390428 ==
1021 10:02:00.393279 RX Vref Scan: 1
1022 10:02:00.393364
1023 10:02:00.396575 Set Vref Range= 32 -> 127
1024 10:02:00.396659
1025 10:02:00.396730 RX Vref 32 -> 127, step: 1
1026 10:02:00.396792
1027 10:02:00.399866 RX Delay -95 -> 252, step: 8
1028 10:02:00.399949
1029 10:02:00.403561 Set Vref, RX VrefLevel [Byte0]: 32
1030 10:02:00.406475 [Byte1]: 32
1031 10:02:00.409901
1032 10:02:00.409984 Set Vref, RX VrefLevel [Byte0]: 33
1033 10:02:00.413555 [Byte1]: 33
1034 10:02:00.417563
1035 10:02:00.417646 Set Vref, RX VrefLevel [Byte0]: 34
1036 10:02:00.421057 [Byte1]: 34
1037 10:02:00.425155
1038 10:02:00.425239 Set Vref, RX VrefLevel [Byte0]: 35
1039 10:02:00.428457 [Byte1]: 35
1040 10:02:00.432858
1041 10:02:00.432941 Set Vref, RX VrefLevel [Byte0]: 36
1042 10:02:00.436192 [Byte1]: 36
1043 10:02:00.440470
1044 10:02:00.440619 Set Vref, RX VrefLevel [Byte0]: 37
1045 10:02:00.444057 [Byte1]: 37
1046 10:02:00.447773
1047 10:02:00.447857 Set Vref, RX VrefLevel [Byte0]: 38
1048 10:02:00.451515 [Byte1]: 38
1049 10:02:00.455333
1050 10:02:00.455424 Set Vref, RX VrefLevel [Byte0]: 39
1051 10:02:00.458971 [Byte1]: 39
1052 10:02:00.463370
1053 10:02:00.463453 Set Vref, RX VrefLevel [Byte0]: 40
1054 10:02:00.466204 [Byte1]: 40
1055 10:02:00.470542
1056 10:02:00.470628 Set Vref, RX VrefLevel [Byte0]: 41
1057 10:02:00.474026 [Byte1]: 41
1058 10:02:00.478570
1059 10:02:00.478655 Set Vref, RX VrefLevel [Byte0]: 42
1060 10:02:00.481654 [Byte1]: 42
1061 10:02:00.485634
1062 10:02:00.485717 Set Vref, RX VrefLevel [Byte0]: 43
1063 10:02:00.489108 [Byte1]: 43
1064 10:02:00.493596
1065 10:02:00.493678 Set Vref, RX VrefLevel [Byte0]: 44
1066 10:02:00.496665 [Byte1]: 44
1067 10:02:00.501301
1068 10:02:00.501384 Set Vref, RX VrefLevel [Byte0]: 45
1069 10:02:00.504271 [Byte1]: 45
1070 10:02:00.508417
1071 10:02:00.508499 Set Vref, RX VrefLevel [Byte0]: 46
1072 10:02:00.512207 [Byte1]: 46
1073 10:02:00.516428
1074 10:02:00.516510 Set Vref, RX VrefLevel [Byte0]: 47
1075 10:02:00.519667 [Byte1]: 47
1076 10:02:00.524347
1077 10:02:00.524460 Set Vref, RX VrefLevel [Byte0]: 48
1078 10:02:00.527632 [Byte1]: 48
1079 10:02:00.531902
1080 10:02:00.531986 Set Vref, RX VrefLevel [Byte0]: 49
1081 10:02:00.534733 [Byte1]: 49
1082 10:02:00.539094
1083 10:02:00.542544 Set Vref, RX VrefLevel [Byte0]: 50
1084 10:02:00.542621 [Byte1]: 50
1085 10:02:00.547202
1086 10:02:00.547300 Set Vref, RX VrefLevel [Byte0]: 51
1087 10:02:00.550197 [Byte1]: 51
1088 10:02:00.554531
1089 10:02:00.554641 Set Vref, RX VrefLevel [Byte0]: 52
1090 10:02:00.557845 [Byte1]: 52
1091 10:02:00.562377
1092 10:02:00.562452 Set Vref, RX VrefLevel [Byte0]: 53
1093 10:02:00.565673 [Byte1]: 53
1094 10:02:00.569625
1095 10:02:00.569696 Set Vref, RX VrefLevel [Byte0]: 54
1096 10:02:00.573175 [Byte1]: 54
1097 10:02:00.577861
1098 10:02:00.577932 Set Vref, RX VrefLevel [Byte0]: 55
1099 10:02:00.580504 [Byte1]: 55
1100 10:02:00.584610
1101 10:02:00.584682 Set Vref, RX VrefLevel [Byte0]: 56
1102 10:02:00.587956 [Byte1]: 56
1103 10:02:00.592405
1104 10:02:00.592504 Set Vref, RX VrefLevel [Byte0]: 57
1105 10:02:00.596102 [Byte1]: 57
1106 10:02:00.599712
1107 10:02:00.603444 Set Vref, RX VrefLevel [Byte0]: 58
1108 10:02:00.603549 [Byte1]: 58
1109 10:02:00.607751
1110 10:02:00.607859 Set Vref, RX VrefLevel [Byte0]: 59
1111 10:02:00.611647 [Byte1]: 59
1112 10:02:00.615320
1113 10:02:00.615404 Set Vref, RX VrefLevel [Byte0]: 60
1114 10:02:00.618335 [Byte1]: 60
1115 10:02:00.622181
1116 10:02:00.625831 Set Vref, RX VrefLevel [Byte0]: 61
1117 10:02:00.625910 [Byte1]: 61
1118 10:02:00.630101
1119 10:02:00.630200 Set Vref, RX VrefLevel [Byte0]: 62
1120 10:02:00.633341 [Byte1]: 62
1121 10:02:00.638112
1122 10:02:00.638193 Set Vref, RX VrefLevel [Byte0]: 63
1123 10:02:00.641525 [Byte1]: 63
1124 10:02:00.645514
1125 10:02:00.645591 Set Vref, RX VrefLevel [Byte0]: 64
1126 10:02:00.649473 [Byte1]: 64
1127 10:02:00.652837
1128 10:02:00.652950 Set Vref, RX VrefLevel [Byte0]: 65
1129 10:02:00.656691 [Byte1]: 65
1130 10:02:00.661117
1131 10:02:00.661199 Set Vref, RX VrefLevel [Byte0]: 66
1132 10:02:00.664910 [Byte1]: 66
1133 10:02:00.668556
1134 10:02:00.668639 Set Vref, RX VrefLevel [Byte0]: 67
1135 10:02:00.671574 [Byte1]: 67
1136 10:02:00.676100
1137 10:02:00.676184 Set Vref, RX VrefLevel [Byte0]: 68
1138 10:02:00.679643 [Byte1]: 68
1139 10:02:00.684286
1140 10:02:00.684370 Set Vref, RX VrefLevel [Byte0]: 69
1141 10:02:00.687044 [Byte1]: 69
1142 10:02:00.690980
1143 10:02:00.691061 Set Vref, RX VrefLevel [Byte0]: 70
1144 10:02:00.694413 [Byte1]: 70
1145 10:02:00.699042
1146 10:02:00.699124 Set Vref, RX VrefLevel [Byte0]: 71
1147 10:02:00.701853 [Byte1]: 71
1148 10:02:00.705943
1149 10:02:00.706025 Set Vref, RX VrefLevel [Byte0]: 72
1150 10:02:00.709518 [Byte1]: 72
1151 10:02:00.714020
1152 10:02:00.714102 Set Vref, RX VrefLevel [Byte0]: 73
1153 10:02:00.717010 [Byte1]: 73
1154 10:02:00.721110
1155 10:02:00.724807 Set Vref, RX VrefLevel [Byte0]: 74
1156 10:02:00.724890 [Byte1]: 74
1157 10:02:00.729203
1158 10:02:00.729285 Set Vref, RX VrefLevel [Byte0]: 75
1159 10:02:00.731843 [Byte1]: 75
1160 10:02:00.736769
1161 10:02:00.736850 Set Vref, RX VrefLevel [Byte0]: 76
1162 10:02:00.740535 [Byte1]: 76
1163 10:02:00.744405
1164 10:02:00.744520 Set Vref, RX VrefLevel [Byte0]: 77
1165 10:02:00.747887 [Byte1]: 77
1166 10:02:00.751880
1167 10:02:00.751963 Set Vref, RX VrefLevel [Byte0]: 78
1168 10:02:00.755885 [Byte1]: 78
1169 10:02:00.759453
1170 10:02:00.759536 Set Vref, RX VrefLevel [Byte0]: 79
1171 10:02:00.763258 [Byte1]: 79
1172 10:02:00.767253
1173 10:02:00.767336 Final RX Vref Byte 0 = 69 to rank0
1174 10:02:00.771190 Final RX Vref Byte 1 = 52 to rank0
1175 10:02:00.774090 Final RX Vref Byte 0 = 69 to rank1
1176 10:02:00.778504 Final RX Vref Byte 1 = 52 to rank1==
1177 10:02:00.781666 Dram Type= 6, Freq= 0, CH_0, rank 0
1178 10:02:00.785744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1179 10:02:00.785833 ==
1180 10:02:00.785904 DQS Delay:
1181 10:02:00.788959 DQS0 = 0, DQS1 = 0
1182 10:02:00.789039 DQM Delay:
1183 10:02:00.792534 DQM0 = 88, DQM1 = 76
1184 10:02:00.792627 DQ Delay:
1185 10:02:00.796278 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1186 10:02:00.799524 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1187 10:02:00.803203 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1188 10:02:00.806838 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1189 10:02:00.806912
1190 10:02:00.806975
1191 10:02:00.814357 [DQSOSCAuto] RK0, (LSB)MR18= 0x482a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
1192 10:02:00.817918 CH0 RK0: MR19=606, MR18=482A
1193 10:02:00.821824 CH0_RK0: MR19=0x606, MR18=0x482A, DQSOSC=391, MR23=63, INC=96, DEC=64
1194 10:02:00.821925
1195 10:02:00.825426 ----->DramcWriteLeveling(PI) begin...
1196 10:02:00.825503 ==
1197 10:02:00.829250 Dram Type= 6, Freq= 0, CH_0, rank 1
1198 10:02:00.832876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1199 10:02:00.832949 ==
1200 10:02:00.836407 Write leveling (Byte 0): 33 => 33
1201 10:02:00.840385 Write leveling (Byte 1): 31 => 31
1202 10:02:00.843844 DramcWriteLeveling(PI) end<-----
1203 10:02:00.843921
1204 10:02:00.843985 ==
1205 10:02:00.847686 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 10:02:00.851165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 10:02:00.851272 ==
1208 10:02:00.854628 [Gating] SW mode calibration
1209 10:02:00.861636 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1210 10:02:00.865310 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1211 10:02:00.869044 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1212 10:02:00.913192 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1213 10:02:00.913716 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1214 10:02:00.914391 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 10:02:00.914671 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 10:02:00.914744 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 10:02:00.914818 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 10:02:00.915093 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 10:02:00.915202 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 10:02:00.915614 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 10:02:00.915724 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 10:02:00.957428 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 10:02:00.957709 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 10:02:00.957810 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 10:02:00.957908 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 10:02:00.957971 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 10:02:00.958061 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 10:02:00.958146 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1229 10:02:00.958262 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 10:02:00.958948 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 10:02:00.959046 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 10:02:00.982495 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 10:02:00.983050 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 10:02:00.983336 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 10:02:00.983618 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 10:02:00.983714 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 10:02:00.987243 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
1238 10:02:00.990532 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 10:02:00.994623 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 10:02:00.998190 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 10:02:01.002025 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 10:02:01.005708 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 10:02:01.012264 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 10:02:01.016097 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1245 10:02:01.018796 0 10 8 | B1->B0 | 3030 2828 | 1 1 | (1 0) (1 0)
1246 10:02:01.025532 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1247 10:02:01.028716 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 10:02:01.032324 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 10:02:01.038721 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 10:02:01.042376 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 10:02:01.045593 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 10:02:01.048962 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 10:02:01.055480 0 11 8 | B1->B0 | 2d2d 4242 | 0 0 | (0 0) (0 0)
1254 10:02:01.058427 0 11 12 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
1255 10:02:01.061976 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 10:02:01.068889 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 10:02:01.071801 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 10:02:01.075564 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 10:02:01.081942 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 10:02:01.085264 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 10:02:01.089003 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1262 10:02:01.095270 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 10:02:01.098399 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 10:02:01.101879 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 10:02:01.108337 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 10:02:01.112106 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 10:02:01.114854 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 10:02:01.121867 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 10:02:01.125121 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 10:02:01.128098 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 10:02:01.134727 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 10:02:01.138446 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 10:02:01.141545 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 10:02:01.148461 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 10:02:01.151761 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 10:02:01.154979 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 10:02:01.161349 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1278 10:02:01.164709 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1279 10:02:01.168324 Total UI for P1: 0, mck2ui 16
1280 10:02:01.171744 best dqsien dly found for B0: ( 0, 14, 8)
1281 10:02:01.174942 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 10:02:01.178079 Total UI for P1: 0, mck2ui 16
1283 10:02:01.181887 best dqsien dly found for B1: ( 0, 14, 10)
1284 10:02:01.184570 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1285 10:02:01.187936 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1286 10:02:01.188024
1287 10:02:01.191433 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1288 10:02:01.198346 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1289 10:02:01.198429 [Gating] SW calibration Done
1290 10:02:01.201776 ==
1291 10:02:01.201859 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 10:02:01.207991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 10:02:01.208075 ==
1294 10:02:01.208140 RX Vref Scan: 0
1295 10:02:01.208201
1296 10:02:01.211369 RX Vref 0 -> 0, step: 1
1297 10:02:01.211452
1298 10:02:01.214665 RX Delay -130 -> 252, step: 16
1299 10:02:01.218121 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1300 10:02:01.221274 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1301 10:02:01.224837 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1302 10:02:01.231308 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1303 10:02:01.234650 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1304 10:02:01.238105 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1305 10:02:01.241272 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1306 10:02:01.244425 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1307 10:02:01.250771 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1308 10:02:01.254869 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1309 10:02:01.257605 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1310 10:02:01.260801 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1311 10:02:01.267684 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1312 10:02:01.271082 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1313 10:02:01.274147 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1314 10:02:01.277425 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1315 10:02:01.277500 ==
1316 10:02:01.281122 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 10:02:01.287760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 10:02:01.287840 ==
1319 10:02:01.287908 DQS Delay:
1320 10:02:01.287970 DQS0 = 0, DQS1 = 0
1321 10:02:01.290720 DQM Delay:
1322 10:02:01.290794 DQM0 = 84, DQM1 = 78
1323 10:02:01.294229 DQ Delay:
1324 10:02:01.297664 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1325 10:02:01.297739 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1326 10:02:01.301115 DQ8 =69, DQ9 =61, DQ10 =85, DQ11 =69
1327 10:02:01.304122 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1328 10:02:01.307326
1329 10:02:01.307403
1330 10:02:01.307466 ==
1331 10:02:01.311016 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 10:02:01.314170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 10:02:01.314243 ==
1334 10:02:01.314305
1335 10:02:01.314367
1336 10:02:01.317156 TX Vref Scan disable
1337 10:02:01.317228 == TX Byte 0 ==
1338 10:02:01.323843 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1339 10:02:01.327272 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1340 10:02:01.327348 == TX Byte 1 ==
1341 10:02:01.333991 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1342 10:02:01.337087 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1343 10:02:01.337162 ==
1344 10:02:01.340787 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 10:02:01.343908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 10:02:01.343982 ==
1347 10:02:01.358024 TX Vref=22, minBit 3, minWin=27, winSum=441
1348 10:02:01.361282 TX Vref=24, minBit 9, minWin=27, winSum=443
1349 10:02:01.364509 TX Vref=26, minBit 9, minWin=27, winSum=448
1350 10:02:01.367663 TX Vref=28, minBit 8, minWin=27, winSum=445
1351 10:02:01.371228 TX Vref=30, minBit 9, minWin=27, winSum=448
1352 10:02:01.377409 TX Vref=32, minBit 9, minWin=27, winSum=444
1353 10:02:01.381152 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 26
1354 10:02:01.381224
1355 10:02:01.384429 Final TX Range 1 Vref 26
1356 10:02:01.384498
1357 10:02:01.384598 ==
1358 10:02:01.387491 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 10:02:01.390789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 10:02:01.393889 ==
1361 10:02:01.393970
1362 10:02:01.394034
1363 10:02:01.394094 TX Vref Scan disable
1364 10:02:01.397528 == TX Byte 0 ==
1365 10:02:01.401104 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1366 10:02:01.407783 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1367 10:02:01.407865 == TX Byte 1 ==
1368 10:02:01.410733 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1369 10:02:01.417607 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1370 10:02:01.417689
1371 10:02:01.417754 [DATLAT]
1372 10:02:01.417815 Freq=800, CH0 RK1
1373 10:02:01.417874
1374 10:02:01.421128 DATLAT Default: 0xa
1375 10:02:01.421210 0, 0xFFFF, sum = 0
1376 10:02:01.424189 1, 0xFFFF, sum = 0
1377 10:02:01.427761 2, 0xFFFF, sum = 0
1378 10:02:01.427844 3, 0xFFFF, sum = 0
1379 10:02:01.431056 4, 0xFFFF, sum = 0
1380 10:02:01.431140 5, 0xFFFF, sum = 0
1381 10:02:01.433961 6, 0xFFFF, sum = 0
1382 10:02:01.434044 7, 0xFFFF, sum = 0
1383 10:02:01.437628 8, 0xFFFF, sum = 0
1384 10:02:01.437711 9, 0x0, sum = 1
1385 10:02:01.440965 10, 0x0, sum = 2
1386 10:02:01.441048 11, 0x0, sum = 3
1387 10:02:01.441113 12, 0x0, sum = 4
1388 10:02:01.444022 best_step = 10
1389 10:02:01.444104
1390 10:02:01.444168 ==
1391 10:02:01.447337 Dram Type= 6, Freq= 0, CH_0, rank 1
1392 10:02:01.450582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 10:02:01.450689 ==
1394 10:02:01.454118 RX Vref Scan: 0
1395 10:02:01.454200
1396 10:02:01.454263 RX Vref 0 -> 0, step: 1
1397 10:02:01.457555
1398 10:02:01.457636 RX Delay -111 -> 252, step: 8
1399 10:02:01.464511 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1400 10:02:01.468127 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1401 10:02:01.471309 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1402 10:02:01.474716 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1403 10:02:01.477838 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1404 10:02:01.484605 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1405 10:02:01.487735 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1406 10:02:01.490834 iDelay=217, Bit 7, Center 100 (-15 ~ 216) 232
1407 10:02:01.494365 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1408 10:02:01.497943 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1409 10:02:01.504339 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1410 10:02:01.507592 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1411 10:02:01.510752 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1412 10:02:01.514186 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1413 10:02:01.521610 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1414 10:02:01.524448 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1415 10:02:01.524587 ==
1416 10:02:01.527630 Dram Type= 6, Freq= 0, CH_0, rank 1
1417 10:02:01.530875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 10:02:01.530960 ==
1419 10:02:01.534697 DQS Delay:
1420 10:02:01.534781 DQS0 = 0, DQS1 = 0
1421 10:02:01.534847 DQM Delay:
1422 10:02:01.537875 DQM0 = 86, DQM1 = 76
1423 10:02:01.537959 DQ Delay:
1424 10:02:01.541015 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1425 10:02:01.544145 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =100
1426 10:02:01.547411 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1427 10:02:01.551069 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1428 10:02:01.551153
1429 10:02:01.551219
1430 10:02:01.560548 [DQSOSCAuto] RK1, (LSB)MR18= 0x4309, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
1431 10:02:01.560648 CH0 RK1: MR19=606, MR18=4309
1432 10:02:01.567463 CH0_RK1: MR19=0x606, MR18=0x4309, DQSOSC=393, MR23=63, INC=95, DEC=63
1433 10:02:01.571013 [RxdqsGatingPostProcess] freq 800
1434 10:02:01.577244 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1435 10:02:01.580623 Pre-setting of DQS Precalculation
1436 10:02:01.584108 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1437 10:02:01.584192 ==
1438 10:02:01.587677 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 10:02:01.593935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 10:02:01.594020 ==
1441 10:02:01.597526 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1442 10:02:01.603992 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1443 10:02:01.613383 [CA 0] Center 36 (6~67) winsize 62
1444 10:02:01.616438 [CA 1] Center 36 (6~67) winsize 62
1445 10:02:01.619845 [CA 2] Center 34 (4~65) winsize 62
1446 10:02:01.623056 [CA 3] Center 34 (3~65) winsize 63
1447 10:02:01.626483 [CA 4] Center 34 (4~65) winsize 62
1448 10:02:01.629949 [CA 5] Center 34 (3~65) winsize 63
1449 10:02:01.630034
1450 10:02:01.632944 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1451 10:02:01.633028
1452 10:02:01.636484 [CATrainingPosCal] consider 1 rank data
1453 10:02:01.639639 u2DelayCellTimex100 = 270/100 ps
1454 10:02:01.642924 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1455 10:02:01.646067 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1456 10:02:01.652996 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1457 10:02:01.656195 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1458 10:02:01.659456 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1459 10:02:01.662642 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1460 10:02:01.662726
1461 10:02:01.666043 CA PerBit enable=1, Macro0, CA PI delay=34
1462 10:02:01.666127
1463 10:02:01.669573 [CBTSetCACLKResult] CA Dly = 34
1464 10:02:01.669656 CS Dly: 4 (0~35)
1465 10:02:01.672756 ==
1466 10:02:01.676690 Dram Type= 6, Freq= 0, CH_1, rank 1
1467 10:02:01.679676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1468 10:02:01.679767 ==
1469 10:02:01.682891 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1470 10:02:01.689435 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1471 10:02:01.698974 [CA 0] Center 37 (7~67) winsize 61
1472 10:02:01.702857 [CA 1] Center 37 (6~68) winsize 63
1473 10:02:01.705764 [CA 2] Center 34 (4~65) winsize 62
1474 10:02:01.708923 [CA 3] Center 34 (3~65) winsize 63
1475 10:02:01.712399 [CA 4] Center 34 (4~65) winsize 62
1476 10:02:01.716104 [CA 5] Center 34 (3~65) winsize 63
1477 10:02:01.716187
1478 10:02:01.719236 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1479 10:02:01.719323
1480 10:02:01.722289 [CATrainingPosCal] consider 2 rank data
1481 10:02:01.725640 u2DelayCellTimex100 = 270/100 ps
1482 10:02:01.729374 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1483 10:02:01.735563 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1484 10:02:01.739366 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1485 10:02:01.742127 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1486 10:02:01.745843 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1487 10:02:01.749007 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1488 10:02:01.749089
1489 10:02:01.752429 CA PerBit enable=1, Macro0, CA PI delay=34
1490 10:02:01.752511
1491 10:02:01.755752 [CBTSetCACLKResult] CA Dly = 34
1492 10:02:01.755833 CS Dly: 5 (0~38)
1493 10:02:01.755899
1494 10:02:01.758729 ----->DramcWriteLeveling(PI) begin...
1495 10:02:01.762117 ==
1496 10:02:01.765874 Dram Type= 6, Freq= 0, CH_1, rank 0
1497 10:02:01.768802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1498 10:02:01.768885 ==
1499 10:02:01.772210 Write leveling (Byte 0): 25 => 25
1500 10:02:01.775546 Write leveling (Byte 1): 30 => 30
1501 10:02:01.778834 DramcWriteLeveling(PI) end<-----
1502 10:02:01.778915
1503 10:02:01.778980 ==
1504 10:02:01.782506 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 10:02:01.785600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 10:02:01.785683 ==
1507 10:02:01.789330 [Gating] SW mode calibration
1508 10:02:01.795626 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1509 10:02:01.801976 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1510 10:02:01.805611 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1511 10:02:01.808969 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1512 10:02:01.815255 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 10:02:01.818899 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 10:02:01.822063 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 10:02:01.828911 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 10:02:01.831851 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 10:02:01.835123 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 10:02:01.841824 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 10:02:01.844960 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 10:02:01.848284 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 10:02:01.851695 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 10:02:01.858481 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 10:02:01.861615 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 10:02:01.864821 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 10:02:01.871621 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 10:02:01.874799 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 10:02:01.877849 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1528 10:02:01.884560 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 10:02:01.888470 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 10:02:01.891136 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 10:02:01.897811 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 10:02:01.901614 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 10:02:01.904967 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 10:02:01.911584 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 10:02:01.914898 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 10:02:01.918010 0 9 8 | B1->B0 | 2c2c 2f2f | 1 1 | (0 0) (1 1)
1537 10:02:01.924335 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 10:02:01.927714 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 10:02:01.931184 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 10:02:01.937692 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 10:02:01.941359 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 10:02:01.944459 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 10:02:01.951316 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
1544 10:02:01.954856 0 10 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
1545 10:02:01.957715 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 10:02:01.964744 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 10:02:01.967623 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 10:02:01.970899 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 10:02:01.977307 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 10:02:01.981135 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 10:02:01.984630 0 11 4 | B1->B0 | 2727 2b2a | 0 1 | (0 0) (0 0)
1552 10:02:01.990703 0 11 8 | B1->B0 | 3b3b 4040 | 1 0 | (0 0) (0 0)
1553 10:02:01.993941 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 10:02:01.997370 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 10:02:02.004086 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 10:02:02.007340 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 10:02:02.010733 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 10:02:02.017477 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 10:02:02.020233 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1560 10:02:02.023858 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1561 10:02:02.030451 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 10:02:02.033605 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 10:02:02.037639 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 10:02:02.043655 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 10:02:02.047159 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 10:02:02.050430 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 10:02:02.057139 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 10:02:02.060192 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 10:02:02.063781 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 10:02:02.066738 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 10:02:02.073340 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 10:02:02.077162 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 10:02:02.080282 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 10:02:02.086581 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 10:02:02.090247 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1576 10:02:02.093266 Total UI for P1: 0, mck2ui 16
1577 10:02:02.096461 best dqsien dly found for B0: ( 0, 14, 2)
1578 10:02:02.099890 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 10:02:02.103238 Total UI for P1: 0, mck2ui 16
1580 10:02:02.106894 best dqsien dly found for B1: ( 0, 14, 4)
1581 10:02:02.110216 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1582 10:02:02.113356 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1583 10:02:02.116882
1584 10:02:02.120191 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1585 10:02:02.123330 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1586 10:02:02.126666 [Gating] SW calibration Done
1587 10:02:02.126749 ==
1588 10:02:02.129941 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 10:02:02.133227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 10:02:02.133311 ==
1591 10:02:02.133376 RX Vref Scan: 0
1592 10:02:02.133435
1593 10:02:02.136643 RX Vref 0 -> 0, step: 1
1594 10:02:02.136727
1595 10:02:02.139788 RX Delay -130 -> 252, step: 16
1596 10:02:02.143092 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1597 10:02:02.146341 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1598 10:02:02.153140 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1599 10:02:02.156486 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1600 10:02:02.159656 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1601 10:02:02.164000 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1602 10:02:02.166412 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1603 10:02:02.173134 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1604 10:02:02.176144 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1605 10:02:02.179465 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1606 10:02:02.183079 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1607 10:02:02.186619 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1608 10:02:02.193291 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1609 10:02:02.196563 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1610 10:02:02.199668 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1611 10:02:02.203002 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1612 10:02:02.203086 ==
1613 10:02:02.206141 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 10:02:02.212978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 10:02:02.213062 ==
1616 10:02:02.213127 DQS Delay:
1617 10:02:02.216121 DQS0 = 0, DQS1 = 0
1618 10:02:02.216204 DQM Delay:
1619 10:02:02.216270 DQM0 = 89, DQM1 = 78
1620 10:02:02.219261 DQ Delay:
1621 10:02:02.223756 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1622 10:02:02.226572 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1623 10:02:02.229404 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1624 10:02:02.232686 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1625 10:02:02.232769
1626 10:02:02.232834
1627 10:02:02.232894 ==
1628 10:02:02.236258 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 10:02:02.239514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 10:02:02.239598 ==
1631 10:02:02.239664
1632 10:02:02.239723
1633 10:02:02.242892 TX Vref Scan disable
1634 10:02:02.245849 == TX Byte 0 ==
1635 10:02:02.249195 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1636 10:02:02.252881 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1637 10:02:02.256255 == TX Byte 1 ==
1638 10:02:02.259165 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1639 10:02:02.262827 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1640 10:02:02.262923 ==
1641 10:02:02.265863 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 10:02:02.269273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 10:02:02.269343 ==
1644 10:02:02.284138 TX Vref=22, minBit 3, minWin=26, winSum=435
1645 10:02:02.287340 TX Vref=24, minBit 1, minWin=27, winSum=440
1646 10:02:02.290663 TX Vref=26, minBit 9, minWin=27, winSum=448
1647 10:02:02.294374 TX Vref=28, minBit 0, minWin=27, winSum=448
1648 10:02:02.297289 TX Vref=30, minBit 9, minWin=27, winSum=448
1649 10:02:02.303925 TX Vref=32, minBit 0, minWin=27, winSum=443
1650 10:02:02.306988 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 26
1651 10:02:02.307067
1652 10:02:02.310452 Final TX Range 1 Vref 26
1653 10:02:02.310521
1654 10:02:02.310584 ==
1655 10:02:02.313700 Dram Type= 6, Freq= 0, CH_1, rank 0
1656 10:02:02.317232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1657 10:02:02.320303 ==
1658 10:02:02.320379
1659 10:02:02.320440
1660 10:02:02.320497 TX Vref Scan disable
1661 10:02:02.324203 == TX Byte 0 ==
1662 10:02:02.327088 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1663 10:02:02.334036 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1664 10:02:02.334118 == TX Byte 1 ==
1665 10:02:02.337180 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1666 10:02:02.344095 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1667 10:02:02.344178
1668 10:02:02.344243 [DATLAT]
1669 10:02:02.344304 Freq=800, CH1 RK0
1670 10:02:02.344362
1671 10:02:02.347652 DATLAT Default: 0xa
1672 10:02:02.347736 0, 0xFFFF, sum = 0
1673 10:02:02.350664 1, 0xFFFF, sum = 0
1674 10:02:02.350741 2, 0xFFFF, sum = 0
1675 10:02:02.353806 3, 0xFFFF, sum = 0
1676 10:02:02.357301 4, 0xFFFF, sum = 0
1677 10:02:02.357386 5, 0xFFFF, sum = 0
1678 10:02:02.360554 6, 0xFFFF, sum = 0
1679 10:02:02.360640 7, 0xFFFF, sum = 0
1680 10:02:02.364404 8, 0xFFFF, sum = 0
1681 10:02:02.364489 9, 0x0, sum = 1
1682 10:02:02.364600 10, 0x0, sum = 2
1683 10:02:02.367461 11, 0x0, sum = 3
1684 10:02:02.367546 12, 0x0, sum = 4
1685 10:02:02.370761 best_step = 10
1686 10:02:02.370844
1687 10:02:02.370909 ==
1688 10:02:02.373818 Dram Type= 6, Freq= 0, CH_1, rank 0
1689 10:02:02.377431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1690 10:02:02.377515 ==
1691 10:02:02.380452 RX Vref Scan: 1
1692 10:02:02.380573
1693 10:02:02.380641 Set Vref Range= 32 -> 127
1694 10:02:02.383662
1695 10:02:02.383744 RX Vref 32 -> 127, step: 1
1696 10:02:02.383810
1697 10:02:02.387071 RX Delay -95 -> 252, step: 8
1698 10:02:02.387155
1699 10:02:02.390663 Set Vref, RX VrefLevel [Byte0]: 32
1700 10:02:02.393685 [Byte1]: 32
1701 10:02:02.393769
1702 10:02:02.397033 Set Vref, RX VrefLevel [Byte0]: 33
1703 10:02:02.400286 [Byte1]: 33
1704 10:02:02.404554
1705 10:02:02.404637 Set Vref, RX VrefLevel [Byte0]: 34
1706 10:02:02.407680 [Byte1]: 34
1707 10:02:02.411684
1708 10:02:02.411768 Set Vref, RX VrefLevel [Byte0]: 35
1709 10:02:02.414952 [Byte1]: 35
1710 10:02:02.419757
1711 10:02:02.419841 Set Vref, RX VrefLevel [Byte0]: 36
1712 10:02:02.422556 [Byte1]: 36
1713 10:02:02.427086
1714 10:02:02.427169 Set Vref, RX VrefLevel [Byte0]: 37
1715 10:02:02.430490 [Byte1]: 37
1716 10:02:02.434643
1717 10:02:02.434726 Set Vref, RX VrefLevel [Byte0]: 38
1718 10:02:02.441255 [Byte1]: 38
1719 10:02:02.441339
1720 10:02:02.444562 Set Vref, RX VrefLevel [Byte0]: 39
1721 10:02:02.447719 [Byte1]: 39
1722 10:02:02.447802
1723 10:02:02.450827 Set Vref, RX VrefLevel [Byte0]: 40
1724 10:02:02.454322 [Byte1]: 40
1725 10:02:02.454406
1726 10:02:02.457585 Set Vref, RX VrefLevel [Byte0]: 41
1727 10:02:02.461300 [Byte1]: 41
1728 10:02:02.465006
1729 10:02:02.465089 Set Vref, RX VrefLevel [Byte0]: 42
1730 10:02:02.468479 [Byte1]: 42
1731 10:02:02.472835
1732 10:02:02.472918 Set Vref, RX VrefLevel [Byte0]: 43
1733 10:02:02.476257 [Byte1]: 43
1734 10:02:02.480151
1735 10:02:02.480234 Set Vref, RX VrefLevel [Byte0]: 44
1736 10:02:02.483436 [Byte1]: 44
1737 10:02:02.487798
1738 10:02:02.487881 Set Vref, RX VrefLevel [Byte0]: 45
1739 10:02:02.490983 [Byte1]: 45
1740 10:02:02.495161
1741 10:02:02.495245 Set Vref, RX VrefLevel [Byte0]: 46
1742 10:02:02.498795 [Byte1]: 46
1743 10:02:02.503258
1744 10:02:02.503340 Set Vref, RX VrefLevel [Byte0]: 47
1745 10:02:02.506446 [Byte1]: 47
1746 10:02:02.510350
1747 10:02:02.510433 Set Vref, RX VrefLevel [Byte0]: 48
1748 10:02:02.513676 [Byte1]: 48
1749 10:02:02.518472
1750 10:02:02.518555 Set Vref, RX VrefLevel [Byte0]: 49
1751 10:02:02.521715 [Byte1]: 49
1752 10:02:02.526116
1753 10:02:02.526199 Set Vref, RX VrefLevel [Byte0]: 50
1754 10:02:02.528922 [Byte1]: 50
1755 10:02:02.533359
1756 10:02:02.533442 Set Vref, RX VrefLevel [Byte0]: 51
1757 10:02:02.539719 [Byte1]: 51
1758 10:02:02.539802
1759 10:02:02.543100 Set Vref, RX VrefLevel [Byte0]: 52
1760 10:02:02.546410 [Byte1]: 52
1761 10:02:02.546499
1762 10:02:02.549684 Set Vref, RX VrefLevel [Byte0]: 53
1763 10:02:02.553384 [Byte1]: 53
1764 10:02:02.553494
1765 10:02:02.556503 Set Vref, RX VrefLevel [Byte0]: 54
1766 10:02:02.560837 [Byte1]: 54
1767 10:02:02.563873
1768 10:02:02.563957 Set Vref, RX VrefLevel [Byte0]: 55
1769 10:02:02.567470 [Byte1]: 55
1770 10:02:02.571244
1771 10:02:02.571328 Set Vref, RX VrefLevel [Byte0]: 56
1772 10:02:02.574557 [Byte1]: 56
1773 10:02:02.579078
1774 10:02:02.579161 Set Vref, RX VrefLevel [Byte0]: 57
1775 10:02:02.582094 [Byte1]: 57
1776 10:02:02.586623
1777 10:02:02.586706 Set Vref, RX VrefLevel [Byte0]: 58
1778 10:02:02.589996 [Byte1]: 58
1779 10:02:02.594051
1780 10:02:02.594134 Set Vref, RX VrefLevel [Byte0]: 59
1781 10:02:02.597373 [Byte1]: 59
1782 10:02:02.601567
1783 10:02:02.601650 Set Vref, RX VrefLevel [Byte0]: 60
1784 10:02:02.605371 [Byte1]: 60
1785 10:02:02.609519
1786 10:02:02.609602 Set Vref, RX VrefLevel [Byte0]: 61
1787 10:02:02.612719 [Byte1]: 61
1788 10:02:02.616873
1789 10:02:02.616956 Set Vref, RX VrefLevel [Byte0]: 62
1790 10:02:02.620237 [Byte1]: 62
1791 10:02:02.624446
1792 10:02:02.624534 Set Vref, RX VrefLevel [Byte0]: 63
1793 10:02:02.628148 [Byte1]: 63
1794 10:02:02.632189
1795 10:02:02.632272 Set Vref, RX VrefLevel [Byte0]: 64
1796 10:02:02.635366 [Byte1]: 64
1797 10:02:02.639644
1798 10:02:02.639726 Set Vref, RX VrefLevel [Byte0]: 65
1799 10:02:02.643005 [Byte1]: 65
1800 10:02:02.647572
1801 10:02:02.647654 Set Vref, RX VrefLevel [Byte0]: 66
1802 10:02:02.650696 [Byte1]: 66
1803 10:02:02.654706
1804 10:02:02.654780 Set Vref, RX VrefLevel [Byte0]: 67
1805 10:02:02.658433 [Byte1]: 67
1806 10:02:02.662334
1807 10:02:02.662408 Set Vref, RX VrefLevel [Byte0]: 68
1808 10:02:02.665662 [Byte1]: 68
1809 10:02:02.669870
1810 10:02:02.669941 Set Vref, RX VrefLevel [Byte0]: 69
1811 10:02:02.673553 [Byte1]: 69
1812 10:02:02.677577
1813 10:02:02.677646 Set Vref, RX VrefLevel [Byte0]: 70
1814 10:02:02.681274 [Byte1]: 70
1815 10:02:02.685456
1816 10:02:02.685530 Set Vref, RX VrefLevel [Byte0]: 71
1817 10:02:02.688440 [Byte1]: 71
1818 10:02:02.692919
1819 10:02:02.692999 Set Vref, RX VrefLevel [Byte0]: 72
1820 10:02:02.696246 [Byte1]: 72
1821 10:02:02.700621
1822 10:02:02.700698 Set Vref, RX VrefLevel [Byte0]: 73
1823 10:02:02.703678 [Byte1]: 73
1824 10:02:02.708671
1825 10:02:02.708741 Set Vref, RX VrefLevel [Byte0]: 74
1826 10:02:02.711822 [Byte1]: 74
1827 10:02:02.715723
1828 10:02:02.715801 Final RX Vref Byte 0 = 55 to rank0
1829 10:02:02.719353 Final RX Vref Byte 1 = 63 to rank0
1830 10:02:02.722354 Final RX Vref Byte 0 = 55 to rank1
1831 10:02:02.726138 Final RX Vref Byte 1 = 63 to rank1==
1832 10:02:02.729073 Dram Type= 6, Freq= 0, CH_1, rank 0
1833 10:02:02.732735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 10:02:02.735935 ==
1835 10:02:02.736009 DQS Delay:
1836 10:02:02.736071 DQS0 = 0, DQS1 = 0
1837 10:02:02.739003 DQM Delay:
1838 10:02:02.739073 DQM0 = 86, DQM1 = 79
1839 10:02:02.742415 DQ Delay:
1840 10:02:02.745748 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1841 10:02:02.745848 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1842 10:02:02.748938 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1843 10:02:02.755817 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1844 10:02:02.755896
1845 10:02:02.755959
1846 10:02:02.762217 [DQSOSCAuto] RK0, (LSB)MR18= 0x301c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1847 10:02:02.765687 CH1 RK0: MR19=606, MR18=301C
1848 10:02:02.772789 CH1_RK0: MR19=0x606, MR18=0x301C, DQSOSC=397, MR23=63, INC=93, DEC=62
1849 10:02:02.772874
1850 10:02:02.776030 ----->DramcWriteLeveling(PI) begin...
1851 10:02:02.776102 ==
1852 10:02:02.779189 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 10:02:02.782459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 10:02:02.782529 ==
1855 10:02:02.785732 Write leveling (Byte 0): 27 => 27
1856 10:02:02.789120 Write leveling (Byte 1): 28 => 28
1857 10:02:02.792703 DramcWriteLeveling(PI) end<-----
1858 10:02:02.792773
1859 10:02:02.792832 ==
1860 10:02:02.795574 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 10:02:02.798926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1862 10:02:02.798996 ==
1863 10:02:02.802495 [Gating] SW mode calibration
1864 10:02:02.809062 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1865 10:02:02.815595 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1866 10:02:02.818967 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1867 10:02:02.822513 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1868 10:02:02.829162 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1869 10:02:02.832542 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 10:02:02.835372 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 10:02:02.842319 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 10:02:02.845256 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 10:02:02.848941 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 10:02:02.855281 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 10:02:02.858622 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 10:02:02.862262 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 10:02:02.868905 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 10:02:02.872143 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 10:02:02.875281 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 10:02:02.882226 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 10:02:02.885521 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 10:02:02.888395 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1883 10:02:02.895371 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1884 10:02:02.898727 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 10:02:02.902441 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 10:02:02.908855 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 10:02:02.912139 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 10:02:02.915146 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 10:02:02.918841 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 10:02:02.925073 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 10:02:02.928358 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 10:02:02.931624 0 9 8 | B1->B0 | 2e2d 2a2a | 1 1 | (0 0) (1 1)
1893 10:02:02.938494 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 10:02:02.941844 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 10:02:02.944931 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 10:02:02.951885 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 10:02:02.955321 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 10:02:02.958241 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 10:02:02.965252 0 10 4 | B1->B0 | 2f2f 3434 | 0 1 | (1 0) (1 1)
1900 10:02:02.968670 0 10 8 | B1->B0 | 2525 2f2f | 0 0 | (1 1) (1 1)
1901 10:02:02.971377 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 10:02:02.978098 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 10:02:02.981280 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 10:02:02.984876 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 10:02:02.991117 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 10:02:02.994975 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 10:02:02.998071 0 11 4 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
1908 10:02:03.005316 0 11 8 | B1->B0 | 3e3e 3434 | 0 0 | (0 0) (0 0)
1909 10:02:03.007969 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 10:02:03.011401 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 10:02:03.018218 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 10:02:03.021442 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 10:02:03.024721 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 10:02:03.031310 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 10:02:03.034847 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1916 10:02:03.038031 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1917 10:02:03.044290 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 10:02:03.047802 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 10:02:03.051063 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 10:02:03.057627 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 10:02:03.061168 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 10:02:03.064268 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 10:02:03.071173 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 10:02:03.074626 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 10:02:03.077684 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 10:02:03.084592 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 10:02:03.087786 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 10:02:03.091449 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 10:02:03.094403 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 10:02:03.100903 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 10:02:03.104165 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1932 10:02:03.107652 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1933 10:02:03.111016 Total UI for P1: 0, mck2ui 16
1934 10:02:03.114539 best dqsien dly found for B1: ( 0, 14, 4)
1935 10:02:03.121438 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 10:02:03.124206 Total UI for P1: 0, mck2ui 16
1937 10:02:03.127556 best dqsien dly found for B0: ( 0, 14, 8)
1938 10:02:03.130920 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1939 10:02:03.134082 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1940 10:02:03.134157
1941 10:02:03.137892 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1942 10:02:03.140875 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1943 10:02:03.144333 [Gating] SW calibration Done
1944 10:02:03.144439 ==
1945 10:02:03.147606 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 10:02:03.150784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 10:02:03.150856 ==
1948 10:02:03.153949 RX Vref Scan: 0
1949 10:02:03.154025
1950 10:02:03.154084 RX Vref 0 -> 0, step: 1
1951 10:02:03.154141
1952 10:02:03.157240 RX Delay -130 -> 252, step: 16
1953 10:02:03.164123 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1954 10:02:03.167593 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1955 10:02:03.170752 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1956 10:02:03.174133 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1957 10:02:03.177653 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1958 10:02:03.183774 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1959 10:02:03.187448 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1960 10:02:03.190450 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1961 10:02:03.193600 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1962 10:02:03.197247 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1963 10:02:03.203695 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1964 10:02:03.207174 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1965 10:02:03.210351 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1966 10:02:03.214049 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1967 10:02:03.217288 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1968 10:02:03.223633 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1969 10:02:03.223714 ==
1970 10:02:03.227254 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 10:02:03.230238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 10:02:03.230315 ==
1973 10:02:03.230377 DQS Delay:
1974 10:02:03.234054 DQS0 = 0, DQS1 = 0
1975 10:02:03.234132 DQM Delay:
1976 10:02:03.236682 DQM0 = 87, DQM1 = 78
1977 10:02:03.236763 DQ Delay:
1978 10:02:03.240203 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1979 10:02:03.243443 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1980 10:02:03.246921 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1981 10:02:03.250149 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1982 10:02:03.250226
1983 10:02:03.250288
1984 10:02:03.250345 ==
1985 10:02:03.253404 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 10:02:03.259775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 10:02:03.259852 ==
1988 10:02:03.259915
1989 10:02:03.259983
1990 10:02:03.260042 TX Vref Scan disable
1991 10:02:03.263488 == TX Byte 0 ==
1992 10:02:03.266519 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1993 10:02:03.273149 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1994 10:02:03.273226 == TX Byte 1 ==
1995 10:02:03.276261 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1996 10:02:03.283495 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1997 10:02:03.283578 ==
1998 10:02:03.286567 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 10:02:03.289747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 10:02:03.289829 ==
2001 10:02:03.302509 TX Vref=22, minBit 8, minWin=27, winSum=445
2002 10:02:03.305517 TX Vref=24, minBit 8, minWin=27, winSum=446
2003 10:02:03.309046 TX Vref=26, minBit 13, minWin=27, winSum=451
2004 10:02:03.312412 TX Vref=28, minBit 13, minWin=27, winSum=452
2005 10:02:03.316017 TX Vref=30, minBit 13, minWin=27, winSum=449
2006 10:02:03.322160 TX Vref=32, minBit 8, minWin=27, winSum=448
2007 10:02:03.325604 [TxChooseVref] Worse bit 13, Min win 27, Win sum 452, Final Vref 28
2008 10:02:03.325686
2009 10:02:03.329246 Final TX Range 1 Vref 28
2010 10:02:03.329329
2011 10:02:03.329394 ==
2012 10:02:03.332029 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 10:02:03.335288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 10:02:03.338960 ==
2015 10:02:03.339067
2016 10:02:03.339159
2017 10:02:03.339247 TX Vref Scan disable
2018 10:02:03.342525 == TX Byte 0 ==
2019 10:02:03.346293 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2020 10:02:03.349375 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2021 10:02:03.353053 == TX Byte 1 ==
2022 10:02:03.355972 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2023 10:02:03.359346 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2024 10:02:03.362719
2025 10:02:03.362800 [DATLAT]
2026 10:02:03.362864 Freq=800, CH1 RK1
2027 10:02:03.362923
2028 10:02:03.366306 DATLAT Default: 0xa
2029 10:02:03.366387 0, 0xFFFF, sum = 0
2030 10:02:03.369377 1, 0xFFFF, sum = 0
2031 10:02:03.369460 2, 0xFFFF, sum = 0
2032 10:02:03.372686 3, 0xFFFF, sum = 0
2033 10:02:03.375924 4, 0xFFFF, sum = 0
2034 10:02:03.376007 5, 0xFFFF, sum = 0
2035 10:02:03.379408 6, 0xFFFF, sum = 0
2036 10:02:03.379517 7, 0xFFFF, sum = 0
2037 10:02:03.382630 8, 0xFFFF, sum = 0
2038 10:02:03.382730 9, 0x0, sum = 1
2039 10:02:03.382821 10, 0x0, sum = 2
2040 10:02:03.386028 11, 0x0, sum = 3
2041 10:02:03.386111 12, 0x0, sum = 4
2042 10:02:03.389294 best_step = 10
2043 10:02:03.389375
2044 10:02:03.389439 ==
2045 10:02:03.392915 Dram Type= 6, Freq= 0, CH_1, rank 1
2046 10:02:03.396187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2047 10:02:03.396269 ==
2048 10:02:03.399277 RX Vref Scan: 0
2049 10:02:03.399359
2050 10:02:03.399423 RX Vref 0 -> 0, step: 1
2051 10:02:03.399483
2052 10:02:03.402239 RX Delay -95 -> 252, step: 8
2053 10:02:03.409643 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2054 10:02:03.412780 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2055 10:02:03.415941 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2056 10:02:03.419046 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2057 10:02:03.422892 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2058 10:02:03.429037 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2059 10:02:03.432797 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2060 10:02:03.435460 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2061 10:02:03.439008 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2062 10:02:03.445390 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2063 10:02:03.448871 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2064 10:02:03.452972 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2065 10:02:03.455954 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2066 10:02:03.458820 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2067 10:02:03.465664 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2068 10:02:03.468943 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2069 10:02:03.469020 ==
2070 10:02:03.472626 Dram Type= 6, Freq= 0, CH_1, rank 1
2071 10:02:03.475552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2072 10:02:03.475631 ==
2073 10:02:03.478712 DQS Delay:
2074 10:02:03.478784 DQS0 = 0, DQS1 = 0
2075 10:02:03.478844 DQM Delay:
2076 10:02:03.482258 DQM0 = 87, DQM1 = 78
2077 10:02:03.482340 DQ Delay:
2078 10:02:03.485440 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2079 10:02:03.488673 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2080 10:02:03.491969 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2081 10:02:03.495571 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2082 10:02:03.495652
2083 10:02:03.495717
2084 10:02:03.505129 [DQSOSCAuto] RK1, (LSB)MR18= 0x1710, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 404 ps
2085 10:02:03.508701 CH1 RK1: MR19=606, MR18=1710
2086 10:02:03.511865 CH1_RK1: MR19=0x606, MR18=0x1710, DQSOSC=404, MR23=63, INC=90, DEC=60
2087 10:02:03.515418 [RxdqsGatingPostProcess] freq 800
2088 10:02:03.522174 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2089 10:02:03.525227 Pre-setting of DQS Precalculation
2090 10:02:03.528510 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2091 10:02:03.538326 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2092 10:02:03.544796 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2093 10:02:03.544878
2094 10:02:03.544942
2095 10:02:03.548320 [Calibration Summary] 1600 Mbps
2096 10:02:03.548408 CH 0, Rank 0
2097 10:02:03.551334 SW Impedance : PASS
2098 10:02:03.551415 DUTY Scan : NO K
2099 10:02:03.554923 ZQ Calibration : PASS
2100 10:02:03.558545 Jitter Meter : NO K
2101 10:02:03.558627 CBT Training : PASS
2102 10:02:03.561562 Write leveling : PASS
2103 10:02:03.564761 RX DQS gating : PASS
2104 10:02:03.564842 RX DQ/DQS(RDDQC) : PASS
2105 10:02:03.568122 TX DQ/DQS : PASS
2106 10:02:03.571570 RX DATLAT : PASS
2107 10:02:03.571677 RX DQ/DQS(Engine): PASS
2108 10:02:03.574817 TX OE : NO K
2109 10:02:03.574899 All Pass.
2110 10:02:03.574963
2111 10:02:03.577933 CH 0, Rank 1
2112 10:02:03.578013 SW Impedance : PASS
2113 10:02:03.581593 DUTY Scan : NO K
2114 10:02:03.584450 ZQ Calibration : PASS
2115 10:02:03.584602 Jitter Meter : NO K
2116 10:02:03.587848 CBT Training : PASS
2117 10:02:03.587947 Write leveling : PASS
2118 10:02:03.591616 RX DQS gating : PASS
2119 10:02:03.594872 RX DQ/DQS(RDDQC) : PASS
2120 10:02:03.594953 TX DQ/DQS : PASS
2121 10:02:03.597844 RX DATLAT : PASS
2122 10:02:03.601342 RX DQ/DQS(Engine): PASS
2123 10:02:03.601449 TX OE : NO K
2124 10:02:03.604597 All Pass.
2125 10:02:03.604678
2126 10:02:03.604741 CH 1, Rank 0
2127 10:02:03.607673 SW Impedance : PASS
2128 10:02:03.607754 DUTY Scan : NO K
2129 10:02:03.611544 ZQ Calibration : PASS
2130 10:02:03.615160 Jitter Meter : NO K
2131 10:02:03.615242 CBT Training : PASS
2132 10:02:03.617881 Write leveling : PASS
2133 10:02:03.621775 RX DQS gating : PASS
2134 10:02:03.621857 RX DQ/DQS(RDDQC) : PASS
2135 10:02:03.624862 TX DQ/DQS : PASS
2136 10:02:03.627746 RX DATLAT : PASS
2137 10:02:03.627828 RX DQ/DQS(Engine): PASS
2138 10:02:03.631285 TX OE : NO K
2139 10:02:03.631367 All Pass.
2140 10:02:03.631432
2141 10:02:03.634789 CH 1, Rank 1
2142 10:02:03.634872 SW Impedance : PASS
2143 10:02:03.637890 DUTY Scan : NO K
2144 10:02:03.637972 ZQ Calibration : PASS
2145 10:02:03.641384 Jitter Meter : NO K
2146 10:02:03.644314 CBT Training : PASS
2147 10:02:03.644427 Write leveling : PASS
2148 10:02:03.648226 RX DQS gating : PASS
2149 10:02:03.651301 RX DQ/DQS(RDDQC) : PASS
2150 10:02:03.651383 TX DQ/DQS : PASS
2151 10:02:03.654293 RX DATLAT : PASS
2152 10:02:03.658252 RX DQ/DQS(Engine): PASS
2153 10:02:03.658335 TX OE : NO K
2154 10:02:03.660701 All Pass.
2155 10:02:03.660783
2156 10:02:03.660848 DramC Write-DBI off
2157 10:02:03.664658 PER_BANK_REFRESH: Hybrid Mode
2158 10:02:03.668179 TX_TRACKING: ON
2159 10:02:03.670972 [GetDramInforAfterCalByMRR] Vendor 6.
2160 10:02:03.674362 [GetDramInforAfterCalByMRR] Revision 606.
2161 10:02:03.677535 [GetDramInforAfterCalByMRR] Revision 2 0.
2162 10:02:03.677617 MR0 0x3b3b
2163 10:02:03.677682 MR8 0x5151
2164 10:02:03.680989 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2165 10:02:03.684431
2166 10:02:03.684512 MR0 0x3b3b
2167 10:02:03.684644 MR8 0x5151
2168 10:02:03.687823 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2169 10:02:03.687906
2170 10:02:03.697178 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2171 10:02:03.700487 [FAST_K] Save calibration result to emmc
2172 10:02:03.703758 [FAST_K] Save calibration result to emmc
2173 10:02:03.707259 dram_init: config_dvfs: 1
2174 10:02:03.710631 dramc_set_vcore_voltage set vcore to 662500
2175 10:02:03.714106 Read voltage for 1200, 2
2176 10:02:03.714189 Vio18 = 0
2177 10:02:03.714253 Vcore = 662500
2178 10:02:03.717154 Vdram = 0
2179 10:02:03.717236 Vddq = 0
2180 10:02:03.717300 Vmddr = 0
2181 10:02:03.724072 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2182 10:02:03.727165 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2183 10:02:03.730430 MEM_TYPE=3, freq_sel=15
2184 10:02:03.733664 sv_algorithm_assistance_LP4_1600
2185 10:02:03.736913 ============ PULL DRAM RESETB DOWN ============
2186 10:02:03.743567 ========== PULL DRAM RESETB DOWN end =========
2187 10:02:03.747093 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2188 10:02:03.750116 ===================================
2189 10:02:03.753660 LPDDR4 DRAM CONFIGURATION
2190 10:02:03.757040 ===================================
2191 10:02:03.757148 EX_ROW_EN[0] = 0x0
2192 10:02:03.759985 EX_ROW_EN[1] = 0x0
2193 10:02:03.760088 LP4Y_EN = 0x0
2194 10:02:03.763542 WORK_FSP = 0x0
2195 10:02:03.763617 WL = 0x4
2196 10:02:03.766647 RL = 0x4
2197 10:02:03.766749 BL = 0x2
2198 10:02:03.769895 RPST = 0x0
2199 10:02:03.769994 RD_PRE = 0x0
2200 10:02:03.773884 WR_PRE = 0x1
2201 10:02:03.777146 WR_PST = 0x0
2202 10:02:03.777224 DBI_WR = 0x0
2203 10:02:03.780260 DBI_RD = 0x0
2204 10:02:03.780359 OTF = 0x1
2205 10:02:03.783287 ===================================
2206 10:02:03.787325 ===================================
2207 10:02:03.787400 ANA top config
2208 10:02:03.790135 ===================================
2209 10:02:03.793557 DLL_ASYNC_EN = 0
2210 10:02:03.796986 ALL_SLAVE_EN = 0
2211 10:02:03.799970 NEW_RANK_MODE = 1
2212 10:02:03.803194 DLL_IDLE_MODE = 1
2213 10:02:03.803296 LP45_APHY_COMB_EN = 1
2214 10:02:03.806474 TX_ODT_DIS = 1
2215 10:02:03.810351 NEW_8X_MODE = 1
2216 10:02:03.813593 ===================================
2217 10:02:03.816495 ===================================
2218 10:02:03.819763 data_rate = 2400
2219 10:02:03.823495 CKR = 1
2220 10:02:03.823598 DQ_P2S_RATIO = 8
2221 10:02:03.826615 ===================================
2222 10:02:03.830301 CA_P2S_RATIO = 8
2223 10:02:03.833023 DQ_CA_OPEN = 0
2224 10:02:03.836725 DQ_SEMI_OPEN = 0
2225 10:02:03.840283 CA_SEMI_OPEN = 0
2226 10:02:03.843131 CA_FULL_RATE = 0
2227 10:02:03.843232 DQ_CKDIV4_EN = 0
2228 10:02:03.846580 CA_CKDIV4_EN = 0
2229 10:02:03.850045 CA_PREDIV_EN = 0
2230 10:02:03.853422 PH8_DLY = 17
2231 10:02:03.856564 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2232 10:02:03.860072 DQ_AAMCK_DIV = 4
2233 10:02:03.860173 CA_AAMCK_DIV = 4
2234 10:02:03.863001 CA_ADMCK_DIV = 4
2235 10:02:03.866806 DQ_TRACK_CA_EN = 0
2236 10:02:03.869530 CA_PICK = 1200
2237 10:02:03.873260 CA_MCKIO = 1200
2238 10:02:03.876445 MCKIO_SEMI = 0
2239 10:02:03.879837 PLL_FREQ = 2366
2240 10:02:03.879937 DQ_UI_PI_RATIO = 32
2241 10:02:03.882849 CA_UI_PI_RATIO = 0
2242 10:02:03.886520 ===================================
2243 10:02:03.889475 ===================================
2244 10:02:03.893065 memory_type:LPDDR4
2245 10:02:03.896624 GP_NUM : 10
2246 10:02:03.896696 SRAM_EN : 1
2247 10:02:03.899598 MD32_EN : 0
2248 10:02:03.902694 ===================================
2249 10:02:03.906465 [ANA_INIT] >>>>>>>>>>>>>>
2250 10:02:03.906542 <<<<<< [CONFIGURE PHASE]: ANA_TX
2251 10:02:03.912676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2252 10:02:03.916057 ===================================
2253 10:02:03.916157 data_rate = 2400,PCW = 0X5b00
2254 10:02:03.919693 ===================================
2255 10:02:03.923045 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2256 10:02:03.929556 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2257 10:02:03.936462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 10:02:03.939476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2259 10:02:03.943227 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2260 10:02:03.946294 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2261 10:02:03.949473 [ANA_INIT] flow start
2262 10:02:03.949545 [ANA_INIT] PLL >>>>>>>>
2263 10:02:03.953001 [ANA_INIT] PLL <<<<<<<<
2264 10:02:03.956337 [ANA_INIT] MIDPI >>>>>>>>
2265 10:02:03.959376 [ANA_INIT] MIDPI <<<<<<<<
2266 10:02:03.959478 [ANA_INIT] DLL >>>>>>>>
2267 10:02:03.962311 [ANA_INIT] DLL <<<<<<<<
2268 10:02:03.962409 [ANA_INIT] flow end
2269 10:02:03.969181 ============ LP4 DIFF to SE enter ============
2270 10:02:03.972474 ============ LP4 DIFF to SE exit ============
2271 10:02:03.975539 [ANA_INIT] <<<<<<<<<<<<<
2272 10:02:03.979317 [Flow] Enable top DCM control >>>>>
2273 10:02:03.982872 [Flow] Enable top DCM control <<<<<
2274 10:02:03.985572 Enable DLL master slave shuffle
2275 10:02:03.989132 ==============================================================
2276 10:02:03.992369 Gating Mode config
2277 10:02:03.996194 ==============================================================
2278 10:02:03.999121 Config description:
2279 10:02:04.008763 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2280 10:02:04.015711 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2281 10:02:04.018750 SELPH_MODE 0: By rank 1: By Phase
2282 10:02:04.025517 ==============================================================
2283 10:02:04.028911 GAT_TRACK_EN = 1
2284 10:02:04.032361 RX_GATING_MODE = 2
2285 10:02:04.035117 RX_GATING_TRACK_MODE = 2
2286 10:02:04.038773 SELPH_MODE = 1
2287 10:02:04.041840 PICG_EARLY_EN = 1
2288 10:02:04.045274 VALID_LAT_VALUE = 1
2289 10:02:04.048693 ==============================================================
2290 10:02:04.051861 Enter into Gating configuration >>>>
2291 10:02:04.055413 Exit from Gating configuration <<<<
2292 10:02:04.058415 Enter into DVFS_PRE_config >>>>>
2293 10:02:04.071600 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2294 10:02:04.071686 Exit from DVFS_PRE_config <<<<<
2295 10:02:04.075095 Enter into PICG configuration >>>>
2296 10:02:04.078195 Exit from PICG configuration <<<<
2297 10:02:04.081396 [RX_INPUT] configuration >>>>>
2298 10:02:04.084674 [RX_INPUT] configuration <<<<<
2299 10:02:04.091564 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2300 10:02:04.094766 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2301 10:02:04.101988 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2302 10:02:04.108005 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2303 10:02:04.115102 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2304 10:02:04.121197 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2305 10:02:04.124847 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2306 10:02:04.128314 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2307 10:02:04.131202 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2308 10:02:04.138108 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2309 10:02:04.141239 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2310 10:02:04.144768 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2311 10:02:04.147615 ===================================
2312 10:02:04.151176 LPDDR4 DRAM CONFIGURATION
2313 10:02:04.154735 ===================================
2314 10:02:04.154833 EX_ROW_EN[0] = 0x0
2315 10:02:04.157917 EX_ROW_EN[1] = 0x0
2316 10:02:04.161221 LP4Y_EN = 0x0
2317 10:02:04.161294 WORK_FSP = 0x0
2318 10:02:04.164359 WL = 0x4
2319 10:02:04.164454 RL = 0x4
2320 10:02:04.168292 BL = 0x2
2321 10:02:04.168393 RPST = 0x0
2322 10:02:04.171623 RD_PRE = 0x0
2323 10:02:04.171700 WR_PRE = 0x1
2324 10:02:04.174947 WR_PST = 0x0
2325 10:02:04.175069 DBI_WR = 0x0
2326 10:02:04.177923 DBI_RD = 0x0
2327 10:02:04.178020 OTF = 0x1
2328 10:02:04.181213 ===================================
2329 10:02:04.184373 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2330 10:02:04.191101 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2331 10:02:04.194754 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2332 10:02:04.198038 ===================================
2333 10:02:04.201369 LPDDR4 DRAM CONFIGURATION
2334 10:02:04.204235 ===================================
2335 10:02:04.204317 EX_ROW_EN[0] = 0x10
2336 10:02:04.207789 EX_ROW_EN[1] = 0x0
2337 10:02:04.210994 LP4Y_EN = 0x0
2338 10:02:04.211074 WORK_FSP = 0x0
2339 10:02:04.214414 WL = 0x4
2340 10:02:04.214496 RL = 0x4
2341 10:02:04.217508 BL = 0x2
2342 10:02:04.217590 RPST = 0x0
2343 10:02:04.220833 RD_PRE = 0x0
2344 10:02:04.220915 WR_PRE = 0x1
2345 10:02:04.224067 WR_PST = 0x0
2346 10:02:04.224147 DBI_WR = 0x0
2347 10:02:04.227802 DBI_RD = 0x0
2348 10:02:04.227883 OTF = 0x1
2349 10:02:04.230966 ===================================
2350 10:02:04.237313 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2351 10:02:04.237394 ==
2352 10:02:04.240691 Dram Type= 6, Freq= 0, CH_0, rank 0
2353 10:02:04.243976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2354 10:02:04.244056 ==
2355 10:02:04.247606 [Duty_Offset_Calibration]
2356 10:02:04.251170 B0:1 B1:-1 CA:0
2357 10:02:04.251250
2358 10:02:04.254199 [DutyScan_Calibration_Flow] k_type=0
2359 10:02:04.262338
2360 10:02:04.262418 ==CLK 0==
2361 10:02:04.265397 Final CLK duty delay cell = 0
2362 10:02:04.268931 [0] MAX Duty = 5125%(X100), DQS PI = 24
2363 10:02:04.272542 [0] MIN Duty = 4907%(X100), DQS PI = 8
2364 10:02:04.272637 [0] AVG Duty = 5016%(X100)
2365 10:02:04.275790
2366 10:02:04.278855 CH0 CLK Duty spec in!! Max-Min= 218%
2367 10:02:04.282314 [DutyScan_Calibration_Flow] ====Done====
2368 10:02:04.282394
2369 10:02:04.285425 [DutyScan_Calibration_Flow] k_type=1
2370 10:02:04.300494
2371 10:02:04.300596 ==DQS 0 ==
2372 10:02:04.303446 Final DQS duty delay cell = -4
2373 10:02:04.306602 [-4] MAX Duty = 5062%(X100), DQS PI = 18
2374 10:02:04.310416 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2375 10:02:04.313575 [-4] AVG Duty = 4968%(X100)
2376 10:02:04.313657
2377 10:02:04.313721 ==DQS 1 ==
2378 10:02:04.316533 Final DQS duty delay cell = -4
2379 10:02:04.319996 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2380 10:02:04.322960 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2381 10:02:04.326735 [-4] AVG Duty = 4938%(X100)
2382 10:02:04.326816
2383 10:02:04.329799 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2384 10:02:04.329880
2385 10:02:04.333127 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2386 10:02:04.336280 [DutyScan_Calibration_Flow] ====Done====
2387 10:02:04.336360
2388 10:02:04.339982 [DutyScan_Calibration_Flow] k_type=3
2389 10:02:04.357964
2390 10:02:04.358078 ==DQM 0 ==
2391 10:02:04.361871 Final DQM duty delay cell = 0
2392 10:02:04.364444 [0] MAX Duty = 5062%(X100), DQS PI = 18
2393 10:02:04.367788 [0] MIN Duty = 4875%(X100), DQS PI = 6
2394 10:02:04.371006 [0] AVG Duty = 4968%(X100)
2395 10:02:04.371087
2396 10:02:04.371151 ==DQM 1 ==
2397 10:02:04.374548 Final DQM duty delay cell = 4
2398 10:02:04.378031 [4] MAX Duty = 5187%(X100), DQS PI = 16
2399 10:02:04.381022 [4] MIN Duty = 4969%(X100), DQS PI = 24
2400 10:02:04.384402 [4] AVG Duty = 5078%(X100)
2401 10:02:04.384486
2402 10:02:04.387977 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2403 10:02:04.388060
2404 10:02:04.391065 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2405 10:02:04.394633 [DutyScan_Calibration_Flow] ====Done====
2406 10:02:04.394717
2407 10:02:04.397494 [DutyScan_Calibration_Flow] k_type=2
2408 10:02:04.412627
2409 10:02:04.412710 ==DQ 0 ==
2410 10:02:04.416058 Final DQ duty delay cell = -4
2411 10:02:04.419513 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2412 10:02:04.423068 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2413 10:02:04.426634 [-4] AVG Duty = 4969%(X100)
2414 10:02:04.426717
2415 10:02:04.426782 ==DQ 1 ==
2416 10:02:04.429743 Final DQ duty delay cell = -4
2417 10:02:04.432958 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2418 10:02:04.436169 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2419 10:02:04.439292 [-4] AVG Duty = 4922%(X100)
2420 10:02:04.439375
2421 10:02:04.443060 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2422 10:02:04.443143
2423 10:02:04.446099 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2424 10:02:04.449349 [DutyScan_Calibration_Flow] ====Done====
2425 10:02:04.449432 ==
2426 10:02:04.453280 Dram Type= 6, Freq= 0, CH_1, rank 0
2427 10:02:04.455970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2428 10:02:04.456054 ==
2429 10:02:04.459075 [Duty_Offset_Calibration]
2430 10:02:04.459161 B0:-1 B1:1 CA:1
2431 10:02:04.462800
2432 10:02:04.465510 [DutyScan_Calibration_Flow] k_type=0
2433 10:02:04.473656
2434 10:02:04.473738 ==CLK 0==
2435 10:02:04.477135 Final CLK duty delay cell = 0
2436 10:02:04.480003 [0] MAX Duty = 5187%(X100), DQS PI = 22
2437 10:02:04.483846 [0] MIN Duty = 5000%(X100), DQS PI = 0
2438 10:02:04.483929 [0] AVG Duty = 5093%(X100)
2439 10:02:04.483995
2440 10:02:04.487071 CH1 CLK Duty spec in!! Max-Min= 187%
2441 10:02:04.493424 [DutyScan_Calibration_Flow] ====Done====
2442 10:02:04.493524
2443 10:02:04.497084 [DutyScan_Calibration_Flow] k_type=1
2444 10:02:04.512867
2445 10:02:04.512979 ==DQS 0 ==
2446 10:02:04.516074 Final DQS duty delay cell = 0
2447 10:02:04.519255 [0] MAX Duty = 5156%(X100), DQS PI = 48
2448 10:02:04.522986 [0] MIN Duty = 4907%(X100), DQS PI = 8
2449 10:02:04.523069 [0] AVG Duty = 5031%(X100)
2450 10:02:04.526246
2451 10:02:04.526329 ==DQS 1 ==
2452 10:02:04.529084 Final DQS duty delay cell = 0
2453 10:02:04.532553 [0] MAX Duty = 5062%(X100), DQS PI = 10
2454 10:02:04.535774 [0] MIN Duty = 4969%(X100), DQS PI = 56
2455 10:02:04.539382 [0] AVG Duty = 5015%(X100)
2456 10:02:04.539465
2457 10:02:04.542385 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2458 10:02:04.542468
2459 10:02:04.546105 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2460 10:02:04.549358 [DutyScan_Calibration_Flow] ====Done====
2461 10:02:04.549474
2462 10:02:04.552705 [DutyScan_Calibration_Flow] k_type=3
2463 10:02:04.568539
2464 10:02:04.568638 ==DQM 0 ==
2465 10:02:04.571582 Final DQM duty delay cell = -4
2466 10:02:04.575177 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2467 10:02:04.578525 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2468 10:02:04.581511 [-4] AVG Duty = 4969%(X100)
2469 10:02:04.581595
2470 10:02:04.581660 ==DQM 1 ==
2471 10:02:04.584669 Final DQM duty delay cell = 0
2472 10:02:04.587880 [0] MAX Duty = 5187%(X100), DQS PI = 6
2473 10:02:04.591092 [0] MIN Duty = 5000%(X100), DQS PI = 28
2474 10:02:04.594621 [0] AVG Duty = 5093%(X100)
2475 10:02:04.594704
2476 10:02:04.597892 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2477 10:02:04.597975
2478 10:02:04.601405 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2479 10:02:04.604458 [DutyScan_Calibration_Flow] ====Done====
2480 10:02:04.604547
2481 10:02:04.607870 [DutyScan_Calibration_Flow] k_type=2
2482 10:02:04.625066
2483 10:02:04.625149 ==DQ 0 ==
2484 10:02:04.628094 Final DQ duty delay cell = 0
2485 10:02:04.631999 [0] MAX Duty = 5187%(X100), DQS PI = 30
2486 10:02:04.634683 [0] MIN Duty = 4907%(X100), DQS PI = 8
2487 10:02:04.634768 [0] AVG Duty = 5047%(X100)
2488 10:02:04.638475
2489 10:02:04.638557 ==DQ 1 ==
2490 10:02:04.641541 Final DQ duty delay cell = 0
2491 10:02:04.644845 [0] MAX Duty = 5124%(X100), DQS PI = 10
2492 10:02:04.648113 [0] MIN Duty = 4938%(X100), DQS PI = 62
2493 10:02:04.648197 [0] AVG Duty = 5031%(X100)
2494 10:02:04.648261
2495 10:02:04.651663 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2496 10:02:04.654632
2497 10:02:04.658170 CH1 DQ 1 Duty spec in!! Max-Min= 186%
2498 10:02:04.661594 [DutyScan_Calibration_Flow] ====Done====
2499 10:02:04.664846 nWR fixed to 30
2500 10:02:04.664930 [ModeRegInit_LP4] CH0 RK0
2501 10:02:04.668302 [ModeRegInit_LP4] CH0 RK1
2502 10:02:04.671327 [ModeRegInit_LP4] CH1 RK0
2503 10:02:04.674769 [ModeRegInit_LP4] CH1 RK1
2504 10:02:04.674851 match AC timing 7
2505 10:02:04.678684 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2506 10:02:04.684867 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2507 10:02:04.688030 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2508 10:02:04.694455 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2509 10:02:04.698036 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2510 10:02:04.698119 ==
2511 10:02:04.701314 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 10:02:04.704510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 10:02:04.704599 ==
2514 10:02:04.711339 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2515 10:02:04.718084 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2516 10:02:04.725097 [CA 0] Center 39 (9~70) winsize 62
2517 10:02:04.728518 [CA 1] Center 39 (9~70) winsize 62
2518 10:02:04.731839 [CA 2] Center 35 (5~66) winsize 62
2519 10:02:04.734879 [CA 3] Center 35 (5~66) winsize 62
2520 10:02:04.738297 [CA 4] Center 34 (4~64) winsize 61
2521 10:02:04.741359 [CA 5] Center 33 (4~63) winsize 60
2522 10:02:04.741441
2523 10:02:04.745007 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2524 10:02:04.745089
2525 10:02:04.748294 [CATrainingPosCal] consider 1 rank data
2526 10:02:04.751344 u2DelayCellTimex100 = 270/100 ps
2527 10:02:04.755101 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2528 10:02:04.761705 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2529 10:02:04.764851 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2530 10:02:04.767982 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2531 10:02:04.771519 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2532 10:02:04.774900 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2533 10:02:04.774981
2534 10:02:04.778767 CA PerBit enable=1, Macro0, CA PI delay=33
2535 10:02:04.778840
2536 10:02:04.782163 [CBTSetCACLKResult] CA Dly = 33
2537 10:02:04.782244 CS Dly: 8 (0~39)
2538 10:02:04.784601 ==
2539 10:02:04.788084 Dram Type= 6, Freq= 0, CH_0, rank 1
2540 10:02:04.791564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2541 10:02:04.791655 ==
2542 10:02:04.794742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2543 10:02:04.801203 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2544 10:02:04.810933 [CA 0] Center 39 (8~70) winsize 63
2545 10:02:04.814542 [CA 1] Center 39 (9~70) winsize 62
2546 10:02:04.817545 [CA 2] Center 35 (5~66) winsize 62
2547 10:02:04.820823 [CA 3] Center 34 (4~65) winsize 62
2548 10:02:04.823834 [CA 4] Center 33 (3~64) winsize 62
2549 10:02:04.827311 [CA 5] Center 33 (3~63) winsize 61
2550 10:02:04.827392
2551 10:02:04.830922 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2552 10:02:04.831004
2553 10:02:04.834226 [CATrainingPosCal] consider 2 rank data
2554 10:02:04.837588 u2DelayCellTimex100 = 270/100 ps
2555 10:02:04.840840 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2556 10:02:04.847272 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2557 10:02:04.850586 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2558 10:02:04.853698 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2559 10:02:04.857611 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2560 10:02:04.860398 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2561 10:02:04.860482
2562 10:02:04.864349 CA PerBit enable=1, Macro0, CA PI delay=33
2563 10:02:04.864433
2564 10:02:04.867320 [CBTSetCACLKResult] CA Dly = 33
2565 10:02:04.867404 CS Dly: 9 (0~41)
2566 10:02:04.867470
2567 10:02:04.873791 ----->DramcWriteLeveling(PI) begin...
2568 10:02:04.873875 ==
2569 10:02:04.876942 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 10:02:04.880695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 10:02:04.880780 ==
2572 10:02:04.884343 Write leveling (Byte 0): 33 => 33
2573 10:02:04.887163 Write leveling (Byte 1): 29 => 29
2574 10:02:04.890515 DramcWriteLeveling(PI) end<-----
2575 10:02:04.890590
2576 10:02:04.890669 ==
2577 10:02:04.893677 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 10:02:04.897410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 10:02:04.897490 ==
2580 10:02:04.900406 [Gating] SW mode calibration
2581 10:02:04.907299 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2582 10:02:04.913440 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2583 10:02:04.916946 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2584 10:02:04.920415 0 15 4 | B1->B0 | 2b2a 3434 | 1 1 | (0 0) (1 1)
2585 10:02:04.926630 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 10:02:04.930275 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 10:02:04.933519 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 10:02:04.936800 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 10:02:04.943995 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 10:02:04.946744 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
2591 10:02:04.949925 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
2592 10:02:04.956777 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 10:02:04.960428 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 10:02:04.963443 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 10:02:04.970282 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 10:02:04.973561 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 10:02:04.976717 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 10:02:04.983692 1 0 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (1 1)
2599 10:02:04.986781 1 1 0 | B1->B0 | 2727 4545 | 0 0 | (0 0) (0 0)
2600 10:02:04.990541 1 1 4 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
2601 10:02:04.996618 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 10:02:05.000083 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 10:02:05.003506 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 10:02:05.009904 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 10:02:05.013380 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2606 10:02:05.016729 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2607 10:02:05.023669 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2608 10:02:05.026455 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 10:02:05.029689 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 10:02:05.036552 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 10:02:05.040074 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 10:02:05.043069 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 10:02:05.049905 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 10:02:05.053219 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 10:02:05.056867 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 10:02:05.063196 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 10:02:05.066500 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 10:02:05.069522 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 10:02:05.076311 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 10:02:05.079820 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 10:02:05.083526 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2622 10:02:05.089955 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2623 10:02:05.093067 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2624 10:02:05.096241 Total UI for P1: 0, mck2ui 16
2625 10:02:05.099385 best dqsien dly found for B0: ( 1, 3, 26)
2626 10:02:05.103038 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 10:02:05.105885 Total UI for P1: 0, mck2ui 16
2628 10:02:05.109150 best dqsien dly found for B1: ( 1, 4, 0)
2629 10:02:05.112771 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2630 10:02:05.116248 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2631 10:02:05.116332
2632 10:02:05.119053 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2633 10:02:05.125811 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2634 10:02:05.125895 [Gating] SW calibration Done
2635 10:02:05.125961 ==
2636 10:02:05.129118 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 10:02:05.135797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 10:02:05.135881 ==
2639 10:02:05.135947 RX Vref Scan: 0
2640 10:02:05.136009
2641 10:02:05.138997 RX Vref 0 -> 0, step: 1
2642 10:02:05.139080
2643 10:02:05.142315 RX Delay -40 -> 252, step: 8
2644 10:02:05.145678 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2645 10:02:05.149306 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2646 10:02:05.152982 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2647 10:02:05.156124 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2648 10:02:05.162608 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2649 10:02:05.166282 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2650 10:02:05.169421 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2651 10:02:05.172445 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2652 10:02:05.176139 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2653 10:02:05.182636 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2654 10:02:05.185794 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2655 10:02:05.189354 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2656 10:02:05.192759 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2657 10:02:05.195619 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2658 10:02:05.202416 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2659 10:02:05.205946 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2660 10:02:05.206030 ==
2661 10:02:05.209381 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 10:02:05.212340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 10:02:05.212424 ==
2664 10:02:05.216013 DQS Delay:
2665 10:02:05.216096 DQS0 = 0, DQS1 = 0
2666 10:02:05.216163 DQM Delay:
2667 10:02:05.219194 DQM0 = 119, DQM1 = 106
2668 10:02:05.219278 DQ Delay:
2669 10:02:05.222233 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2670 10:02:05.226015 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2671 10:02:05.232305 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2672 10:02:05.235438 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2673 10:02:05.235522
2674 10:02:05.235588
2675 10:02:05.235649 ==
2676 10:02:05.239087 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 10:02:05.242315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 10:02:05.242400 ==
2679 10:02:05.242472
2680 10:02:05.242535
2681 10:02:05.245443 TX Vref Scan disable
2682 10:02:05.245526 == TX Byte 0 ==
2683 10:02:05.252408 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2684 10:02:05.255513 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2685 10:02:05.255598 == TX Byte 1 ==
2686 10:02:05.261929 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2687 10:02:05.265052 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2688 10:02:05.265138 ==
2689 10:02:05.268424 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 10:02:05.271686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 10:02:05.271771 ==
2692 10:02:05.284827 TX Vref=22, minBit 1, minWin=25, winSum=413
2693 10:02:05.288459 TX Vref=24, minBit 13, minWin=25, winSum=423
2694 10:02:05.292135 TX Vref=26, minBit 14, minWin=25, winSum=427
2695 10:02:05.294948 TX Vref=28, minBit 4, minWin=26, winSum=430
2696 10:02:05.298222 TX Vref=30, minBit 5, minWin=26, winSum=434
2697 10:02:05.304725 TX Vref=32, minBit 4, minWin=26, winSum=431
2698 10:02:05.308189 [TxChooseVref] Worse bit 5, Min win 26, Win sum 434, Final Vref 30
2699 10:02:05.308274
2700 10:02:05.311456 Final TX Range 1 Vref 30
2701 10:02:05.311540
2702 10:02:05.311606 ==
2703 10:02:05.314768 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 10:02:05.322032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 10:02:05.322117 ==
2706 10:02:05.322183
2707 10:02:05.322244
2708 10:02:05.322327 TX Vref Scan disable
2709 10:02:05.325204 == TX Byte 0 ==
2710 10:02:05.329044 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2711 10:02:05.335340 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2712 10:02:05.335423 == TX Byte 1 ==
2713 10:02:05.338592 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2714 10:02:05.344853 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2715 10:02:05.344937
2716 10:02:05.345003 [DATLAT]
2717 10:02:05.345065 Freq=1200, CH0 RK0
2718 10:02:05.345124
2719 10:02:05.348031 DATLAT Default: 0xd
2720 10:02:05.351364 0, 0xFFFF, sum = 0
2721 10:02:05.351448 1, 0xFFFF, sum = 0
2722 10:02:05.354750 2, 0xFFFF, sum = 0
2723 10:02:05.354847 3, 0xFFFF, sum = 0
2724 10:02:05.358061 4, 0xFFFF, sum = 0
2725 10:02:05.358145 5, 0xFFFF, sum = 0
2726 10:02:05.361499 6, 0xFFFF, sum = 0
2727 10:02:05.361584 7, 0xFFFF, sum = 0
2728 10:02:05.364664 8, 0xFFFF, sum = 0
2729 10:02:05.364749 9, 0xFFFF, sum = 0
2730 10:02:05.368120 10, 0xFFFF, sum = 0
2731 10:02:05.368204 11, 0xFFFF, sum = 0
2732 10:02:05.371147 12, 0x0, sum = 1
2733 10:02:05.371232 13, 0x0, sum = 2
2734 10:02:05.374878 14, 0x0, sum = 3
2735 10:02:05.374963 15, 0x0, sum = 4
2736 10:02:05.377736 best_step = 13
2737 10:02:05.377819
2738 10:02:05.377884 ==
2739 10:02:05.381023 Dram Type= 6, Freq= 0, CH_0, rank 0
2740 10:02:05.384423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2741 10:02:05.384545 ==
2742 10:02:05.387543 RX Vref Scan: 1
2743 10:02:05.387626
2744 10:02:05.387692 Set Vref Range= 32 -> 127
2745 10:02:05.387752
2746 10:02:05.391408 RX Vref 32 -> 127, step: 1
2747 10:02:05.391492
2748 10:02:05.394033 RX Delay -21 -> 252, step: 4
2749 10:02:05.394117
2750 10:02:05.397479 Set Vref, RX VrefLevel [Byte0]: 32
2751 10:02:05.401057 [Byte1]: 32
2752 10:02:05.401141
2753 10:02:05.404104 Set Vref, RX VrefLevel [Byte0]: 33
2754 10:02:05.407660 [Byte1]: 33
2755 10:02:05.411672
2756 10:02:05.411754 Set Vref, RX VrefLevel [Byte0]: 34
2757 10:02:05.415962 [Byte1]: 34
2758 10:02:05.419353
2759 10:02:05.419436 Set Vref, RX VrefLevel [Byte0]: 35
2760 10:02:05.422811 [Byte1]: 35
2761 10:02:05.427383
2762 10:02:05.427466 Set Vref, RX VrefLevel [Byte0]: 36
2763 10:02:05.430654 [Byte1]: 36
2764 10:02:05.435585
2765 10:02:05.435668 Set Vref, RX VrefLevel [Byte0]: 37
2766 10:02:05.438463 [Byte1]: 37
2767 10:02:05.443365
2768 10:02:05.443448 Set Vref, RX VrefLevel [Byte0]: 38
2769 10:02:05.446511 [Byte1]: 38
2770 10:02:05.451353
2771 10:02:05.451436 Set Vref, RX VrefLevel [Byte0]: 39
2772 10:02:05.454431 [Byte1]: 39
2773 10:02:05.459011
2774 10:02:05.459094 Set Vref, RX VrefLevel [Byte0]: 40
2775 10:02:05.462444 [Byte1]: 40
2776 10:02:05.467146
2777 10:02:05.467230 Set Vref, RX VrefLevel [Byte0]: 41
2778 10:02:05.470831 [Byte1]: 41
2779 10:02:05.474984
2780 10:02:05.475067 Set Vref, RX VrefLevel [Byte0]: 42
2781 10:02:05.478095 [Byte1]: 42
2782 10:02:05.482840
2783 10:02:05.482923 Set Vref, RX VrefLevel [Byte0]: 43
2784 10:02:05.486188 [Byte1]: 43
2785 10:02:05.490954
2786 10:02:05.491037 Set Vref, RX VrefLevel [Byte0]: 44
2787 10:02:05.494320 [Byte1]: 44
2788 10:02:05.499159
2789 10:02:05.499242 Set Vref, RX VrefLevel [Byte0]: 45
2790 10:02:05.502294 [Byte1]: 45
2791 10:02:05.506701
2792 10:02:05.506784 Set Vref, RX VrefLevel [Byte0]: 46
2793 10:02:05.509978 [Byte1]: 46
2794 10:02:05.514927
2795 10:02:05.515009 Set Vref, RX VrefLevel [Byte0]: 47
2796 10:02:05.518702 [Byte1]: 47
2797 10:02:05.522463
2798 10:02:05.522550 Set Vref, RX VrefLevel [Byte0]: 48
2799 10:02:05.526146 [Byte1]: 48
2800 10:02:05.530350
2801 10:02:05.530433 Set Vref, RX VrefLevel [Byte0]: 49
2802 10:02:05.534035 [Byte1]: 49
2803 10:02:05.538615
2804 10:02:05.538698 Set Vref, RX VrefLevel [Byte0]: 50
2805 10:02:05.541567 [Byte1]: 50
2806 10:02:05.546415
2807 10:02:05.550139 Set Vref, RX VrefLevel [Byte0]: 51
2808 10:02:05.552667 [Byte1]: 51
2809 10:02:05.552750
2810 10:02:05.555864 Set Vref, RX VrefLevel [Byte0]: 52
2811 10:02:05.559632 [Byte1]: 52
2812 10:02:05.559715
2813 10:02:05.562816 Set Vref, RX VrefLevel [Byte0]: 53
2814 10:02:05.566165 [Byte1]: 53
2815 10:02:05.569950
2816 10:02:05.570033 Set Vref, RX VrefLevel [Byte0]: 54
2817 10:02:05.573595 [Byte1]: 54
2818 10:02:05.577863
2819 10:02:05.577946 Set Vref, RX VrefLevel [Byte0]: 55
2820 10:02:05.581315 [Byte1]: 55
2821 10:02:05.585933
2822 10:02:05.586015 Set Vref, RX VrefLevel [Byte0]: 56
2823 10:02:05.589199 [Byte1]: 56
2824 10:02:05.593914
2825 10:02:05.593997 Set Vref, RX VrefLevel [Byte0]: 57
2826 10:02:05.597464 [Byte1]: 57
2827 10:02:05.602265
2828 10:02:05.602348 Set Vref, RX VrefLevel [Byte0]: 58
2829 10:02:05.605245 [Byte1]: 58
2830 10:02:05.609737
2831 10:02:05.609820 Set Vref, RX VrefLevel [Byte0]: 59
2832 10:02:05.613136 [Byte1]: 59
2833 10:02:05.617963
2834 10:02:05.618046 Set Vref, RX VrefLevel [Byte0]: 60
2835 10:02:05.621599 [Byte1]: 60
2836 10:02:05.625872
2837 10:02:05.625954 Set Vref, RX VrefLevel [Byte0]: 61
2838 10:02:05.629280 [Byte1]: 61
2839 10:02:05.633608
2840 10:02:05.633691 Set Vref, RX VrefLevel [Byte0]: 62
2841 10:02:05.636973 [Byte1]: 62
2842 10:02:05.641280
2843 10:02:05.641363 Set Vref, RX VrefLevel [Byte0]: 63
2844 10:02:05.644712 [Byte1]: 63
2845 10:02:05.649385
2846 10:02:05.649467 Set Vref, RX VrefLevel [Byte0]: 64
2847 10:02:05.652405 [Byte1]: 64
2848 10:02:05.657528
2849 10:02:05.657624 Set Vref, RX VrefLevel [Byte0]: 65
2850 10:02:05.660520 [Byte1]: 65
2851 10:02:05.665615
2852 10:02:05.665697 Set Vref, RX VrefLevel [Byte0]: 66
2853 10:02:05.668769 [Byte1]: 66
2854 10:02:05.672990
2855 10:02:05.673072 Set Vref, RX VrefLevel [Byte0]: 67
2856 10:02:05.676624 [Byte1]: 67
2857 10:02:05.680966
2858 10:02:05.681049 Set Vref, RX VrefLevel [Byte0]: 68
2859 10:02:05.684084 [Byte1]: 68
2860 10:02:05.689359
2861 10:02:05.689441 Set Vref, RX VrefLevel [Byte0]: 69
2862 10:02:05.692374 [Byte1]: 69
2863 10:02:05.697269
2864 10:02:05.697351 Set Vref, RX VrefLevel [Byte0]: 70
2865 10:02:05.700433 [Byte1]: 70
2866 10:02:05.705138
2867 10:02:05.705219 Set Vref, RX VrefLevel [Byte0]: 71
2868 10:02:05.708103 [Byte1]: 71
2869 10:02:05.713255
2870 10:02:05.713337 Set Vref, RX VrefLevel [Byte0]: 72
2871 10:02:05.716372 [Byte1]: 72
2872 10:02:05.721035
2873 10:02:05.721117 Set Vref, RX VrefLevel [Byte0]: 73
2874 10:02:05.724784 [Byte1]: 73
2875 10:02:05.729085
2876 10:02:05.729167 Set Vref, RX VrefLevel [Byte0]: 74
2877 10:02:05.731916 [Byte1]: 74
2878 10:02:05.736734
2879 10:02:05.736818 Set Vref, RX VrefLevel [Byte0]: 75
2880 10:02:05.739911 [Byte1]: 75
2881 10:02:05.744371
2882 10:02:05.747662 Set Vref, RX VrefLevel [Byte0]: 76
2883 10:02:05.751374 [Byte1]: 76
2884 10:02:05.751456
2885 10:02:05.754762 Final RX Vref Byte 0 = 61 to rank0
2886 10:02:05.757987 Final RX Vref Byte 1 = 49 to rank0
2887 10:02:05.760816 Final RX Vref Byte 0 = 61 to rank1
2888 10:02:05.764610 Final RX Vref Byte 1 = 49 to rank1==
2889 10:02:05.767637 Dram Type= 6, Freq= 0, CH_0, rank 0
2890 10:02:05.771313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 10:02:05.771397 ==
2892 10:02:05.771463 DQS Delay:
2893 10:02:05.774159 DQS0 = 0, DQS1 = 0
2894 10:02:05.774241 DQM Delay:
2895 10:02:05.777732 DQM0 = 119, DQM1 = 106
2896 10:02:05.777816 DQ Delay:
2897 10:02:05.780752 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2898 10:02:05.784339 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
2899 10:02:05.787585 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
2900 10:02:05.791314 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =116
2901 10:02:05.791398
2902 10:02:05.791463
2903 10:02:05.800826 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 403 ps
2904 10:02:05.804505 CH0 RK0: MR19=403, MR18=12FE
2905 10:02:05.811022 CH0_RK0: MR19=0x403, MR18=0x12FE, DQSOSC=403, MR23=63, INC=40, DEC=26
2906 10:02:05.811106
2907 10:02:05.814215 ----->DramcWriteLeveling(PI) begin...
2908 10:02:05.814299 ==
2909 10:02:05.817781 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 10:02:05.821058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 10:02:05.821142 ==
2912 10:02:05.824172 Write leveling (Byte 0): 33 => 33
2913 10:02:05.827561 Write leveling (Byte 1): 29 => 29
2914 10:02:05.830759 DramcWriteLeveling(PI) end<-----
2915 10:02:05.830841
2916 10:02:05.830906 ==
2917 10:02:05.833844 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 10:02:05.837665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 10:02:05.837749 ==
2920 10:02:05.840906 [Gating] SW mode calibration
2921 10:02:05.847455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2922 10:02:05.854769 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2923 10:02:05.857317 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2924 10:02:05.861149 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2925 10:02:05.867389 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 10:02:05.870947 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 10:02:05.874141 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 10:02:05.880729 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 10:02:05.884419 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2930 10:02:05.887835 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
2931 10:02:05.894090 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
2932 10:02:05.897734 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2933 10:02:05.900907 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 10:02:05.904214 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 10:02:05.910948 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 10:02:05.914031 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 10:02:05.917252 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 10:02:05.924285 1 0 28 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
2939 10:02:05.927429 1 1 0 | B1->B0 | 3131 4343 | 0 0 | (0 0) (0 0)
2940 10:02:05.931002 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 10:02:05.937338 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 10:02:05.940477 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 10:02:05.944652 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 10:02:05.950829 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 10:02:05.954135 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 10:02:05.957521 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2947 10:02:05.963646 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2948 10:02:05.967067 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 10:02:05.970352 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 10:02:05.976929 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 10:02:05.980441 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 10:02:05.983795 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 10:02:05.990311 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 10:02:05.994030 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 10:02:05.997242 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 10:02:06.003575 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 10:02:06.007437 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 10:02:06.010578 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 10:02:06.017160 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 10:02:06.020405 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 10:02:06.023588 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2962 10:02:06.030014 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2963 10:02:06.033637 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2964 10:02:06.036796 Total UI for P1: 0, mck2ui 16
2965 10:02:06.040113 best dqsien dly found for B0: ( 1, 3, 26)
2966 10:02:06.043454 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 10:02:06.046923 Total UI for P1: 0, mck2ui 16
2968 10:02:06.050150 best dqsien dly found for B1: ( 1, 4, 0)
2969 10:02:06.054449 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2970 10:02:06.056927 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2971 10:02:06.057009
2972 10:02:06.059984 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2973 10:02:06.063748 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2974 10:02:06.066505 [Gating] SW calibration Done
2975 10:02:06.066588 ==
2976 10:02:06.069903 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 10:02:06.076500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 10:02:06.076623 ==
2979 10:02:06.076688 RX Vref Scan: 0
2980 10:02:06.076750
2981 10:02:06.080082 RX Vref 0 -> 0, step: 1
2982 10:02:06.080164
2983 10:02:06.083581 RX Delay -40 -> 252, step: 8
2984 10:02:06.086697 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2985 10:02:06.089990 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2986 10:02:06.093249 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2987 10:02:06.099846 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2988 10:02:06.103441 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2989 10:02:06.106974 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2990 10:02:06.110308 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2991 10:02:06.113032 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2992 10:02:06.116693 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2993 10:02:06.122908 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2994 10:02:06.127388 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2995 10:02:06.129760 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2996 10:02:06.133520 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2997 10:02:06.136492 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2998 10:02:06.143377 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2999 10:02:06.146124 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3000 10:02:06.146207 ==
3001 10:02:06.149565 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 10:02:06.152725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 10:02:06.152809 ==
3004 10:02:06.156340 DQS Delay:
3005 10:02:06.156449 DQS0 = 0, DQS1 = 0
3006 10:02:06.156565 DQM Delay:
3007 10:02:06.159380 DQM0 = 116, DQM1 = 108
3008 10:02:06.159465 DQ Delay:
3009 10:02:06.162950 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
3010 10:02:06.166467 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3011 10:02:06.173353 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3012 10:02:06.175970 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3013 10:02:06.176052
3014 10:02:06.176116
3015 10:02:06.176176 ==
3016 10:02:06.179612 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 10:02:06.182599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 10:02:06.182683 ==
3019 10:02:06.182748
3020 10:02:06.182808
3021 10:02:06.185925 TX Vref Scan disable
3022 10:02:06.189358 == TX Byte 0 ==
3023 10:02:06.192688 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3024 10:02:06.195843 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3025 10:02:06.199211 == TX Byte 1 ==
3026 10:02:06.202799 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3027 10:02:06.206010 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3028 10:02:06.206093 ==
3029 10:02:06.209391 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 10:02:06.212652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 10:02:06.212735 ==
3032 10:02:06.226196 TX Vref=22, minBit 1, minWin=25, winSum=415
3033 10:02:06.229417 TX Vref=24, minBit 5, minWin=25, winSum=422
3034 10:02:06.232913 TX Vref=26, minBit 1, minWin=26, winSum=427
3035 10:02:06.235919 TX Vref=28, minBit 1, minWin=26, winSum=429
3036 10:02:06.239185 TX Vref=30, minBit 10, minWin=26, winSum=430
3037 10:02:06.245999 TX Vref=32, minBit 10, minWin=25, winSum=426
3038 10:02:06.249098 [TxChooseVref] Worse bit 10, Min win 26, Win sum 430, Final Vref 30
3039 10:02:06.249181
3040 10:02:06.253167 Final TX Range 1 Vref 30
3041 10:02:06.253251
3042 10:02:06.253315 ==
3043 10:02:06.256032 Dram Type= 6, Freq= 0, CH_0, rank 1
3044 10:02:06.259585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 10:02:06.259669 ==
3046 10:02:06.262486
3047 10:02:06.262569
3048 10:02:06.262633 TX Vref Scan disable
3049 10:02:06.266435 == TX Byte 0 ==
3050 10:02:06.269128 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3051 10:02:06.275814 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3052 10:02:06.275924 == TX Byte 1 ==
3053 10:02:06.279029 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3054 10:02:06.286195 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3055 10:02:06.286271
3056 10:02:06.286335 [DATLAT]
3057 10:02:06.286397 Freq=1200, CH0 RK1
3058 10:02:06.286457
3059 10:02:06.289532 DATLAT Default: 0xd
3060 10:02:06.292427 0, 0xFFFF, sum = 0
3061 10:02:06.292562 1, 0xFFFF, sum = 0
3062 10:02:06.295883 2, 0xFFFF, sum = 0
3063 10:02:06.295953 3, 0xFFFF, sum = 0
3064 10:02:06.299538 4, 0xFFFF, sum = 0
3065 10:02:06.299638 5, 0xFFFF, sum = 0
3066 10:02:06.302381 6, 0xFFFF, sum = 0
3067 10:02:06.302452 7, 0xFFFF, sum = 0
3068 10:02:06.305611 8, 0xFFFF, sum = 0
3069 10:02:06.305683 9, 0xFFFF, sum = 0
3070 10:02:06.308994 10, 0xFFFF, sum = 0
3071 10:02:06.309069 11, 0xFFFF, sum = 0
3072 10:02:06.312321 12, 0x0, sum = 1
3073 10:02:06.312418 13, 0x0, sum = 2
3074 10:02:06.315965 14, 0x0, sum = 3
3075 10:02:06.316066 15, 0x0, sum = 4
3076 10:02:06.318848 best_step = 13
3077 10:02:06.318943
3078 10:02:06.319033 ==
3079 10:02:06.322261 Dram Type= 6, Freq= 0, CH_0, rank 1
3080 10:02:06.325499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 10:02:06.325575 ==
3082 10:02:06.328765 RX Vref Scan: 0
3083 10:02:06.328840
3084 10:02:06.328902 RX Vref 0 -> 0, step: 1
3085 10:02:06.328960
3086 10:02:06.332024 RX Delay -21 -> 252, step: 4
3087 10:02:06.339069 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3088 10:02:06.342179 iDelay=195, Bit 1, Center 120 (47 ~ 194) 148
3089 10:02:06.345606 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3090 10:02:06.348934 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3091 10:02:06.352122 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3092 10:02:06.358665 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3093 10:02:06.361859 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3094 10:02:06.365282 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3095 10:02:06.368968 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3096 10:02:06.371656 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3097 10:02:06.375370 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3098 10:02:06.381998 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3099 10:02:06.385313 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3100 10:02:06.388336 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3101 10:02:06.392397 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3102 10:02:06.398536 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3103 10:02:06.398633 ==
3104 10:02:06.401977 Dram Type= 6, Freq= 0, CH_0, rank 1
3105 10:02:06.405158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 10:02:06.405233 ==
3107 10:02:06.405296 DQS Delay:
3108 10:02:06.408708 DQS0 = 0, DQS1 = 0
3109 10:02:06.408780 DQM Delay:
3110 10:02:06.411666 DQM0 = 116, DQM1 = 107
3111 10:02:06.411764 DQ Delay:
3112 10:02:06.414727 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =114
3113 10:02:06.418385 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3114 10:02:06.421433 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3115 10:02:06.425172 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3116 10:02:06.425248
3117 10:02:06.425314
3118 10:02:06.434969 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3119 10:02:06.437864 CH0 RK1: MR19=403, MR18=BE6
3120 10:02:06.444658 CH0_RK1: MR19=0x403, MR18=0xBE6, DQSOSC=405, MR23=63, INC=39, DEC=26
3121 10:02:06.444759 [RxdqsGatingPostProcess] freq 1200
3122 10:02:06.451737 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3123 10:02:06.454536 best DQS0 dly(2T, 0.5T) = (0, 11)
3124 10:02:06.458601 best DQS1 dly(2T, 0.5T) = (0, 12)
3125 10:02:06.461210 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3126 10:02:06.464470 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3127 10:02:06.467897 best DQS0 dly(2T, 0.5T) = (0, 11)
3128 10:02:06.471232 best DQS1 dly(2T, 0.5T) = (0, 12)
3129 10:02:06.474606 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3130 10:02:06.477412 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3131 10:02:06.481103 Pre-setting of DQS Precalculation
3132 10:02:06.484271 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3133 10:02:06.484372 ==
3134 10:02:06.487616 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 10:02:06.490869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 10:02:06.490968 ==
3137 10:02:06.497937 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3138 10:02:06.504043 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3139 10:02:06.512440 [CA 0] Center 37 (7~68) winsize 62
3140 10:02:06.515185 [CA 1] Center 38 (8~68) winsize 61
3141 10:02:06.518610 [CA 2] Center 34 (4~64) winsize 61
3142 10:02:06.522553 [CA 3] Center 33 (3~64) winsize 62
3143 10:02:06.525109 [CA 4] Center 34 (5~64) winsize 60
3144 10:02:06.528717 [CA 5] Center 33 (3~64) winsize 62
3145 10:02:06.528787
3146 10:02:06.532056 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3147 10:02:06.532124
3148 10:02:06.535375 [CATrainingPosCal] consider 1 rank data
3149 10:02:06.538511 u2DelayCellTimex100 = 270/100 ps
3150 10:02:06.541715 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3151 10:02:06.548239 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3152 10:02:06.551709 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3153 10:02:06.555102 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3154 10:02:06.558404 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3155 10:02:06.561595 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3156 10:02:06.561700
3157 10:02:06.565236 CA PerBit enable=1, Macro0, CA PI delay=33
3158 10:02:06.565333
3159 10:02:06.568883 [CBTSetCACLKResult] CA Dly = 33
3160 10:02:06.568953 CS Dly: 6 (0~37)
3161 10:02:06.571709 ==
3162 10:02:06.574923 Dram Type= 6, Freq= 0, CH_1, rank 1
3163 10:02:06.578485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 10:02:06.578588 ==
3165 10:02:06.581989 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3166 10:02:06.588070 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3167 10:02:06.597638 [CA 0] Center 37 (7~67) winsize 61
3168 10:02:06.601253 [CA 1] Center 37 (7~68) winsize 62
3169 10:02:06.604655 [CA 2] Center 34 (4~65) winsize 62
3170 10:02:06.607759 [CA 3] Center 33 (3~64) winsize 62
3171 10:02:06.610862 [CA 4] Center 34 (4~64) winsize 61
3172 10:02:06.614490 [CA 5] Center 33 (3~64) winsize 62
3173 10:02:06.614587
3174 10:02:06.617807 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3175 10:02:06.617879
3176 10:02:06.621183 [CATrainingPosCal] consider 2 rank data
3177 10:02:06.624677 u2DelayCellTimex100 = 270/100 ps
3178 10:02:06.628200 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3179 10:02:06.631122 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3180 10:02:06.638069 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3181 10:02:06.641260 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3182 10:02:06.644380 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3183 10:02:06.647874 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3184 10:02:06.647960
3185 10:02:06.650686 CA PerBit enable=1, Macro0, CA PI delay=33
3186 10:02:06.650770
3187 10:02:06.654195 [CBTSetCACLKResult] CA Dly = 33
3188 10:02:06.654278 CS Dly: 7 (0~40)
3189 10:02:06.654344
3190 10:02:06.657802 ----->DramcWriteLeveling(PI) begin...
3191 10:02:06.661193 ==
3192 10:02:06.664264 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 10:02:06.667469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 10:02:06.667553 ==
3195 10:02:06.671012 Write leveling (Byte 0): 24 => 24
3196 10:02:06.673932 Write leveling (Byte 1): 28 => 28
3197 10:02:06.677618 DramcWriteLeveling(PI) end<-----
3198 10:02:06.677702
3199 10:02:06.677768 ==
3200 10:02:06.680776 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 10:02:06.684457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 10:02:06.684578 ==
3203 10:02:06.687236 [Gating] SW mode calibration
3204 10:02:06.693852 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3205 10:02:06.700621 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3206 10:02:06.704537 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3207 10:02:06.707153 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 10:02:06.714034 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 10:02:06.717244 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 10:02:06.720305 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 10:02:06.728317 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 10:02:06.730522 0 15 24 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 1)
3213 10:02:06.733902 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
3214 10:02:06.740110 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 10:02:06.743713 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 10:02:06.746933 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 10:02:06.753421 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 10:02:06.757159 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 10:02:06.760434 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 10:02:06.763596 1 0 24 | B1->B0 | 2929 3737 | 0 1 | (1 1) (0 0)
3221 10:02:06.770108 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3222 10:02:06.773738 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 10:02:06.776818 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 10:02:06.783270 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 10:02:06.787017 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 10:02:06.790174 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 10:02:06.796501 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 10:02:06.799858 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3229 10:02:06.803317 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3230 10:02:06.809834 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 10:02:06.813062 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 10:02:06.816451 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 10:02:06.823103 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 10:02:06.826664 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 10:02:06.829613 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 10:02:06.836244 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 10:02:06.839603 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 10:02:06.843426 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 10:02:06.849615 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 10:02:06.852979 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 10:02:06.856554 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 10:02:06.862756 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 10:02:06.866158 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 10:02:06.869506 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3245 10:02:06.875967 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3246 10:02:06.876041 Total UI for P1: 0, mck2ui 16
3247 10:02:06.882368 best dqsien dly found for B0: ( 1, 3, 24)
3248 10:02:06.886492 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3249 10:02:06.889840 Total UI for P1: 0, mck2ui 16
3250 10:02:06.892870 best dqsien dly found for B1: ( 1, 3, 28)
3251 10:02:06.895800 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3252 10:02:06.899396 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3253 10:02:06.899465
3254 10:02:06.902446 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3255 10:02:06.906122 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3256 10:02:06.909588 [Gating] SW calibration Done
3257 10:02:06.909690 ==
3258 10:02:06.912242 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 10:02:06.915914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 10:02:06.918899 ==
3261 10:02:06.918976 RX Vref Scan: 0
3262 10:02:06.919036
3263 10:02:06.922596 RX Vref 0 -> 0, step: 1
3264 10:02:06.922694
3265 10:02:06.925657 RX Delay -40 -> 252, step: 8
3266 10:02:06.929148 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3267 10:02:06.932568 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3268 10:02:06.935947 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3269 10:02:06.939214 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3270 10:02:06.945456 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3271 10:02:06.949130 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3272 10:02:06.952510 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3273 10:02:06.955531 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3274 10:02:06.959261 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3275 10:02:06.962478 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3276 10:02:06.969032 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3277 10:02:06.972320 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3278 10:02:06.975483 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3279 10:02:06.979023 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3280 10:02:06.985252 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3281 10:02:06.989632 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3282 10:02:06.989732 ==
3283 10:02:06.992260 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 10:02:06.995362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 10:02:06.995433 ==
3286 10:02:06.999117 DQS Delay:
3287 10:02:06.999185 DQS0 = 0, DQS1 = 0
3288 10:02:06.999245 DQM Delay:
3289 10:02:07.002222 DQM0 = 118, DQM1 = 109
3290 10:02:07.002295 DQ Delay:
3291 10:02:07.005158 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3292 10:02:07.008851 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3293 10:02:07.011957 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3294 10:02:07.018758 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3295 10:02:07.018835
3296 10:02:07.018895
3297 10:02:07.018952 ==
3298 10:02:07.021656 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 10:02:07.025124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 10:02:07.025201 ==
3301 10:02:07.025264
3302 10:02:07.025330
3303 10:02:07.028467 TX Vref Scan disable
3304 10:02:07.028602 == TX Byte 0 ==
3305 10:02:07.035368 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3306 10:02:07.038354 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3307 10:02:07.038426 == TX Byte 1 ==
3308 10:02:07.045352 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3309 10:02:07.048576 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3310 10:02:07.048650 ==
3311 10:02:07.051601 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 10:02:07.055186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 10:02:07.055257 ==
3314 10:02:07.067879 TX Vref=22, minBit 9, minWin=25, winSum=417
3315 10:02:07.071181 TX Vref=24, minBit 11, minWin=25, winSum=425
3316 10:02:07.074384 TX Vref=26, minBit 9, minWin=25, winSum=430
3317 10:02:07.077751 TX Vref=28, minBit 8, minWin=26, winSum=434
3318 10:02:07.081153 TX Vref=30, minBit 11, minWin=25, winSum=430
3319 10:02:07.087921 TX Vref=32, minBit 9, minWin=25, winSum=428
3320 10:02:07.090749 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
3321 10:02:07.090852
3322 10:02:07.094254 Final TX Range 1 Vref 28
3323 10:02:07.094330
3324 10:02:07.094398 ==
3325 10:02:07.097422 Dram Type= 6, Freq= 0, CH_1, rank 0
3326 10:02:07.101185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3327 10:02:07.104255 ==
3328 10:02:07.104335
3329 10:02:07.104397
3330 10:02:07.104456 TX Vref Scan disable
3331 10:02:07.107380 == TX Byte 0 ==
3332 10:02:07.111104 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3333 10:02:07.114276 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3334 10:02:07.117620 == TX Byte 1 ==
3335 10:02:07.120953 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3336 10:02:07.127451 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3337 10:02:07.127534
3338 10:02:07.127599 [DATLAT]
3339 10:02:07.127658 Freq=1200, CH1 RK0
3340 10:02:07.127716
3341 10:02:07.131117 DATLAT Default: 0xd
3342 10:02:07.131212 0, 0xFFFF, sum = 0
3343 10:02:07.134037 1, 0xFFFF, sum = 0
3344 10:02:07.134107 2, 0xFFFF, sum = 0
3345 10:02:07.137378 3, 0xFFFF, sum = 0
3346 10:02:07.140602 4, 0xFFFF, sum = 0
3347 10:02:07.140675 5, 0xFFFF, sum = 0
3348 10:02:07.144442 6, 0xFFFF, sum = 0
3349 10:02:07.144577 7, 0xFFFF, sum = 0
3350 10:02:07.147258 8, 0xFFFF, sum = 0
3351 10:02:07.147328 9, 0xFFFF, sum = 0
3352 10:02:07.150916 10, 0xFFFF, sum = 0
3353 10:02:07.150989 11, 0xFFFF, sum = 0
3354 10:02:07.154223 12, 0x0, sum = 1
3355 10:02:07.154328 13, 0x0, sum = 2
3356 10:02:07.157556 14, 0x0, sum = 3
3357 10:02:07.157625 15, 0x0, sum = 4
3358 10:02:07.157697 best_step = 13
3359 10:02:07.160491
3360 10:02:07.160619 ==
3361 10:02:07.164277 Dram Type= 6, Freq= 0, CH_1, rank 0
3362 10:02:07.167861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3363 10:02:07.167954 ==
3364 10:02:07.168019 RX Vref Scan: 1
3365 10:02:07.168077
3366 10:02:07.171047 Set Vref Range= 32 -> 127
3367 10:02:07.171127
3368 10:02:07.173841 RX Vref 32 -> 127, step: 1
3369 10:02:07.173912
3370 10:02:07.177369 RX Delay -21 -> 252, step: 4
3371 10:02:07.177437
3372 10:02:07.180745 Set Vref, RX VrefLevel [Byte0]: 32
3373 10:02:07.184428 [Byte1]: 32
3374 10:02:07.184529
3375 10:02:07.187587 Set Vref, RX VrefLevel [Byte0]: 33
3376 10:02:07.190436 [Byte1]: 33
3377 10:02:07.194288
3378 10:02:07.194358 Set Vref, RX VrefLevel [Byte0]: 34
3379 10:02:07.197747 [Byte1]: 34
3380 10:02:07.202155
3381 10:02:07.202225 Set Vref, RX VrefLevel [Byte0]: 35
3382 10:02:07.205486 [Byte1]: 35
3383 10:02:07.210224
3384 10:02:07.210295 Set Vref, RX VrefLevel [Byte0]: 36
3385 10:02:07.213481 [Byte1]: 36
3386 10:02:07.218072
3387 10:02:07.218140 Set Vref, RX VrefLevel [Byte0]: 37
3388 10:02:07.220929 [Byte1]: 37
3389 10:02:07.225924
3390 10:02:07.225996 Set Vref, RX VrefLevel [Byte0]: 38
3391 10:02:07.229665 [Byte1]: 38
3392 10:02:07.233517
3393 10:02:07.233587 Set Vref, RX VrefLevel [Byte0]: 39
3394 10:02:07.237057 [Byte1]: 39
3395 10:02:07.241810
3396 10:02:07.241879 Set Vref, RX VrefLevel [Byte0]: 40
3397 10:02:07.245263 [Byte1]: 40
3398 10:02:07.249887
3399 10:02:07.249958 Set Vref, RX VrefLevel [Byte0]: 41
3400 10:02:07.253025 [Byte1]: 41
3401 10:02:07.257327
3402 10:02:07.257403 Set Vref, RX VrefLevel [Byte0]: 42
3403 10:02:07.260492 [Byte1]: 42
3404 10:02:07.265218
3405 10:02:07.265289 Set Vref, RX VrefLevel [Byte0]: 43
3406 10:02:07.268856 [Byte1]: 43
3407 10:02:07.273593
3408 10:02:07.273692 Set Vref, RX VrefLevel [Byte0]: 44
3409 10:02:07.276837 [Byte1]: 44
3410 10:02:07.281419
3411 10:02:07.281490 Set Vref, RX VrefLevel [Byte0]: 45
3412 10:02:07.284653 [Byte1]: 45
3413 10:02:07.289397
3414 10:02:07.289472 Set Vref, RX VrefLevel [Byte0]: 46
3415 10:02:07.292428 [Byte1]: 46
3416 10:02:07.296952
3417 10:02:07.297023 Set Vref, RX VrefLevel [Byte0]: 47
3418 10:02:07.300483 [Byte1]: 47
3419 10:02:07.305104
3420 10:02:07.305175 Set Vref, RX VrefLevel [Byte0]: 48
3421 10:02:07.308175 [Byte1]: 48
3422 10:02:07.313194
3423 10:02:07.313264 Set Vref, RX VrefLevel [Byte0]: 49
3424 10:02:07.316400 [Byte1]: 49
3425 10:02:07.321193
3426 10:02:07.321263 Set Vref, RX VrefLevel [Byte0]: 50
3427 10:02:07.323984 [Byte1]: 50
3428 10:02:07.328821
3429 10:02:07.328927 Set Vref, RX VrefLevel [Byte0]: 51
3430 10:02:07.332151 [Byte1]: 51
3431 10:02:07.336656
3432 10:02:07.336727 Set Vref, RX VrefLevel [Byte0]: 52
3433 10:02:07.339774 [Byte1]: 52
3434 10:02:07.345307
3435 10:02:07.345381 Set Vref, RX VrefLevel [Byte0]: 53
3436 10:02:07.347842 [Byte1]: 53
3437 10:02:07.352461
3438 10:02:07.352596 Set Vref, RX VrefLevel [Byte0]: 54
3439 10:02:07.355559 [Byte1]: 54
3440 10:02:07.360303
3441 10:02:07.360373 Set Vref, RX VrefLevel [Byte0]: 55
3442 10:02:07.363643 [Byte1]: 55
3443 10:02:07.368492
3444 10:02:07.368613 Set Vref, RX VrefLevel [Byte0]: 56
3445 10:02:07.371511 [Byte1]: 56
3446 10:02:07.376023
3447 10:02:07.376095 Set Vref, RX VrefLevel [Byte0]: 57
3448 10:02:07.380087 [Byte1]: 57
3449 10:02:07.383964
3450 10:02:07.384034 Set Vref, RX VrefLevel [Byte0]: 58
3451 10:02:07.387792 [Byte1]: 58
3452 10:02:07.392030
3453 10:02:07.392099 Set Vref, RX VrefLevel [Byte0]: 59
3454 10:02:07.395139 [Byte1]: 59
3455 10:02:07.399981
3456 10:02:07.400051 Set Vref, RX VrefLevel [Byte0]: 60
3457 10:02:07.403037 [Byte1]: 60
3458 10:02:07.407780
3459 10:02:07.407880 Set Vref, RX VrefLevel [Byte0]: 61
3460 10:02:07.411083 [Byte1]: 61
3461 10:02:07.415838
3462 10:02:07.415909 Set Vref, RX VrefLevel [Byte0]: 62
3463 10:02:07.419618 [Byte1]: 62
3464 10:02:07.423626
3465 10:02:07.423724 Set Vref, RX VrefLevel [Byte0]: 63
3466 10:02:07.427209 [Byte1]: 63
3467 10:02:07.431896
3468 10:02:07.431967 Set Vref, RX VrefLevel [Byte0]: 64
3469 10:02:07.435206 [Byte1]: 64
3470 10:02:07.439504
3471 10:02:07.439576 Set Vref, RX VrefLevel [Byte0]: 65
3472 10:02:07.442714 [Byte1]: 65
3473 10:02:07.447469
3474 10:02:07.447576 Set Vref, RX VrefLevel [Byte0]: 66
3475 10:02:07.450552 [Byte1]: 66
3476 10:02:07.455276
3477 10:02:07.455381 Set Vref, RX VrefLevel [Byte0]: 67
3478 10:02:07.458846 [Byte1]: 67
3479 10:02:07.463474
3480 10:02:07.463577 Set Vref, RX VrefLevel [Byte0]: 68
3481 10:02:07.466584 [Byte1]: 68
3482 10:02:07.471152
3483 10:02:07.471249 Final RX Vref Byte 0 = 47 to rank0
3484 10:02:07.474754 Final RX Vref Byte 1 = 53 to rank0
3485 10:02:07.477647 Final RX Vref Byte 0 = 47 to rank1
3486 10:02:07.481093 Final RX Vref Byte 1 = 53 to rank1==
3487 10:02:07.484646 Dram Type= 6, Freq= 0, CH_1, rank 0
3488 10:02:07.491448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 10:02:07.491534 ==
3490 10:02:07.491600 DQS Delay:
3491 10:02:07.491666 DQS0 = 0, DQS1 = 0
3492 10:02:07.494221 DQM Delay:
3493 10:02:07.494291 DQM0 = 116, DQM1 = 110
3494 10:02:07.498229 DQ Delay:
3495 10:02:07.500927 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3496 10:02:07.504630 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =114
3497 10:02:07.507477 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =100
3498 10:02:07.510862 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3499 10:02:07.510940
3500 10:02:07.511000
3501 10:02:07.520770 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3502 10:02:07.520850 CH1 RK0: MR19=403, MR18=3F7
3503 10:02:07.527446 CH1_RK0: MR19=0x403, MR18=0x3F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3504 10:02:07.527526
3505 10:02:07.531447 ----->DramcWriteLeveling(PI) begin...
3506 10:02:07.531518 ==
3507 10:02:07.533963 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 10:02:07.540621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 10:02:07.540704 ==
3510 10:02:07.543929 Write leveling (Byte 0): 24 => 24
3511 10:02:07.544000 Write leveling (Byte 1): 29 => 29
3512 10:02:07.547179 DramcWriteLeveling(PI) end<-----
3513 10:02:07.547260
3514 10:02:07.547326 ==
3515 10:02:07.551118 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 10:02:07.557650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 10:02:07.557724 ==
3518 10:02:07.560698 [Gating] SW mode calibration
3519 10:02:07.567311 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3520 10:02:07.570554 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3521 10:02:07.577376 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3522 10:02:07.581166 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 10:02:07.584037 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 10:02:07.590454 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 10:02:07.593742 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 10:02:07.596963 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3527 10:02:07.603383 0 15 24 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 1)
3528 10:02:07.607088 0 15 28 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (1 0)
3529 10:02:07.609915 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 10:02:07.616409 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 10:02:07.619884 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 10:02:07.622974 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 10:02:07.629589 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3534 10:02:07.633149 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 10:02:07.636322 1 0 24 | B1->B0 | 4040 2b2b | 0 0 | (0 0) (0 0)
3536 10:02:07.642898 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3537 10:02:07.646467 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 10:02:07.649505 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 10:02:07.656144 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 10:02:07.659531 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 10:02:07.663352 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 10:02:07.669633 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 10:02:07.672718 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 10:02:07.676133 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3545 10:02:07.682681 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 10:02:07.686120 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 10:02:07.689485 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 10:02:07.695729 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 10:02:07.698966 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 10:02:07.702902 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 10:02:07.709443 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 10:02:07.712609 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 10:02:07.715467 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 10:02:07.722366 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 10:02:07.725527 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 10:02:07.728684 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 10:02:07.735395 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 10:02:07.739098 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 10:02:07.742144 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3560 10:02:07.748588 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3561 10:02:07.752132 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3562 10:02:07.755861 Total UI for P1: 0, mck2ui 16
3563 10:02:07.758465 best dqsien dly found for B0: ( 1, 3, 26)
3564 10:02:07.762074 Total UI for P1: 0, mck2ui 16
3565 10:02:07.765380 best dqsien dly found for B1: ( 1, 3, 26)
3566 10:02:07.769005 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3567 10:02:07.772105 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3568 10:02:07.772187
3569 10:02:07.775348 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3570 10:02:07.778276 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3571 10:02:07.781619 [Gating] SW calibration Done
3572 10:02:07.781700 ==
3573 10:02:07.784804 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 10:02:07.788000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 10:02:07.791792 ==
3576 10:02:07.791874 RX Vref Scan: 0
3577 10:02:07.791938
3578 10:02:07.794712 RX Vref 0 -> 0, step: 1
3579 10:02:07.794794
3580 10:02:07.798152 RX Delay -40 -> 252, step: 8
3581 10:02:07.801883 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3582 10:02:07.805149 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3583 10:02:07.807943 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3584 10:02:07.811914 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3585 10:02:07.818180 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3586 10:02:07.821725 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3587 10:02:07.825155 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3588 10:02:07.828164 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3589 10:02:07.831326 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3590 10:02:07.837795 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3591 10:02:07.841183 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3592 10:02:07.844853 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3593 10:02:07.847715 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3594 10:02:07.851590 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3595 10:02:07.857718 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3596 10:02:07.860894 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3597 10:02:07.860976 ==
3598 10:02:07.864364 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 10:02:07.867425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 10:02:07.867507 ==
3601 10:02:07.870595 DQS Delay:
3602 10:02:07.870676 DQS0 = 0, DQS1 = 0
3603 10:02:07.870741 DQM Delay:
3604 10:02:07.874511 DQM0 = 116, DQM1 = 109
3605 10:02:07.874592 DQ Delay:
3606 10:02:07.877608 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =111
3607 10:02:07.880740 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3608 10:02:07.884087 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3609 10:02:07.891019 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3610 10:02:07.891101
3611 10:02:07.891165
3612 10:02:07.891224 ==
3613 10:02:07.893937 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 10:02:07.897565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 10:02:07.897647 ==
3616 10:02:07.897711
3617 10:02:07.897771
3618 10:02:07.900374 TX Vref Scan disable
3619 10:02:07.900456 == TX Byte 0 ==
3620 10:02:07.907096 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3621 10:02:07.910483 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3622 10:02:07.913749 == TX Byte 1 ==
3623 10:02:07.916810 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3624 10:02:07.920253 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3625 10:02:07.920334 ==
3626 10:02:07.923487 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 10:02:07.926683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 10:02:07.930175 ==
3629 10:02:07.940330 TX Vref=22, minBit 9, minWin=25, winSum=424
3630 10:02:07.943625 TX Vref=24, minBit 8, minWin=25, winSum=429
3631 10:02:07.947201 TX Vref=26, minBit 8, minWin=26, winSum=435
3632 10:02:07.950154 TX Vref=28, minBit 8, minWin=26, winSum=436
3633 10:02:07.953298 TX Vref=30, minBit 8, minWin=26, winSum=433
3634 10:02:07.960434 TX Vref=32, minBit 7, minWin=26, winSum=432
3635 10:02:07.963230 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 28
3636 10:02:07.963312
3637 10:02:07.966583 Final TX Range 1 Vref 28
3638 10:02:07.966665
3639 10:02:07.966730 ==
3640 10:02:07.969797 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 10:02:07.973463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 10:02:07.976680 ==
3643 10:02:07.976762
3644 10:02:07.976826
3645 10:02:07.976886 TX Vref Scan disable
3646 10:02:07.980433 == TX Byte 0 ==
3647 10:02:07.983232 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3648 10:02:07.989972 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3649 10:02:07.990054 == TX Byte 1 ==
3650 10:02:07.993483 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3651 10:02:07.999686 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3652 10:02:07.999768
3653 10:02:07.999833 [DATLAT]
3654 10:02:07.999894 Freq=1200, CH1 RK1
3655 10:02:07.999952
3656 10:02:08.003260 DATLAT Default: 0xd
3657 10:02:08.006442 0, 0xFFFF, sum = 0
3658 10:02:08.006525 1, 0xFFFF, sum = 0
3659 10:02:08.009878 2, 0xFFFF, sum = 0
3660 10:02:08.009960 3, 0xFFFF, sum = 0
3661 10:02:08.013045 4, 0xFFFF, sum = 0
3662 10:02:08.013128 5, 0xFFFF, sum = 0
3663 10:02:08.016251 6, 0xFFFF, sum = 0
3664 10:02:08.016334 7, 0xFFFF, sum = 0
3665 10:02:08.019600 8, 0xFFFF, sum = 0
3666 10:02:08.019684 9, 0xFFFF, sum = 0
3667 10:02:08.023361 10, 0xFFFF, sum = 0
3668 10:02:08.023445 11, 0xFFFF, sum = 0
3669 10:02:08.026562 12, 0x0, sum = 1
3670 10:02:08.026645 13, 0x0, sum = 2
3671 10:02:08.029568 14, 0x0, sum = 3
3672 10:02:08.029651 15, 0x0, sum = 4
3673 10:02:08.033088 best_step = 13
3674 10:02:08.033169
3675 10:02:08.033233 ==
3676 10:02:08.036108 Dram Type= 6, Freq= 0, CH_1, rank 1
3677 10:02:08.039574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3678 10:02:08.039671 ==
3679 10:02:08.039738 RX Vref Scan: 0
3680 10:02:08.042832
3681 10:02:08.042914 RX Vref 0 -> 0, step: 1
3682 10:02:08.042979
3683 10:02:08.046397 RX Delay -21 -> 252, step: 4
3684 10:02:08.053076 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3685 10:02:08.056270 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3686 10:02:08.059602 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3687 10:02:08.062693 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3688 10:02:08.065866 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3689 10:02:08.072506 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3690 10:02:08.075584 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3691 10:02:08.079115 iDelay=199, Bit 7, Center 112 (47 ~ 178) 132
3692 10:02:08.082425 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3693 10:02:08.085667 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3694 10:02:08.092109 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3695 10:02:08.095503 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3696 10:02:08.099083 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3697 10:02:08.101935 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3698 10:02:08.108490 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3699 10:02:08.112199 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3700 10:02:08.112281 ==
3701 10:02:08.115153 Dram Type= 6, Freq= 0, CH_1, rank 1
3702 10:02:08.118450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3703 10:02:08.118533 ==
3704 10:02:08.118598 DQS Delay:
3705 10:02:08.122121 DQS0 = 0, DQS1 = 0
3706 10:02:08.122203 DQM Delay:
3707 10:02:08.125371 DQM0 = 116, DQM1 = 110
3708 10:02:08.125453 DQ Delay:
3709 10:02:08.128668 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3710 10:02:08.132239 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =112
3711 10:02:08.135419 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =100
3712 10:02:08.142022 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3713 10:02:08.142104
3714 10:02:08.142189
3715 10:02:08.148777 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5ef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 414 ps
3716 10:02:08.151740 CH1 RK1: MR19=303, MR18=F5EF
3717 10:02:08.158271 CH1_RK1: MR19=0x303, MR18=0xF5EF, DQSOSC=414, MR23=63, INC=38, DEC=25
3718 10:02:08.161862 [RxdqsGatingPostProcess] freq 1200
3719 10:02:08.165204 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3720 10:02:08.168261 best DQS0 dly(2T, 0.5T) = (0, 11)
3721 10:02:08.171872 best DQS1 dly(2T, 0.5T) = (0, 11)
3722 10:02:08.174831 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3723 10:02:08.178068 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3724 10:02:08.181768 best DQS0 dly(2T, 0.5T) = (0, 11)
3725 10:02:08.184801 best DQS1 dly(2T, 0.5T) = (0, 11)
3726 10:02:08.188468 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3727 10:02:08.191720 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3728 10:02:08.194858 Pre-setting of DQS Precalculation
3729 10:02:08.197853 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3730 10:02:08.208236 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3731 10:02:08.214806 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3732 10:02:08.214890
3733 10:02:08.214956
3734 10:02:08.217902 [Calibration Summary] 2400 Mbps
3735 10:02:08.217986 CH 0, Rank 0
3736 10:02:08.221090 SW Impedance : PASS
3737 10:02:08.221173 DUTY Scan : NO K
3738 10:02:08.224258 ZQ Calibration : PASS
3739 10:02:08.227475 Jitter Meter : NO K
3740 10:02:08.227558 CBT Training : PASS
3741 10:02:08.230881 Write leveling : PASS
3742 10:02:08.234025 RX DQS gating : PASS
3743 10:02:08.234109 RX DQ/DQS(RDDQC) : PASS
3744 10:02:08.237941 TX DQ/DQS : PASS
3745 10:02:08.240687 RX DATLAT : PASS
3746 10:02:08.240770 RX DQ/DQS(Engine): PASS
3747 10:02:08.243977 TX OE : NO K
3748 10:02:08.244060 All Pass.
3749 10:02:08.244126
3750 10:02:08.247700 CH 0, Rank 1
3751 10:02:08.247799 SW Impedance : PASS
3752 10:02:08.250592 DUTY Scan : NO K
3753 10:02:08.253928 ZQ Calibration : PASS
3754 10:02:08.254011 Jitter Meter : NO K
3755 10:02:08.257669 CBT Training : PASS
3756 10:02:08.260657 Write leveling : PASS
3757 10:02:08.260740 RX DQS gating : PASS
3758 10:02:08.264244 RX DQ/DQS(RDDQC) : PASS
3759 10:02:08.267011 TX DQ/DQS : PASS
3760 10:02:08.267094 RX DATLAT : PASS
3761 10:02:08.270915 RX DQ/DQS(Engine): PASS
3762 10:02:08.270998 TX OE : NO K
3763 10:02:08.273931 All Pass.
3764 10:02:08.274014
3765 10:02:08.274080 CH 1, Rank 0
3766 10:02:08.277224 SW Impedance : PASS
3767 10:02:08.277308 DUTY Scan : NO K
3768 10:02:08.280892 ZQ Calibration : PASS
3769 10:02:08.284490 Jitter Meter : NO K
3770 10:02:08.284627 CBT Training : PASS
3771 10:02:08.287113 Write leveling : PASS
3772 10:02:08.290395 RX DQS gating : PASS
3773 10:02:08.290478 RX DQ/DQS(RDDQC) : PASS
3774 10:02:08.293943 TX DQ/DQS : PASS
3775 10:02:08.297247 RX DATLAT : PASS
3776 10:02:08.297330 RX DQ/DQS(Engine): PASS
3777 10:02:08.300477 TX OE : NO K
3778 10:02:08.300607 All Pass.
3779 10:02:08.300674
3780 10:02:08.303712 CH 1, Rank 1
3781 10:02:08.303796 SW Impedance : PASS
3782 10:02:08.307013 DUTY Scan : NO K
3783 10:02:08.310210 ZQ Calibration : PASS
3784 10:02:08.310293 Jitter Meter : NO K
3785 10:02:08.313838 CBT Training : PASS
3786 10:02:08.316758 Write leveling : PASS
3787 10:02:08.316841 RX DQS gating : PASS
3788 10:02:08.320412 RX DQ/DQS(RDDQC) : PASS
3789 10:02:08.323837 TX DQ/DQS : PASS
3790 10:02:08.323921 RX DATLAT : PASS
3791 10:02:08.326613 RX DQ/DQS(Engine): PASS
3792 10:02:08.329778 TX OE : NO K
3793 10:02:08.329862 All Pass.
3794 10:02:08.329927
3795 10:02:08.329988 DramC Write-DBI off
3796 10:02:08.333457 PER_BANK_REFRESH: Hybrid Mode
3797 10:02:08.336810 TX_TRACKING: ON
3798 10:02:08.343363 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3799 10:02:08.346619 [FAST_K] Save calibration result to emmc
3800 10:02:08.352980 dramc_set_vcore_voltage set vcore to 650000
3801 10:02:08.353092 Read voltage for 600, 5
3802 10:02:08.356430 Vio18 = 0
3803 10:02:08.356535 Vcore = 650000
3804 10:02:08.356622 Vdram = 0
3805 10:02:08.359619 Vddq = 0
3806 10:02:08.359703 Vmddr = 0
3807 10:02:08.362915 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3808 10:02:08.369614 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3809 10:02:08.372929 MEM_TYPE=3, freq_sel=19
3810 10:02:08.376073 sv_algorithm_assistance_LP4_1600
3811 10:02:08.379575 ============ PULL DRAM RESETB DOWN ============
3812 10:02:08.383089 ========== PULL DRAM RESETB DOWN end =========
3813 10:02:08.389211 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3814 10:02:08.392460 ===================================
3815 10:02:08.392551 LPDDR4 DRAM CONFIGURATION
3816 10:02:08.395692 ===================================
3817 10:02:08.399808 EX_ROW_EN[0] = 0x0
3818 10:02:08.399892 EX_ROW_EN[1] = 0x0
3819 10:02:08.402739 LP4Y_EN = 0x0
3820 10:02:08.402823 WORK_FSP = 0x0
3821 10:02:08.405761 WL = 0x2
3822 10:02:08.409112 RL = 0x2
3823 10:02:08.409195 BL = 0x2
3824 10:02:08.412195 RPST = 0x0
3825 10:02:08.412310 RD_PRE = 0x0
3826 10:02:08.415780 WR_PRE = 0x1
3827 10:02:08.415860 WR_PST = 0x0
3828 10:02:08.418760 DBI_WR = 0x0
3829 10:02:08.418850 DBI_RD = 0x0
3830 10:02:08.422370 OTF = 0x1
3831 10:02:08.425819 ===================================
3832 10:02:08.428625 ===================================
3833 10:02:08.428701 ANA top config
3834 10:02:08.431993 ===================================
3835 10:02:08.435400 DLL_ASYNC_EN = 0
3836 10:02:08.438485 ALL_SLAVE_EN = 1
3837 10:02:08.438562 NEW_RANK_MODE = 1
3838 10:02:08.442034 DLL_IDLE_MODE = 1
3839 10:02:08.445427 LP45_APHY_COMB_EN = 1
3840 10:02:08.449391 TX_ODT_DIS = 1
3841 10:02:08.452363 NEW_8X_MODE = 1
3842 10:02:08.455187 ===================================
3843 10:02:08.458499 ===================================
3844 10:02:08.458591 data_rate = 1200
3845 10:02:08.461918 CKR = 1
3846 10:02:08.465182 DQ_P2S_RATIO = 8
3847 10:02:08.468553 ===================================
3848 10:02:08.471517 CA_P2S_RATIO = 8
3849 10:02:08.475103 DQ_CA_OPEN = 0
3850 10:02:08.478479 DQ_SEMI_OPEN = 0
3851 10:02:08.478552 CA_SEMI_OPEN = 0
3852 10:02:08.481711 CA_FULL_RATE = 0
3853 10:02:08.484782 DQ_CKDIV4_EN = 1
3854 10:02:08.488397 CA_CKDIV4_EN = 1
3855 10:02:08.491517 CA_PREDIV_EN = 0
3856 10:02:08.495466 PH8_DLY = 0
3857 10:02:08.495575 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3858 10:02:08.498081 DQ_AAMCK_DIV = 4
3859 10:02:08.501262 CA_AAMCK_DIV = 4
3860 10:02:08.504879 CA_ADMCK_DIV = 4
3861 10:02:08.508113 DQ_TRACK_CA_EN = 0
3862 10:02:08.511385 CA_PICK = 600
3863 10:02:08.514456 CA_MCKIO = 600
3864 10:02:08.514538 MCKIO_SEMI = 0
3865 10:02:08.517854 PLL_FREQ = 2288
3866 10:02:08.521502 DQ_UI_PI_RATIO = 32
3867 10:02:08.524548 CA_UI_PI_RATIO = 0
3868 10:02:08.527926 ===================================
3869 10:02:08.531133 ===================================
3870 10:02:08.534615 memory_type:LPDDR4
3871 10:02:08.534697 GP_NUM : 10
3872 10:02:08.537716 SRAM_EN : 1
3873 10:02:08.541217 MD32_EN : 0
3874 10:02:08.544427 ===================================
3875 10:02:08.544509 [ANA_INIT] >>>>>>>>>>>>>>
3876 10:02:08.547598 <<<<<< [CONFIGURE PHASE]: ANA_TX
3877 10:02:08.551213 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3878 10:02:08.554320 ===================================
3879 10:02:08.557624 data_rate = 1200,PCW = 0X5800
3880 10:02:08.560906 ===================================
3881 10:02:08.564371 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3882 10:02:08.570813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3883 10:02:08.573929 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3884 10:02:08.580550 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3885 10:02:08.584225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3886 10:02:08.587334 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3887 10:02:08.590976 [ANA_INIT] flow start
3888 10:02:08.591058 [ANA_INIT] PLL >>>>>>>>
3889 10:02:08.594118 [ANA_INIT] PLL <<<<<<<<
3890 10:02:08.597211 [ANA_INIT] MIDPI >>>>>>>>
3891 10:02:08.597293 [ANA_INIT] MIDPI <<<<<<<<
3892 10:02:08.600808 [ANA_INIT] DLL >>>>>>>>
3893 10:02:08.604038 [ANA_INIT] flow end
3894 10:02:08.607017 ============ LP4 DIFF to SE enter ============
3895 10:02:08.610780 ============ LP4 DIFF to SE exit ============
3896 10:02:08.613643 [ANA_INIT] <<<<<<<<<<<<<
3897 10:02:08.617011 [Flow] Enable top DCM control >>>>>
3898 10:02:08.620028 [Flow] Enable top DCM control <<<<<
3899 10:02:08.623670 Enable DLL master slave shuffle
3900 10:02:08.626667 ==============================================================
3901 10:02:08.630175 Gating Mode config
3902 10:02:08.636487 ==============================================================
3903 10:02:08.636575 Config description:
3904 10:02:08.646673 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3905 10:02:08.653039 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3906 10:02:08.659924 SELPH_MODE 0: By rank 1: By Phase
3907 10:02:08.663205 ==============================================================
3908 10:02:08.666309 GAT_TRACK_EN = 1
3909 10:02:08.669931 RX_GATING_MODE = 2
3910 10:02:08.673149 RX_GATING_TRACK_MODE = 2
3911 10:02:08.676521 SELPH_MODE = 1
3912 10:02:08.680522 PICG_EARLY_EN = 1
3913 10:02:08.683080 VALID_LAT_VALUE = 1
3914 10:02:08.686521 ==============================================================
3915 10:02:08.689887 Enter into Gating configuration >>>>
3916 10:02:08.692903 Exit from Gating configuration <<<<
3917 10:02:08.696811 Enter into DVFS_PRE_config >>>>>
3918 10:02:08.709773 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3919 10:02:08.712786 Exit from DVFS_PRE_config <<<<<
3920 10:02:08.716612 Enter into PICG configuration >>>>
3921 10:02:08.716722 Exit from PICG configuration <<<<
3922 10:02:08.719269 [RX_INPUT] configuration >>>>>
3923 10:02:08.723130 [RX_INPUT] configuration <<<<<
3924 10:02:08.729454 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3925 10:02:08.732531 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3926 10:02:08.738920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3927 10:02:08.745625 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3928 10:02:08.752662 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3929 10:02:08.759371 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3930 10:02:08.762300 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3931 10:02:08.765463 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3932 10:02:08.772264 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3933 10:02:08.775208 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3934 10:02:08.778506 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3935 10:02:08.785532 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3936 10:02:08.788844 ===================================
3937 10:02:08.788927 LPDDR4 DRAM CONFIGURATION
3938 10:02:08.791599 ===================================
3939 10:02:08.795182 EX_ROW_EN[0] = 0x0
3940 10:02:08.795264 EX_ROW_EN[1] = 0x0
3941 10:02:08.798808 LP4Y_EN = 0x0
3942 10:02:08.798893 WORK_FSP = 0x0
3943 10:02:08.801677 WL = 0x2
3944 10:02:08.801759 RL = 0x2
3945 10:02:08.805010 BL = 0x2
3946 10:02:08.808635 RPST = 0x0
3947 10:02:08.808721 RD_PRE = 0x0
3948 10:02:08.811357 WR_PRE = 0x1
3949 10:02:08.811429 WR_PST = 0x0
3950 10:02:08.815083 DBI_WR = 0x0
3951 10:02:08.815165 DBI_RD = 0x0
3952 10:02:08.818399 OTF = 0x1
3953 10:02:08.821729 ===================================
3954 10:02:08.824842 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3955 10:02:08.827931 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3956 10:02:08.831235 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3957 10:02:08.834553 ===================================
3958 10:02:08.838460 LPDDR4 DRAM CONFIGURATION
3959 10:02:08.841039 ===================================
3960 10:02:08.844887 EX_ROW_EN[0] = 0x10
3961 10:02:08.844960 EX_ROW_EN[1] = 0x0
3962 10:02:08.847575 LP4Y_EN = 0x0
3963 10:02:08.847678 WORK_FSP = 0x0
3964 10:02:08.850883 WL = 0x2
3965 10:02:08.854167 RL = 0x2
3966 10:02:08.854241 BL = 0x2
3967 10:02:08.857666 RPST = 0x0
3968 10:02:08.857737 RD_PRE = 0x0
3969 10:02:08.860860 WR_PRE = 0x1
3970 10:02:08.860931 WR_PST = 0x0
3971 10:02:08.864397 DBI_WR = 0x0
3972 10:02:08.864474 DBI_RD = 0x0
3973 10:02:08.867732 OTF = 0x1
3974 10:02:08.871126 ===================================
3975 10:02:08.877995 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3976 10:02:08.880699 nWR fixed to 30
3977 10:02:08.880781 [ModeRegInit_LP4] CH0 RK0
3978 10:02:08.884078 [ModeRegInit_LP4] CH0 RK1
3979 10:02:08.887384 [ModeRegInit_LP4] CH1 RK0
3980 10:02:08.890555 [ModeRegInit_LP4] CH1 RK1
3981 10:02:08.890637 match AC timing 17
3982 10:02:08.894132 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3983 10:02:08.900499 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3984 10:02:08.904080 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3985 10:02:08.907345 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3986 10:02:08.913627 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3987 10:02:08.913710 ==
3988 10:02:08.917044 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 10:02:08.920356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 10:02:08.920439 ==
3991 10:02:08.927151 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3992 10:02:08.933849 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3993 10:02:08.937130 [CA 0] Center 36 (6~66) winsize 61
3994 10:02:08.940239 [CA 1] Center 36 (6~66) winsize 61
3995 10:02:08.943501 [CA 2] Center 34 (3~65) winsize 63
3996 10:02:08.946627 [CA 3] Center 34 (4~65) winsize 62
3997 10:02:08.949792 [CA 4] Center 33 (3~64) winsize 62
3998 10:02:08.953445 [CA 5] Center 33 (3~64) winsize 62
3999 10:02:08.953528
4000 10:02:08.957067 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4001 10:02:08.957149
4002 10:02:08.960141 [CATrainingPosCal] consider 1 rank data
4003 10:02:08.963506 u2DelayCellTimex100 = 270/100 ps
4004 10:02:08.966457 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4005 10:02:08.969936 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4006 10:02:08.973039 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4007 10:02:08.976727 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4008 10:02:08.979801 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4009 10:02:08.983056 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4010 10:02:08.986453
4011 10:02:08.989314 CA PerBit enable=1, Macro0, CA PI delay=33
4012 10:02:08.989396
4013 10:02:08.992918 [CBTSetCACLKResult] CA Dly = 33
4014 10:02:08.993000 CS Dly: 5 (0~36)
4015 10:02:08.993065 ==
4016 10:02:08.995973 Dram Type= 6, Freq= 0, CH_0, rank 1
4017 10:02:08.999461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 10:02:09.002629 ==
4019 10:02:09.005930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4020 10:02:09.012511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4021 10:02:09.015641 [CA 0] Center 36 (6~66) winsize 61
4022 10:02:09.019250 [CA 1] Center 36 (6~66) winsize 61
4023 10:02:09.022387 [CA 2] Center 34 (4~64) winsize 61
4024 10:02:09.025983 [CA 3] Center 33 (3~64) winsize 62
4025 10:02:09.028800 [CA 4] Center 33 (2~64) winsize 63
4026 10:02:09.032150 [CA 5] Center 33 (2~64) winsize 63
4027 10:02:09.032232
4028 10:02:09.035932 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4029 10:02:09.036015
4030 10:02:09.039288 [CATrainingPosCal] consider 2 rank data
4031 10:02:09.042607 u2DelayCellTimex100 = 270/100 ps
4032 10:02:09.045674 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4033 10:02:09.048862 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4034 10:02:09.055466 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4035 10:02:09.058577 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4036 10:02:09.061704 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4037 10:02:09.065285 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4038 10:02:09.065367
4039 10:02:09.068506 CA PerBit enable=1, Macro0, CA PI delay=33
4040 10:02:09.068628
4041 10:02:09.071858 [CBTSetCACLKResult] CA Dly = 33
4042 10:02:09.071940 CS Dly: 5 (0~37)
4043 10:02:09.072005
4044 10:02:09.078226 ----->DramcWriteLeveling(PI) begin...
4045 10:02:09.078310 ==
4046 10:02:09.081738 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 10:02:09.085082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 10:02:09.085165 ==
4049 10:02:09.088415 Write leveling (Byte 0): 35 => 35
4050 10:02:09.091686 Write leveling (Byte 1): 29 => 29
4051 10:02:09.095026 DramcWriteLeveling(PI) end<-----
4052 10:02:09.095107
4053 10:02:09.095172 ==
4054 10:02:09.098022 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 10:02:09.101680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 10:02:09.101762 ==
4057 10:02:09.104921 [Gating] SW mode calibration
4058 10:02:09.111495 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4059 10:02:09.118152 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4060 10:02:09.121382 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4061 10:02:09.124431 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4062 10:02:09.131249 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4063 10:02:09.134608 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
4064 10:02:09.138231 0 9 16 | B1->B0 | 3030 2626 | 1 0 | (1 0) (0 0)
4065 10:02:09.144356 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 10:02:09.147376 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 10:02:09.150766 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 10:02:09.157477 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 10:02:09.160936 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 10:02:09.163979 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 10:02:09.170464 0 10 12 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
4072 10:02:09.173907 0 10 16 | B1->B0 | 3636 3c3c | 0 0 | (0 0) (0 0)
4073 10:02:09.177461 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 10:02:09.183653 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 10:02:09.187309 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 10:02:09.190110 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 10:02:09.196915 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 10:02:09.200226 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 10:02:09.203397 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4080 10:02:09.210476 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4081 10:02:09.213437 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 10:02:09.216606 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 10:02:09.223038 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 10:02:09.226378 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 10:02:09.229828 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 10:02:09.236246 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 10:02:09.239621 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 10:02:09.243043 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 10:02:09.249729 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 10:02:09.253182 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 10:02:09.256413 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 10:02:09.262651 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 10:02:09.266136 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 10:02:09.269371 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 10:02:09.275840 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4096 10:02:09.279295 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 10:02:09.282810 Total UI for P1: 0, mck2ui 16
4098 10:02:09.285672 best dqsien dly found for B0: ( 0, 13, 12)
4099 10:02:09.289448 Total UI for P1: 0, mck2ui 16
4100 10:02:09.292378 best dqsien dly found for B1: ( 0, 13, 12)
4101 10:02:09.296631 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4102 10:02:09.299651 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4103 10:02:09.299733
4104 10:02:09.302511 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4105 10:02:09.305951 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4106 10:02:09.309110 [Gating] SW calibration Done
4107 10:02:09.309192 ==
4108 10:02:09.312477 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 10:02:09.318784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 10:02:09.318868 ==
4111 10:02:09.318933 RX Vref Scan: 0
4112 10:02:09.318993
4113 10:02:09.322420 RX Vref 0 -> 0, step: 1
4114 10:02:09.322502
4115 10:02:09.325700 RX Delay -230 -> 252, step: 16
4116 10:02:09.328404 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4117 10:02:09.331849 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4118 10:02:09.335460 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4119 10:02:09.342052 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4120 10:02:09.345245 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4121 10:02:09.348658 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4122 10:02:09.351414 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4123 10:02:09.358004 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4124 10:02:09.361188 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4125 10:02:09.364774 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4126 10:02:09.367871 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4127 10:02:09.375088 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4128 10:02:09.378236 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4129 10:02:09.381278 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4130 10:02:09.384439 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4131 10:02:09.391735 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4132 10:02:09.391820 ==
4133 10:02:09.394443 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 10:02:09.398176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 10:02:09.398251 ==
4136 10:02:09.398335 DQS Delay:
4137 10:02:09.401103 DQS0 = 0, DQS1 = 0
4138 10:02:09.401176 DQM Delay:
4139 10:02:09.404465 DQM0 = 47, DQM1 = 31
4140 10:02:09.404558 DQ Delay:
4141 10:02:09.407969 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =49
4142 10:02:09.410951 DQ4 =57, DQ5 =33, DQ6 =57, DQ7 =57
4143 10:02:09.414573 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4144 10:02:09.417774 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4145 10:02:09.417850
4146 10:02:09.417932
4147 10:02:09.418008 ==
4148 10:02:09.420994 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 10:02:09.424343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 10:02:09.424422 ==
4151 10:02:09.427483
4152 10:02:09.427564
4153 10:02:09.427647 TX Vref Scan disable
4154 10:02:09.430820 == TX Byte 0 ==
4155 10:02:09.434314 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4156 10:02:09.437851 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4157 10:02:09.441077 == TX Byte 1 ==
4158 10:02:09.444257 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4159 10:02:09.447237 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4160 10:02:09.450762 ==
4161 10:02:09.454092 Dram Type= 6, Freq= 0, CH_0, rank 0
4162 10:02:09.457197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 10:02:09.457271 ==
4164 10:02:09.457355
4165 10:02:09.457431
4166 10:02:09.460625 TX Vref Scan disable
4167 10:02:09.463954 == TX Byte 0 ==
4168 10:02:09.466905 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4169 10:02:09.470554 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4170 10:02:09.473641 == TX Byte 1 ==
4171 10:02:09.476852 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4172 10:02:09.480616 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4173 10:02:09.480691
4174 10:02:09.480772 [DATLAT]
4175 10:02:09.484105 Freq=600, CH0 RK0
4176 10:02:09.484178
4177 10:02:09.486775 DATLAT Default: 0x9
4178 10:02:09.486849 0, 0xFFFF, sum = 0
4179 10:02:09.490759 1, 0xFFFF, sum = 0
4180 10:02:09.490846 2, 0xFFFF, sum = 0
4181 10:02:09.493449 3, 0xFFFF, sum = 0
4182 10:02:09.493534 4, 0xFFFF, sum = 0
4183 10:02:09.497024 5, 0xFFFF, sum = 0
4184 10:02:09.497109 6, 0xFFFF, sum = 0
4185 10:02:09.500621 7, 0xFFFF, sum = 0
4186 10:02:09.500707 8, 0x0, sum = 1
4187 10:02:09.503680 9, 0x0, sum = 2
4188 10:02:09.503766 10, 0x0, sum = 3
4189 10:02:09.507239 11, 0x0, sum = 4
4190 10:02:09.507323 best_step = 9
4191 10:02:09.507388
4192 10:02:09.507449 ==
4193 10:02:09.510476 Dram Type= 6, Freq= 0, CH_0, rank 0
4194 10:02:09.513056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 10:02:09.513144 ==
4196 10:02:09.516708 RX Vref Scan: 1
4197 10:02:09.516791
4198 10:02:09.519867 RX Vref 0 -> 0, step: 1
4199 10:02:09.519950
4200 10:02:09.520015 RX Delay -195 -> 252, step: 8
4201 10:02:09.520077
4202 10:02:09.523181 Set Vref, RX VrefLevel [Byte0]: 61
4203 10:02:09.526564 [Byte1]: 49
4204 10:02:09.531074
4205 10:02:09.531158 Final RX Vref Byte 0 = 61 to rank0
4206 10:02:09.534293 Final RX Vref Byte 1 = 49 to rank0
4207 10:02:09.538217 Final RX Vref Byte 0 = 61 to rank1
4208 10:02:09.541399 Final RX Vref Byte 1 = 49 to rank1==
4209 10:02:09.544468 Dram Type= 6, Freq= 0, CH_0, rank 0
4210 10:02:09.550978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 10:02:09.551088 ==
4212 10:02:09.551203 DQS Delay:
4213 10:02:09.554383 DQS0 = 0, DQS1 = 0
4214 10:02:09.554466 DQM Delay:
4215 10:02:09.554531 DQM0 = 44, DQM1 = 32
4216 10:02:09.557858 DQ Delay:
4217 10:02:09.560835 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4218 10:02:09.563894 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =52
4219 10:02:09.567248 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4220 10:02:09.570723 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4221 10:02:09.570807
4222 10:02:09.570872
4223 10:02:09.577331 [DQSOSCAuto] RK0, (LSB)MR18= 0x633a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4224 10:02:09.580739 CH0 RK0: MR19=808, MR18=633A
4225 10:02:09.587378 CH0_RK0: MR19=0x808, MR18=0x633A, DQSOSC=391, MR23=63, INC=171, DEC=114
4226 10:02:09.587461
4227 10:02:09.590575 ----->DramcWriteLeveling(PI) begin...
4228 10:02:09.590660 ==
4229 10:02:09.593865 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 10:02:09.596875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 10:02:09.596959 ==
4232 10:02:09.600312 Write leveling (Byte 0): 34 => 34
4233 10:02:09.603399 Write leveling (Byte 1): 30 => 30
4234 10:02:09.606909 DramcWriteLeveling(PI) end<-----
4235 10:02:09.606993
4236 10:02:09.607058 ==
4237 10:02:09.610095 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 10:02:09.616787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 10:02:09.616871 ==
4240 10:02:09.616937 [Gating] SW mode calibration
4241 10:02:09.626339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4242 10:02:09.629748 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4243 10:02:09.636692 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4244 10:02:09.639572 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4245 10:02:09.642820 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4246 10:02:09.649393 0 9 12 | B1->B0 | 3434 3333 | 0 0 | (0 1) (0 0)
4247 10:02:09.652567 0 9 16 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 0)
4248 10:02:09.656213 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 10:02:09.662610 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 10:02:09.666009 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 10:02:09.669219 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 10:02:09.675644 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 10:02:09.679103 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 10:02:09.682272 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 10:02:09.688655 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4256 10:02:09.692396 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 10:02:09.696005 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 10:02:09.702298 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 10:02:09.705087 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 10:02:09.708647 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 10:02:09.715288 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 10:02:09.718951 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4263 10:02:09.722039 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 10:02:09.728422 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 10:02:09.731759 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 10:02:09.735159 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 10:02:09.742199 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 10:02:09.744892 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 10:02:09.748422 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 10:02:09.754965 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 10:02:09.758600 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 10:02:09.761281 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 10:02:09.768452 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 10:02:09.771303 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 10:02:09.774947 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 10:02:09.781356 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 10:02:09.784370 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 10:02:09.788064 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4279 10:02:09.794462 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4280 10:02:09.794545 Total UI for P1: 0, mck2ui 16
4281 10:02:09.801216 best dqsien dly found for B0: ( 0, 13, 12)
4282 10:02:09.801300 Total UI for P1: 0, mck2ui 16
4283 10:02:09.804997 best dqsien dly found for B1: ( 0, 13, 12)
4284 10:02:09.811474 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4285 10:02:09.814415 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4286 10:02:09.814499
4287 10:02:09.817940 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4288 10:02:09.820700 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4289 10:02:09.824082 [Gating] SW calibration Done
4290 10:02:09.824153 ==
4291 10:02:09.827447 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 10:02:09.831016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 10:02:09.831088 ==
4294 10:02:09.834194 RX Vref Scan: 0
4295 10:02:09.834264
4296 10:02:09.834324 RX Vref 0 -> 0, step: 1
4297 10:02:09.834388
4298 10:02:09.837503 RX Delay -230 -> 252, step: 16
4299 10:02:09.844025 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4300 10:02:09.847338 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4301 10:02:09.850343 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4302 10:02:09.853564 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4303 10:02:09.857063 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4304 10:02:09.863668 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4305 10:02:09.867236 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4306 10:02:09.870145 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4307 10:02:09.873553 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4308 10:02:09.880339 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4309 10:02:09.883556 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4310 10:02:09.886660 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4311 10:02:09.889695 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4312 10:02:09.896404 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4313 10:02:09.899760 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4314 10:02:09.903017 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4315 10:02:09.903115 ==
4316 10:02:09.906497 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 10:02:09.910087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 10:02:09.912967 ==
4319 10:02:09.913042 DQS Delay:
4320 10:02:09.913108 DQS0 = 0, DQS1 = 0
4321 10:02:09.916314 DQM Delay:
4322 10:02:09.916410 DQM0 = 45, DQM1 = 38
4323 10:02:09.919488 DQ Delay:
4324 10:02:09.922929 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4325 10:02:09.923028 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =49
4326 10:02:09.926403 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =25
4327 10:02:09.932648 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4328 10:02:09.932724
4329 10:02:09.932787
4330 10:02:09.932846 ==
4331 10:02:09.936402 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 10:02:09.939297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 10:02:09.939395 ==
4334 10:02:09.939487
4335 10:02:09.939574
4336 10:02:09.942636 TX Vref Scan disable
4337 10:02:09.942735 == TX Byte 0 ==
4338 10:02:09.949361 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4339 10:02:09.952399 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4340 10:02:09.952521 == TX Byte 1 ==
4341 10:02:09.959189 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4342 10:02:09.962391 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4343 10:02:09.962469 ==
4344 10:02:09.966085 Dram Type= 6, Freq= 0, CH_0, rank 1
4345 10:02:09.968956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 10:02:09.969033 ==
4347 10:02:09.969095
4348 10:02:09.972723
4349 10:02:09.972792 TX Vref Scan disable
4350 10:02:09.975959 == TX Byte 0 ==
4351 10:02:09.979170 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4352 10:02:09.986364 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4353 10:02:09.986439 == TX Byte 1 ==
4354 10:02:09.989549 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4355 10:02:09.995846 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4356 10:02:09.995945
4357 10:02:09.996034 [DATLAT]
4358 10:02:09.996123 Freq=600, CH0 RK1
4359 10:02:09.996193
4360 10:02:09.998992 DATLAT Default: 0x9
4361 10:02:09.999056 0, 0xFFFF, sum = 0
4362 10:02:10.002233 1, 0xFFFF, sum = 0
4363 10:02:10.005523 2, 0xFFFF, sum = 0
4364 10:02:10.005594 3, 0xFFFF, sum = 0
4365 10:02:10.009175 4, 0xFFFF, sum = 0
4366 10:02:10.009243 5, 0xFFFF, sum = 0
4367 10:02:10.012369 6, 0xFFFF, sum = 0
4368 10:02:10.012438 7, 0xFFFF, sum = 0
4369 10:02:10.015617 8, 0x0, sum = 1
4370 10:02:10.015715 9, 0x0, sum = 2
4371 10:02:10.018648 10, 0x0, sum = 3
4372 10:02:10.018745 11, 0x0, sum = 4
4373 10:02:10.018835 best_step = 9
4374 10:02:10.018919
4375 10:02:10.022768 ==
4376 10:02:10.025374 Dram Type= 6, Freq= 0, CH_0, rank 1
4377 10:02:10.029011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 10:02:10.029084 ==
4379 10:02:10.029148 RX Vref Scan: 0
4380 10:02:10.029205
4381 10:02:10.031972 RX Vref 0 -> 0, step: 1
4382 10:02:10.032044
4383 10:02:10.035627 RX Delay -179 -> 252, step: 8
4384 10:02:10.042089 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4385 10:02:10.045282 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4386 10:02:10.048922 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4387 10:02:10.052065 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4388 10:02:10.055052 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4389 10:02:10.061569 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4390 10:02:10.065693 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4391 10:02:10.068240 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4392 10:02:10.071806 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4393 10:02:10.078609 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4394 10:02:10.081607 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4395 10:02:10.085104 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4396 10:02:10.088185 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4397 10:02:10.095128 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4398 10:02:10.098053 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4399 10:02:10.101880 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4400 10:02:10.101960 ==
4401 10:02:10.104916 Dram Type= 6, Freq= 0, CH_0, rank 1
4402 10:02:10.108080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 10:02:10.108148 ==
4404 10:02:10.111842 DQS Delay:
4405 10:02:10.111938 DQS0 = 0, DQS1 = 0
4406 10:02:10.114939 DQM Delay:
4407 10:02:10.115034 DQM0 = 42, DQM1 = 36
4408 10:02:10.115122 DQ Delay:
4409 10:02:10.118036 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4410 10:02:10.121185 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4411 10:02:10.124397 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4412 10:02:10.127701 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4413 10:02:10.127774
4414 10:02:10.127834
4415 10:02:10.137991 [DQSOSCAuto] RK1, (LSB)MR18= 0x6417, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4416 10:02:10.141024 CH0 RK1: MR19=808, MR18=6417
4417 10:02:10.148073 CH0_RK1: MR19=0x808, MR18=0x6417, DQSOSC=391, MR23=63, INC=171, DEC=114
4418 10:02:10.148176 [RxdqsGatingPostProcess] freq 600
4419 10:02:10.154695 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4420 10:02:10.157667 Pre-setting of DQS Precalculation
4421 10:02:10.161389 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4422 10:02:10.164491 ==
4423 10:02:10.167617 Dram Type= 6, Freq= 0, CH_1, rank 0
4424 10:02:10.171086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 10:02:10.171185 ==
4426 10:02:10.174143 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4427 10:02:10.181059 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4428 10:02:10.184954 [CA 0] Center 35 (5~66) winsize 62
4429 10:02:10.188334 [CA 1] Center 35 (5~66) winsize 62
4430 10:02:10.191180 [CA 2] Center 34 (4~65) winsize 62
4431 10:02:10.194679 [CA 3] Center 33 (3~64) winsize 62
4432 10:02:10.198293 [CA 4] Center 34 (4~64) winsize 61
4433 10:02:10.201082 [CA 5] Center 33 (3~64) winsize 62
4434 10:02:10.201153
4435 10:02:10.204431 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4436 10:02:10.204501
4437 10:02:10.207735 [CATrainingPosCal] consider 1 rank data
4438 10:02:10.211463 u2DelayCellTimex100 = 270/100 ps
4439 10:02:10.214239 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4440 10:02:10.221094 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4441 10:02:10.224435 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 10:02:10.227846 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4443 10:02:10.231016 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4444 10:02:10.234074 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4445 10:02:10.234147
4446 10:02:10.237730 CA PerBit enable=1, Macro0, CA PI delay=33
4447 10:02:10.237802
4448 10:02:10.241295 [CBTSetCACLKResult] CA Dly = 33
4449 10:02:10.244430 CS Dly: 3 (0~34)
4450 10:02:10.244538 ==
4451 10:02:10.247262 Dram Type= 6, Freq= 0, CH_1, rank 1
4452 10:02:10.250829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4453 10:02:10.250906 ==
4454 10:02:10.257574 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4455 10:02:10.260567 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4456 10:02:10.265329 [CA 0] Center 35 (5~66) winsize 62
4457 10:02:10.268197 [CA 1] Center 36 (6~66) winsize 61
4458 10:02:10.271439 [CA 2] Center 34 (4~65) winsize 62
4459 10:02:10.274963 [CA 3] Center 34 (3~65) winsize 63
4460 10:02:10.277973 [CA 4] Center 34 (3~65) winsize 63
4461 10:02:10.281606 [CA 5] Center 34 (4~65) winsize 62
4462 10:02:10.281692
4463 10:02:10.284626 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4464 10:02:10.284709
4465 10:02:10.288151 [CATrainingPosCal] consider 2 rank data
4466 10:02:10.291535 u2DelayCellTimex100 = 270/100 ps
4467 10:02:10.294533 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4468 10:02:10.301246 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4469 10:02:10.304378 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4470 10:02:10.307924 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4471 10:02:10.311151 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4472 10:02:10.314335 CA5 delay=34 (4~64),Diff = 1 PI (9 cell)
4473 10:02:10.314419
4474 10:02:10.318141 CA PerBit enable=1, Macro0, CA PI delay=33
4475 10:02:10.318224
4476 10:02:10.321322 [CBTSetCACLKResult] CA Dly = 33
4477 10:02:10.325002 CS Dly: 4 (0~37)
4478 10:02:10.325143
4479 10:02:10.328015 ----->DramcWriteLeveling(PI) begin...
4480 10:02:10.328140 ==
4481 10:02:10.331163 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 10:02:10.334511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 10:02:10.334660 ==
4484 10:02:10.337622 Write leveling (Byte 0): 28 => 28
4485 10:02:10.340698 Write leveling (Byte 1): 31 => 31
4486 10:02:10.344411 DramcWriteLeveling(PI) end<-----
4487 10:02:10.344570
4488 10:02:10.344640 ==
4489 10:02:10.347616 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 10:02:10.350621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 10:02:10.350750 ==
4492 10:02:10.354092 [Gating] SW mode calibration
4493 10:02:10.361000 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4494 10:02:10.367187 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4495 10:02:10.370829 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4496 10:02:10.374132 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4497 10:02:10.380757 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4498 10:02:10.383527 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (0 1)
4499 10:02:10.387262 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 10:02:10.393721 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 10:02:10.396784 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 10:02:10.400369 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 10:02:10.406736 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 10:02:10.410782 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 10:02:10.413457 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 10:02:10.420510 0 10 12 | B1->B0 | 2e2e 3838 | 0 1 | (0 0) (0 0)
4507 10:02:10.423427 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 10:02:10.427119 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 10:02:10.433325 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 10:02:10.436608 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 10:02:10.439632 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 10:02:10.446553 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 10:02:10.449836 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 10:02:10.453130 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4515 10:02:10.459522 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 10:02:10.462983 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 10:02:10.466188 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 10:02:10.472876 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 10:02:10.476078 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 10:02:10.479615 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 10:02:10.485698 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 10:02:10.489172 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 10:02:10.492737 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 10:02:10.499412 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 10:02:10.502455 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 10:02:10.505470 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 10:02:10.512638 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 10:02:10.515292 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 10:02:10.518993 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 10:02:10.525278 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4531 10:02:10.528454 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 10:02:10.532000 Total UI for P1: 0, mck2ui 16
4533 10:02:10.535093 best dqsien dly found for B0: ( 0, 13, 12)
4534 10:02:10.539259 Total UI for P1: 0, mck2ui 16
4535 10:02:10.541687 best dqsien dly found for B1: ( 0, 13, 14)
4536 10:02:10.544972 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4537 10:02:10.548732 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4538 10:02:10.548818
4539 10:02:10.551839 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4540 10:02:10.558156 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4541 10:02:10.558244 [Gating] SW calibration Done
4542 10:02:10.558310 ==
4543 10:02:10.561649 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 10:02:10.569745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 10:02:10.569840 ==
4546 10:02:10.569907 RX Vref Scan: 0
4547 10:02:10.569969
4548 10:02:10.571716 RX Vref 0 -> 0, step: 1
4549 10:02:10.571799
4550 10:02:10.574392 RX Delay -230 -> 252, step: 16
4551 10:02:10.577905 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4552 10:02:10.580970 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4553 10:02:10.588041 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4554 10:02:10.591467 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4555 10:02:10.594672 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4556 10:02:10.598458 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4557 10:02:10.604392 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4558 10:02:10.608078 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4559 10:02:10.610981 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4560 10:02:10.614261 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4561 10:02:10.618032 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4562 10:02:10.623766 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4563 10:02:10.627937 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4564 10:02:10.630623 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4565 10:02:10.634065 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4566 10:02:10.640784 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4567 10:02:10.640870 ==
4568 10:02:10.643880 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 10:02:10.647424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 10:02:10.647533 ==
4571 10:02:10.647627 DQS Delay:
4572 10:02:10.650635 DQS0 = 0, DQS1 = 0
4573 10:02:10.650720 DQM Delay:
4574 10:02:10.653875 DQM0 = 46, DQM1 = 36
4575 10:02:10.653971 DQ Delay:
4576 10:02:10.656980 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4577 10:02:10.660692 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4578 10:02:10.663906 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4579 10:02:10.667140 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4580 10:02:10.667223
4581 10:02:10.667289
4582 10:02:10.667350 ==
4583 10:02:10.669948 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 10:02:10.676812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 10:02:10.676896 ==
4586 10:02:10.676985
4587 10:02:10.677060
4588 10:02:10.677118 TX Vref Scan disable
4589 10:02:10.680448 == TX Byte 0 ==
4590 10:02:10.683718 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4591 10:02:10.689957 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4592 10:02:10.690071 == TX Byte 1 ==
4593 10:02:10.693258 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4594 10:02:10.699929 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4595 10:02:10.700015 ==
4596 10:02:10.703305 Dram Type= 6, Freq= 0, CH_1, rank 0
4597 10:02:10.706629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 10:02:10.706716 ==
4599 10:02:10.706782
4600 10:02:10.706844
4601 10:02:10.710071 TX Vref Scan disable
4602 10:02:10.713218 == TX Byte 0 ==
4603 10:02:10.716856 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4604 10:02:10.720291 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4605 10:02:10.723116 == TX Byte 1 ==
4606 10:02:10.726626 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4607 10:02:10.730142 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4608 10:02:10.730227
4609 10:02:10.730294 [DATLAT]
4610 10:02:10.733329 Freq=600, CH1 RK0
4611 10:02:10.733413
4612 10:02:10.736191 DATLAT Default: 0x9
4613 10:02:10.736274 0, 0xFFFF, sum = 0
4614 10:02:10.739530 1, 0xFFFF, sum = 0
4615 10:02:10.739619 2, 0xFFFF, sum = 0
4616 10:02:10.743317 3, 0xFFFF, sum = 0
4617 10:02:10.743403 4, 0xFFFF, sum = 0
4618 10:02:10.746613 5, 0xFFFF, sum = 0
4619 10:02:10.746698 6, 0xFFFF, sum = 0
4620 10:02:10.749407 7, 0xFFFF, sum = 0
4621 10:02:10.749491 8, 0x0, sum = 1
4622 10:02:10.752813 9, 0x0, sum = 2
4623 10:02:10.752898 10, 0x0, sum = 3
4624 10:02:10.756293 11, 0x0, sum = 4
4625 10:02:10.756378 best_step = 9
4626 10:02:10.756442
4627 10:02:10.756502 ==
4628 10:02:10.759420 Dram Type= 6, Freq= 0, CH_1, rank 0
4629 10:02:10.762463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 10:02:10.762547 ==
4631 10:02:10.765812 RX Vref Scan: 1
4632 10:02:10.765895
4633 10:02:10.768899 RX Vref 0 -> 0, step: 1
4634 10:02:10.768983
4635 10:02:10.772185 RX Delay -195 -> 252, step: 8
4636 10:02:10.772268
4637 10:02:10.775841 Set Vref, RX VrefLevel [Byte0]: 47
4638 10:02:10.778904 [Byte1]: 53
4639 10:02:10.779013
4640 10:02:10.782119 Final RX Vref Byte 0 = 47 to rank0
4641 10:02:10.785531 Final RX Vref Byte 1 = 53 to rank0
4642 10:02:10.788915 Final RX Vref Byte 0 = 47 to rank1
4643 10:02:10.792307 Final RX Vref Byte 1 = 53 to rank1==
4644 10:02:10.795778 Dram Type= 6, Freq= 0, CH_1, rank 0
4645 10:02:10.799122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 10:02:10.799206 ==
4647 10:02:10.801732 DQS Delay:
4648 10:02:10.801815 DQS0 = 0, DQS1 = 0
4649 10:02:10.801881 DQM Delay:
4650 10:02:10.805759 DQM0 = 47, DQM1 = 37
4651 10:02:10.805843 DQ Delay:
4652 10:02:10.808447 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =44
4653 10:02:10.811905 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =40
4654 10:02:10.815328 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4655 10:02:10.818419 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =48
4656 10:02:10.818502
4657 10:02:10.818566
4658 10:02:10.828672 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e34, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4659 10:02:10.832088 CH1 RK0: MR19=808, MR18=4E34
4660 10:02:10.834935 CH1_RK0: MR19=0x808, MR18=0x4E34, DQSOSC=395, MR23=63, INC=168, DEC=112
4661 10:02:10.835023
4662 10:02:10.838421 ----->DramcWriteLeveling(PI) begin...
4663 10:02:10.841982 ==
4664 10:02:10.844775 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 10:02:10.848394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 10:02:10.848481 ==
4667 10:02:10.851430 Write leveling (Byte 0): 28 => 28
4668 10:02:10.854894 Write leveling (Byte 1): 28 => 28
4669 10:02:10.858112 DramcWriteLeveling(PI) end<-----
4670 10:02:10.858195
4671 10:02:10.858260 ==
4672 10:02:10.861132 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 10:02:10.864655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 10:02:10.864739 ==
4675 10:02:10.868107 [Gating] SW mode calibration
4676 10:02:10.874838 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4677 10:02:10.881211 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4678 10:02:10.884654 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4679 10:02:10.887709 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4680 10:02:10.894350 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4681 10:02:10.897843 0 9 12 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
4682 10:02:10.901066 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4683 10:02:10.907623 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 10:02:10.910694 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 10:02:10.914177 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 10:02:10.920680 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 10:02:10.923930 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4688 10:02:10.927439 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4689 10:02:10.934144 0 10 12 | B1->B0 | 3737 302f | 0 1 | (0 0) (0 0)
4690 10:02:10.937492 0 10 16 | B1->B0 | 4646 4040 | 0 1 | (0 0) (0 0)
4691 10:02:10.941017 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 10:02:10.947639 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 10:02:10.950838 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 10:02:10.953755 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 10:02:10.960606 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 10:02:10.963983 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 10:02:10.967182 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4698 10:02:10.973588 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 10:02:10.976806 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 10:02:10.980259 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 10:02:10.987017 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 10:02:10.990259 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 10:02:10.993434 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 10:02:11.000375 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 10:02:11.003663 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 10:02:11.006945 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 10:02:11.013801 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 10:02:11.016405 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 10:02:11.019855 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 10:02:11.026461 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 10:02:11.029957 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 10:02:11.033201 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 10:02:11.036254 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4714 10:02:11.040324 Total UI for P1: 0, mck2ui 16
4715 10:02:11.042986 best dqsien dly found for B1: ( 0, 13, 10)
4716 10:02:11.050175 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4717 10:02:11.052822 Total UI for P1: 0, mck2ui 16
4718 10:02:11.056156 best dqsien dly found for B0: ( 0, 13, 12)
4719 10:02:11.059475 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4720 10:02:11.063022 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4721 10:02:11.063114
4722 10:02:11.066388 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4723 10:02:11.069464 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4724 10:02:11.072700 [Gating] SW calibration Done
4725 10:02:11.072798 ==
4726 10:02:11.076390 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 10:02:11.079655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 10:02:11.079740 ==
4729 10:02:11.082785 RX Vref Scan: 0
4730 10:02:11.082868
4731 10:02:11.086087 RX Vref 0 -> 0, step: 1
4732 10:02:11.086170
4733 10:02:11.089327 RX Delay -230 -> 252, step: 16
4734 10:02:11.092797 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4735 10:02:11.096395 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4736 10:02:11.099104 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4737 10:02:11.102257 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4738 10:02:11.109400 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4739 10:02:11.112386 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4740 10:02:11.116035 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4741 10:02:11.118852 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4742 10:02:11.125533 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4743 10:02:11.129260 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4744 10:02:11.132090 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4745 10:02:11.135543 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4746 10:02:11.143068 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4747 10:02:11.145502 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4748 10:02:11.148406 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4749 10:02:11.152096 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4750 10:02:11.152197 ==
4751 10:02:11.155362 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 10:02:11.161789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 10:02:11.161866 ==
4754 10:02:11.161930 DQS Delay:
4755 10:02:11.165311 DQS0 = 0, DQS1 = 0
4756 10:02:11.165388 DQM Delay:
4757 10:02:11.168629 DQM0 = 43, DQM1 = 38
4758 10:02:11.168710 DQ Delay:
4759 10:02:11.171810 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4760 10:02:11.174872 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4761 10:02:11.178029 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4762 10:02:11.181482 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4763 10:02:11.181565
4764 10:02:11.181629
4765 10:02:11.181688 ==
4766 10:02:11.184974 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 10:02:11.188439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 10:02:11.188580 ==
4769 10:02:11.188648
4770 10:02:11.188709
4771 10:02:11.191456 TX Vref Scan disable
4772 10:02:11.194942 == TX Byte 0 ==
4773 10:02:11.198311 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4774 10:02:11.201549 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4775 10:02:11.204633 == TX Byte 1 ==
4776 10:02:11.207953 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4777 10:02:11.211162 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4778 10:02:11.211245 ==
4779 10:02:11.214474 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 10:02:11.221430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 10:02:11.221513 ==
4782 10:02:11.221602
4783 10:02:11.221707
4784 10:02:11.221765 TX Vref Scan disable
4785 10:02:11.225203 == TX Byte 0 ==
4786 10:02:11.228794 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4787 10:02:11.235437 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4788 10:02:11.235520 == TX Byte 1 ==
4789 10:02:11.238725 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4790 10:02:11.245308 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4791 10:02:11.245390
4792 10:02:11.245455 [DATLAT]
4793 10:02:11.245515 Freq=600, CH1 RK1
4794 10:02:11.245573
4795 10:02:11.248951 DATLAT Default: 0x9
4796 10:02:11.249034 0, 0xFFFF, sum = 0
4797 10:02:11.252013 1, 0xFFFF, sum = 0
4798 10:02:11.255739 2, 0xFFFF, sum = 0
4799 10:02:11.255822 3, 0xFFFF, sum = 0
4800 10:02:11.258748 4, 0xFFFF, sum = 0
4801 10:02:11.258832 5, 0xFFFF, sum = 0
4802 10:02:11.261548 6, 0xFFFF, sum = 0
4803 10:02:11.261631 7, 0xFFFF, sum = 0
4804 10:02:11.265060 8, 0x0, sum = 1
4805 10:02:11.265143 9, 0x0, sum = 2
4806 10:02:11.268070 10, 0x0, sum = 3
4807 10:02:11.268154 11, 0x0, sum = 4
4808 10:02:11.268221 best_step = 9
4809 10:02:11.268281
4810 10:02:11.271344 ==
4811 10:02:11.275065 Dram Type= 6, Freq= 0, CH_1, rank 1
4812 10:02:11.277996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4813 10:02:11.278079 ==
4814 10:02:11.278144 RX Vref Scan: 0
4815 10:02:11.278204
4816 10:02:11.281862 RX Vref 0 -> 0, step: 1
4817 10:02:11.281944
4818 10:02:11.285062 RX Delay -179 -> 252, step: 8
4819 10:02:11.291388 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4820 10:02:11.294771 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4821 10:02:11.297810 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4822 10:02:11.301680 iDelay=213, Bit 3, Center 44 (-99 ~ 188) 288
4823 10:02:11.304699 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4824 10:02:11.311112 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4825 10:02:11.314515 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4826 10:02:11.318342 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4827 10:02:11.321704 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4828 10:02:11.324478 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4829 10:02:11.330757 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4830 10:02:11.334446 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4831 10:02:11.337710 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4832 10:02:11.340923 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4833 10:02:11.347605 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4834 10:02:11.351040 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4835 10:02:11.351123 ==
4836 10:02:11.353886 Dram Type= 6, Freq= 0, CH_1, rank 1
4837 10:02:11.357463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4838 10:02:11.357546 ==
4839 10:02:11.360607 DQS Delay:
4840 10:02:11.360690 DQS0 = 0, DQS1 = 0
4841 10:02:11.363458 DQM Delay:
4842 10:02:11.363539 DQM0 = 46, DQM1 = 36
4843 10:02:11.367096 DQ Delay:
4844 10:02:11.367179 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4845 10:02:11.370537 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4846 10:02:11.373552 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4847 10:02:11.376774 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4848 10:02:11.376857
4849 10:02:11.380384
4850 10:02:11.387130 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4851 10:02:11.390289 CH1 RK1: MR19=808, MR18=2D21
4852 10:02:11.397025 CH1_RK1: MR19=0x808, MR18=0x2D21, DQSOSC=401, MR23=63, INC=163, DEC=108
4853 10:02:11.400435 [RxdqsGatingPostProcess] freq 600
4854 10:02:11.403499 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4855 10:02:11.406988 Pre-setting of DQS Precalculation
4856 10:02:11.413963 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4857 10:02:11.419981 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4858 10:02:11.426883 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4859 10:02:11.426967
4860 10:02:11.427032
4861 10:02:11.429787 [Calibration Summary] 1200 Mbps
4862 10:02:11.429871 CH 0, Rank 0
4863 10:02:11.433029 SW Impedance : PASS
4864 10:02:11.436491 DUTY Scan : NO K
4865 10:02:11.436584 ZQ Calibration : PASS
4866 10:02:11.439804 Jitter Meter : NO K
4867 10:02:11.443105 CBT Training : PASS
4868 10:02:11.443188 Write leveling : PASS
4869 10:02:11.446610 RX DQS gating : PASS
4870 10:02:11.446711 RX DQ/DQS(RDDQC) : PASS
4871 10:02:11.449911 TX DQ/DQS : PASS
4872 10:02:11.453055 RX DATLAT : PASS
4873 10:02:11.453171 RX DQ/DQS(Engine): PASS
4874 10:02:11.456820 TX OE : NO K
4875 10:02:11.456903 All Pass.
4876 10:02:11.456968
4877 10:02:11.459530 CH 0, Rank 1
4878 10:02:11.459612 SW Impedance : PASS
4879 10:02:11.462774 DUTY Scan : NO K
4880 10:02:11.466714 ZQ Calibration : PASS
4881 10:02:11.466799 Jitter Meter : NO K
4882 10:02:11.469359 CBT Training : PASS
4883 10:02:11.472953 Write leveling : PASS
4884 10:02:11.473037 RX DQS gating : PASS
4885 10:02:11.475915 RX DQ/DQS(RDDQC) : PASS
4886 10:02:11.479487 TX DQ/DQS : PASS
4887 10:02:11.479570 RX DATLAT : PASS
4888 10:02:11.482669 RX DQ/DQS(Engine): PASS
4889 10:02:11.486044 TX OE : NO K
4890 10:02:11.486127 All Pass.
4891 10:02:11.486192
4892 10:02:11.486252 CH 1, Rank 0
4893 10:02:11.489291 SW Impedance : PASS
4894 10:02:11.493236 DUTY Scan : NO K
4895 10:02:11.493318 ZQ Calibration : PASS
4896 10:02:11.495849 Jitter Meter : NO K
4897 10:02:11.499741 CBT Training : PASS
4898 10:02:11.499824 Write leveling : PASS
4899 10:02:11.502246 RX DQS gating : PASS
4900 10:02:11.505755 RX DQ/DQS(RDDQC) : PASS
4901 10:02:11.505837 TX DQ/DQS : PASS
4902 10:02:11.509234 RX DATLAT : PASS
4903 10:02:11.512386 RX DQ/DQS(Engine): PASS
4904 10:02:11.512468 TX OE : NO K
4905 10:02:11.512569 All Pass.
4906 10:02:11.512630
4907 10:02:11.515747 CH 1, Rank 1
4908 10:02:11.519269 SW Impedance : PASS
4909 10:02:11.519351 DUTY Scan : NO K
4910 10:02:11.522741 ZQ Calibration : PASS
4911 10:02:11.522823 Jitter Meter : NO K
4912 10:02:11.525697 CBT Training : PASS
4913 10:02:11.529003 Write leveling : PASS
4914 10:02:11.529086 RX DQS gating : PASS
4915 10:02:11.532232 RX DQ/DQS(RDDQC) : PASS
4916 10:02:11.535560 TX DQ/DQS : PASS
4917 10:02:11.535643 RX DATLAT : PASS
4918 10:02:11.539729 RX DQ/DQS(Engine): PASS
4919 10:02:11.542149 TX OE : NO K
4920 10:02:11.542233 All Pass.
4921 10:02:11.542298
4922 10:02:11.545731 DramC Write-DBI off
4923 10:02:11.545813 PER_BANK_REFRESH: Hybrid Mode
4924 10:02:11.548743 TX_TRACKING: ON
4925 10:02:11.558458 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4926 10:02:11.561994 [FAST_K] Save calibration result to emmc
4927 10:02:11.566194 dramc_set_vcore_voltage set vcore to 662500
4928 10:02:11.566292 Read voltage for 933, 3
4929 10:02:11.568268 Vio18 = 0
4930 10:02:11.568377 Vcore = 662500
4931 10:02:11.568475 Vdram = 0
4932 10:02:11.572037 Vddq = 0
4933 10:02:11.572177 Vmddr = 0
4934 10:02:11.575692 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4935 10:02:11.581846 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4936 10:02:11.585454 MEM_TYPE=3, freq_sel=17
4937 10:02:11.588577 sv_algorithm_assistance_LP4_1600
4938 10:02:11.591695 ============ PULL DRAM RESETB DOWN ============
4939 10:02:11.596217 ========== PULL DRAM RESETB DOWN end =========
4940 10:02:11.601798 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4941 10:02:11.605103 ===================================
4942 10:02:11.605187 LPDDR4 DRAM CONFIGURATION
4943 10:02:11.608191 ===================================
4944 10:02:11.611837 EX_ROW_EN[0] = 0x0
4945 10:02:11.614928 EX_ROW_EN[1] = 0x0
4946 10:02:11.615010 LP4Y_EN = 0x0
4947 10:02:11.618080 WORK_FSP = 0x0
4948 10:02:11.618163 WL = 0x3
4949 10:02:11.621087 RL = 0x3
4950 10:02:11.621172 BL = 0x2
4951 10:02:11.624692 RPST = 0x0
4952 10:02:11.624808 RD_PRE = 0x0
4953 10:02:11.628009 WR_PRE = 0x1
4954 10:02:11.628091 WR_PST = 0x0
4955 10:02:11.631379 DBI_WR = 0x0
4956 10:02:11.631461 DBI_RD = 0x0
4957 10:02:11.634382 OTF = 0x1
4958 10:02:11.637699 ===================================
4959 10:02:11.640816 ===================================
4960 10:02:11.640899 ANA top config
4961 10:02:11.644076 ===================================
4962 10:02:11.647322 DLL_ASYNC_EN = 0
4963 10:02:11.650811 ALL_SLAVE_EN = 1
4964 10:02:11.654144 NEW_RANK_MODE = 1
4965 10:02:11.654228 DLL_IDLE_MODE = 1
4966 10:02:11.657570 LP45_APHY_COMB_EN = 1
4967 10:02:11.660555 TX_ODT_DIS = 1
4968 10:02:11.663976 NEW_8X_MODE = 1
4969 10:02:11.667469 ===================================
4970 10:02:11.670527 ===================================
4971 10:02:11.674392 data_rate = 1866
4972 10:02:11.674474 CKR = 1
4973 10:02:11.677202 DQ_P2S_RATIO = 8
4974 10:02:11.680731 ===================================
4975 10:02:11.683707 CA_P2S_RATIO = 8
4976 10:02:11.686964 DQ_CA_OPEN = 0
4977 10:02:11.690833 DQ_SEMI_OPEN = 0
4978 10:02:11.693957 CA_SEMI_OPEN = 0
4979 10:02:11.694040 CA_FULL_RATE = 0
4980 10:02:11.697226 DQ_CKDIV4_EN = 1
4981 10:02:11.700416 CA_CKDIV4_EN = 1
4982 10:02:11.703405 CA_PREDIV_EN = 0
4983 10:02:11.706955 PH8_DLY = 0
4984 10:02:11.710138 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4985 10:02:11.710221 DQ_AAMCK_DIV = 4
4986 10:02:11.713450 CA_AAMCK_DIV = 4
4987 10:02:11.716882 CA_ADMCK_DIV = 4
4988 10:02:11.719779 DQ_TRACK_CA_EN = 0
4989 10:02:11.723376 CA_PICK = 933
4990 10:02:11.726615 CA_MCKIO = 933
4991 10:02:11.729969 MCKIO_SEMI = 0
4992 10:02:11.733562 PLL_FREQ = 3732
4993 10:02:11.733657 DQ_UI_PI_RATIO = 32
4994 10:02:11.736347 CA_UI_PI_RATIO = 0
4995 10:02:11.739642 ===================================
4996 10:02:11.742672 ===================================
4997 10:02:11.746175 memory_type:LPDDR4
4998 10:02:11.749289 GP_NUM : 10
4999 10:02:11.749369 SRAM_EN : 1
5000 10:02:11.753161 MD32_EN : 0
5001 10:02:11.756192 ===================================
5002 10:02:11.759033 [ANA_INIT] >>>>>>>>>>>>>>
5003 10:02:11.759139 <<<<<< [CONFIGURE PHASE]: ANA_TX
5004 10:02:11.765609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5005 10:02:11.769293 ===================================
5006 10:02:11.769377 data_rate = 1866,PCW = 0X8f00
5007 10:02:11.772407 ===================================
5008 10:02:11.775735 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5009 10:02:11.782468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5010 10:02:11.788897 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5011 10:02:11.792288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5012 10:02:11.795851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5013 10:02:11.798878 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5014 10:02:11.802398 [ANA_INIT] flow start
5015 10:02:11.805389 [ANA_INIT] PLL >>>>>>>>
5016 10:02:11.805502 [ANA_INIT] PLL <<<<<<<<
5017 10:02:11.809064 [ANA_INIT] MIDPI >>>>>>>>
5018 10:02:11.812314 [ANA_INIT] MIDPI <<<<<<<<
5019 10:02:11.812425 [ANA_INIT] DLL >>>>>>>>
5020 10:02:11.815278 [ANA_INIT] flow end
5021 10:02:11.818424 ============ LP4 DIFF to SE enter ============
5022 10:02:11.821727 ============ LP4 DIFF to SE exit ============
5023 10:02:11.825219 [ANA_INIT] <<<<<<<<<<<<<
5024 10:02:11.828639 [Flow] Enable top DCM control >>>>>
5025 10:02:11.831798 [Flow] Enable top DCM control <<<<<
5026 10:02:11.835011 Enable DLL master slave shuffle
5027 10:02:11.841545 ==============================================================
5028 10:02:11.841627 Gating Mode config
5029 10:02:11.848404 ==============================================================
5030 10:02:11.848521 Config description:
5031 10:02:11.858036 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5032 10:02:11.865439 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5033 10:02:11.871800 SELPH_MODE 0: By rank 1: By Phase
5034 10:02:11.878337 ==============================================================
5035 10:02:11.878422 GAT_TRACK_EN = 1
5036 10:02:11.881427 RX_GATING_MODE = 2
5037 10:02:11.885062 RX_GATING_TRACK_MODE = 2
5038 10:02:11.888782 SELPH_MODE = 1
5039 10:02:11.891574 PICG_EARLY_EN = 1
5040 10:02:11.895011 VALID_LAT_VALUE = 1
5041 10:02:11.901299 ==============================================================
5042 10:02:11.904425 Enter into Gating configuration >>>>
5043 10:02:11.908335 Exit from Gating configuration <<<<
5044 10:02:11.910965 Enter into DVFS_PRE_config >>>>>
5045 10:02:11.921240 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5046 10:02:11.924490 Exit from DVFS_PRE_config <<<<<
5047 10:02:11.928053 Enter into PICG configuration >>>>
5048 10:02:11.931013 Exit from PICG configuration <<<<
5049 10:02:11.934150 [RX_INPUT] configuration >>>>>
5050 10:02:11.934233 [RX_INPUT] configuration <<<<<
5051 10:02:11.941213 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5052 10:02:11.947928 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5053 10:02:11.954164 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5054 10:02:11.957497 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5055 10:02:11.964087 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5056 10:02:11.970663 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5057 10:02:11.973940 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5058 10:02:11.980676 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5059 10:02:11.984180 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5060 10:02:11.987104 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5061 10:02:11.990743 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5062 10:02:11.997664 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5063 10:02:12.000645 ===================================
5064 10:02:12.000761 LPDDR4 DRAM CONFIGURATION
5065 10:02:12.003679 ===================================
5066 10:02:12.006875 EX_ROW_EN[0] = 0x0
5067 10:02:12.010592 EX_ROW_EN[1] = 0x0
5068 10:02:12.010700 LP4Y_EN = 0x0
5069 10:02:12.013974 WORK_FSP = 0x0
5070 10:02:12.014056 WL = 0x3
5071 10:02:12.016762 RL = 0x3
5072 10:02:12.016844 BL = 0x2
5073 10:02:12.019886 RPST = 0x0
5074 10:02:12.019969 RD_PRE = 0x0
5075 10:02:12.023139 WR_PRE = 0x1
5076 10:02:12.023222 WR_PST = 0x0
5077 10:02:12.026412 DBI_WR = 0x0
5078 10:02:12.026494 DBI_RD = 0x0
5079 10:02:12.029821 OTF = 0x1
5080 10:02:12.033553 ===================================
5081 10:02:12.036524 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5082 10:02:12.040023 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5083 10:02:12.046438 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5084 10:02:12.049619 ===================================
5085 10:02:12.049702 LPDDR4 DRAM CONFIGURATION
5086 10:02:12.053149 ===================================
5087 10:02:12.056287 EX_ROW_EN[0] = 0x10
5088 10:02:12.059780 EX_ROW_EN[1] = 0x0
5089 10:02:12.059862 LP4Y_EN = 0x0
5090 10:02:12.063206 WORK_FSP = 0x0
5091 10:02:12.063289 WL = 0x3
5092 10:02:12.066572 RL = 0x3
5093 10:02:12.066654 BL = 0x2
5094 10:02:12.069577 RPST = 0x0
5095 10:02:12.069659 RD_PRE = 0x0
5096 10:02:12.072805 WR_PRE = 0x1
5097 10:02:12.072887 WR_PST = 0x0
5098 10:02:12.076129 DBI_WR = 0x0
5099 10:02:12.076212 DBI_RD = 0x0
5100 10:02:12.079074 OTF = 0x1
5101 10:02:12.082382 ===================================
5102 10:02:12.088934 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5103 10:02:12.092664 nWR fixed to 30
5104 10:02:12.095943 [ModeRegInit_LP4] CH0 RK0
5105 10:02:12.096025 [ModeRegInit_LP4] CH0 RK1
5106 10:02:12.099278 [ModeRegInit_LP4] CH1 RK0
5107 10:02:12.102532 [ModeRegInit_LP4] CH1 RK1
5108 10:02:12.102622 match AC timing 9
5109 10:02:12.108759 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5110 10:02:12.112336 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5111 10:02:12.115605 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5112 10:02:12.122351 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5113 10:02:12.125366 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5114 10:02:12.125448 ==
5115 10:02:12.128716 Dram Type= 6, Freq= 0, CH_0, rank 0
5116 10:02:12.132076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 10:02:12.132197 ==
5118 10:02:12.138904 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5119 10:02:12.145633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5120 10:02:12.149070 [CA 0] Center 37 (7~68) winsize 62
5121 10:02:12.151979 [CA 1] Center 37 (7~68) winsize 62
5122 10:02:12.155356 [CA 2] Center 34 (4~65) winsize 62
5123 10:02:12.158433 [CA 3] Center 35 (5~65) winsize 61
5124 10:02:12.161952 [CA 4] Center 33 (3~64) winsize 62
5125 10:02:12.165494 [CA 5] Center 33 (3~63) winsize 61
5126 10:02:12.165577
5127 10:02:12.168847 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5128 10:02:12.168948
5129 10:02:12.172233 [CATrainingPosCal] consider 1 rank data
5130 10:02:12.175591 u2DelayCellTimex100 = 270/100 ps
5131 10:02:12.178701 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5132 10:02:12.181654 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5133 10:02:12.185129 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5134 10:02:12.188248 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5135 10:02:12.194667 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5136 10:02:12.197966 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5137 10:02:12.198069
5138 10:02:12.201507 CA PerBit enable=1, Macro0, CA PI delay=33
5139 10:02:12.201593
5140 10:02:12.204801 [CBTSetCACLKResult] CA Dly = 33
5141 10:02:12.204878 CS Dly: 7 (0~38)
5142 10:02:12.205009 ==
5143 10:02:12.208214 Dram Type= 6, Freq= 0, CH_0, rank 1
5144 10:02:12.214757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5145 10:02:12.214862 ==
5146 10:02:12.217761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5147 10:02:12.224458 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5148 10:02:12.228014 [CA 0] Center 37 (7~68) winsize 62
5149 10:02:12.231375 [CA 1] Center 37 (7~68) winsize 62
5150 10:02:12.234518 [CA 2] Center 34 (4~65) winsize 62
5151 10:02:12.238417 [CA 3] Center 34 (4~65) winsize 62
5152 10:02:12.241598 [CA 4] Center 33 (3~64) winsize 62
5153 10:02:12.244106 [CA 5] Center 33 (3~63) winsize 61
5154 10:02:12.244203
5155 10:02:12.247457 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5156 10:02:12.247540
5157 10:02:12.250840 [CATrainingPosCal] consider 2 rank data
5158 10:02:12.254440 u2DelayCellTimex100 = 270/100 ps
5159 10:02:12.257533 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5160 10:02:12.260931 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5161 10:02:12.267537 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5162 10:02:12.270928 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5163 10:02:12.275050 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5164 10:02:12.277285 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5165 10:02:12.277363
5166 10:02:12.280790 CA PerBit enable=1, Macro0, CA PI delay=33
5167 10:02:12.280879
5168 10:02:12.284172 [CBTSetCACLKResult] CA Dly = 33
5169 10:02:12.284243 CS Dly: 7 (0~39)
5170 10:02:12.287486
5171 10:02:12.290712 ----->DramcWriteLeveling(PI) begin...
5172 10:02:12.290787 ==
5173 10:02:12.293554 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 10:02:12.296825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 10:02:12.296906 ==
5176 10:02:12.300271 Write leveling (Byte 0): 33 => 33
5177 10:02:12.303684 Write leveling (Byte 1): 29 => 29
5178 10:02:12.306977 DramcWriteLeveling(PI) end<-----
5179 10:02:12.307055
5180 10:02:12.307122 ==
5181 10:02:12.310263 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 10:02:12.313616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 10:02:12.313693 ==
5184 10:02:12.317028 [Gating] SW mode calibration
5185 10:02:12.323296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5186 10:02:12.330200 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5187 10:02:12.333223 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
5188 10:02:12.336435 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5189 10:02:12.343025 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 10:02:12.346899 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 10:02:12.350074 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 10:02:12.357072 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5193 10:02:12.360154 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5194 10:02:12.363381 0 14 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
5195 10:02:12.370294 0 15 0 | B1->B0 | 3030 2525 | 1 1 | (1 1) (1 0)
5196 10:02:12.373212 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 10:02:12.376618 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 10:02:12.382908 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 10:02:12.386536 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 10:02:12.389926 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5201 10:02:12.396140 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5202 10:02:12.399431 0 15 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5203 10:02:12.402685 1 0 0 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
5204 10:02:12.409281 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 10:02:12.413078 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 10:02:12.416045 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 10:02:12.423216 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 10:02:12.425855 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 10:02:12.428886 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 10:02:12.435583 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5211 10:02:12.439205 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5212 10:02:12.442535 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5213 10:02:12.449240 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 10:02:12.451945 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 10:02:12.455675 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 10:02:12.462174 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 10:02:12.465494 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 10:02:12.468641 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 10:02:12.475680 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 10:02:12.478742 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 10:02:12.481978 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 10:02:12.488433 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 10:02:12.491581 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 10:02:12.495459 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 10:02:12.501595 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 10:02:12.504934 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5227 10:02:12.508414 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5228 10:02:12.511855 Total UI for P1: 0, mck2ui 16
5229 10:02:12.515062 best dqsien dly found for B0: ( 1, 2, 28)
5230 10:02:12.521440 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5231 10:02:12.524731 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5232 10:02:12.527924 Total UI for P1: 0, mck2ui 16
5233 10:02:12.531867 best dqsien dly found for B1: ( 1, 3, 2)
5234 10:02:12.534716 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5235 10:02:12.537854 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5236 10:02:12.537937
5237 10:02:12.541130 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5238 10:02:12.544527 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5239 10:02:12.548021 [Gating] SW calibration Done
5240 10:02:12.548102 ==
5241 10:02:12.551275 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 10:02:12.554387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 10:02:12.557721 ==
5244 10:02:12.557802 RX Vref Scan: 0
5245 10:02:12.557866
5246 10:02:12.561127 RX Vref 0 -> 0, step: 1
5247 10:02:12.561209
5248 10:02:12.564352 RX Delay -80 -> 252, step: 8
5249 10:02:12.567411 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5250 10:02:12.570617 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5251 10:02:12.574062 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5252 10:02:12.577395 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5253 10:02:12.580491 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5254 10:02:12.587169 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5255 10:02:12.590265 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5256 10:02:12.593814 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5257 10:02:12.597235 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5258 10:02:12.600230 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5259 10:02:12.607123 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5260 10:02:12.610507 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5261 10:02:12.613789 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5262 10:02:12.617104 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5263 10:02:12.619952 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5264 10:02:12.626861 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5265 10:02:12.626956 ==
5266 10:02:12.630835 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 10:02:12.633545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 10:02:12.633628 ==
5269 10:02:12.633692 DQS Delay:
5270 10:02:12.637378 DQS0 = 0, DQS1 = 0
5271 10:02:12.637475 DQM Delay:
5272 10:02:12.640197 DQM0 = 97, DQM1 = 86
5273 10:02:12.640279 DQ Delay:
5274 10:02:12.643838 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5275 10:02:12.647126 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5276 10:02:12.650216 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5277 10:02:12.653445 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5278 10:02:12.653526
5279 10:02:12.653590
5280 10:02:12.653649 ==
5281 10:02:12.656799 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 10:02:12.659672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 10:02:12.663054 ==
5284 10:02:12.663134
5285 10:02:12.663197
5286 10:02:12.663257 TX Vref Scan disable
5287 10:02:12.666397 == TX Byte 0 ==
5288 10:02:12.669489 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5289 10:02:12.676301 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5290 10:02:12.676410 == TX Byte 1 ==
5291 10:02:12.679657 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5292 10:02:12.686448 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5293 10:02:12.686554 ==
5294 10:02:12.689805 Dram Type= 6, Freq= 0, CH_0, rank 0
5295 10:02:12.693270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 10:02:12.693375 ==
5297 10:02:12.693467
5298 10:02:12.693557
5299 10:02:12.696377 TX Vref Scan disable
5300 10:02:12.696473 == TX Byte 0 ==
5301 10:02:12.702980 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5302 10:02:12.706062 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5303 10:02:12.709613 == TX Byte 1 ==
5304 10:02:12.712400 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5305 10:02:12.715749 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5306 10:02:12.715852
5307 10:02:12.715945 [DATLAT]
5308 10:02:12.719078 Freq=933, CH0 RK0
5309 10:02:12.719177
5310 10:02:12.719269 DATLAT Default: 0xd
5311 10:02:12.722492 0, 0xFFFF, sum = 0
5312 10:02:12.725786 1, 0xFFFF, sum = 0
5313 10:02:12.725893 2, 0xFFFF, sum = 0
5314 10:02:12.729014 3, 0xFFFF, sum = 0
5315 10:02:12.729116 4, 0xFFFF, sum = 0
5316 10:02:12.732234 5, 0xFFFF, sum = 0
5317 10:02:12.732336 6, 0xFFFF, sum = 0
5318 10:02:12.735732 7, 0xFFFF, sum = 0
5319 10:02:12.735835 8, 0xFFFF, sum = 0
5320 10:02:12.738771 9, 0xFFFF, sum = 0
5321 10:02:12.738875 10, 0x0, sum = 1
5322 10:02:12.742670 11, 0x0, sum = 2
5323 10:02:12.742783 12, 0x0, sum = 3
5324 10:02:12.745314 13, 0x0, sum = 4
5325 10:02:12.745404 best_step = 11
5326 10:02:12.745469
5327 10:02:12.745529 ==
5328 10:02:12.748815 Dram Type= 6, Freq= 0, CH_0, rank 0
5329 10:02:12.752073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 10:02:12.754988 ==
5331 10:02:12.755067 RX Vref Scan: 1
5332 10:02:12.755130
5333 10:02:12.758343 RX Vref 0 -> 0, step: 1
5334 10:02:12.758448
5335 10:02:12.762048 RX Delay -61 -> 252, step: 4
5336 10:02:12.762157
5337 10:02:12.762249 Set Vref, RX VrefLevel [Byte0]: 61
5338 10:02:12.764967 [Byte1]: 49
5339 10:02:12.770615
5340 10:02:12.770720 Final RX Vref Byte 0 = 61 to rank0
5341 10:02:12.773821 Final RX Vref Byte 1 = 49 to rank0
5342 10:02:12.777044 Final RX Vref Byte 0 = 61 to rank1
5343 10:02:12.780347 Final RX Vref Byte 1 = 49 to rank1==
5344 10:02:12.783473 Dram Type= 6, Freq= 0, CH_0, rank 0
5345 10:02:12.790380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 10:02:12.790493 ==
5347 10:02:12.790588 DQS Delay:
5348 10:02:12.793768 DQS0 = 0, DQS1 = 0
5349 10:02:12.793873 DQM Delay:
5350 10:02:12.793964 DQM0 = 96, DQM1 = 85
5351 10:02:12.797194 DQ Delay:
5352 10:02:12.800264 DQ0 =94, DQ1 =100, DQ2 =92, DQ3 =94
5353 10:02:12.803230 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =106
5354 10:02:12.806579 DQ8 =78, DQ9 =74, DQ10 =84, DQ11 =78
5355 10:02:12.809834 DQ12 =90, DQ13 =88, DQ14 =98, DQ15 =92
5356 10:02:12.809931
5357 10:02:12.810030
5358 10:02:12.816233 [DQSOSCAuto] RK0, (LSB)MR18= 0x2910, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5359 10:02:12.819492 CH0 RK0: MR19=505, MR18=2910
5360 10:02:12.826478 CH0_RK0: MR19=0x505, MR18=0x2910, DQSOSC=408, MR23=63, INC=65, DEC=43
5361 10:02:12.826582
5362 10:02:12.829459 ----->DramcWriteLeveling(PI) begin...
5363 10:02:12.829556 ==
5364 10:02:12.833040 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 10:02:12.836145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 10:02:12.836244 ==
5367 10:02:12.839533 Write leveling (Byte 0): 32 => 32
5368 10:02:12.842725 Write leveling (Byte 1): 30 => 30
5369 10:02:12.846368 DramcWriteLeveling(PI) end<-----
5370 10:02:12.846470
5371 10:02:12.846562 ==
5372 10:02:12.849470 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 10:02:12.852702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 10:02:12.855778 ==
5375 10:02:12.855878 [Gating] SW mode calibration
5376 10:02:12.865958 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5377 10:02:12.869430 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5378 10:02:12.872604 0 14 0 | B1->B0 | 2525 3131 | 1 0 | (0 0) (0 0)
5379 10:02:12.879113 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5380 10:02:12.882263 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 10:02:12.885494 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 10:02:12.891918 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5383 10:02:12.895652 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 10:02:12.901966 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5385 10:02:12.905178 0 14 28 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
5386 10:02:12.908845 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5387 10:02:12.912116 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 10:02:12.918287 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 10:02:12.922161 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 10:02:12.925095 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 10:02:12.931680 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 10:02:12.935033 0 15 24 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
5393 10:02:12.938596 0 15 28 | B1->B0 | 2727 3636 | 0 0 | (0 0) (0 0)
5394 10:02:12.945374 1 0 0 | B1->B0 | 4444 4343 | 0 0 | (0 0) (0 0)
5395 10:02:12.948503 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 10:02:12.951410 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 10:02:12.958075 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 10:02:12.961804 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 10:02:12.964621 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 10:02:12.971344 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 10:02:12.974626 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5402 10:02:12.977920 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5403 10:02:12.984584 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 10:02:12.988628 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 10:02:12.990991 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 10:02:12.997716 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 10:02:13.001073 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 10:02:13.004722 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 10:02:13.011321 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 10:02:13.014632 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 10:02:13.017882 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 10:02:13.024467 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 10:02:13.027813 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 10:02:13.031134 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 10:02:13.037448 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 10:02:13.040950 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 10:02:13.044616 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5418 10:02:13.050936 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5419 10:02:13.054160 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5420 10:02:13.057407 Total UI for P1: 0, mck2ui 16
5421 10:02:13.060716 best dqsien dly found for B0: ( 1, 2, 30)
5422 10:02:13.063821 Total UI for P1: 0, mck2ui 16
5423 10:02:13.067454 best dqsien dly found for B1: ( 1, 3, 0)
5424 10:02:13.070524 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5425 10:02:13.073953 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5426 10:02:13.074056
5427 10:02:13.077422 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5428 10:02:13.080922 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5429 10:02:13.083813 [Gating] SW calibration Done
5430 10:02:13.083922 ==
5431 10:02:13.087124 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 10:02:13.090256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 10:02:13.093580 ==
5434 10:02:13.093662 RX Vref Scan: 0
5435 10:02:13.093728
5436 10:02:13.097161 RX Vref 0 -> 0, step: 1
5437 10:02:13.097244
5438 10:02:13.100296 RX Delay -80 -> 252, step: 8
5439 10:02:13.103655 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5440 10:02:13.107425 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5441 10:02:13.110046 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5442 10:02:13.113809 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5443 10:02:13.116879 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5444 10:02:13.123297 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5445 10:02:13.126604 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5446 10:02:13.130332 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5447 10:02:13.132964 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5448 10:02:13.136191 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5449 10:02:13.143111 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5450 10:02:13.146089 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5451 10:02:13.149666 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5452 10:02:13.152813 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5453 10:02:13.155966 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5454 10:02:13.163029 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5455 10:02:13.163112 ==
5456 10:02:13.166131 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 10:02:13.169670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 10:02:13.169754 ==
5459 10:02:13.169819 DQS Delay:
5460 10:02:13.172805 DQS0 = 0, DQS1 = 0
5461 10:02:13.172889 DQM Delay:
5462 10:02:13.176018 DQM0 = 96, DQM1 = 87
5463 10:02:13.176131 DQ Delay:
5464 10:02:13.179150 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5465 10:02:13.182718 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5466 10:02:13.185752 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5467 10:02:13.189225 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5468 10:02:13.189320
5469 10:02:13.189385
5470 10:02:13.189444 ==
5471 10:02:13.192667 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 10:02:13.195813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 10:02:13.199358 ==
5474 10:02:13.199438
5475 10:02:13.199502
5476 10:02:13.199561 TX Vref Scan disable
5477 10:02:13.202671 == TX Byte 0 ==
5478 10:02:13.205901 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5479 10:02:13.209641 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5480 10:02:13.212663 == TX Byte 1 ==
5481 10:02:13.216320 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5482 10:02:13.218863 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5483 10:02:13.222333 ==
5484 10:02:13.225523 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 10:02:13.229380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 10:02:13.229462 ==
5487 10:02:13.229526
5488 10:02:13.229585
5489 10:02:13.232658 TX Vref Scan disable
5490 10:02:13.232740 == TX Byte 0 ==
5491 10:02:13.238474 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5492 10:02:13.242164 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5493 10:02:13.242248 == TX Byte 1 ==
5494 10:02:13.248350 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5495 10:02:13.252323 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5496 10:02:13.252398
5497 10:02:13.252468 [DATLAT]
5498 10:02:13.255497 Freq=933, CH0 RK1
5499 10:02:13.255576
5500 10:02:13.255642 DATLAT Default: 0xb
5501 10:02:13.258455 0, 0xFFFF, sum = 0
5502 10:02:13.258531 1, 0xFFFF, sum = 0
5503 10:02:13.262176 2, 0xFFFF, sum = 0
5504 10:02:13.265162 3, 0xFFFF, sum = 0
5505 10:02:13.265242 4, 0xFFFF, sum = 0
5506 10:02:13.268409 5, 0xFFFF, sum = 0
5507 10:02:13.268483 6, 0xFFFF, sum = 0
5508 10:02:13.271590 7, 0xFFFF, sum = 0
5509 10:02:13.271668 8, 0xFFFF, sum = 0
5510 10:02:13.274963 9, 0xFFFF, sum = 0
5511 10:02:13.275039 10, 0x0, sum = 1
5512 10:02:13.278530 11, 0x0, sum = 2
5513 10:02:13.278610 12, 0x0, sum = 3
5514 10:02:13.281465 13, 0x0, sum = 4
5515 10:02:13.281541 best_step = 11
5516 10:02:13.281606
5517 10:02:13.281665 ==
5518 10:02:13.284861 Dram Type= 6, Freq= 0, CH_0, rank 1
5519 10:02:13.288234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 10:02:13.288314 ==
5521 10:02:13.291321 RX Vref Scan: 0
5522 10:02:13.291400
5523 10:02:13.295137 RX Vref 0 -> 0, step: 1
5524 10:02:13.295219
5525 10:02:13.295282 RX Delay -61 -> 252, step: 4
5526 10:02:13.302456 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5527 10:02:13.306288 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5528 10:02:13.309502 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5529 10:02:13.312427 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5530 10:02:13.315964 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5531 10:02:13.322448 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5532 10:02:13.325485 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5533 10:02:13.329079 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5534 10:02:13.332156 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5535 10:02:13.336125 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5536 10:02:13.341928 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5537 10:02:13.345349 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5538 10:02:13.348483 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5539 10:02:13.351994 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5540 10:02:13.355284 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5541 10:02:13.362181 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5542 10:02:13.362283 ==
5543 10:02:13.365235 Dram Type= 6, Freq= 0, CH_0, rank 1
5544 10:02:13.368345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 10:02:13.368444 ==
5546 10:02:13.368510 DQS Delay:
5547 10:02:13.371595 DQS0 = 0, DQS1 = 0
5548 10:02:13.371677 DQM Delay:
5549 10:02:13.375742 DQM0 = 95, DQM1 = 86
5550 10:02:13.375824 DQ Delay:
5551 10:02:13.379259 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5552 10:02:13.381768 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5553 10:02:13.384923 DQ8 =80, DQ9 =74, DQ10 =86, DQ11 =80
5554 10:02:13.388467 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
5555 10:02:13.388596
5556 10:02:13.388688
5557 10:02:13.398499 [DQSOSCAuto] RK1, (LSB)MR18= 0x25f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5558 10:02:13.398608 CH0 RK1: MR19=504, MR18=25F7
5559 10:02:13.404674 CH0_RK1: MR19=0x504, MR18=0x25F7, DQSOSC=410, MR23=63, INC=64, DEC=42
5560 10:02:13.408251 [RxdqsGatingPostProcess] freq 933
5561 10:02:13.414569 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5562 10:02:13.418210 best DQS0 dly(2T, 0.5T) = (0, 10)
5563 10:02:13.421640 best DQS1 dly(2T, 0.5T) = (0, 11)
5564 10:02:13.425216 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5565 10:02:13.427967 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5566 10:02:13.428066 best DQS0 dly(2T, 0.5T) = (0, 10)
5567 10:02:13.431339 best DQS1 dly(2T, 0.5T) = (0, 11)
5568 10:02:13.434549 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5569 10:02:13.437968 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5570 10:02:13.441579 Pre-setting of DQS Precalculation
5571 10:02:13.448464 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5572 10:02:13.448596 ==
5573 10:02:13.451429 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 10:02:13.454500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 10:02:13.454610 ==
5576 10:02:13.461479 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5577 10:02:13.467975 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5578 10:02:13.471313 [CA 0] Center 37 (7~67) winsize 61
5579 10:02:13.474303 [CA 1] Center 37 (7~68) winsize 62
5580 10:02:13.477533 [CA 2] Center 34 (4~65) winsize 62
5581 10:02:13.481381 [CA 3] Center 33 (3~64) winsize 62
5582 10:02:13.484555 [CA 4] Center 34 (4~65) winsize 62
5583 10:02:13.484691 [CA 5] Center 33 (3~64) winsize 62
5584 10:02:13.487966
5585 10:02:13.491087 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5586 10:02:13.491179
5587 10:02:13.494082 [CATrainingPosCal] consider 1 rank data
5588 10:02:13.497633 u2DelayCellTimex100 = 270/100 ps
5589 10:02:13.500841 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5590 10:02:13.504553 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5591 10:02:13.507725 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5592 10:02:13.510887 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5593 10:02:13.514270 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5594 10:02:13.517615 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5595 10:02:13.517698
5596 10:02:13.521010 CA PerBit enable=1, Macro0, CA PI delay=33
5597 10:02:13.521093
5598 10:02:13.524444 [CBTSetCACLKResult] CA Dly = 33
5599 10:02:13.527423 CS Dly: 6 (0~37)
5600 10:02:13.527504 ==
5601 10:02:13.530928 Dram Type= 6, Freq= 0, CH_1, rank 1
5602 10:02:13.534279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 10:02:13.534383 ==
5604 10:02:13.540665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5605 10:02:13.547471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5606 10:02:13.550710 [CA 0] Center 37 (7~67) winsize 61
5607 10:02:13.553929 [CA 1] Center 37 (7~68) winsize 62
5608 10:02:13.557543 [CA 2] Center 34 (4~65) winsize 62
5609 10:02:13.560354 [CA 3] Center 34 (3~65) winsize 63
5610 10:02:13.564124 [CA 4] Center 34 (4~65) winsize 62
5611 10:02:13.567272 [CA 5] Center 33 (3~64) winsize 62
5612 10:02:13.567354
5613 10:02:13.570362 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5614 10:02:13.570492
5615 10:02:13.573701 [CATrainingPosCal] consider 2 rank data
5616 10:02:13.576823 u2DelayCellTimex100 = 270/100 ps
5617 10:02:13.580181 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5618 10:02:13.583546 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5619 10:02:13.586765 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5620 10:02:13.590282 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5621 10:02:13.593318 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5622 10:02:13.599864 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5623 10:02:13.599946
5624 10:02:13.603463 CA PerBit enable=1, Macro0, CA PI delay=33
5625 10:02:13.603546
5626 10:02:13.606708 [CBTSetCACLKResult] CA Dly = 33
5627 10:02:13.606790 CS Dly: 7 (0~39)
5628 10:02:13.606856
5629 10:02:13.609662 ----->DramcWriteLeveling(PI) begin...
5630 10:02:13.609746 ==
5631 10:02:13.612939 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 10:02:13.619608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 10:02:13.619692 ==
5634 10:02:13.622896 Write leveling (Byte 0): 25 => 25
5635 10:02:13.622979 Write leveling (Byte 1): 26 => 26
5636 10:02:13.626361 DramcWriteLeveling(PI) end<-----
5637 10:02:13.626444
5638 10:02:13.626509 ==
5639 10:02:13.629473 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 10:02:13.636070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 10:02:13.636154 ==
5642 10:02:13.639404 [Gating] SW mode calibration
5643 10:02:13.646506 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5644 10:02:13.649159 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5645 10:02:13.655996 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 10:02:13.659312 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 10:02:13.662537 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 10:02:13.668809 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 10:02:13.672406 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 10:02:13.675721 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5651 10:02:13.682781 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 1)
5652 10:02:13.685838 0 14 28 | B1->B0 | 2f2f 2a2a | 0 0 | (1 1) (0 0)
5653 10:02:13.689755 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5654 10:02:13.695567 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 10:02:13.699112 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 10:02:13.702185 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 10:02:13.708788 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 10:02:13.711969 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5659 10:02:13.715483 0 15 24 | B1->B0 | 2625 2928 | 1 1 | (0 0) (0 0)
5660 10:02:13.722327 0 15 28 | B1->B0 | 3a39 3e3d | 1 1 | (0 0) (0 0)
5661 10:02:13.725414 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 10:02:13.728957 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 10:02:13.735202 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 10:02:13.738766 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 10:02:13.742132 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 10:02:13.748765 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5667 10:02:13.751921 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 10:02:13.755632 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5669 10:02:13.761609 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 10:02:13.764915 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 10:02:13.768306 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 10:02:13.774931 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 10:02:13.778397 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 10:02:13.781605 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 10:02:13.788145 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 10:02:13.791696 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 10:02:13.794907 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 10:02:13.801089 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 10:02:13.804861 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 10:02:13.808012 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 10:02:13.814523 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 10:02:13.817853 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 10:02:13.821090 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5684 10:02:13.827795 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5685 10:02:13.827877 Total UI for P1: 0, mck2ui 16
5686 10:02:13.834324 best dqsien dly found for B0: ( 1, 2, 24)
5687 10:02:13.837576 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5688 10:02:13.840698 Total UI for P1: 0, mck2ui 16
5689 10:02:13.844470 best dqsien dly found for B1: ( 1, 2, 26)
5690 10:02:13.847686 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5691 10:02:13.850725 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5692 10:02:13.850808
5693 10:02:13.854019 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5694 10:02:13.857325 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5695 10:02:13.860473 [Gating] SW calibration Done
5696 10:02:13.860599 ==
5697 10:02:13.863767 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 10:02:13.867145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 10:02:13.870520 ==
5700 10:02:13.870616 RX Vref Scan: 0
5701 10:02:13.870681
5702 10:02:13.873944 RX Vref 0 -> 0, step: 1
5703 10:02:13.874087
5704 10:02:13.874153 RX Delay -80 -> 252, step: 8
5705 10:02:13.880811 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5706 10:02:13.884234 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5707 10:02:13.887347 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5708 10:02:13.890557 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5709 10:02:13.893720 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5710 10:02:13.897280 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5711 10:02:13.904339 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5712 10:02:13.907214 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5713 10:02:13.910429 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5714 10:02:13.913759 iDelay=208, Bit 9, Center 79 (-24 ~ 183) 208
5715 10:02:13.916885 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5716 10:02:13.923727 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5717 10:02:13.926839 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5718 10:02:13.930177 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5719 10:02:13.933563 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5720 10:02:13.936699 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5721 10:02:13.936782 ==
5722 10:02:13.940691 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 10:02:13.946954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 10:02:13.947037 ==
5725 10:02:13.947103 DQS Delay:
5726 10:02:13.950425 DQS0 = 0, DQS1 = 0
5727 10:02:13.950508 DQM Delay:
5728 10:02:13.953574 DQM0 = 102, DQM1 = 90
5729 10:02:13.953688 DQ Delay:
5730 10:02:13.956687 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5731 10:02:13.959810 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5732 10:02:13.963394 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5733 10:02:13.966651 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5734 10:02:13.966749
5735 10:02:13.966829
5736 10:02:13.966889 ==
5737 10:02:13.969984 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 10:02:13.973414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 10:02:13.973498 ==
5740 10:02:13.973563
5741 10:02:13.973623
5742 10:02:13.976495 TX Vref Scan disable
5743 10:02:13.980020 == TX Byte 0 ==
5744 10:02:13.983353 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5745 10:02:13.986320 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5746 10:02:13.990215 == TX Byte 1 ==
5747 10:02:13.992926 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5748 10:02:13.996303 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5749 10:02:13.996386 ==
5750 10:02:13.999985 Dram Type= 6, Freq= 0, CH_1, rank 0
5751 10:02:14.006646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 10:02:14.006745 ==
5753 10:02:14.006810
5754 10:02:14.006870
5755 10:02:14.006927 TX Vref Scan disable
5756 10:02:14.010094 == TX Byte 0 ==
5757 10:02:14.013705 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5758 10:02:14.020165 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5759 10:02:14.020248 == TX Byte 1 ==
5760 10:02:14.023419 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5761 10:02:14.029816 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5762 10:02:14.029898
5763 10:02:14.029963 [DATLAT]
5764 10:02:14.030024 Freq=933, CH1 RK0
5765 10:02:14.030083
5766 10:02:14.033371 DATLAT Default: 0xd
5767 10:02:14.033458 0, 0xFFFF, sum = 0
5768 10:02:14.036620 1, 0xFFFF, sum = 0
5769 10:02:14.039713 2, 0xFFFF, sum = 0
5770 10:02:14.039796 3, 0xFFFF, sum = 0
5771 10:02:14.043589 4, 0xFFFF, sum = 0
5772 10:02:14.043673 5, 0xFFFF, sum = 0
5773 10:02:14.046684 6, 0xFFFF, sum = 0
5774 10:02:14.046767 7, 0xFFFF, sum = 0
5775 10:02:14.049941 8, 0xFFFF, sum = 0
5776 10:02:14.050025 9, 0xFFFF, sum = 0
5777 10:02:14.052981 10, 0x0, sum = 1
5778 10:02:14.053065 11, 0x0, sum = 2
5779 10:02:14.056632 12, 0x0, sum = 3
5780 10:02:14.056717 13, 0x0, sum = 4
5781 10:02:14.056782 best_step = 11
5782 10:02:14.059620
5783 10:02:14.059702 ==
5784 10:02:14.062788 Dram Type= 6, Freq= 0, CH_1, rank 0
5785 10:02:14.066083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5786 10:02:14.066166 ==
5787 10:02:14.066231 RX Vref Scan: 1
5788 10:02:14.066292
5789 10:02:14.069461 RX Vref 0 -> 0, step: 1
5790 10:02:14.069546
5791 10:02:14.073071 RX Delay -69 -> 252, step: 4
5792 10:02:14.073198
5793 10:02:14.075889 Set Vref, RX VrefLevel [Byte0]: 47
5794 10:02:14.079379 [Byte1]: 53
5795 10:02:14.082871
5796 10:02:14.082953 Final RX Vref Byte 0 = 47 to rank0
5797 10:02:14.086095 Final RX Vref Byte 1 = 53 to rank0
5798 10:02:14.089429 Final RX Vref Byte 0 = 47 to rank1
5799 10:02:14.092493 Final RX Vref Byte 1 = 53 to rank1==
5800 10:02:14.096258 Dram Type= 6, Freq= 0, CH_1, rank 0
5801 10:02:14.102496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 10:02:14.102575 ==
5803 10:02:14.102640 DQS Delay:
5804 10:02:14.106186 DQS0 = 0, DQS1 = 0
5805 10:02:14.106259 DQM Delay:
5806 10:02:14.106321 DQM0 = 101, DQM1 = 95
5807 10:02:14.109114 DQ Delay:
5808 10:02:14.112159 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5809 10:02:14.115533 DQ4 =100, DQ5 =112, DQ6 =108, DQ7 =98
5810 10:02:14.119561 DQ8 =82, DQ9 =86, DQ10 =98, DQ11 =86
5811 10:02:14.122259 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =104
5812 10:02:14.122329
5813 10:02:14.122393
5814 10:02:14.128903 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5815 10:02:14.132043 CH1 RK0: MR19=505, MR18=1A0A
5816 10:02:14.138627 CH1_RK0: MR19=0x505, MR18=0x1A0A, DQSOSC=413, MR23=63, INC=63, DEC=42
5817 10:02:14.138711
5818 10:02:14.142006 ----->DramcWriteLeveling(PI) begin...
5819 10:02:14.142091 ==
5820 10:02:14.145335 Dram Type= 6, Freq= 0, CH_1, rank 1
5821 10:02:14.149107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5822 10:02:14.151730 ==
5823 10:02:14.155440 Write leveling (Byte 0): 28 => 28
5824 10:02:14.155523 Write leveling (Byte 1): 29 => 29
5825 10:02:14.158567 DramcWriteLeveling(PI) end<-----
5826 10:02:14.158650
5827 10:02:14.158714 ==
5828 10:02:14.161888 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 10:02:14.168317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 10:02:14.168400 ==
5831 10:02:14.171383 [Gating] SW mode calibration
5832 10:02:14.178150 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5833 10:02:14.181603 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5834 10:02:14.188284 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5835 10:02:14.191526 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 10:02:14.194576 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 10:02:14.200922 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 10:02:14.204197 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5839 10:02:14.207869 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5840 10:02:14.214052 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (0 1) (1 1)
5841 10:02:14.217738 0 14 28 | B1->B0 | 2929 3030 | 0 0 | (1 1) (0 1)
5842 10:02:14.221135 0 15 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 0)
5843 10:02:14.227909 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 10:02:14.230759 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 10:02:14.234410 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 10:02:14.240834 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5847 10:02:14.243962 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5848 10:02:14.247099 0 15 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5849 10:02:14.254035 0 15 28 | B1->B0 | 4242 3030 | 0 0 | (0 0) (0 0)
5850 10:02:14.257458 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5851 10:02:14.260728 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 10:02:14.266864 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 10:02:14.270615 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 10:02:14.273903 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 10:02:14.280114 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5856 10:02:14.283656 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5857 10:02:14.286947 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5858 10:02:14.293387 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 10:02:14.296963 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 10:02:14.300067 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 10:02:14.306514 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 10:02:14.310133 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 10:02:14.313328 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 10:02:14.319747 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 10:02:14.323183 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 10:02:14.326536 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 10:02:14.333262 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 10:02:14.336470 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 10:02:14.339827 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 10:02:14.346711 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 10:02:14.349576 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 10:02:14.352983 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5873 10:02:14.359474 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5874 10:02:14.363252 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5875 10:02:14.366494 Total UI for P1: 0, mck2ui 16
5876 10:02:14.369500 best dqsien dly found for B0: ( 1, 2, 28)
5877 10:02:14.373263 Total UI for P1: 0, mck2ui 16
5878 10:02:14.376070 best dqsien dly found for B1: ( 1, 2, 26)
5879 10:02:14.379515 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5880 10:02:14.382593 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5881 10:02:14.382674
5882 10:02:14.386143 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5883 10:02:14.389168 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5884 10:02:14.392616 [Gating] SW calibration Done
5885 10:02:14.392698 ==
5886 10:02:14.395677 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 10:02:14.399205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 10:02:14.402508 ==
5889 10:02:14.402590 RX Vref Scan: 0
5890 10:02:14.402654
5891 10:02:14.405969 RX Vref 0 -> 0, step: 1
5892 10:02:14.406051
5893 10:02:14.409316 RX Delay -80 -> 252, step: 8
5894 10:02:14.413110 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5895 10:02:14.415837 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5896 10:02:14.419558 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5897 10:02:14.422442 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5898 10:02:14.425750 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5899 10:02:14.432391 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5900 10:02:14.435335 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5901 10:02:14.438645 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5902 10:02:14.442178 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5903 10:02:14.445320 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5904 10:02:14.452090 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5905 10:02:14.455343 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5906 10:02:14.458246 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5907 10:02:14.461814 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5908 10:02:14.465094 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5909 10:02:14.471803 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5910 10:02:14.471896 ==
5911 10:02:14.475048 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 10:02:14.478214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 10:02:14.478297 ==
5914 10:02:14.478363 DQS Delay:
5915 10:02:14.481387 DQS0 = 0, DQS1 = 0
5916 10:02:14.481468 DQM Delay:
5917 10:02:14.484707 DQM0 = 99, DQM1 = 92
5918 10:02:14.484789 DQ Delay:
5919 10:02:14.488280 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5920 10:02:14.491525 DQ4 =99, DQ5 =107, DQ6 =111, DQ7 =95
5921 10:02:14.494892 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =87
5922 10:02:14.498084 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =103
5923 10:02:14.498166
5924 10:02:14.498230
5925 10:02:14.498289 ==
5926 10:02:14.501604 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 10:02:14.504746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 10:02:14.508262 ==
5929 10:02:14.508344
5930 10:02:14.508408
5931 10:02:14.508467 TX Vref Scan disable
5932 10:02:14.511706 == TX Byte 0 ==
5933 10:02:14.514641 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5934 10:02:14.518415 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5935 10:02:14.521119 == TX Byte 1 ==
5936 10:02:14.524411 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5937 10:02:14.527704 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5938 10:02:14.531289 ==
5939 10:02:14.531379 Dram Type= 6, Freq= 0, CH_1, rank 1
5940 10:02:14.537593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5941 10:02:14.537674 ==
5942 10:02:14.537738
5943 10:02:14.537803
5944 10:02:14.541187 TX Vref Scan disable
5945 10:02:14.541294 == TX Byte 0 ==
5946 10:02:14.547593 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5947 10:02:14.550522 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5948 10:02:14.550628 == TX Byte 1 ==
5949 10:02:14.557408 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5950 10:02:14.560346 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5951 10:02:14.560449
5952 10:02:14.560581 [DATLAT]
5953 10:02:14.563764 Freq=933, CH1 RK1
5954 10:02:14.563870
5955 10:02:14.563963 DATLAT Default: 0xb
5956 10:02:14.567265 0, 0xFFFF, sum = 0
5957 10:02:14.567367 1, 0xFFFF, sum = 0
5958 10:02:14.570399 2, 0xFFFF, sum = 0
5959 10:02:14.570504 3, 0xFFFF, sum = 0
5960 10:02:14.574241 4, 0xFFFF, sum = 0
5961 10:02:14.576908 5, 0xFFFF, sum = 0
5962 10:02:14.577014 6, 0xFFFF, sum = 0
5963 10:02:14.580286 7, 0xFFFF, sum = 0
5964 10:02:14.580392 8, 0xFFFF, sum = 0
5965 10:02:14.584122 9, 0xFFFF, sum = 0
5966 10:02:14.584227 10, 0x0, sum = 1
5967 10:02:14.587158 11, 0x0, sum = 2
5968 10:02:14.587269 12, 0x0, sum = 3
5969 10:02:14.587364 13, 0x0, sum = 4
5970 10:02:14.590427 best_step = 11
5971 10:02:14.590527
5972 10:02:14.590628 ==
5973 10:02:14.593397 Dram Type= 6, Freq= 0, CH_1, rank 1
5974 10:02:14.596731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5975 10:02:14.596831 ==
5976 10:02:14.600445 RX Vref Scan: 0
5977 10:02:14.600579
5978 10:02:14.603230 RX Vref 0 -> 0, step: 1
5979 10:02:14.603328
5980 10:02:14.603421 RX Delay -61 -> 252, step: 4
5981 10:02:14.610931 iDelay=203, Bit 0, Center 106 (19 ~ 194) 176
5982 10:02:14.614451 iDelay=203, Bit 1, Center 96 (11 ~ 182) 172
5983 10:02:14.617680 iDelay=203, Bit 2, Center 92 (7 ~ 178) 172
5984 10:02:14.621243 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5985 10:02:14.624338 iDelay=203, Bit 4, Center 100 (11 ~ 190) 180
5986 10:02:14.631476 iDelay=203, Bit 5, Center 112 (27 ~ 198) 172
5987 10:02:14.634743 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5988 10:02:14.637700 iDelay=203, Bit 7, Center 98 (7 ~ 190) 184
5989 10:02:14.641001 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5990 10:02:14.644109 iDelay=203, Bit 9, Center 84 (-5 ~ 174) 180
5991 10:02:14.647578 iDelay=203, Bit 10, Center 96 (7 ~ 186) 180
5992 10:02:14.654217 iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180
5993 10:02:14.657269 iDelay=203, Bit 12, Center 102 (11 ~ 194) 184
5994 10:02:14.660697 iDelay=203, Bit 13, Center 102 (11 ~ 194) 184
5995 10:02:14.664405 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5996 10:02:14.670447 iDelay=203, Bit 15, Center 102 (11 ~ 194) 184
5997 10:02:14.670556 ==
5998 10:02:14.673889 Dram Type= 6, Freq= 0, CH_1, rank 1
5999 10:02:14.677302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6000 10:02:14.677407 ==
6001 10:02:14.677500 DQS Delay:
6002 10:02:14.680454 DQS0 = 0, DQS1 = 0
6003 10:02:14.680596 DQM Delay:
6004 10:02:14.684236 DQM0 = 102, DQM1 = 94
6005 10:02:14.684342 DQ Delay:
6006 10:02:14.686940 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
6007 10:02:14.690389 DQ4 =100, DQ5 =112, DQ6 =114, DQ7 =98
6008 10:02:14.693978 DQ8 =82, DQ9 =84, DQ10 =96, DQ11 =84
6009 10:02:14.696761 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
6010 10:02:14.696843
6011 10:02:14.696908
6012 10:02:14.706617 [DQSOSCAuto] RK1, (LSB)MR18= 0xa03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 418 ps
6013 10:02:14.710130 CH1 RK1: MR19=505, MR18=A03
6014 10:02:14.713412 CH1_RK1: MR19=0x505, MR18=0xA03, DQSOSC=418, MR23=63, INC=62, DEC=41
6015 10:02:14.716705 [RxdqsGatingPostProcess] freq 933
6016 10:02:14.723167 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6017 10:02:14.726631 best DQS0 dly(2T, 0.5T) = (0, 10)
6018 10:02:14.730299 best DQS1 dly(2T, 0.5T) = (0, 10)
6019 10:02:14.733510 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6020 10:02:14.737800 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6021 10:02:14.739824 best DQS0 dly(2T, 0.5T) = (0, 10)
6022 10:02:14.743319 best DQS1 dly(2T, 0.5T) = (0, 10)
6023 10:02:14.746641 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6024 10:02:14.750242 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6025 10:02:14.750324 Pre-setting of DQS Precalculation
6026 10:02:14.756198 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6027 10:02:14.762762 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6028 10:02:14.769677 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6029 10:02:14.769761
6030 10:02:14.769889
6031 10:02:14.772702 [Calibration Summary] 1866 Mbps
6032 10:02:14.776118 CH 0, Rank 0
6033 10:02:14.776200 SW Impedance : PASS
6034 10:02:14.779217 DUTY Scan : NO K
6035 10:02:14.782593 ZQ Calibration : PASS
6036 10:02:14.782676 Jitter Meter : NO K
6037 10:02:14.786007 CBT Training : PASS
6038 10:02:14.789275 Write leveling : PASS
6039 10:02:14.789358 RX DQS gating : PASS
6040 10:02:14.792551 RX DQ/DQS(RDDQC) : PASS
6041 10:02:14.795965 TX DQ/DQS : PASS
6042 10:02:14.796048 RX DATLAT : PASS
6043 10:02:14.799620 RX DQ/DQS(Engine): PASS
6044 10:02:14.802484 TX OE : NO K
6045 10:02:14.802566 All Pass.
6046 10:02:14.802632
6047 10:02:14.802692 CH 0, Rank 1
6048 10:02:14.805799 SW Impedance : PASS
6049 10:02:14.809146 DUTY Scan : NO K
6050 10:02:14.809228 ZQ Calibration : PASS
6051 10:02:14.812209 Jitter Meter : NO K
6052 10:02:14.815896 CBT Training : PASS
6053 10:02:14.815978 Write leveling : PASS
6054 10:02:14.818716 RX DQS gating : PASS
6055 10:02:14.818799 RX DQ/DQS(RDDQC) : PASS
6056 10:02:14.822037 TX DQ/DQS : PASS
6057 10:02:14.826005 RX DATLAT : PASS
6058 10:02:14.826087 RX DQ/DQS(Engine): PASS
6059 10:02:14.829145 TX OE : NO K
6060 10:02:14.829228 All Pass.
6061 10:02:14.829293
6062 10:02:14.832663 CH 1, Rank 0
6063 10:02:14.832746 SW Impedance : PASS
6064 10:02:14.835310 DUTY Scan : NO K
6065 10:02:14.838683 ZQ Calibration : PASS
6066 10:02:14.838765 Jitter Meter : NO K
6067 10:02:14.842433 CBT Training : PASS
6068 10:02:14.845261 Write leveling : PASS
6069 10:02:14.845344 RX DQS gating : PASS
6070 10:02:14.848964 RX DQ/DQS(RDDQC) : PASS
6071 10:02:14.851858 TX DQ/DQS : PASS
6072 10:02:14.851967 RX DATLAT : PASS
6073 10:02:14.855100 RX DQ/DQS(Engine): PASS
6074 10:02:14.858296 TX OE : NO K
6075 10:02:14.858375 All Pass.
6076 10:02:14.858438
6077 10:02:14.858514 CH 1, Rank 1
6078 10:02:14.862024 SW Impedance : PASS
6079 10:02:14.864972 DUTY Scan : NO K
6080 10:02:14.865049 ZQ Calibration : PASS
6081 10:02:14.868140 Jitter Meter : NO K
6082 10:02:14.871544 CBT Training : PASS
6083 10:02:14.871617 Write leveling : PASS
6084 10:02:14.874745 RX DQS gating : PASS
6085 10:02:14.878382 RX DQ/DQS(RDDQC) : PASS
6086 10:02:14.878489 TX DQ/DQS : PASS
6087 10:02:14.881592 RX DATLAT : PASS
6088 10:02:14.884943 RX DQ/DQS(Engine): PASS
6089 10:02:14.885046 TX OE : NO K
6090 10:02:14.885137 All Pass.
6091 10:02:14.888288
6092 10:02:14.888385 DramC Write-DBI off
6093 10:02:14.891214 PER_BANK_REFRESH: Hybrid Mode
6094 10:02:14.891318 TX_TRACKING: ON
6095 10:02:14.901285 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6096 10:02:14.904983 [FAST_K] Save calibration result to emmc
6097 10:02:14.908150 dramc_set_vcore_voltage set vcore to 650000
6098 10:02:14.911128 Read voltage for 400, 6
6099 10:02:14.911204 Vio18 = 0
6100 10:02:14.914479 Vcore = 650000
6101 10:02:14.914549 Vdram = 0
6102 10:02:14.914608 Vddq = 0
6103 10:02:14.914665 Vmddr = 0
6104 10:02:14.921076 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6105 10:02:14.927721 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6106 10:02:14.927803 MEM_TYPE=3, freq_sel=20
6107 10:02:14.931313 sv_algorithm_assistance_LP4_800
6108 10:02:14.934085 ============ PULL DRAM RESETB DOWN ============
6109 10:02:14.941235 ========== PULL DRAM RESETB DOWN end =========
6110 10:02:14.944792 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6111 10:02:14.948128 ===================================
6112 10:02:14.950874 LPDDR4 DRAM CONFIGURATION
6113 10:02:14.954160 ===================================
6114 10:02:14.954243 EX_ROW_EN[0] = 0x0
6115 10:02:14.957651 EX_ROW_EN[1] = 0x0
6116 10:02:14.957733 LP4Y_EN = 0x0
6117 10:02:14.961053 WORK_FSP = 0x0
6118 10:02:14.964048 WL = 0x2
6119 10:02:14.964130 RL = 0x2
6120 10:02:14.967770 BL = 0x2
6121 10:02:14.967852 RPST = 0x0
6122 10:02:14.970600 RD_PRE = 0x0
6123 10:02:14.970683 WR_PRE = 0x1
6124 10:02:14.974157 WR_PST = 0x0
6125 10:02:14.974240 DBI_WR = 0x0
6126 10:02:14.977240 DBI_RD = 0x0
6127 10:02:14.977322 OTF = 0x1
6128 10:02:14.980847 ===================================
6129 10:02:14.984176 ===================================
6130 10:02:14.987297 ANA top config
6131 10:02:14.990558 ===================================
6132 10:02:14.990641 DLL_ASYNC_EN = 0
6133 10:02:14.993924 ALL_SLAVE_EN = 1
6134 10:02:14.997140 NEW_RANK_MODE = 1
6135 10:02:15.000394 DLL_IDLE_MODE = 1
6136 10:02:15.003714 LP45_APHY_COMB_EN = 1
6137 10:02:15.003797 TX_ODT_DIS = 1
6138 10:02:15.006905 NEW_8X_MODE = 1
6139 10:02:15.010170 ===================================
6140 10:02:15.013439 ===================================
6141 10:02:15.016980 data_rate = 800
6142 10:02:15.019845 CKR = 1
6143 10:02:15.023821 DQ_P2S_RATIO = 4
6144 10:02:15.026604 ===================================
6145 10:02:15.030163 CA_P2S_RATIO = 4
6146 10:02:15.030238 DQ_CA_OPEN = 0
6147 10:02:15.033364 DQ_SEMI_OPEN = 1
6148 10:02:15.036336 CA_SEMI_OPEN = 1
6149 10:02:15.039657 CA_FULL_RATE = 0
6150 10:02:15.042951 DQ_CKDIV4_EN = 0
6151 10:02:15.046529 CA_CKDIV4_EN = 1
6152 10:02:15.046630 CA_PREDIV_EN = 0
6153 10:02:15.049927 PH8_DLY = 0
6154 10:02:15.052806 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6155 10:02:15.056324 DQ_AAMCK_DIV = 0
6156 10:02:15.059785 CA_AAMCK_DIV = 0
6157 10:02:15.062902 CA_ADMCK_DIV = 4
6158 10:02:15.062983 DQ_TRACK_CA_EN = 0
6159 10:02:15.066077 CA_PICK = 800
6160 10:02:15.069432 CA_MCKIO = 400
6161 10:02:15.072744 MCKIO_SEMI = 400
6162 10:02:15.076148 PLL_FREQ = 3016
6163 10:02:15.079457 DQ_UI_PI_RATIO = 32
6164 10:02:15.082903 CA_UI_PI_RATIO = 32
6165 10:02:15.085828 ===================================
6166 10:02:15.089829 ===================================
6167 10:02:15.089932 memory_type:LPDDR4
6168 10:02:15.092803 GP_NUM : 10
6169 10:02:15.095867 SRAM_EN : 1
6170 10:02:15.095939 MD32_EN : 0
6171 10:02:15.099131 ===================================
6172 10:02:15.103128 [ANA_INIT] >>>>>>>>>>>>>>
6173 10:02:15.106289 <<<<<< [CONFIGURE PHASE]: ANA_TX
6174 10:02:15.109131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6175 10:02:15.112629 ===================================
6176 10:02:15.115970 data_rate = 800,PCW = 0X7400
6177 10:02:15.119226 ===================================
6178 10:02:15.122269 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6179 10:02:15.125985 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6180 10:02:15.138975 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6181 10:02:15.142790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6182 10:02:15.146036 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6183 10:02:15.149196 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6184 10:02:15.152093 [ANA_INIT] flow start
6185 10:02:15.155427 [ANA_INIT] PLL >>>>>>>>
6186 10:02:15.155534 [ANA_INIT] PLL <<<<<<<<
6187 10:02:15.158562 [ANA_INIT] MIDPI >>>>>>>>
6188 10:02:15.162487 [ANA_INIT] MIDPI <<<<<<<<
6189 10:02:15.162587 [ANA_INIT] DLL >>>>>>>>
6190 10:02:15.165586 [ANA_INIT] flow end
6191 10:02:15.168609 ============ LP4 DIFF to SE enter ============
6192 10:02:15.175152 ============ LP4 DIFF to SE exit ============
6193 10:02:15.175242 [ANA_INIT] <<<<<<<<<<<<<
6194 10:02:15.179276 [Flow] Enable top DCM control >>>>>
6195 10:02:15.182217 [Flow] Enable top DCM control <<<<<
6196 10:02:15.185451 Enable DLL master slave shuffle
6197 10:02:15.191787 ==============================================================
6198 10:02:15.191872 Gating Mode config
6199 10:02:15.198759 ==============================================================
6200 10:02:15.201986 Config description:
6201 10:02:15.208794 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6202 10:02:15.215464 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6203 10:02:15.221575 SELPH_MODE 0: By rank 1: By Phase
6204 10:02:15.228300 ==============================================================
6205 10:02:15.231474 GAT_TRACK_EN = 0
6206 10:02:15.231559 RX_GATING_MODE = 2
6207 10:02:15.234715 RX_GATING_TRACK_MODE = 2
6208 10:02:15.238265 SELPH_MODE = 1
6209 10:02:15.241360 PICG_EARLY_EN = 1
6210 10:02:15.244970 VALID_LAT_VALUE = 1
6211 10:02:15.251320 ==============================================================
6212 10:02:15.254571 Enter into Gating configuration >>>>
6213 10:02:15.258490 Exit from Gating configuration <<<<
6214 10:02:15.261065 Enter into DVFS_PRE_config >>>>>
6215 10:02:15.271011 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6216 10:02:15.274686 Exit from DVFS_PRE_config <<<<<
6217 10:02:15.277797 Enter into PICG configuration >>>>
6218 10:02:15.281291 Exit from PICG configuration <<<<
6219 10:02:15.284328 [RX_INPUT] configuration >>>>>
6220 10:02:15.287926 [RX_INPUT] configuration <<<<<
6221 10:02:15.290906 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6222 10:02:15.297447 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6223 10:02:15.304259 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6224 10:02:15.310547 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6225 10:02:15.313989 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6226 10:02:15.320535 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6227 10:02:15.323681 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6228 10:02:15.330232 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6229 10:02:15.333790 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6230 10:02:15.337168 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6231 10:02:15.340132 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6232 10:02:15.346902 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6233 10:02:15.350408 ===================================
6234 10:02:15.353443 LPDDR4 DRAM CONFIGURATION
6235 10:02:15.356760 ===================================
6236 10:02:15.356842 EX_ROW_EN[0] = 0x0
6237 10:02:15.360345 EX_ROW_EN[1] = 0x0
6238 10:02:15.360426 LP4Y_EN = 0x0
6239 10:02:15.363346 WORK_FSP = 0x0
6240 10:02:15.363427 WL = 0x2
6241 10:02:15.367164 RL = 0x2
6242 10:02:15.367246 BL = 0x2
6243 10:02:15.370186 RPST = 0x0
6244 10:02:15.370267 RD_PRE = 0x0
6245 10:02:15.373534 WR_PRE = 0x1
6246 10:02:15.373616 WR_PST = 0x0
6247 10:02:15.376727 DBI_WR = 0x0
6248 10:02:15.376840 DBI_RD = 0x0
6249 10:02:15.380401 OTF = 0x1
6250 10:02:15.383603 ===================================
6251 10:02:15.386772 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6252 10:02:15.390616 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6253 10:02:15.396819 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6254 10:02:15.399967 ===================================
6255 10:02:15.403059 LPDDR4 DRAM CONFIGURATION
6256 10:02:15.403141 ===================================
6257 10:02:15.406726 EX_ROW_EN[0] = 0x10
6258 10:02:15.410076 EX_ROW_EN[1] = 0x0
6259 10:02:15.410158 LP4Y_EN = 0x0
6260 10:02:15.413293 WORK_FSP = 0x0
6261 10:02:15.413374 WL = 0x2
6262 10:02:15.416601 RL = 0x2
6263 10:02:15.416684 BL = 0x2
6264 10:02:15.419916 RPST = 0x0
6265 10:02:15.419998 RD_PRE = 0x0
6266 10:02:15.423412 WR_PRE = 0x1
6267 10:02:15.423494 WR_PST = 0x0
6268 10:02:15.426299 DBI_WR = 0x0
6269 10:02:15.426381 DBI_RD = 0x0
6270 10:02:15.429894 OTF = 0x1
6271 10:02:15.432999 ===================================
6272 10:02:15.440068 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6273 10:02:15.443076 nWR fixed to 30
6274 10:02:15.445993 [ModeRegInit_LP4] CH0 RK0
6275 10:02:15.446075 [ModeRegInit_LP4] CH0 RK1
6276 10:02:15.449827 [ModeRegInit_LP4] CH1 RK0
6277 10:02:15.453051 [ModeRegInit_LP4] CH1 RK1
6278 10:02:15.453133 match AC timing 19
6279 10:02:15.459521 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6280 10:02:15.462647 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6281 10:02:15.466014 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6282 10:02:15.473019 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6283 10:02:15.476095 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6284 10:02:15.476178 ==
6285 10:02:15.479471 Dram Type= 6, Freq= 0, CH_0, rank 0
6286 10:02:15.482626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 10:02:15.482735 ==
6288 10:02:15.489202 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6289 10:02:15.496086 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6290 10:02:15.499471 [CA 0] Center 36 (8~64) winsize 57
6291 10:02:15.502459 [CA 1] Center 36 (8~64) winsize 57
6292 10:02:15.505721 [CA 2] Center 36 (8~64) winsize 57
6293 10:02:15.509152 [CA 3] Center 36 (8~64) winsize 57
6294 10:02:15.512467 [CA 4] Center 36 (8~64) winsize 57
6295 10:02:15.512630 [CA 5] Center 36 (8~64) winsize 57
6296 10:02:15.512739
6297 10:02:15.518966 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6298 10:02:15.519049
6299 10:02:15.522112 [CATrainingPosCal] consider 1 rank data
6300 10:02:15.525682 u2DelayCellTimex100 = 270/100 ps
6301 10:02:15.529061 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 10:02:15.531951 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 10:02:15.535411 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 10:02:15.538741 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 10:02:15.542133 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 10:02:15.545149 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 10:02:15.545231
6308 10:02:15.548481 CA PerBit enable=1, Macro0, CA PI delay=36
6309 10:02:15.551857
6310 10:02:15.551964 [CBTSetCACLKResult] CA Dly = 36
6311 10:02:15.555518 CS Dly: 1 (0~32)
6312 10:02:15.555642 ==
6313 10:02:15.558539 Dram Type= 6, Freq= 0, CH_0, rank 1
6314 10:02:15.561638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 10:02:15.561715 ==
6316 10:02:15.568131 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6317 10:02:15.574350 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6318 10:02:15.577840 [CA 0] Center 36 (8~64) winsize 57
6319 10:02:15.581421 [CA 1] Center 36 (8~64) winsize 57
6320 10:02:15.584638 [CA 2] Center 36 (8~64) winsize 57
6321 10:02:15.588009 [CA 3] Center 36 (8~64) winsize 57
6322 10:02:15.588120 [CA 4] Center 36 (8~64) winsize 57
6323 10:02:15.591078 [CA 5] Center 36 (8~64) winsize 57
6324 10:02:15.591176
6325 10:02:15.597949 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6326 10:02:15.598047
6327 10:02:15.601145 [CATrainingPosCal] consider 2 rank data
6328 10:02:15.604600 u2DelayCellTimex100 = 270/100 ps
6329 10:02:15.607881 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 10:02:15.611170 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 10:02:15.614503 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 10:02:15.617883 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 10:02:15.621053 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 10:02:15.624453 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 10:02:15.624555
6336 10:02:15.627553 CA PerBit enable=1, Macro0, CA PI delay=36
6337 10:02:15.627665
6338 10:02:15.630995 [CBTSetCACLKResult] CA Dly = 36
6339 10:02:15.634100 CS Dly: 1 (0~32)
6340 10:02:15.634174
6341 10:02:15.637192 ----->DramcWriteLeveling(PI) begin...
6342 10:02:15.637270 ==
6343 10:02:15.640662 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 10:02:15.644112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 10:02:15.644195 ==
6346 10:02:15.647564 Write leveling (Byte 0): 40 => 8
6347 10:02:15.650819 Write leveling (Byte 1): 32 => 0
6348 10:02:15.653830 DramcWriteLeveling(PI) end<-----
6349 10:02:15.653910
6350 10:02:15.653972 ==
6351 10:02:15.657113 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 10:02:15.660996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 10:02:15.661077 ==
6354 10:02:15.663700 [Gating] SW mode calibration
6355 10:02:15.670706 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6356 10:02:15.677214 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6357 10:02:15.680533 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6358 10:02:15.687789 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6359 10:02:15.690242 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6360 10:02:15.693674 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6361 10:02:15.700159 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6362 10:02:15.703524 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6363 10:02:15.706893 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6364 10:02:15.713442 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6365 10:02:15.716670 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6366 10:02:15.720351 Total UI for P1: 0, mck2ui 16
6367 10:02:15.723093 best dqsien dly found for B0: ( 0, 14, 24)
6368 10:02:15.726812 Total UI for P1: 0, mck2ui 16
6369 10:02:15.729882 best dqsien dly found for B1: ( 0, 14, 24)
6370 10:02:15.733049 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6371 10:02:15.736417 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6372 10:02:15.736538
6373 10:02:15.739950 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6374 10:02:15.742943 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6375 10:02:15.746284 [Gating] SW calibration Done
6376 10:02:15.746369 ==
6377 10:02:15.749578 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 10:02:15.753228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 10:02:15.756121 ==
6380 10:02:15.756195 RX Vref Scan: 0
6381 10:02:15.756257
6382 10:02:15.759630 RX Vref 0 -> 0, step: 1
6383 10:02:15.759705
6384 10:02:15.763049 RX Delay -410 -> 252, step: 16
6385 10:02:15.766320 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6386 10:02:15.769591 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6387 10:02:15.772724 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6388 10:02:15.779526 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6389 10:02:15.782825 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6390 10:02:15.786050 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6391 10:02:15.789685 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6392 10:02:15.796183 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6393 10:02:15.799289 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6394 10:02:15.803135 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6395 10:02:15.806081 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6396 10:02:15.812674 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6397 10:02:15.815945 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6398 10:02:15.819279 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6399 10:02:15.825662 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6400 10:02:15.829418 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6401 10:02:15.829499 ==
6402 10:02:15.832143 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 10:02:15.835730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 10:02:15.835809 ==
6405 10:02:15.839108 DQS Delay:
6406 10:02:15.839186 DQS0 = 43, DQS1 = 59
6407 10:02:15.839248 DQM Delay:
6408 10:02:15.842084 DQM0 = 9, DQM1 = 11
6409 10:02:15.842158 DQ Delay:
6410 10:02:15.845310 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6411 10:02:15.849715 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6412 10:02:15.852052 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6413 10:02:15.855306 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6414 10:02:15.855385
6415 10:02:15.855449
6416 10:02:15.855513 ==
6417 10:02:15.858915 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 10:02:15.862245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 10:02:15.865150 ==
6420 10:02:15.865271
6421 10:02:15.865335
6422 10:02:15.865395 TX Vref Scan disable
6423 10:02:15.868929 == TX Byte 0 ==
6424 10:02:15.871810 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6425 10:02:15.875357 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6426 10:02:15.879058 == TX Byte 1 ==
6427 10:02:15.882009 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6428 10:02:15.885199 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6429 10:02:15.885306 ==
6430 10:02:15.888547 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 10:02:15.895069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 10:02:15.895170 ==
6433 10:02:15.895266
6434 10:02:15.895353
6435 10:02:15.895446 TX Vref Scan disable
6436 10:02:15.898699 == TX Byte 0 ==
6437 10:02:15.901833 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6438 10:02:15.905166 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6439 10:02:15.908285 == TX Byte 1 ==
6440 10:02:15.911526 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6441 10:02:15.914845 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6442 10:02:15.914917
6443 10:02:15.918443 [DATLAT]
6444 10:02:15.918515 Freq=400, CH0 RK0
6445 10:02:15.918577
6446 10:02:15.921616 DATLAT Default: 0xf
6447 10:02:15.921733 0, 0xFFFF, sum = 0
6448 10:02:15.925015 1, 0xFFFF, sum = 0
6449 10:02:15.925088 2, 0xFFFF, sum = 0
6450 10:02:15.928285 3, 0xFFFF, sum = 0
6451 10:02:15.928364 4, 0xFFFF, sum = 0
6452 10:02:15.931363 5, 0xFFFF, sum = 0
6453 10:02:15.934863 6, 0xFFFF, sum = 0
6454 10:02:15.934938 7, 0xFFFF, sum = 0
6455 10:02:15.937688 8, 0xFFFF, sum = 0
6456 10:02:15.937759 9, 0xFFFF, sum = 0
6457 10:02:15.941516 10, 0xFFFF, sum = 0
6458 10:02:15.941586 11, 0xFFFF, sum = 0
6459 10:02:15.944674 12, 0xFFFF, sum = 0
6460 10:02:15.944750 13, 0x0, sum = 1
6461 10:02:15.947994 14, 0x0, sum = 2
6462 10:02:15.948079 15, 0x0, sum = 3
6463 10:02:15.951537 16, 0x0, sum = 4
6464 10:02:15.951612 best_step = 14
6465 10:02:15.951674
6466 10:02:15.951732 ==
6467 10:02:15.954483 Dram Type= 6, Freq= 0, CH_0, rank 0
6468 10:02:15.958176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 10:02:15.958263 ==
6470 10:02:15.961186 RX Vref Scan: 1
6471 10:02:15.961269
6472 10:02:15.964509 RX Vref 0 -> 0, step: 1
6473 10:02:15.964612
6474 10:02:15.964676 RX Delay -359 -> 252, step: 8
6475 10:02:15.967784
6476 10:02:15.967865 Set Vref, RX VrefLevel [Byte0]: 61
6477 10:02:15.971784 [Byte1]: 49
6478 10:02:15.977257
6479 10:02:15.977340 Final RX Vref Byte 0 = 61 to rank0
6480 10:02:15.980194 Final RX Vref Byte 1 = 49 to rank0
6481 10:02:15.983427 Final RX Vref Byte 0 = 61 to rank1
6482 10:02:15.986992 Final RX Vref Byte 1 = 49 to rank1==
6483 10:02:15.990319 Dram Type= 6, Freq= 0, CH_0, rank 0
6484 10:02:15.997074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 10:02:15.997157 ==
6486 10:02:15.997222 DQS Delay:
6487 10:02:16.000238 DQS0 = 44, DQS1 = 60
6488 10:02:16.000319 DQM Delay:
6489 10:02:16.000384 DQM0 = 8, DQM1 = 12
6490 10:02:16.003450 DQ Delay:
6491 10:02:16.006310 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6492 10:02:16.006391 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6493 10:02:16.009563 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6494 10:02:16.013417 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6495 10:02:16.013498
6496 10:02:16.016110
6497 10:02:16.023090 [DQSOSCAuto] RK0, (LSB)MR18= 0xbd81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6498 10:02:16.026052 CH0 RK0: MR19=C0C, MR18=BD81
6499 10:02:16.033090 CH0_RK0: MR19=0xC0C, MR18=0xBD81, DQSOSC=386, MR23=63, INC=396, DEC=264
6500 10:02:16.033172 ==
6501 10:02:16.036187 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 10:02:16.039665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 10:02:16.039747 ==
6504 10:02:16.042860 [Gating] SW mode calibration
6505 10:02:16.049240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6506 10:02:16.055875 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6507 10:02:16.059565 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6508 10:02:16.062528 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6509 10:02:16.069362 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6510 10:02:16.072191 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6511 10:02:16.075747 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 10:02:16.082643 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 10:02:16.085393 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6514 10:02:16.088772 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6515 10:02:16.095666 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6516 10:02:16.095749 Total UI for P1: 0, mck2ui 16
6517 10:02:16.102112 best dqsien dly found for B0: ( 0, 14, 24)
6518 10:02:16.102235 Total UI for P1: 0, mck2ui 16
6519 10:02:16.108859 best dqsien dly found for B1: ( 0, 14, 24)
6520 10:02:16.112145 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6521 10:02:16.114990 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6522 10:02:16.115072
6523 10:02:16.118447 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6524 10:02:16.121695 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6525 10:02:16.125014 [Gating] SW calibration Done
6526 10:02:16.125113 ==
6527 10:02:16.128232 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 10:02:16.131476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 10:02:16.131558 ==
6530 10:02:16.134951 RX Vref Scan: 0
6531 10:02:16.135033
6532 10:02:16.135097 RX Vref 0 -> 0, step: 1
6533 10:02:16.138468
6534 10:02:16.138548 RX Delay -410 -> 252, step: 16
6535 10:02:16.145065 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6536 10:02:16.148719 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6537 10:02:16.151627 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6538 10:02:16.157912 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6539 10:02:16.161086 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6540 10:02:16.164457 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6541 10:02:16.168168 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6542 10:02:16.174486 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6543 10:02:16.177593 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6544 10:02:16.180754 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6545 10:02:16.183966 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6546 10:02:16.190578 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6547 10:02:16.194231 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6548 10:02:16.197632 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6549 10:02:16.200496 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6550 10:02:16.207185 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6551 10:02:16.207268 ==
6552 10:02:16.210704 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 10:02:16.213670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 10:02:16.213753 ==
6555 10:02:16.216956 DQS Delay:
6556 10:02:16.217038 DQS0 = 43, DQS1 = 59
6557 10:02:16.217102 DQM Delay:
6558 10:02:16.220306 DQM0 = 10, DQM1 = 16
6559 10:02:16.220387 DQ Delay:
6560 10:02:16.223852 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6561 10:02:16.227006 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6562 10:02:16.230205 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6563 10:02:16.233690 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6564 10:02:16.233805
6565 10:02:16.233903
6566 10:02:16.233965 ==
6567 10:02:16.236714 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 10:02:16.239935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 10:02:16.240018 ==
6570 10:02:16.243662
6571 10:02:16.243743
6572 10:02:16.243806 TX Vref Scan disable
6573 10:02:16.246716 == TX Byte 0 ==
6574 10:02:16.250034 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6575 10:02:16.253205 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6576 10:02:16.256662 == TX Byte 1 ==
6577 10:02:16.259686 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6578 10:02:16.263339 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6579 10:02:16.263422 ==
6580 10:02:16.266499 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 10:02:16.272745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 10:02:16.272828 ==
6583 10:02:16.272892
6584 10:02:16.272955
6585 10:02:16.273013 TX Vref Scan disable
6586 10:02:16.276413 == TX Byte 0 ==
6587 10:02:16.280016 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6588 10:02:16.282742 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6589 10:02:16.285769 == TX Byte 1 ==
6590 10:02:16.289065 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6591 10:02:16.292758 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6592 10:02:16.292843
6593 10:02:16.295636 [DATLAT]
6594 10:02:16.295717 Freq=400, CH0 RK1
6595 10:02:16.295782
6596 10:02:16.300468 DATLAT Default: 0xe
6597 10:02:16.300599 0, 0xFFFF, sum = 0
6598 10:02:16.303490 1, 0xFFFF, sum = 0
6599 10:02:16.303573 2, 0xFFFF, sum = 0
6600 10:02:16.306239 3, 0xFFFF, sum = 0
6601 10:02:16.306322 4, 0xFFFF, sum = 0
6602 10:02:16.308959 5, 0xFFFF, sum = 0
6603 10:02:16.309042 6, 0xFFFF, sum = 0
6604 10:02:16.312453 7, 0xFFFF, sum = 0
6605 10:02:16.312593 8, 0xFFFF, sum = 0
6606 10:02:16.315494 9, 0xFFFF, sum = 0
6607 10:02:16.319015 10, 0xFFFF, sum = 0
6608 10:02:16.319097 11, 0xFFFF, sum = 0
6609 10:02:16.322326 12, 0xFFFF, sum = 0
6610 10:02:16.322409 13, 0x0, sum = 1
6611 10:02:16.325765 14, 0x0, sum = 2
6612 10:02:16.325848 15, 0x0, sum = 3
6613 10:02:16.325914 16, 0x0, sum = 4
6614 10:02:16.329346 best_step = 14
6615 10:02:16.329459
6616 10:02:16.329523 ==
6617 10:02:16.332226 Dram Type= 6, Freq= 0, CH_0, rank 1
6618 10:02:16.335692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 10:02:16.335774 ==
6620 10:02:16.338616 RX Vref Scan: 0
6621 10:02:16.338698
6622 10:02:16.342215 RX Vref 0 -> 0, step: 1
6623 10:02:16.342298
6624 10:02:16.342364 RX Delay -359 -> 252, step: 8
6625 10:02:16.350760 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6626 10:02:16.354586 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6627 10:02:16.357484 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6628 10:02:16.364173 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6629 10:02:16.367438 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6630 10:02:16.370959 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6631 10:02:16.373869 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6632 10:02:16.380603 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6633 10:02:16.383935 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6634 10:02:16.387185 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6635 10:02:16.390572 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6636 10:02:16.397415 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6637 10:02:16.400546 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6638 10:02:16.404200 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6639 10:02:16.407032 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6640 10:02:16.413700 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6641 10:02:16.413784 ==
6642 10:02:16.416856 Dram Type= 6, Freq= 0, CH_0, rank 1
6643 10:02:16.420548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 10:02:16.420645 ==
6645 10:02:16.420710 DQS Delay:
6646 10:02:16.423770 DQS0 = 44, DQS1 = 60
6647 10:02:16.423852 DQM Delay:
6648 10:02:16.426872 DQM0 = 8, DQM1 = 14
6649 10:02:16.426954 DQ Delay:
6650 10:02:16.430153 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =8
6651 10:02:16.433590 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6652 10:02:16.436539 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6653 10:02:16.439791 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6654 10:02:16.439873
6655 10:02:16.439937
6656 10:02:16.446307 [DQSOSCAuto] RK1, (LSB)MR18= 0xb946, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6657 10:02:16.450077 CH0 RK1: MR19=C0C, MR18=B946
6658 10:02:16.456605 CH0_RK1: MR19=0xC0C, MR18=0xB946, DQSOSC=386, MR23=63, INC=396, DEC=264
6659 10:02:16.459763 [RxdqsGatingPostProcess] freq 400
6660 10:02:16.466160 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6661 10:02:16.469874 best DQS0 dly(2T, 0.5T) = (0, 10)
6662 10:02:16.473108 best DQS1 dly(2T, 0.5T) = (0, 10)
6663 10:02:16.476716 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6664 10:02:16.476800 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6665 10:02:16.479785 best DQS0 dly(2T, 0.5T) = (0, 10)
6666 10:02:16.482825 best DQS1 dly(2T, 0.5T) = (0, 10)
6667 10:02:16.486505 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6668 10:02:16.489794 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6669 10:02:16.492919 Pre-setting of DQS Precalculation
6670 10:02:16.499592 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6671 10:02:16.499675 ==
6672 10:02:16.503334 Dram Type= 6, Freq= 0, CH_1, rank 0
6673 10:02:16.506568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 10:02:16.506685 ==
6675 10:02:16.512888 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6676 10:02:16.519673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6677 10:02:16.519786 [CA 0] Center 36 (8~64) winsize 57
6678 10:02:16.522741 [CA 1] Center 36 (8~64) winsize 57
6679 10:02:16.526808 [CA 2] Center 36 (8~64) winsize 57
6680 10:02:16.529264 [CA 3] Center 36 (8~64) winsize 57
6681 10:02:16.532474 [CA 4] Center 36 (8~64) winsize 57
6682 10:02:16.535888 [CA 5] Center 36 (8~64) winsize 57
6683 10:02:16.535975
6684 10:02:16.539048 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6685 10:02:16.539135
6686 10:02:16.542703 [CATrainingPosCal] consider 1 rank data
6687 10:02:16.545761 u2DelayCellTimex100 = 270/100 ps
6688 10:02:16.549498 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 10:02:16.556083 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 10:02:16.559218 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 10:02:16.562634 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 10:02:16.565991 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 10:02:16.568749 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 10:02:16.568819
6695 10:02:16.572056 CA PerBit enable=1, Macro0, CA PI delay=36
6696 10:02:16.572153
6697 10:02:16.575434 [CBTSetCACLKResult] CA Dly = 36
6698 10:02:16.579353 CS Dly: 1 (0~32)
6699 10:02:16.579452 ==
6700 10:02:16.582148 Dram Type= 6, Freq= 0, CH_1, rank 1
6701 10:02:16.585186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 10:02:16.585258 ==
6703 10:02:16.592188 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6704 10:02:16.595130 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6705 10:02:16.598642 [CA 0] Center 36 (8~64) winsize 57
6706 10:02:16.601884 [CA 1] Center 36 (8~64) winsize 57
6707 10:02:16.605348 [CA 2] Center 36 (8~64) winsize 57
6708 10:02:16.608395 [CA 3] Center 36 (8~64) winsize 57
6709 10:02:16.611921 [CA 4] Center 36 (8~64) winsize 57
6710 10:02:16.615266 [CA 5] Center 36 (8~64) winsize 57
6711 10:02:16.615367
6712 10:02:16.618822 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6713 10:02:16.618894
6714 10:02:16.622123 [CATrainingPosCal] consider 2 rank data
6715 10:02:16.625351 u2DelayCellTimex100 = 270/100 ps
6716 10:02:16.628293 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 10:02:16.631791 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 10:02:16.638139 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 10:02:16.641494 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 10:02:16.644628 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 10:02:16.648352 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 10:02:16.648462
6723 10:02:16.651578 CA PerBit enable=1, Macro0, CA PI delay=36
6724 10:02:16.651661
6725 10:02:16.654687 [CBTSetCACLKResult] CA Dly = 36
6726 10:02:16.654796 CS Dly: 1 (0~32)
6727 10:02:16.654889
6728 10:02:16.657841 ----->DramcWriteLeveling(PI) begin...
6729 10:02:16.661562 ==
6730 10:02:16.661645 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 10:02:16.667813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 10:02:16.667896 ==
6733 10:02:16.671770 Write leveling (Byte 0): 40 => 8
6734 10:02:16.674659 Write leveling (Byte 1): 40 => 8
6735 10:02:16.678048 DramcWriteLeveling(PI) end<-----
6736 10:02:16.678130
6737 10:02:16.678195 ==
6738 10:02:16.681313 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 10:02:16.685133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 10:02:16.685216 ==
6741 10:02:16.687877 [Gating] SW mode calibration
6742 10:02:16.694371 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6743 10:02:16.701083 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6744 10:02:16.704227 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6745 10:02:16.707754 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6746 10:02:16.711061 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6747 10:02:16.717423 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6748 10:02:16.720919 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6749 10:02:16.724648 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6750 10:02:16.731047 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6751 10:02:16.735122 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6752 10:02:16.737708 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6753 10:02:16.740596 Total UI for P1: 0, mck2ui 16
6754 10:02:16.743923 best dqsien dly found for B0: ( 0, 14, 24)
6755 10:02:16.747028 Total UI for P1: 0, mck2ui 16
6756 10:02:16.750285 best dqsien dly found for B1: ( 0, 14, 24)
6757 10:02:16.754014 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6758 10:02:16.760700 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6759 10:02:16.760785
6760 10:02:16.763941 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6761 10:02:16.767187 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6762 10:02:16.770262 [Gating] SW calibration Done
6763 10:02:16.770333 ==
6764 10:02:16.773869 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 10:02:16.776913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 10:02:16.777000 ==
6767 10:02:16.780677 RX Vref Scan: 0
6768 10:02:16.780756
6769 10:02:16.780818 RX Vref 0 -> 0, step: 1
6770 10:02:16.780876
6771 10:02:16.783421 RX Delay -410 -> 252, step: 16
6772 10:02:16.786856 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6773 10:02:16.793435 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6774 10:02:16.796762 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6775 10:02:16.799841 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6776 10:02:16.806909 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6777 10:02:16.809840 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6778 10:02:16.813351 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6779 10:02:16.816412 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6780 10:02:16.823149 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6781 10:02:16.826598 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6782 10:02:16.829869 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6783 10:02:16.833060 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6784 10:02:16.839553 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6785 10:02:16.842982 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6786 10:02:16.846344 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6787 10:02:16.849568 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6788 10:02:16.852885 ==
6789 10:02:16.855970 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 10:02:16.859202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 10:02:16.859329 ==
6792 10:02:16.859426 DQS Delay:
6793 10:02:16.862775 DQS0 = 43, DQS1 = 51
6794 10:02:16.862882 DQM Delay:
6795 10:02:16.866051 DQM0 = 12, DQM1 = 14
6796 10:02:16.866143 DQ Delay:
6797 10:02:16.869717 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6798 10:02:16.872966 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6799 10:02:16.876306 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6800 10:02:16.879539 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6801 10:02:16.879622
6802 10:02:16.879687
6803 10:02:16.879778 ==
6804 10:02:16.883027 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 10:02:16.885864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 10:02:16.885946 ==
6807 10:02:16.886012
6808 10:02:16.886072
6809 10:02:16.889054 TX Vref Scan disable
6810 10:02:16.889137 == TX Byte 0 ==
6811 10:02:16.895858 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6812 10:02:16.899140 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6813 10:02:16.899222 == TX Byte 1 ==
6814 10:02:16.905922 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6815 10:02:16.908906 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6816 10:02:16.908988 ==
6817 10:02:16.912386 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 10:02:16.915990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 10:02:16.916073 ==
6820 10:02:16.916138
6821 10:02:16.916198
6822 10:02:16.918749 TX Vref Scan disable
6823 10:02:16.918846 == TX Byte 0 ==
6824 10:02:16.925285 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6825 10:02:16.928830 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6826 10:02:16.928913 == TX Byte 1 ==
6827 10:02:16.935787 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6828 10:02:16.938733 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6829 10:02:16.938855
6830 10:02:16.938937 [DATLAT]
6831 10:02:16.942043 Freq=400, CH1 RK0
6832 10:02:16.942155
6833 10:02:16.942254 DATLAT Default: 0xf
6834 10:02:16.945403 0, 0xFFFF, sum = 0
6835 10:02:16.945487 1, 0xFFFF, sum = 0
6836 10:02:16.948636 2, 0xFFFF, sum = 0
6837 10:02:16.948751 3, 0xFFFF, sum = 0
6838 10:02:16.951929 4, 0xFFFF, sum = 0
6839 10:02:16.955064 5, 0xFFFF, sum = 0
6840 10:02:16.955148 6, 0xFFFF, sum = 0
6841 10:02:16.958338 7, 0xFFFF, sum = 0
6842 10:02:16.958437 8, 0xFFFF, sum = 0
6843 10:02:16.961461 9, 0xFFFF, sum = 0
6844 10:02:16.961545 10, 0xFFFF, sum = 0
6845 10:02:16.964987 11, 0xFFFF, sum = 0
6846 10:02:16.965071 12, 0xFFFF, sum = 0
6847 10:02:16.968179 13, 0x0, sum = 1
6848 10:02:16.968263 14, 0x0, sum = 2
6849 10:02:16.971930 15, 0x0, sum = 3
6850 10:02:16.972014 16, 0x0, sum = 4
6851 10:02:16.975221 best_step = 14
6852 10:02:16.975303
6853 10:02:16.975367 ==
6854 10:02:16.978053 Dram Type= 6, Freq= 0, CH_1, rank 0
6855 10:02:16.981829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 10:02:16.981913 ==
6857 10:02:16.981977 RX Vref Scan: 1
6858 10:02:16.984919
6859 10:02:16.985002 RX Vref 0 -> 0, step: 1
6860 10:02:16.985066
6861 10:02:16.988062 RX Delay -343 -> 252, step: 8
6862 10:02:16.988145
6863 10:02:16.991832 Set Vref, RX VrefLevel [Byte0]: 47
6864 10:02:16.994844 [Byte1]: 53
6865 10:02:16.999171
6866 10:02:16.999253 Final RX Vref Byte 0 = 47 to rank0
6867 10:02:17.002365 Final RX Vref Byte 1 = 53 to rank0
6868 10:02:17.005903 Final RX Vref Byte 0 = 47 to rank1
6869 10:02:17.008625 Final RX Vref Byte 1 = 53 to rank1==
6870 10:02:17.012279 Dram Type= 6, Freq= 0, CH_1, rank 0
6871 10:02:17.018660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 10:02:17.018829 ==
6873 10:02:17.018898 DQS Delay:
6874 10:02:17.022458 DQS0 = 44, DQS1 = 56
6875 10:02:17.022556 DQM Delay:
6876 10:02:17.022622 DQM0 = 7, DQM1 = 12
6877 10:02:17.025188 DQ Delay:
6878 10:02:17.029142 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6879 10:02:17.029224 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6880 10:02:17.031695 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6881 10:02:17.035711 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6882 10:02:17.035794
6883 10:02:17.038451
6884 10:02:17.044905 [DQSOSCAuto] RK0, (LSB)MR18= 0x9f75, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 389 ps
6885 10:02:17.048299 CH1 RK0: MR19=C0C, MR18=9F75
6886 10:02:17.055047 CH1_RK0: MR19=0xC0C, MR18=0x9F75, DQSOSC=389, MR23=63, INC=390, DEC=260
6887 10:02:17.055130 ==
6888 10:02:17.058213 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 10:02:17.061396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 10:02:17.061480 ==
6891 10:02:17.065090 [Gating] SW mode calibration
6892 10:02:17.071409 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6893 10:02:17.078285 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6894 10:02:17.081505 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6895 10:02:17.084958 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6896 10:02:17.090980 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6897 10:02:17.094885 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6898 10:02:17.097634 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6899 10:02:17.104507 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6900 10:02:17.107332 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6901 10:02:17.110465 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6902 10:02:17.117259 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6903 10:02:17.120335 Total UI for P1: 0, mck2ui 16
6904 10:02:17.123796 best dqsien dly found for B0: ( 0, 14, 24)
6905 10:02:17.123871 Total UI for P1: 0, mck2ui 16
6906 10:02:17.130321 best dqsien dly found for B1: ( 0, 14, 24)
6907 10:02:17.134271 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6908 10:02:17.137126 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6909 10:02:17.137237
6910 10:02:17.140760 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6911 10:02:17.144159 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6912 10:02:17.147514 [Gating] SW calibration Done
6913 10:02:17.147590 ==
6914 10:02:17.150573 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 10:02:17.153767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 10:02:17.153854 ==
6917 10:02:17.156808 RX Vref Scan: 0
6918 10:02:17.156914
6919 10:02:17.160407 RX Vref 0 -> 0, step: 1
6920 10:02:17.160536
6921 10:02:17.160644 RX Delay -410 -> 252, step: 16
6922 10:02:17.166712 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6923 10:02:17.170237 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6924 10:02:17.173258 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6925 10:02:17.180350 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6926 10:02:17.183655 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6927 10:02:17.186931 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6928 10:02:17.189763 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6929 10:02:17.196602 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6930 10:02:17.199733 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6931 10:02:17.203050 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6932 10:02:17.206016 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6933 10:02:17.213231 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6934 10:02:17.216094 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6935 10:02:17.219740 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6936 10:02:17.222874 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6937 10:02:17.229675 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6938 10:02:17.229778 ==
6939 10:02:17.233159 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 10:02:17.235916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 10:02:17.236004 ==
6942 10:02:17.239536 DQS Delay:
6943 10:02:17.239651 DQS0 = 51, DQS1 = 51
6944 10:02:17.239747 DQM Delay:
6945 10:02:17.242648 DQM0 = 19, DQM1 = 14
6946 10:02:17.242747 DQ Delay:
6947 10:02:17.246351 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6948 10:02:17.248993 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6949 10:02:17.252524 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6950 10:02:17.256378 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6951 10:02:17.256491
6952 10:02:17.256623
6953 10:02:17.256701 ==
6954 10:02:17.259487 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 10:02:17.262306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 10:02:17.265864 ==
6957 10:02:17.265953
6958 10:02:17.266016
6959 10:02:17.266076 TX Vref Scan disable
6960 10:02:17.269063 == TX Byte 0 ==
6961 10:02:17.272752 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6962 10:02:17.275696 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6963 10:02:17.278893 == TX Byte 1 ==
6964 10:02:17.282375 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6965 10:02:17.285496 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6966 10:02:17.285573 ==
6967 10:02:17.288628 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 10:02:17.295176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 10:02:17.295255 ==
6970 10:02:17.295357
6971 10:02:17.295453
6972 10:02:17.295543 TX Vref Scan disable
6973 10:02:17.298754 == TX Byte 0 ==
6974 10:02:17.301993 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6975 10:02:17.305395 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6976 10:02:17.308705 == TX Byte 1 ==
6977 10:02:17.311783 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6978 10:02:17.315260 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6979 10:02:17.315362
6980 10:02:17.318276 [DATLAT]
6981 10:02:17.318377 Freq=400, CH1 RK1
6982 10:02:17.318451
6983 10:02:17.321544 DATLAT Default: 0xe
6984 10:02:17.321621 0, 0xFFFF, sum = 0
6985 10:02:17.324869 1, 0xFFFF, sum = 0
6986 10:02:17.324946 2, 0xFFFF, sum = 0
6987 10:02:17.328141 3, 0xFFFF, sum = 0
6988 10:02:17.328216 4, 0xFFFF, sum = 0
6989 10:02:17.331934 5, 0xFFFF, sum = 0
6990 10:02:17.332011 6, 0xFFFF, sum = 0
6991 10:02:17.335052 7, 0xFFFF, sum = 0
6992 10:02:17.335157 8, 0xFFFF, sum = 0
6993 10:02:17.338145 9, 0xFFFF, sum = 0
6994 10:02:17.341912 10, 0xFFFF, sum = 0
6995 10:02:17.341993 11, 0xFFFF, sum = 0
6996 10:02:17.345201 12, 0xFFFF, sum = 0
6997 10:02:17.345280 13, 0x0, sum = 1
6998 10:02:17.348211 14, 0x0, sum = 2
6999 10:02:17.348314 15, 0x0, sum = 3
7000 10:02:17.348408 16, 0x0, sum = 4
7001 10:02:17.351549 best_step = 14
7002 10:02:17.351652
7003 10:02:17.351746 ==
7004 10:02:17.355137 Dram Type= 6, Freq= 0, CH_1, rank 1
7005 10:02:17.358404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7006 10:02:17.358506 ==
7007 10:02:17.361171 RX Vref Scan: 0
7008 10:02:17.361250
7009 10:02:17.364949 RX Vref 0 -> 0, step: 1
7010 10:02:17.365052
7011 10:02:17.365146 RX Delay -343 -> 252, step: 8
7012 10:02:17.373272 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7013 10:02:17.377002 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7014 10:02:17.379789 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7015 10:02:17.386782 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7016 10:02:17.389640 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7017 10:02:17.393079 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7018 10:02:17.396370 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7019 10:02:17.402899 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7020 10:02:17.406483 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7021 10:02:17.409801 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7022 10:02:17.413156 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7023 10:02:17.419598 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7024 10:02:17.422866 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7025 10:02:17.426032 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7026 10:02:17.429480 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7027 10:02:17.436266 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7028 10:02:17.436368 ==
7029 10:02:17.439419 Dram Type= 6, Freq= 0, CH_1, rank 1
7030 10:02:17.442939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7031 10:02:17.443038 ==
7032 10:02:17.443139 DQS Delay:
7033 10:02:17.445610 DQS0 = 48, DQS1 = 56
7034 10:02:17.445717 DQM Delay:
7035 10:02:17.448893 DQM0 = 13, DQM1 = 11
7036 10:02:17.448997 DQ Delay:
7037 10:02:17.452735 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7038 10:02:17.455593 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
7039 10:02:17.460158 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7040 10:02:17.462507 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7041 10:02:17.462579
7042 10:02:17.462641
7043 10:02:17.472318 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e5f, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
7044 10:02:17.472426 CH1 RK1: MR19=C0C, MR18=6E5F
7045 10:02:17.479166 CH1_RK1: MR19=0xC0C, MR18=0x6E5F, DQSOSC=395, MR23=63, INC=378, DEC=252
7046 10:02:17.482320 [RxdqsGatingPostProcess] freq 400
7047 10:02:17.489081 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7048 10:02:17.492413 best DQS0 dly(2T, 0.5T) = (0, 10)
7049 10:02:17.495457 best DQS1 dly(2T, 0.5T) = (0, 10)
7050 10:02:17.498685 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7051 10:02:17.502106 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7052 10:02:17.505233 best DQS0 dly(2T, 0.5T) = (0, 10)
7053 10:02:17.505335 best DQS1 dly(2T, 0.5T) = (0, 10)
7054 10:02:17.508715 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7055 10:02:17.512750 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7056 10:02:17.515090 Pre-setting of DQS Precalculation
7057 10:02:17.522220 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7058 10:02:17.528836 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7059 10:02:17.535329 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7060 10:02:17.535434
7061 10:02:17.535529
7062 10:02:17.538928 [Calibration Summary] 800 Mbps
7063 10:02:17.539031 CH 0, Rank 0
7064 10:02:17.541874 SW Impedance : PASS
7065 10:02:17.545014 DUTY Scan : NO K
7066 10:02:17.545116 ZQ Calibration : PASS
7067 10:02:17.548886 Jitter Meter : NO K
7068 10:02:17.551721 CBT Training : PASS
7069 10:02:17.551822 Write leveling : PASS
7070 10:02:17.554924 RX DQS gating : PASS
7071 10:02:17.558600 RX DQ/DQS(RDDQC) : PASS
7072 10:02:17.558706 TX DQ/DQS : PASS
7073 10:02:17.561482 RX DATLAT : PASS
7074 10:02:17.565284 RX DQ/DQS(Engine): PASS
7075 10:02:17.565368 TX OE : NO K
7076 10:02:17.568237 All Pass.
7077 10:02:17.568336
7078 10:02:17.568431 CH 0, Rank 1
7079 10:02:17.571533 SW Impedance : PASS
7080 10:02:17.571629 DUTY Scan : NO K
7081 10:02:17.574647 ZQ Calibration : PASS
7082 10:02:17.577823 Jitter Meter : NO K
7083 10:02:17.577927 CBT Training : PASS
7084 10:02:17.581602 Write leveling : NO K
7085 10:02:17.584481 RX DQS gating : PASS
7086 10:02:17.584599 RX DQ/DQS(RDDQC) : PASS
7087 10:02:17.588051 TX DQ/DQS : PASS
7088 10:02:17.591594 RX DATLAT : PASS
7089 10:02:17.591698 RX DQ/DQS(Engine): PASS
7090 10:02:17.594363 TX OE : NO K
7091 10:02:17.594469 All Pass.
7092 10:02:17.594561
7093 10:02:17.597691 CH 1, Rank 0
7094 10:02:17.597789 SW Impedance : PASS
7095 10:02:17.601152 DUTY Scan : NO K
7096 10:02:17.601227 ZQ Calibration : PASS
7097 10:02:17.604532 Jitter Meter : NO K
7098 10:02:17.607732 CBT Training : PASS
7099 10:02:17.607807 Write leveling : PASS
7100 10:02:17.611365 RX DQS gating : PASS
7101 10:02:17.614228 RX DQ/DQS(RDDQC) : PASS
7102 10:02:17.614333 TX DQ/DQS : PASS
7103 10:02:17.617976 RX DATLAT : PASS
7104 10:02:17.621004 RX DQ/DQS(Engine): PASS
7105 10:02:17.621093 TX OE : NO K
7106 10:02:17.624133 All Pass.
7107 10:02:17.624228
7108 10:02:17.624316 CH 1, Rank 1
7109 10:02:17.627423 SW Impedance : PASS
7110 10:02:17.627520 DUTY Scan : NO K
7111 10:02:17.630759 ZQ Calibration : PASS
7112 10:02:17.633852 Jitter Meter : NO K
7113 10:02:17.633956 CBT Training : PASS
7114 10:02:17.637295 Write leveling : NO K
7115 10:02:17.640637 RX DQS gating : PASS
7116 10:02:17.640715 RX DQ/DQS(RDDQC) : PASS
7117 10:02:17.644218 TX DQ/DQS : PASS
7118 10:02:17.647652 RX DATLAT : PASS
7119 10:02:17.647753 RX DQ/DQS(Engine): PASS
7120 10:02:17.650450 TX OE : NO K
7121 10:02:17.650558 All Pass.
7122 10:02:17.650649
7123 10:02:17.654035 DramC Write-DBI off
7124 10:02:17.657037 PER_BANK_REFRESH: Hybrid Mode
7125 10:02:17.657140 TX_TRACKING: ON
7126 10:02:17.666860 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7127 10:02:17.670423 [FAST_K] Save calibration result to emmc
7128 10:02:17.673293 dramc_set_vcore_voltage set vcore to 725000
7129 10:02:17.676861 Read voltage for 1600, 0
7130 10:02:17.676972 Vio18 = 0
7131 10:02:17.677061 Vcore = 725000
7132 10:02:17.680118 Vdram = 0
7133 10:02:17.680217 Vddq = 0
7134 10:02:17.680308 Vmddr = 0
7135 10:02:17.686771 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7136 10:02:17.690053 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7137 10:02:17.693093 MEM_TYPE=3, freq_sel=13
7138 10:02:17.696380 sv_algorithm_assistance_LP4_3733
7139 10:02:17.699653 ============ PULL DRAM RESETB DOWN ============
7140 10:02:17.706335 ========== PULL DRAM RESETB DOWN end =========
7141 10:02:17.709716 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7142 10:02:17.713208 ===================================
7143 10:02:17.716617 LPDDR4 DRAM CONFIGURATION
7144 10:02:17.719655 ===================================
7145 10:02:17.719737 EX_ROW_EN[0] = 0x0
7146 10:02:17.722837 EX_ROW_EN[1] = 0x0
7147 10:02:17.722919 LP4Y_EN = 0x0
7148 10:02:17.726642 WORK_FSP = 0x1
7149 10:02:17.726724 WL = 0x5
7150 10:02:17.729797 RL = 0x5
7151 10:02:17.729879 BL = 0x2
7152 10:02:17.733298 RPST = 0x0
7153 10:02:17.736323 RD_PRE = 0x0
7154 10:02:17.736405 WR_PRE = 0x1
7155 10:02:17.739515 WR_PST = 0x1
7156 10:02:17.739598 DBI_WR = 0x0
7157 10:02:17.743136 DBI_RD = 0x0
7158 10:02:17.743236 OTF = 0x1
7159 10:02:17.746270 ===================================
7160 10:02:17.750312 ===================================
7161 10:02:17.752770 ANA top config
7162 10:02:17.752852 ===================================
7163 10:02:17.756332 DLL_ASYNC_EN = 0
7164 10:02:17.759693 ALL_SLAVE_EN = 0
7165 10:02:17.762662 NEW_RANK_MODE = 1
7166 10:02:17.765973 DLL_IDLE_MODE = 1
7167 10:02:17.766055 LP45_APHY_COMB_EN = 1
7168 10:02:17.768974 TX_ODT_DIS = 0
7169 10:02:17.772640 NEW_8X_MODE = 1
7170 10:02:17.775643 ===================================
7171 10:02:17.779096 ===================================
7172 10:02:17.782810 data_rate = 3200
7173 10:02:17.785813 CKR = 1
7174 10:02:17.789322 DQ_P2S_RATIO = 8
7175 10:02:17.792661 ===================================
7176 10:02:17.792760 CA_P2S_RATIO = 8
7177 10:02:17.795764 DQ_CA_OPEN = 0
7178 10:02:17.799089 DQ_SEMI_OPEN = 0
7179 10:02:17.802100 CA_SEMI_OPEN = 0
7180 10:02:17.805569 CA_FULL_RATE = 0
7181 10:02:17.808934 DQ_CKDIV4_EN = 0
7182 10:02:17.809034 CA_CKDIV4_EN = 0
7183 10:02:17.812170 CA_PREDIV_EN = 0
7184 10:02:17.815756 PH8_DLY = 12
7185 10:02:17.818795 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7186 10:02:17.821937 DQ_AAMCK_DIV = 4
7187 10:02:17.826021 CA_AAMCK_DIV = 4
7188 10:02:17.826120 CA_ADMCK_DIV = 4
7189 10:02:17.828968 DQ_TRACK_CA_EN = 0
7190 10:02:17.831729 CA_PICK = 1600
7191 10:02:17.835226 CA_MCKIO = 1600
7192 10:02:17.838192 MCKIO_SEMI = 0
7193 10:02:17.841538 PLL_FREQ = 3068
7194 10:02:17.845211 DQ_UI_PI_RATIO = 32
7195 10:02:17.848353 CA_UI_PI_RATIO = 0
7196 10:02:17.851465 ===================================
7197 10:02:17.854681 ===================================
7198 10:02:17.854781 memory_type:LPDDR4
7199 10:02:17.858177 GP_NUM : 10
7200 10:02:17.861337 SRAM_EN : 1
7201 10:02:17.861435 MD32_EN : 0
7202 10:02:17.864627 ===================================
7203 10:02:17.868037 [ANA_INIT] >>>>>>>>>>>>>>
7204 10:02:17.871091 <<<<<< [CONFIGURE PHASE]: ANA_TX
7205 10:02:17.874693 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7206 10:02:17.878293 ===================================
7207 10:02:17.881316 data_rate = 3200,PCW = 0X7600
7208 10:02:17.884606 ===================================
7209 10:02:17.888115 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7210 10:02:17.891240 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7211 10:02:17.897484 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7212 10:02:17.901150 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7213 10:02:17.907166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7214 10:02:17.910541 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7215 10:02:17.910625 [ANA_INIT] flow start
7216 10:02:17.914087 [ANA_INIT] PLL >>>>>>>>
7217 10:02:17.917347 [ANA_INIT] PLL <<<<<<<<
7218 10:02:17.917431 [ANA_INIT] MIDPI >>>>>>>>
7219 10:02:17.920402 [ANA_INIT] MIDPI <<<<<<<<
7220 10:02:17.924044 [ANA_INIT] DLL >>>>>>>>
7221 10:02:17.924129 [ANA_INIT] DLL <<<<<<<<
7222 10:02:17.927149 [ANA_INIT] flow end
7223 10:02:17.930687 ============ LP4 DIFF to SE enter ============
7224 10:02:17.934103 ============ LP4 DIFF to SE exit ============
7225 10:02:17.936885 [ANA_INIT] <<<<<<<<<<<<<
7226 10:02:17.940267 [Flow] Enable top DCM control >>>>>
7227 10:02:17.943572 [Flow] Enable top DCM control <<<<<
7228 10:02:17.947200 Enable DLL master slave shuffle
7229 10:02:17.953677 ==============================================================
7230 10:02:17.953761 Gating Mode config
7231 10:02:17.959985 ==============================================================
7232 10:02:17.963540 Config description:
7233 10:02:17.969928 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7234 10:02:17.976371 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7235 10:02:17.983183 SELPH_MODE 0: By rank 1: By Phase
7236 10:02:17.989950 ==============================================================
7237 10:02:17.993173 GAT_TRACK_EN = 1
7238 10:02:17.993274 RX_GATING_MODE = 2
7239 10:02:17.996362 RX_GATING_TRACK_MODE = 2
7240 10:02:17.999830 SELPH_MODE = 1
7241 10:02:18.002951 PICG_EARLY_EN = 1
7242 10:02:18.006395 VALID_LAT_VALUE = 1
7243 10:02:18.012703 ==============================================================
7244 10:02:18.015927 Enter into Gating configuration >>>>
7245 10:02:18.019822 Exit from Gating configuration <<<<
7246 10:02:18.022956 Enter into DVFS_PRE_config >>>>>
7247 10:02:18.032748 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7248 10:02:18.035791 Exit from DVFS_PRE_config <<<<<
7249 10:02:18.039055 Enter into PICG configuration >>>>
7250 10:02:18.042586 Exit from PICG configuration <<<<
7251 10:02:18.045908 [RX_INPUT] configuration >>>>>
7252 10:02:18.049445 [RX_INPUT] configuration <<<<<
7253 10:02:18.052400 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7254 10:02:18.059408 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7255 10:02:18.065896 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7256 10:02:18.071752 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7257 10:02:18.078841 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7258 10:02:18.081999 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7259 10:02:18.088352 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7260 10:02:18.091756 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7261 10:02:18.095089 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7262 10:02:18.098074 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7263 10:02:18.105221 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7264 10:02:18.108044 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7265 10:02:18.111416 ===================================
7266 10:02:18.114781 LPDDR4 DRAM CONFIGURATION
7267 10:02:18.118011 ===================================
7268 10:02:18.118115 EX_ROW_EN[0] = 0x0
7269 10:02:18.121325 EX_ROW_EN[1] = 0x0
7270 10:02:18.121402 LP4Y_EN = 0x0
7271 10:02:18.124944 WORK_FSP = 0x1
7272 10:02:18.125022 WL = 0x5
7273 10:02:18.127723 RL = 0x5
7274 10:02:18.127824 BL = 0x2
7275 10:02:18.131178 RPST = 0x0
7276 10:02:18.134296 RD_PRE = 0x0
7277 10:02:18.134398 WR_PRE = 0x1
7278 10:02:18.137896 WR_PST = 0x1
7279 10:02:18.137973 DBI_WR = 0x0
7280 10:02:18.141255 DBI_RD = 0x0
7281 10:02:18.141332 OTF = 0x1
7282 10:02:18.144606 ===================================
7283 10:02:18.148087 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7284 10:02:18.154032 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7285 10:02:18.157907 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7286 10:02:18.160853 ===================================
7287 10:02:18.164369 LPDDR4 DRAM CONFIGURATION
7288 10:02:18.167479 ===================================
7289 10:02:18.167558 EX_ROW_EN[0] = 0x10
7290 10:02:18.170734 EX_ROW_EN[1] = 0x0
7291 10:02:18.170820 LP4Y_EN = 0x0
7292 10:02:18.174098 WORK_FSP = 0x1
7293 10:02:18.174174 WL = 0x5
7294 10:02:18.177301 RL = 0x5
7295 10:02:18.180437 BL = 0x2
7296 10:02:18.180561 RPST = 0x0
7297 10:02:18.184090 RD_PRE = 0x0
7298 10:02:18.184192 WR_PRE = 0x1
7299 10:02:18.187190 WR_PST = 0x1
7300 10:02:18.187304 DBI_WR = 0x0
7301 10:02:18.190581 DBI_RD = 0x0
7302 10:02:18.190682 OTF = 0x1
7303 10:02:18.193712 ===================================
7304 10:02:18.200356 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7305 10:02:18.200462 ==
7306 10:02:18.203712 Dram Type= 6, Freq= 0, CH_0, rank 0
7307 10:02:18.207114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7308 10:02:18.210353 ==
7309 10:02:18.210487 [Duty_Offset_Calibration]
7310 10:02:18.213527 B0:1 B1:-1 CA:0
7311 10:02:18.213623
7312 10:02:18.216530 [DutyScan_Calibration_Flow] k_type=0
7313 10:02:18.225709
7314 10:02:18.225784 ==CLK 0==
7315 10:02:18.228725 Final CLK duty delay cell = 0
7316 10:02:18.232035 [0] MAX Duty = 5125%(X100), DQS PI = 20
7317 10:02:18.235637 [0] MIN Duty = 4907%(X100), DQS PI = 6
7318 10:02:18.238667 [0] AVG Duty = 5016%(X100)
7319 10:02:18.238777
7320 10:02:18.242022 CH0 CLK Duty spec in!! Max-Min= 218%
7321 10:02:18.245099 [DutyScan_Calibration_Flow] ====Done====
7322 10:02:18.245171
7323 10:02:18.248971 [DutyScan_Calibration_Flow] k_type=1
7324 10:02:18.264770
7325 10:02:18.264875 ==DQS 0 ==
7326 10:02:18.268405 Final DQS duty delay cell = -4
7327 10:02:18.271373 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7328 10:02:18.275000 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7329 10:02:18.277830 [-4] AVG Duty = 4922%(X100)
7330 10:02:18.277934
7331 10:02:18.278038 ==DQS 1 ==
7332 10:02:18.281388 Final DQS duty delay cell = 0
7333 10:02:18.284300 [0] MAX Duty = 5187%(X100), DQS PI = 4
7334 10:02:18.287553 [0] MIN Duty = 5031%(X100), DQS PI = 18
7335 10:02:18.291157 [0] AVG Duty = 5109%(X100)
7336 10:02:18.291264
7337 10:02:18.294755 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7338 10:02:18.294852
7339 10:02:18.297955 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7340 10:02:18.300903 [DutyScan_Calibration_Flow] ====Done====
7341 10:02:18.301011
7342 10:02:18.304106 [DutyScan_Calibration_Flow] k_type=3
7343 10:02:18.322072
7344 10:02:18.322177 ==DQM 0 ==
7345 10:02:18.325579 Final DQM duty delay cell = 0
7346 10:02:18.329130 [0] MAX Duty = 5093%(X100), DQS PI = 20
7347 10:02:18.332352 [0] MIN Duty = 4907%(X100), DQS PI = 8
7348 10:02:18.335262 [0] AVG Duty = 5000%(X100)
7349 10:02:18.335362
7350 10:02:18.335460 ==DQM 1 ==
7351 10:02:18.338554 Final DQM duty delay cell = 0
7352 10:02:18.342384 [0] MAX Duty = 5000%(X100), DQS PI = 4
7353 10:02:18.345636 [0] MIN Duty = 4782%(X100), DQS PI = 20
7354 10:02:18.349157 [0] AVG Duty = 4891%(X100)
7355 10:02:18.349226
7356 10:02:18.352093 CH0 DQM 0 Duty spec in!! Max-Min= 186%
7357 10:02:18.352188
7358 10:02:18.355345 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7359 10:02:18.358551 [DutyScan_Calibration_Flow] ====Done====
7360 10:02:18.358658
7361 10:02:18.362175 [DutyScan_Calibration_Flow] k_type=2
7362 10:02:18.378200
7363 10:02:18.378305 ==DQ 0 ==
7364 10:02:18.382159 Final DQ duty delay cell = -4
7365 10:02:18.384931 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7366 10:02:18.388626 [-4] MIN Duty = 4876%(X100), DQS PI = 56
7367 10:02:18.391861 [-4] AVG Duty = 4953%(X100)
7368 10:02:18.391957
7369 10:02:18.392049 ==DQ 1 ==
7370 10:02:18.394903 Final DQ duty delay cell = 0
7371 10:02:18.398263 [0] MAX Duty = 5125%(X100), DQS PI = 2
7372 10:02:18.401982 [0] MIN Duty = 5000%(X100), DQS PI = 34
7373 10:02:18.404839 [0] AVG Duty = 5062%(X100)
7374 10:02:18.404941
7375 10:02:18.408388 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7376 10:02:18.408495
7377 10:02:18.411431 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7378 10:02:18.414673 [DutyScan_Calibration_Flow] ====Done====
7379 10:02:18.414776 ==
7380 10:02:18.417907 Dram Type= 6, Freq= 0, CH_1, rank 0
7381 10:02:18.421469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7382 10:02:18.421544 ==
7383 10:02:18.424588 [Duty_Offset_Calibration]
7384 10:02:18.424661 B0:-1 B1:1 CA:1
7385 10:02:18.424723
7386 10:02:18.428127 [DutyScan_Calibration_Flow] k_type=0
7387 10:02:18.439437
7388 10:02:18.439540 ==CLK 0==
7389 10:02:18.442131 Final CLK duty delay cell = 0
7390 10:02:18.445882 [0] MAX Duty = 5187%(X100), DQS PI = 22
7391 10:02:18.449129 [0] MIN Duty = 5000%(X100), DQS PI = 0
7392 10:02:18.452187 [0] AVG Duty = 5093%(X100)
7393 10:02:18.452288
7394 10:02:18.455667 CH1 CLK Duty spec in!! Max-Min= 187%
7395 10:02:18.458935 [DutyScan_Calibration_Flow] ====Done====
7396 10:02:18.459036
7397 10:02:18.462493 [DutyScan_Calibration_Flow] k_type=1
7398 10:02:18.479009
7399 10:02:18.479120 ==DQS 0 ==
7400 10:02:18.482204 Final DQS duty delay cell = 0
7401 10:02:18.485257 [0] MAX Duty = 5124%(X100), DQS PI = 16
7402 10:02:18.488966 [0] MIN Duty = 4907%(X100), DQS PI = 10
7403 10:02:18.492073 [0] AVG Duty = 5015%(X100)
7404 10:02:18.492148
7405 10:02:18.492214 ==DQS 1 ==
7406 10:02:18.495382 Final DQS duty delay cell = 0
7407 10:02:18.499220 [0] MAX Duty = 5093%(X100), DQS PI = 24
7408 10:02:18.502241 [0] MIN Duty = 4969%(X100), DQS PI = 56
7409 10:02:18.505124 [0] AVG Duty = 5031%(X100)
7410 10:02:18.505199
7411 10:02:18.508525 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7412 10:02:18.508612
7413 10:02:18.512233 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7414 10:02:18.515208 [DutyScan_Calibration_Flow] ====Done====
7415 10:02:18.515283
7416 10:02:18.518572 [DutyScan_Calibration_Flow] k_type=3
7417 10:02:18.534808
7418 10:02:18.534905 ==DQM 0 ==
7419 10:02:18.538568 Final DQM duty delay cell = -4
7420 10:02:18.541578 [-4] MAX Duty = 5031%(X100), DQS PI = 18
7421 10:02:18.544790 [-4] MIN Duty = 4782%(X100), DQS PI = 8
7422 10:02:18.548059 [-4] AVG Duty = 4906%(X100)
7423 10:02:18.548134
7424 10:02:18.548198 ==DQM 1 ==
7425 10:02:18.551354 Final DQM duty delay cell = 0
7426 10:02:18.554653 [0] MAX Duty = 5156%(X100), DQS PI = 4
7427 10:02:18.558397 [0] MIN Duty = 4969%(X100), DQS PI = 34
7428 10:02:18.561408 [0] AVG Duty = 5062%(X100)
7429 10:02:18.561485
7430 10:02:18.564386 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7431 10:02:18.564489
7432 10:02:18.568062 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7433 10:02:18.571296 [DutyScan_Calibration_Flow] ====Done====
7434 10:02:18.571397
7435 10:02:18.575028 [DutyScan_Calibration_Flow] k_type=2
7436 10:02:18.591981
7437 10:02:18.592067 ==DQ 0 ==
7438 10:02:18.595151 Final DQ duty delay cell = 0
7439 10:02:18.598959 [0] MAX Duty = 5187%(X100), DQS PI = 32
7440 10:02:18.601999 [0] MIN Duty = 4906%(X100), DQS PI = 10
7441 10:02:18.602091 [0] AVG Duty = 5046%(X100)
7442 10:02:18.605098
7443 10:02:18.605174 ==DQ 1 ==
7444 10:02:18.608293 Final DQ duty delay cell = 0
7445 10:02:18.612125 [0] MAX Duty = 5156%(X100), DQS PI = 10
7446 10:02:18.614834 [0] MIN Duty = 4969%(X100), DQS PI = 56
7447 10:02:18.614913 [0] AVG Duty = 5062%(X100)
7448 10:02:18.618330
7449 10:02:18.621679 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7450 10:02:18.621783
7451 10:02:18.625157 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7452 10:02:18.628497 [DutyScan_Calibration_Flow] ====Done====
7453 10:02:18.631359 nWR fixed to 30
7454 10:02:18.634833 [ModeRegInit_LP4] CH0 RK0
7455 10:02:18.634948 [ModeRegInit_LP4] CH0 RK1
7456 10:02:18.638240 [ModeRegInit_LP4] CH1 RK0
7457 10:02:18.641130 [ModeRegInit_LP4] CH1 RK1
7458 10:02:18.641237 match AC timing 5
7459 10:02:18.647722 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7460 10:02:18.651444 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7461 10:02:18.654505 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7462 10:02:18.661197 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7463 10:02:18.664430 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7464 10:02:18.664552 [MiockJmeterHQA]
7465 10:02:18.664621
7466 10:02:18.667844 [DramcMiockJmeter] u1RxGatingPI = 0
7467 10:02:18.671284 0 : 4252, 4027
7468 10:02:18.671361 4 : 4363, 4138
7469 10:02:18.674101 8 : 4252, 4027
7470 10:02:18.674178 12 : 4363, 4137
7471 10:02:18.677486 16 : 4252, 4026
7472 10:02:18.677591 20 : 4252, 4027
7473 10:02:18.677700 24 : 4252, 4027
7474 10:02:18.680939 28 : 4363, 4137
7475 10:02:18.681021 32 : 4363, 4138
7476 10:02:18.684384 36 : 4250, 4026
7477 10:02:18.684503 40 : 4252, 4027
7478 10:02:18.687467 44 : 4252, 4026
7479 10:02:18.687569 48 : 4253, 4026
7480 10:02:18.691287 52 : 4254, 4029
7481 10:02:18.691391 56 : 4363, 4137
7482 10:02:18.691483 60 : 4253, 4027
7483 10:02:18.694257 64 : 4252, 4026
7484 10:02:18.694360 68 : 4252, 4027
7485 10:02:18.697837 72 : 4254, 4029
7486 10:02:18.697943 76 : 4250, 4026
7487 10:02:18.700683 80 : 4361, 4137
7488 10:02:18.700786 84 : 4361, 4137
7489 10:02:18.703938 88 : 4250, 4026
7490 10:02:18.704043 92 : 4250, 936
7491 10:02:18.704136 96 : 4363, 0
7492 10:02:18.706984 100 : 4361, 0
7493 10:02:18.707087 104 : 4253, 0
7494 10:02:18.710373 108 : 4250, 0
7495 10:02:18.710472 112 : 4250, 0
7496 10:02:18.710564 116 : 4252, 0
7497 10:02:18.713570 120 : 4361, 0
7498 10:02:18.713651 124 : 4250, 0
7499 10:02:18.717314 128 : 4361, 0
7500 10:02:18.717416 132 : 4250, 0
7501 10:02:18.717511 136 : 4360, 0
7502 10:02:18.720505 140 : 4360, 0
7503 10:02:18.720642 144 : 4250, 0
7504 10:02:18.723888 148 : 4250, 0
7505 10:02:18.723993 152 : 4250, 0
7506 10:02:18.724059 156 : 4250, 0
7507 10:02:18.727118 160 : 4250, 0
7508 10:02:18.727196 164 : 4250, 0
7509 10:02:18.727265 168 : 4252, 0
7510 10:02:18.730141 172 : 4250, 0
7511 10:02:18.730214 176 : 4250, 0
7512 10:02:18.733602 180 : 4253, 0
7513 10:02:18.733678 184 : 4360, 0
7514 10:02:18.733741 188 : 4361, 0
7515 10:02:18.736652 192 : 4363, 0
7516 10:02:18.736762 196 : 4250, 0
7517 10:02:18.741247 200 : 4250, 0
7518 10:02:18.741325 204 : 4250, 0
7519 10:02:18.741390 208 : 4250, 0
7520 10:02:18.744010 212 : 4250, 0
7521 10:02:18.744098 216 : 4250, 0
7522 10:02:18.746706 220 : 4252, 0
7523 10:02:18.746812 224 : 4250, 111
7524 10:02:18.746914 228 : 4360, 3097
7525 10:02:18.749884 232 : 4252, 4030
7526 10:02:18.749989 236 : 4252, 4026
7527 10:02:18.753520 240 : 4252, 4027
7528 10:02:18.753595 244 : 4252, 4030
7529 10:02:18.756584 248 : 4249, 4027
7530 10:02:18.756656 252 : 4250, 4026
7531 10:02:18.759993 256 : 4361, 4137
7532 10:02:18.760098 260 : 4250, 4027
7533 10:02:18.763170 264 : 4249, 4027
7534 10:02:18.763274 268 : 4360, 4137
7535 10:02:18.766540 272 : 4250, 4026
7536 10:02:18.766640 276 : 4250, 4027
7537 10:02:18.770220 280 : 4363, 4140
7538 10:02:18.770321 284 : 4250, 4027
7539 10:02:18.770412 288 : 4250, 4026
7540 10:02:18.772888 292 : 4250, 4027
7541 10:02:18.772968 296 : 4252, 4030
7542 10:02:18.776174 300 : 4249, 4027
7543 10:02:18.776276 304 : 4250, 4026
7544 10:02:18.779828 308 : 4361, 4137
7545 10:02:18.779913 312 : 4250, 4027
7546 10:02:18.783002 316 : 4250, 4027
7547 10:02:18.783103 320 : 4360, 4137
7548 10:02:18.786228 324 : 4250, 4026
7549 10:02:18.786326 328 : 4250, 4027
7550 10:02:18.789391 332 : 4363, 4140
7551 10:02:18.789460 336 : 4249, 3929
7552 10:02:18.793017 340 : 4250, 2146
7553 10:02:18.793085 344 : 4250, 13
7554 10:02:18.793149
7555 10:02:18.796262 MIOCK jitter meter ch=0
7556 10:02:18.796361
7557 10:02:18.799475 1T = (344-92) = 252 dly cells
7558 10:02:18.803177 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7559 10:02:18.803282 ==
7560 10:02:18.806298 Dram Type= 6, Freq= 0, CH_0, rank 0
7561 10:02:18.812777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7562 10:02:18.812855 ==
7563 10:02:18.815937 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7564 10:02:18.822577 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7565 10:02:18.826117 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7566 10:02:18.832062 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7567 10:02:18.840214 [CA 0] Center 43 (12~74) winsize 63
7568 10:02:18.844132 [CA 1] Center 43 (13~73) winsize 61
7569 10:02:18.846922 [CA 2] Center 38 (9~68) winsize 60
7570 10:02:18.850510 [CA 3] Center 38 (8~68) winsize 61
7571 10:02:18.854062 [CA 4] Center 36 (7~66) winsize 60
7572 10:02:18.856690 [CA 5] Center 35 (6~65) winsize 60
7573 10:02:18.856767
7574 10:02:18.860155 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7575 10:02:18.860229
7576 10:02:18.866623 [CATrainingPosCal] consider 1 rank data
7577 10:02:18.866702 u2DelayCellTimex100 = 258/100 ps
7578 10:02:18.873617 CA0 delay=43 (12~74),Diff = 8 PI (30 cell)
7579 10:02:18.876863 CA1 delay=43 (13~73),Diff = 8 PI (30 cell)
7580 10:02:18.880312 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7581 10:02:18.883045 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7582 10:02:18.886516 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7583 10:02:18.889719 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7584 10:02:18.889819
7585 10:02:18.893179 CA PerBit enable=1, Macro0, CA PI delay=35
7586 10:02:18.893255
7587 10:02:18.896372 [CBTSetCACLKResult] CA Dly = 35
7588 10:02:18.899890 CS Dly: 11 (0~42)
7589 10:02:18.903261 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7590 10:02:18.906626 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7591 10:02:18.906724 ==
7592 10:02:18.910057 Dram Type= 6, Freq= 0, CH_0, rank 1
7593 10:02:18.916506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 10:02:18.916591 ==
7595 10:02:18.919796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7596 10:02:18.926218 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7597 10:02:18.929498 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7598 10:02:18.936396 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7599 10:02:18.944436 [CA 0] Center 42 (12~73) winsize 62
7600 10:02:18.947182 [CA 1] Center 43 (13~73) winsize 61
7601 10:02:18.951189 [CA 2] Center 37 (8~67) winsize 60
7602 10:02:18.953829 [CA 3] Center 37 (7~67) winsize 61
7603 10:02:18.957731 [CA 4] Center 35 (6~65) winsize 60
7604 10:02:18.960477 [CA 5] Center 35 (5~65) winsize 61
7605 10:02:18.960602
7606 10:02:18.964133 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7607 10:02:18.964236
7608 10:02:18.967300 [CATrainingPosCal] consider 2 rank data
7609 10:02:18.970606 u2DelayCellTimex100 = 258/100 ps
7610 10:02:18.973836 CA0 delay=42 (12~73),Diff = 7 PI (26 cell)
7611 10:02:18.980449 CA1 delay=43 (13~73),Diff = 8 PI (30 cell)
7612 10:02:18.984074 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7613 10:02:18.986922 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7614 10:02:18.990192 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7615 10:02:18.993537 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7616 10:02:18.993639
7617 10:02:18.996773 CA PerBit enable=1, Macro0, CA PI delay=35
7618 10:02:18.996876
7619 10:02:19.000096 [CBTSetCACLKResult] CA Dly = 35
7620 10:02:19.003711 CS Dly: 11 (0~43)
7621 10:02:19.007056 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7622 10:02:19.010018 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7623 10:02:19.010095
7624 10:02:19.013640 ----->DramcWriteLeveling(PI) begin...
7625 10:02:19.013721 ==
7626 10:02:19.017307 Dram Type= 6, Freq= 0, CH_0, rank 0
7627 10:02:19.023327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7628 10:02:19.023411 ==
7629 10:02:19.026520 Write leveling (Byte 0): 35 => 35
7630 10:02:19.026596 Write leveling (Byte 1): 26 => 26
7631 10:02:19.030029 DramcWriteLeveling(PI) end<-----
7632 10:02:19.030104
7633 10:02:19.033574 ==
7634 10:02:19.033650 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 10:02:19.040195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 10:02:19.040302 ==
7637 10:02:19.044094 [Gating] SW mode calibration
7638 10:02:19.050220 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7639 10:02:19.053393 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7640 10:02:19.060074 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 10:02:19.063430 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 10:02:19.066737 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 10:02:19.072949 1 4 12 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7644 10:02:19.076549 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7645 10:02:19.079939 1 4 20 | B1->B0 | 2524 3434 | 1 1 | (0 0) (1 1)
7646 10:02:19.086540 1 4 24 | B1->B0 | 3231 3434 | 1 1 | (1 1) (1 1)
7647 10:02:19.089756 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7648 10:02:19.092790 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7649 10:02:19.099755 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7650 10:02:19.103126 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7651 10:02:19.106320 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
7652 10:02:19.112836 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7653 10:02:19.116511 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (0 1) (0 0)
7654 10:02:19.119520 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
7655 10:02:19.126151 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 10:02:19.129279 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 10:02:19.132477 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 10:02:19.139645 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7659 10:02:19.142567 1 6 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7660 10:02:19.145892 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7661 10:02:19.152865 1 6 20 | B1->B0 | 2525 4646 | 0 0 | (1 1) (0 0)
7662 10:02:19.155567 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7663 10:02:19.159837 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 10:02:19.165839 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7665 10:02:19.168635 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 10:02:19.172034 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7667 10:02:19.178887 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7668 10:02:19.181787 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7669 10:02:19.185407 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7670 10:02:19.191769 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7671 10:02:19.195306 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 10:02:19.198405 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 10:02:19.205393 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 10:02:19.208477 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 10:02:19.211521 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 10:02:19.218422 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 10:02:19.221591 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 10:02:19.225098 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 10:02:19.231315 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 10:02:19.234628 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 10:02:19.237828 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 10:02:19.244459 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 10:02:19.247850 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7684 10:02:19.251496 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7685 10:02:19.254509 Total UI for P1: 0, mck2ui 16
7686 10:02:19.258222 best dqsien dly found for B0: ( 1, 9, 12)
7687 10:02:19.264478 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7688 10:02:19.268237 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7689 10:02:19.270936 Total UI for P1: 0, mck2ui 16
7690 10:02:19.274272 best dqsien dly found for B1: ( 1, 9, 20)
7691 10:02:19.277699 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7692 10:02:19.280691 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7693 10:02:19.280774
7694 10:02:19.284107 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7695 10:02:19.287689 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7696 10:02:19.290566 [Gating] SW calibration Done
7697 10:02:19.290666 ==
7698 10:02:19.294214 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 10:02:19.300415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 10:02:19.300563 ==
7701 10:02:19.300632 RX Vref Scan: 0
7702 10:02:19.300696
7703 10:02:19.303904 RX Vref 0 -> 0, step: 1
7704 10:02:19.304011
7705 10:02:19.307003 RX Delay 0 -> 252, step: 8
7706 10:02:19.310418 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7707 10:02:19.313349 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7708 10:02:19.316920 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7709 10:02:19.320688 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7710 10:02:19.326526 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7711 10:02:19.330140 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7712 10:02:19.333331 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7713 10:02:19.336720 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7714 10:02:19.340326 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7715 10:02:19.346523 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7716 10:02:19.349927 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7717 10:02:19.352972 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7718 10:02:19.356691 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7719 10:02:19.362749 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7720 10:02:19.367042 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7721 10:02:19.369301 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7722 10:02:19.369402 ==
7723 10:02:19.372726 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 10:02:19.375843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 10:02:19.379901 ==
7726 10:02:19.379983 DQS Delay:
7727 10:02:19.380049 DQS0 = 0, DQS1 = 0
7728 10:02:19.382505 DQM Delay:
7729 10:02:19.382605 DQM0 = 136, DQM1 = 126
7730 10:02:19.386131 DQ Delay:
7731 10:02:19.389192 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7732 10:02:19.392359 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7733 10:02:19.395635 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7734 10:02:19.398913 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7735 10:02:19.399022
7736 10:02:19.399113
7737 10:02:19.399204 ==
7738 10:02:19.402286 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 10:02:19.405979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 10:02:19.406062 ==
7741 10:02:19.408970
7742 10:02:19.409044
7743 10:02:19.409123 TX Vref Scan disable
7744 10:02:19.412272 == TX Byte 0 ==
7745 10:02:19.415625 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7746 10:02:19.418906 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7747 10:02:19.422152 == TX Byte 1 ==
7748 10:02:19.425329 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7749 10:02:19.428645 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7750 10:02:19.432176 ==
7751 10:02:19.432281 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 10:02:19.438862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7753 10:02:19.438966 ==
7754 10:02:19.451237
7755 10:02:19.454718 TX Vref early break, caculate TX vref
7756 10:02:19.458059 TX Vref=16, minBit 6, minWin=22, winSum=371
7757 10:02:19.461474 TX Vref=18, minBit 1, minWin=23, winSum=379
7758 10:02:19.464638 TX Vref=20, minBit 1, minWin=24, winSum=390
7759 10:02:19.468305 TX Vref=22, minBit 1, minWin=24, winSum=399
7760 10:02:19.471102 TX Vref=24, minBit 1, minWin=24, winSum=403
7761 10:02:19.477847 TX Vref=26, minBit 4, minWin=24, winSum=416
7762 10:02:19.481603 TX Vref=28, minBit 0, minWin=25, winSum=414
7763 10:02:19.484327 TX Vref=30, minBit 11, minWin=24, winSum=410
7764 10:02:19.487843 TX Vref=32, minBit 7, minWin=23, winSum=398
7765 10:02:19.490878 TX Vref=34, minBit 0, minWin=23, winSum=385
7766 10:02:19.497679 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
7767 10:02:19.497772
7768 10:02:19.500719 Final TX Range 0 Vref 28
7769 10:02:19.500798
7770 10:02:19.500861 ==
7771 10:02:19.504162 Dram Type= 6, Freq= 0, CH_0, rank 0
7772 10:02:19.507390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7773 10:02:19.507492 ==
7774 10:02:19.507591
7775 10:02:19.507684
7776 10:02:19.510948 TX Vref Scan disable
7777 10:02:19.517095 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7778 10:02:19.517173 == TX Byte 0 ==
7779 10:02:19.520404 u2DelayCellOfst[0]=11 cells (3 PI)
7780 10:02:19.523842 u2DelayCellOfst[1]=15 cells (4 PI)
7781 10:02:19.527346 u2DelayCellOfst[2]=11 cells (3 PI)
7782 10:02:19.530762 u2DelayCellOfst[3]=11 cells (3 PI)
7783 10:02:19.533656 u2DelayCellOfst[4]=11 cells (3 PI)
7784 10:02:19.537176 u2DelayCellOfst[5]=0 cells (0 PI)
7785 10:02:19.540140 u2DelayCellOfst[6]=15 cells (4 PI)
7786 10:02:19.543354 u2DelayCellOfst[7]=18 cells (5 PI)
7787 10:02:19.547055 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7788 10:02:19.550489 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7789 10:02:19.553868 == TX Byte 1 ==
7790 10:02:19.556807 u2DelayCellOfst[8]=0 cells (0 PI)
7791 10:02:19.560245 u2DelayCellOfst[9]=3 cells (1 PI)
7792 10:02:19.563259 u2DelayCellOfst[10]=7 cells (2 PI)
7793 10:02:19.566799 u2DelayCellOfst[11]=3 cells (1 PI)
7794 10:02:19.570124 u2DelayCellOfst[12]=15 cells (4 PI)
7795 10:02:19.570203 u2DelayCellOfst[13]=15 cells (4 PI)
7796 10:02:19.573314 u2DelayCellOfst[14]=18 cells (5 PI)
7797 10:02:19.576493 u2DelayCellOfst[15]=11 cells (3 PI)
7798 10:02:19.582958 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7799 10:02:19.586462 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7800 10:02:19.586583 DramC Write-DBI on
7801 10:02:19.589966 ==
7802 10:02:19.593183 Dram Type= 6, Freq= 0, CH_0, rank 0
7803 10:02:19.596384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7804 10:02:19.596506 ==
7805 10:02:19.596597
7806 10:02:19.596658
7807 10:02:19.599909 TX Vref Scan disable
7808 10:02:19.600019 == TX Byte 0 ==
7809 10:02:19.606300 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7810 10:02:19.606412 == TX Byte 1 ==
7811 10:02:19.609487 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7812 10:02:19.612729 DramC Write-DBI off
7813 10:02:19.612804
7814 10:02:19.612871 [DATLAT]
7815 10:02:19.616410 Freq=1600, CH0 RK0
7816 10:02:19.616510
7817 10:02:19.616631 DATLAT Default: 0xf
7818 10:02:19.620072 0, 0xFFFF, sum = 0
7819 10:02:19.620174 1, 0xFFFF, sum = 0
7820 10:02:19.622640 2, 0xFFFF, sum = 0
7821 10:02:19.622749 3, 0xFFFF, sum = 0
7822 10:02:19.626078 4, 0xFFFF, sum = 0
7823 10:02:19.626182 5, 0xFFFF, sum = 0
7824 10:02:19.629349 6, 0xFFFF, sum = 0
7825 10:02:19.632912 7, 0xFFFF, sum = 0
7826 10:02:19.633017 8, 0xFFFF, sum = 0
7827 10:02:19.635777 9, 0xFFFF, sum = 0
7828 10:02:19.635871 10, 0xFFFF, sum = 0
7829 10:02:19.639526 11, 0xFFFF, sum = 0
7830 10:02:19.639631 12, 0xFFFF, sum = 0
7831 10:02:19.642755 13, 0xFFFF, sum = 0
7832 10:02:19.642839 14, 0x0, sum = 1
7833 10:02:19.646052 15, 0x0, sum = 2
7834 10:02:19.646136 16, 0x0, sum = 3
7835 10:02:19.649704 17, 0x0, sum = 4
7836 10:02:19.649788 best_step = 15
7837 10:02:19.649853
7838 10:02:19.649913 ==
7839 10:02:19.652412 Dram Type= 6, Freq= 0, CH_0, rank 0
7840 10:02:19.656372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7841 10:02:19.658818 ==
7842 10:02:19.658901 RX Vref Scan: 1
7843 10:02:19.658966
7844 10:02:19.662738 Set Vref Range= 24 -> 127
7845 10:02:19.662820
7846 10:02:19.665877 RX Vref 24 -> 127, step: 1
7847 10:02:19.665959
7848 10:02:19.666024 RX Delay 19 -> 252, step: 4
7849 10:02:19.666086
7850 10:02:19.669080 Set Vref, RX VrefLevel [Byte0]: 24
7851 10:02:19.672439 [Byte1]: 24
7852 10:02:19.675931
7853 10:02:19.676014 Set Vref, RX VrefLevel [Byte0]: 25
7854 10:02:19.679730 [Byte1]: 25
7855 10:02:19.683694
7856 10:02:19.683777 Set Vref, RX VrefLevel [Byte0]: 26
7857 10:02:19.687419 [Byte1]: 26
7858 10:02:19.691528
7859 10:02:19.691610 Set Vref, RX VrefLevel [Byte0]: 27
7860 10:02:19.694587 [Byte1]: 27
7861 10:02:19.699246
7862 10:02:19.699329 Set Vref, RX VrefLevel [Byte0]: 28
7863 10:02:19.702136 [Byte1]: 28
7864 10:02:19.706351
7865 10:02:19.706455 Set Vref, RX VrefLevel [Byte0]: 29
7866 10:02:19.709589 [Byte1]: 29
7867 10:02:19.714373
7868 10:02:19.714489 Set Vref, RX VrefLevel [Byte0]: 30
7869 10:02:19.717067 [Byte1]: 30
7870 10:02:19.721590
7871 10:02:19.721695 Set Vref, RX VrefLevel [Byte0]: 31
7872 10:02:19.725000 [Byte1]: 31
7873 10:02:19.728980
7874 10:02:19.729066 Set Vref, RX VrefLevel [Byte0]: 32
7875 10:02:19.732879 [Byte1]: 32
7876 10:02:19.736589
7877 10:02:19.736665 Set Vref, RX VrefLevel [Byte0]: 33
7878 10:02:19.740130 [Byte1]: 33
7879 10:02:19.744246
7880 10:02:19.744352 Set Vref, RX VrefLevel [Byte0]: 34
7881 10:02:19.748154 [Byte1]: 34
7882 10:02:19.751659
7883 10:02:19.751768 Set Vref, RX VrefLevel [Byte0]: 35
7884 10:02:19.755095 [Byte1]: 35
7885 10:02:19.759607
7886 10:02:19.759681 Set Vref, RX VrefLevel [Byte0]: 36
7887 10:02:19.762954 [Byte1]: 36
7888 10:02:19.766848
7889 10:02:19.766948 Set Vref, RX VrefLevel [Byte0]: 37
7890 10:02:19.770050 [Byte1]: 37
7891 10:02:19.774440
7892 10:02:19.774545 Set Vref, RX VrefLevel [Byte0]: 38
7893 10:02:19.777981 [Byte1]: 38
7894 10:02:19.782373
7895 10:02:19.785629 Set Vref, RX VrefLevel [Byte0]: 39
7896 10:02:19.788396 [Byte1]: 39
7897 10:02:19.788506
7898 10:02:19.791701 Set Vref, RX VrefLevel [Byte0]: 40
7899 10:02:19.795303 [Byte1]: 40
7900 10:02:19.795387
7901 10:02:19.798548 Set Vref, RX VrefLevel [Byte0]: 41
7902 10:02:19.801578 [Byte1]: 41
7903 10:02:19.804947
7904 10:02:19.805036 Set Vref, RX VrefLevel [Byte0]: 42
7905 10:02:19.808145 [Byte1]: 42
7906 10:02:19.812372
7907 10:02:19.812478 Set Vref, RX VrefLevel [Byte0]: 43
7908 10:02:19.815634 [Byte1]: 43
7909 10:02:19.820231
7910 10:02:19.820317 Set Vref, RX VrefLevel [Byte0]: 44
7911 10:02:19.823309 [Byte1]: 44
7912 10:02:19.827786
7913 10:02:19.827863 Set Vref, RX VrefLevel [Byte0]: 45
7914 10:02:19.830758 [Byte1]: 45
7915 10:02:19.834953
7916 10:02:19.835032 Set Vref, RX VrefLevel [Byte0]: 46
7917 10:02:19.838592 [Byte1]: 46
7918 10:02:19.842874
7919 10:02:19.842985 Set Vref, RX VrefLevel [Byte0]: 47
7920 10:02:19.845866 [Byte1]: 47
7921 10:02:19.850233
7922 10:02:19.850321 Set Vref, RX VrefLevel [Byte0]: 48
7923 10:02:19.853867 [Byte1]: 48
7924 10:02:19.857808
7925 10:02:19.857891 Set Vref, RX VrefLevel [Byte0]: 49
7926 10:02:19.861211 [Byte1]: 49
7927 10:02:19.865628
7928 10:02:19.865711 Set Vref, RX VrefLevel [Byte0]: 50
7929 10:02:19.868808 [Byte1]: 50
7930 10:02:19.873373
7931 10:02:19.873456 Set Vref, RX VrefLevel [Byte0]: 51
7932 10:02:19.876442 [Byte1]: 51
7933 10:02:19.880431
7934 10:02:19.880522 Set Vref, RX VrefLevel [Byte0]: 52
7935 10:02:19.883674 [Byte1]: 52
7936 10:02:19.888269
7937 10:02:19.888346 Set Vref, RX VrefLevel [Byte0]: 53
7938 10:02:19.891321 [Byte1]: 53
7939 10:02:19.895557
7940 10:02:19.895634 Set Vref, RX VrefLevel [Byte0]: 54
7941 10:02:19.899364 [Byte1]: 54
7942 10:02:19.903297
7943 10:02:19.903379 Set Vref, RX VrefLevel [Byte0]: 55
7944 10:02:19.906603 [Byte1]: 55
7945 10:02:19.910782
7946 10:02:19.910896 Set Vref, RX VrefLevel [Byte0]: 56
7947 10:02:19.914637 [Byte1]: 56
7948 10:02:19.918350
7949 10:02:19.918472 Set Vref, RX VrefLevel [Byte0]: 57
7950 10:02:19.922024 [Byte1]: 57
7951 10:02:19.926314
7952 10:02:19.926405 Set Vref, RX VrefLevel [Byte0]: 58
7953 10:02:19.929424 [Byte1]: 58
7954 10:02:19.933337
7955 10:02:19.933460 Set Vref, RX VrefLevel [Byte0]: 59
7956 10:02:19.936644 [Byte1]: 59
7957 10:02:19.941158
7958 10:02:19.941252 Set Vref, RX VrefLevel [Byte0]: 60
7959 10:02:19.944415 [Byte1]: 60
7960 10:02:19.948783
7961 10:02:19.948881 Set Vref, RX VrefLevel [Byte0]: 61
7962 10:02:19.952002 [Byte1]: 61
7963 10:02:19.956448
7964 10:02:19.956529 Set Vref, RX VrefLevel [Byte0]: 62
7965 10:02:19.959832 [Byte1]: 62
7966 10:02:19.964120
7967 10:02:19.964205 Set Vref, RX VrefLevel [Byte0]: 63
7968 10:02:19.967520 [Byte1]: 63
7969 10:02:19.971881
7970 10:02:19.971966 Set Vref, RX VrefLevel [Byte0]: 64
7971 10:02:19.974897 [Byte1]: 64
7972 10:02:19.979418
7973 10:02:19.979505 Set Vref, RX VrefLevel [Byte0]: 65
7974 10:02:19.982026 [Byte1]: 65
7975 10:02:19.986500
7976 10:02:19.986605 Set Vref, RX VrefLevel [Byte0]: 66
7977 10:02:19.989752 [Byte1]: 66
7978 10:02:19.994107
7979 10:02:19.994199 Set Vref, RX VrefLevel [Byte0]: 67
7980 10:02:19.997529 [Byte1]: 67
7981 10:02:20.001602
7982 10:02:20.001708 Set Vref, RX VrefLevel [Byte0]: 68
7983 10:02:20.005735 [Byte1]: 68
7984 10:02:20.009257
7985 10:02:20.009334 Set Vref, RX VrefLevel [Byte0]: 69
7986 10:02:20.012478 [Byte1]: 69
7987 10:02:20.016792
7988 10:02:20.016868 Set Vref, RX VrefLevel [Byte0]: 70
7989 10:02:20.020063 [Byte1]: 70
7990 10:02:20.024494
7991 10:02:20.024578 Set Vref, RX VrefLevel [Byte0]: 71
7992 10:02:20.027756 [Byte1]: 71
7993 10:02:20.032813
7994 10:02:20.032894 Set Vref, RX VrefLevel [Byte0]: 72
7995 10:02:20.035405 [Byte1]: 72
7996 10:02:20.039887
7997 10:02:20.039963 Set Vref, RX VrefLevel [Byte0]: 73
7998 10:02:20.042773 [Byte1]: 73
7999 10:02:20.046962
8000 10:02:20.047038 Set Vref, RX VrefLevel [Byte0]: 74
8001 10:02:20.050392 [Byte1]: 74
8002 10:02:20.055027
8003 10:02:20.055122 Set Vref, RX VrefLevel [Byte0]: 75
8004 10:02:20.058216 [Byte1]: 75
8005 10:02:20.062065
8006 10:02:20.062155 Set Vref, RX VrefLevel [Byte0]: 76
8007 10:02:20.065878 [Byte1]: 76
8008 10:02:20.069717
8009 10:02:20.069794 Set Vref, RX VrefLevel [Byte0]: 77
8010 10:02:20.072959 [Byte1]: 77
8011 10:02:20.077316
8012 10:02:20.077395 Set Vref, RX VrefLevel [Byte0]: 78
8013 10:02:20.081070 [Byte1]: 78
8014 10:02:20.084798
8015 10:02:20.084879 Set Vref, RX VrefLevel [Byte0]: 79
8016 10:02:20.088425 [Byte1]: 79
8017 10:02:20.092671
8018 10:02:20.092750 Final RX Vref Byte 0 = 65 to rank0
8019 10:02:20.095790 Final RX Vref Byte 1 = 56 to rank0
8020 10:02:20.099256 Final RX Vref Byte 0 = 65 to rank1
8021 10:02:20.102807 Final RX Vref Byte 1 = 56 to rank1==
8022 10:02:20.105962 Dram Type= 6, Freq= 0, CH_0, rank 0
8023 10:02:20.112265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 10:02:20.112344 ==
8025 10:02:20.112409 DQS Delay:
8026 10:02:20.115501 DQS0 = 0, DQS1 = 0
8027 10:02:20.115576 DQM Delay:
8028 10:02:20.118997 DQM0 = 133, DQM1 = 123
8029 10:02:20.119068 DQ Delay:
8030 10:02:20.122120 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8031 10:02:20.125204 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8032 10:02:20.128614 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8033 10:02:20.132433 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
8034 10:02:20.132524
8035 10:02:20.132604
8036 10:02:20.132665
8037 10:02:20.135670 [DramC_TX_OE_Calibration] TA2
8038 10:02:20.138624 Original DQ_B0 (3 6) =30, OEN = 27
8039 10:02:20.141902 Original DQ_B1 (3 6) =30, OEN = 27
8040 10:02:20.145407 24, 0x0, End_B0=24 End_B1=24
8041 10:02:20.148708 25, 0x0, End_B0=25 End_B1=25
8042 10:02:20.148791 26, 0x0, End_B0=26 End_B1=26
8043 10:02:20.151623 27, 0x0, End_B0=27 End_B1=27
8044 10:02:20.154889 28, 0x0, End_B0=28 End_B1=28
8045 10:02:20.158609 29, 0x0, End_B0=29 End_B1=29
8046 10:02:20.158693 30, 0x0, End_B0=30 End_B1=30
8047 10:02:20.161630 31, 0x4141, End_B0=30 End_B1=30
8048 10:02:20.164927 Byte0 end_step=30 best_step=27
8049 10:02:20.168321 Byte1 end_step=30 best_step=27
8050 10:02:20.171453 Byte0 TX OE(2T, 0.5T) = (3, 3)
8051 10:02:20.175144 Byte1 TX OE(2T, 0.5T) = (3, 3)
8052 10:02:20.175227
8053 10:02:20.175292
8054 10:02:20.181420 [DQSOSCAuto] RK0, (LSB)MR18= 0x2314, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
8055 10:02:20.184769 CH0 RK0: MR19=303, MR18=2314
8056 10:02:20.191234 CH0_RK0: MR19=0x303, MR18=0x2314, DQSOSC=392, MR23=63, INC=24, DEC=16
8057 10:02:20.191318
8058 10:02:20.194998 ----->DramcWriteLeveling(PI) begin...
8059 10:02:20.195083 ==
8060 10:02:20.197793 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 10:02:20.201588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 10:02:20.201664 ==
8063 10:02:20.204446 Write leveling (Byte 0): 35 => 35
8064 10:02:20.207876 Write leveling (Byte 1): 28 => 28
8065 10:02:20.210991 DramcWriteLeveling(PI) end<-----
8066 10:02:20.211068
8067 10:02:20.211130 ==
8068 10:02:20.214582 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 10:02:20.221275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 10:02:20.221349 ==
8071 10:02:20.221411 [Gating] SW mode calibration
8072 10:02:20.231609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8073 10:02:20.235046 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8074 10:02:20.237663 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 10:02:20.244183 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 10:02:20.247694 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 10:02:20.250974 1 4 12 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8078 10:02:20.257702 1 4 16 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8079 10:02:20.261200 1 4 20 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
8080 10:02:20.264012 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8081 10:02:20.270953 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8082 10:02:20.274156 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8083 10:02:20.276942 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8084 10:02:20.283902 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8085 10:02:20.286855 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8086 10:02:20.290173 1 5 16 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
8087 10:02:20.297565 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
8088 10:02:20.300229 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 10:02:20.303244 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8090 10:02:20.309836 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8091 10:02:20.312951 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 10:02:20.320031 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 10:02:20.323038 1 6 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8094 10:02:20.326649 1 6 16 | B1->B0 | 2c2c 4545 | 1 0 | (0 0) (0 0)
8095 10:02:20.333051 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8096 10:02:20.336468 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 10:02:20.339507 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 10:02:20.346478 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 10:02:20.349667 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 10:02:20.352668 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8101 10:02:20.356296 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8102 10:02:20.363087 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8103 10:02:20.365838 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8104 10:02:20.369146 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8105 10:02:20.375925 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 10:02:20.379360 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 10:02:20.382351 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 10:02:20.389190 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 10:02:20.392344 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 10:02:20.396002 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 10:02:20.402739 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 10:02:20.405402 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 10:02:20.408872 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 10:02:20.415583 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 10:02:20.418815 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 10:02:20.422282 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8117 10:02:20.428631 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8118 10:02:20.432162 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8119 10:02:20.435557 Total UI for P1: 0, mck2ui 16
8120 10:02:20.438475 best dqsien dly found for B0: ( 1, 9, 10)
8121 10:02:20.442206 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8122 10:02:20.448494 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8123 10:02:20.452274 Total UI for P1: 0, mck2ui 16
8124 10:02:20.455181 best dqsien dly found for B1: ( 1, 9, 18)
8125 10:02:20.458320 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8126 10:02:20.461647 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8127 10:02:20.461745
8128 10:02:20.464994 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8129 10:02:20.468616 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8130 10:02:20.471834 [Gating] SW calibration Done
8131 10:02:20.471908 ==
8132 10:02:20.475140 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 10:02:20.478512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 10:02:20.478621 ==
8135 10:02:20.481679 RX Vref Scan: 0
8136 10:02:20.481784
8137 10:02:20.485286 RX Vref 0 -> 0, step: 1
8138 10:02:20.485360
8139 10:02:20.485423 RX Delay 0 -> 252, step: 8
8140 10:02:20.491530 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8141 10:02:20.495045 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8142 10:02:20.498458 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8143 10:02:20.501916 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8144 10:02:20.504901 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8145 10:02:20.511523 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8146 10:02:20.515086 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8147 10:02:20.518584 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8148 10:02:20.521361 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8149 10:02:20.524963 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8150 10:02:20.531616 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8151 10:02:20.534435 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8152 10:02:20.537717 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8153 10:02:20.540943 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8154 10:02:20.544504 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8155 10:02:20.551023 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8156 10:02:20.551107 ==
8157 10:02:20.554525 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 10:02:20.557868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 10:02:20.557952 ==
8160 10:02:20.558019 DQS Delay:
8161 10:02:20.561187 DQS0 = 0, DQS1 = 0
8162 10:02:20.561301 DQM Delay:
8163 10:02:20.564328 DQM0 = 133, DQM1 = 129
8164 10:02:20.564441 DQ Delay:
8165 10:02:20.567488 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8166 10:02:20.570703 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8167 10:02:20.574229 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8168 10:02:20.581079 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8169 10:02:20.581195
8170 10:02:20.581274
8171 10:02:20.581399 ==
8172 10:02:20.583927 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 10:02:20.587493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 10:02:20.587575 ==
8175 10:02:20.587640
8176 10:02:20.587698
8177 10:02:20.590783 TX Vref Scan disable
8178 10:02:20.590865 == TX Byte 0 ==
8179 10:02:20.597305 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8180 10:02:20.600979 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8181 10:02:20.601063 == TX Byte 1 ==
8182 10:02:20.607266 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8183 10:02:20.610613 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8184 10:02:20.610696 ==
8185 10:02:20.613848 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 10:02:20.616947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 10:02:20.617030 ==
8188 10:02:20.631564
8189 10:02:20.635049 TX Vref early break, caculate TX vref
8190 10:02:20.638508 TX Vref=16, minBit 0, minWin=22, winSum=375
8191 10:02:20.641798 TX Vref=18, minBit 0, minWin=23, winSum=384
8192 10:02:20.644699 TX Vref=20, minBit 2, minWin=23, winSum=392
8193 10:02:20.647962 TX Vref=22, minBit 1, minWin=23, winSum=401
8194 10:02:20.651236 TX Vref=24, minBit 1, minWin=24, winSum=409
8195 10:02:20.658065 TX Vref=26, minBit 1, minWin=24, winSum=410
8196 10:02:20.661343 TX Vref=28, minBit 0, minWin=24, winSum=413
8197 10:02:20.664543 TX Vref=30, minBit 1, minWin=24, winSum=406
8198 10:02:20.667851 TX Vref=32, minBit 0, minWin=24, winSum=398
8199 10:02:20.671150 TX Vref=34, minBit 2, minWin=23, winSum=387
8200 10:02:20.677900 [TxChooseVref] Worse bit 0, Min win 24, Win sum 413, Final Vref 28
8201 10:02:20.678012
8202 10:02:20.681261 Final TX Range 0 Vref 28
8203 10:02:20.681347
8204 10:02:20.681420 ==
8205 10:02:20.683981 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 10:02:20.687497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 10:02:20.687577 ==
8208 10:02:20.687641
8209 10:02:20.687709
8210 10:02:20.691170 TX Vref Scan disable
8211 10:02:20.697356 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8212 10:02:20.697432 == TX Byte 0 ==
8213 10:02:20.700741 u2DelayCellOfst[0]=11 cells (3 PI)
8214 10:02:20.703908 u2DelayCellOfst[1]=15 cells (4 PI)
8215 10:02:20.707519 u2DelayCellOfst[2]=11 cells (3 PI)
8216 10:02:20.710726 u2DelayCellOfst[3]=11 cells (3 PI)
8217 10:02:20.713995 u2DelayCellOfst[4]=7 cells (2 PI)
8218 10:02:20.717037 u2DelayCellOfst[5]=0 cells (0 PI)
8219 10:02:20.720168 u2DelayCellOfst[6]=15 cells (4 PI)
8220 10:02:20.724183 u2DelayCellOfst[7]=18 cells (5 PI)
8221 10:02:20.727632 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8222 10:02:20.730328 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8223 10:02:20.733493 == TX Byte 1 ==
8224 10:02:20.736775 u2DelayCellOfst[8]=0 cells (0 PI)
8225 10:02:20.740044 u2DelayCellOfst[9]=3 cells (1 PI)
8226 10:02:20.743513 u2DelayCellOfst[10]=7 cells (2 PI)
8227 10:02:20.747137 u2DelayCellOfst[11]=3 cells (1 PI)
8228 10:02:20.747215 u2DelayCellOfst[12]=11 cells (3 PI)
8229 10:02:20.750451 u2DelayCellOfst[13]=15 cells (4 PI)
8230 10:02:20.753578 u2DelayCellOfst[14]=18 cells (5 PI)
8231 10:02:20.756703 u2DelayCellOfst[15]=15 cells (4 PI)
8232 10:02:20.763296 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8233 10:02:20.766568 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8234 10:02:20.766645 DramC Write-DBI on
8235 10:02:20.770448 ==
8236 10:02:20.773524 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 10:02:20.776495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 10:02:20.776595 ==
8239 10:02:20.776661
8240 10:02:20.776721
8241 10:02:20.779748 TX Vref Scan disable
8242 10:02:20.779830 == TX Byte 0 ==
8243 10:02:20.786460 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8244 10:02:20.786541 == TX Byte 1 ==
8245 10:02:20.790111 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8246 10:02:20.794347 DramC Write-DBI off
8247 10:02:20.794431
8248 10:02:20.794500 [DATLAT]
8249 10:02:20.796726 Freq=1600, CH0 RK1
8250 10:02:20.796813
8251 10:02:20.796896 DATLAT Default: 0xf
8252 10:02:20.799711 0, 0xFFFF, sum = 0
8253 10:02:20.799787 1, 0xFFFF, sum = 0
8254 10:02:20.803491 2, 0xFFFF, sum = 0
8255 10:02:20.803572 3, 0xFFFF, sum = 0
8256 10:02:20.806311 4, 0xFFFF, sum = 0
8257 10:02:20.806384 5, 0xFFFF, sum = 0
8258 10:02:20.809964 6, 0xFFFF, sum = 0
8259 10:02:20.813286 7, 0xFFFF, sum = 0
8260 10:02:20.813373 8, 0xFFFF, sum = 0
8261 10:02:20.816058 9, 0xFFFF, sum = 0
8262 10:02:20.816139 10, 0xFFFF, sum = 0
8263 10:02:20.819487 11, 0xFFFF, sum = 0
8264 10:02:20.819562 12, 0xFFFF, sum = 0
8265 10:02:20.822734 13, 0xFFFF, sum = 0
8266 10:02:20.822809 14, 0x0, sum = 1
8267 10:02:20.826709 15, 0x0, sum = 2
8268 10:02:20.826784 16, 0x0, sum = 3
8269 10:02:20.829250 17, 0x0, sum = 4
8270 10:02:20.829346 best_step = 15
8271 10:02:20.829427
8272 10:02:20.829486 ==
8273 10:02:20.832631 Dram Type= 6, Freq= 0, CH_0, rank 1
8274 10:02:20.836428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 10:02:20.836576 ==
8276 10:02:20.839723 RX Vref Scan: 0
8277 10:02:20.839796
8278 10:02:20.842999 RX Vref 0 -> 0, step: 1
8279 10:02:20.843083
8280 10:02:20.843148 RX Delay 11 -> 252, step: 4
8281 10:02:20.849909 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8282 10:02:20.853618 iDelay=195, Bit 1, Center 136 (83 ~ 190) 108
8283 10:02:20.856670 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8284 10:02:20.860013 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8285 10:02:20.866586 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8286 10:02:20.870078 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8287 10:02:20.873037 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8288 10:02:20.876796 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8289 10:02:20.879581 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8290 10:02:20.886403 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8291 10:02:20.889614 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8292 10:02:20.893127 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8293 10:02:20.896441 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8294 10:02:20.899604 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8295 10:02:20.905963 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8296 10:02:20.909661 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8297 10:02:20.909738 ==
8298 10:02:20.913142 Dram Type= 6, Freq= 0, CH_0, rank 1
8299 10:02:20.915966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 10:02:20.916080 ==
8301 10:02:20.919173 DQS Delay:
8302 10:02:20.919251 DQS0 = 0, DQS1 = 0
8303 10:02:20.919314 DQM Delay:
8304 10:02:20.922977 DQM0 = 130, DQM1 = 125
8305 10:02:20.923052 DQ Delay:
8306 10:02:20.926043 DQ0 =128, DQ1 =136, DQ2 =126, DQ3 =128
8307 10:02:20.929590 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =140
8308 10:02:20.932653 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8309 10:02:20.939233 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8310 10:02:20.939332
8311 10:02:20.939396
8312 10:02:20.939464
8313 10:02:20.942658 [DramC_TX_OE_Calibration] TA2
8314 10:02:20.945929 Original DQ_B0 (3 6) =30, OEN = 27
8315 10:02:20.946004 Original DQ_B1 (3 6) =30, OEN = 27
8316 10:02:20.949163 24, 0x0, End_B0=24 End_B1=24
8317 10:02:20.952631 25, 0x0, End_B0=25 End_B1=25
8318 10:02:20.955756 26, 0x0, End_B0=26 End_B1=26
8319 10:02:20.959229 27, 0x0, End_B0=27 End_B1=27
8320 10:02:20.959309 28, 0x0, End_B0=28 End_B1=28
8321 10:02:20.962373 29, 0x0, End_B0=29 End_B1=29
8322 10:02:20.965535 30, 0x0, End_B0=30 End_B1=30
8323 10:02:20.968899 31, 0x4141, End_B0=30 End_B1=30
8324 10:02:20.972783 Byte0 end_step=30 best_step=27
8325 10:02:20.975925 Byte1 end_step=30 best_step=27
8326 10:02:20.976001 Byte0 TX OE(2T, 0.5T) = (3, 3)
8327 10:02:20.979332 Byte1 TX OE(2T, 0.5T) = (3, 3)
8328 10:02:20.979411
8329 10:02:20.979479
8330 10:02:20.988926 [DQSOSCAuto] RK1, (LSB)MR18= 0x2003, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8331 10:02:20.992219 CH0 RK1: MR19=303, MR18=2003
8332 10:02:20.995642 CH0_RK1: MR19=0x303, MR18=0x2003, DQSOSC=393, MR23=63, INC=23, DEC=15
8333 10:02:20.998913 [RxdqsGatingPostProcess] freq 1600
8334 10:02:21.005537 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8335 10:02:21.008445 best DQS0 dly(2T, 0.5T) = (1, 1)
8336 10:02:21.012249 best DQS1 dly(2T, 0.5T) = (1, 1)
8337 10:02:21.015164 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8338 10:02:21.018609 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8339 10:02:21.021517 best DQS0 dly(2T, 0.5T) = (1, 1)
8340 10:02:21.025235 best DQS1 dly(2T, 0.5T) = (1, 1)
8341 10:02:21.028160 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8342 10:02:21.028238 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8343 10:02:21.031784 Pre-setting of DQS Precalculation
8344 10:02:21.039732 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8345 10:02:21.039811 ==
8346 10:02:21.041281 Dram Type= 6, Freq= 0, CH_1, rank 0
8347 10:02:21.045131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 10:02:21.045206 ==
8349 10:02:21.051684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8350 10:02:21.054660 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8351 10:02:21.058162 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8352 10:02:21.064547 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8353 10:02:21.074569 [CA 0] Center 42 (13~72) winsize 60
8354 10:02:21.077501 [CA 1] Center 43 (14~72) winsize 59
8355 10:02:21.081349 [CA 2] Center 37 (9~66) winsize 58
8356 10:02:21.084681 [CA 3] Center 37 (8~66) winsize 59
8357 10:02:21.087738 [CA 4] Center 38 (8~68) winsize 61
8358 10:02:21.090636 [CA 5] Center 37 (8~67) winsize 60
8359 10:02:21.090717
8360 10:02:21.094305 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8361 10:02:21.094387
8362 10:02:21.097457 [CATrainingPosCal] consider 1 rank data
8363 10:02:21.100705 u2DelayCellTimex100 = 258/100 ps
8364 10:02:21.104196 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8365 10:02:21.110685 CA1 delay=43 (14~72),Diff = 6 PI (22 cell)
8366 10:02:21.114368 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8367 10:02:21.117728 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8368 10:02:21.120663 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8369 10:02:21.123884 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8370 10:02:21.123965
8371 10:02:21.127077 CA PerBit enable=1, Macro0, CA PI delay=37
8372 10:02:21.127158
8373 10:02:21.130725 [CBTSetCACLKResult] CA Dly = 37
8374 10:02:21.133725 CS Dly: 9 (0~40)
8375 10:02:21.137091 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8376 10:02:21.140347 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8377 10:02:21.140427 ==
8378 10:02:21.144134 Dram Type= 6, Freq= 0, CH_1, rank 1
8379 10:02:21.147136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 10:02:21.150564 ==
8381 10:02:21.153632 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8382 10:02:21.157004 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8383 10:02:21.163587 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8384 10:02:21.170241 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8385 10:02:21.177446 [CA 0] Center 41 (12~71) winsize 60
8386 10:02:21.180817 [CA 1] Center 42 (13~72) winsize 60
8387 10:02:21.184617 [CA 2] Center 37 (8~67) winsize 60
8388 10:02:21.187562 [CA 3] Center 36 (7~66) winsize 60
8389 10:02:21.190390 [CA 4] Center 37 (8~67) winsize 60
8390 10:02:21.193879 [CA 5] Center 36 (7~66) winsize 60
8391 10:02:21.194035
8392 10:02:21.197306 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8393 10:02:21.197415
8394 10:02:21.203722 [CATrainingPosCal] consider 2 rank data
8395 10:02:21.203809 u2DelayCellTimex100 = 258/100 ps
8396 10:02:21.210080 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8397 10:02:21.213870 CA1 delay=43 (14~72),Diff = 6 PI (22 cell)
8398 10:02:21.216929 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8399 10:02:21.220474 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8400 10:02:21.223519 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8401 10:02:21.226470 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8402 10:02:21.226542
8403 10:02:21.230076 CA PerBit enable=1, Macro0, CA PI delay=37
8404 10:02:21.230148
8405 10:02:21.233500 [CBTSetCACLKResult] CA Dly = 37
8406 10:02:21.236340 CS Dly: 10 (0~43)
8407 10:02:21.240312 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8408 10:02:21.243283 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8409 10:02:21.243361
8410 10:02:21.246751 ----->DramcWriteLeveling(PI) begin...
8411 10:02:21.246822 ==
8412 10:02:21.250396 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 10:02:21.256655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 10:02:21.256732 ==
8415 10:02:21.259763 Write leveling (Byte 0): 23 => 23
8416 10:02:21.263182 Write leveling (Byte 1): 27 => 27
8417 10:02:21.265960 DramcWriteLeveling(PI) end<-----
8418 10:02:21.266031
8419 10:02:21.266092 ==
8420 10:02:21.269291 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 10:02:21.272598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 10:02:21.272668 ==
8423 10:02:21.276354 [Gating] SW mode calibration
8424 10:02:21.282830 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8425 10:02:21.289137 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8426 10:02:21.292431 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 10:02:21.295843 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 10:02:21.302107 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8429 10:02:21.305837 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8430 10:02:21.309395 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8431 10:02:21.315833 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8432 10:02:21.318571 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8433 10:02:21.322110 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8434 10:02:21.329146 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8435 10:02:21.332295 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8436 10:02:21.335044 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8437 10:02:21.341920 1 5 12 | B1->B0 | 2f2f 2424 | 1 1 | (1 0) (1 0)
8438 10:02:21.345289 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 10:02:21.348602 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 10:02:21.354968 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 10:02:21.358456 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8442 10:02:21.361666 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8443 10:02:21.368302 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8444 10:02:21.372086 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8445 10:02:21.375197 1 6 12 | B1->B0 | 3635 4141 | 1 0 | (0 0) (1 1)
8446 10:02:21.381435 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 10:02:21.384777 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 10:02:21.388173 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8449 10:02:21.394647 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8450 10:02:21.398248 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8451 10:02:21.401364 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8452 10:02:21.407981 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8453 10:02:21.411240 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8454 10:02:21.414405 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 10:02:21.421584 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 10:02:21.424416 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 10:02:21.427625 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 10:02:21.434108 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 10:02:21.437352 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 10:02:21.441272 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 10:02:21.447638 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 10:02:21.450778 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 10:02:21.453960 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 10:02:21.461017 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 10:02:21.464164 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 10:02:21.467413 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 10:02:21.474261 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 10:02:21.477359 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8469 10:02:21.480480 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8470 10:02:21.487034 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8471 10:02:21.487119 Total UI for P1: 0, mck2ui 16
8472 10:02:21.490391 best dqsien dly found for B0: ( 1, 9, 10)
8473 10:02:21.493843 Total UI for P1: 0, mck2ui 16
8474 10:02:21.496843 best dqsien dly found for B1: ( 1, 9, 10)
8475 10:02:21.503456 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8476 10:02:21.506573 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8477 10:02:21.506646
8478 10:02:21.510008 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8479 10:02:21.513370 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8480 10:02:21.517009 [Gating] SW calibration Done
8481 10:02:21.517082 ==
8482 10:02:21.519894 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 10:02:21.523393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 10:02:21.523467 ==
8485 10:02:21.526502 RX Vref Scan: 0
8486 10:02:21.526572
8487 10:02:21.526632 RX Vref 0 -> 0, step: 1
8488 10:02:21.526713
8489 10:02:21.529801 RX Delay 0 -> 252, step: 8
8490 10:02:21.533228 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8491 10:02:21.539998 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8492 10:02:21.542916 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8493 10:02:21.546978 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8494 10:02:21.549615 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8495 10:02:21.553052 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8496 10:02:21.559790 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8497 10:02:21.562685 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8498 10:02:21.566200 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8499 10:02:21.569246 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8500 10:02:21.572644 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8501 10:02:21.579179 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8502 10:02:21.582586 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8503 10:02:21.585731 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8504 10:02:21.589727 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8505 10:02:21.595882 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8506 10:02:21.595965 ==
8507 10:02:21.599262 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 10:02:21.602510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 10:02:21.602594 ==
8510 10:02:21.602660 DQS Delay:
8511 10:02:21.606230 DQS0 = 0, DQS1 = 0
8512 10:02:21.606312 DQM Delay:
8513 10:02:21.609003 DQM0 = 137, DQM1 = 128
8514 10:02:21.609086 DQ Delay:
8515 10:02:21.612660 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8516 10:02:21.615722 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8517 10:02:21.619495 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8518 10:02:21.622426 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8519 10:02:21.622509
8520 10:02:21.622574
8521 10:02:21.625825 ==
8522 10:02:21.629068 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 10:02:21.632408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 10:02:21.632526 ==
8525 10:02:21.632609
8526 10:02:21.632670
8527 10:02:21.635707 TX Vref Scan disable
8528 10:02:21.635790 == TX Byte 0 ==
8529 10:02:21.642254 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8530 10:02:21.645552 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8531 10:02:21.645635 == TX Byte 1 ==
8532 10:02:21.651997 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8533 10:02:21.655456 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8534 10:02:21.655535 ==
8535 10:02:21.658549 Dram Type= 6, Freq= 0, CH_1, rank 0
8536 10:02:21.661881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8537 10:02:21.661959 ==
8538 10:02:21.675630
8539 10:02:21.678943 TX Vref early break, caculate TX vref
8540 10:02:21.681887 TX Vref=16, minBit 5, minWin=21, winSum=373
8541 10:02:21.685260 TX Vref=18, minBit 0, minWin=22, winSum=383
8542 10:02:21.688476 TX Vref=20, minBit 0, minWin=22, winSum=389
8543 10:02:21.691977 TX Vref=22, minBit 0, minWin=23, winSum=400
8544 10:02:21.695118 TX Vref=24, minBit 0, minWin=23, winSum=410
8545 10:02:21.701929 TX Vref=26, minBit 0, minWin=25, winSum=417
8546 10:02:21.705179 TX Vref=28, minBit 0, minWin=24, winSum=413
8547 10:02:21.708441 TX Vref=30, minBit 1, minWin=24, winSum=408
8548 10:02:21.711445 TX Vref=32, minBit 0, minWin=23, winSum=397
8549 10:02:21.715059 TX Vref=34, minBit 5, minWin=22, winSum=389
8550 10:02:21.721575 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 26
8551 10:02:21.721659
8552 10:02:21.724703 Final TX Range 0 Vref 26
8553 10:02:21.724841
8554 10:02:21.724926 ==
8555 10:02:21.728334 Dram Type= 6, Freq= 0, CH_1, rank 0
8556 10:02:21.731713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8557 10:02:21.731796 ==
8558 10:02:21.731861
8559 10:02:21.731922
8560 10:02:21.735052 TX Vref Scan disable
8561 10:02:21.741256 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8562 10:02:21.741339 == TX Byte 0 ==
8563 10:02:21.744477 u2DelayCellOfst[0]=18 cells (5 PI)
8564 10:02:21.748709 u2DelayCellOfst[1]=15 cells (4 PI)
8565 10:02:21.751434 u2DelayCellOfst[2]=0 cells (0 PI)
8566 10:02:21.754688 u2DelayCellOfst[3]=7 cells (2 PI)
8567 10:02:21.757995 u2DelayCellOfst[4]=11 cells (3 PI)
8568 10:02:21.761200 u2DelayCellOfst[5]=22 cells (6 PI)
8569 10:02:21.764876 u2DelayCellOfst[6]=22 cells (6 PI)
8570 10:02:21.767951 u2DelayCellOfst[7]=7 cells (2 PI)
8571 10:02:21.771783 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8572 10:02:21.774393 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8573 10:02:21.777648 == TX Byte 1 ==
8574 10:02:21.780979 u2DelayCellOfst[8]=0 cells (0 PI)
8575 10:02:21.781061 u2DelayCellOfst[9]=3 cells (1 PI)
8576 10:02:21.784401 u2DelayCellOfst[10]=11 cells (3 PI)
8577 10:02:21.788199 u2DelayCellOfst[11]=3 cells (1 PI)
8578 10:02:21.790978 u2DelayCellOfst[12]=15 cells (4 PI)
8579 10:02:21.794197 u2DelayCellOfst[13]=15 cells (4 PI)
8580 10:02:21.797632 u2DelayCellOfst[14]=18 cells (5 PI)
8581 10:02:21.800829 u2DelayCellOfst[15]=18 cells (5 PI)
8582 10:02:21.807607 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8583 10:02:21.810830 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8584 10:02:21.810913 DramC Write-DBI on
8585 10:02:21.810978 ==
8586 10:02:21.814203 Dram Type= 6, Freq= 0, CH_1, rank 0
8587 10:02:21.820584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8588 10:02:21.820667 ==
8589 10:02:21.820733
8590 10:02:21.820794
8591 10:02:21.823992 TX Vref Scan disable
8592 10:02:21.824074 == TX Byte 0 ==
8593 10:02:21.830241 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8594 10:02:21.830339 == TX Byte 1 ==
8595 10:02:21.833378 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8596 10:02:21.837104 DramC Write-DBI off
8597 10:02:21.837203
8598 10:02:21.837269 [DATLAT]
8599 10:02:21.840189 Freq=1600, CH1 RK0
8600 10:02:21.840300
8601 10:02:21.840365 DATLAT Default: 0xf
8602 10:02:21.843277 0, 0xFFFF, sum = 0
8603 10:02:21.843365 1, 0xFFFF, sum = 0
8604 10:02:21.846804 2, 0xFFFF, sum = 0
8605 10:02:21.846882 3, 0xFFFF, sum = 0
8606 10:02:21.849987 4, 0xFFFF, sum = 0
8607 10:02:21.850060 5, 0xFFFF, sum = 0
8608 10:02:21.853252 6, 0xFFFF, sum = 0
8609 10:02:21.856276 7, 0xFFFF, sum = 0
8610 10:02:21.856351 8, 0xFFFF, sum = 0
8611 10:02:21.859686 9, 0xFFFF, sum = 0
8612 10:02:21.859763 10, 0xFFFF, sum = 0
8613 10:02:21.862805 11, 0xFFFF, sum = 0
8614 10:02:21.862881 12, 0xFFFF, sum = 0
8615 10:02:21.866306 13, 0xFFFF, sum = 0
8616 10:02:21.866380 14, 0x0, sum = 1
8617 10:02:21.869818 15, 0x0, sum = 2
8618 10:02:21.869895 16, 0x0, sum = 3
8619 10:02:21.873130 17, 0x0, sum = 4
8620 10:02:21.873206 best_step = 15
8621 10:02:21.873268
8622 10:02:21.873330 ==
8623 10:02:21.876112 Dram Type= 6, Freq= 0, CH_1, rank 0
8624 10:02:21.879424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8625 10:02:21.882882 ==
8626 10:02:21.882961 RX Vref Scan: 1
8627 10:02:21.883025
8628 10:02:21.886090 Set Vref Range= 24 -> 127
8629 10:02:21.886159
8630 10:02:21.889626 RX Vref 24 -> 127, step: 1
8631 10:02:21.889709
8632 10:02:21.889773 RX Delay 11 -> 252, step: 4
8633 10:02:21.889840
8634 10:02:21.892440 Set Vref, RX VrefLevel [Byte0]: 24
8635 10:02:21.895956 [Byte1]: 24
8636 10:02:21.899951
8637 10:02:21.900026 Set Vref, RX VrefLevel [Byte0]: 25
8638 10:02:21.903202 [Byte1]: 25
8639 10:02:21.907453
8640 10:02:21.907526 Set Vref, RX VrefLevel [Byte0]: 26
8641 10:02:21.910727 [Byte1]: 26
8642 10:02:21.914803
8643 10:02:21.914883 Set Vref, RX VrefLevel [Byte0]: 27
8644 10:02:21.918287 [Byte1]: 27
8645 10:02:21.922651
8646 10:02:21.922735 Set Vref, RX VrefLevel [Byte0]: 28
8647 10:02:21.926242 [Byte1]: 28
8648 10:02:21.930023
8649 10:02:21.930100 Set Vref, RX VrefLevel [Byte0]: 29
8650 10:02:21.933703 [Byte1]: 29
8651 10:02:21.938076
8652 10:02:21.938155 Set Vref, RX VrefLevel [Byte0]: 30
8653 10:02:21.941375 [Byte1]: 30
8654 10:02:21.945581
8655 10:02:21.945665 Set Vref, RX VrefLevel [Byte0]: 31
8656 10:02:21.948770 [Byte1]: 31
8657 10:02:21.953361
8658 10:02:21.953443 Set Vref, RX VrefLevel [Byte0]: 32
8659 10:02:21.956712 [Byte1]: 32
8660 10:02:21.960708
8661 10:02:21.960790 Set Vref, RX VrefLevel [Byte0]: 33
8662 10:02:21.964216 [Byte1]: 33
8663 10:02:21.968120
8664 10:02:21.968204 Set Vref, RX VrefLevel [Byte0]: 34
8665 10:02:21.971629 [Byte1]: 34
8666 10:02:21.975655
8667 10:02:21.975724 Set Vref, RX VrefLevel [Byte0]: 35
8668 10:02:21.979385 [Byte1]: 35
8669 10:02:21.983388
8670 10:02:21.983498 Set Vref, RX VrefLevel [Byte0]: 36
8671 10:02:21.987141 [Byte1]: 36
8672 10:02:21.991566
8673 10:02:21.991668 Set Vref, RX VrefLevel [Byte0]: 37
8674 10:02:21.994666 [Byte1]: 37
8675 10:02:21.998552
8676 10:02:21.998625 Set Vref, RX VrefLevel [Byte0]: 38
8677 10:02:22.002680 [Byte1]: 38
8678 10:02:22.006153
8679 10:02:22.006233 Set Vref, RX VrefLevel [Byte0]: 39
8680 10:02:22.009506 [Byte1]: 39
8681 10:02:22.014005
8682 10:02:22.014077 Set Vref, RX VrefLevel [Byte0]: 40
8683 10:02:22.017228 [Byte1]: 40
8684 10:02:22.022022
8685 10:02:22.022100 Set Vref, RX VrefLevel [Byte0]: 41
8686 10:02:22.024717 [Byte1]: 41
8687 10:02:22.029275
8688 10:02:22.029357 Set Vref, RX VrefLevel [Byte0]: 42
8689 10:02:22.032435 [Byte1]: 42
8690 10:02:22.037145
8691 10:02:22.037225 Set Vref, RX VrefLevel [Byte0]: 43
8692 10:02:22.039937 [Byte1]: 43
8693 10:02:22.044550
8694 10:02:22.044626 Set Vref, RX VrefLevel [Byte0]: 44
8695 10:02:22.048023 [Byte1]: 44
8696 10:02:22.052234
8697 10:02:22.052307 Set Vref, RX VrefLevel [Byte0]: 45
8698 10:02:22.055347 [Byte1]: 45
8699 10:02:22.059891
8700 10:02:22.059998 Set Vref, RX VrefLevel [Byte0]: 46
8701 10:02:22.062992 [Byte1]: 46
8702 10:02:22.067249
8703 10:02:22.067327 Set Vref, RX VrefLevel [Byte0]: 47
8704 10:02:22.070451 [Byte1]: 47
8705 10:02:22.075129
8706 10:02:22.075204 Set Vref, RX VrefLevel [Byte0]: 48
8707 10:02:22.078011 [Byte1]: 48
8708 10:02:22.082454
8709 10:02:22.082534 Set Vref, RX VrefLevel [Byte0]: 49
8710 10:02:22.086043 [Byte1]: 49
8711 10:02:22.090701
8712 10:02:22.090775 Set Vref, RX VrefLevel [Byte0]: 50
8713 10:02:22.093664 [Byte1]: 50
8714 10:02:22.098023
8715 10:02:22.098099 Set Vref, RX VrefLevel [Byte0]: 51
8716 10:02:22.100879 [Byte1]: 51
8717 10:02:22.105583
8718 10:02:22.105661 Set Vref, RX VrefLevel [Byte0]: 52
8719 10:02:22.108936 [Byte1]: 52
8720 10:02:22.113352
8721 10:02:22.113425 Set Vref, RX VrefLevel [Byte0]: 53
8722 10:02:22.116106 [Byte1]: 53
8723 10:02:22.120675
8724 10:02:22.120747 Set Vref, RX VrefLevel [Byte0]: 54
8725 10:02:22.123885 [Byte1]: 54
8726 10:02:22.128047
8727 10:02:22.128118 Set Vref, RX VrefLevel [Byte0]: 55
8728 10:02:22.131309 [Byte1]: 55
8729 10:02:22.135857
8730 10:02:22.135931 Set Vref, RX VrefLevel [Byte0]: 56
8731 10:02:22.139257 [Byte1]: 56
8732 10:02:22.143170
8733 10:02:22.143247 Set Vref, RX VrefLevel [Byte0]: 57
8734 10:02:22.147375 [Byte1]: 57
8735 10:02:22.151243
8736 10:02:22.151314 Set Vref, RX VrefLevel [Byte0]: 58
8737 10:02:22.154460 [Byte1]: 58
8738 10:02:22.158460
8739 10:02:22.158532 Set Vref, RX VrefLevel [Byte0]: 59
8740 10:02:22.162436 [Byte1]: 59
8741 10:02:22.166571
8742 10:02:22.166651 Set Vref, RX VrefLevel [Byte0]: 60
8743 10:02:22.169386 [Byte1]: 60
8744 10:02:22.174023
8745 10:02:22.174095 Set Vref, RX VrefLevel [Byte0]: 61
8746 10:02:22.177539 [Byte1]: 61
8747 10:02:22.181571
8748 10:02:22.181671 Set Vref, RX VrefLevel [Byte0]: 62
8749 10:02:22.184586 [Byte1]: 62
8750 10:02:22.188860
8751 10:02:22.188941 Set Vref, RX VrefLevel [Byte0]: 63
8752 10:02:22.195673 [Byte1]: 63
8753 10:02:22.195748
8754 10:02:22.198728 Set Vref, RX VrefLevel [Byte0]: 64
8755 10:02:22.202108 [Byte1]: 64
8756 10:02:22.202183
8757 10:02:22.205168 Set Vref, RX VrefLevel [Byte0]: 65
8758 10:02:22.208772 [Byte1]: 65
8759 10:02:22.212020
8760 10:02:22.212099 Set Vref, RX VrefLevel [Byte0]: 66
8761 10:02:22.215266 [Byte1]: 66
8762 10:02:22.219445
8763 10:02:22.219516 Set Vref, RX VrefLevel [Byte0]: 67
8764 10:02:22.222957 [Byte1]: 67
8765 10:02:22.227307
8766 10:02:22.227384 Set Vref, RX VrefLevel [Byte0]: 68
8767 10:02:22.230489 [Byte1]: 68
8768 10:02:22.234965
8769 10:02:22.235066 Set Vref, RX VrefLevel [Byte0]: 69
8770 10:02:22.237884 [Byte1]: 69
8771 10:02:22.242142
8772 10:02:22.242214 Set Vref, RX VrefLevel [Byte0]: 70
8773 10:02:22.245980 [Byte1]: 70
8774 10:02:22.249731
8775 10:02:22.249812 Set Vref, RX VrefLevel [Byte0]: 71
8776 10:02:22.253279 [Byte1]: 71
8777 10:02:22.257298
8778 10:02:22.257370 Final RX Vref Byte 0 = 55 to rank0
8779 10:02:22.261217 Final RX Vref Byte 1 = 60 to rank0
8780 10:02:22.264524 Final RX Vref Byte 0 = 55 to rank1
8781 10:02:22.267576 Final RX Vref Byte 1 = 60 to rank1==
8782 10:02:22.270793 Dram Type= 6, Freq= 0, CH_1, rank 0
8783 10:02:22.277149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8784 10:02:22.277231 ==
8785 10:02:22.277295 DQS Delay:
8786 10:02:22.280634 DQS0 = 0, DQS1 = 0
8787 10:02:22.280716 DQM Delay:
8788 10:02:22.280779 DQM0 = 133, DQM1 = 128
8789 10:02:22.283755 DQ Delay:
8790 10:02:22.287263 DQ0 =140, DQ1 =126, DQ2 =124, DQ3 =130
8791 10:02:22.290879 DQ4 =132, DQ5 =146, DQ6 =144, DQ7 =128
8792 10:02:22.293911 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8793 10:02:22.297018 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8794 10:02:22.297099
8795 10:02:22.297162
8796 10:02:22.297220
8797 10:02:22.300242 [DramC_TX_OE_Calibration] TA2
8798 10:02:22.303756 Original DQ_B0 (3 6) =30, OEN = 27
8799 10:02:22.306762 Original DQ_B1 (3 6) =30, OEN = 27
8800 10:02:22.310535 24, 0x0, End_B0=24 End_B1=24
8801 10:02:22.313689 25, 0x0, End_B0=25 End_B1=25
8802 10:02:22.313767 26, 0x0, End_B0=26 End_B1=26
8803 10:02:22.316688 27, 0x0, End_B0=27 End_B1=27
8804 10:02:22.320375 28, 0x0, End_B0=28 End_B1=28
8805 10:02:22.323479 29, 0x0, End_B0=29 End_B1=29
8806 10:02:22.323554 30, 0x0, End_B0=30 End_B1=30
8807 10:02:22.326833 31, 0x4141, End_B0=30 End_B1=30
8808 10:02:22.330090 Byte0 end_step=30 best_step=27
8809 10:02:22.333600 Byte1 end_step=30 best_step=27
8810 10:02:22.336834 Byte0 TX OE(2T, 0.5T) = (3, 3)
8811 10:02:22.340120 Byte1 TX OE(2T, 0.5T) = (3, 3)
8812 10:02:22.340195
8813 10:02:22.340257
8814 10:02:22.346696 [DQSOSCAuto] RK0, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8815 10:02:22.349963 CH1 RK0: MR19=303, MR18=180D
8816 10:02:22.356435 CH1_RK0: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8817 10:02:22.356555
8818 10:02:22.359696 ----->DramcWriteLeveling(PI) begin...
8819 10:02:22.359772 ==
8820 10:02:22.362928 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 10:02:22.366499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 10:02:22.366571 ==
8823 10:02:22.369832 Write leveling (Byte 0): 23 => 23
8824 10:02:22.373035 Write leveling (Byte 1): 28 => 28
8825 10:02:22.376065 DramcWriteLeveling(PI) end<-----
8826 10:02:22.376134
8827 10:02:22.376194 ==
8828 10:02:22.379276 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 10:02:22.385980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 10:02:22.386062 ==
8831 10:02:22.386127 [Gating] SW mode calibration
8832 10:02:22.396289 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8833 10:02:22.399517 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8834 10:02:22.402782 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 10:02:22.409306 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 10:02:22.412755 1 4 8 | B1->B0 | 2625 2323 | 1 0 | (0 0) (0 0)
8837 10:02:22.415806 1 4 12 | B1->B0 | 3434 2323 | 1 0 | (0 0) (0 0)
8838 10:02:22.422258 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 10:02:22.425926 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 10:02:22.428753 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8841 10:02:22.435680 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8842 10:02:22.438794 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8843 10:02:22.441998 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8844 10:02:22.448779 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8845 10:02:22.452125 1 5 12 | B1->B0 | 2828 3434 | 0 1 | (1 0) (1 0)
8846 10:02:22.455300 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8847 10:02:22.462135 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 10:02:22.465486 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 10:02:22.468372 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8850 10:02:22.475382 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 10:02:22.478683 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 10:02:22.481574 1 6 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8853 10:02:22.488776 1 6 12 | B1->B0 | 4545 2424 | 0 0 | (0 0) (0 0)
8854 10:02:22.491458 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 10:02:22.494916 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 10:02:22.501835 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 10:02:22.505264 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 10:02:22.508291 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 10:02:22.514646 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 10:02:22.517977 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8861 10:02:22.521438 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8862 10:02:22.527936 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8863 10:02:22.531134 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 10:02:22.534408 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 10:02:22.541385 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 10:02:22.544278 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 10:02:22.547405 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 10:02:22.554243 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 10:02:22.557850 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 10:02:22.560737 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 10:02:22.567495 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 10:02:22.570794 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 10:02:22.574115 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 10:02:22.580775 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 10:02:22.583836 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 10:02:22.587454 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8877 10:02:22.593520 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8878 10:02:22.597017 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8879 10:02:22.600552 Total UI for P1: 0, mck2ui 16
8880 10:02:22.603928 best dqsien dly found for B0: ( 1, 9, 12)
8881 10:02:22.607189 Total UI for P1: 0, mck2ui 16
8882 10:02:22.610576 best dqsien dly found for B1: ( 1, 9, 10)
8883 10:02:22.613752 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8884 10:02:22.616789 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8885 10:02:22.616872
8886 10:02:22.620004 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8887 10:02:22.627205 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8888 10:02:22.627317 [Gating] SW calibration Done
8889 10:02:22.627383 ==
8890 10:02:22.630402 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 10:02:22.636676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 10:02:22.636759 ==
8893 10:02:22.636857 RX Vref Scan: 0
8894 10:02:22.636949
8895 10:02:22.640444 RX Vref 0 -> 0, step: 1
8896 10:02:22.640572
8897 10:02:22.643081 RX Delay 0 -> 252, step: 8
8898 10:02:22.646449 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8899 10:02:22.649646 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8900 10:02:22.653235 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8901 10:02:22.659520 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8902 10:02:22.662910 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8903 10:02:22.666230 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8904 10:02:22.669542 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8905 10:02:22.672850 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8906 10:02:22.679309 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8907 10:02:22.682874 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8908 10:02:22.685821 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8909 10:02:22.689367 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8910 10:02:22.693044 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8911 10:02:22.699099 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8912 10:02:22.702746 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8913 10:02:22.705664 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8914 10:02:22.705766 ==
8915 10:02:22.708886 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 10:02:22.712453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 10:02:22.715880 ==
8918 10:02:22.715984 DQS Delay:
8919 10:02:22.716076 DQS0 = 0, DQS1 = 0
8920 10:02:22.718846 DQM Delay:
8921 10:02:22.718949 DQM0 = 136, DQM1 = 130
8922 10:02:22.722229 DQ Delay:
8923 10:02:22.725536 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =131
8924 10:02:22.728909 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8925 10:02:22.731843 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8926 10:02:22.735397 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8927 10:02:22.735506
8928 10:02:22.735600
8929 10:02:22.735696 ==
8930 10:02:22.739045 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 10:02:22.742458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 10:02:22.745774 ==
8933 10:02:22.745879
8934 10:02:22.745973
8935 10:02:22.746065 TX Vref Scan disable
8936 10:02:22.749125 == TX Byte 0 ==
8937 10:02:22.752421 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8938 10:02:22.755066 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8939 10:02:22.758544 == TX Byte 1 ==
8940 10:02:22.761934 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8941 10:02:22.765266 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8942 10:02:22.768322 ==
8943 10:02:22.771984 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 10:02:22.775248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 10:02:22.775352 ==
8946 10:02:22.787421
8947 10:02:22.790555 TX Vref early break, caculate TX vref
8948 10:02:22.794121 TX Vref=16, minBit 0, minWin=22, winSum=377
8949 10:02:22.797524 TX Vref=18, minBit 1, minWin=23, winSum=389
8950 10:02:22.800422 TX Vref=20, minBit 1, minWin=23, winSum=397
8951 10:02:22.803920 TX Vref=22, minBit 1, minWin=23, winSum=404
8952 10:02:22.807168 TX Vref=24, minBit 5, minWin=24, winSum=413
8953 10:02:22.814194 TX Vref=26, minBit 0, minWin=25, winSum=417
8954 10:02:22.817129 TX Vref=28, minBit 0, minWin=25, winSum=416
8955 10:02:22.820532 TX Vref=30, minBit 0, minWin=24, winSum=408
8956 10:02:22.824264 TX Vref=32, minBit 0, minWin=23, winSum=402
8957 10:02:22.827277 TX Vref=34, minBit 0, minWin=22, winSum=390
8958 10:02:22.833410 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 26
8959 10:02:22.833518
8960 10:02:22.837033 Final TX Range 0 Vref 26
8961 10:02:22.837139
8962 10:02:22.837235 ==
8963 10:02:22.840453 Dram Type= 6, Freq= 0, CH_1, rank 1
8964 10:02:22.843581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8965 10:02:22.843686 ==
8966 10:02:22.843780
8967 10:02:22.843869
8968 10:02:22.847323 TX Vref Scan disable
8969 10:02:22.853300 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8970 10:02:22.853403 == TX Byte 0 ==
8971 10:02:22.857212 u2DelayCellOfst[0]=15 cells (4 PI)
8972 10:02:22.860432 u2DelayCellOfst[1]=11 cells (3 PI)
8973 10:02:22.863404 u2DelayCellOfst[2]=0 cells (0 PI)
8974 10:02:22.866626 u2DelayCellOfst[3]=7 cells (2 PI)
8975 10:02:22.869946 u2DelayCellOfst[4]=7 cells (2 PI)
8976 10:02:22.873476 u2DelayCellOfst[5]=18 cells (5 PI)
8977 10:02:22.877238 u2DelayCellOfst[6]=18 cells (5 PI)
8978 10:02:22.879656 u2DelayCellOfst[7]=3 cells (1 PI)
8979 10:02:22.882999 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8980 10:02:22.886170 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8981 10:02:22.889579 == TX Byte 1 ==
8982 10:02:22.892930 u2DelayCellOfst[8]=0 cells (0 PI)
8983 10:02:22.895871 u2DelayCellOfst[9]=7 cells (2 PI)
8984 10:02:22.895973 u2DelayCellOfst[10]=15 cells (4 PI)
8985 10:02:22.900048 u2DelayCellOfst[11]=7 cells (2 PI)
8986 10:02:22.902727 u2DelayCellOfst[12]=15 cells (4 PI)
8987 10:02:22.906390 u2DelayCellOfst[13]=15 cells (4 PI)
8988 10:02:22.909379 u2DelayCellOfst[14]=18 cells (5 PI)
8989 10:02:22.912689 u2DelayCellOfst[15]=18 cells (5 PI)
8990 10:02:22.919288 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8991 10:02:22.922526 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8992 10:02:22.922630 DramC Write-DBI on
8993 10:02:22.925789 ==
8994 10:02:22.925888 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 10:02:22.932027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 10:02:22.932134 ==
8997 10:02:22.932228
8998 10:02:22.932318
8999 10:02:22.935379 TX Vref Scan disable
9000 10:02:22.935481 == TX Byte 0 ==
9001 10:02:22.941907 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9002 10:02:22.942008 == TX Byte 1 ==
9003 10:02:22.945171 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9004 10:02:22.948389 DramC Write-DBI off
9005 10:02:22.948491
9006 10:02:22.948606 [DATLAT]
9007 10:02:22.952128 Freq=1600, CH1 RK1
9008 10:02:22.952227
9009 10:02:22.952322 DATLAT Default: 0xf
9010 10:02:22.955116 0, 0xFFFF, sum = 0
9011 10:02:22.955216 1, 0xFFFF, sum = 0
9012 10:02:22.958675 2, 0xFFFF, sum = 0
9013 10:02:22.958775 3, 0xFFFF, sum = 0
9014 10:02:22.962040 4, 0xFFFF, sum = 0
9015 10:02:22.964971 5, 0xFFFF, sum = 0
9016 10:02:22.965072 6, 0xFFFF, sum = 0
9017 10:02:22.968493 7, 0xFFFF, sum = 0
9018 10:02:22.968598 8, 0xFFFF, sum = 0
9019 10:02:22.971619 9, 0xFFFF, sum = 0
9020 10:02:22.971731 10, 0xFFFF, sum = 0
9021 10:02:22.974820 11, 0xFFFF, sum = 0
9022 10:02:22.974916 12, 0xFFFF, sum = 0
9023 10:02:22.978053 13, 0xFFFF, sum = 0
9024 10:02:22.978125 14, 0x0, sum = 1
9025 10:02:22.981559 15, 0x0, sum = 2
9026 10:02:22.981656 16, 0x0, sum = 3
9027 10:02:22.984934 17, 0x0, sum = 4
9028 10:02:22.985043 best_step = 15
9029 10:02:22.985138
9030 10:02:22.985230 ==
9031 10:02:22.987712 Dram Type= 6, Freq= 0, CH_1, rank 1
9032 10:02:22.994622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9033 10:02:22.994729 ==
9034 10:02:22.994823 RX Vref Scan: 0
9035 10:02:22.994912
9036 10:02:22.997612 RX Vref 0 -> 0, step: 1
9037 10:02:22.997713
9038 10:02:23.000931 RX Delay 11 -> 252, step: 4
9039 10:02:23.004329 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9040 10:02:23.007531 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9041 10:02:23.011175 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9042 10:02:23.018171 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9043 10:02:23.021133 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9044 10:02:23.024127 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9045 10:02:23.027480 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9046 10:02:23.031146 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9047 10:02:23.037504 iDelay=203, Bit 8, Center 114 (59 ~ 170) 112
9048 10:02:23.040605 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9049 10:02:23.044242 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9050 10:02:23.047165 iDelay=203, Bit 11, Center 120 (67 ~ 174) 108
9051 10:02:23.053971 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9052 10:02:23.057387 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9053 10:02:23.060099 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9054 10:02:23.063887 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9055 10:02:23.063989 ==
9056 10:02:23.067154 Dram Type= 6, Freq= 0, CH_1, rank 1
9057 10:02:23.073277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9058 10:02:23.073357 ==
9059 10:02:23.073422 DQS Delay:
9060 10:02:23.076911 DQS0 = 0, DQS1 = 0
9061 10:02:23.077008 DQM Delay:
9062 10:02:23.077098 DQM0 = 134, DQM1 = 127
9063 10:02:23.080229 DQ Delay:
9064 10:02:23.083965 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9065 10:02:23.086557 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9066 10:02:23.090173 DQ8 =114, DQ9 =114, DQ10 =126, DQ11 =120
9067 10:02:23.093599 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9068 10:02:23.093674
9069 10:02:23.093751
9070 10:02:23.093852
9071 10:02:23.096671 [DramC_TX_OE_Calibration] TA2
9072 10:02:23.100462 Original DQ_B0 (3 6) =30, OEN = 27
9073 10:02:23.103711 Original DQ_B1 (3 6) =30, OEN = 27
9074 10:02:23.106458 24, 0x0, End_B0=24 End_B1=24
9075 10:02:23.109727 25, 0x0, End_B0=25 End_B1=25
9076 10:02:23.109805 26, 0x0, End_B0=26 End_B1=26
9077 10:02:23.113521 27, 0x0, End_B0=27 End_B1=27
9078 10:02:23.116236 28, 0x0, End_B0=28 End_B1=28
9079 10:02:23.119822 29, 0x0, End_B0=29 End_B1=29
9080 10:02:23.119922 30, 0x0, End_B0=30 End_B1=30
9081 10:02:23.123360 31, 0x4141, End_B0=30 End_B1=30
9082 10:02:23.126998 Byte0 end_step=30 best_step=27
9083 10:02:23.129772 Byte1 end_step=30 best_step=27
9084 10:02:23.133010 Byte0 TX OE(2T, 0.5T) = (3, 3)
9085 10:02:23.136637 Byte1 TX OE(2T, 0.5T) = (3, 3)
9086 10:02:23.136734
9087 10:02:23.136826
9088 10:02:23.142875 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9089 10:02:23.146503 CH1 RK1: MR19=303, MR18=E0A
9090 10:02:23.152884 CH1_RK1: MR19=0x303, MR18=0xE0A, DQSOSC=402, MR23=63, INC=22, DEC=15
9091 10:02:23.156102 [RxdqsGatingPostProcess] freq 1600
9092 10:02:23.159532 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9093 10:02:23.162951 best DQS0 dly(2T, 0.5T) = (1, 1)
9094 10:02:23.166049 best DQS1 dly(2T, 0.5T) = (1, 1)
9095 10:02:23.169113 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9096 10:02:23.172493 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9097 10:02:23.176454 best DQS0 dly(2T, 0.5T) = (1, 1)
9098 10:02:23.179235 best DQS1 dly(2T, 0.5T) = (1, 1)
9099 10:02:23.182841 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9100 10:02:23.185881 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9101 10:02:23.189026 Pre-setting of DQS Precalculation
9102 10:02:23.192245 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9103 10:02:23.199456 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9104 10:02:23.209033 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9105 10:02:23.209143
9106 10:02:23.209209
9107 10:02:23.212531 [Calibration Summary] 3200 Mbps
9108 10:02:23.212675 CH 0, Rank 0
9109 10:02:23.215757 SW Impedance : PASS
9110 10:02:23.215854 DUTY Scan : NO K
9111 10:02:23.218744 ZQ Calibration : PASS
9112 10:02:23.222087 Jitter Meter : NO K
9113 10:02:23.222189 CBT Training : PASS
9114 10:02:23.225676 Write leveling : PASS
9115 10:02:23.228644 RX DQS gating : PASS
9116 10:02:23.228746 RX DQ/DQS(RDDQC) : PASS
9117 10:02:23.231807 TX DQ/DQS : PASS
9118 10:02:23.235326 RX DATLAT : PASS
9119 10:02:23.235427 RX DQ/DQS(Engine): PASS
9120 10:02:23.238400 TX OE : PASS
9121 10:02:23.238502 All Pass.
9122 10:02:23.238593
9123 10:02:23.241934 CH 0, Rank 1
9124 10:02:23.242013 SW Impedance : PASS
9125 10:02:23.245604 DUTY Scan : NO K
9126 10:02:23.245681 ZQ Calibration : PASS
9127 10:02:23.248449 Jitter Meter : NO K
9128 10:02:23.252404 CBT Training : PASS
9129 10:02:23.252509 Write leveling : PASS
9130 10:02:23.255168 RX DQS gating : PASS
9131 10:02:23.258450 RX DQ/DQS(RDDQC) : PASS
9132 10:02:23.258552 TX DQ/DQS : PASS
9133 10:02:23.261799 RX DATLAT : PASS
9134 10:02:23.265293 RX DQ/DQS(Engine): PASS
9135 10:02:23.265369 TX OE : PASS
9136 10:02:23.268443 All Pass.
9137 10:02:23.268547
9138 10:02:23.268615 CH 1, Rank 0
9139 10:02:23.272007 SW Impedance : PASS
9140 10:02:23.272127 DUTY Scan : NO K
9141 10:02:23.275260 ZQ Calibration : PASS
9142 10:02:23.278596 Jitter Meter : NO K
9143 10:02:23.278674 CBT Training : PASS
9144 10:02:23.281741 Write leveling : PASS
9145 10:02:23.285117 RX DQS gating : PASS
9146 10:02:23.285202 RX DQ/DQS(RDDQC) : PASS
9147 10:02:23.288457 TX DQ/DQS : PASS
9148 10:02:23.292419 RX DATLAT : PASS
9149 10:02:23.292548 RX DQ/DQS(Engine): PASS
9150 10:02:23.294951 TX OE : PASS
9151 10:02:23.295053 All Pass.
9152 10:02:23.295145
9153 10:02:23.298268 CH 1, Rank 1
9154 10:02:23.298373 SW Impedance : PASS
9155 10:02:23.301538 DUTY Scan : NO K
9156 10:02:23.301640 ZQ Calibration : PASS
9157 10:02:23.305111 Jitter Meter : NO K
9158 10:02:23.307966 CBT Training : PASS
9159 10:02:23.308068 Write leveling : PASS
9160 10:02:23.311394 RX DQS gating : PASS
9161 10:02:23.314580 RX DQ/DQS(RDDQC) : PASS
9162 10:02:23.314725 TX DQ/DQS : PASS
9163 10:02:23.317695 RX DATLAT : PASS
9164 10:02:23.321215 RX DQ/DQS(Engine): PASS
9165 10:02:23.321319 TX OE : PASS
9166 10:02:23.324387 All Pass.
9167 10:02:23.324489
9168 10:02:23.324619 DramC Write-DBI on
9169 10:02:23.327923 PER_BANK_REFRESH: Hybrid Mode
9170 10:02:23.331389 TX_TRACKING: ON
9171 10:02:23.338085 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9172 10:02:23.347749 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9173 10:02:23.354640 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9174 10:02:23.357498 [FAST_K] Save calibration result to emmc
9175 10:02:23.360655 sync common calibartion params.
9176 10:02:23.360732 sync cbt_mode0:1, 1:1
9177 10:02:23.364600 dram_init: ddr_geometry: 2
9178 10:02:23.367464 dram_init: ddr_geometry: 2
9179 10:02:23.370942 dram_init: ddr_geometry: 2
9180 10:02:23.371045 0:dram_rank_size:100000000
9181 10:02:23.374122 1:dram_rank_size:100000000
9182 10:02:23.381056 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9183 10:02:23.381159 DFS_SHUFFLE_HW_MODE: ON
9184 10:02:23.387294 dramc_set_vcore_voltage set vcore to 725000
9185 10:02:23.387401 Read voltage for 1600, 0
9186 10:02:23.390320 Vio18 = 0
9187 10:02:23.390437 Vcore = 725000
9188 10:02:23.390544 Vdram = 0
9189 10:02:23.393949 Vddq = 0
9190 10:02:23.394048 Vmddr = 0
9191 10:02:23.397128 switch to 3200 Mbps bootup
9192 10:02:23.397215 [DramcRunTimeConfig]
9193 10:02:23.397285 PHYPLL
9194 10:02:23.400218 DPM_CONTROL_AFTERK: ON
9195 10:02:23.404083 PER_BANK_REFRESH: ON
9196 10:02:23.404188 REFRESH_OVERHEAD_REDUCTION: ON
9197 10:02:23.407183 CMD_PICG_NEW_MODE: OFF
9198 10:02:23.410188 XRTWTW_NEW_MODE: ON
9199 10:02:23.410299 XRTRTR_NEW_MODE: ON
9200 10:02:23.413895 TX_TRACKING: ON
9201 10:02:23.413996 RDSEL_TRACKING: OFF
9202 10:02:23.416987 DQS Precalculation for DVFS: ON
9203 10:02:23.417093 RX_TRACKING: OFF
9204 10:02:23.420272 HW_GATING DBG: ON
9205 10:02:23.420372 ZQCS_ENABLE_LP4: ON
9206 10:02:23.423408 RX_PICG_NEW_MODE: ON
9207 10:02:23.426959 TX_PICG_NEW_MODE: ON
9208 10:02:23.427065 ENABLE_RX_DCM_DPHY: ON
9209 10:02:23.430255 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9210 10:02:23.433719 DUMMY_READ_FOR_TRACKING: OFF
9211 10:02:23.436762 !!! SPM_CONTROL_AFTERK: OFF
9212 10:02:23.440234 !!! SPM could not control APHY
9213 10:02:23.440341 IMPEDANCE_TRACKING: ON
9214 10:02:23.443165 TEMP_SENSOR: ON
9215 10:02:23.443274 HW_SAVE_FOR_SR: OFF
9216 10:02:23.446385 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9217 10:02:23.449626 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9218 10:02:23.452954 Read ODT Tracking: ON
9219 10:02:23.456263 Refresh Rate DeBounce: ON
9220 10:02:23.456364 DFS_NO_QUEUE_FLUSH: ON
9221 10:02:23.459472 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9222 10:02:23.463105 ENABLE_DFS_RUNTIME_MRW: OFF
9223 10:02:23.466746 DDR_RESERVE_NEW_MODE: ON
9224 10:02:23.466847 MR_CBT_SWITCH_FREQ: ON
9225 10:02:23.469928 =========================
9226 10:02:23.487786 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9227 10:02:23.491509 dram_init: ddr_geometry: 2
9228 10:02:23.509815 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9229 10:02:23.512917 dram_init: dram init end (result: 0)
9230 10:02:23.519941 DRAM-K: Full calibration passed in 24572 msecs
9231 10:02:23.522498 MRC: failed to locate region type 0.
9232 10:02:23.522609 DRAM rank0 size:0x100000000,
9233 10:02:23.525971 DRAM rank1 size=0x100000000
9234 10:02:23.535720 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9235 10:02:23.542718 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9236 10:02:23.549213 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9237 10:02:23.558961 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9238 10:02:23.559071 DRAM rank0 size:0x100000000,
9239 10:02:23.562713 DRAM rank1 size=0x100000000
9240 10:02:23.562817 CBMEM:
9241 10:02:23.566373 IMD: root @ 0xfffff000 254 entries.
9242 10:02:23.569041 IMD: root @ 0xffffec00 62 entries.
9243 10:02:23.572240 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9244 10:02:23.578890 WARNING: RO_VPD is uninitialized or empty.
9245 10:02:23.582382 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9246 10:02:23.590011 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9247 10:02:23.602806 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9248 10:02:23.613794 BS: romstage times (exec / console): total (unknown) / 24075 ms
9249 10:02:23.613877
9250 10:02:23.613943
9251 10:02:23.623538 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9252 10:02:23.627104 ARM64: Exception handlers installed.
9253 10:02:23.630475 ARM64: Testing exception
9254 10:02:23.633606 ARM64: Done test exception
9255 10:02:23.633683 Enumerating buses...
9256 10:02:23.636787 Show all devs... Before device enumeration.
9257 10:02:23.640580 Root Device: enabled 1
9258 10:02:23.644042 CPU_CLUSTER: 0: enabled 1
9259 10:02:23.644142 CPU: 00: enabled 1
9260 10:02:23.647113 Compare with tree...
9261 10:02:23.647189 Root Device: enabled 1
9262 10:02:23.650545 CPU_CLUSTER: 0: enabled 1
9263 10:02:23.653347 CPU: 00: enabled 1
9264 10:02:23.653444 Root Device scanning...
9265 10:02:23.656735 scan_static_bus for Root Device
9266 10:02:23.659898 CPU_CLUSTER: 0 enabled
9267 10:02:23.663354 scan_static_bus for Root Device done
9268 10:02:23.666705 scan_bus: bus Root Device finished in 8 msecs
9269 10:02:23.666822 done
9270 10:02:23.673584 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9271 10:02:23.676605 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9272 10:02:23.683451 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9273 10:02:23.686344 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9274 10:02:23.689793 Allocating resources...
9275 10:02:23.693397 Reading resources...
9276 10:02:23.696807 Root Device read_resources bus 0 link: 0
9277 10:02:23.699473 DRAM rank0 size:0x100000000,
9278 10:02:23.699573 DRAM rank1 size=0x100000000
9279 10:02:23.703299 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9280 10:02:23.706758 CPU: 00 missing read_resources
9281 10:02:23.712928 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9282 10:02:23.716344 Root Device read_resources bus 0 link: 0 done
9283 10:02:23.716452 Done reading resources.
9284 10:02:23.722597 Show resources in subtree (Root Device)...After reading.
9285 10:02:23.726046 Root Device child on link 0 CPU_CLUSTER: 0
9286 10:02:23.729248 CPU_CLUSTER: 0 child on link 0 CPU: 00
9287 10:02:23.739512 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9288 10:02:23.739597 CPU: 00
9289 10:02:23.742884 Root Device assign_resources, bus 0 link: 0
9290 10:02:23.745818 CPU_CLUSTER: 0 missing set_resources
9291 10:02:23.753154 Root Device assign_resources, bus 0 link: 0 done
9292 10:02:23.753236 Done setting resources.
9293 10:02:23.758931 Show resources in subtree (Root Device)...After assigning values.
9294 10:02:23.762402 Root Device child on link 0 CPU_CLUSTER: 0
9295 10:02:23.766315 CPU_CLUSTER: 0 child on link 0 CPU: 00
9296 10:02:23.775549 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9297 10:02:23.775633 CPU: 00
9298 10:02:23.778976 Done allocating resources.
9299 10:02:23.785675 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9300 10:02:23.785758 Enabling resources...
9301 10:02:23.785824 done.
9302 10:02:23.792344 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9303 10:02:23.795943 Initializing devices...
9304 10:02:23.796025 Root Device init
9305 10:02:23.799188 init hardware done!
9306 10:02:23.799270 0x00000018: ctrlr->caps
9307 10:02:23.802180 52.000 MHz: ctrlr->f_max
9308 10:02:23.805756 0.400 MHz: ctrlr->f_min
9309 10:02:23.805841 0x40ff8080: ctrlr->voltages
9310 10:02:23.808830 sclk: 390625
9311 10:02:23.808927 Bus Width = 1
9312 10:02:23.809025 sclk: 390625
9313 10:02:23.811816 Bus Width = 1
9314 10:02:23.815384 Early init status = 3
9315 10:02:23.818480 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9316 10:02:23.821930 in-header: 03 fc 00 00 01 00 00 00
9317 10:02:23.825297 in-data: 00
9318 10:02:23.828363 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9319 10:02:23.832866 in-header: 03 fd 00 00 00 00 00 00
9320 10:02:23.836087 in-data:
9321 10:02:23.839539 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9322 10:02:23.843284 in-header: 03 fc 00 00 01 00 00 00
9323 10:02:23.845863 in-data: 00
9324 10:02:23.849333 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9325 10:02:23.854225 in-header: 03 fd 00 00 00 00 00 00
9326 10:02:23.857372 in-data:
9327 10:02:23.860980 [SSUSB] Setting up USB HOST controller...
9328 10:02:23.864074 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9329 10:02:23.866917 [SSUSB] phy power-on done.
9330 10:02:23.870395 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9331 10:02:23.876720 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9332 10:02:23.880525 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9333 10:02:23.886521 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9334 10:02:23.893578 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9335 10:02:23.899837 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9336 10:02:23.906279 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9337 10:02:23.913226 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9338 10:02:23.916233 SPM: binary array size = 0x9dc
9339 10:02:23.922455 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9340 10:02:23.926264 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9341 10:02:23.935981 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9342 10:02:23.939115 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9343 10:02:23.942767 configure_display: Starting display init
9344 10:02:23.977135 anx7625_power_on_init: Init interface.
9345 10:02:23.980672 anx7625_disable_pd_protocol: Disabled PD feature.
9346 10:02:23.983749 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9347 10:02:24.011650 anx7625_start_dp_work: Secure OCM version=00
9348 10:02:24.014921 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9349 10:02:24.029544 sp_tx_get_edid_block: EDID Block = 1
9350 10:02:24.132350 Extracted contents:
9351 10:02:24.135412 header: 00 ff ff ff ff ff ff 00
9352 10:02:24.138731 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9353 10:02:24.141881 version: 01 04
9354 10:02:24.145644 basic params: 95 1f 11 78 0a
9355 10:02:24.148603 chroma info: 76 90 94 55 54 90 27 21 50 54
9356 10:02:24.152099 established: 00 00 00
9357 10:02:24.159058 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9358 10:02:24.165054 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9359 10:02:24.168223 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9360 10:02:24.175262 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9361 10:02:24.181974 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9362 10:02:24.185014 extensions: 00
9363 10:02:24.185096 checksum: fb
9364 10:02:24.185166
9365 10:02:24.191396 Manufacturer: IVO Model 57d Serial Number 0
9366 10:02:24.191481 Made week 0 of 2020
9367 10:02:24.194659 EDID version: 1.4
9368 10:02:24.194736 Digital display
9369 10:02:24.198023 6 bits per primary color channel
9370 10:02:24.198098 DisplayPort interface
9371 10:02:24.201521 Maximum image size: 31 cm x 17 cm
9372 10:02:24.205309 Gamma: 220%
9373 10:02:24.205403 Check DPMS levels
9374 10:02:24.208267 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9375 10:02:24.214525 First detailed timing is preferred timing
9376 10:02:24.214605 Established timings supported:
9377 10:02:24.218029 Standard timings supported:
9378 10:02:24.221163 Detailed timings
9379 10:02:24.224875 Hex of detail: 383680a07038204018303c0035ae10000019
9380 10:02:24.231634 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9381 10:02:24.234667 0780 0798 07c8 0820 hborder 0
9382 10:02:24.237735 0438 043b 0447 0458 vborder 0
9383 10:02:24.240932 -hsync -vsync
9384 10:02:24.241008 Did detailed timing
9385 10:02:24.247812 Hex of detail: 000000000000000000000000000000000000
9386 10:02:24.251273 Manufacturer-specified data, tag 0
9387 10:02:24.254630 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9388 10:02:24.257803 ASCII string: InfoVision
9389 10:02:24.260927 Hex of detail: 000000fe00523134304e574635205248200a
9390 10:02:24.264063 ASCII string: R140NWF5 RH
9391 10:02:24.264154 Checksum
9392 10:02:24.267682 Checksum: 0xfb (valid)
9393 10:02:24.271236 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9394 10:02:24.274147 DSI data_rate: 832800000 bps
9395 10:02:24.280897 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9396 10:02:24.284060 anx7625_parse_edid: pixelclock(138800).
9397 10:02:24.287111 hactive(1920), hsync(48), hfp(24), hbp(88)
9398 10:02:24.290634 vactive(1080), vsync(12), vfp(3), vbp(17)
9399 10:02:24.294164 anx7625_dsi_config: config dsi.
9400 10:02:24.300965 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9401 10:02:24.314421 anx7625_dsi_config: success to config DSI
9402 10:02:24.317379 anx7625_dp_start: MIPI phy setup OK.
9403 10:02:24.320750 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9404 10:02:24.324407 mtk_ddp_mode_set invalid vrefresh 60
9405 10:02:24.327427 main_disp_path_setup
9406 10:02:24.327512 ovl_layer_smi_id_en
9407 10:02:24.330752 ovl_layer_smi_id_en
9408 10:02:24.330836 ccorr_config
9409 10:02:24.330903 aal_config
9410 10:02:24.334254 gamma_config
9411 10:02:24.334339 postmask_config
9412 10:02:24.337537 dither_config
9413 10:02:24.341015 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9414 10:02:24.347349 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9415 10:02:24.350810 Root Device init finished in 551 msecs
9416 10:02:24.354199 CPU_CLUSTER: 0 init
9417 10:02:24.360696 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9418 10:02:24.367255 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9419 10:02:24.367342 APU_MBOX 0x190000b0 = 0x10001
9420 10:02:24.370478 APU_MBOX 0x190001b0 = 0x10001
9421 10:02:24.373422 APU_MBOX 0x190005b0 = 0x10001
9422 10:02:24.377058 APU_MBOX 0x190006b0 = 0x10001
9423 10:02:24.383449 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9424 10:02:24.393326 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9425 10:02:24.405692 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9426 10:02:24.411994 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9427 10:02:24.424101 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9428 10:02:24.433052 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9429 10:02:24.436372 CPU_CLUSTER: 0 init finished in 81 msecs
9430 10:02:24.439784 Devices initialized
9431 10:02:24.443081 Show all devs... After init.
9432 10:02:24.443164 Root Device: enabled 1
9433 10:02:24.445976 CPU_CLUSTER: 0: enabled 1
9434 10:02:24.450017 CPU: 00: enabled 1
9435 10:02:24.452776 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9436 10:02:24.456002 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9437 10:02:24.459443 ELOG: NV offset 0x57f000 size 0x1000
9438 10:02:24.466117 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9439 10:02:24.472643 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9440 10:02:24.475994 ELOG: Event(17) added with size 13 at 2023-06-10 10:02:26 UTC
9441 10:02:24.482666 out: cmd=0x121: 03 db 21 01 00 00 00 00
9442 10:02:24.485717 in-header: 03 f5 00 00 2c 00 00 00
9443 10:02:24.495995 in-data: 6a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9444 10:02:24.502387 ELOG: Event(A1) added with size 10 at 2023-06-10 10:02:27 UTC
9445 10:02:24.509043 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9446 10:02:24.515671 ELOG: Event(A0) added with size 9 at 2023-06-10 10:02:27 UTC
9447 10:02:24.518817 elog_add_boot_reason: Logged dev mode boot
9448 10:02:24.525209 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9449 10:02:24.525284 Finalize devices...
9450 10:02:24.528607 Devices finalized
9451 10:02:24.531869 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9452 10:02:24.535337 Writing coreboot table at 0xffe64000
9453 10:02:24.538858 0. 000000000010a000-0000000000113fff: RAMSTAGE
9454 10:02:24.545422 1. 0000000040000000-00000000400fffff: RAM
9455 10:02:24.548501 2. 0000000040100000-000000004032afff: RAMSTAGE
9456 10:02:24.551956 3. 000000004032b000-00000000545fffff: RAM
9457 10:02:24.555547 4. 0000000054600000-000000005465ffff: BL31
9458 10:02:24.558513 5. 0000000054660000-00000000ffe63fff: RAM
9459 10:02:24.565450 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9460 10:02:24.568394 7. 0000000100000000-000000023fffffff: RAM
9461 10:02:24.571704 Passing 5 GPIOs to payload:
9462 10:02:24.575139 NAME | PORT | POLARITY | VALUE
9463 10:02:24.581430 EC in RW | 0x000000aa | low | undefined
9464 10:02:24.584996 EC interrupt | 0x00000005 | low | undefined
9465 10:02:24.588408 TPM interrupt | 0x000000ab | high | undefined
9466 10:02:24.595106 SD card detect | 0x00000011 | high | undefined
9467 10:02:24.598707 speaker enable | 0x00000093 | high | undefined
9468 10:02:24.601582 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9469 10:02:24.605072 in-header: 03 f9 00 00 02 00 00 00
9470 10:02:24.608055 in-data: 02 00
9471 10:02:24.611670 ADC[4]: Raw value=901922 ID=7
9472 10:02:24.611772 ADC[3]: Raw value=213282 ID=1
9473 10:02:24.615021 RAM Code: 0x71
9474 10:02:24.618220 ADC[6]: Raw value=75036 ID=0
9475 10:02:24.618317 ADC[5]: Raw value=212912 ID=1
9476 10:02:24.621196 SKU Code: 0x1
9477 10:02:24.627920 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a169
9478 10:02:24.628023 coreboot table: 964 bytes.
9479 10:02:24.631382 IMD ROOT 0. 0xfffff000 0x00001000
9480 10:02:24.634821 IMD SMALL 1. 0xffffe000 0x00001000
9481 10:02:24.638412 RO MCACHE 2. 0xffffc000 0x00001104
9482 10:02:24.641136 CONSOLE 3. 0xfff7c000 0x00080000
9483 10:02:24.644699 FMAP 4. 0xfff7b000 0x00000452
9484 10:02:24.648228 TIME STAMP 5. 0xfff7a000 0x00000910
9485 10:02:24.651104 VBOOT WORK 6. 0xfff66000 0x00014000
9486 10:02:24.655038 RAMOOPS 7. 0xffe66000 0x00100000
9487 10:02:24.657847 COREBOOT 8. 0xffe64000 0x00002000
9488 10:02:24.661300 IMD small region:
9489 10:02:24.664775 IMD ROOT 0. 0xffffec00 0x00000400
9490 10:02:24.667980 VPD 1. 0xffffeba0 0x0000004c
9491 10:02:24.670977 MMC STATUS 2. 0xffffeb80 0x00000004
9492 10:02:24.674357 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9493 10:02:24.677465 Probing TPM: done!
9494 10:02:24.681071 Connected to device vid:did:rid of 1ae0:0028:00
9495 10:02:24.691715 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9496 10:02:24.695327 Initialized TPM device CR50 revision 0
9497 10:02:24.698981 Checking cr50 for pending updates
9498 10:02:24.702910 Reading cr50 TPM mode
9499 10:02:24.711636 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9500 10:02:24.718175 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9501 10:02:24.758323 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9502 10:02:24.761045 Checking segment from ROM address 0x40100000
9503 10:02:24.764445 Checking segment from ROM address 0x4010001c
9504 10:02:24.771633 Loading segment from ROM address 0x40100000
9505 10:02:24.771712 code (compression=0)
9506 10:02:24.781444 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9507 10:02:24.788168 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9508 10:02:24.788276 it's not compressed!
9509 10:02:24.794565 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9510 10:02:24.801305 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9511 10:02:24.818165 Loading segment from ROM address 0x4010001c
9512 10:02:24.818242 Entry Point 0x80000000
9513 10:02:24.821581 Loaded segments
9514 10:02:24.825378 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9515 10:02:24.831525 Jumping to boot code at 0x80000000(0xffe64000)
9516 10:02:24.838195 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9517 10:02:24.844580 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9518 10:02:24.852912 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9519 10:02:24.856175 Checking segment from ROM address 0x40100000
9520 10:02:24.859294 Checking segment from ROM address 0x4010001c
9521 10:02:24.866156 Loading segment from ROM address 0x40100000
9522 10:02:24.866263 code (compression=1)
9523 10:02:24.872531 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9524 10:02:24.882535 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9525 10:02:24.882644 using LZMA
9526 10:02:24.891491 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9527 10:02:24.897603 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9528 10:02:24.901339 Loading segment from ROM address 0x4010001c
9529 10:02:24.901444 Entry Point 0x54601000
9530 10:02:24.904404 Loaded segments
9531 10:02:24.907893 NOTICE: MT8192 bl31_setup
9532 10:02:24.914660 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9533 10:02:24.918206 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9534 10:02:24.921689 WARNING: region 0:
9535 10:02:24.924642 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9536 10:02:24.924722 WARNING: region 1:
9537 10:02:24.931719 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9538 10:02:24.934597 WARNING: region 2:
9539 10:02:24.938102 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9540 10:02:24.941533 WARNING: region 3:
9541 10:02:24.944887 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9542 10:02:24.948258 WARNING: region 4:
9543 10:02:24.954587 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9544 10:02:24.954693 WARNING: region 5:
9545 10:02:24.957682 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 10:02:24.961260 WARNING: region 6:
9547 10:02:24.964934 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9548 10:02:24.968078 WARNING: region 7:
9549 10:02:24.971217 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9550 10:02:24.977688 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9551 10:02:24.981247 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9552 10:02:24.984648 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9553 10:02:24.991172 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9554 10:02:24.994496 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9555 10:02:24.997768 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9556 10:02:25.004420 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9557 10:02:25.007549 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9558 10:02:25.014404 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9559 10:02:25.017634 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9560 10:02:25.020753 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9561 10:02:25.027353 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9562 10:02:25.030612 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9563 10:02:25.037640 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9564 10:02:25.040510 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9565 10:02:25.044080 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9566 10:02:25.050941 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9567 10:02:25.054045 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9568 10:02:25.057239 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9569 10:02:25.063672 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9570 10:02:25.067008 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9571 10:02:25.073949 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9572 10:02:25.077150 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9573 10:02:25.081079 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9574 10:02:25.087155 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9575 10:02:25.090403 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9576 10:02:25.097049 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9577 10:02:25.100432 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9578 10:02:25.108051 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9579 10:02:25.110115 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9580 10:02:25.113519 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9581 10:02:25.120337 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9582 10:02:25.123867 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9583 10:02:25.126980 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9584 10:02:25.130248 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9585 10:02:25.136909 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9586 10:02:25.140229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9587 10:02:25.143278 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9588 10:02:25.147110 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9589 10:02:25.153487 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9590 10:02:25.156687 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9591 10:02:25.159687 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9592 10:02:25.163024 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9593 10:02:25.169877 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9594 10:02:25.173505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9595 10:02:25.176300 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9596 10:02:25.183060 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9597 10:02:25.186391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9598 10:02:25.189944 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9599 10:02:25.196259 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9600 10:02:25.199910 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9601 10:02:25.203239 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9602 10:02:25.210095 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9603 10:02:25.213099 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9604 10:02:25.220006 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9605 10:02:25.222891 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9606 10:02:25.229471 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9607 10:02:25.232821 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9608 10:02:25.239711 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9609 10:02:25.242962 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9610 10:02:25.246210 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9611 10:02:25.252905 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9612 10:02:25.256092 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9613 10:02:25.262596 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9614 10:02:25.266023 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9615 10:02:25.272638 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9616 10:02:25.275941 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9617 10:02:25.283018 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9618 10:02:25.286022 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9619 10:02:25.289321 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9620 10:02:25.296423 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9621 10:02:25.299163 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9622 10:02:25.306137 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9623 10:02:25.309910 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9624 10:02:25.316186 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9625 10:02:25.319029 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9626 10:02:25.322223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9627 10:02:25.329244 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9628 10:02:25.332766 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9629 10:02:25.339023 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9630 10:02:25.342750 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9631 10:02:25.349036 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9632 10:02:25.352583 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9633 10:02:25.359103 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9634 10:02:25.362274 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9635 10:02:25.365723 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9636 10:02:25.372269 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9637 10:02:25.375605 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9638 10:02:25.382344 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9639 10:02:25.385433 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9640 10:02:25.392007 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9641 10:02:25.395652 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9642 10:02:25.398508 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9643 10:02:25.405647 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9644 10:02:25.408688 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9645 10:02:25.415402 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9646 10:02:25.419167 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9647 10:02:25.421943 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9648 10:02:25.429077 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9649 10:02:25.432244 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9650 10:02:25.435101 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9651 10:02:25.438684 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9652 10:02:25.445348 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9653 10:02:25.448769 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9654 10:02:25.454952 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9655 10:02:25.458666 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9656 10:02:25.464943 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9657 10:02:25.468312 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9658 10:02:25.471536 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9659 10:02:25.478313 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9660 10:02:25.481683 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9661 10:02:25.488192 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9662 10:02:25.492116 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9663 10:02:25.495095 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9664 10:02:25.501543 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9665 10:02:25.504660 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9666 10:02:25.508242 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9667 10:02:25.515314 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9668 10:02:25.518516 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9669 10:02:25.521363 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9670 10:02:25.528056 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9671 10:02:25.531540 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9672 10:02:25.534620 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9673 10:02:25.538496 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9674 10:02:25.545028 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9675 10:02:25.547872 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9676 10:02:25.554822 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9677 10:02:25.558216 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9678 10:02:25.561625 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9679 10:02:25.567784 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9680 10:02:25.571117 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9681 10:02:25.574310 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9682 10:02:25.580748 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9683 10:02:25.584686 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9684 10:02:25.590668 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9685 10:02:25.594188 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9686 10:02:25.601009 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9687 10:02:25.604368 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9688 10:02:25.608075 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9689 10:02:25.614223 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9690 10:02:25.617334 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9691 10:02:25.620873 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9692 10:02:25.627449 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9693 10:02:25.630493 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9694 10:02:25.637126 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9695 10:02:25.640542 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9696 10:02:25.643823 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9697 10:02:25.650372 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9698 10:02:25.653651 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9699 10:02:25.659971 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9700 10:02:25.663821 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9701 10:02:25.666654 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9702 10:02:25.673308 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9703 10:02:25.676811 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9704 10:02:25.683229 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9705 10:02:25.687246 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9706 10:02:25.690113 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9707 10:02:25.696588 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9708 10:02:25.699941 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9709 10:02:25.706668 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9710 10:02:25.710295 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9711 10:02:25.713211 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9712 10:02:25.719912 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9713 10:02:25.723324 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9714 10:02:25.729659 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9715 10:02:25.733247 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9716 10:02:25.736656 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9717 10:02:25.743036 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9718 10:02:25.746286 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9719 10:02:25.752953 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9720 10:02:25.755935 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9721 10:02:25.759993 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9722 10:02:25.766352 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9723 10:02:25.769696 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9724 10:02:25.775908 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9725 10:02:25.779072 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9726 10:02:25.782443 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9727 10:02:25.788880 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9728 10:02:25.792173 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9729 10:02:25.799353 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9730 10:02:25.802325 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9731 10:02:25.805767 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9732 10:02:25.812408 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9733 10:02:25.815265 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9734 10:02:25.822469 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9735 10:02:25.825600 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9736 10:02:25.828784 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9737 10:02:25.835589 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9738 10:02:25.838381 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9739 10:02:25.844903 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9740 10:02:25.848372 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9741 10:02:25.855125 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9742 10:02:25.858281 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9743 10:02:25.861521 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9744 10:02:25.867803 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9745 10:02:25.871243 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9746 10:02:25.877864 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9747 10:02:25.881010 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9748 10:02:25.887618 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9749 10:02:25.891432 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9750 10:02:25.894522 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9751 10:02:25.901146 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9752 10:02:25.904415 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9753 10:02:25.911015 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9754 10:02:25.914630 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9755 10:02:25.921541 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9756 10:02:25.924135 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9757 10:02:25.927369 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9758 10:02:25.934233 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9759 10:02:25.937663 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9760 10:02:25.943988 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9761 10:02:25.947248 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9762 10:02:25.950514 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9763 10:02:25.957101 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9764 10:02:25.960291 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9765 10:02:25.966935 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9766 10:02:25.970308 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9767 10:02:25.976798 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9768 10:02:25.980410 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9769 10:02:25.983551 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9770 10:02:25.990108 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9771 10:02:25.993901 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9772 10:02:26.000098 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9773 10:02:26.003367 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9774 10:02:26.010279 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9775 10:02:26.013582 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9776 10:02:26.017055 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9777 10:02:26.023414 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9778 10:02:26.026897 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9779 10:02:26.030337 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9780 10:02:26.037235 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9781 10:02:26.040211 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9782 10:02:26.044047 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9783 10:02:26.046651 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9784 10:02:26.053034 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9785 10:02:26.056582 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9786 10:02:26.060302 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9787 10:02:26.066497 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9788 10:02:26.070094 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9789 10:02:26.073278 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9790 10:02:26.079631 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9791 10:02:26.082917 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9792 10:02:26.089650 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9793 10:02:26.092911 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9794 10:02:26.096306 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9795 10:02:26.103157 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9796 10:02:26.106371 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9797 10:02:26.112736 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9798 10:02:26.116376 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9799 10:02:26.119524 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9800 10:02:26.126006 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9801 10:02:26.129501 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9802 10:02:26.132955 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9803 10:02:26.139278 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9804 10:02:26.142798 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9805 10:02:26.146842 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9806 10:02:26.153056 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9807 10:02:26.156405 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9808 10:02:26.159312 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9809 10:02:26.166253 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9810 10:02:26.169176 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9811 10:02:26.175708 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9812 10:02:26.178693 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9813 10:02:26.182338 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9814 10:02:26.188983 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9815 10:02:26.192010 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9816 10:02:26.198707 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9817 10:02:26.202112 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9818 10:02:26.205191 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9819 10:02:26.208322 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9820 10:02:26.215074 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9821 10:02:26.218244 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9822 10:02:26.222051 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9823 10:02:26.224957 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9824 10:02:26.231397 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9825 10:02:26.234906 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9826 10:02:26.238375 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9827 10:02:26.241785 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9828 10:02:26.248216 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9829 10:02:26.251796 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9830 10:02:26.254871 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9831 10:02:26.262109 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9832 10:02:26.265083 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9833 10:02:26.268214 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9834 10:02:26.274772 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9835 10:02:26.278137 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9836 10:02:26.284664 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9837 10:02:26.288070 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9838 10:02:26.294450 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9839 10:02:26.298221 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9840 10:02:26.301501 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9841 10:02:26.307778 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9842 10:02:26.311032 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9843 10:02:26.318149 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9844 10:02:26.321034 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9845 10:02:26.324657 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9846 10:02:26.330867 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9847 10:02:26.334591 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9848 10:02:26.340543 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9849 10:02:26.344458 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9850 10:02:26.347679 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9851 10:02:26.353989 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9852 10:02:26.357376 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9853 10:02:26.364018 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9854 10:02:26.367295 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9855 10:02:26.373477 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9856 10:02:26.376968 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9857 10:02:26.380443 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9858 10:02:26.386668 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9859 10:02:26.390537 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9860 10:02:26.396780 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9861 10:02:26.400017 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9862 10:02:26.406673 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9863 10:02:26.409745 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9864 10:02:26.413115 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9865 10:02:26.419718 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9866 10:02:26.423408 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9867 10:02:26.430006 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9868 10:02:26.433038 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9869 10:02:26.436849 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9870 10:02:26.443117 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9871 10:02:26.446509 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9872 10:02:26.452908 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9873 10:02:26.456342 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9874 10:02:26.459564 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9875 10:02:26.466081 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9876 10:02:26.469824 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9877 10:02:26.476582 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9878 10:02:26.479847 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9879 10:02:26.483184 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9880 10:02:26.489403 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9881 10:02:26.492873 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9882 10:02:26.499478 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9883 10:02:26.502804 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9884 10:02:26.509329 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9885 10:02:26.512347 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9886 10:02:26.515700 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9887 10:02:26.522354 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9888 10:02:26.526011 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9889 10:02:26.532290 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9890 10:02:26.535624 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9891 10:02:26.538888 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9892 10:02:26.545700 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9893 10:02:26.548701 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9894 10:02:26.555500 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9895 10:02:26.558820 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9896 10:02:26.565371 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9897 10:02:26.569170 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9898 10:02:26.571861 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9899 10:02:26.578957 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9900 10:02:26.581813 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9901 10:02:26.588617 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9902 10:02:26.591827 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9903 10:02:26.595207 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9904 10:02:26.601728 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9905 10:02:26.604891 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9906 10:02:26.611430 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9907 10:02:26.615013 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9908 10:02:26.621490 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9909 10:02:26.625553 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9910 10:02:26.631465 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9911 10:02:26.634530 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9912 10:02:26.637684 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9913 10:02:26.644589 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9914 10:02:26.647589 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9915 10:02:26.654636 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9916 10:02:26.657767 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9917 10:02:26.664341 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9918 10:02:26.667976 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9919 10:02:26.674285 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9920 10:02:26.677450 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9921 10:02:26.683903 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9922 10:02:26.686960 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9923 10:02:26.690308 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9924 10:02:26.697657 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9925 10:02:26.700705 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9926 10:02:26.706866 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9927 10:02:26.710487 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9928 10:02:26.716991 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9929 10:02:26.720631 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9930 10:02:26.726774 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9931 10:02:26.729895 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9932 10:02:26.733292 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9933 10:02:26.740203 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9934 10:02:26.742999 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9935 10:02:26.749677 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9936 10:02:26.753283 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9937 10:02:26.759686 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9938 10:02:26.763254 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9939 10:02:26.769370 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9940 10:02:26.773324 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9941 10:02:26.776732 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9942 10:02:26.782813 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9943 10:02:26.786155 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9944 10:02:26.792823 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9945 10:02:26.796156 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9946 10:02:26.802796 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9947 10:02:26.806242 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9948 10:02:26.813206 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9949 10:02:26.815859 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9950 10:02:26.819421 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9951 10:02:26.826191 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9952 10:02:26.829157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9953 10:02:26.835693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9954 10:02:26.839376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9955 10:02:26.845303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9956 10:02:26.848887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9957 10:02:26.851884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9958 10:02:26.859139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9959 10:02:26.862159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9960 10:02:26.868426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9961 10:02:26.872304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9962 10:02:26.878462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9963 10:02:26.881953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9964 10:02:26.888590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9965 10:02:26.891597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9966 10:02:26.898033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9967 10:02:26.901339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9968 10:02:26.908097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9969 10:02:26.911180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9970 10:02:26.918101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9971 10:02:26.921242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9972 10:02:26.928233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9973 10:02:26.931037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9974 10:02:26.937804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9975 10:02:26.940804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9976 10:02:26.947426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9977 10:02:26.951102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9978 10:02:26.957659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9979 10:02:26.964042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9980 10:02:26.967776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9981 10:02:26.974394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9982 10:02:26.977586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9983 10:02:26.983881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9984 10:02:26.987057 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9985 10:02:26.987140 INFO: [APUAPC] vio 0
9986 10:02:26.994816 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9987 10:02:26.997817 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9988 10:02:27.001633 INFO: [APUAPC] D0_APC_0: 0x400510
9989 10:02:27.004285 INFO: [APUAPC] D0_APC_1: 0x0
9990 10:02:27.007730 INFO: [APUAPC] D0_APC_2: 0x1540
9991 10:02:27.010758 INFO: [APUAPC] D0_APC_3: 0x0
9992 10:02:27.014912 INFO: [APUAPC] D1_APC_0: 0xffffffff
9993 10:02:27.017860 INFO: [APUAPC] D1_APC_1: 0xffffffff
9994 10:02:27.021150 INFO: [APUAPC] D1_APC_2: 0x3fffff
9995 10:02:27.024350 INFO: [APUAPC] D1_APC_3: 0x0
9996 10:02:27.027380 INFO: [APUAPC] D2_APC_0: 0xffffffff
9997 10:02:27.030664 INFO: [APUAPC] D2_APC_1: 0xffffffff
9998 10:02:27.033744 INFO: [APUAPC] D2_APC_2: 0x3fffff
9999 10:02:27.037059 INFO: [APUAPC] D2_APC_3: 0x0
10000 10:02:27.041127 INFO: [APUAPC] D3_APC_0: 0xffffffff
10001 10:02:27.044001 INFO: [APUAPC] D3_APC_1: 0xffffffff
10002 10:02:27.047073 INFO: [APUAPC] D3_APC_2: 0x3fffff
10003 10:02:27.050900 INFO: [APUAPC] D3_APC_3: 0x0
10004 10:02:27.053771 INFO: [APUAPC] D4_APC_0: 0xffffffff
10005 10:02:27.057148 INFO: [APUAPC] D4_APC_1: 0xffffffff
10006 10:02:27.060373 INFO: [APUAPC] D4_APC_2: 0x3fffff
10007 10:02:27.063609 INFO: [APUAPC] D4_APC_3: 0x0
10008 10:02:27.067135 INFO: [APUAPC] D5_APC_0: 0xffffffff
10009 10:02:27.070212 INFO: [APUAPC] D5_APC_1: 0xffffffff
10010 10:02:27.073662 INFO: [APUAPC] D5_APC_2: 0x3fffff
10011 10:02:27.076880 INFO: [APUAPC] D5_APC_3: 0x0
10012 10:02:27.080351 INFO: [APUAPC] D6_APC_0: 0xffffffff
10013 10:02:27.083398 INFO: [APUAPC] D6_APC_1: 0xffffffff
10014 10:02:27.086695 INFO: [APUAPC] D6_APC_2: 0x3fffff
10015 10:02:27.090627 INFO: [APUAPC] D6_APC_3: 0x0
10016 10:02:27.093400 INFO: [APUAPC] D7_APC_0: 0xffffffff
10017 10:02:27.096427 INFO: [APUAPC] D7_APC_1: 0xffffffff
10018 10:02:27.100151 INFO: [APUAPC] D7_APC_2: 0x3fffff
10019 10:02:27.100234 INFO: [APUAPC] D7_APC_3: 0x0
10020 10:02:27.106396 INFO: [APUAPC] D8_APC_0: 0xffffffff
10021 10:02:27.110125 INFO: [APUAPC] D8_APC_1: 0xffffffff
10022 10:02:27.113367 INFO: [APUAPC] D8_APC_2: 0x3fffff
10023 10:02:27.113438 INFO: [APUAPC] D8_APC_3: 0x0
10024 10:02:27.116568 INFO: [APUAPC] D9_APC_0: 0xffffffff
10025 10:02:27.123131 INFO: [APUAPC] D9_APC_1: 0xffffffff
10026 10:02:27.126321 INFO: [APUAPC] D9_APC_2: 0x3fffff
10027 10:02:27.126407 INFO: [APUAPC] D9_APC_3: 0x0
10028 10:02:27.129512 INFO: [APUAPC] D10_APC_0: 0xffffffff
10029 10:02:27.132796 INFO: [APUAPC] D10_APC_1: 0xffffffff
10030 10:02:27.136434 INFO: [APUAPC] D10_APC_2: 0x3fffff
10031 10:02:27.139551 INFO: [APUAPC] D10_APC_3: 0x0
10032 10:02:27.142671 INFO: [APUAPC] D11_APC_0: 0xffffffff
10033 10:02:27.149578 INFO: [APUAPC] D11_APC_1: 0xffffffff
10034 10:02:27.152869 INFO: [APUAPC] D11_APC_2: 0x3fffff
10035 10:02:27.152946 INFO: [APUAPC] D11_APC_3: 0x0
10036 10:02:27.156380 INFO: [APUAPC] D12_APC_0: 0xffffffff
10037 10:02:27.162840 INFO: [APUAPC] D12_APC_1: 0xffffffff
10038 10:02:27.166061 INFO: [APUAPC] D12_APC_2: 0x3fffff
10039 10:02:27.166140 INFO: [APUAPC] D12_APC_3: 0x0
10040 10:02:27.169365 INFO: [APUAPC] D13_APC_0: 0xffffffff
10041 10:02:27.176019 INFO: [APUAPC] D13_APC_1: 0xffffffff
10042 10:02:27.179685 INFO: [APUAPC] D13_APC_2: 0x3fffff
10043 10:02:27.179783 INFO: [APUAPC] D13_APC_3: 0x0
10044 10:02:27.186399 INFO: [APUAPC] D14_APC_0: 0xffffffff
10045 10:02:27.189582 INFO: [APUAPC] D14_APC_1: 0xffffffff
10046 10:02:27.192681 INFO: [APUAPC] D14_APC_2: 0x3fffff
10047 10:02:27.196320 INFO: [APUAPC] D14_APC_3: 0x0
10048 10:02:27.199401 INFO: [APUAPC] D15_APC_0: 0xffffffff
10049 10:02:27.202388 INFO: [APUAPC] D15_APC_1: 0xffffffff
10050 10:02:27.205900 INFO: [APUAPC] D15_APC_2: 0x3fffff
10051 10:02:27.209022 INFO: [APUAPC] D15_APC_3: 0x0
10052 10:02:27.209099 INFO: [APUAPC] APC_CON: 0x4
10053 10:02:27.212205 INFO: [NOCDAPC] D0_APC_0: 0x0
10054 10:02:27.215779 INFO: [NOCDAPC] D0_APC_1: 0x0
10055 10:02:27.218949 INFO: [NOCDAPC] D1_APC_0: 0x0
10056 10:02:27.222207 INFO: [NOCDAPC] D1_APC_1: 0xfff
10057 10:02:27.225499 INFO: [NOCDAPC] D2_APC_0: 0x0
10058 10:02:27.229162 INFO: [NOCDAPC] D2_APC_1: 0xfff
10059 10:02:27.232055 INFO: [NOCDAPC] D3_APC_0: 0x0
10060 10:02:27.235780 INFO: [NOCDAPC] D3_APC_1: 0xfff
10061 10:02:27.239206 INFO: [NOCDAPC] D4_APC_0: 0x0
10062 10:02:27.239282 INFO: [NOCDAPC] D4_APC_1: 0xfff
10063 10:02:27.241897 INFO: [NOCDAPC] D5_APC_0: 0x0
10064 10:02:27.245486 INFO: [NOCDAPC] D5_APC_1: 0xfff
10065 10:02:27.248655 INFO: [NOCDAPC] D6_APC_0: 0x0
10066 10:02:27.252416 INFO: [NOCDAPC] D6_APC_1: 0xfff
10067 10:02:27.255128 INFO: [NOCDAPC] D7_APC_0: 0x0
10068 10:02:27.258393 INFO: [NOCDAPC] D7_APC_1: 0xfff
10069 10:02:27.261779 INFO: [NOCDAPC] D8_APC_0: 0x0
10070 10:02:27.265247 INFO: [NOCDAPC] D8_APC_1: 0xfff
10071 10:02:27.268221 INFO: [NOCDAPC] D9_APC_0: 0x0
10072 10:02:27.271770 INFO: [NOCDAPC] D9_APC_1: 0xfff
10073 10:02:27.275207 INFO: [NOCDAPC] D10_APC_0: 0x0
10074 10:02:27.278615 INFO: [NOCDAPC] D10_APC_1: 0xfff
10075 10:02:27.278691 INFO: [NOCDAPC] D11_APC_0: 0x0
10076 10:02:27.281671 INFO: [NOCDAPC] D11_APC_1: 0xfff
10077 10:02:27.284670 INFO: [NOCDAPC] D12_APC_0: 0x0
10078 10:02:27.288258 INFO: [NOCDAPC] D12_APC_1: 0xfff
10079 10:02:27.291922 INFO: [NOCDAPC] D13_APC_0: 0x0
10080 10:02:27.295130 INFO: [NOCDAPC] D13_APC_1: 0xfff
10081 10:02:27.298337 INFO: [NOCDAPC] D14_APC_0: 0x0
10082 10:02:27.301480 INFO: [NOCDAPC] D14_APC_1: 0xfff
10083 10:02:27.304732 INFO: [NOCDAPC] D15_APC_0: 0x0
10084 10:02:27.307984 INFO: [NOCDAPC] D15_APC_1: 0xfff
10085 10:02:27.311576 INFO: [NOCDAPC] APC_CON: 0x4
10086 10:02:27.315197 INFO: [APUAPC] set_apusys_apc done
10087 10:02:27.317923 INFO: [DEVAPC] devapc_init done
10088 10:02:27.321284 INFO: GICv3 without legacy support detected.
10089 10:02:27.324581 INFO: ARM GICv3 driver initialized in EL3
10090 10:02:27.327931 INFO: Maximum SPI INTID supported: 639
10091 10:02:27.334413 INFO: BL31: Initializing runtime services
10092 10:02:27.338142 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10093 10:02:27.341339 INFO: SPM: enable CPC mode
10094 10:02:27.347897 INFO: mcdi ready for mcusys-off-idle and system suspend
10095 10:02:27.351259 INFO: BL31: Preparing for EL3 exit to normal world
10096 10:02:27.354532 INFO: Entry point address = 0x80000000
10097 10:02:27.357578 INFO: SPSR = 0x8
10098 10:02:27.363095
10099 10:02:27.363178
10100 10:02:27.363243
10101 10:02:27.366323 Starting depthcharge on Spherion...
10102 10:02:27.366405
10103 10:02:27.366470 Wipe memory regions:
10104 10:02:27.366530
10105 10:02:27.367167 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10106 10:02:27.367267 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10107 10:02:27.367353 Setting prompt string to ['asurada:']
10108 10:02:27.367652 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10109 10:02:27.369170 [0x00000040000000, 0x00000054600000)
10110 10:02:27.491925
10111 10:02:27.492048 [0x00000054660000, 0x00000080000000)
10112 10:02:27.752612
10113 10:02:27.752747 [0x000000821a7280, 0x000000ffe64000)
10114 10:02:28.496967
10115 10:02:28.497103 [0x00000100000000, 0x00000240000000)
10116 10:02:30.387771
10117 10:02:30.391192 Initializing XHCI USB controller at 0x11200000.
10118 10:02:31.372532
10119 10:02:31.372680 R8152: Initializing
10120 10:02:31.372748
10121 10:02:31.375403 Version 9 (ocp_data = 6010)
10122 10:02:31.375490
10123 10:02:31.379151 R8152: Done initializing
10124 10:02:31.379235
10125 10:02:31.379301 Adding net device
10126 10:02:31.900779
10127 10:02:31.903794 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10128 10:02:31.903878
10129 10:02:31.903943
10130 10:02:31.904005
10131 10:02:31.904291 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10133 10:02:32.004637 asurada: tftpboot 192.168.201.1 10670640/tftp-deploy-knu8rojz/kernel/image.itb 10670640/tftp-deploy-knu8rojz/kernel/cmdline
10134 10:02:32.004767 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10135 10:02:32.004862 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10136 10:02:32.008980 tftpboot 192.168.201.1 10670640/tftp-deploy-knu8rojz/kernel/image.itp-deploy-knu8rojz/kernel/cmdline
10137 10:02:32.009074
10138 10:02:32.009142 Waiting for link
10139 10:02:32.211268
10140 10:02:32.211401 done.
10141 10:02:32.211470
10142 10:02:32.211532 MAC: f4:f5:e8:50:de:0a
10143 10:02:32.211593
10144 10:02:32.214604 Sending DHCP discover... done.
10145 10:02:32.214690
10146 10:02:32.218253 Waiting for reply... done.
10147 10:02:32.218337
10148 10:02:32.221453 Sending DHCP request... done.
10149 10:02:32.221538
10150 10:02:32.225471 Waiting for reply... done.
10151 10:02:32.225555
10152 10:02:32.225622 My ip is 192.168.201.14
10153 10:02:32.225682
10154 10:02:32.228535 The DHCP server ip is 192.168.201.1
10155 10:02:32.228632
10156 10:02:32.235434 TFTP server IP predefined by user: 192.168.201.1
10157 10:02:32.235517
10158 10:02:32.241688 Bootfile predefined by user: 10670640/tftp-deploy-knu8rojz/kernel/image.itb
10159 10:02:32.241771
10160 10:02:32.245134 Sending tftp read request... done.
10161 10:02:32.245218
10162 10:02:32.248621 Waiting for the transfer...
10163 10:02:32.248703
10164 10:02:32.474102 00000000 ################################################################
10165 10:02:32.474245
10166 10:02:32.698317 00080000 ################################################################
10167 10:02:32.698465
10168 10:02:32.919337 00100000 ################################################################
10169 10:02:32.919483
10170 10:02:33.141583 00180000 ################################################################
10171 10:02:33.141725
10172 10:02:33.362853 00200000 ################################################################
10173 10:02:33.363000
10174 10:02:33.586720 00280000 ################################################################
10175 10:02:33.586876
10176 10:02:33.817178 00300000 ################################################################
10177 10:02:33.817319
10178 10:02:34.049616 00380000 ################################################################
10179 10:02:34.049752
10180 10:02:34.279038 00400000 ################################################################
10181 10:02:34.279179
10182 10:02:34.508647 00480000 ################################################################
10183 10:02:34.508784
10184 10:02:34.745799 00500000 ################################################################
10185 10:02:34.745936
10186 10:02:35.007487 00580000 ################################################################
10187 10:02:35.007649
10188 10:02:35.239029 00600000 ################################################################
10189 10:02:35.239161
10190 10:02:35.483290 00680000 ################################################################
10191 10:02:35.483422
10192 10:02:35.715787 00700000 ################################################################
10193 10:02:35.715946
10194 10:02:35.944041 00780000 ################################################################
10195 10:02:35.944170
10196 10:02:36.184956 00800000 ################################################################
10197 10:02:36.185096
10198 10:02:36.412275 00880000 ################################################################
10199 10:02:36.412408
10200 10:02:36.641370 00900000 ################################################################
10201 10:02:36.641529
10202 10:02:36.866472 00980000 ################################################################
10203 10:02:36.866630
10204 10:02:37.092509 00a00000 ################################################################
10205 10:02:37.092678
10206 10:02:37.326453 00a80000 ################################################################
10207 10:02:37.326596
10208 10:02:37.588941 00b00000 ################################################################
10209 10:02:37.589083
10210 10:02:37.853208 00b80000 ################################################################
10211 10:02:37.853352
10212 10:02:38.118412 00c00000 ################################################################
10213 10:02:38.118577
10214 10:02:38.384199 00c80000 ################################################################
10215 10:02:38.384367
10216 10:02:38.638631 00d00000 ################################################################
10217 10:02:38.638825
10218 10:02:38.893729 00d80000 ################################################################
10219 10:02:38.893906
10220 10:02:39.136997 00e00000 ################################################################
10221 10:02:39.137137
10222 10:02:39.370662 00e80000 ################################################################
10223 10:02:39.370819
10224 10:02:39.597269 00f00000 ################################################################
10225 10:02:39.597400
10226 10:02:39.836125 00f80000 ################################################################
10227 10:02:39.836284
10228 10:02:40.066802 01000000 ################################################################
10229 10:02:40.066971
10230 10:02:40.313139 01080000 ################################################################
10231 10:02:40.313287
10232 10:02:40.550262 01100000 ################################################################
10233 10:02:40.550397
10234 10:02:40.783977 01180000 ################################################################
10235 10:02:40.784118
10236 10:02:41.017869 01200000 ################################################################
10237 10:02:41.018003
10238 10:02:41.259351 01280000 ################################################################
10239 10:02:41.259488
10240 10:02:41.492868 01300000 ################################################################
10241 10:02:41.493004
10242 10:02:41.720102 01380000 ################################################################
10243 10:02:41.720265
10244 10:02:41.973774 01400000 ################################################################
10245 10:02:41.973909
10246 10:02:42.232256 01480000 ################################################################
10247 10:02:42.232420
10248 10:02:42.468996 01500000 ################################################################
10249 10:02:42.469145
10250 10:02:42.701122 01580000 ################################################################
10251 10:02:42.701284
10252 10:02:42.931025 01600000 ################################################################
10253 10:02:42.931158
10254 10:02:43.159870 01680000 ################################################################
10255 10:02:43.160000
10256 10:02:43.387946 01700000 ################################################################
10257 10:02:43.388075
10258 10:02:43.614598 01780000 ################################################################
10259 10:02:43.614731
10260 10:02:43.849917 01800000 ################################################################
10261 10:02:43.850067
10262 10:02:44.086547 01880000 ################################################################
10263 10:02:44.086687
10264 10:02:44.315641 01900000 ################################################################
10265 10:02:44.315781
10266 10:02:44.541673 01980000 ################################################################
10267 10:02:44.541809
10268 10:02:44.787099 01a00000 ################################################################ done.
10269 10:02:44.787233
10270 10:02:44.790609 The bootfile was 27783378 bytes long.
10271 10:02:44.790699
10272 10:02:44.793546 Sending tftp read request... done.
10273 10:02:44.793644
10274 10:02:44.797522 Waiting for the transfer...
10275 10:02:44.797697
10276 10:02:44.797811 00000000 # done.
10277 10:02:44.800532
10278 10:02:44.807230 Command line loaded dynamically from TFTP file: 10670640/tftp-deploy-knu8rojz/kernel/cmdline
10279 10:02:44.807424
10280 10:02:44.827409 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10670640/extract-nfsrootfs-yyvetb3c,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10281 10:02:44.827995
10282 10:02:44.828368 Loading FIT.
10283 10:02:44.828788
10284 10:02:44.830312 Image ramdisk-1 has 17647103 bytes.
10285 10:02:44.830784
10286 10:02:44.833498 Image fdt-1 has 46924 bytes.
10287 10:02:44.833968
10288 10:02:44.836957 Image kernel-1 has 10087317 bytes.
10289 10:02:44.837429
10290 10:02:44.846923 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10291 10:02:44.847500
10292 10:02:44.863773 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10293 10:02:44.864391
10294 10:02:44.870122 Choosing best match conf-1 for compat google,spherion-rev2.
10295 10:02:44.870712
10296 10:02:44.877355 Connected to device vid:did:rid of 1ae0:0028:00
10297 10:02:44.884790
10298 10:02:44.887953 tpm_get_response: command 0x17b, return code 0x0
10299 10:02:44.888566
10300 10:02:44.891119 ec_init: CrosEC protocol v3 supported (256, 248)
10301 10:02:44.898096
10302 10:02:44.901165 tpm_cleanup: add release locality here.
10303 10:02:44.901748
10304 10:02:44.902235 Shutting down all USB controllers.
10305 10:02:44.904328
10306 10:02:44.904854 Removing current net device
10307 10:02:44.905334
10308 10:02:44.911156 Exiting depthcharge with code 4 at timestamp: 46914099
10309 10:02:44.911653
10310 10:02:44.914390 LZMA decompressing kernel-1 to 0x821a6718
10311 10:02:44.914914
10312 10:02:44.917837 LZMA decompressing kernel-1 to 0x40000000
10313 10:02:46.185691
10314 10:02:46.186264 jumping to kernel
10315 10:02:46.187700 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
10316 10:02:46.188233 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
10317 10:02:46.188679 Setting prompt string to ['Linux version [0-9]']
10318 10:02:46.189059 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10319 10:02:46.189439 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10320 10:02:46.267294
10321 10:02:46.271120 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10322 10:02:46.274853 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
10323 10:02:46.275462 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10324 10:02:46.276035 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10325 10:02:46.276463 Using line separator: #'\n'#
10326 10:02:46.276918 No login prompt set.
10327 10:02:46.277300 Parsing kernel messages
10328 10:02:46.277689 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10329 10:02:46.278279 [login-action] Waiting for messages, (timeout 00:04:06)
10330 10:02:46.293749 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j19381-arm64-gcc-10-defconfig-arm64-chromebook-d6qsg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023
10331 10:02:46.296571 [ 0.000000] random: crng init done
10332 10:02:46.300275 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10333 10:02:46.303733 [ 0.000000] efi: UEFI not found.
10334 10:02:46.313190 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10335 10:02:46.320017 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10336 10:02:46.329841 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10337 10:02:46.339879 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10338 10:02:46.346575 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10339 10:02:46.352929 [ 0.000000] printk: bootconsole [mtk8250] enabled
10340 10:02:46.359415 [ 0.000000] NUMA: No NUMA configuration found
10341 10:02:46.366163 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10342 10:02:46.369420 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10343 10:02:46.372691 [ 0.000000] Zone ranges:
10344 10:02:46.379612 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10345 10:02:46.383067 [ 0.000000] DMA32 empty
10346 10:02:46.389528 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10347 10:02:46.392947 [ 0.000000] Movable zone start for each node
10348 10:02:46.395721 [ 0.000000] Early memory node ranges
10349 10:02:46.402916 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10350 10:02:46.409412 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10351 10:02:46.415891 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10352 10:02:46.422119 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10353 10:02:46.426030 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10354 10:02:46.435482 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10355 10:02:46.491329 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10356 10:02:46.497618 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10357 10:02:46.504681 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10358 10:02:46.508283 [ 0.000000] psci: probing for conduit method from DT.
10359 10:02:46.514862 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10360 10:02:46.517571 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10361 10:02:46.524250 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10362 10:02:46.527744 [ 0.000000] psci: SMC Calling Convention v1.2
10363 10:02:46.534133 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10364 10:02:46.537226 [ 0.000000] Detected VIPT I-cache on CPU0
10365 10:02:46.544389 [ 0.000000] CPU features: detected: GIC system register CPU interface
10366 10:02:46.550465 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10367 10:02:46.557317 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10368 10:02:46.563686 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10369 10:02:46.573569 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10370 10:02:46.579948 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10371 10:02:46.583766 [ 0.000000] alternatives: applying boot alternatives
10372 10:02:46.590378 [ 0.000000] Fallback order for Node 0: 0
10373 10:02:46.597129 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10374 10:02:46.600043 [ 0.000000] Policy zone: Normal
10375 10:02:46.620230 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10670640/extract-nfsrootfs-yyvetb3c,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10376 10:02:46.629898 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10377 10:02:46.641892 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10378 10:02:46.651505 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10379 10:02:46.658037 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10380 10:02:46.661605 <6>[ 0.000000] software IO TLB: area num 8.
10381 10:02:46.717976 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10382 10:02:46.867181 <6>[ 0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)
10383 10:02:46.873800 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10384 10:02:46.880620 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10385 10:02:46.884022 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10386 10:02:46.890577 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10387 10:02:46.896874 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10388 10:02:46.903157 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10389 10:02:46.910253 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10390 10:02:46.916341 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10391 10:02:46.923485 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10392 10:02:46.930121 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10393 10:02:46.933211 <6>[ 0.000000] GICv3: 608 SPIs implemented
10394 10:02:46.936820 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10395 10:02:46.942999 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10396 10:02:46.946506 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10397 10:02:46.952985 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10398 10:02:46.966185 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10399 10:02:46.979777 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10400 10:02:46.986048 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10401 10:02:46.994770 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10402 10:02:47.007610 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10403 10:02:47.013763 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10404 10:02:47.020370 <6>[ 0.009167] Console: colour dummy device 80x25
10405 10:02:47.030592 <6>[ 0.013893] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10406 10:02:47.036766 <6>[ 0.024335] pid_max: default: 32768 minimum: 301
10407 10:02:47.039964 <6>[ 0.029238] LSM: Security Framework initializing
10408 10:02:47.046718 <6>[ 0.034176] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10409 10:02:47.056888 <6>[ 0.041958] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10410 10:02:47.066482 <6>[ 0.051383] cblist_init_generic: Setting adjustable number of callback queues.
10411 10:02:47.069609 <6>[ 0.058832] cblist_init_generic: Setting shift to 3 and lim to 1.
10412 10:02:47.076360 <6>[ 0.065169] cblist_init_generic: Setting shift to 3 and lim to 1.
10413 10:02:47.082741 <6>[ 0.071576] rcu: Hierarchical SRCU implementation.
10414 10:02:47.089305 <6>[ 0.076589] rcu: Max phase no-delay instances is 1000.
10415 10:02:47.096496 <6>[ 0.083609] EFI services will not be available.
10416 10:02:47.099016 <6>[ 0.088577] smp: Bringing up secondary CPUs ...
10417 10:02:47.107172 <6>[ 0.093627] Detected VIPT I-cache on CPU1
10418 10:02:47.113771 <6>[ 0.093699] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10419 10:02:47.120271 <6>[ 0.093731] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10420 10:02:47.123811 <6>[ 0.094067] Detected VIPT I-cache on CPU2
10421 10:02:47.133465 <6>[ 0.094117] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10422 10:02:47.140062 <6>[ 0.094132] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10423 10:02:47.143646 <6>[ 0.094392] Detected VIPT I-cache on CPU3
10424 10:02:47.150155 <6>[ 0.094440] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10425 10:02:47.156719 <6>[ 0.094454] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10426 10:02:47.163391 <6>[ 0.094756] CPU features: detected: Spectre-v4
10427 10:02:47.166483 <6>[ 0.094763] CPU features: detected: Spectre-BHB
10428 10:02:47.169833 <6>[ 0.094769] Detected PIPT I-cache on CPU4
10429 10:02:47.176990 <6>[ 0.094826] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10430 10:02:47.186198 <6>[ 0.094843] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10431 10:02:47.189454 <6>[ 0.095134] Detected PIPT I-cache on CPU5
10432 10:02:47.196254 <6>[ 0.095198] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10433 10:02:47.202806 <6>[ 0.095214] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10434 10:02:47.206069 <6>[ 0.095496] Detected PIPT I-cache on CPU6
10435 10:02:47.215962 <6>[ 0.095562] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10436 10:02:47.222247 <6>[ 0.095578] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10437 10:02:47.225514 <6>[ 0.095875] Detected PIPT I-cache on CPU7
10438 10:02:47.232033 <6>[ 0.095938] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10439 10:02:47.239122 <6>[ 0.095954] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10440 10:02:47.242401 <6>[ 0.096001] smp: Brought up 1 node, 8 CPUs
10441 10:02:47.248925 <6>[ 0.237309] SMP: Total of 8 processors activated.
10442 10:02:47.252223 <6>[ 0.242230] CPU features: detected: 32-bit EL0 Support
10443 10:02:47.261988 <6>[ 0.247593] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10444 10:02:47.268619 <6>[ 0.256394] CPU features: detected: Common not Private translations
10445 10:02:47.275750 <6>[ 0.262870] CPU features: detected: CRC32 instructions
10446 10:02:47.281659 <6>[ 0.268254] CPU features: detected: RCpc load-acquire (LDAPR)
10447 10:02:47.285156 <6>[ 0.274214] CPU features: detected: LSE atomic instructions
10448 10:02:47.291930 <6>[ 0.279995] CPU features: detected: Privileged Access Never
10449 10:02:47.298610 <6>[ 0.285775] CPU features: detected: RAS Extension Support
10450 10:02:47.305366 <6>[ 0.291418] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10451 10:02:47.308080 <6>[ 0.298683] CPU: All CPU(s) started at EL2
10452 10:02:47.315081 <6>[ 0.303000] alternatives: applying system-wide alternatives
10453 10:02:47.324831 <6>[ 0.313678] devtmpfs: initialized
10454 10:02:47.340198 <6>[ 0.322537] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10455 10:02:47.346823 <6>[ 0.332498] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10456 10:02:47.353149 <6>[ 0.340727] pinctrl core: initialized pinctrl subsystem
10457 10:02:47.356491 <6>[ 0.347396] DMI not present or invalid.
10458 10:02:47.363685 <6>[ 0.351803] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10459 10:02:47.373105 <6>[ 0.358687] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10460 10:02:47.379946 <6>[ 0.366261] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10461 10:02:47.389764 <6>[ 0.374489] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10462 10:02:47.396665 <6>[ 0.382730] audit: initializing netlink subsys (disabled)
10463 10:02:47.402647 <5>[ 0.388424] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10464 10:02:47.409317 <6>[ 0.389136] thermal_sys: Registered thermal governor 'step_wise'
10465 10:02:47.415612 <6>[ 0.396389] thermal_sys: Registered thermal governor 'power_allocator'
10466 10:02:47.419383 <6>[ 0.402642] cpuidle: using governor menu
10467 10:02:47.426254 <6>[ 0.413598] NET: Registered PF_QIPCRTR protocol family
10468 10:02:47.432500 <6>[ 0.419093] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10469 10:02:47.439526 <6>[ 0.426196] ASID allocator initialised with 32768 entries
10470 10:02:47.442265 <6>[ 0.432765] Serial: AMBA PL011 UART driver
10471 10:02:47.452849 <4>[ 0.441448] Trying to register duplicate clock ID: 134
10472 10:02:47.506370 <6>[ 0.498642] KASLR enabled
10473 10:02:47.520558 <6>[ 0.506340] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10474 10:02:47.527595 <6>[ 0.513352] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10475 10:02:47.533953 <6>[ 0.519840] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10476 10:02:47.540976 <6>[ 0.526845] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10477 10:02:47.547354 <6>[ 0.533333] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10478 10:02:47.553859 <6>[ 0.540335] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10479 10:02:47.560237 <6>[ 0.546819] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10480 10:02:47.567038 <6>[ 0.553824] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10481 10:02:47.570289 <6>[ 0.561291] ACPI: Interpreter disabled.
10482 10:02:47.578826 <6>[ 0.567723] iommu: Default domain type: Translated
10483 10:02:47.585161 <6>[ 0.572833] iommu: DMA domain TLB invalidation policy: strict mode
10484 10:02:47.588636 <5>[ 0.579497] SCSI subsystem initialized
10485 10:02:47.595357 <6>[ 0.583732] usbcore: registered new interface driver usbfs
10486 10:02:47.602160 <6>[ 0.589459] usbcore: registered new interface driver hub
10487 10:02:47.605004 <6>[ 0.595011] usbcore: registered new device driver usb
10488 10:02:47.612408 <6>[ 0.601108] pps_core: LinuxPPS API ver. 1 registered
10489 10:02:47.622175 <6>[ 0.606304] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10490 10:02:47.625207 <6>[ 0.615642] PTP clock support registered
10491 10:02:47.628399 <6>[ 0.619879] EDAC MC: Ver: 3.0.0
10492 10:02:47.635882 <6>[ 0.625067] FPGA manager framework
10493 10:02:47.642331 <6>[ 0.628742] Advanced Linux Sound Architecture Driver Initialized.
10494 10:02:47.645527 <6>[ 0.635504] vgaarb: loaded
10495 10:02:47.652150 <6>[ 0.638673] clocksource: Switched to clocksource arch_sys_counter
10496 10:02:47.655669 <5>[ 0.645096] VFS: Disk quotas dquot_6.6.0
10497 10:02:47.662575 <6>[ 0.649282] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10498 10:02:47.665420 <6>[ 0.656469] pnp: PnP ACPI: disabled
10499 10:02:47.674097 <6>[ 0.663103] NET: Registered PF_INET protocol family
10500 10:02:47.683952 <6>[ 0.668686] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10501 10:02:47.695128 <6>[ 0.680920] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10502 10:02:47.704951 <6>[ 0.689736] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10503 10:02:47.711553 <6>[ 0.697706] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10504 10:02:47.721732 <6>[ 0.706406] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10505 10:02:47.728316 <6>[ 0.716152] TCP: Hash tables configured (established 65536 bind 65536)
10506 10:02:47.735023 <6>[ 0.723012] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10507 10:02:47.744932 <6>[ 0.730207] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10508 10:02:47.751312 <6>[ 0.737905] NET: Registered PF_UNIX/PF_LOCAL protocol family
10509 10:02:47.757924 <6>[ 0.744069] RPC: Registered named UNIX socket transport module.
10510 10:02:47.761321 <6>[ 0.750222] RPC: Registered udp transport module.
10511 10:02:47.767582 <6>[ 0.755154] RPC: Registered tcp transport module.
10512 10:02:47.774261 <6>[ 0.760086] RPC: Registered tcp NFSv4.1 backchannel transport module.
10513 10:02:47.777378 <6>[ 0.766752] PCI: CLS 0 bytes, default 64
10514 10:02:47.780991 <6>[ 0.771130] Unpacking initramfs...
10515 10:02:47.797399 <6>[ 0.783246] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10516 10:02:47.807434 <6>[ 0.791901] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10517 10:02:47.811030 <6>[ 0.800739] kvm [1]: IPA Size Limit: 40 bits
10518 10:02:47.817709 <6>[ 0.805266] kvm [1]: GICv3: no GICV resource entry
10519 10:02:47.821014 <6>[ 0.810285] kvm [1]: disabling GICv2 emulation
10520 10:02:47.827277 <6>[ 0.814968] kvm [1]: GIC system register CPU interface enabled
10521 10:02:47.830507 <6>[ 0.821133] kvm [1]: vgic interrupt IRQ18
10522 10:02:47.838291 <6>[ 0.826776] kvm [1]: VHE mode initialized successfully
10523 10:02:47.844463 <5>[ 0.833172] Initialise system trusted keyrings
10524 10:02:47.851480 <6>[ 0.837991] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10525 10:02:47.859150 <6>[ 0.848000] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10526 10:02:47.865581 <5>[ 0.854402] NFS: Registering the id_resolver key type
10527 10:02:47.868801 <5>[ 0.859702] Key type id_resolver registered
10528 10:02:47.875520 <5>[ 0.864116] Key type id_legacy registered
10529 10:02:47.882279 <6>[ 0.868399] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10530 10:02:47.888726 <6>[ 0.875325] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10531 10:02:47.895574 <6>[ 0.883068] 9p: Installing v9fs 9p2000 file system support
10532 10:02:47.932010 <5>[ 0.920836] Key type asymmetric registered
10533 10:02:47.935157 <5>[ 0.925174] Asymmetric key parser 'x509' registered
10534 10:02:47.945121 <6>[ 0.930320] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10535 10:02:47.948857 <6>[ 0.937935] io scheduler mq-deadline registered
10536 10:02:47.951958 <6>[ 0.942708] io scheduler kyber registered
10537 10:02:47.970285 <6>[ 0.959547] EINJ: ACPI disabled.
10538 10:02:48.002709 <4>[ 0.985050] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10539 10:02:48.012609 <4>[ 0.995690] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10540 10:02:48.027585 <6>[ 1.016471] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10541 10:02:48.035367 <6>[ 1.024460] printk: console [ttyS0] disabled
10542 10:02:48.063307 <6>[ 1.049134] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10543 10:02:48.070344 <6>[ 1.058608] printk: console [ttyS0] enabled
10544 10:02:48.074110 <6>[ 1.058608] printk: console [ttyS0] enabled
10545 10:02:48.080064 <6>[ 1.067503] printk: bootconsole [mtk8250] disabled
10546 10:02:48.083172 <6>[ 1.067503] printk: bootconsole [mtk8250] disabled
10547 10:02:48.090206 <6>[ 1.078764] SuperH (H)SCI(F) driver initialized
10548 10:02:48.093067 <6>[ 1.084028] msm_serial: driver initialized
10549 10:02:48.107704 <6>[ 1.093094] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10550 10:02:48.117543 <6>[ 1.101644] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10551 10:02:48.124023 <6>[ 1.110187] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10552 10:02:48.134078 <6>[ 1.118816] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10553 10:02:48.143738 <6>[ 1.127524] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10554 10:02:48.151149 <6>[ 1.136238] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10555 10:02:48.160409 <6>[ 1.144780] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10556 10:02:48.167220 <6>[ 1.153588] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10557 10:02:48.176797 <6>[ 1.162133] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10558 10:02:48.189369 <6>[ 1.177830] loop: module loaded
10559 10:02:48.195519 <6>[ 1.183786] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10560 10:02:48.218422 <4>[ 1.207470] mtk-pmic-keys: Failed to locate of_node [id: -1]
10561 10:02:48.225326 <6>[ 1.214417] megasas: 07.719.03.00-rc1
10562 10:02:48.235234 <6>[ 1.224176] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10563 10:02:48.245745 <6>[ 1.234050] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10564 10:02:48.262091 <6>[ 1.250777] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10565 10:02:48.322564 <6>[ 1.304870] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10566 10:02:48.507486 <6>[ 1.496129] Freeing initrd memory: 17228K
10567 10:02:48.517742 <6>[ 1.506485] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10568 10:02:48.528662 <6>[ 1.517302] tun: Universal TUN/TAP device driver, 1.6
10569 10:02:48.531802 <6>[ 1.523355] thunder_xcv, ver 1.0
10570 10:02:48.535679 <6>[ 1.526860] thunder_bgx, ver 1.0
10571 10:02:48.537967 <6>[ 1.530349] nicpf, ver 1.0
10572 10:02:48.548672 <6>[ 1.534345] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10573 10:02:48.551962 <6>[ 1.541820] hns3: Copyright (c) 2017 Huawei Corporation.
10574 10:02:48.558738 <6>[ 1.547409] hclge is initializing
10575 10:02:48.562398 <6>[ 1.550987] e1000: Intel(R) PRO/1000 Network Driver
10576 10:02:48.568676 <6>[ 1.556116] e1000: Copyright (c) 1999-2006 Intel Corporation.
10577 10:02:48.571821 <6>[ 1.562129] e1000e: Intel(R) PRO/1000 Network Driver
10578 10:02:48.578511 <6>[ 1.567345] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10579 10:02:48.585190 <6>[ 1.573531] igb: Intel(R) Gigabit Ethernet Network Driver
10580 10:02:48.591681 <6>[ 1.579181] igb: Copyright (c) 2007-2014 Intel Corporation.
10581 10:02:48.598287 <6>[ 1.585017] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10582 10:02:48.604620 <6>[ 1.591534] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10583 10:02:48.607996 <6>[ 1.597993] sky2: driver version 1.30
10584 10:02:48.614852 <6>[ 1.602970] VFIO - User Level meta-driver version: 0.3
10585 10:02:48.622140 <6>[ 1.611169] usbcore: registered new interface driver usb-storage
10586 10:02:48.628721 <6>[ 1.617613] usbcore: registered new device driver onboard-usb-hub
10587 10:02:48.638044 <6>[ 1.626716] mt6397-rtc mt6359-rtc: registered as rtc0
10588 10:02:48.647564 <6>[ 1.632177] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-10T10:02:51 UTC (1686391371)
10589 10:02:48.650929 <6>[ 1.641735] i2c_dev: i2c /dev entries driver
10590 10:02:48.668675 <6>[ 1.653373] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10591 10:02:48.674749 <6>[ 1.663572] sdhci: Secure Digital Host Controller Interface driver
10592 10:02:48.681216 <6>[ 1.670010] sdhci: Copyright(c) Pierre Ossman
10593 10:02:48.688222 <6>[ 1.675405] Synopsys Designware Multimedia Card Interface Driver
10594 10:02:48.691654 <6>[ 1.682002] mmc0: CQHCI version 5.10
10595 10:02:48.697798 <6>[ 1.682554] sdhci-pltfm: SDHCI platform and OF driver helper
10596 10:02:48.705078 <6>[ 1.693866] ledtrig-cpu: registered to indicate activity on CPUs
10597 10:02:48.715613 <6>[ 1.701142] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10598 10:02:48.721905 <6>[ 1.708535] usbcore: registered new interface driver usbhid
10599 10:02:48.725222 <6>[ 1.714367] usbhid: USB HID core driver
10600 10:02:48.731998 <6>[ 1.718612] spi_master spi0: will run message pump with realtime priority
10601 10:02:48.777320 <6>[ 1.759623] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10602 10:02:48.796956 <6>[ 1.775538] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10603 10:02:48.800255 <6>[ 1.789123] mmc0: Command Queue Engine enabled
10604 10:02:48.806749 <6>[ 1.793114] cros-ec-spi spi0.0: Chrome EC device registered
10605 10:02:48.813788 <6>[ 1.793856] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10606 10:02:48.817132 <6>[ 1.806910] mmcblk0: mmc0:0001 DA4128 116 GiB
10607 10:02:48.828345 <6>[ 1.817217] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10608 10:02:48.838150 <6>[ 1.817356] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10609 10:02:48.844957 <6>[ 1.824576] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10610 10:02:48.848153 <6>[ 1.834648] NET: Registered PF_PACKET protocol family
10611 10:02:48.854953 <6>[ 1.838363] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10612 10:02:48.858502 <6>[ 1.843120] 9pnet: Installing 9P2000 support
10613 10:02:48.864717 <6>[ 1.848883] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10614 10:02:48.868332 <5>[ 1.852783] Key type dns_resolver registered
10615 10:02:48.875548 <6>[ 1.864419] registered taskstats version 1
10616 10:02:48.878869 <5>[ 1.868827] Loading compiled-in X.509 certificates
10617 10:02:48.913784 <4>[ 1.895546] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10618 10:02:48.923182 <4>[ 1.906224] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10619 10:02:48.933243 <3>[ 1.918892] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10620 10:02:48.945317 <6>[ 1.934318] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10621 10:02:48.952680 <6>[ 1.941142] xhci-mtk 11200000.usb: xHCI Host Controller
10622 10:02:48.958593 <6>[ 1.946654] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10623 10:02:48.968704 <6>[ 1.954505] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10624 10:02:48.975296 <6>[ 1.963956] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10625 10:02:48.982249 <6>[ 1.970167] xhci-mtk 11200000.usb: xHCI Host Controller
10626 10:02:48.989198 <6>[ 1.975669] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10627 10:02:48.995439 <6>[ 1.983327] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10628 10:02:49.002026 <6>[ 1.991234] hub 1-0:1.0: USB hub found
10629 10:02:49.005842 <6>[ 1.995274] hub 1-0:1.0: 1 port detected
10630 10:02:49.015482 <6>[ 1.999618] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10631 10:02:49.018838 <6>[ 2.008230] hub 2-0:1.0: USB hub found
10632 10:02:49.022338 <6>[ 2.012247] hub 2-0:1.0: 1 port detected
10633 10:02:49.030693 <6>[ 2.019232] mtk-msdc 11f70000.mmc: Got CD GPIO
10634 10:02:49.051251 <6>[ 2.036641] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10635 10:02:49.058157 <6>[ 2.044705] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10636 10:02:49.067511 <4>[ 2.052700] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10637 10:02:49.077707 <6>[ 2.062365] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10638 10:02:49.083979 <6>[ 2.070446] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10639 10:02:49.094548 <6>[ 2.078481] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10640 10:02:49.100669 <6>[ 2.086395] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10641 10:02:49.107120 <6>[ 2.094216] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10642 10:02:49.117203 <6>[ 2.102039] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10643 10:02:49.127760 <6>[ 2.112839] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10644 10:02:49.137587 <6>[ 2.121211] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10645 10:02:49.143709 <6>[ 2.129563] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10646 10:02:49.153941 <6>[ 2.137906] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10647 10:02:49.160249 <6>[ 2.146249] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10648 10:02:49.170415 <6>[ 2.154592] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10649 10:02:49.176963 <6>[ 2.162937] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10650 10:02:49.187013 <6>[ 2.171280] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10651 10:02:49.193934 <6>[ 2.179623] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10652 10:02:49.203723 <6>[ 2.187967] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10653 10:02:49.210139 <6>[ 2.196311] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10654 10:02:49.220504 <6>[ 2.204654] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10655 10:02:49.227454 <6>[ 2.212997] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10656 10:02:49.236839 <6>[ 2.221341] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10657 10:02:49.243103 <6>[ 2.229685] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10658 10:02:49.249608 <6>[ 2.238595] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10659 10:02:49.256919 <6>[ 2.246049] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10660 10:02:49.264423 <6>[ 2.253116] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10661 10:02:49.274890 <6>[ 2.260205] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10662 10:02:49.281034 <6>[ 2.267476] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10663 10:02:49.291321 <6>[ 2.274387] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10664 10:02:49.297856 <6>[ 2.283539] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10665 10:02:49.307944 <6>[ 2.292665] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10666 10:02:49.317554 <6>[ 2.301969] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10667 10:02:49.327755 <6>[ 2.311444] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10668 10:02:49.337160 <6>[ 2.320918] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10669 10:02:49.344012 <6>[ 2.330046] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10670 10:02:49.353875 <6>[ 2.339523] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10671 10:02:49.363894 <6>[ 2.348650] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10672 10:02:49.373626 <6>[ 2.357952] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10673 10:02:49.383574 <6>[ 2.368117] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10674 10:02:49.393932 <6>[ 2.380106] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10675 10:02:49.400932 <6>[ 2.390035] Trying to probe devices needed for running init ...
10676 10:02:49.433639 <6>[ 2.418741] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10677 10:02:49.586054 <6>[ 2.574953] hub 1-1:1.0: USB hub found
10678 10:02:49.589153 <6>[ 2.579309] hub 1-1:1.0: 4 ports detected
10679 10:02:49.713313 <6>[ 2.699034] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10680 10:02:49.740020 <6>[ 2.729103] hub 2-1:1.0: USB hub found
10681 10:02:49.743090 <6>[ 2.733628] hub 2-1:1.0: 3 ports detected
10682 10:02:49.909426 <6>[ 2.894975] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10683 10:02:50.039612 <6>[ 3.028835] hub 1-1.1:1.0: USB hub found
10684 10:02:50.043404 <6>[ 3.033113] hub 1-1.1:1.0: 4 ports detected
10685 10:02:50.156816 <6>[ 3.142809] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10686 10:02:50.289815 <6>[ 3.279009] hub 1-1.4:1.0: USB hub found
10687 10:02:50.293110 <6>[ 3.283691] hub 1-1.4:1.0: 2 ports detected
10688 10:02:50.373264 <6>[ 3.358919] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10689 10:02:50.557248 <6>[ 3.542916] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10690 10:02:50.641935 <3>[ 3.630947] usb 1-1.1.4: device descriptor read/64, error -32
10691 10:02:50.833116 <3>[ 3.822947] usb 1-1.1.4: device descriptor read/64, error -32
10692 10:02:51.028763 <6>[ 4.014915] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10693 10:02:51.212637 <6>[ 4.198916] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10694 10:02:51.297117 <3>[ 4.286946] usb 1-1.1.4: device descriptor read/64, error -32
10695 10:02:51.489590 <3>[ 4.478947] usb 1-1.1.4: device descriptor read/64, error -32
10696 10:02:51.601719 <6>[ 4.591231] usb 1-1.1-port4: attempt power cycle
10697 10:02:51.688238 <6>[ 4.674916] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10698 10:02:52.212871 <6>[ 5.198918] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10699 10:02:52.219247 <4>[ 5.206273] usb 1-1.1.4: Device not responding to setup address.
10700 10:02:52.429630 <4>[ 5.418998] usb 1-1.1.4: Device not responding to setup address.
10701 10:02:52.641203 <3>[ 5.630910] usb 1-1.1.4: device not accepting address 10, error -71
10702 10:02:52.728559 <6>[ 5.714852] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10703 10:02:52.735240 <4>[ 5.722256] usb 1-1.1.4: Device not responding to setup address.
10704 10:02:52.945705 <4>[ 5.935033] usb 1-1.1.4: Device not responding to setup address.
10705 10:02:53.157813 <3>[ 6.146912] usb 1-1.1.4: device not accepting address 11, error -71
10706 10:02:53.164187 <3>[ 6.153667] usb 1-1.1-port4: unable to enumerate USB device
10707 10:03:01.673854 <6>[ 14.667507] ALSA device list:
10708 10:03:01.680430 <6>[ 14.670764] No soundcards found.
10709 10:03:01.692551 <6>[ 14.683162] Freeing unused kernel memory: 8384K
10710 10:03:01.695636 <6>[ 14.688097] Run /init as init process
10711 10:03:01.706391 Loading, please wait...
10712 10:03:01.726519 Starting version 247.3-7+deb11u2
10713 10:03:02.054214 <6>[ 15.041091] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10714 10:03:02.100286 <3>[ 15.087393] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 10:03:02.106791 <3>[ 15.095559] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 10:03:02.116826 <3>[ 15.103650] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 10:03:02.120678 <6>[ 15.104280] remoteproc remoteproc0: scp is available
10718 10:03:02.130274 <4>[ 15.117180] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10719 10:03:02.140032 <3>[ 15.123066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 10:03:02.143136 <6>[ 15.127047] remoteproc remoteproc0: powering up scp
10721 10:03:02.153024 <3>[ 15.135157] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 10:03:02.163271 <4>[ 15.140297] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10723 10:03:02.169840 <3>[ 15.148354] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 10:03:02.179571 <6>[ 15.153182] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10725 10:03:02.186509 <6>[ 15.153206] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10726 10:03:02.196662 <6>[ 15.153217] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10727 10:03:02.203685 <3>[ 15.158177] remoteproc remoteproc0: request_firmware failed: -2
10728 10:03:02.210111 <3>[ 15.166377] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 10:03:02.216196 <6>[ 15.184232] mc: Linux media interface: v0.10
10730 10:03:02.222732 <3>[ 15.191554] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 10:03:02.229782 <4>[ 15.191838] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10732 10:03:02.235841 <4>[ 15.192649] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10733 10:03:02.246107 <6>[ 15.196335] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10734 10:03:02.250821 <6>[ 15.211516] usbcore: registered new interface driver r8152
10735 10:03:02.260169 <3>[ 15.218621] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 10:03:02.266602 <6>[ 15.219197] videodev: Linux video capture interface: v2.00
10737 10:03:02.273779 <4>[ 15.224414] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10738 10:03:02.277095 <4>[ 15.224414] Fallback method does not support PEC.
10739 10:03:02.287605 <3>[ 15.240399] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10740 10:03:02.293852 <3>[ 15.240823] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 10:03:02.303695 <3>[ 15.271309] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10742 10:03:02.310217 <6>[ 15.272216] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10743 10:03:02.317132 <6>[ 15.272226] pci_bus 0000:00: root bus resource [bus 00-ff]
10744 10:03:02.322954 <6>[ 15.272235] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10745 10:03:02.333260 <6>[ 15.272242] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10746 10:03:02.340055 <6>[ 15.272278] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10747 10:03:02.346633 <6>[ 15.272296] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10748 10:03:02.352839 <6>[ 15.272371] pci 0000:00:00.0: supports D1 D2
10749 10:03:02.359544 <6>[ 15.272375] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10750 10:03:02.366729 <3>[ 15.273790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 10:03:02.376453 <6>[ 15.274222] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10752 10:03:02.382626 <6>[ 15.274325] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10753 10:03:02.389630 <6>[ 15.274353] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10754 10:03:02.396029 <6>[ 15.274373] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10755 10:03:02.402754 <6>[ 15.274390] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10756 10:03:02.409657 <6>[ 15.274500] pci 0000:01:00.0: supports D1 D2
10757 10:03:02.415926 <6>[ 15.274503] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10758 10:03:02.422607 <6>[ 15.286717] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10759 10:03:02.429083 <3>[ 15.290586] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 10:03:02.438890 <6>[ 15.299370] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10761 10:03:02.445844 <3>[ 15.306268] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 10:03:02.455489 <6>[ 15.306986] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10763 10:03:02.462360 <6>[ 15.307367] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10764 10:03:02.471775 <6>[ 15.311954] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10765 10:03:02.481815 <6>[ 15.315376] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10766 10:03:02.491905 <6>[ 15.315624] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10767 10:03:02.498343 <3>[ 15.319083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 10:03:02.504658 <6>[ 15.329004] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10769 10:03:02.514729 <3>[ 15.335263] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 10:03:02.521931 <6>[ 15.335763] usbcore: registered new interface driver cdc_ether
10771 10:03:02.527957 <6>[ 15.342782] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10772 10:03:02.534968 <6>[ 15.343156] usbcore: registered new interface driver r8153_ecm
10773 10:03:02.545036 <3>[ 15.347304] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 10:03:02.550839 <6>[ 15.354204] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10775 10:03:02.554694 <6>[ 15.355093] Bluetooth: Core ver 2.22
10776 10:03:02.560894 <6>[ 15.355193] NET: Registered PF_BLUETOOTH protocol family
10777 10:03:02.568418 <6>[ 15.355196] Bluetooth: HCI device and connection manager initialized
10778 10:03:02.571122 <6>[ 15.355222] Bluetooth: HCI socket layer initialized
10779 10:03:02.577675 <6>[ 15.355229] Bluetooth: L2CAP socket layer initialized
10780 10:03:02.584248 <6>[ 15.355246] Bluetooth: SCO socket layer initialized
10781 10:03:02.591114 <3>[ 15.362276] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 10:03:02.597207 <6>[ 15.363257] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10783 10:03:02.610300 <6>[ 15.364502] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10784 10:03:02.617139 <6>[ 15.364645] usbcore: registered new interface driver uvcvideo
10785 10:03:02.620776 <6>[ 15.370548] pci 0000:00:00.0: PCI bridge to [bus 01]
10786 10:03:02.630587 <3>[ 15.376828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10787 10:03:02.636906 <6>[ 15.384281] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10788 10:03:02.643424 <6>[ 15.392884] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10789 10:03:02.649873 <6>[ 15.399754] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10790 10:03:02.656245 <6>[ 15.411720] usbcore: registered new interface driver btusb
10791 10:03:02.666390 <4>[ 15.412475] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10792 10:03:02.673766 <3>[ 15.412485] Bluetooth: hci0: Failed to load firmware file (-2)
10793 10:03:02.679914 <3>[ 15.412490] Bluetooth: hci0: Failed to set up firmware (-2)
10794 10:03:02.689205 <4>[ 15.412494] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10795 10:03:02.696114 <6>[ 15.418797] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10796 10:03:02.702827 <4>[ 15.425655] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10797 10:03:02.712166 <4>[ 15.425665] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10798 10:03:02.716249 <6>[ 15.486903] r8152 1-1.1.1:1.0 eth0: v1.12.13
10799 10:03:02.722337 <6>[ 15.494222] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10800 10:03:02.729240 <6>[ 15.511282] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10801 10:03:02.765319 <5>[ 15.752654] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10802 10:03:02.783922 <5>[ 15.771149] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10803 10:03:02.791026 <4>[ 15.778027] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10804 10:03:02.796983 <6>[ 15.786911] cfg80211: failed to load regulatory.db
10805 10:03:02.842041 <6>[ 15.828973] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10806 10:03:02.848470 <6>[ 15.836557] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10807 10:03:02.872856 <6>[ 15.863360] mt7921e 0000:01:00.0: ASIC revision: 79610010
10808 10:03:02.978371 <4>[ 15.961976] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 10:03:02.981677 Begin: Loading essential drivers ... done.
10810 10:03:02.988287 Begin: Running /scripts/init-premount ... done.
10811 10:03:02.994348 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10812 10:03:03.004458 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10813 10:03:03.007947 Device /sys/class/net/enxf4f5e850de0a found
10814 10:03:03.008553 done.
10815 10:03:03.060048 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10816 10:03:03.101300 <4>[ 16.085299] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10817 10:03:03.221791 <4>[ 16.204987] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10818 10:03:03.340893 <4>[ 16.324778] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10819 10:03:03.457029 <4>[ 16.440750] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10820 10:03:03.573004 <4>[ 16.556701] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10821 10:03:03.688738 <4>[ 16.672587] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10822 10:03:03.804300 <4>[ 16.788531] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10823 10:03:03.921062 <4>[ 16.904453] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10824 10:03:04.036498 <4>[ 17.020408] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10825 10:03:04.144672 IP-Config: no re<6>[ 17.133473] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10826 10:03:04.151899 sponse after 2 s<3>[ 17.134468] mt7921e 0000:01:00.0: hardware init failed
10827 10:03:04.152444 ecs - giving up
10828 10:03:04.187575 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10829 10:03:05.292927 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10830 10:03:05.299911 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10831 10:03:05.305927 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10832 10:03:05.312350 host : mt8192-asurada-spherion-r0-cbg-9
10833 10:03:05.319165 domain : lava-rack
10834 10:03:05.322180 rootserver: 192.168.201.1 rootpath:
10835 10:03:05.325648 filename :
10836 10:03:05.384280 done.
10837 10:03:05.391584 Begin: Running /scripts/nfs-bottom ... done.
10838 10:03:05.409379 Begin: Running /scripts/init-bottom ... done.
10839 10:03:06.533891 <6>[ 19.524807] NET: Registered PF_INET6 protocol family
10840 10:03:06.540604 <6>[ 19.531501] Segment Routing with IPv6
10841 10:03:06.543694 <6>[ 19.535484] In-situ OAM (IOAM) with IPv6
10842 10:03:06.662369 <30>[ 19.632721] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10843 10:03:06.664894 <30>[ 19.656492] systemd[1]: Detected architecture arm64.
10844 10:03:06.686587
10845 10:03:06.689461 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10846 10:03:06.689935
10847 10:03:06.706686 <30>[ 19.697537] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10848 10:03:07.266310 <30>[ 20.253771] systemd[1]: Queued start job for default target Graphical Interface.
10849 10:03:07.293667 <30>[ 20.283973] systemd[1]: Created slice system-getty.slice.
10850 10:03:07.299671 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10851 10:03:07.316698 <30>[ 20.307561] systemd[1]: Created slice system-modprobe.slice.
10852 10:03:07.323235 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10853 10:03:07.340480 <30>[ 20.331610] systemd[1]: Created slice system-serial\x2dgetty.slice.
10854 10:03:07.350404 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10855 10:03:07.364666 <30>[ 20.355396] systemd[1]: Created slice User and Session Slice.
10856 10:03:07.371585 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10857 10:03:07.391103 <30>[ 20.379052] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10858 10:03:07.401469 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10859 10:03:07.415692 <30>[ 20.403094] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10860 10:03:07.422134 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10861 10:03:07.442780 <30>[ 20.427032] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10862 10:03:07.449305 <30>[ 20.439057] systemd[1]: Reached target Local Encrypted Volumes.
10863 10:03:07.455797 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10864 10:03:07.472401 <30>[ 20.463046] systemd[1]: Reached target Paths.
10865 10:03:07.475644 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10866 10:03:07.492295 <30>[ 20.482971] systemd[1]: Reached target Remote File Systems.
10867 10:03:07.498194 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10868 10:03:07.511937 <30>[ 20.502958] systemd[1]: Reached target Slices.
10869 10:03:07.518390 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10870 10:03:07.531936 <30>[ 20.522980] systemd[1]: Reached target Swap.
10871 10:03:07.535501 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10872 10:03:07.555547 <30>[ 20.543173] systemd[1]: Listening on initctl Compatibility Named Pipe.
10873 10:03:07.561962 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10874 10:03:07.568815 <30>[ 20.558482] systemd[1]: Listening on Journal Audit Socket.
10875 10:03:07.575199 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10876 10:03:07.589455 <30>[ 20.580308] systemd[1]: Listening on Journal Socket (/dev/log).
10877 10:03:07.595787 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10878 10:03:07.612295 <30>[ 20.603226] systemd[1]: Listening on Journal Socket.
10879 10:03:07.619002 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10880 10:03:07.637262 <30>[ 20.624215] systemd[1]: Listening on Network Service Netlink Socket.
10881 10:03:07.643409 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10882 10:03:07.659284 <30>[ 20.650201] systemd[1]: Listening on udev Control Socket.
10883 10:03:07.665689 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10884 10:03:07.679921 <30>[ 20.671223] systemd[1]: Listening on udev Kernel Socket.
10885 10:03:07.686717 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10886 10:03:07.724189 <30>[ 20.715139] systemd[1]: Mounting Huge Pages File System...
10887 10:03:07.730726 Mounting [0;1;39mHuge Pages File System[0m...
10888 10:03:07.749517 <30>[ 20.737499] systemd[1]: Mounting POSIX Message Queue File System...
10889 10:03:07.752798 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10890 10:03:07.770143 <30>[ 20.761247] systemd[1]: Mounting Kernel Debug File System...
10891 10:03:07.776610 Mounting [0;1;39mKernel Debug File System[0m...
10892 10:03:07.795208 <30>[ 20.783203] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10893 10:03:07.843817 <30>[ 20.831433] systemd[1]: Starting Create list of static device nodes for the current kernel...
10894 10:03:07.851045 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10895 10:03:07.870235 <30>[ 20.861450] systemd[1]: Starting Load Kernel Module configfs...
10896 10:03:07.877027 Starting [0;1;39mLoad Kernel Module configfs[0m...
10897 10:03:07.894787 <30>[ 20.885528] systemd[1]: Starting Load Kernel Module drm...
10898 10:03:07.900898 Starting [0;1;39mLoad Kernel Module drm[0m...
10899 10:03:07.918330 <30>[ 20.909347] systemd[1]: Starting Load Kernel Module fuse...
10900 10:03:07.924851 Starting [0;1;39mLoad Kernel Module fuse[0m...
10901 10:03:07.958648 <6>[ 20.949268] fuse: init (API version 7.37)
10902 10:03:07.967842 <30>[ 20.950323] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10903 10:03:07.976711 <30>[ 20.967456] systemd[1]: Starting Journal Service...
10904 10:03:07.980065 Starting [0;1;39mJournal Service[0m...
10905 10:03:08.004082 <30>[ 20.995225] systemd[1]: Starting Load Kernel Modules...
10906 10:03:08.010366 Starting [0;1;39mLoad Kernel Modules[0m...
10907 10:03:08.030345 <30>[ 21.017858] systemd[1]: Starting Remount Root and Kernel File Systems...
10908 10:03:08.036178 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10909 10:03:08.051621 <30>[ 21.042657] systemd[1]: Starting Coldplug All udev Devices...
10910 10:03:08.058287 Starting [0;1;39mColdplug All udev Devices[0m...
10911 10:03:08.074549 <30>[ 21.065984] systemd[1]: Mounted Huge Pages File System.
10912 10:03:08.081050 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10913 10:03:08.095914 <30>[ 21.087339] systemd[1]: Mounted POSIX Message Queue File System.
10914 10:03:08.102809 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10915 10:03:08.120924 <30>[ 21.111456] systemd[1]: Mounted Kernel Debug File System.
10916 10:03:08.127111 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10917 10:03:08.140490 <3>[ 21.128266] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 10:03:08.150373 <30>[ 21.138133] systemd[1]: Finished Create list of static device nodes for the current kernel.
10919 10:03:08.160363 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10920 10:03:08.172578 <3>[ 21.160190] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 10:03:08.179880 <30>[ 21.169999] systemd[1]: modprobe@configfs.service: Succeeded.
10922 10:03:08.185658 <30>[ 21.176660] systemd[1]: Finished Load Kernel Module configfs.
10923 10:03:08.192354 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10924 10:03:08.209097 <30>[ 21.199777] systemd[1]: modprobe@drm.service: Succeeded.
10925 10:03:08.215357 <30>[ 21.206009] systemd[1]: Finished Load Kernel Module drm.
10926 10:03:08.225496 <3>[ 21.206449] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 10:03:08.231909 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10928 10:03:08.245373 <30>[ 21.235684] systemd[1]: modprobe@fuse.service: Succeeded.
10929 10:03:08.251790 <30>[ 21.242185] systemd[1]: Finished Load Kernel Module fuse.
10930 10:03:08.261830 <3>[ 21.245907] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 10:03:08.269219 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10932 10:03:08.281725 <30>[ 21.272002] systemd[1]: Finished Load Kernel Modules.
10933 10:03:08.294504 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 21.281435] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 10:03:08.295074 l Modules[0m.
10935 10:03:08.312058 <30>[ 21.300107] systemd[1]: Finished Remount Root and Kernel File Systems.
10936 10:03:08.319908 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10937 10:03:08.325936 <3>[ 21.314188] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 10:03:08.360899 <3>[ 21.348148] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 10:03:08.367935 <30>[ 21.359297] systemd[1]: Mounting FUSE Control File System...
10940 10:03:08.374504 Mounting [0;1;39mFUSE Control File System[0m...
10941 10:03:08.389610 <3>[ 21.377105] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 10:03:08.400703 <30>[ 21.388675] systemd[1]: Mounting Kernel Configuration File System...
10943 10:03:08.404352 Mounting [0;1;39mKernel Configuration File System[0m...
10944 10:03:08.420330 <3>[ 21.408128] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 10:03:08.434905 <30>[ 21.422917] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10946 10:03:08.445278 <30>[ 21.432000] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10947 10:03:08.455100 <3>[ 21.439632] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 10:03:08.485417 <30>[ 21.475354] systemd[1]: Starting Load/Save Random Seed...
10949 10:03:08.491242 Starting [0;1;39mLoad/Save Random Seed[0m...
10950 10:03:08.508107 <30>[ 21.498165] systemd[1]: Starting Apply Kernel Variables...
10951 10:03:08.514034 Starting [0;1;39mApply Kernel Variables[0m...
10952 10:03:08.531166 <30>[ 21.522447] systemd[1]: Starting Create System Users...
10953 10:03:08.537587 Starting [0;1;39mCreate System Users[0m...
10954 10:03:08.553310 <30>[ 21.544439] systemd[1]: Started Journal Service.
10955 10:03:08.559969 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10956 10:03:08.601358 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10957 10:03:08.620607 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10958 10:03:08.641413 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10959 10:03:08.657311 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10960 10:03:08.673047 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10961 10:03:08.733101 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10962 10:03:08.754529 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10963 10:03:08.792644 <46>[ 21.780209] systemd-journald[295]: Received client request to flush runtime journal.
10964 10:03:08.808933 <4>[ 21.787302] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10965 10:03:08.816011 <3>[ 21.804088] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10966 10:03:08.844755 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10967 10:03:08.859819 See 'systemctl status systemd-udev-trigger.service' for details.
10968 10:03:09.187448 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10969 10:03:09.200111 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10970 10:03:09.219468 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10971 10:03:09.279025 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10972 10:03:10.197103 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10973 10:03:10.232865 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10974 10:03:10.252418 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10975 10:03:10.276226 Starting [0;1;39mNetwork Service[0m...
10976 10:03:10.620114 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10977 10:03:10.647544 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10978 10:03:10.709567 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10979 10:03:10.841066 <6>[ 23.832830] remoteproc remoteproc0: powering up scp
10980 10:03:10.862979 <4>[ 23.851486] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10981 10:03:10.869830 <3>[ 23.861350] remoteproc remoteproc0: request_firmware failed: -2
10982 10:03:10.879618 <3>[ 23.867547] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10983 10:03:10.994508 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10984 10:03:11.007402 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10985 10:03:11.047767 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10986 10:03:11.069531 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10987 10:03:11.091434 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10988 10:03:11.135990 Starting [0;1;39mNetwork Name Resolution[0m...
10989 10:03:11.161374 Starting [0;1;39mNetwork Time Synchronization[0m...
10990 10:03:11.178444 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10991 10:03:11.232162 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10992 10:03:11.267394 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10993 10:03:11.321084 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10994 10:03:11.615940 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10995 10:03:11.631414 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10996 10:03:11.650805 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10997 10:03:11.663141 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10998 10:03:11.679358 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10999 10:03:11.702190 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11000 10:03:11.745611 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11001 10:03:12.119392 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11002 10:03:12.477168 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11003 10:03:12.491379 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11004 10:03:12.804384 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11005 10:03:12.819322 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11006 10:03:12.835189 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11007 10:03:12.883437 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11008 10:03:12.922534 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11009 10:03:12.992192 Starting [0;1;39mUser Login Management[0m...
11010 10:03:13.007894 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11011 10:03:13.024555 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11012 10:03:13.042652 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11013 10:03:13.083564 Starting [0;1;39mPermit User Sessions[0m...
11014 10:03:13.216353 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11015 10:03:13.247634 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11016 10:03:13.272957 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11017 10:03:13.287981 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11018 10:03:13.308573 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11019 10:03:13.325757 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11020 10:03:13.344752 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11021 10:03:13.360204 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11022 10:03:13.404630 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11023 10:03:13.471047 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11024 10:03:13.527697
11025 10:03:13.527857
11026 10:03:13.531225 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11027 10:03:13.531303
11028 10:03:13.533785 debian-bullseye-arm64 login: root (automatic login)
11029 10:03:13.533860
11030 10:03:13.533923
11031 10:03:13.814065 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023 aarch64
11032 10:03:13.814590
11033 10:03:13.819766 The programs included with the Debian GNU/Linux system are free software;
11034 10:03:13.826830 the exact distribution terms for each program are described in the
11035 10:03:13.829982 individual files in /usr/share/doc/*/copyright.
11036 10:03:13.830431
11037 10:03:13.836369 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11038 10:03:13.836935 permitted by applicable law.
11039 10:03:13.892175 Matched prompt #10: / #
11041 10:03:13.892412 Setting prompt string to ['/ #']
11042 10:03:13.892508 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11044 10:03:13.892712 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11045 10:03:13.892800 start: 2.2.6 expect-shell-connection (timeout 00:03:39) [common]
11046 10:03:13.892873 Setting prompt string to ['/ #']
11047 10:03:13.892934 Forcing a shell prompt, looking for ['/ #']
11049 10:03:13.943257 / #
11050 10:03:13.943923 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11051 10:03:13.944364 Waiting using forced prompt support (timeout 00:02:30)
11052 10:03:13.950252
11053 10:03:13.951181 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11054 10:03:13.951733 start: 2.2.7 export-device-env (timeout 00:03:39) [common]
11056 10:03:14.053138 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10670640/extract-nfsrootfs-yyvetb3c'
11057 10:03:14.059743 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10670640/extract-nfsrootfs-yyvetb3c'
11059 10:03:14.161479 / # export NFS_SERVER_IP='192.168.201.1'
11060 10:03:14.168059 export NFS_SERVER_IP='192.168.201.1'
11061 10:03:14.169193 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11062 10:03:14.169754 end: 2.2 depthcharge-retry (duration 00:01:22) [common]
11063 10:03:14.170254 end: 2 depthcharge-action (duration 00:01:22) [common]
11064 10:03:14.170771 start: 3 lava-test-retry (timeout 00:01:00) [common]
11065 10:03:14.171238 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11066 10:03:14.171680 Using namespace: common
11068 10:03:14.272840 / # #
11069 10:03:14.273681 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11070 10:03:14.279861 #
11071 10:03:14.280737 Using /lava-10670640
11073 10:03:14.382369 / # export SHELL=/bin/sh
11074 10:03:14.389055 export SHELL=/bin/sh
11076 10:03:14.490868 / # . /lava-10670640/environment
11077 10:03:14.497106 . /lava-10670640/environment
11079 10:03:14.603690 / # /lava-10670640/bin/lava-test-runner /lava-10670640/0
11080 10:03:14.604375 Test shell timeout: 10s (minimum of the action and connection timeout)
11081 10:03:14.610401 /lava-10670640/bin/lava-test-runner /lava-10670640/0
11082 10:03:14.817786 + export TESTRUN_ID=0_dmesg
11083 10:03:14.820890 + cd /lava-10670640/0/tests/0_dmesg
11084 10:03:14.824146 + cat uuid
11085 10:03:14.830949 + UUID=10670640_1.<8>[ 27.822080] <LAVA_SIGNAL_STARTRUN 0_dmesg 10670640_1.6.2.3.1>
11086 10:03:14.831218 Received signal: <STARTRUN> 0_dmesg 10670640_1.6.2.3.1
11087 10:03:14.831301 Starting test lava.0_dmesg (10670640_1.6.2.3.1)
11088 10:03:14.831396 Skipping test definition patterns.
11089 10:03:14.834238 6.2.3.1
11090 10:03:14.834340 + set +x
11091 10:03:14.837581 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11092 10:03:14.935071 <8>[ 27.923840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11093 10:03:14.935804 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11095 10:03:15.003013 <8>[ 27.991411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11096 10:03:15.003725 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11098 10:03:15.064472 <8>[ 28.053327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11099 10:03:15.064769 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11101 10:03:15.068109 + set +x
11102 10:03:15.071152 <8>[ 28.062761] <LAVA_SIGNAL_ENDRUN 0_dmesg 10670640_1.6.2.3.1>
11103 10:03:15.071528 Received signal: <ENDRUN> 0_dmesg 10670640_1.6.2.3.1
11104 10:03:15.071674 Ending use of test pattern.
11105 10:03:15.071765 Ending test lava.0_dmesg (10670640_1.6.2.3.1), duration 0.24
11107 10:03:15.076175 <LAVA_TEST_RUNNER EXIT>
11108 10:03:15.076464 ok: lava_test_shell seems to have completed
11109 10:03:15.076621 alert: pass
crit: pass
emerg: pass
11110 10:03:15.076738 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11111 10:03:15.076853 end: 3 lava-test-retry (duration 00:00:01) [common]
11112 10:03:15.076962 start: 4 lava-test-retry (timeout 00:01:00) [common]
11113 10:03:15.077071 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11114 10:03:15.077156 Using namespace: common
11116 10:03:15.177824 / # #
11117 10:03:15.178471 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11118 10:03:15.179033 Using /lava-10670640
11120 10:03:15.280175 export SHELL=/bin/sh
11121 10:03:15.281075 #
11123 10:03:15.382978 / # export SHELL=/bin/sh. /lava-10670640/environment
11124 10:03:15.383763
11126 10:03:15.485463 / # . /lava-10670640/environment/lava-10670640/bin/lava-test-runner /lava-10670640/1
11127 10:03:15.486094 Test shell timeout: 10s (minimum of the action and connection timeout)
11128 10:03:15.486724
11129 10:03:15.491895 / # /lava-10670640/bin/lava-test-runner /lava-10670640/1
11130 10:03:15.601928 + export TESTRUN_ID=1_bootrr
11131 10:03:15.604178 + cd /lava-10670640/1/tests/1_bootrr
11132 10:03:15.607557 + cat uuid
11133 10:03:15.614545 Received signal: <STARTRUN> 1_bootrr 10670640_1.6.2.3.5
11134 10:03:15.614724 Starting test lava.1_bootrr (10670640_1.6.2.3.5)
11135 10:03:15.614846 Skipping test definition patterns.
11136 10:03:15.618180 + UUID=10670640_1.<8>[ 28.605665] <LAVA_SIGNAL_STARTRUN 1_bootrr 10670640_1.6.2.3.5>
11137 10:03:15.618333 6.2.3.5
11138 10:03:15.618435 + set +x
11139 10:03:15.631146 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10670640/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11140 10:03:15.631626 + cd /opt/bootrr/libexec/bootrr
11141 10:03:15.634093 + sh helpers/bootrr-auto
11142 10:03:15.690246 /lava-10670640/1/../bin/lava-test-case
11143 10:03:15.720407 <8>[ 28.709009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11144 10:03:15.721261 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11146 10:03:15.755685 /lava-10670640/1/../bin/lava-test-case
11147 10:03:15.776500 <8>[ 28.765852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11148 10:03:15.776808 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11150 10:03:15.797821 /lava-10670640/1/../bin/lava-test-case
11151 10:03:15.823270 <8>[ 28.812207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11152 10:03:15.823964 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11154 10:03:15.876887 /lava-10670640/1/../bin/lava-test-case
11155 10:03:15.905341 <8>[ 28.894099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11156 10:03:15.906138 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11158 10:03:15.945274 /lava-10670640/1/../bin/lava-test-case
11159 10:03:15.969574 <8>[ 28.958219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11160 10:03:15.970434 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11162 10:03:16.002879 /lava-10670640/1/../bin/lava-test-case
11163 10:03:16.027646 <8>[ 29.016381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11164 10:03:16.028329 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11166 10:03:16.059504 /lava-10670640/1/../bin/lava-test-case
11167 10:03:16.085310 <8>[ 29.073537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11168 10:03:16.086122 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11170 10:03:16.117619 /lava-10670640/1/../bin/lava-test-case
11171 10:03:16.145571 <8>[ 29.134226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11172 10:03:16.146307 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11174 10:03:16.164892 /lava-10670640/1/../bin/lava-test-case
11175 10:03:16.192231 <8>[ 29.180995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11176 10:03:16.192956 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11178 10:03:16.223502 /lava-10670640/1/../bin/lava-test-case
11179 10:03:16.249721 <8>[ 29.238724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11180 10:03:16.250492 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11182 10:03:16.276507 /lava-10670640/1/../bin/lava-test-case
11183 10:03:16.299652 <8>[ 29.289060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11184 10:03:16.299948 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11186 10:03:16.330662 /lava-10670640/1/../bin/lava-test-case
11187 10:03:16.352026 <8>[ 29.340822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11188 10:03:16.352724 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11190 10:03:16.380949 /lava-10670640/1/../bin/lava-test-case
11191 10:03:16.404967 <8>[ 29.393915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11192 10:03:16.405768 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11194 10:03:16.435755 /lava-10670640/1/../bin/lava-test-case
11195 10:03:16.462621 <8>[ 29.451186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11196 10:03:16.463482 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11198 10:03:16.492789 /lava-10670640/1/../bin/lava-test-case
11199 10:03:16.518683 <8>[ 29.506918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11200 10:03:16.519533 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11202 10:03:16.542161 /lava-10670640/1/../bin/lava-test-case
11203 10:03:16.568499 <8>[ 29.557410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11204 10:03:16.569345 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11206 10:03:16.612927 /lava-10670640/1/../bin/lava-test-case
11207 10:03:16.642304 <8>[ 29.630359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11208 10:03:16.643161 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11210 10:03:16.663664 /lava-10670640/1/../bin/lava-test-case
11211 10:03:16.691933 <8>[ 29.681007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11212 10:03:16.692891 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11214 10:03:16.729190 /lava-10670640/1/../bin/lava-test-case
11215 10:03:16.756091 <8>[ 29.745228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11216 10:03:16.756822 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11218 10:03:16.775798 /lava-10670640/1/../bin/lava-test-case
11219 10:03:16.798562 <8>[ 29.787499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11220 10:03:16.799521 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11222 10:03:16.831369 /lava-10670640/1/../bin/lava-test-case
11223 10:03:16.858367 <8>[ 29.847062] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11224 10:03:16.859326 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11226 10:03:16.878019 /lava-10670640/1/../bin/lava-test-case
11227 10:03:16.903253 <8>[ 29.891947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11228 10:03:16.904186 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11230 10:03:16.945236 /lava-10670640/1/../bin/lava-test-case
11231 10:03:16.973715 <8>[ 29.962419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11232 10:03:16.974706 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11234 10:03:16.995123 /lava-10670640/1/../bin/lava-test-case
11235 10:03:17.021383 <8>[ 30.010316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11236 10:03:17.022220 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11238 10:03:17.060060 /lava-10670640/1/../bin/lava-test-case
11239 10:03:17.089172 <8>[ 30.078046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11240 10:03:17.089995 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11242 10:03:17.121117 /lava-10670640/1/../bin/lava-test-case
11243 10:03:17.145255 <8>[ 30.134160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11244 10:03:17.145990 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11246 10:03:17.168327 /lava-10670640/1/../bin/lava-test-case
11247 10:03:17.200266 <8>[ 30.189316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11248 10:03:17.201157 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11250 10:03:17.234492 /lava-10670640/1/../bin/lava-test-case
11251 10:03:17.257274 <8>[ 30.246313] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11252 10:03:17.257988 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11254 10:03:17.284856 /lava-10670640/1/../bin/lava-test-case
11255 10:03:17.312616 <8>[ 30.301660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11256 10:03:17.313336 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11258 10:03:17.344983 /lava-10670640/1/../bin/lava-test-case
11259 10:03:17.371329 <8>[ 30.360025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11260 10:03:17.372082 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11262 10:03:17.404814 /lava-10670640/1/../bin/lava-test-case
11263 10:03:17.430443 <8>[ 30.419190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11264 10:03:17.431278 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11266 10:03:17.462756 /lava-10670640/1/../bin/lava-test-case
11267 10:03:17.487294 <8>[ 30.476335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11268 10:03:17.488142 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11270 10:03:17.522291 /lava-10670640/1/../bin/lava-test-case
11271 10:03:17.540587 <8>[ 30.530027] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11272 10:03:17.540944 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11274 10:03:17.559969 /lava-10670640/1/../bin/lava-test-case
11275 10:03:17.583825 <8>[ 30.572009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11276 10:03:17.584652 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11278 10:03:17.620257 /lava-10670640/1/../bin/lava-test-case
11279 10:03:17.645192 <8>[ 30.634414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11280 10:03:17.645983 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11282 10:03:17.677247 /lava-10670640/1/../bin/lava-test-case
11283 10:03:17.701384 <8>[ 30.690031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11284 10:03:17.702067 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11286 10:03:17.723384 /lava-10670640/1/../bin/lava-test-case
11287 10:03:17.753801 <8>[ 30.742860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11288 10:03:17.754490 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11290 10:03:17.785261 /lava-10670640/1/../bin/lava-test-case
11291 10:03:17.809180 <8>[ 30.798029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11292 10:03:17.810008 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11294 10:03:17.831391 /lava-10670640/1/../bin/lava-test-case
11295 10:03:17.860659 <8>[ 30.849479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11296 10:03:17.861491 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11298 10:03:17.893551 /lava-10670640/1/../bin/lava-test-case
11299 10:03:17.917191 <8>[ 30.906148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11300 10:03:17.917995 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11302 10:03:17.944666 /lava-10670640/1/../bin/lava-test-case
11303 10:03:17.970106 <8>[ 30.959114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11304 10:03:17.970998 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11306 10:03:18.008106 /lava-10670640/1/../bin/lava-test-case
11307 10:03:18.038157 <8>[ 31.026991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11308 10:03:18.038987 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11310 10:03:18.058226 /lava-10670640/1/../bin/lava-test-case
11311 10:03:18.083546 <8>[ 31.072649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11312 10:03:18.084362 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11314 10:03:18.123135 /lava-10670640/1/../bin/lava-test-case
11315 10:03:18.151643 <8>[ 31.140776] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11316 10:03:18.152324 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11318 10:03:18.172368 /lava-10670640/1/../bin/lava-test-case
11319 10:03:18.197613 <8>[ 31.186701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11320 10:03:18.198521 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11322 10:03:18.236314 /lava-10670640/1/../bin/lava-test-case
11323 10:03:18.263481 <8>[ 31.252402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11324 10:03:18.264169 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11326 10:03:18.289793 /lava-10670640/1/../bin/lava-test-case
11327 10:03:18.313382 <8>[ 31.301642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11328 10:03:18.314058 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11330 10:03:18.343702 /lava-10670640/1/../bin/lava-test-case
11331 10:03:18.370852 <8>[ 31.359310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11332 10:03:18.371551 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11334 10:03:18.393521 /lava-10670640/1/../bin/lava-test-case
11335 10:03:18.418129 <8>[ 31.407223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11336 10:03:18.418934 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11338 10:03:18.447564 /lava-10670640/1/../bin/lava-test-case
11339 10:03:18.470804 <8>[ 31.460324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11340 10:03:18.471172 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11342 10:03:18.501335 /lava-10670640/1/../bin/lava-test-case
11343 10:03:18.529546 <8>[ 31.518316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11344 10:03:18.530337 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11346 10:03:19.567654 /lava-10670640/1/../bin/lava-test-case
11347 10:03:19.596874 <8>[ 32.586441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11348 10:03:19.597207 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11350 10:03:20.628733 /lava-10670640/1/../bin/lava-test-case
11351 10:03:20.657759 <8>[ 33.646912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11352 10:03:20.658579 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11353 10:03:20.659045 Bad test result: blocked
11354 10:03:20.678157 /lava-10670640/1/../bin/lava-test-case
11355 10:03:20.703020 <8>[ 33.692551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11356 10:03:20.703810 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11358 10:03:20.735500 /lava-10670640/1/../bin/lava-test-case
11359 10:03:20.765316 <8>[ 33.754798] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11360 10:03:20.765986 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11362 10:03:20.801414 /lava-10670640/1/../bin/lava-test-case
11363 10:03:20.826038 <8>[ 33.814986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11364 10:03:20.826834 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11366 10:03:20.860722 /lava-10670640/1/../bin/lava-test-case
11367 10:03:20.884642 <8>[ 33.874310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11368 10:03:20.885013 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11370 10:03:20.912735 /lava-10670640/1/../bin/lava-test-case
11371 10:03:20.934131 <8>[ 33.923291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11372 10:03:20.934929 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11374 10:03:20.972165 /lava-10670640/1/../bin/lava-test-case
11375 10:03:20.996774 <8>[ 33.986406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11376 10:03:20.997128 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11378 10:03:21.016659 /lava-10670640/1/../bin/lava-test-case
11379 10:03:21.041971 <8>[ 34.031137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11380 10:03:21.042764 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11382 10:03:21.077709 /lava-10670640/1/../bin/lava-test-case
11383 10:03:21.106557 <8>[ 34.095491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11384 10:03:21.107402 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11386 10:03:21.136349 /lava-10670640/1/../bin/lava-test-case
11387 10:03:21.161903 <8>[ 34.151019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11388 10:03:21.162667 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11390 10:03:21.184423 /lava-10670640/1/../bin/lava-test-case
11391 10:03:21.213265 <8>[ 34.202635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11392 10:03:21.214068 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11394 10:03:21.246551 /lava-10670640/1/../bin/lava-test-case
11395 10:03:21.269769 <8>[ 34.258998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11396 10:03:21.270520 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11398 10:03:21.296688 /lava-10670640/1/../bin/lava-test-case
11399 10:03:21.318928 <8>[ 34.307693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11400 10:03:21.319733 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11402 10:03:21.351787 /lava-10670640/1/../bin/lava-test-case
11403 10:03:21.378632 <8>[ 34.368049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11404 10:03:21.379423 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11406 10:03:21.398768 /lava-10670640/1/../bin/lava-test-case
11407 10:03:21.423764 <8>[ 34.413208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11408 10:03:21.424605 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11410 10:03:21.459700 /lava-10670640/1/../bin/lava-test-case
11411 10:03:21.487445 <8>[ 34.476920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11412 10:03:21.488257 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11414 10:03:21.519230 /lava-10670640/1/../bin/lava-test-case
11415 10:03:21.541821 <8>[ 34.531142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11416 10:03:21.542666 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11418 10:03:21.574600 /lava-10670640/1/../bin/lava-test-case
11419 10:03:21.601379 <8>[ 34.590879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11420 10:03:21.601664 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11422 10:03:21.635338 /lava-10670640/1/../bin/lava-test-case
11423 10:03:21.664273 <8>[ 34.653691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11424 10:03:21.664993 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11426 10:03:21.692854 /lava-10670640/1/../bin/lava-test-case
11427 10:03:21.718805 <8>[ 34.708511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11428 10:03:21.719482 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11430 10:03:21.747131 /lava-10670640/1/../bin/lava-test-case
11431 10:03:21.772402 <8>[ 34.761742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11432 10:03:21.773248 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11434 10:03:21.800743 /lava-10670640/1/../bin/lava-test-case
11435 10:03:21.823840 <8>[ 34.813475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11436 10:03:21.824562 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11438 10:03:21.853856 /lava-10670640/1/../bin/lava-test-case
11439 10:03:21.878288 <8>[ 34.867913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11440 10:03:21.879093 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11442 10:03:21.910737 /lava-10670640/1/../bin/lava-test-case
11443 10:03:21.933724 <8>[ 34.923230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11444 10:03:21.934703 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11446 10:03:21.971097 /lava-10670640/1/../bin/lava-test-case
11447 10:03:21.997642 <8>[ 34.986759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11448 10:03:21.998408 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11450 10:03:22.028003 /lava-10670640/1/../bin/lava-test-case
11451 10:03:22.050840 <8>[ 35.040594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11452 10:03:22.051533 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11454 10:03:22.080279 /lava-10670640/1/../bin/lava-test-case
11455 10:03:22.099896 <8>[ 35.089974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11456 10:03:22.100304 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11458 10:03:22.126440 /lava-10670640/1/../bin/lava-test-case
11459 10:03:22.146574 <8>[ 35.135801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11460 10:03:22.147228 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11462 10:03:22.175272 /lava-10670640/1/../bin/lava-test-case
11463 10:03:22.197495 <8>[ 35.187148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11464 10:03:22.198218 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11466 10:03:22.227757 /lava-10670640/1/../bin/lava-test-case
11467 10:03:22.252504 <8>[ 35.242287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11468 10:03:22.253492 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11470 10:03:22.282886 /lava-10670640/1/../bin/lava-test-case
11471 10:03:22.307376 <8>[ 35.297206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11472 10:03:22.307788 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11474 10:03:22.341091 /lava-10670640/1/../bin/lava-test-case
11475 10:03:22.364432 <8>[ 35.354135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11476 10:03:22.365356 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11478 10:03:22.385510 /lava-10670640/1/../bin/lava-test-case
11479 10:03:22.412408 <8>[ 35.401792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11480 10:03:22.413142 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11482 10:03:22.441033 /lava-10670640/1/../bin/lava-test-case
11483 10:03:22.462976 <8>[ 35.452763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11484 10:03:22.463360 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11486 10:03:22.478882 /lava-10670640/1/../bin/lava-test-case
11487 10:03:22.503185 <8>[ 35.492378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11488 10:03:22.504068 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11490 10:03:22.541710 /lava-10670640/1/../bin/lava-test-case
11491 10:03:22.566060 <8>[ 35.555846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11492 10:03:22.566862 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11494 10:03:22.591888 /lava-10670640/1/../bin/lava-test-case
11495 10:03:22.617012 <8>[ 35.605843] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11496 10:03:22.617694 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11498 10:03:22.648711 /lava-10670640/1/../bin/lava-test-case
11499 10:03:22.675711 <8>[ 35.665186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11500 10:03:22.676571 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11502 10:03:22.696947 /lava-10670640/1/../bin/lava-test-case
11503 10:03:22.723149 <8>[ 35.711869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11504 10:03:22.723983 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11506 10:03:22.754230 /lava-10670640/1/../bin/lava-test-case
11507 10:03:22.777299 <8>[ 35.766870] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11508 10:03:22.778094 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11510 10:03:22.797517 /lava-10670640/1/../bin/lava-test-case
11511 10:03:22.822888 <8>[ 35.812547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11512 10:03:22.823569 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11514 10:03:22.853176 /lava-10670640/1/../bin/lava-test-case
11515 10:03:22.876739 <8>[ 35.866282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11516 10:03:22.877578 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11518 10:03:22.916250 /lava-10670640/1/../bin/lava-test-case
11519 10:03:22.941514 <8>[ 35.931052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11520 10:03:22.942309 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11522 10:03:22.964678 /lava-10670640/1/../bin/lava-test-case
11523 10:03:22.992327 <8>[ 35.981267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11524 10:03:22.993094 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11526 10:03:23.030465 /lava-10670640/1/../bin/lava-test-case
11527 10:03:23.058226 <8>[ 36.047868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11528 10:03:23.059047 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11530 10:03:23.080254 /lava-10670640/1/../bin/lava-test-case
11531 10:03:23.104716 <8>[ 36.094163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11532 10:03:23.105572 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11534 10:03:23.135644 /lava-10670640/1/../bin/lava-test-case
11535 10:03:23.165050 <8>[ 36.154384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11536 10:03:23.165746 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11538 10:03:23.184906 /lava-10670640/1/../bin/lava-test-case
11539 10:03:23.209700 <8>[ 36.199132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11540 10:03:23.210525 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11542 10:03:24.257583 /lava-10670640/1/../bin/lava-test-case
11543 10:03:24.292813 <8>[ 37.282831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11544 10:03:24.293577 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11546 10:03:24.313191 /lava-10670640/1/../bin/lava-test-case
11547 10:03:24.341322 <8>[ 37.331016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11548 10:03:24.342127 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11550 10:03:25.386640 /lava-10670640/1/../bin/lava-test-case
11551 10:03:25.423308 <8>[ 38.412671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11552 10:03:25.424113 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11554 10:03:25.446978 /lava-10670640/1/../bin/lava-test-case
11555 10:03:25.473385 <8>[ 38.463150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11556 10:03:25.474094 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11558 10:03:26.520492 /lava-10670640/1/../bin/lava-test-case
11559 10:03:26.546339 <8>[ 39.535959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11560 10:03:26.547130 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11562 10:03:26.566637 /lava-10670640/1/../bin/lava-test-case
11563 10:03:26.592694 <8>[ 39.582354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11564 10:03:26.593379 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11566 10:03:27.632860 /lava-10670640/1/../bin/lava-test-case
11567 10:03:27.659128 <8>[ 40.649089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11568 10:03:27.659915 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11570 10:03:27.680305 /lava-10670640/1/../bin/lava-test-case
11571 10:03:27.706997 <8>[ 40.697156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11572 10:03:27.707770 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11574 10:03:28.747782 /lava-10670640/1/../bin/lava-test-case
11575 10:03:28.778661 <8>[ 41.768925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11576 10:03:28.779435 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11578 10:03:28.801538 /lava-10670640/1/../bin/lava-test-case
11579 10:03:28.828376 <8>[ 41.818099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11580 10:03:28.829197 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11582 10:03:29.870316 /lava-10670640/1/../bin/lava-test-case
11583 10:03:29.894091 <8>[ 42.884872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11584 10:03:29.894394 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11586 10:03:29.911805 /lava-10670640/1/../bin/lava-test-case
11587 10:03:29.931284 <8>[ 42.921913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11588 10:03:29.931576 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11590 10:03:30.963905 /lava-10670640/1/../bin/lava-test-case
11591 10:03:30.990385 <8>[ 43.981312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11592 10:03:30.990720 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11594 10:03:31.009576 /lava-10670640/1/../bin/lava-test-case
11595 10:03:31.028905 <8>[ 44.019891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11596 10:03:31.029207 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11598 10:03:31.045583 /lava-10670640/1/../bin/lava-test-case
11599 10:03:31.063600 <8>[ 44.054516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11600 10:03:31.063893 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11602 10:03:32.101576 /lava-10670640/1/../bin/lava-test-case
11603 10:03:32.127932 <8>[ 45.119002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11604 10:03:32.128284 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11606 10:03:32.146169 /lava-10670640/1/../bin/lava-test-case
11607 10:03:32.167271 <8>[ 45.158134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11608 10:03:32.167580 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11610 10:03:32.195852 /lava-10670640/1/../bin/lava-test-case
11611 10:03:32.218362 <8>[ 45.209582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11612 10:03:32.218647 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11614 10:03:32.234628 /lava-10670640/1/../bin/lava-test-case
11615 10:03:32.254779 <8>[ 45.245745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11616 10:03:32.255062 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11618 10:03:32.282750 /lava-10670640/1/../bin/lava-test-case
11619 10:03:32.306142 <8>[ 45.297123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11620 10:03:32.306468 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11622 10:03:32.330221 /lava-10670640/1/../bin/lava-test-case
11623 10:03:32.349308 <8>[ 45.340600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11624 10:03:32.349603 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11626 10:03:32.382377 /lava-10670640/1/../bin/lava-test-case
11627 10:03:32.405645 <8>[ 45.396448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11628 10:03:32.405950 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11630 10:03:32.431959 /lava-10670640/1/../bin/lava-test-case
11631 10:03:32.451247 <8>[ 45.442112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11632 10:03:32.451556 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11634 10:03:32.479128 /lava-10670640/1/../bin/lava-test-case
11635 10:03:32.500301 <8>[ 45.491267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11636 10:03:32.500601 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11638 10:03:32.526926 /lava-10670640/1/../bin/lava-test-case
11639 10:03:32.549467 <8>[ 45.540842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11640 10:03:32.549761 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11642 10:03:32.569537 /lava-10670640/1/../bin/lava-test-case
11643 10:03:32.586725 <8>[ 45.578013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11644 10:03:32.587009 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11646 10:03:32.611867 /lava-10670640/1/../bin/lava-test-case
11647 10:03:32.631283 <8>[ 45.622393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11648 10:03:32.631584 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11650 10:03:32.650478 /lava-10670640/1/../bin/lava-test-case
11651 10:03:32.670693 <8>[ 45.662002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11652 10:03:32.670981 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11654 10:03:32.703124 /lava-10670640/1/../bin/lava-test-case
11655 10:03:32.720397 <8>[ 45.711571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11656 10:03:32.720722 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11658 10:03:32.742099 /lava-10670640/1/../bin/lava-test-case
11659 10:03:32.763650 <8>[ 45.754719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11660 10:03:32.763934 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11662 10:03:32.791374 /lava-10670640/1/../bin/lava-test-case
11663 10:03:32.812051 <8>[ 45.803104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11664 10:03:32.812338 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11666 10:03:32.830559 /lava-10670640/1/../bin/lava-test-case
11667 10:03:32.850817 <8>[ 45.841872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11668 10:03:32.851102 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11670 10:03:32.877574 /lava-10670640/1/../bin/lava-test-case
11671 10:03:32.897710 <8>[ 45.889011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11672 10:03:32.897990 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11674 10:03:32.915011 /lava-10670640/1/../bin/lava-test-case
11675 10:03:32.935446 <8>[ 45.926653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11676 10:03:32.935742 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11678 10:03:32.961501 /lava-10670640/1/../bin/lava-test-case
11679 10:03:32.978896 <8>[ 45.970154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11680 10:03:32.979182 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11682 10:03:32.995629 /lava-10670640/1/../bin/lava-test-case
11683 10:03:33.015853 <8>[ 46.006658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11684 10:03:33.016139 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11686 10:03:33.157714 <6>[ 46.154994] vpu: disabling
11687 10:03:33.160639 <6>[ 46.158045] vproc2: disabling
11688 10:03:33.163697 <6>[ 46.161319] vproc1: disabling
11689 10:03:33.167378 <6>[ 46.164584] vaud18: disabling
11690 10:03:33.174239 <6>[ 46.167994] vsram_others: disabling
11691 10:03:33.177049 <6>[ 46.171872] va09: disabling
11692 10:03:33.180412 <6>[ 46.174978] vsram_md: disabling
11693 10:03:33.183349 <6>[ 46.178463] Vgpu: disabling
11694 10:03:34.056249 /lava-10670640/1/../bin/lava-test-case
11695 10:03:34.076844 <8>[ 47.068035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11696 10:03:34.077135 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11698 10:03:35.108921 /lava-10670640/1/../bin/lava-test-case
11699 10:03:35.131634 <8>[ 48.123119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11700 10:03:35.131962 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11702 10:03:35.152172 /lava-10670640/1/../bin/lava-test-case
11703 10:03:35.175902 <8>[ 48.167138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11704 10:03:35.176196 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11706 10:03:35.201312 /lava-10670640/1/../bin/lava-test-case
11707 10:03:35.221298 <8>[ 48.212515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11708 10:03:35.221572 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11710 10:03:35.239443 /lava-10670640/1/../bin/lava-test-case
11711 10:03:35.263543 <8>[ 48.254598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11712 10:03:35.263839 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11714 10:03:35.289736 /lava-10670640/1/../bin/lava-test-case
11715 10:03:35.308488 <8>[ 48.299927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11716 10:03:35.308818 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11718 10:03:35.326718 /lava-10670640/1/../bin/lava-test-case
11719 10:03:35.344995 <8>[ 48.336341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11720 10:03:35.345289 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11722 10:03:35.370895 /lava-10670640/1/../bin/lava-test-case
11723 10:03:35.392879 <8>[ 48.384242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11724 10:03:35.393168 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11726 10:03:35.418918 /lava-10670640/1/../bin/lava-test-case
11727 10:03:35.436443 <8>[ 48.427564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11728 10:03:35.436746 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11730 10:03:35.461823 /lava-10670640/1/../bin/lava-test-case
11731 10:03:35.480324 <8>[ 48.471820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11732 10:03:35.480596 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11734 10:03:35.498054 /lava-10670640/1/../bin/lava-test-case
11735 10:03:35.515612 <8>[ 48.506512] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11736 10:03:35.515884 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11738 10:03:35.540055 /lava-10670640/1/../bin/lava-test-case
11739 10:03:35.560226 <8>[ 48.551533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11740 10:03:35.560505 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11742 10:03:35.577921 /lava-10670640/1/../bin/lava-test-case
11743 10:03:35.600736 <8>[ 48.592275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11744 10:03:35.601017 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11746 10:03:35.625212 /lava-10670640/1/../bin/lava-test-case
11747 10:03:35.646612 <8>[ 48.637690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11748 10:03:35.646922 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11750 10:03:35.663932 /lava-10670640/1/../bin/lava-test-case
11751 10:03:35.686580 <8>[ 48.678080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11752 10:03:35.686880 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11754 10:03:35.710580 /lava-10670640/1/../bin/lava-test-case
11755 10:03:35.727154 <8>[ 48.718692] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11756 10:03:35.727455 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11758 10:03:35.755801 /lava-10670640/1/../bin/lava-test-case
11759 10:03:35.774941 <8>[ 48.766313] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11760 10:03:35.775225 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11762 10:03:35.800484 /lava-10670640/1/../bin/lava-test-case
11763 10:03:35.819097 <8>[ 48.810654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11764 10:03:35.819402 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11766 10:03:35.838977 /lava-10670640/1/../bin/lava-test-case
11767 10:03:35.858997 <8>[ 48.850468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11768 10:03:35.859303 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11770 10:03:35.886354 /lava-10670640/1/../bin/lava-test-case
11771 10:03:35.905901 <8>[ 48.897130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11772 10:03:35.906164 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11774 10:03:35.923253 /lava-10670640/1/../bin/lava-test-case
11775 10:03:35.946843 <8>[ 48.937997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11776 10:03:35.947134 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11778 10:03:35.973320 /lava-10670640/1/../bin/lava-test-case
11779 10:03:35.995835 <8>[ 48.986388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11780 10:03:35.996116 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11782 10:03:37.019423 /lava-10670640/1/../bin/lava-test-case
11783 10:03:37.038320 <8>[ 50.029874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11784 10:03:37.038635 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11786 10:03:38.063797 /lava-10670640/1/../bin/lava-test-case
11787 10:03:38.087337 <8>[ 51.078916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11788 10:03:38.087640 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11789 10:03:38.087728 Bad test result: blocked
11790 10:03:38.106010 /lava-10670640/1/../bin/lava-test-case
11791 10:03:38.123653 <8>[ 51.115401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11792 10:03:38.123966 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11794 10:03:39.153930 /lava-10670640/1/../bin/lava-test-case
11795 10:03:39.174790 <8>[ 52.166858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11796 10:03:39.175061 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11798 10:03:39.192424 /lava-10670640/1/../bin/lava-test-case
11799 10:03:39.214802 <8>[ 52.206838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11800 10:03:39.215062 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11802 10:03:39.243252 /lava-10670640/1/../bin/lava-test-case
11803 10:03:39.264796 <8>[ 52.256472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11804 10:03:39.265081 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11806 10:03:39.288963 /lava-10670640/1/../bin/lava-test-case
11807 10:03:39.308838 <8>[ 52.300417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11808 10:03:39.309107 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11810 10:03:39.330562 /lava-10670640/1/../bin/lava-test-case
11811 10:03:39.351439 <8>[ 52.343186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11812 10:03:39.351718 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11814 10:03:39.378097 /lava-10670640/1/../bin/lava-test-case
11815 10:03:39.396742 <8>[ 52.388978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11816 10:03:39.397019 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11818 10:03:39.414912 /lava-10670640/1/../bin/lava-test-case
11819 10:03:39.435046 <8>[ 52.426908] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11820 10:03:39.435305 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11822 10:03:40.474862 /lava-10670640/1/../bin/lava-test-case
11823 10:03:40.497878 <8>[ 53.490207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11824 10:03:40.498186 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11826 10:03:40.513356 /lava-10670640/1/../bin/lava-test-case
11827 10:03:40.530437 <8>[ 53.522759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11828 10:03:40.530750 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11830 10:03:41.561786 /lava-10670640/1/../bin/lava-test-case
11831 10:03:41.586723 <8>[ 54.579157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11832 10:03:41.587085 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11834 10:03:41.605527 /lava-10670640/1/../bin/lava-test-case
11835 10:03:41.624909 <8>[ 54.617035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11836 10:03:41.625174 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11838 10:03:42.655800 /lava-10670640/1/../bin/lava-test-case
11839 10:03:42.680853 <8>[ 55.673274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11840 10:03:42.681173 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11842 10:03:42.701614 /lava-10670640/1/../bin/lava-test-case
11843 10:03:42.722803 <8>[ 55.715098] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11844 10:03:42.723086 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11846 10:03:43.760494 /lava-10670640/1/../bin/lava-test-case
11847 10:03:43.787295 <8>[ 56.779643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11848 10:03:43.787636 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11850 10:03:43.804788 /lava-10670640/1/../bin/lava-test-case
11851 10:03:43.825748 <8>[ 56.817818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11852 10:03:43.826524 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11854 10:03:43.855276 /lava-10670640/1/../bin/lava-test-case
11855 10:03:43.876834 <8>[ 56.869299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11856 10:03:43.877098 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11858 10:03:43.900170 /lava-10670640/1/../bin/lava-test-case
11859 10:03:43.918369 <8>[ 56.910782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11860 10:03:43.918628 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11862 10:03:43.935337 /lava-10670640/1/../bin/lava-test-case
11863 10:03:43.953188 <8>[ 56.945535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11864 10:03:43.953451 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11866 10:03:43.976231 /lava-10670640/1/../bin/lava-test-case
11867 10:03:43.996629 <8>[ 56.989121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11868 10:03:43.996895 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11870 10:03:44.012523 /lava-10670640/1/../bin/lava-test-case
11871 10:03:44.030593 <8>[ 57.022662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11872 10:03:44.030855 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11874 10:03:44.054283 /lava-10670640/1/../bin/lava-test-case
11875 10:03:44.074146 <8>[ 57.066462] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11876 10:03:44.074416 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11878 10:03:44.100138 /lava-10670640/1/../bin/lava-test-case
11879 10:03:44.118089 <8>[ 57.110767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11880 10:03:44.118372 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11882 10:03:45.154897 /lava-10670640/1/../bin/lava-test-case
11883 10:03:45.180470 <8>[ 58.173142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11884 10:03:45.180781 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11886 10:03:45.185198 + set +x
11887 10:03:45.188639 Received signal: <ENDRUN> 1_bootrr 10670640_1.6.2.3.5
11888 10:03:45.188726 Ending use of test pattern.
11889 10:03:45.188792 Ending test lava.1_bootrr (10670640_1.6.2.3.5), duration 29.57
11891 10:03:45.191587 <8>[ 58.184290] <LAVA_SIGNAL_ENDRUN 1_bootrr 10670640_1.6.2.3.5>
11892 10:03:45.195162 <LAVA_TEST_RUNNER EXIT>
11893 10:03:45.195411 ok: lava_test_shell seems to have completed
11894 10:03:45.196391 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11895 10:03:45.196572 end: 4.1 lava-test-shell (duration 00:00:30) [common]
11896 10:03:45.196660 end: 4 lava-test-retry (duration 00:00:30) [common]
11897 10:03:45.196743 start: 5 finalize (timeout 00:07:42) [common]
11898 10:03:45.196834 start: 5.1 power-off (timeout 00:00:30) [common]
11899 10:03:45.197009 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11900 10:03:45.273414 >> Command sent successfully.
11901 10:03:45.275730 Returned 0 in 0 seconds
11902 10:03:45.376091 end: 5.1 power-off (duration 00:00:00) [common]
11904 10:03:45.376429 start: 5.2 read-feedback (timeout 00:07:42) [common]
11905 10:03:45.376730 Listened to connection for namespace 'common' for up to 1s
11906 10:03:46.376647 Finalising connection for namespace 'common'
11907 10:03:46.376807 Disconnecting from shell: Finalise
11908 10:03:46.376888 / #
11909 10:03:46.477205 end: 5.2 read-feedback (duration 00:00:01) [common]
11910 10:03:46.477362 end: 5 finalize (duration 00:00:01) [common]
11911 10:03:46.477472 Cleaning after the job
11912 10:03:46.477564 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/ramdisk
11913 10:03:46.479570 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/kernel
11914 10:03:46.488703 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/dtb
11915 10:03:46.488949 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/nfsrootfs
11916 10:03:46.544476 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670640/tftp-deploy-knu8rojz/modules
11917 10:03:46.549774 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10670640
11918 10:03:46.854424 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10670640
11919 10:03:46.854654 Job finished correctly