Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 35
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
- Errors: 0
1 10:04:25.686864 lava-dispatcher, installed at version: 2023.05.1
2 10:04:25.687063 start: 0 validate
3 10:04:25.687197 Start time: 2023-06-10 10:04:25.687190+00:00 (UTC)
4 10:04:25.687316 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:04:25.687441 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 10:04:25.956016 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:04:25.956767 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:04:26.218353 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:04:26.219091 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:04:26.488480 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:04:26.489234 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:04:26.754568 validate duration: 1.07
14 10:04:26.754880 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:04:26.755046 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:04:26.755132 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:04:26.755259 Not decompressing ramdisk as can be used compressed.
18 10:04:26.755342 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230527.0/arm64/rootfs.cpio.gz
19 10:04:26.755404 saving as /var/lib/lava/dispatcher/tmp/10670697/tftp-deploy-artaceso/ramdisk/rootfs.cpio.gz
20 10:04:26.755464 total size: 34405874 (32MB)
21 10:04:26.756507 progress 0% (0MB)
22 10:04:26.765428 progress 5% (1MB)
23 10:04:26.773894 progress 10% (3MB)
24 10:04:26.782519 progress 15% (4MB)
25 10:04:26.790909 progress 20% (6MB)
26 10:04:26.799444 progress 25% (8MB)
27 10:04:26.807873 progress 30% (9MB)
28 10:04:26.816449 progress 35% (11MB)
29 10:04:26.824872 progress 40% (13MB)
30 10:04:26.833391 progress 45% (14MB)
31 10:04:26.841801 progress 50% (16MB)
32 10:04:26.850379 progress 55% (18MB)
33 10:04:26.858977 progress 60% (19MB)
34 10:04:26.867776 progress 65% (21MB)
35 10:04:26.876334 progress 70% (22MB)
36 10:04:26.884929 progress 75% (24MB)
37 10:04:26.893321 progress 80% (26MB)
38 10:04:26.901867 progress 85% (27MB)
39 10:04:26.910323 progress 90% (29MB)
40 10:04:26.918792 progress 95% (31MB)
41 10:04:26.927343 progress 100% (32MB)
42 10:04:26.927597 32MB downloaded in 0.17s (190.63MB/s)
43 10:04:26.927747 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:04:26.927982 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:04:26.928066 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:04:26.928149 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:04:26.928282 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:04:26.928370 saving as /var/lib/lava/dispatcher/tmp/10670697/tftp-deploy-artaceso/kernel/Image
50 10:04:26.928431 total size: 45746688 (43MB)
51 10:04:26.928506 No compression specified
52 10:04:26.929568 progress 0% (0MB)
53 10:04:26.940902 progress 5% (2MB)
54 10:04:26.952586 progress 10% (4MB)
55 10:04:26.964610 progress 15% (6MB)
56 10:04:26.976483 progress 20% (8MB)
57 10:04:26.988307 progress 25% (10MB)
58 10:04:26.999498 progress 30% (13MB)
59 10:04:27.010999 progress 35% (15MB)
60 10:04:27.022468 progress 40% (17MB)
61 10:04:27.033917 progress 45% (19MB)
62 10:04:27.045370 progress 50% (21MB)
63 10:04:27.056966 progress 55% (24MB)
64 10:04:27.068551 progress 60% (26MB)
65 10:04:27.080191 progress 65% (28MB)
66 10:04:27.091772 progress 70% (30MB)
67 10:04:27.103243 progress 75% (32MB)
68 10:04:27.114669 progress 80% (34MB)
69 10:04:27.126129 progress 85% (37MB)
70 10:04:27.137604 progress 90% (39MB)
71 10:04:27.148963 progress 95% (41MB)
72 10:04:27.160321 progress 100% (43MB)
73 10:04:27.160469 43MB downloaded in 0.23s (188.02MB/s)
74 10:04:27.160618 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:04:27.160891 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:04:27.161016 start: 1.3 download-retry (timeout 00:10:00) [common]
78 10:04:27.161124 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 10:04:27.161262 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:04:27.161333 saving as /var/lib/lava/dispatcher/tmp/10670697/tftp-deploy-artaceso/dtb/mt8192-asurada-spherion-r0.dtb
81 10:04:27.161395 total size: 46924 (0MB)
82 10:04:27.161455 No compression specified
83 10:04:27.162597 progress 69% (0MB)
84 10:04:27.162875 progress 100% (0MB)
85 10:04:27.163029 0MB downloaded in 0.00s (27.47MB/s)
86 10:04:27.163165 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:04:27.163387 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:04:27.163471 start: 1.4 download-retry (timeout 00:10:00) [common]
90 10:04:27.163552 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 10:04:27.163661 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:04:27.163729 saving as /var/lib/lava/dispatcher/tmp/10670697/tftp-deploy-artaceso/modules/modules.tar
93 10:04:27.163790 total size: 8540248 (8MB)
94 10:04:27.163850 Using unxz to decompress xz
95 10:04:27.167492 progress 0% (0MB)
96 10:04:27.189612 progress 5% (0MB)
97 10:04:27.214231 progress 10% (0MB)
98 10:04:27.238033 progress 15% (1MB)
99 10:04:27.263233 progress 20% (1MB)
100 10:04:27.287349 progress 25% (2MB)
101 10:04:27.310114 progress 30% (2MB)
102 10:04:27.335385 progress 35% (2MB)
103 10:04:27.360037 progress 40% (3MB)
104 10:04:27.383824 progress 45% (3MB)
105 10:04:27.410886 progress 50% (4MB)
106 10:04:27.435177 progress 55% (4MB)
107 10:04:27.460315 progress 60% (4MB)
108 10:04:27.485734 progress 65% (5MB)
109 10:04:27.510395 progress 70% (5MB)
110 10:04:27.534036 progress 75% (6MB)
111 10:04:27.556901 progress 80% (6MB)
112 10:04:27.580733 progress 85% (6MB)
113 10:04:27.609300 progress 90% (7MB)
114 10:04:27.634451 progress 95% (7MB)
115 10:04:27.659029 progress 100% (8MB)
116 10:04:27.664310 8MB downloaded in 0.50s (16.27MB/s)
117 10:04:27.664587 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:04:27.664891 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:04:27.664985 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:04:27.665081 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:04:27.665166 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:04:27.665253 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:04:27.665470 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o
125 10:04:27.665598 makedir: /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin
126 10:04:27.665701 makedir: /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/tests
127 10:04:27.665797 makedir: /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/results
128 10:04:27.665912 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-add-keys
129 10:04:27.666058 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-add-sources
130 10:04:27.666189 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-background-process-start
131 10:04:27.666318 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-background-process-stop
132 10:04:27.666442 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-common-functions
133 10:04:27.666563 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-echo-ipv4
134 10:04:27.666686 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-install-packages
135 10:04:27.666810 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-installed-packages
136 10:04:27.666933 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-os-build
137 10:04:27.667055 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-probe-channel
138 10:04:27.667177 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-probe-ip
139 10:04:27.667298 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-target-ip
140 10:04:27.667418 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-target-mac
141 10:04:27.667537 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-target-storage
142 10:04:27.667659 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-test-case
143 10:04:27.667780 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-test-event
144 10:04:27.667899 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-test-feedback
145 10:04:27.668020 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-test-raise
146 10:04:27.668143 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-test-reference
147 10:04:27.668264 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-test-runner
148 10:04:27.668384 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-test-set
149 10:04:27.668507 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-test-shell
150 10:04:27.668632 Updating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-install-packages (oe)
151 10:04:27.668778 Updating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/bin/lava-installed-packages (oe)
152 10:04:27.668946 Creating /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/environment
153 10:04:27.669047 LAVA metadata
154 10:04:27.669121 - LAVA_JOB_ID=10670697
155 10:04:27.669187 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:04:27.669293 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:04:27.669361 skipped lava-vland-overlay
158 10:04:27.669436 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:04:27.669515 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:04:27.669577 skipped lava-multinode-overlay
161 10:04:27.669651 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:04:27.669733 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:04:27.669809 Loading test definitions
164 10:04:27.669900 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 10:04:27.669972 Using /lava-10670697 at stage 0
166 10:04:27.670271 uuid=10670697_1.5.2.3.1 testdef=None
167 10:04:27.670359 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:04:27.670444 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 10:04:27.670946 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:04:27.671165 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 10:04:27.671762 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:04:27.671996 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 10:04:27.672581 runner path: /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/0/tests/0_cros-ec test_uuid 10670697_1.5.2.3.1
176 10:04:27.672731 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:04:27.672983 Creating lava-test-runner.conf files
179 10:04:27.673045 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10670697/lava-overlay-ls9_9k4o/lava-10670697/0 for stage 0
180 10:04:27.673132 - 0_cros-ec
181 10:04:27.673229 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 10:04:27.673316 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 10:04:27.679764 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 10:04:27.679870 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 10:04:27.679957 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 10:04:27.680041 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 10:04:27.680130 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 10:04:28.614808 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 10:04:28.615191 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 10:04:28.615312 extracting modules file /var/lib/lava/dispatcher/tmp/10670697/tftp-deploy-artaceso/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670697/extract-overlay-ramdisk-7m59rfle/ramdisk
191 10:04:28.834785 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 10:04:28.834950 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 10:04:28.835056 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670697/compress-overlay-sic3tvxj/overlay-1.5.2.4.tar.gz to ramdisk
194 10:04:28.835134 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670697/compress-overlay-sic3tvxj/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10670697/extract-overlay-ramdisk-7m59rfle/ramdisk
195 10:04:28.841829 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 10:04:28.841944 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 10:04:28.842037 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 10:04:28.842130 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 10:04:28.842211 Building ramdisk /var/lib/lava/dispatcher/tmp/10670697/extract-overlay-ramdisk-7m59rfle/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10670697/extract-overlay-ramdisk-7m59rfle/ramdisk
200 10:04:29.569166 >> 269475 blocks
201 10:04:34.247099 rename /var/lib/lava/dispatcher/tmp/10670697/extract-overlay-ramdisk-7m59rfle/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10670697/tftp-deploy-artaceso/ramdisk/ramdisk.cpio.gz
202 10:04:34.247538 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 10:04:34.247661 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 10:04:34.247760 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 10:04:34.247867 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10670697/tftp-deploy-artaceso/kernel/Image'
206 10:04:45.817774 Returned 0 in 11 seconds
207 10:04:45.918413 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10670697/tftp-deploy-artaceso/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10670697/tftp-deploy-artaceso/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10670697/tftp-deploy-artaceso/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10670697/tftp-deploy-artaceso/kernel/image.itb
208 10:04:46.590941 output: FIT description: Kernel Image image with one or more FDT blobs
209 10:04:46.591310 output: Created: Sat Jun 10 11:04:46 2023
210 10:04:46.591387 output: Image 0 (kernel-1)
211 10:04:46.591452 output: Description:
212 10:04:46.591518 output: Created: Sat Jun 10 11:04:46 2023
213 10:04:46.591581 output: Type: Kernel Image
214 10:04:46.591642 output: Compression: lzma compressed
215 10:04:46.591702 output: Data Size: 10087317 Bytes = 9850.90 KiB = 9.62 MiB
216 10:04:46.591761 output: Architecture: AArch64
217 10:04:46.591817 output: OS: Linux
218 10:04:46.591870 output: Load Address: 0x00000000
219 10:04:46.591925 output: Entry Point: 0x00000000
220 10:04:46.591981 output: Hash algo: crc32
221 10:04:46.592036 output: Hash value: c9e456fd
222 10:04:46.592089 output: Image 1 (fdt-1)
223 10:04:46.592142 output: Description: mt8192-asurada-spherion-r0
224 10:04:46.592195 output: Created: Sat Jun 10 11:04:46 2023
225 10:04:46.592248 output: Type: Flat Device Tree
226 10:04:46.592301 output: Compression: uncompressed
227 10:04:46.592354 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 10:04:46.592407 output: Architecture: AArch64
229 10:04:46.592459 output: Hash algo: crc32
230 10:04:46.592511 output: Hash value: 1df858fa
231 10:04:46.592563 output: Image 2 (ramdisk-1)
232 10:04:46.592616 output: Description: unavailable
233 10:04:46.592668 output: Created: Sat Jun 10 11:04:46 2023
234 10:04:46.592721 output: Type: RAMDisk Image
235 10:04:46.592773 output: Compression: Unknown Compression
236 10:04:46.592859 output: Data Size: 47388497 Bytes = 46277.83 KiB = 45.19 MiB
237 10:04:46.592927 output: Architecture: AArch64
238 10:04:46.592981 output: OS: Linux
239 10:04:46.593034 output: Load Address: unavailable
240 10:04:46.593087 output: Entry Point: unavailable
241 10:04:46.593140 output: Hash algo: crc32
242 10:04:46.593193 output: Hash value: f0e4e6ac
243 10:04:46.593246 output: Default Configuration: 'conf-1'
244 10:04:46.593299 output: Configuration 0 (conf-1)
245 10:04:46.593352 output: Description: mt8192-asurada-spherion-r0
246 10:04:46.593405 output: Kernel: kernel-1
247 10:04:46.593473 output: Init Ramdisk: ramdisk-1
248 10:04:46.593527 output: FDT: fdt-1
249 10:04:46.593580 output: Loadables: kernel-1
250 10:04:46.593633 output:
251 10:04:46.593822 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 10:04:46.593924 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 10:04:46.594033 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 10:04:46.594130 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 10:04:46.594209 No LXC device requested
256 10:04:46.594294 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 10:04:46.594380 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 10:04:46.594457 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 10:04:46.594525 Checking files for TFTP limit of 4294967296 bytes.
260 10:04:46.595014 end: 1 tftp-deploy (duration 00:00:20) [common]
261 10:04:46.595117 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 10:04:46.595209 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 10:04:46.595333 substitutions:
264 10:04:46.595411 - {DTB}: 10670697/tftp-deploy-artaceso/dtb/mt8192-asurada-spherion-r0.dtb
265 10:04:46.595500 - {INITRD}: 10670697/tftp-deploy-artaceso/ramdisk/ramdisk.cpio.gz
266 10:04:46.595576 - {KERNEL}: 10670697/tftp-deploy-artaceso/kernel/Image
267 10:04:46.595637 - {LAVA_MAC}: None
268 10:04:46.595695 - {PRESEED_CONFIG}: None
269 10:04:46.595752 - {PRESEED_LOCAL}: None
270 10:04:46.595808 - {RAMDISK}: 10670697/tftp-deploy-artaceso/ramdisk/ramdisk.cpio.gz
271 10:04:46.595864 - {ROOT_PART}: None
272 10:04:46.595920 - {ROOT}: None
273 10:04:46.595975 - {SERVER_IP}: 192.168.201.1
274 10:04:46.596029 - {TEE}: None
275 10:04:46.596083 Parsed boot commands:
276 10:04:46.596136 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 10:04:46.596312 Parsed boot commands: tftpboot 192.168.201.1 10670697/tftp-deploy-artaceso/kernel/image.itb 10670697/tftp-deploy-artaceso/kernel/cmdline
278 10:04:46.596400 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 10:04:46.596486 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 10:04:46.596575 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 10:04:46.596662 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 10:04:46.596733 Not connected, no need to disconnect.
283 10:04:46.596814 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 10:04:46.596933 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 10:04:46.597001 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
286 10:04:46.600377 Setting prompt string to ['lava-test: # ']
287 10:04:46.600709 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 10:04:46.600846 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 10:04:46.600958 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 10:04:46.601050 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 10:04:46.601248 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 10:04:51.736157 >> Command sent successfully.
293 10:04:51.738507 Returned 0 in 5 seconds
294 10:04:51.838889 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 10:04:51.839470 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 10:04:51.839575 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 10:04:51.839671 Setting prompt string to 'Starting depthcharge on Spherion...'
299 10:04:51.839741 Changing prompt to 'Starting depthcharge on Spherion...'
300 10:04:51.839813 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 10:04:51.840072 [Enter `^Ec?' for help]
302 10:04:52.015650
303 10:04:52.015801
304 10:04:52.015875 F0: 102B 0000
305 10:04:52.015940
306 10:04:52.016001 F3: 1001 0000 [0200]
307 10:04:52.019104
308 10:04:52.019189 F3: 1001 0000
309 10:04:52.019258
310 10:04:52.019322 F7: 102D 0000
311 10:04:52.019383
312 10:04:52.022711 F1: 0000 0000
313 10:04:52.022796
314 10:04:52.022864 V0: 0000 0000 [0001]
315 10:04:52.022927
316 10:04:52.026054 00: 0007 8000
317 10:04:52.026143
318 10:04:52.026210 01: 0000 0000
319 10:04:52.026275
320 10:04:52.029307 BP: 0C00 0209 [0000]
321 10:04:52.029392
322 10:04:52.029459 G0: 1182 0000
323 10:04:52.029520
324 10:04:52.032613 EC: 0000 0021 [4000]
325 10:04:52.032698
326 10:04:52.032765 S7: 0000 0000 [0000]
327 10:04:52.032844
328 10:04:52.036659 CC: 0000 0000 [0001]
329 10:04:52.036743
330 10:04:52.036816 T0: 0000 0040 [010F]
331 10:04:52.036884
332 10:04:52.036945 Jump to BL
333 10:04:52.037046
334 10:04:52.063647
335 10:04:52.063734
336 10:04:52.063802
337 10:04:52.070941 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 10:04:52.074526 ARM64: Exception handlers installed.
339 10:04:52.077968 ARM64: Testing exception
340 10:04:52.078054 ARM64: Done test exception
341 10:04:52.088611 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 10:04:52.098692 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 10:04:52.105599 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 10:04:52.115471 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 10:04:52.122529 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 10:04:52.128789 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 10:04:52.140340 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 10:04:52.146657 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 10:04:52.165686 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 10:04:52.169381 WDT: Last reset was cold boot
351 10:04:52.172539 SPI1(PAD0) initialized at 2873684 Hz
352 10:04:52.175952 SPI5(PAD0) initialized at 992727 Hz
353 10:04:52.179318 VBOOT: Loading verstage.
354 10:04:52.185661 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 10:04:52.189703 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 10:04:52.192683 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 10:04:52.196214 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 10:04:52.203691 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 10:04:52.209831 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 10:04:52.221197 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 10:04:52.221290
362 10:04:52.221357
363 10:04:52.231320 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 10:04:52.234642 ARM64: Exception handlers installed.
365 10:04:52.238062 ARM64: Testing exception
366 10:04:52.238146 ARM64: Done test exception
367 10:04:52.244612 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 10:04:52.248091 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 10:04:52.262141 Probing TPM: . done!
370 10:04:52.262231 TPM ready after 0 ms
371 10:04:52.268954 Connected to device vid:did:rid of 1ae0:0028:00
372 10:04:52.276454 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 10:04:52.335330 Initialized TPM device CR50 revision 0
374 10:04:52.346921 tlcl_send_startup: Startup return code is 0
375 10:04:52.347027 TPM: setup succeeded
376 10:04:52.358616 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 10:04:52.367310 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 10:04:52.381654 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 10:04:52.389072 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 10:04:52.392816 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 10:04:52.396638 in-header: 03 07 00 00 08 00 00 00
382 10:04:52.400123 in-data: aa e4 47 04 13 02 00 00
383 10:04:52.400210 Chrome EC: UHEPI supported
384 10:04:52.407453 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 10:04:52.412137 in-header: 03 95 00 00 08 00 00 00
386 10:04:52.415282 in-data: 18 20 20 08 00 00 00 00
387 10:04:52.415367 Phase 1
388 10:04:52.419590 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 10:04:52.426473 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 10:04:52.434612 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 10:04:52.434705 Recovery requested (1009000e)
392 10:04:52.446705 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 10:04:52.450443 tlcl_extend: response is 0
394 10:04:52.459929 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 10:04:52.465509 tlcl_extend: response is 0
396 10:04:52.471841 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 10:04:52.491778 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 10:04:52.498484 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 10:04:52.498615
400 10:04:52.498685
401 10:04:52.508715 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 10:04:52.511880 ARM64: Exception handlers installed.
403 10:04:52.515353 ARM64: Testing exception
404 10:04:52.515438 ARM64: Done test exception
405 10:04:52.537366 pmic_efuse_setting: Set efuses in 11 msecs
406 10:04:52.541203 pmwrap_interface_init: Select PMIF_VLD_RDY
407 10:04:52.547614 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 10:04:52.551089 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 10:04:52.554756 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 10:04:52.562111 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 10:04:52.565722 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 10:04:52.569649 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 10:04:52.577433 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 10:04:52.581015 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 10:04:52.584549 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 10:04:52.588140 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 10:04:52.596432 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 10:04:52.599988 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 10:04:52.603880 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 10:04:52.611706 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 10:04:52.615195 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 10:04:52.622477 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 10:04:52.626668 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 10:04:52.633906 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 10:04:52.637916 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 10:04:52.645228 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 10:04:52.649433 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 10:04:52.656652 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 10:04:52.660042 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 10:04:52.664176 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 10:04:52.671168 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 10:04:52.678745 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 10:04:52.682363 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 10:04:52.685986 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 10:04:52.693651 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 10:04:52.697152 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 10:04:52.700936 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 10:04:52.708424 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 10:04:52.711991 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 10:04:52.715586 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 10:04:52.723177 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 10:04:52.726857 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 10:04:52.730742 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 10:04:52.738365 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 10:04:52.742170 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 10:04:52.745758 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 10:04:52.749361 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 10:04:52.752663 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 10:04:52.760080 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 10:04:52.763747 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 10:04:52.768709 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 10:04:52.771696 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 10:04:52.774972 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 10:04:52.779273 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 10:04:52.782760 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 10:04:52.790083 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 10:04:52.793873 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 10:04:52.801299 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 10:04:52.808993 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 10:04:52.812221 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 10:04:52.823619 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 10:04:52.831098 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 10:04:52.834856 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 10:04:52.838325 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 10:04:52.842436 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 10:04:52.851214 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1a
467 10:04:52.854432 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 10:04:52.859704 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 10:04:52.866220 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 10:04:52.875063 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 10:04:52.884254 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 10:04:52.894513 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 10:04:52.903862 [RTC]rtc_get_frequency_meter,154: input=17, output=804
474 10:04:52.912705 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 10:04:52.922519 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 10:04:52.933242 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 10:04:52.937081 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 10:04:52.940902 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 10:04:52.945186 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 10:04:52.948406 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 10:04:52.955709 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 10:04:52.959684 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 10:04:52.959771 ADC[4]: Raw value=905834 ID=7
484 10:04:52.963771 ADC[3]: Raw value=213441 ID=1
485 10:04:52.963895 RAM Code: 0x71
486 10:04:52.971269 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 10:04:52.974808 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 10:04:52.983034 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 10:04:52.990440 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 10:04:52.993827 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 10:04:52.997523 in-header: 03 07 00 00 08 00 00 00
492 10:04:53.001660 in-data: aa e4 47 04 13 02 00 00
493 10:04:53.001746 Chrome EC: UHEPI supported
494 10:04:53.008168 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 10:04:53.012243 in-header: 03 95 00 00 08 00 00 00
496 10:04:53.015825 in-data: 18 20 20 08 00 00 00 00
497 10:04:53.019456 MRC: failed to locate region type 0.
498 10:04:53.027358 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 10:04:53.030982 DRAM-K: Running full calibration
500 10:04:53.034688 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 10:04:53.038222 header.status = 0x0
502 10:04:53.041926 header.version = 0x6 (expected: 0x6)
503 10:04:53.045112 header.size = 0xd00 (expected: 0xd00)
504 10:04:53.045197 header.flags = 0x0
505 10:04:53.052532 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 10:04:53.070119 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 10:04:53.077707 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 10:04:53.081078 dram_init: ddr_geometry: 2
509 10:04:53.081161 [EMI] MDL number = 2
510 10:04:53.084921 [EMI] Get MDL freq = 0
511 10:04:53.085004 dram_init: ddr_type: 0
512 10:04:53.088699 is_discrete_lpddr4: 1
513 10:04:53.092529 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 10:04:53.092612
515 10:04:53.092697
516 10:04:53.092761 [Bian_co] ETT version 0.0.0.1
517 10:04:53.100354 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 10:04:53.100439
519 10:04:53.103805 dramc_set_vcore_voltage set vcore to 650000
520 10:04:53.103888 Read voltage for 800, 4
521 10:04:53.107402 Vio18 = 0
522 10:04:53.107485 Vcore = 650000
523 10:04:53.107551 Vdram = 0
524 10:04:53.107615 Vddq = 0
525 10:04:53.110712 Vmddr = 0
526 10:04:53.110795 dram_init: config_dvfs: 1
527 10:04:53.118809 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 10:04:53.122266 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 10:04:53.126237 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 10:04:53.130101 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 10:04:53.133901 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 10:04:53.137493 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 10:04:53.140795 MEM_TYPE=3, freq_sel=18
534 10:04:53.143928 sv_algorithm_assistance_LP4_1600
535 10:04:53.147743 ============ PULL DRAM RESETB DOWN ============
536 10:04:53.150907 ========== PULL DRAM RESETB DOWN end =========
537 10:04:53.154842 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 10:04:53.157513 ===================================
539 10:04:53.161515 LPDDR4 DRAM CONFIGURATION
540 10:04:53.165122 ===================================
541 10:04:53.168390 EX_ROW_EN[0] = 0x0
542 10:04:53.168473 EX_ROW_EN[1] = 0x0
543 10:04:53.172356 LP4Y_EN = 0x0
544 10:04:53.172439 WORK_FSP = 0x0
545 10:04:53.172504 WL = 0x2
546 10:04:53.176005 RL = 0x2
547 10:04:53.176088 BL = 0x2
548 10:04:53.179585 RPST = 0x0
549 10:04:53.179668 RD_PRE = 0x0
550 10:04:53.182928 WR_PRE = 0x1
551 10:04:53.183011 WR_PST = 0x0
552 10:04:53.186673 DBI_WR = 0x0
553 10:04:53.186756 DBI_RD = 0x0
554 10:04:53.189773 OTF = 0x1
555 10:04:53.193031 ===================================
556 10:04:53.196608 ===================================
557 10:04:53.196691 ANA top config
558 10:04:53.200106 ===================================
559 10:04:53.203157 DLL_ASYNC_EN = 0
560 10:04:53.206490 ALL_SLAVE_EN = 1
561 10:04:53.210053 NEW_RANK_MODE = 1
562 10:04:53.210140 DLL_IDLE_MODE = 1
563 10:04:53.213352 LP45_APHY_COMB_EN = 1
564 10:04:53.217040 TX_ODT_DIS = 1
565 10:04:53.217123 NEW_8X_MODE = 1
566 10:04:53.221154 ===================================
567 10:04:53.224479 ===================================
568 10:04:53.227559 data_rate = 1600
569 10:04:53.231097 CKR = 1
570 10:04:53.234139 DQ_P2S_RATIO = 8
571 10:04:53.237615 ===================================
572 10:04:53.241332 CA_P2S_RATIO = 8
573 10:04:53.241415 DQ_CA_OPEN = 0
574 10:04:53.244114 DQ_SEMI_OPEN = 0
575 10:04:53.247729 CA_SEMI_OPEN = 0
576 10:04:53.251180 CA_FULL_RATE = 0
577 10:04:53.254173 DQ_CKDIV4_EN = 1
578 10:04:53.257627 CA_CKDIV4_EN = 1
579 10:04:53.257710 CA_PREDIV_EN = 0
580 10:04:53.261156 PH8_DLY = 0
581 10:04:53.264052 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 10:04:53.267468 DQ_AAMCK_DIV = 4
583 10:04:53.270686 CA_AAMCK_DIV = 4
584 10:04:53.274339 CA_ADMCK_DIV = 4
585 10:04:53.274423 DQ_TRACK_CA_EN = 0
586 10:04:53.277630 CA_PICK = 800
587 10:04:53.280989 CA_MCKIO = 800
588 10:04:53.285342 MCKIO_SEMI = 0
589 10:04:53.288662 PLL_FREQ = 3068
590 10:04:53.288746 DQ_UI_PI_RATIO = 32
591 10:04:53.292236 CA_UI_PI_RATIO = 0
592 10:04:53.296458 ===================================
593 10:04:53.299621 ===================================
594 10:04:53.303562 memory_type:LPDDR4
595 10:04:53.303647 GP_NUM : 10
596 10:04:53.307313 SRAM_EN : 1
597 10:04:53.307398 MD32_EN : 0
598 10:04:53.310449 ===================================
599 10:04:53.314534 [ANA_INIT] >>>>>>>>>>>>>>
600 10:04:53.318485 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 10:04:53.318577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 10:04:53.322289 ===================================
603 10:04:53.324978 data_rate = 1600,PCW = 0X7600
604 10:04:53.328749 ===================================
605 10:04:53.331776 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 10:04:53.338474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 10:04:53.345449 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 10:04:53.348584 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 10:04:53.352164 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 10:04:53.355274 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 10:04:53.359266 [ANA_INIT] flow start
612 10:04:53.359351 [ANA_INIT] PLL >>>>>>>>
613 10:04:53.361861 [ANA_INIT] PLL <<<<<<<<
614 10:04:53.365083 [ANA_INIT] MIDPI >>>>>>>>
615 10:04:53.365168 [ANA_INIT] MIDPI <<<<<<<<
616 10:04:53.368487 [ANA_INIT] DLL >>>>>>>>
617 10:04:53.372553 [ANA_INIT] flow end
618 10:04:53.375126 ============ LP4 DIFF to SE enter ============
619 10:04:53.378641 ============ LP4 DIFF to SE exit ============
620 10:04:53.382528 [ANA_INIT] <<<<<<<<<<<<<
621 10:04:53.385148 [Flow] Enable top DCM control >>>>>
622 10:04:53.388688 [Flow] Enable top DCM control <<<<<
623 10:04:53.392291 Enable DLL master slave shuffle
624 10:04:53.395511 ==============================================================
625 10:04:53.398671 Gating Mode config
626 10:04:53.402228 ==============================================================
627 10:04:53.405463 Config description:
628 10:04:53.415835 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 10:04:53.422411 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 10:04:53.425327 SELPH_MODE 0: By rank 1: By Phase
631 10:04:53.432108 ==============================================================
632 10:04:53.435510 GAT_TRACK_EN = 1
633 10:04:53.438732 RX_GATING_MODE = 2
634 10:04:53.441965 RX_GATING_TRACK_MODE = 2
635 10:04:53.445937 SELPH_MODE = 1
636 10:04:53.446022 PICG_EARLY_EN = 1
637 10:04:53.449067 VALID_LAT_VALUE = 1
638 10:04:53.455621 ==============================================================
639 10:04:53.458834 Enter into Gating configuration >>>>
640 10:04:53.462184 Exit from Gating configuration <<<<
641 10:04:53.465821 Enter into DVFS_PRE_config >>>>>
642 10:04:53.476378 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 10:04:53.478853 Exit from DVFS_PRE_config <<<<<
644 10:04:53.482313 Enter into PICG configuration >>>>
645 10:04:53.485986 Exit from PICG configuration <<<<
646 10:04:53.488847 [RX_INPUT] configuration >>>>>
647 10:04:53.492378 [RX_INPUT] configuration <<<<<
648 10:04:53.495729 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 10:04:53.502350 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 10:04:53.509387 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 10:04:53.515523 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 10:04:53.518869 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 10:04:53.525622 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 10:04:53.529181 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 10:04:53.535697 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 10:04:53.539056 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 10:04:53.542159 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 10:04:53.546054 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 10:04:53.552694 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 10:04:53.555689 ===================================
661 10:04:53.555774 LPDDR4 DRAM CONFIGURATION
662 10:04:53.558933 ===================================
663 10:04:53.562499 EX_ROW_EN[0] = 0x0
664 10:04:53.565948 EX_ROW_EN[1] = 0x0
665 10:04:53.566032 LP4Y_EN = 0x0
666 10:04:53.569036 WORK_FSP = 0x0
667 10:04:53.569120 WL = 0x2
668 10:04:53.572667 RL = 0x2
669 10:04:53.572750 BL = 0x2
670 10:04:53.575921 RPST = 0x0
671 10:04:53.576005 RD_PRE = 0x0
672 10:04:53.579393 WR_PRE = 0x1
673 10:04:53.579476 WR_PST = 0x0
674 10:04:53.582445 DBI_WR = 0x0
675 10:04:53.582529 DBI_RD = 0x0
676 10:04:53.585903 OTF = 0x1
677 10:04:53.589792 ===================================
678 10:04:53.592697 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 10:04:53.595785 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 10:04:53.602473 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 10:04:53.605830 ===================================
682 10:04:53.605915 LPDDR4 DRAM CONFIGURATION
683 10:04:53.609391 ===================================
684 10:04:53.612552 EX_ROW_EN[0] = 0x10
685 10:04:53.612637 EX_ROW_EN[1] = 0x0
686 10:04:53.616126 LP4Y_EN = 0x0
687 10:04:53.616210 WORK_FSP = 0x0
688 10:04:53.619357 WL = 0x2
689 10:04:53.619441 RL = 0x2
690 10:04:53.622632 BL = 0x2
691 10:04:53.625973 RPST = 0x0
692 10:04:53.626058 RD_PRE = 0x0
693 10:04:53.629319 WR_PRE = 0x1
694 10:04:53.629403 WR_PST = 0x0
695 10:04:53.632533 DBI_WR = 0x0
696 10:04:53.632650 DBI_RD = 0x0
697 10:04:53.635918 OTF = 0x1
698 10:04:53.639538 ===================================
699 10:04:53.643143 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 10:04:53.647884 nWR fixed to 40
701 10:04:53.651456 [ModeRegInit_LP4] CH0 RK0
702 10:04:53.651540 [ModeRegInit_LP4] CH0 RK1
703 10:04:53.655223 [ModeRegInit_LP4] CH1 RK0
704 10:04:53.657846 [ModeRegInit_LP4] CH1 RK1
705 10:04:53.657930 match AC timing 13
706 10:04:53.664620 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 10:04:53.668271 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 10:04:53.671403 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 10:04:53.678277 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 10:04:53.681235 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 10:04:53.681319 [EMI DOE] emi_dcm 0
712 10:04:53.688488 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 10:04:53.688572 ==
714 10:04:53.691615 Dram Type= 6, Freq= 0, CH_0, rank 0
715 10:04:53.694886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 10:04:53.694970 ==
717 10:04:53.701506 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 10:04:53.707980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 10:04:53.715805 [CA 0] Center 36 (6~67) winsize 62
720 10:04:53.719017 [CA 1] Center 36 (6~67) winsize 62
721 10:04:53.721956 [CA 2] Center 34 (4~65) winsize 62
722 10:04:53.725204 [CA 3] Center 34 (4~64) winsize 61
723 10:04:53.729066 [CA 4] Center 33 (2~64) winsize 63
724 10:04:53.732025 [CA 5] Center 32 (2~62) winsize 61
725 10:04:53.732109
726 10:04:53.735582 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 10:04:53.735666
728 10:04:53.738706 [CATrainingPosCal] consider 1 rank data
729 10:04:53.742101 u2DelayCellTimex100 = 270/100 ps
730 10:04:53.745660 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 10:04:53.748842 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 10:04:53.755311 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 10:04:53.758942 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
734 10:04:53.762063 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
735 10:04:53.765658 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 10:04:53.765742
737 10:04:53.769014 CA PerBit enable=1, Macro0, CA PI delay=32
738 10:04:53.769097
739 10:04:53.772352 [CBTSetCACLKResult] CA Dly = 32
740 10:04:53.772435 CS Dly: 4 (0~35)
741 10:04:53.772502 ==
742 10:04:53.775686 Dram Type= 6, Freq= 0, CH_0, rank 1
743 10:04:53.782418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 10:04:53.782502 ==
745 10:04:53.786158 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 10:04:53.792330 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 10:04:53.801826 [CA 0] Center 36 (6~67) winsize 62
748 10:04:53.805369 [CA 1] Center 36 (6~67) winsize 62
749 10:04:53.808117 [CA 2] Center 34 (3~65) winsize 63
750 10:04:53.811539 [CA 3] Center 34 (4~65) winsize 62
751 10:04:53.814974 [CA 4] Center 33 (3~63) winsize 61
752 10:04:53.818488 [CA 5] Center 32 (2~63) winsize 62
753 10:04:53.818572
754 10:04:53.821955 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 10:04:53.822041
756 10:04:53.824987 [CATrainingPosCal] consider 2 rank data
757 10:04:53.828589 u2DelayCellTimex100 = 270/100 ps
758 10:04:53.832146 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 10:04:53.834974 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 10:04:53.841691 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 10:04:53.845051 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 10:04:53.848822 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 10:04:53.852106 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 10:04:53.852190
765 10:04:53.855310 CA PerBit enable=1, Macro0, CA PI delay=32
766 10:04:53.855393
767 10:04:53.858419 [CBTSetCACLKResult] CA Dly = 32
768 10:04:53.858502 CS Dly: 5 (0~37)
769 10:04:53.858569
770 10:04:53.862456 ----->DramcWriteLeveling(PI) begin...
771 10:04:53.862541 ==
772 10:04:53.866236 Dram Type= 6, Freq= 0, CH_0, rank 0
773 10:04:53.869754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 10:04:53.869838 ==
775 10:04:53.873737 Write leveling (Byte 0): 33 => 33
776 10:04:53.877100 Write leveling (Byte 1): 31 => 31
777 10:04:53.880616 DramcWriteLeveling(PI) end<-----
778 10:04:53.880699
779 10:04:53.880766 ==
780 10:04:53.884245 Dram Type= 6, Freq= 0, CH_0, rank 0
781 10:04:53.887414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 10:04:53.887499 ==
783 10:04:53.891603 [Gating] SW mode calibration
784 10:04:53.898991 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 10:04:53.901815 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 10:04:53.908658 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 10:04:53.912376 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 10:04:53.915677 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 10:04:53.921721 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 10:04:53.925341 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 10:04:53.928699 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 10:04:53.935202 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 10:04:53.938766 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 10:04:53.942104 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 10:04:53.948769 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 10:04:53.951939 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 10:04:53.955560 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 10:04:53.959234 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 10:04:53.965369 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 10:04:53.968919 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 10:04:53.972129 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 10:04:53.978870 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 10:04:53.982280 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 10:04:53.985243 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 10:04:53.992155 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 10:04:53.995679 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 10:04:53.998932 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 10:04:54.005521 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 10:04:54.009154 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 10:04:54.012164 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 10:04:54.019425 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 10:04:54.022067 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
813 10:04:54.025500 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 10:04:54.032422 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 10:04:54.035772 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 10:04:54.039040 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 10:04:54.042165 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 10:04:54.048669 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 10:04:54.052065 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
820 10:04:54.055776 0 10 8 | B1->B0 | 3232 2828 | 0 0 | (1 0) (1 1)
821 10:04:54.062395 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 10:04:54.065988 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 10:04:54.068756 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 10:04:54.075701 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 10:04:54.079070 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 10:04:54.082413 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 10:04:54.089474 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
828 10:04:54.092264 0 11 8 | B1->B0 | 2a2a 4343 | 0 0 | (0 0) (0 0)
829 10:04:54.095917 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
830 10:04:54.102372 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 10:04:54.106449 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 10:04:54.109569 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 10:04:54.112714 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 10:04:54.119667 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 10:04:54.122669 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 10:04:54.126006 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 10:04:54.132988 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 10:04:54.135880 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 10:04:54.139454 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 10:04:54.145800 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 10:04:54.149658 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 10:04:54.153154 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 10:04:54.159326 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 10:04:54.162612 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 10:04:54.166404 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 10:04:54.173112 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 10:04:54.176587 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 10:04:54.179540 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 10:04:54.183015 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 10:04:54.189790 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 10:04:54.192997 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 10:04:54.196198 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 10:04:54.199335 Total UI for P1: 0, mck2ui 16
854 10:04:54.202649 best dqsien dly found for B0: ( 0, 14, 4)
855 10:04:54.209528 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 10:04:54.213390 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 10:04:54.217025 Total UI for P1: 0, mck2ui 16
858 10:04:54.220162 best dqsien dly found for B1: ( 0, 14, 10)
859 10:04:54.223305 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
860 10:04:54.226929 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 10:04:54.227014
862 10:04:54.230106 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
863 10:04:54.233321 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 10:04:54.236947 [Gating] SW calibration Done
865 10:04:54.237030 ==
866 10:04:54.240074 Dram Type= 6, Freq= 0, CH_0, rank 0
867 10:04:54.243509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 10:04:54.243593 ==
869 10:04:54.247000 RX Vref Scan: 0
870 10:04:54.247083
871 10:04:54.247150 RX Vref 0 -> 0, step: 1
872 10:04:54.250437
873 10:04:54.250521 RX Delay -130 -> 252, step: 16
874 10:04:54.257291 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 10:04:54.260768 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
876 10:04:54.263582 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 10:04:54.266685 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 10:04:54.270056 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
879 10:04:54.276723 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
880 10:04:54.280090 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
881 10:04:54.283450 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
882 10:04:54.286986 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
883 10:04:54.290743 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
884 10:04:54.293652 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
885 10:04:54.300453 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 10:04:54.303789 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
887 10:04:54.307602 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
888 10:04:54.310456 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
889 10:04:54.317107 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 10:04:54.317190 ==
891 10:04:54.320585 Dram Type= 6, Freq= 0, CH_0, rank 0
892 10:04:54.323992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 10:04:54.324076 ==
894 10:04:54.324142 DQS Delay:
895 10:04:54.327055 DQS0 = 0, DQS1 = 0
896 10:04:54.327138 DQM Delay:
897 10:04:54.330393 DQM0 = 89, DQM1 = 80
898 10:04:54.330476 DQ Delay:
899 10:04:54.333599 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
900 10:04:54.337280 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
901 10:04:54.340416 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
902 10:04:54.343711 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
903 10:04:54.343793
904 10:04:54.343860
905 10:04:54.343923 ==
906 10:04:54.347107 Dram Type= 6, Freq= 0, CH_0, rank 0
907 10:04:54.350489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 10:04:54.350573 ==
909 10:04:54.350639
910 10:04:54.350699
911 10:04:54.354016 TX Vref Scan disable
912 10:04:54.357042 == TX Byte 0 ==
913 10:04:54.360471 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
914 10:04:54.364465 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
915 10:04:54.367298 == TX Byte 1 ==
916 10:04:54.370780 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
917 10:04:54.374176 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
918 10:04:54.374259 ==
919 10:04:54.377736 Dram Type= 6, Freq= 0, CH_0, rank 0
920 10:04:54.380490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 10:04:54.384207 ==
922 10:04:54.395978 TX Vref=22, minBit 5, minWin=27, winSum=446
923 10:04:54.399035 TX Vref=24, minBit 12, minWin=27, winSum=453
924 10:04:54.401804 TX Vref=26, minBit 11, minWin=27, winSum=452
925 10:04:54.405256 TX Vref=28, minBit 0, minWin=28, winSum=458
926 10:04:54.408809 TX Vref=30, minBit 4, minWin=28, winSum=457
927 10:04:54.415556 TX Vref=32, minBit 0, minWin=28, winSum=456
928 10:04:54.418830 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
929 10:04:54.418914
930 10:04:54.421950 Final TX Range 1 Vref 28
931 10:04:54.422033
932 10:04:54.422099 ==
933 10:04:54.425285 Dram Type= 6, Freq= 0, CH_0, rank 0
934 10:04:54.428754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 10:04:54.428857 ==
936 10:04:54.428924
937 10:04:54.432232
938 10:04:54.432314 TX Vref Scan disable
939 10:04:54.435452 == TX Byte 0 ==
940 10:04:54.439149 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
941 10:04:54.442018 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
942 10:04:54.445981 == TX Byte 1 ==
943 10:04:54.448702 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
944 10:04:54.451989 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
945 10:04:54.455520
946 10:04:54.455602 [DATLAT]
947 10:04:54.455667 Freq=800, CH0 RK0
948 10:04:54.455730
949 10:04:54.459346 DATLAT Default: 0xa
950 10:04:54.459428 0, 0xFFFF, sum = 0
951 10:04:54.462053 1, 0xFFFF, sum = 0
952 10:04:54.462139 2, 0xFFFF, sum = 0
953 10:04:54.465414 3, 0xFFFF, sum = 0
954 10:04:54.465498 4, 0xFFFF, sum = 0
955 10:04:54.469333 5, 0xFFFF, sum = 0
956 10:04:54.469418 6, 0xFFFF, sum = 0
957 10:04:54.472450 7, 0xFFFF, sum = 0
958 10:04:54.472535 8, 0xFFFF, sum = 0
959 10:04:54.475733 9, 0x0, sum = 1
960 10:04:54.475817 10, 0x0, sum = 2
961 10:04:54.478961 11, 0x0, sum = 3
962 10:04:54.479044 12, 0x0, sum = 4
963 10:04:54.482271 best_step = 10
964 10:04:54.482353
965 10:04:54.482419 ==
966 10:04:54.485676 Dram Type= 6, Freq= 0, CH_0, rank 0
967 10:04:54.488716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 10:04:54.488828 ==
969 10:04:54.492594 RX Vref Scan: 1
970 10:04:54.492706
971 10:04:54.492827 Set Vref Range= 32 -> 127
972 10:04:54.492907
973 10:04:54.495452 RX Vref 32 -> 127, step: 1
974 10:04:54.495535
975 10:04:54.499145 RX Delay -95 -> 252, step: 8
976 10:04:54.499228
977 10:04:54.502047 Set Vref, RX VrefLevel [Byte0]: 32
978 10:04:54.505841 [Byte1]: 32
979 10:04:54.505925
980 10:04:54.509118 Set Vref, RX VrefLevel [Byte0]: 33
981 10:04:54.512249 [Byte1]: 33
982 10:04:54.515850
983 10:04:54.515937 Set Vref, RX VrefLevel [Byte0]: 34
984 10:04:54.519350 [Byte1]: 34
985 10:04:54.523445
986 10:04:54.523527 Set Vref, RX VrefLevel [Byte0]: 35
987 10:04:54.526898 [Byte1]: 35
988 10:04:54.531552
989 10:04:54.531634 Set Vref, RX VrefLevel [Byte0]: 36
990 10:04:54.534789 [Byte1]: 36
991 10:04:54.538952
992 10:04:54.539033 Set Vref, RX VrefLevel [Byte0]: 37
993 10:04:54.541662 [Byte1]: 37
994 10:04:54.545831
995 10:04:54.545913 Set Vref, RX VrefLevel [Byte0]: 38
996 10:04:54.549997 [Byte1]: 38
997 10:04:54.553991
998 10:04:54.554072 Set Vref, RX VrefLevel [Byte0]: 39
999 10:04:54.557137 [Byte1]: 39
1000 10:04:54.561879
1001 10:04:54.561962 Set Vref, RX VrefLevel [Byte0]: 40
1002 10:04:54.564827 [Byte1]: 40
1003 10:04:54.568929
1004 10:04:54.569011 Set Vref, RX VrefLevel [Byte0]: 41
1005 10:04:54.571961 [Byte1]: 41
1006 10:04:54.576730
1007 10:04:54.576837 Set Vref, RX VrefLevel [Byte0]: 42
1008 10:04:54.579998 [Byte1]: 42
1009 10:04:54.584544
1010 10:04:54.584626 Set Vref, RX VrefLevel [Byte0]: 43
1011 10:04:54.587446 [Byte1]: 43
1012 10:04:54.591724
1013 10:04:54.591805 Set Vref, RX VrefLevel [Byte0]: 44
1014 10:04:54.595476 [Byte1]: 44
1015 10:04:54.599329
1016 10:04:54.599411 Set Vref, RX VrefLevel [Byte0]: 45
1017 10:04:54.602919 [Byte1]: 45
1018 10:04:54.607132
1019 10:04:54.607214 Set Vref, RX VrefLevel [Byte0]: 46
1020 10:04:54.610276 [Byte1]: 46
1021 10:04:54.614389
1022 10:04:54.614472 Set Vref, RX VrefLevel [Byte0]: 47
1023 10:04:54.617497 [Byte1]: 47
1024 10:04:54.622355
1025 10:04:54.622441 Set Vref, RX VrefLevel [Byte0]: 48
1026 10:04:54.625297 [Byte1]: 48
1027 10:04:54.630127
1028 10:04:54.630207 Set Vref, RX VrefLevel [Byte0]: 49
1029 10:04:54.632947 [Byte1]: 49
1030 10:04:54.637268
1031 10:04:54.637349 Set Vref, RX VrefLevel [Byte0]: 50
1032 10:04:54.640478 [Byte1]: 50
1033 10:04:54.644983
1034 10:04:54.645063 Set Vref, RX VrefLevel [Byte0]: 51
1035 10:04:54.648178 [Byte1]: 51
1036 10:04:54.652781
1037 10:04:54.652867 Set Vref, RX VrefLevel [Byte0]: 52
1038 10:04:54.655664 [Byte1]: 52
1039 10:04:54.660341
1040 10:04:54.660422 Set Vref, RX VrefLevel [Byte0]: 53
1041 10:04:54.663463 [Byte1]: 53
1042 10:04:54.667884
1043 10:04:54.667966 Set Vref, RX VrefLevel [Byte0]: 54
1044 10:04:54.670817 [Byte1]: 54
1045 10:04:54.674987
1046 10:04:54.675067 Set Vref, RX VrefLevel [Byte0]: 55
1047 10:04:54.678666 [Byte1]: 55
1048 10:04:54.682989
1049 10:04:54.683070 Set Vref, RX VrefLevel [Byte0]: 56
1050 10:04:54.686902 [Byte1]: 56
1051 10:04:54.690343
1052 10:04:54.690425 Set Vref, RX VrefLevel [Byte0]: 57
1053 10:04:54.693540 [Byte1]: 57
1054 10:04:54.698032
1055 10:04:54.698113 Set Vref, RX VrefLevel [Byte0]: 58
1056 10:04:54.701421 [Byte1]: 58
1057 10:04:54.705909
1058 10:04:54.705990 Set Vref, RX VrefLevel [Byte0]: 59
1059 10:04:54.708942 [Byte1]: 59
1060 10:04:54.713113
1061 10:04:54.713193 Set Vref, RX VrefLevel [Byte0]: 60
1062 10:04:54.716639 [Byte1]: 60
1063 10:04:54.720694
1064 10:04:54.720775 Set Vref, RX VrefLevel [Byte0]: 61
1065 10:04:54.723909 [Byte1]: 61
1066 10:04:54.728827
1067 10:04:54.728932 Set Vref, RX VrefLevel [Byte0]: 62
1068 10:04:54.731625 [Byte1]: 62
1069 10:04:54.735851
1070 10:04:54.735955 Set Vref, RX VrefLevel [Byte0]: 63
1071 10:04:54.739487 [Byte1]: 63
1072 10:04:54.743669
1073 10:04:54.743762 Set Vref, RX VrefLevel [Byte0]: 64
1074 10:04:54.746867 [Byte1]: 64
1075 10:04:54.751660
1076 10:04:54.751754 Set Vref, RX VrefLevel [Byte0]: 65
1077 10:04:54.754513 [Byte1]: 65
1078 10:04:54.759059
1079 10:04:54.759141 Set Vref, RX VrefLevel [Byte0]: 66
1080 10:04:54.762098 [Byte1]: 66
1081 10:04:54.766534
1082 10:04:54.766617 Set Vref, RX VrefLevel [Byte0]: 67
1083 10:04:54.769687 [Byte1]: 67
1084 10:04:54.773950
1085 10:04:54.774032 Set Vref, RX VrefLevel [Byte0]: 68
1086 10:04:54.777461 [Byte1]: 68
1087 10:04:54.781749
1088 10:04:54.781832 Set Vref, RX VrefLevel [Byte0]: 69
1089 10:04:54.785361 [Byte1]: 69
1090 10:04:54.789143
1091 10:04:54.789225 Set Vref, RX VrefLevel [Byte0]: 70
1092 10:04:54.792774 [Byte1]: 70
1093 10:04:54.797083
1094 10:04:54.797168 Set Vref, RX VrefLevel [Byte0]: 71
1095 10:04:54.800209 [Byte1]: 71
1096 10:04:54.804637
1097 10:04:54.804730 Set Vref, RX VrefLevel [Byte0]: 72
1098 10:04:54.807773 [Byte1]: 72
1099 10:04:54.812187
1100 10:04:54.812269 Set Vref, RX VrefLevel [Byte0]: 73
1101 10:04:54.815160 [Byte1]: 73
1102 10:04:54.819632
1103 10:04:54.819715 Set Vref, RX VrefLevel [Byte0]: 74
1104 10:04:54.823225 [Byte1]: 74
1105 10:04:54.827155
1106 10:04:54.827237 Set Vref, RX VrefLevel [Byte0]: 75
1107 10:04:54.830565 [Byte1]: 75
1108 10:04:54.834673
1109 10:04:54.834758 Set Vref, RX VrefLevel [Byte0]: 76
1110 10:04:54.838459 [Byte1]: 76
1111 10:04:54.842414
1112 10:04:54.842499 Set Vref, RX VrefLevel [Byte0]: 77
1113 10:04:54.845693 [Byte1]: 77
1114 10:04:54.850141
1115 10:04:54.850227 Set Vref, RX VrefLevel [Byte0]: 78
1116 10:04:54.853685 [Byte1]: 78
1117 10:04:54.857660
1118 10:04:54.857745 Final RX Vref Byte 0 = 50 to rank0
1119 10:04:54.861154 Final RX Vref Byte 1 = 61 to rank0
1120 10:04:54.864662 Final RX Vref Byte 0 = 50 to rank1
1121 10:04:54.868346 Final RX Vref Byte 1 = 61 to rank1==
1122 10:04:54.871021 Dram Type= 6, Freq= 0, CH_0, rank 0
1123 10:04:54.877393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1124 10:04:54.877481 ==
1125 10:04:54.877547 DQS Delay:
1126 10:04:54.877608 DQS0 = 0, DQS1 = 0
1127 10:04:54.880935 DQM Delay:
1128 10:04:54.881018 DQM0 = 91, DQM1 = 86
1129 10:04:54.884312 DQ Delay:
1130 10:04:54.887234 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1131 10:04:54.890639 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1132 10:04:54.894128 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =80
1133 10:04:54.897816 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1134 10:04:54.897901
1135 10:04:54.897966
1136 10:04:54.904411 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1137 10:04:54.907728 CH0 RK0: MR19=606, MR18=4C42
1138 10:04:54.914120 CH0_RK0: MR19=0x606, MR18=0x4C42, DQSOSC=390, MR23=63, INC=97, DEC=64
1139 10:04:54.914220
1140 10:04:54.917566 ----->DramcWriteLeveling(PI) begin...
1141 10:04:54.917650 ==
1142 10:04:54.920866 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 10:04:54.924453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 10:04:54.924536 ==
1145 10:04:54.927628 Write leveling (Byte 0): 33 => 33
1146 10:04:54.931337 Write leveling (Byte 1): 31 => 31
1147 10:04:54.934233 DramcWriteLeveling(PI) end<-----
1148 10:04:54.934316
1149 10:04:54.934381 ==
1150 10:04:54.937255 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 10:04:54.981587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 10:04:54.981748 ==
1153 10:04:54.981818 [Gating] SW mode calibration
1154 10:04:54.982070 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1155 10:04:54.982320 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1156 10:04:54.982387 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 10:04:54.983357 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1158 10:04:54.983864 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 10:04:54.984510 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 10:04:54.984770 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 10:04:54.984864 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 10:04:55.025914 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 10:04:55.026262 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 10:04:55.026341 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 10:04:55.026405 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 10:04:55.026466 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 10:04:55.026814 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 10:04:55.027480 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 10:04:55.027740 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 10:04:55.027987 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 10:04:55.028055 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 10:04:55.039268 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 10:04:55.039557 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1174 10:04:55.042632 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1175 10:04:55.045897 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 10:04:55.049002 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 10:04:55.052479 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 10:04:55.059434 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 10:04:55.062633 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 10:04:55.066029 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 10:04:55.069058 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 10:04:55.076331 0 9 8 | B1->B0 | 3131 2d2d | 0 0 | (0 0) (1 1)
1183 10:04:55.079732 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 10:04:55.082800 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 10:04:55.089593 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 10:04:55.093116 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 10:04:55.096457 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 10:04:55.102751 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 10:04:55.106516 0 10 4 | B1->B0 | 3232 3333 | 1 0 | (1 1) (0 0)
1190 10:04:55.110116 0 10 8 | B1->B0 | 2727 2828 | 0 0 | (0 0) (0 0)
1191 10:04:55.113769 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 10:04:55.117642 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 10:04:55.125129 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 10:04:55.128204 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 10:04:55.131287 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 10:04:55.135070 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 10:04:55.142122 0 11 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1198 10:04:55.145558 0 11 8 | B1->B0 | 3d3d 3838 | 0 0 | (0 0) (0 0)
1199 10:04:55.148977 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 10:04:55.155582 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 10:04:55.159479 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 10:04:55.162353 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 10:04:55.169411 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 10:04:55.172503 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 10:04:55.175801 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 10:04:55.182495 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1207 10:04:55.185990 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 10:04:55.189221 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 10:04:55.192584 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 10:04:55.199473 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 10:04:55.202205 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 10:04:55.205602 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 10:04:55.212452 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 10:04:55.215738 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 10:04:55.219226 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 10:04:55.225570 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 10:04:55.228973 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 10:04:55.232471 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 10:04:55.238894 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 10:04:55.242581 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 10:04:55.245503 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 10:04:55.252251 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1223 10:04:55.255705 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 10:04:55.259214 Total UI for P1: 0, mck2ui 16
1225 10:04:55.262144 best dqsien dly found for B0: ( 0, 14, 8)
1226 10:04:55.265522 Total UI for P1: 0, mck2ui 16
1227 10:04:55.268879 best dqsien dly found for B1: ( 0, 14, 8)
1228 10:04:55.272292 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1229 10:04:55.275902 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1230 10:04:55.275998
1231 10:04:55.279221 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 10:04:55.282865 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1233 10:04:55.286004 [Gating] SW calibration Done
1234 10:04:55.286092 ==
1235 10:04:55.289238 Dram Type= 6, Freq= 0, CH_0, rank 1
1236 10:04:55.292695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1237 10:04:55.292781 ==
1238 10:04:55.296345 RX Vref Scan: 0
1239 10:04:55.296432
1240 10:04:55.296499 RX Vref 0 -> 0, step: 1
1241 10:04:55.299575
1242 10:04:55.299659 RX Delay -130 -> 252, step: 16
1243 10:04:55.305600 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1244 10:04:55.309529 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1245 10:04:55.312700 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1246 10:04:55.316138 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1247 10:04:55.319066 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1248 10:04:55.325918 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1249 10:04:55.329464 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1250 10:04:55.332520 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
1251 10:04:55.335709 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1252 10:04:55.339719 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1253 10:04:55.342516 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1254 10:04:55.349290 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1255 10:04:55.352783 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1256 10:04:55.356443 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1257 10:04:55.359461 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1258 10:04:55.366150 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1259 10:04:55.366249 ==
1260 10:04:55.369670 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 10:04:55.372723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1262 10:04:55.372870 ==
1263 10:04:55.372939 DQS Delay:
1264 10:04:55.376480 DQS0 = 0, DQS1 = 0
1265 10:04:55.376564 DQM Delay:
1266 10:04:55.379274 DQM0 = 89, DQM1 = 83
1267 10:04:55.379358 DQ Delay:
1268 10:04:55.382633 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1269 10:04:55.386221 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
1270 10:04:55.389615 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1271 10:04:55.392732 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1272 10:04:55.392874
1273 10:04:55.392941
1274 10:04:55.393002 ==
1275 10:04:55.396402 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 10:04:55.399590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 10:04:55.399676 ==
1278 10:04:55.399742
1279 10:04:55.399804
1280 10:04:55.402781 TX Vref Scan disable
1281 10:04:55.406104 == TX Byte 0 ==
1282 10:04:55.409557 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1283 10:04:55.412544 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1284 10:04:55.416310 == TX Byte 1 ==
1285 10:04:55.419328 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1286 10:04:55.422733 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1287 10:04:55.422830 ==
1288 10:04:55.426189 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 10:04:55.429709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 10:04:55.432638 ==
1291 10:04:55.444153 TX Vref=22, minBit 8, minWin=27, winSum=448
1292 10:04:55.447548 TX Vref=24, minBit 1, minWin=28, winSum=453
1293 10:04:55.451458 TX Vref=26, minBit 11, minWin=27, winSum=452
1294 10:04:55.454105 TX Vref=28, minBit 4, minWin=28, winSum=456
1295 10:04:55.457405 TX Vref=30, minBit 4, minWin=28, winSum=460
1296 10:04:55.460966 TX Vref=32, minBit 1, minWin=28, winSum=455
1297 10:04:55.468004 [TxChooseVref] Worse bit 4, Min win 28, Win sum 460, Final Vref 30
1298 10:04:55.468102
1299 10:04:55.471007 Final TX Range 1 Vref 30
1300 10:04:55.471103
1301 10:04:55.471173 ==
1302 10:04:55.474980 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 10:04:55.477869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 10:04:55.477957 ==
1305 10:04:55.478023
1306 10:04:55.478084
1307 10:04:55.481267 TX Vref Scan disable
1308 10:04:55.484730 == TX Byte 0 ==
1309 10:04:55.488092 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1310 10:04:55.491105 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1311 10:04:55.494245 == TX Byte 1 ==
1312 10:04:55.498081 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1313 10:04:55.501681 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1314 10:04:55.501768
1315 10:04:55.504573 [DATLAT]
1316 10:04:55.504664 Freq=800, CH0 RK1
1317 10:04:55.504731
1318 10:04:55.507920 DATLAT Default: 0xa
1319 10:04:55.508007 0, 0xFFFF, sum = 0
1320 10:04:55.511762 1, 0xFFFF, sum = 0
1321 10:04:55.511847 2, 0xFFFF, sum = 0
1322 10:04:55.514632 3, 0xFFFF, sum = 0
1323 10:04:55.514715 4, 0xFFFF, sum = 0
1324 10:04:55.518150 5, 0xFFFF, sum = 0
1325 10:04:55.518233 6, 0xFFFF, sum = 0
1326 10:04:55.521143 7, 0xFFFF, sum = 0
1327 10:04:55.521226 8, 0xFFFF, sum = 0
1328 10:04:55.524628 9, 0x0, sum = 1
1329 10:04:55.524711 10, 0x0, sum = 2
1330 10:04:55.528065 11, 0x0, sum = 3
1331 10:04:55.528150 12, 0x0, sum = 4
1332 10:04:55.531146 best_step = 10
1333 10:04:55.531227
1334 10:04:55.531291 ==
1335 10:04:55.534745 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 10:04:55.537773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 10:04:55.537856 ==
1338 10:04:55.541051 RX Vref Scan: 0
1339 10:04:55.541132
1340 10:04:55.541195 RX Vref 0 -> 0, step: 1
1341 10:04:55.541255
1342 10:04:55.544602 RX Delay -79 -> 252, step: 8
1343 10:04:55.551206 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1344 10:04:55.554705 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1345 10:04:55.558309 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1346 10:04:55.561629 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1347 10:04:55.564727 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1348 10:04:55.567884 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1349 10:04:55.575186 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1350 10:04:55.577906 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1351 10:04:55.581485 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1352 10:04:55.584526 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1353 10:04:55.587978 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1354 10:04:55.594650 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1355 10:04:55.597949 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1356 10:04:55.601226 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1357 10:04:55.604526 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1358 10:04:55.607831 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1359 10:04:55.611122 ==
1360 10:04:55.614918 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 10:04:55.618404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 10:04:55.618496 ==
1363 10:04:55.618563 DQS Delay:
1364 10:04:55.621562 DQS0 = 0, DQS1 = 0
1365 10:04:55.621645 DQM Delay:
1366 10:04:55.624746 DQM0 = 92, DQM1 = 84
1367 10:04:55.624886 DQ Delay:
1368 10:04:55.628313 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1369 10:04:55.631974 DQ4 =96, DQ5 =84, DQ6 =96, DQ7 =100
1370 10:04:55.635025 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1371 10:04:55.638196 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1372 10:04:55.638281
1373 10:04:55.638346
1374 10:04:55.644756 [DQSOSCAuto] RK1, (LSB)MR18= 0x4616, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1375 10:04:55.648007 CH0 RK1: MR19=606, MR18=4616
1376 10:04:55.654762 CH0_RK1: MR19=0x606, MR18=0x4616, DQSOSC=392, MR23=63, INC=96, DEC=64
1377 10:04:55.658783 [RxdqsGatingPostProcess] freq 800
1378 10:04:55.661683 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1379 10:04:55.665087 Pre-setting of DQS Precalculation
1380 10:04:55.671535 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1381 10:04:55.671635 ==
1382 10:04:55.674705 Dram Type= 6, Freq= 0, CH_1, rank 0
1383 10:04:55.678435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1384 10:04:55.678525 ==
1385 10:04:55.684952 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1386 10:04:55.691562 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1387 10:04:55.699311 [CA 0] Center 36 (6~67) winsize 62
1388 10:04:55.702773 [CA 1] Center 36 (6~67) winsize 62
1389 10:04:55.706334 [CA 2] Center 35 (5~65) winsize 61
1390 10:04:55.709169 [CA 3] Center 35 (5~65) winsize 61
1391 10:04:55.712635 [CA 4] Center 34 (4~65) winsize 62
1392 10:04:55.716221 [CA 5] Center 34 (4~64) winsize 61
1393 10:04:55.716308
1394 10:04:55.719390 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1395 10:04:55.719474
1396 10:04:55.722419 [CATrainingPosCal] consider 1 rank data
1397 10:04:55.726135 u2DelayCellTimex100 = 270/100 ps
1398 10:04:55.729161 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 10:04:55.732649 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1400 10:04:55.736002 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1401 10:04:55.743083 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1402 10:04:55.746182 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1403 10:04:55.749752 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1404 10:04:55.749839
1405 10:04:55.752979 CA PerBit enable=1, Macro0, CA PI delay=34
1406 10:04:55.753064
1407 10:04:55.756309 [CBTSetCACLKResult] CA Dly = 34
1408 10:04:55.756393 CS Dly: 5 (0~36)
1409 10:04:55.756459 ==
1410 10:04:55.759296 Dram Type= 6, Freq= 0, CH_1, rank 1
1411 10:04:55.766158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 10:04:55.766276 ==
1413 10:04:55.769677 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1414 10:04:55.776175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1415 10:04:55.785954 [CA 0] Center 36 (6~67) winsize 62
1416 10:04:55.790291 [CA 1] Center 37 (6~68) winsize 63
1417 10:04:55.793562 [CA 2] Center 35 (5~66) winsize 62
1418 10:04:55.797045 [CA 3] Center 34 (4~65) winsize 62
1419 10:04:55.801113 [CA 4] Center 35 (5~66) winsize 62
1420 10:04:55.801213 [CA 5] Center 34 (4~65) winsize 62
1421 10:04:55.801281
1422 10:04:55.804710 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1423 10:04:55.804808
1424 10:04:55.808255 [CATrainingPosCal] consider 2 rank data
1425 10:04:55.811402 u2DelayCellTimex100 = 270/100 ps
1426 10:04:55.814852 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 10:04:55.821326 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1428 10:04:55.824602 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1429 10:04:55.827946 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1430 10:04:55.831561 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1431 10:04:55.834665 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1432 10:04:55.834754
1433 10:04:55.838051 CA PerBit enable=1, Macro0, CA PI delay=34
1434 10:04:55.838135
1435 10:04:55.841367 [CBTSetCACLKResult] CA Dly = 34
1436 10:04:55.844941 CS Dly: 6 (0~39)
1437 10:04:55.845026
1438 10:04:55.847908 ----->DramcWriteLeveling(PI) begin...
1439 10:04:55.848020 ==
1440 10:04:55.851713 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 10:04:55.854733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 10:04:55.854824 ==
1443 10:04:55.858248 Write leveling (Byte 0): 27 => 27
1444 10:04:55.861361 Write leveling (Byte 1): 29 => 29
1445 10:04:55.865186 DramcWriteLeveling(PI) end<-----
1446 10:04:55.865274
1447 10:04:55.865339 ==
1448 10:04:55.868125 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 10:04:55.871600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 10:04:55.871687 ==
1451 10:04:55.874568 [Gating] SW mode calibration
1452 10:04:55.881737 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1453 10:04:55.888068 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1454 10:04:55.891545 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1455 10:04:55.895075 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1456 10:04:55.898253 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 10:04:55.905059 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 10:04:55.908398 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 10:04:55.911572 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 10:04:55.918206 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 10:04:55.921603 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 10:04:55.925084 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 10:04:55.931618 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 10:04:55.934899 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 10:04:55.938617 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 10:04:55.945174 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 10:04:55.948528 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 10:04:55.952045 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 10:04:55.958696 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 10:04:55.961983 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1471 10:04:55.965377 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1472 10:04:55.968612 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1473 10:04:55.975326 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 10:04:55.978645 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 10:04:55.982155 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 10:04:55.988941 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 10:04:55.992099 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 10:04:55.995388 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 10:04:56.002124 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1480 10:04:56.005818 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1481 10:04:56.008556 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 10:04:56.015155 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 10:04:56.018675 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 10:04:56.021849 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 10:04:56.028398 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 10:04:56.032017 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1487 10:04:56.035026 0 10 4 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (0 0)
1488 10:04:56.041826 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 10:04:56.045400 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 10:04:56.048634 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 10:04:56.055105 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 10:04:56.058352 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 10:04:56.061775 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 10:04:56.068395 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 10:04:56.071959 0 11 4 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
1496 10:04:56.075302 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1497 10:04:56.078661 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 10:04:56.085360 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 10:04:56.088687 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 10:04:56.091996 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 10:04:56.098941 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 10:04:56.102395 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 10:04:56.105684 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1504 10:04:56.112041 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 10:04:56.115408 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 10:04:56.118788 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 10:04:56.125656 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 10:04:56.128724 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 10:04:56.132411 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 10:04:56.135607 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 10:04:56.142291 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 10:04:56.145534 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 10:04:56.149150 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 10:04:56.155393 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 10:04:56.158675 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 10:04:56.162409 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 10:04:56.169328 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 10:04:56.172612 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1519 10:04:56.175782 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1520 10:04:56.182172 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 10:04:56.182280 Total UI for P1: 0, mck2ui 16
1522 10:04:56.188862 best dqsien dly found for B0: ( 0, 14, 4)
1523 10:04:56.188963 Total UI for P1: 0, mck2ui 16
1524 10:04:56.192620 best dqsien dly found for B1: ( 0, 14, 2)
1525 10:04:56.198950 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1526 10:04:56.202192 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1527 10:04:56.202288
1528 10:04:56.205610 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1529 10:04:56.208961 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1530 10:04:56.212738 [Gating] SW calibration Done
1531 10:04:56.212872 ==
1532 10:04:56.215874 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 10:04:56.219133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 10:04:56.219228 ==
1535 10:04:56.219298 RX Vref Scan: 0
1536 10:04:56.222476
1537 10:04:56.222560 RX Vref 0 -> 0, step: 1
1538 10:04:56.222626
1539 10:04:56.225768 RX Delay -130 -> 252, step: 16
1540 10:04:56.229060 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1541 10:04:56.232717 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1542 10:04:56.239054 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1543 10:04:56.242745 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1544 10:04:56.246224 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1545 10:04:56.249235 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1546 10:04:56.252946 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1547 10:04:56.259626 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1548 10:04:56.262906 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1549 10:04:56.266402 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1550 10:04:56.269599 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1551 10:04:56.272947 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1552 10:04:56.279422 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1553 10:04:56.282394 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1554 10:04:56.286098 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1555 10:04:56.289665 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1556 10:04:56.289752 ==
1557 10:04:56.292725 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 10:04:56.299350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 10:04:56.299450 ==
1560 10:04:56.299519 DQS Delay:
1561 10:04:56.299581 DQS0 = 0, DQS1 = 0
1562 10:04:56.302567 DQM Delay:
1563 10:04:56.302651 DQM0 = 94, DQM1 = 89
1564 10:04:56.305806 DQ Delay:
1565 10:04:56.309461 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1566 10:04:56.312662 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1567 10:04:56.312778 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1568 10:04:56.319356 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1569 10:04:56.319449
1570 10:04:56.319516
1571 10:04:56.319576 ==
1572 10:04:56.322832 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 10:04:56.326233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 10:04:56.326333 ==
1575 10:04:56.326432
1576 10:04:56.326499
1577 10:04:56.329596 TX Vref Scan disable
1578 10:04:56.329680 == TX Byte 0 ==
1579 10:04:56.336310 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1580 10:04:56.339226 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1581 10:04:56.339316 == TX Byte 1 ==
1582 10:04:56.345954 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1583 10:04:56.350292 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1584 10:04:56.350387 ==
1585 10:04:56.353645 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 10:04:56.356958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 10:04:56.357051 ==
1588 10:04:56.370180 TX Vref=22, minBit 0, minWin=26, winSum=438
1589 10:04:56.373353 TX Vref=24, minBit 1, minWin=27, winSum=443
1590 10:04:56.376573 TX Vref=26, minBit 1, minWin=27, winSum=443
1591 10:04:56.380425 TX Vref=28, minBit 2, minWin=27, winSum=448
1592 10:04:56.384145 TX Vref=30, minBit 1, minWin=27, winSum=448
1593 10:04:56.386496 TX Vref=32, minBit 1, minWin=27, winSum=449
1594 10:04:56.393280 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 32
1595 10:04:56.393386
1596 10:04:56.396663 Final TX Range 1 Vref 32
1597 10:04:56.396816
1598 10:04:56.396900 ==
1599 10:04:56.400303 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 10:04:56.403509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 10:04:56.403603 ==
1602 10:04:56.403671
1603 10:04:56.403731
1604 10:04:56.406961 TX Vref Scan disable
1605 10:04:56.409933 == TX Byte 0 ==
1606 10:04:56.413417 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1607 10:04:56.417083 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1608 10:04:56.419749 == TX Byte 1 ==
1609 10:04:56.423171 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1610 10:04:56.426547 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1611 10:04:56.426635
1612 10:04:56.429823 [DATLAT]
1613 10:04:56.429907 Freq=800, CH1 RK0
1614 10:04:56.429972
1615 10:04:56.433501 DATLAT Default: 0xa
1616 10:04:56.433584 0, 0xFFFF, sum = 0
1617 10:04:56.436543 1, 0xFFFF, sum = 0
1618 10:04:56.436628 2, 0xFFFF, sum = 0
1619 10:04:56.440073 3, 0xFFFF, sum = 0
1620 10:04:56.440157 4, 0xFFFF, sum = 0
1621 10:04:56.443473 5, 0xFFFF, sum = 0
1622 10:04:56.443559 6, 0xFFFF, sum = 0
1623 10:04:56.447261 7, 0xFFFF, sum = 0
1624 10:04:56.447346 8, 0xFFFF, sum = 0
1625 10:04:56.449857 9, 0x0, sum = 1
1626 10:04:56.449942 10, 0x0, sum = 2
1627 10:04:56.453310 11, 0x0, sum = 3
1628 10:04:56.453394 12, 0x0, sum = 4
1629 10:04:56.456754 best_step = 10
1630 10:04:56.456891
1631 10:04:56.456958 ==
1632 10:04:56.459932 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 10:04:56.463415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 10:04:56.463502 ==
1635 10:04:56.466775 RX Vref Scan: 1
1636 10:04:56.466859
1637 10:04:56.466924 Set Vref Range= 32 -> 127
1638 10:04:56.466983
1639 10:04:56.469929 RX Vref 32 -> 127, step: 1
1640 10:04:56.470012
1641 10:04:56.473613 RX Delay -79 -> 252, step: 8
1642 10:04:56.473700
1643 10:04:56.476633 Set Vref, RX VrefLevel [Byte0]: 32
1644 10:04:56.479763 [Byte1]: 32
1645 10:04:56.479849
1646 10:04:56.483827 Set Vref, RX VrefLevel [Byte0]: 33
1647 10:04:56.486657 [Byte1]: 33
1648 10:04:56.489789
1649 10:04:56.489884 Set Vref, RX VrefLevel [Byte0]: 34
1650 10:04:56.493709 [Byte1]: 34
1651 10:04:56.497576
1652 10:04:56.497669 Set Vref, RX VrefLevel [Byte0]: 35
1653 10:04:56.500729 [Byte1]: 35
1654 10:04:56.505042
1655 10:04:56.505132 Set Vref, RX VrefLevel [Byte0]: 36
1656 10:04:56.508185 [Byte1]: 36
1657 10:04:56.512733
1658 10:04:56.512884 Set Vref, RX VrefLevel [Byte0]: 37
1659 10:04:56.516072 [Byte1]: 37
1660 10:04:56.520275
1661 10:04:56.520363 Set Vref, RX VrefLevel [Byte0]: 38
1662 10:04:56.523497 [Byte1]: 38
1663 10:04:56.527595
1664 10:04:56.527681 Set Vref, RX VrefLevel [Byte0]: 39
1665 10:04:56.530931 [Byte1]: 39
1666 10:04:56.535478
1667 10:04:56.535569 Set Vref, RX VrefLevel [Byte0]: 40
1668 10:04:56.538445 [Byte1]: 40
1669 10:04:56.543122
1670 10:04:56.543217 Set Vref, RX VrefLevel [Byte0]: 41
1671 10:04:56.546743 [Byte1]: 41
1672 10:04:56.550645
1673 10:04:56.550733 Set Vref, RX VrefLevel [Byte0]: 42
1674 10:04:56.554237 [Byte1]: 42
1675 10:04:56.558057
1676 10:04:56.558146 Set Vref, RX VrefLevel [Byte0]: 43
1677 10:04:56.561573 [Byte1]: 43
1678 10:04:56.565761
1679 10:04:56.565852 Set Vref, RX VrefLevel [Byte0]: 44
1680 10:04:56.568769 [Byte1]: 44
1681 10:04:56.573319
1682 10:04:56.573411 Set Vref, RX VrefLevel [Byte0]: 45
1683 10:04:56.576212 [Byte1]: 45
1684 10:04:56.580785
1685 10:04:56.580888 Set Vref, RX VrefLevel [Byte0]: 46
1686 10:04:56.584090 [Byte1]: 46
1687 10:04:56.588044
1688 10:04:56.588140 Set Vref, RX VrefLevel [Byte0]: 47
1689 10:04:56.591164 [Byte1]: 47
1690 10:04:56.595724
1691 10:04:56.595822 Set Vref, RX VrefLevel [Byte0]: 48
1692 10:04:56.598956 [Byte1]: 48
1693 10:04:56.603255
1694 10:04:56.603352 Set Vref, RX VrefLevel [Byte0]: 49
1695 10:04:56.606731 [Byte1]: 49
1696 10:04:56.610963
1697 10:04:56.611060 Set Vref, RX VrefLevel [Byte0]: 50
1698 10:04:56.614348 [Byte1]: 50
1699 10:04:56.618281
1700 10:04:56.618371 Set Vref, RX VrefLevel [Byte0]: 51
1701 10:04:56.621539 [Byte1]: 51
1702 10:04:56.626158
1703 10:04:56.626247 Set Vref, RX VrefLevel [Byte0]: 52
1704 10:04:56.629557 [Byte1]: 52
1705 10:04:56.633558
1706 10:04:56.633649 Set Vref, RX VrefLevel [Byte0]: 53
1707 10:04:56.636628 [Byte1]: 53
1708 10:04:56.640937
1709 10:04:56.641027 Set Vref, RX VrefLevel [Byte0]: 54
1710 10:04:56.644103 [Byte1]: 54
1711 10:04:56.648711
1712 10:04:56.648808 Set Vref, RX VrefLevel [Byte0]: 55
1713 10:04:56.652027 [Byte1]: 55
1714 10:04:56.655807
1715 10:04:56.655897 Set Vref, RX VrefLevel [Byte0]: 56
1716 10:04:56.659213 [Byte1]: 56
1717 10:04:56.663982
1718 10:04:56.664075 Set Vref, RX VrefLevel [Byte0]: 57
1719 10:04:56.666769 [Byte1]: 57
1720 10:04:56.671120
1721 10:04:56.671211 Set Vref, RX VrefLevel [Byte0]: 58
1722 10:04:56.674390 [Byte1]: 58
1723 10:04:56.678639
1724 10:04:56.678731 Set Vref, RX VrefLevel [Byte0]: 59
1725 10:04:56.681766 [Byte1]: 59
1726 10:04:56.686409
1727 10:04:56.686509 Set Vref, RX VrefLevel [Byte0]: 60
1728 10:04:56.689549 [Byte1]: 60
1729 10:04:56.693518
1730 10:04:56.693611 Set Vref, RX VrefLevel [Byte0]: 61
1731 10:04:56.696811 [Byte1]: 61
1732 10:04:56.701183
1733 10:04:56.701282 Set Vref, RX VrefLevel [Byte0]: 62
1734 10:04:56.704838 [Byte1]: 62
1735 10:04:56.709008
1736 10:04:56.709102 Set Vref, RX VrefLevel [Byte0]: 63
1737 10:04:56.712733 [Byte1]: 63
1738 10:04:56.716835
1739 10:04:56.716940 Set Vref, RX VrefLevel [Byte0]: 64
1740 10:04:56.719599 [Byte1]: 64
1741 10:04:56.723864
1742 10:04:56.723952 Set Vref, RX VrefLevel [Byte0]: 65
1743 10:04:56.727008 [Byte1]: 65
1744 10:04:56.731690
1745 10:04:56.731778 Set Vref, RX VrefLevel [Byte0]: 66
1746 10:04:56.734575 [Byte1]: 66
1747 10:04:56.739136
1748 10:04:56.739228 Set Vref, RX VrefLevel [Byte0]: 67
1749 10:04:56.742332 [Byte1]: 67
1750 10:04:56.746413
1751 10:04:56.746504 Set Vref, RX VrefLevel [Byte0]: 68
1752 10:04:56.749700 [Byte1]: 68
1753 10:04:56.754195
1754 10:04:56.754287 Set Vref, RX VrefLevel [Byte0]: 69
1755 10:04:56.757729 [Byte1]: 69
1756 10:04:56.761866
1757 10:04:56.761960 Set Vref, RX VrefLevel [Byte0]: 70
1758 10:04:56.765785 [Byte1]: 70
1759 10:04:56.769100
1760 10:04:56.769191 Set Vref, RX VrefLevel [Byte0]: 71
1761 10:04:56.772449 [Byte1]: 71
1762 10:04:56.776657
1763 10:04:56.776747 Set Vref, RX VrefLevel [Byte0]: 72
1764 10:04:56.779949 [Byte1]: 72
1765 10:04:56.784942
1766 10:04:56.785051 Final RX Vref Byte 0 = 57 to rank0
1767 10:04:56.787609 Final RX Vref Byte 1 = 53 to rank0
1768 10:04:56.790942 Final RX Vref Byte 0 = 57 to rank1
1769 10:04:56.794290 Final RX Vref Byte 1 = 53 to rank1==
1770 10:04:56.797527 Dram Type= 6, Freq= 0, CH_1, rank 0
1771 10:04:56.804630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1772 10:04:56.804749 ==
1773 10:04:56.804891 DQS Delay:
1774 10:04:56.804974 DQS0 = 0, DQS1 = 0
1775 10:04:56.807815 DQM Delay:
1776 10:04:56.807901 DQM0 = 95, DQM1 = 89
1777 10:04:56.811300 DQ Delay:
1778 10:04:56.814392 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =96
1779 10:04:56.817747 DQ4 =96, DQ5 =108, DQ6 =100, DQ7 =92
1780 10:04:56.817842 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1781 10:04:56.824299 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1782 10:04:56.824397
1783 10:04:56.824485
1784 10:04:56.831136 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a46, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1785 10:04:56.834874 CH1 RK0: MR19=606, MR18=2A46
1786 10:04:56.840941 CH1_RK0: MR19=0x606, MR18=0x2A46, DQSOSC=392, MR23=63, INC=96, DEC=64
1787 10:04:56.841050
1788 10:04:56.844315 ----->DramcWriteLeveling(PI) begin...
1789 10:04:56.844406 ==
1790 10:04:56.847643 Dram Type= 6, Freq= 0, CH_1, rank 1
1791 10:04:56.851199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 10:04:56.851299 ==
1793 10:04:56.854962 Write leveling (Byte 0): 29 => 29
1794 10:04:56.857945 Write leveling (Byte 1): 29 => 29
1795 10:04:56.861695 DramcWriteLeveling(PI) end<-----
1796 10:04:56.861787
1797 10:04:56.861855 ==
1798 10:04:56.864735 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 10:04:56.867760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 10:04:56.867847 ==
1801 10:04:56.871349 [Gating] SW mode calibration
1802 10:04:56.877998 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1803 10:04:56.884721 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1804 10:04:56.888016 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1805 10:04:56.891370 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1806 10:04:56.897949 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 10:04:56.901430 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 10:04:56.904632 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 10:04:56.911306 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 10:04:56.914948 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 10:04:56.918507 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 10:04:56.921686 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 10:04:56.928142 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 10:04:56.931602 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 10:04:56.934488 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 10:04:56.941033 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 10:04:56.944644 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 10:04:56.948016 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 10:04:56.954518 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1820 10:04:56.958035 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1821 10:04:56.961459 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 10:04:56.968405 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 10:04:56.971394 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 10:04:56.974876 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 10:04:56.981375 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 10:04:56.984648 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 10:04:56.988002 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 10:04:56.994709 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 10:04:56.998145 0 9 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1830 10:04:57.001497 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
1831 10:04:57.005068 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 10:04:57.011652 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 10:04:57.014966 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 10:04:57.021347 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 10:04:57.024369 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 10:04:57.028319 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1837 10:04:57.031478 0 10 4 | B1->B0 | 2e2e 3030 | 0 0 | (0 1) (0 1)
1838 10:04:57.038020 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 10:04:57.041331 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 10:04:57.044652 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 10:04:57.051483 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 10:04:57.054775 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 10:04:57.057891 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 10:04:57.064706 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1845 10:04:57.067844 0 11 4 | B1->B0 | 3737 2f2f | 0 0 | (0 0) (1 1)
1846 10:04:57.071531 0 11 8 | B1->B0 | 4646 3f3f | 0 1 | (0 0) (0 0)
1847 10:04:57.078093 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 10:04:57.081277 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 10:04:57.084434 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 10:04:57.091402 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 10:04:57.094747 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 10:04:57.097681 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1853 10:04:57.104628 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1854 10:04:57.108174 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 10:04:57.111457 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 10:04:57.114715 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 10:04:57.121333 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 10:04:57.124906 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 10:04:57.127836 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 10:04:57.134629 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 10:04:57.137826 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 10:04:57.141238 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 10:04:57.148315 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 10:04:57.151625 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 10:04:57.154834 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 10:04:57.161471 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 10:04:57.165400 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1868 10:04:57.168047 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1869 10:04:57.174622 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1870 10:04:57.178282 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 10:04:57.181444 Total UI for P1: 0, mck2ui 16
1872 10:04:57.184697 best dqsien dly found for B0: ( 0, 14, 2)
1873 10:04:57.188708 Total UI for P1: 0, mck2ui 16
1874 10:04:57.191532 best dqsien dly found for B1: ( 0, 14, 4)
1875 10:04:57.195148 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1876 10:04:57.198242 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1877 10:04:57.198337
1878 10:04:57.201775 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1879 10:04:57.204967 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1880 10:04:57.208580 [Gating] SW calibration Done
1881 10:04:57.208676 ==
1882 10:04:57.212074 Dram Type= 6, Freq= 0, CH_1, rank 1
1883 10:04:57.215543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1884 10:04:57.215634 ==
1885 10:04:57.218400 RX Vref Scan: 0
1886 10:04:57.218485
1887 10:04:57.218552 RX Vref 0 -> 0, step: 1
1888 10:04:57.218614
1889 10:04:57.221780 RX Delay -130 -> 252, step: 16
1890 10:04:57.225426 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1891 10:04:57.231831 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1892 10:04:57.235213 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1893 10:04:57.238345 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1894 10:04:57.241653 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1895 10:04:57.245022 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1896 10:04:57.251816 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1897 10:04:57.255147 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1898 10:04:57.258342 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1899 10:04:57.262269 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1900 10:04:57.265301 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1901 10:04:57.271774 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1902 10:04:57.275309 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1903 10:04:57.278667 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1904 10:04:57.281975 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1905 10:04:57.285451 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1906 10:04:57.289235 ==
1907 10:04:57.289327 Dram Type= 6, Freq= 0, CH_1, rank 1
1908 10:04:57.295461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1909 10:04:57.295563 ==
1910 10:04:57.295633 DQS Delay:
1911 10:04:57.298955 DQS0 = 0, DQS1 = 0
1912 10:04:57.299045 DQM Delay:
1913 10:04:57.302567 DQM0 = 92, DQM1 = 88
1914 10:04:57.302653 DQ Delay:
1915 10:04:57.305336 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1916 10:04:57.308744 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1917 10:04:57.312113 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1918 10:04:57.315707 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1919 10:04:57.315799
1920 10:04:57.315866
1921 10:04:57.315928 ==
1922 10:04:57.319038 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 10:04:57.322397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 10:04:57.322484 ==
1925 10:04:57.322552
1926 10:04:57.322614
1927 10:04:57.325526 TX Vref Scan disable
1928 10:04:57.328873 == TX Byte 0 ==
1929 10:04:57.331858 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1930 10:04:57.335370 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1931 10:04:57.339044 == TX Byte 1 ==
1932 10:04:57.342387 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1933 10:04:57.345984 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1934 10:04:57.346076 ==
1935 10:04:57.349268 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 10:04:57.352281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 10:04:57.352369 ==
1938 10:04:57.366966 TX Vref=22, minBit 0, minWin=27, winSum=444
1939 10:04:57.369720 TX Vref=24, minBit 1, minWin=27, winSum=448
1940 10:04:57.373434 TX Vref=26, minBit 2, minWin=27, winSum=450
1941 10:04:57.376559 TX Vref=28, minBit 2, minWin=27, winSum=451
1942 10:04:57.379851 TX Vref=30, minBit 2, minWin=27, winSum=452
1943 10:04:57.383440 TX Vref=32, minBit 2, minWin=27, winSum=451
1944 10:04:57.389850 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 30
1945 10:04:57.389958
1946 10:04:57.393689 Final TX Range 1 Vref 30
1947 10:04:57.393778
1948 10:04:57.393845 ==
1949 10:04:57.396629 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 10:04:57.399884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 10:04:57.399976 ==
1952 10:04:57.400044
1953 10:04:57.400104
1954 10:04:57.403240 TX Vref Scan disable
1955 10:04:57.406668 == TX Byte 0 ==
1956 10:04:57.409918 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1957 10:04:57.413294 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1958 10:04:57.417056 == TX Byte 1 ==
1959 10:04:57.419993 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1960 10:04:57.423500 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1961 10:04:57.423595
1962 10:04:57.426634 [DATLAT]
1963 10:04:57.426719 Freq=800, CH1 RK1
1964 10:04:57.426786
1965 10:04:57.430007 DATLAT Default: 0xa
1966 10:04:57.430093 0, 0xFFFF, sum = 0
1967 10:04:57.433209 1, 0xFFFF, sum = 0
1968 10:04:57.433297 2, 0xFFFF, sum = 0
1969 10:04:57.436534 3, 0xFFFF, sum = 0
1970 10:04:57.436621 4, 0xFFFF, sum = 0
1971 10:04:57.440394 5, 0xFFFF, sum = 0
1972 10:04:57.440483 6, 0xFFFF, sum = 0
1973 10:04:57.443443 7, 0xFFFF, sum = 0
1974 10:04:57.443530 8, 0xFFFF, sum = 0
1975 10:04:57.446602 9, 0x0, sum = 1
1976 10:04:57.446689 10, 0x0, sum = 2
1977 10:04:57.450114 11, 0x0, sum = 3
1978 10:04:57.450201 12, 0x0, sum = 4
1979 10:04:57.453133 best_step = 10
1980 10:04:57.453218
1981 10:04:57.453285 ==
1982 10:04:57.456485 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 10:04:57.460293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 10:04:57.460384 ==
1985 10:04:57.463356 RX Vref Scan: 0
1986 10:04:57.463442
1987 10:04:57.463509 RX Vref 0 -> 0, step: 1
1988 10:04:57.463572
1989 10:04:57.466546 RX Delay -79 -> 252, step: 8
1990 10:04:57.473520 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1991 10:04:57.476723 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1992 10:04:57.480148 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1993 10:04:57.483131 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1994 10:04:57.486669 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1995 10:04:57.490529 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1996 10:04:57.496951 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1997 10:04:57.500180 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1998 10:04:57.503310 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1999 10:04:57.506763 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2000 10:04:57.509865 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
2001 10:04:57.516624 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
2002 10:04:57.519832 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2003 10:04:57.523361 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2004 10:04:57.526750 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2005 10:04:57.530471 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2006 10:04:57.530558 ==
2007 10:04:57.533313 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 10:04:57.540192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 10:04:57.540311 ==
2010 10:04:57.540381 DQS Delay:
2011 10:04:57.543912 DQS0 = 0, DQS1 = 0
2012 10:04:57.543997 DQM Delay:
2013 10:04:57.544062 DQM0 = 97, DQM1 = 89
2014 10:04:57.546935 DQ Delay:
2015 10:04:57.550109 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2016 10:04:57.553430 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2017 10:04:57.556686 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =80
2018 10:04:57.560176 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2019 10:04:57.560267
2020 10:04:57.560332
2021 10:04:57.566974 [DQSOSCAuto] RK1, (LSB)MR18= 0x4812, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2022 10:04:57.570033 CH1 RK1: MR19=606, MR18=4812
2023 10:04:57.577332 CH1_RK1: MR19=0x606, MR18=0x4812, DQSOSC=391, MR23=63, INC=96, DEC=64
2024 10:04:57.580983 [RxdqsGatingPostProcess] freq 800
2025 10:04:57.583503 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2026 10:04:57.587129 Pre-setting of DQS Precalculation
2027 10:04:57.593839 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2028 10:04:57.600467 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2029 10:04:57.607168 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2030 10:04:57.607291
2031 10:04:57.607363
2032 10:04:57.610333 [Calibration Summary] 1600 Mbps
2033 10:04:57.610426 CH 0, Rank 0
2034 10:04:57.613211 SW Impedance : PASS
2035 10:04:57.616817 DUTY Scan : NO K
2036 10:04:57.616936 ZQ Calibration : PASS
2037 10:04:57.620367 Jitter Meter : NO K
2038 10:04:57.623760 CBT Training : PASS
2039 10:04:57.623848 Write leveling : PASS
2040 10:04:57.626965 RX DQS gating : PASS
2041 10:04:57.627050 RX DQ/DQS(RDDQC) : PASS
2042 10:04:57.630397 TX DQ/DQS : PASS
2043 10:04:57.634156 RX DATLAT : PASS
2044 10:04:57.634246 RX DQ/DQS(Engine): PASS
2045 10:04:57.637220 TX OE : NO K
2046 10:04:57.637306 All Pass.
2047 10:04:57.637371
2048 10:04:57.640598 CH 0, Rank 1
2049 10:04:57.640683 SW Impedance : PASS
2050 10:04:57.643903 DUTY Scan : NO K
2051 10:04:57.647005 ZQ Calibration : PASS
2052 10:04:57.647092 Jitter Meter : NO K
2053 10:04:57.650355 CBT Training : PASS
2054 10:04:57.654067 Write leveling : PASS
2055 10:04:57.654155 RX DQS gating : PASS
2056 10:04:57.656919 RX DQ/DQS(RDDQC) : PASS
2057 10:04:57.660329 TX DQ/DQS : PASS
2058 10:04:57.660417 RX DATLAT : PASS
2059 10:04:57.663836 RX DQ/DQS(Engine): PASS
2060 10:04:57.667428 TX OE : NO K
2061 10:04:57.667517 All Pass.
2062 10:04:57.667584
2063 10:04:57.667645 CH 1, Rank 0
2064 10:04:57.670325 SW Impedance : PASS
2065 10:04:57.670409 DUTY Scan : NO K
2066 10:04:57.673713 ZQ Calibration : PASS
2067 10:04:57.677591 Jitter Meter : NO K
2068 10:04:57.677682 CBT Training : PASS
2069 10:04:57.680631 Write leveling : PASS
2070 10:04:57.683999 RX DQS gating : PASS
2071 10:04:57.684087 RX DQ/DQS(RDDQC) : PASS
2072 10:04:57.687146 TX DQ/DQS : PASS
2073 10:04:57.690443 RX DATLAT : PASS
2074 10:04:57.690552 RX DQ/DQS(Engine): PASS
2075 10:04:57.694000 TX OE : NO K
2076 10:04:57.694086 All Pass.
2077 10:04:57.694151
2078 10:04:57.696965 CH 1, Rank 1
2079 10:04:57.697049 SW Impedance : PASS
2080 10:04:57.700634 DUTY Scan : NO K
2081 10:04:57.703970 ZQ Calibration : PASS
2082 10:04:57.704058 Jitter Meter : NO K
2083 10:04:57.707731 CBT Training : PASS
2084 10:04:57.707817 Write leveling : PASS
2085 10:04:57.710338 RX DQS gating : PASS
2086 10:04:57.714138 RX DQ/DQS(RDDQC) : PASS
2087 10:04:57.714227 TX DQ/DQS : PASS
2088 10:04:57.717329 RX DATLAT : PASS
2089 10:04:57.721158 RX DQ/DQS(Engine): PASS
2090 10:04:57.721246 TX OE : NO K
2091 10:04:57.723678 All Pass.
2092 10:04:57.723760
2093 10:04:57.723827 DramC Write-DBI off
2094 10:04:57.727118 PER_BANK_REFRESH: Hybrid Mode
2095 10:04:57.730392 TX_TRACKING: ON
2096 10:04:57.733945 [GetDramInforAfterCalByMRR] Vendor 6.
2097 10:04:57.737309 [GetDramInforAfterCalByMRR] Revision 606.
2098 10:04:57.740794 [GetDramInforAfterCalByMRR] Revision 2 0.
2099 10:04:57.740890 MR0 0x3b3b
2100 10:04:57.740959 MR8 0x5151
2101 10:04:57.744296 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2102 10:04:57.744380
2103 10:04:57.747299 MR0 0x3b3b
2104 10:04:57.747398 MR8 0x5151
2105 10:04:57.750923 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2106 10:04:57.751008
2107 10:04:57.760485 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2108 10:04:57.763934 [FAST_K] Save calibration result to emmc
2109 10:04:57.767190 [FAST_K] Save calibration result to emmc
2110 10:04:57.770427 dram_init: config_dvfs: 1
2111 10:04:57.774164 dramc_set_vcore_voltage set vcore to 662500
2112 10:04:57.777078 Read voltage for 1200, 2
2113 10:04:57.777168 Vio18 = 0
2114 10:04:57.777234 Vcore = 662500
2115 10:04:57.780943 Vdram = 0
2116 10:04:57.781029 Vddq = 0
2117 10:04:57.781094 Vmddr = 0
2118 10:04:57.787319 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2119 10:04:57.790655 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2120 10:04:57.794090 MEM_TYPE=3, freq_sel=15
2121 10:04:57.797373 sv_algorithm_assistance_LP4_1600
2122 10:04:57.800798 ============ PULL DRAM RESETB DOWN ============
2123 10:04:57.804285 ========== PULL DRAM RESETB DOWN end =========
2124 10:04:57.811332 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2125 10:04:57.814402 ===================================
2126 10:04:57.814496 LPDDR4 DRAM CONFIGURATION
2127 10:04:57.817296 ===================================
2128 10:04:57.821102 EX_ROW_EN[0] = 0x0
2129 10:04:57.824198 EX_ROW_EN[1] = 0x0
2130 10:04:57.824283 LP4Y_EN = 0x0
2131 10:04:57.827142 WORK_FSP = 0x0
2132 10:04:57.827225 WL = 0x4
2133 10:04:57.830723 RL = 0x4
2134 10:04:57.830807 BL = 0x2
2135 10:04:57.834287 RPST = 0x0
2136 10:04:57.834371 RD_PRE = 0x0
2137 10:04:57.837647 WR_PRE = 0x1
2138 10:04:57.837742 WR_PST = 0x0
2139 10:04:57.840591 DBI_WR = 0x0
2140 10:04:57.840674 DBI_RD = 0x0
2141 10:04:57.844274 OTF = 0x1
2142 10:04:57.847232 ===================================
2143 10:04:57.851109 ===================================
2144 10:04:57.851197 ANA top config
2145 10:04:57.854042 ===================================
2146 10:04:57.857503 DLL_ASYNC_EN = 0
2147 10:04:57.860952 ALL_SLAVE_EN = 0
2148 10:04:57.861047 NEW_RANK_MODE = 1
2149 10:04:57.864357 DLL_IDLE_MODE = 1
2150 10:04:57.867977 LP45_APHY_COMB_EN = 1
2151 10:04:57.870921 TX_ODT_DIS = 1
2152 10:04:57.874152 NEW_8X_MODE = 1
2153 10:04:57.877306 ===================================
2154 10:04:57.880924 ===================================
2155 10:04:57.881028 data_rate = 2400
2156 10:04:57.883954 CKR = 1
2157 10:04:57.887314 DQ_P2S_RATIO = 8
2158 10:04:57.890628 ===================================
2159 10:04:57.894357 CA_P2S_RATIO = 8
2160 10:04:57.897449 DQ_CA_OPEN = 0
2161 10:04:57.897536 DQ_SEMI_OPEN = 0
2162 10:04:57.900755 CA_SEMI_OPEN = 0
2163 10:04:57.904009 CA_FULL_RATE = 0
2164 10:04:57.907696 DQ_CKDIV4_EN = 0
2165 10:04:57.911336 CA_CKDIV4_EN = 0
2166 10:04:57.914283 CA_PREDIV_EN = 0
2167 10:04:57.914373 PH8_DLY = 17
2168 10:04:57.917486 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2169 10:04:57.921098 DQ_AAMCK_DIV = 4
2170 10:04:57.924046 CA_AAMCK_DIV = 4
2171 10:04:57.927373 CA_ADMCK_DIV = 4
2172 10:04:57.931586 DQ_TRACK_CA_EN = 0
2173 10:04:57.931678 CA_PICK = 1200
2174 10:04:57.934241 CA_MCKIO = 1200
2175 10:04:57.937419 MCKIO_SEMI = 0
2176 10:04:57.940896 PLL_FREQ = 2366
2177 10:04:57.944375 DQ_UI_PI_RATIO = 32
2178 10:04:57.947955 CA_UI_PI_RATIO = 0
2179 10:04:57.951070 ===================================
2180 10:04:57.954061 ===================================
2181 10:04:57.957506 memory_type:LPDDR4
2182 10:04:57.957597 GP_NUM : 10
2183 10:04:57.961223 SRAM_EN : 1
2184 10:04:57.961309 MD32_EN : 0
2185 10:04:57.964498 ===================================
2186 10:04:57.967440 [ANA_INIT] >>>>>>>>>>>>>>
2187 10:04:57.971107 <<<<<< [CONFIGURE PHASE]: ANA_TX
2188 10:04:57.974616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2189 10:04:57.977788 ===================================
2190 10:04:57.980987 data_rate = 2400,PCW = 0X5b00
2191 10:04:57.984371 ===================================
2192 10:04:57.987770 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2193 10:04:57.990863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2194 10:04:57.997888 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2195 10:04:58.001415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2196 10:04:58.004155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2197 10:04:58.007694 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2198 10:04:58.011021 [ANA_INIT] flow start
2199 10:04:58.014445 [ANA_INIT] PLL >>>>>>>>
2200 10:04:58.014535 [ANA_INIT] PLL <<<<<<<<
2201 10:04:58.017572 [ANA_INIT] MIDPI >>>>>>>>
2202 10:04:58.021099 [ANA_INIT] MIDPI <<<<<<<<
2203 10:04:58.024506 [ANA_INIT] DLL >>>>>>>>
2204 10:04:58.024595 [ANA_INIT] DLL <<<<<<<<
2205 10:04:58.027735 [ANA_INIT] flow end
2206 10:04:58.030687 ============ LP4 DIFF to SE enter ============
2207 10:04:58.034307 ============ LP4 DIFF to SE exit ============
2208 10:04:58.037876 [ANA_INIT] <<<<<<<<<<<<<
2209 10:04:58.041089 [Flow] Enable top DCM control >>>>>
2210 10:04:58.044570 [Flow] Enable top DCM control <<<<<
2211 10:04:58.047849 Enable DLL master slave shuffle
2212 10:04:58.054304 ==============================================================
2213 10:04:58.054401 Gating Mode config
2214 10:04:58.061037 ==============================================================
2215 10:04:58.061140 Config description:
2216 10:04:58.070879 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2217 10:04:58.077804 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2218 10:04:58.084523 SELPH_MODE 0: By rank 1: By Phase
2219 10:04:58.087566 ==============================================================
2220 10:04:58.091217 GAT_TRACK_EN = 1
2221 10:04:58.094838 RX_GATING_MODE = 2
2222 10:04:58.097983 RX_GATING_TRACK_MODE = 2
2223 10:04:58.101229 SELPH_MODE = 1
2224 10:04:58.104659 PICG_EARLY_EN = 1
2225 10:04:58.108416 VALID_LAT_VALUE = 1
2226 10:04:58.111555 ==============================================================
2227 10:04:58.114847 Enter into Gating configuration >>>>
2228 10:04:58.118016 Exit from Gating configuration <<<<
2229 10:04:58.121114 Enter into DVFS_PRE_config >>>>>
2230 10:04:58.131341 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2231 10:04:58.134695 Exit from DVFS_PRE_config <<<<<
2232 10:04:58.137877 Enter into PICG configuration >>>>
2233 10:04:58.141734 Exit from PICG configuration <<<<
2234 10:04:58.144647 [RX_INPUT] configuration >>>>>
2235 10:04:58.148184 [RX_INPUT] configuration <<<<<
2236 10:04:58.154888 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2237 10:04:58.158224 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2238 10:04:58.164601 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 10:04:58.171599 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 10:04:58.178794 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 10:04:58.181730 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 10:04:58.188679 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2243 10:04:58.192005 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2244 10:04:58.195445 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2245 10:04:58.198363 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2246 10:04:58.201830 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2247 10:04:58.208628 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2248 10:04:58.212300 ===================================
2249 10:04:58.215384 LPDDR4 DRAM CONFIGURATION
2250 10:04:58.218874 ===================================
2251 10:04:58.218966 EX_ROW_EN[0] = 0x0
2252 10:04:58.221822 EX_ROW_EN[1] = 0x0
2253 10:04:58.221905 LP4Y_EN = 0x0
2254 10:04:58.225136 WORK_FSP = 0x0
2255 10:04:58.225222 WL = 0x4
2256 10:04:58.229031 RL = 0x4
2257 10:04:58.229117 BL = 0x2
2258 10:04:58.232039 RPST = 0x0
2259 10:04:58.232124 RD_PRE = 0x0
2260 10:04:58.235420 WR_PRE = 0x1
2261 10:04:58.235512 WR_PST = 0x0
2262 10:04:58.238763 DBI_WR = 0x0
2263 10:04:58.238846 DBI_RD = 0x0
2264 10:04:58.242192 OTF = 0x1
2265 10:04:58.245121 ===================================
2266 10:04:58.248592 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2267 10:04:58.252246 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2268 10:04:58.258611 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2269 10:04:58.262073 ===================================
2270 10:04:58.262171 LPDDR4 DRAM CONFIGURATION
2271 10:04:58.265988 ===================================
2272 10:04:58.268636 EX_ROW_EN[0] = 0x10
2273 10:04:58.271846 EX_ROW_EN[1] = 0x0
2274 10:04:58.271931 LP4Y_EN = 0x0
2275 10:04:58.275333 WORK_FSP = 0x0
2276 10:04:58.275417 WL = 0x4
2277 10:04:58.278909 RL = 0x4
2278 10:04:58.278995 BL = 0x2
2279 10:04:58.281979 RPST = 0x0
2280 10:04:58.282064 RD_PRE = 0x0
2281 10:04:58.285276 WR_PRE = 0x1
2282 10:04:58.285364 WR_PST = 0x0
2283 10:04:58.288782 DBI_WR = 0x0
2284 10:04:58.288906 DBI_RD = 0x0
2285 10:04:58.291852 OTF = 0x1
2286 10:04:58.295119 ===================================
2287 10:04:58.301899 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2288 10:04:58.302010 ==
2289 10:04:58.305220 Dram Type= 6, Freq= 0, CH_0, rank 0
2290 10:04:58.308489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2291 10:04:58.308583 ==
2292 10:04:58.311808 [Duty_Offset_Calibration]
2293 10:04:58.311902 B0:2 B1:1 CA:1
2294 10:04:58.311967
2295 10:04:58.315223 [DutyScan_Calibration_Flow] k_type=0
2296 10:04:58.325102
2297 10:04:58.325230 ==CLK 0==
2298 10:04:58.328498 Final CLK duty delay cell = 0
2299 10:04:58.331871 [0] MAX Duty = 5187%(X100), DQS PI = 24
2300 10:04:58.335600 [0] MIN Duty = 4844%(X100), DQS PI = 48
2301 10:04:58.335690 [0] AVG Duty = 5015%(X100)
2302 10:04:58.338359
2303 10:04:58.342097 CH0 CLK Duty spec in!! Max-Min= 343%
2304 10:04:58.345080 [DutyScan_Calibration_Flow] ====Done====
2305 10:04:58.345168
2306 10:04:58.348311 [DutyScan_Calibration_Flow] k_type=1
2307 10:04:58.363013
2308 10:04:58.363158 ==DQS 0 ==
2309 10:04:58.366718 Final DQS duty delay cell = -4
2310 10:04:58.369378 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2311 10:04:58.372799 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2312 10:04:58.376484 [-4] AVG Duty = 4953%(X100)
2313 10:04:58.376574
2314 10:04:58.376639 ==DQS 1 ==
2315 10:04:58.379539 Final DQS duty delay cell = -4
2316 10:04:58.382984 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2317 10:04:58.386278 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2318 10:04:58.390034 [-4] AVG Duty = 4906%(X100)
2319 10:04:58.390125
2320 10:04:58.392851 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2321 10:04:58.392936
2322 10:04:58.396421 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2323 10:04:58.399710 [DutyScan_Calibration_Flow] ====Done====
2324 10:04:58.399800
2325 10:04:58.402666 [DutyScan_Calibration_Flow] k_type=3
2326 10:04:58.420402
2327 10:04:58.420558 ==DQM 0 ==
2328 10:04:58.423417 Final DQM duty delay cell = 0
2329 10:04:58.426987 [0] MAX Duty = 5156%(X100), DQS PI = 26
2330 10:04:58.430528 [0] MIN Duty = 4906%(X100), DQS PI = 50
2331 10:04:58.430620 [0] AVG Duty = 5031%(X100)
2332 10:04:58.433941
2333 10:04:58.434027 ==DQM 1 ==
2334 10:04:58.437074 Final DQM duty delay cell = 0
2335 10:04:58.440243 [0] MAX Duty = 5124%(X100), DQS PI = 8
2336 10:04:58.443421 [0] MIN Duty = 5031%(X100), DQS PI = 34
2337 10:04:58.443512 [0] AVG Duty = 5077%(X100)
2338 10:04:58.446672
2339 10:04:58.450067 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2340 10:04:58.450154
2341 10:04:58.453937 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2342 10:04:58.457036 [DutyScan_Calibration_Flow] ====Done====
2343 10:04:58.457125
2344 10:04:58.460267 [DutyScan_Calibration_Flow] k_type=2
2345 10:04:58.476682
2346 10:04:58.476841 ==DQ 0 ==
2347 10:04:58.480001 Final DQ duty delay cell = 0
2348 10:04:58.482897 [0] MAX Duty = 5062%(X100), DQS PI = 32
2349 10:04:58.486382 [0] MIN Duty = 4906%(X100), DQS PI = 0
2350 10:04:58.486468 [0] AVG Duty = 4984%(X100)
2351 10:04:58.486533
2352 10:04:58.489946 ==DQ 1 ==
2353 10:04:58.492903 Final DQ duty delay cell = 0
2354 10:04:58.496517 [0] MAX Duty = 5093%(X100), DQS PI = 8
2355 10:04:58.500011 [0] MIN Duty = 4938%(X100), DQS PI = 36
2356 10:04:58.500105 [0] AVG Duty = 5015%(X100)
2357 10:04:58.500170
2358 10:04:58.502966 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2359 10:04:58.503050
2360 10:04:58.506720 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2361 10:04:58.513161 [DutyScan_Calibration_Flow] ====Done====
2362 10:04:58.513275 ==
2363 10:04:58.516380 Dram Type= 6, Freq= 0, CH_1, rank 0
2364 10:04:58.519900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2365 10:04:58.520017 ==
2366 10:04:58.523062 [Duty_Offset_Calibration]
2367 10:04:58.523145 B0:1 B1:0 CA:1
2368 10:04:58.523208
2369 10:04:58.526580 [DutyScan_Calibration_Flow] k_type=0
2370 10:04:58.535636
2371 10:04:58.535757 ==CLK 0==
2372 10:04:58.539192 Final CLK duty delay cell = -4
2373 10:04:58.542193 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2374 10:04:58.546104 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2375 10:04:58.549044 [-4] AVG Duty = 4969%(X100)
2376 10:04:58.549134
2377 10:04:58.552208 CH1 CLK Duty spec in!! Max-Min= 124%
2378 10:04:58.555523 [DutyScan_Calibration_Flow] ====Done====
2379 10:04:58.555641
2380 10:04:58.558750 [DutyScan_Calibration_Flow] k_type=1
2381 10:04:58.575416
2382 10:04:58.575572 ==DQS 0 ==
2383 10:04:58.578705 Final DQS duty delay cell = 0
2384 10:04:58.582491 [0] MAX Duty = 5094%(X100), DQS PI = 24
2385 10:04:58.585542 [0] MIN Duty = 4875%(X100), DQS PI = 0
2386 10:04:58.585629 [0] AVG Duty = 4984%(X100)
2387 10:04:58.588756
2388 10:04:58.588903 ==DQS 1 ==
2389 10:04:58.592337 Final DQS duty delay cell = 0
2390 10:04:58.595833 [0] MAX Duty = 5218%(X100), DQS PI = 20
2391 10:04:58.599120 [0] MIN Duty = 4969%(X100), DQS PI = 10
2392 10:04:58.599235 [0] AVG Duty = 5093%(X100)
2393 10:04:58.602603
2394 10:04:58.605264 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2395 10:04:58.605352
2396 10:04:58.608551 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2397 10:04:58.611978 [DutyScan_Calibration_Flow] ====Done====
2398 10:04:58.612072
2399 10:04:58.615404 [DutyScan_Calibration_Flow] k_type=3
2400 10:04:58.632180
2401 10:04:58.632334 ==DQM 0 ==
2402 10:04:58.635505 Final DQM duty delay cell = 0
2403 10:04:58.638508 [0] MAX Duty = 5156%(X100), DQS PI = 6
2404 10:04:58.641748 [0] MIN Duty = 5031%(X100), DQS PI = 0
2405 10:04:58.641837 [0] AVG Duty = 5093%(X100)
2406 10:04:58.641904
2407 10:04:58.645062 ==DQM 1 ==
2408 10:04:58.648633 Final DQM duty delay cell = 0
2409 10:04:58.652159 [0] MAX Duty = 5062%(X100), DQS PI = 28
2410 10:04:58.655194 [0] MIN Duty = 4907%(X100), DQS PI = 36
2411 10:04:58.655282 [0] AVG Duty = 4984%(X100)
2412 10:04:58.655350
2413 10:04:58.661664 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2414 10:04:58.661772
2415 10:04:58.665265 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2416 10:04:58.668710 [DutyScan_Calibration_Flow] ====Done====
2417 10:04:58.668840
2418 10:04:58.671652 [DutyScan_Calibration_Flow] k_type=2
2419 10:04:58.687359
2420 10:04:58.687508 ==DQ 0 ==
2421 10:04:58.690943 Final DQ duty delay cell = -4
2422 10:04:58.694300 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2423 10:04:58.697512 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2424 10:04:58.700688 [-4] AVG Duty = 5000%(X100)
2425 10:04:58.700812
2426 10:04:58.700892 ==DQ 1 ==
2427 10:04:58.704389 Final DQ duty delay cell = 0
2428 10:04:58.707871 [0] MAX Duty = 5125%(X100), DQS PI = 20
2429 10:04:58.710562 [0] MIN Duty = 4969%(X100), DQS PI = 12
2430 10:04:58.714370 [0] AVG Duty = 5047%(X100)
2431 10:04:58.714464
2432 10:04:58.717537 CH1 DQ 0 Duty spec in!! Max-Min= 188%
2433 10:04:58.717622
2434 10:04:58.720948 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2435 10:04:58.724363 [DutyScan_Calibration_Flow] ====Done====
2436 10:04:58.727629 nWR fixed to 30
2437 10:04:58.727720 [ModeRegInit_LP4] CH0 RK0
2438 10:04:58.730685 [ModeRegInit_LP4] CH0 RK1
2439 10:04:58.734669 [ModeRegInit_LP4] CH1 RK0
2440 10:04:58.737575 [ModeRegInit_LP4] CH1 RK1
2441 10:04:58.737666 match AC timing 7
2442 10:04:58.740959 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2443 10:04:58.747492 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2444 10:04:58.751311 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2445 10:04:58.754596 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2446 10:04:58.761484 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2447 10:04:58.761598 ==
2448 10:04:58.764262 Dram Type= 6, Freq= 0, CH_0, rank 0
2449 10:04:58.767956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2450 10:04:58.768047 ==
2451 10:04:58.774490 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2452 10:04:58.777789 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2453 10:04:58.787597 [CA 0] Center 39 (8~70) winsize 63
2454 10:04:58.791464 [CA 1] Center 39 (8~70) winsize 63
2455 10:04:58.794355 [CA 2] Center 35 (5~66) winsize 62
2456 10:04:58.797908 [CA 3] Center 34 (4~65) winsize 62
2457 10:04:58.801356 [CA 4] Center 33 (3~64) winsize 62
2458 10:04:58.804549 [CA 5] Center 32 (3~62) winsize 60
2459 10:04:58.804637
2460 10:04:58.807574 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2461 10:04:58.807660
2462 10:04:58.811055 [CATrainingPosCal] consider 1 rank data
2463 10:04:58.814452 u2DelayCellTimex100 = 270/100 ps
2464 10:04:58.818020 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2465 10:04:58.821369 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2466 10:04:58.827634 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2467 10:04:58.830854 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2468 10:04:58.834342 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2469 10:04:58.837624 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2470 10:04:58.837716
2471 10:04:58.841546 CA PerBit enable=1, Macro0, CA PI delay=32
2472 10:04:58.841635
2473 10:04:58.844273 [CBTSetCACLKResult] CA Dly = 32
2474 10:04:58.844359 CS Dly: 6 (0~37)
2475 10:04:58.847821 ==
2476 10:04:58.847910 Dram Type= 6, Freq= 0, CH_0, rank 1
2477 10:04:58.854308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2478 10:04:58.854405 ==
2479 10:04:58.857678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2480 10:04:58.864122 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2481 10:04:58.874044 [CA 0] Center 38 (8~69) winsize 62
2482 10:04:58.876756 [CA 1] Center 38 (8~69) winsize 62
2483 10:04:58.880423 [CA 2] Center 35 (4~66) winsize 63
2484 10:04:58.883631 [CA 3] Center 34 (4~65) winsize 62
2485 10:04:58.887095 [CA 4] Center 33 (3~64) winsize 62
2486 10:04:58.890465 [CA 5] Center 32 (3~62) winsize 60
2487 10:04:58.890558
2488 10:04:58.893928 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2489 10:04:58.894014
2490 10:04:58.896998 [CATrainingPosCal] consider 2 rank data
2491 10:04:58.900083 u2DelayCellTimex100 = 270/100 ps
2492 10:04:58.903549 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2493 10:04:58.907024 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2494 10:04:58.913941 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2495 10:04:58.916979 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2496 10:04:58.920323 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2497 10:04:58.923648 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2498 10:04:58.923736
2499 10:04:58.927170 CA PerBit enable=1, Macro0, CA PI delay=32
2500 10:04:58.927256
2501 10:04:58.930522 [CBTSetCACLKResult] CA Dly = 32
2502 10:04:58.930609 CS Dly: 6 (0~38)
2503 10:04:58.930675
2504 10:04:58.934101 ----->DramcWriteLeveling(PI) begin...
2505 10:04:58.934187 ==
2506 10:04:58.936818 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 10:04:58.943650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 10:04:58.943749 ==
2509 10:04:58.947069 Write leveling (Byte 0): 35 => 35
2510 10:04:58.951168 Write leveling (Byte 1): 29 => 29
2511 10:04:58.951257 DramcWriteLeveling(PI) end<-----
2512 10:04:58.951324
2513 10:04:58.954671 ==
2514 10:04:58.957167 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 10:04:58.960466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 10:04:58.960553 ==
2517 10:04:58.963696 [Gating] SW mode calibration
2518 10:04:58.970808 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2519 10:04:58.973894 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2520 10:04:58.980488 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
2521 10:04:58.984070 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2522 10:04:58.987722 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 10:04:58.994475 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 10:04:58.997898 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 10:04:59.000523 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 10:04:59.007540 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2527 10:04:59.010938 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (1 0)
2528 10:04:59.014294 1 0 0 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
2529 10:04:59.017233 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 10:04:59.024240 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 10:04:59.027902 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 10:04:59.030514 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 10:04:59.037276 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 10:04:59.040737 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
2535 10:04:59.044316 1 0 28 | B1->B0 | 2a2a 4444 | 0 0 | (0 0) (0 0)
2536 10:04:59.050748 1 1 0 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
2537 10:04:59.054519 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 10:04:59.057379 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 10:04:59.064625 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 10:04:59.067628 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 10:04:59.071263 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 10:04:59.077829 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 10:04:59.081061 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2544 10:04:59.084101 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2545 10:04:59.087438 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2546 10:04:59.094620 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 10:04:59.097984 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 10:04:59.100992 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 10:04:59.107640 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 10:04:59.111062 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 10:04:59.114634 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 10:04:59.120751 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 10:04:59.124182 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 10:04:59.127760 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 10:04:59.134811 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 10:04:59.137586 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 10:04:59.141213 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 10:04:59.147516 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 10:04:59.150711 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2560 10:04:59.154444 Total UI for P1: 0, mck2ui 16
2561 10:04:59.157797 best dqsien dly found for B0: ( 1, 3, 26)
2562 10:04:59.161308 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2563 10:04:59.168076 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2564 10:04:59.171261 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 10:04:59.174208 Total UI for P1: 0, mck2ui 16
2566 10:04:59.177994 best dqsien dly found for B1: ( 1, 4, 0)
2567 10:04:59.181018 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2568 10:04:59.184298 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2569 10:04:59.184388
2570 10:04:59.187779 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2571 10:04:59.190947 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2572 10:04:59.194314 [Gating] SW calibration Done
2573 10:04:59.194404 ==
2574 10:04:59.197833 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 10:04:59.201000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 10:04:59.201091 ==
2577 10:04:59.204374 RX Vref Scan: 0
2578 10:04:59.204459
2579 10:04:59.207537 RX Vref 0 -> 0, step: 1
2580 10:04:59.207625
2581 10:04:59.207692 RX Delay -40 -> 252, step: 8
2582 10:04:59.214332 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
2583 10:04:59.217814 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2584 10:04:59.220668 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2585 10:04:59.224111 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2586 10:04:59.227520 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2587 10:04:59.234108 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2588 10:04:59.237885 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2589 10:04:59.240639 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2590 10:04:59.244545 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2591 10:04:59.247478 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2592 10:04:59.251303 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2593 10:04:59.257660 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2594 10:04:59.260945 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2595 10:04:59.264248 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2596 10:04:59.267702 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2597 10:04:59.274193 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2598 10:04:59.274304 ==
2599 10:04:59.277991 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 10:04:59.280988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 10:04:59.281080 ==
2602 10:04:59.281148 DQS Delay:
2603 10:04:59.284077 DQS0 = 0, DQS1 = 0
2604 10:04:59.284163 DQM Delay:
2605 10:04:59.287703 DQM0 = 122, DQM1 = 114
2606 10:04:59.287790 DQ Delay:
2607 10:04:59.291065 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2608 10:04:59.294692 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2609 10:04:59.297539 DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107
2610 10:04:59.301143 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2611 10:04:59.301239
2612 10:04:59.301308
2613 10:04:59.301368 ==
2614 10:04:59.304228 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 10:04:59.310983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 10:04:59.311106 ==
2617 10:04:59.311174
2618 10:04:59.311235
2619 10:04:59.311296 TX Vref Scan disable
2620 10:04:59.314570 == TX Byte 0 ==
2621 10:04:59.318008 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2622 10:04:59.321044 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2623 10:04:59.324534 == TX Byte 1 ==
2624 10:04:59.328242 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2625 10:04:59.331426 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2626 10:04:59.335188 ==
2627 10:04:59.338384 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 10:04:59.341113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 10:04:59.341202 ==
2630 10:04:59.353043 TX Vref=22, minBit 7, minWin=24, winSum=408
2631 10:04:59.356088 TX Vref=24, minBit 0, minWin=25, winSum=414
2632 10:04:59.359806 TX Vref=26, minBit 0, minWin=25, winSum=418
2633 10:04:59.363106 TX Vref=28, minBit 0, minWin=26, winSum=422
2634 10:04:59.366133 TX Vref=30, minBit 4, minWin=25, winSum=421
2635 10:04:59.370082 TX Vref=32, minBit 0, minWin=26, winSum=422
2636 10:04:59.376063 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 28
2637 10:04:59.376164
2638 10:04:59.379595 Final TX Range 1 Vref 28
2639 10:04:59.379683
2640 10:04:59.379749 ==
2641 10:04:59.382743 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 10:04:59.386590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 10:04:59.386681 ==
2644 10:04:59.386749
2645 10:04:59.389813
2646 10:04:59.389900 TX Vref Scan disable
2647 10:04:59.392960 == TX Byte 0 ==
2648 10:04:59.396239 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2649 10:04:59.399724 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2650 10:04:59.403123 == TX Byte 1 ==
2651 10:04:59.406482 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2652 10:04:59.410192 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2653 10:04:59.410287
2654 10:04:59.413075 [DATLAT]
2655 10:04:59.413165 Freq=1200, CH0 RK0
2656 10:04:59.413236
2657 10:04:59.416540 DATLAT Default: 0xd
2658 10:04:59.416648 0, 0xFFFF, sum = 0
2659 10:04:59.419649 1, 0xFFFF, sum = 0
2660 10:04:59.419734 2, 0xFFFF, sum = 0
2661 10:04:59.423446 3, 0xFFFF, sum = 0
2662 10:04:59.423547 4, 0xFFFF, sum = 0
2663 10:04:59.426349 5, 0xFFFF, sum = 0
2664 10:04:59.426434 6, 0xFFFF, sum = 0
2665 10:04:59.429985 7, 0xFFFF, sum = 0
2666 10:04:59.430072 8, 0xFFFF, sum = 0
2667 10:04:59.432749 9, 0xFFFF, sum = 0
2668 10:04:59.432842 10, 0xFFFF, sum = 0
2669 10:04:59.436398 11, 0xFFFF, sum = 0
2670 10:04:59.439620 12, 0x0, sum = 1
2671 10:04:59.439709 13, 0x0, sum = 2
2672 10:04:59.439776 14, 0x0, sum = 3
2673 10:04:59.443113 15, 0x0, sum = 4
2674 10:04:59.443198 best_step = 13
2675 10:04:59.443264
2676 10:04:59.443323 ==
2677 10:04:59.446480 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 10:04:59.453108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 10:04:59.453216 ==
2680 10:04:59.453286 RX Vref Scan: 1
2681 10:04:59.453346
2682 10:04:59.456652 Set Vref Range= 32 -> 127
2683 10:04:59.456737
2684 10:04:59.459518 RX Vref 32 -> 127, step: 1
2685 10:04:59.459603
2686 10:04:59.462960 RX Delay -13 -> 252, step: 4
2687 10:04:59.463045
2688 10:04:59.466436 Set Vref, RX VrefLevel [Byte0]: 32
2689 10:04:59.469859 [Byte1]: 32
2690 10:04:59.469948
2691 10:04:59.473080 Set Vref, RX VrefLevel [Byte0]: 33
2692 10:04:59.476503 [Byte1]: 33
2693 10:04:59.476588
2694 10:04:59.480061 Set Vref, RX VrefLevel [Byte0]: 34
2695 10:04:59.482936 [Byte1]: 34
2696 10:04:59.486935
2697 10:04:59.487025 Set Vref, RX VrefLevel [Byte0]: 35
2698 10:04:59.490039 [Byte1]: 35
2699 10:04:59.495163
2700 10:04:59.495257 Set Vref, RX VrefLevel [Byte0]: 36
2701 10:04:59.498286 [Byte1]: 36
2702 10:04:59.503036
2703 10:04:59.503135 Set Vref, RX VrefLevel [Byte0]: 37
2704 10:04:59.506031 [Byte1]: 37
2705 10:04:59.510675
2706 10:04:59.510765 Set Vref, RX VrefLevel [Byte0]: 38
2707 10:04:59.513983 [Byte1]: 38
2708 10:04:59.518640
2709 10:04:59.518734 Set Vref, RX VrefLevel [Byte0]: 39
2710 10:04:59.521916 [Byte1]: 39
2711 10:04:59.526186
2712 10:04:59.526278 Set Vref, RX VrefLevel [Byte0]: 40
2713 10:04:59.529676 [Byte1]: 40
2714 10:04:59.534192
2715 10:04:59.534286 Set Vref, RX VrefLevel [Byte0]: 41
2716 10:04:59.538003 [Byte1]: 41
2717 10:04:59.542706
2718 10:04:59.542800 Set Vref, RX VrefLevel [Byte0]: 42
2719 10:04:59.545378 [Byte1]: 42
2720 10:04:59.549875
2721 10:04:59.549966 Set Vref, RX VrefLevel [Byte0]: 43
2722 10:04:59.553340 [Byte1]: 43
2723 10:04:59.557856
2724 10:04:59.557954 Set Vref, RX VrefLevel [Byte0]: 44
2725 10:04:59.561473 [Byte1]: 44
2726 10:04:59.565838
2727 10:04:59.565930 Set Vref, RX VrefLevel [Byte0]: 45
2728 10:04:59.569249 [Byte1]: 45
2729 10:04:59.573560
2730 10:04:59.573651 Set Vref, RX VrefLevel [Byte0]: 46
2731 10:04:59.577411 [Byte1]: 46
2732 10:04:59.581753
2733 10:04:59.581845 Set Vref, RX VrefLevel [Byte0]: 47
2734 10:04:59.584869 [Byte1]: 47
2735 10:04:59.589334
2736 10:04:59.593217 Set Vref, RX VrefLevel [Byte0]: 48
2737 10:04:59.593310 [Byte1]: 48
2738 10:04:59.597216
2739 10:04:59.597303 Set Vref, RX VrefLevel [Byte0]: 49
2740 10:04:59.600689 [Byte1]: 49
2741 10:04:59.605521
2742 10:04:59.605635 Set Vref, RX VrefLevel [Byte0]: 50
2743 10:04:59.608701 [Byte1]: 50
2744 10:04:59.613368
2745 10:04:59.613470 Set Vref, RX VrefLevel [Byte0]: 51
2746 10:04:59.616955 [Byte1]: 51
2747 10:04:59.621065
2748 10:04:59.621154 Set Vref, RX VrefLevel [Byte0]: 52
2749 10:04:59.624385 [Byte1]: 52
2750 10:04:59.629282
2751 10:04:59.629376 Set Vref, RX VrefLevel [Byte0]: 53
2752 10:04:59.632789 [Byte1]: 53
2753 10:04:59.637050
2754 10:04:59.637139 Set Vref, RX VrefLevel [Byte0]: 54
2755 10:04:59.640530 [Byte1]: 54
2756 10:04:59.644599
2757 10:04:59.644688 Set Vref, RX VrefLevel [Byte0]: 55
2758 10:04:59.648537 [Byte1]: 55
2759 10:04:59.652770
2760 10:04:59.652912 Set Vref, RX VrefLevel [Byte0]: 56
2761 10:04:59.655704 [Byte1]: 56
2762 10:04:59.661032
2763 10:04:59.661181 Set Vref, RX VrefLevel [Byte0]: 57
2764 10:04:59.664283 [Byte1]: 57
2765 10:04:59.668567
2766 10:04:59.668659 Set Vref, RX VrefLevel [Byte0]: 58
2767 10:04:59.672064 [Byte1]: 58
2768 10:04:59.676565
2769 10:04:59.676657 Set Vref, RX VrefLevel [Byte0]: 59
2770 10:04:59.679932 [Byte1]: 59
2771 10:04:59.683979
2772 10:04:59.684068 Set Vref, RX VrefLevel [Byte0]: 60
2773 10:04:59.687630 [Byte1]: 60
2774 10:04:59.692093
2775 10:04:59.692187 Set Vref, RX VrefLevel [Byte0]: 61
2776 10:04:59.695607 [Byte1]: 61
2777 10:04:59.699840
2778 10:04:59.699944 Set Vref, RX VrefLevel [Byte0]: 62
2779 10:04:59.703042 [Byte1]: 62
2780 10:04:59.708117
2781 10:04:59.708245 Set Vref, RX VrefLevel [Byte0]: 63
2782 10:04:59.711289 [Byte1]: 63
2783 10:04:59.715794
2784 10:04:59.715893 Set Vref, RX VrefLevel [Byte0]: 64
2785 10:04:59.719030 [Byte1]: 64
2786 10:04:59.723948
2787 10:04:59.724049 Set Vref, RX VrefLevel [Byte0]: 65
2788 10:04:59.727091 [Byte1]: 65
2789 10:04:59.731625
2790 10:04:59.731718 Set Vref, RX VrefLevel [Byte0]: 66
2791 10:04:59.734940 [Byte1]: 66
2792 10:04:59.739314
2793 10:04:59.739408 Set Vref, RX VrefLevel [Byte0]: 67
2794 10:04:59.743149 [Byte1]: 67
2795 10:04:59.747455
2796 10:04:59.747549 Set Vref, RX VrefLevel [Byte0]: 68
2797 10:04:59.750724 [Byte1]: 68
2798 10:04:59.755530
2799 10:04:59.755630 Final RX Vref Byte 0 = 55 to rank0
2800 10:04:59.758448 Final RX Vref Byte 1 = 50 to rank0
2801 10:04:59.762315 Final RX Vref Byte 0 = 55 to rank1
2802 10:04:59.765037 Final RX Vref Byte 1 = 50 to rank1==
2803 10:04:59.768498 Dram Type= 6, Freq= 0, CH_0, rank 0
2804 10:04:59.775827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2805 10:04:59.775947 ==
2806 10:04:59.776040 DQS Delay:
2807 10:04:59.776121 DQS0 = 0, DQS1 = 0
2808 10:04:59.778464 DQM Delay:
2809 10:04:59.778550 DQM0 = 121, DQM1 = 112
2810 10:04:59.781809 DQ Delay:
2811 10:04:59.785494 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =120
2812 10:04:59.788474 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2813 10:04:59.791830 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2814 10:04:59.795432 DQ12 =118, DQ13 =116, DQ14 =124, DQ15 =122
2815 10:04:59.795525
2816 10:04:59.795611
2817 10:04:59.802105 [DQSOSCAuto] RK0, (LSB)MR18= 0x130c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2818 10:04:59.805350 CH0 RK0: MR19=404, MR18=130C
2819 10:04:59.813208 CH0_RK0: MR19=0x404, MR18=0x130C, DQSOSC=402, MR23=63, INC=40, DEC=27
2820 10:04:59.813335
2821 10:04:59.815584 ----->DramcWriteLeveling(PI) begin...
2822 10:04:59.815672 ==
2823 10:04:59.818611 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 10:04:59.822251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 10:04:59.822343 ==
2826 10:04:59.825450 Write leveling (Byte 0): 33 => 33
2827 10:04:59.829005 Write leveling (Byte 1): 29 => 29
2828 10:04:59.832099 DramcWriteLeveling(PI) end<-----
2829 10:04:59.832190
2830 10:04:59.832275 ==
2831 10:04:59.835699 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 10:04:59.841990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 10:04:59.842093 ==
2834 10:04:59.842180 [Gating] SW mode calibration
2835 10:04:59.852086 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2836 10:04:59.855244 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2837 10:04:59.858541 0 15 0 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 1)
2838 10:04:59.865377 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 10:04:59.868938 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 10:04:59.872163 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 10:04:59.879151 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 10:04:59.881992 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 10:04:59.885882 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 10:04:59.891975 0 15 28 | B1->B0 | 2e2e 2c2c | 1 1 | (1 0) (1 0)
2845 10:04:59.895441 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 10:04:59.899099 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 10:04:59.905717 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 10:04:59.908820 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 10:04:59.912398 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 10:04:59.918900 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 10:04:59.922390 1 0 24 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
2852 10:04:59.925262 1 0 28 | B1->B0 | 4040 403f | 0 1 | (0 0) (0 0)
2853 10:04:59.932417 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 10:04:59.935711 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 10:04:59.938635 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 10:04:59.942125 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 10:04:59.948591 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 10:04:59.952044 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 10:04:59.955339 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 10:04:59.962156 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2861 10:04:59.965461 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2862 10:04:59.969175 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 10:04:59.975307 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 10:04:59.979091 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 10:04:59.981967 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 10:04:59.988587 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 10:04:59.992063 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 10:04:59.995684 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 10:05:00.002357 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 10:05:00.005761 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 10:05:00.008625 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 10:05:00.015805 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 10:05:00.018706 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 10:05:00.022453 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 10:05:00.025450 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 10:05:00.031952 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2877 10:05:00.035390 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2878 10:05:00.038884 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 10:05:00.042313 Total UI for P1: 0, mck2ui 16
2880 10:05:00.045447 best dqsien dly found for B0: ( 1, 3, 30)
2881 10:05:00.048725 Total UI for P1: 0, mck2ui 16
2882 10:05:00.052341 best dqsien dly found for B1: ( 1, 3, 30)
2883 10:05:00.055702 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2884 10:05:00.058787 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2885 10:05:00.062183
2886 10:05:00.065338 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2887 10:05:00.069333 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2888 10:05:00.072487 [Gating] SW calibration Done
2889 10:05:00.072579 ==
2890 10:05:00.075380 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 10:05:00.079185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 10:05:00.079278 ==
2893 10:05:00.079365 RX Vref Scan: 0
2894 10:05:00.079445
2895 10:05:00.082305 RX Vref 0 -> 0, step: 1
2896 10:05:00.082391
2897 10:05:00.085743 RX Delay -40 -> 252, step: 8
2898 10:05:00.088919 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2899 10:05:00.092054 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2900 10:05:00.099007 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2901 10:05:00.102151 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2902 10:05:00.105890 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2903 10:05:00.108925 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2904 10:05:00.112566 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2905 10:05:00.115582 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2906 10:05:00.122364 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2907 10:05:00.125594 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2908 10:05:00.128782 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2909 10:05:00.132845 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2910 10:05:00.135899 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2911 10:05:00.142491 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2912 10:05:00.145629 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2913 10:05:00.148865 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2914 10:05:00.148956 ==
2915 10:05:00.152787 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 10:05:00.155787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 10:05:00.155876 ==
2918 10:05:00.158946 DQS Delay:
2919 10:05:00.159033 DQS0 = 0, DQS1 = 0
2920 10:05:00.162942 DQM Delay:
2921 10:05:00.163031 DQM0 = 121, DQM1 = 112
2922 10:05:00.163099 DQ Delay:
2923 10:05:00.169008 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2924 10:05:00.172624 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2925 10:05:00.176145 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2926 10:05:00.179116 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2927 10:05:00.179205
2928 10:05:00.179271
2929 10:05:00.179333 ==
2930 10:05:00.182618 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 10:05:00.185810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 10:05:00.185901 ==
2933 10:05:00.185969
2934 10:05:00.186031
2935 10:05:00.189201 TX Vref Scan disable
2936 10:05:00.192403 == TX Byte 0 ==
2937 10:05:00.196118 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2938 10:05:00.199218 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2939 10:05:00.202622 == TX Byte 1 ==
2940 10:05:00.205638 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2941 10:05:00.209076 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2942 10:05:00.209167 ==
2943 10:05:00.212702 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 10:05:00.215978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 10:05:00.216073 ==
2946 10:05:00.229460 TX Vref=22, minBit 1, minWin=25, winSum=417
2947 10:05:00.232736 TX Vref=24, minBit 3, minWin=25, winSum=424
2948 10:05:00.236249 TX Vref=26, minBit 0, minWin=26, winSum=427
2949 10:05:00.239847 TX Vref=28, minBit 1, minWin=26, winSum=428
2950 10:05:00.242874 TX Vref=30, minBit 1, minWin=26, winSum=429
2951 10:05:00.246279 TX Vref=32, minBit 0, minWin=26, winSum=428
2952 10:05:00.252985 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
2953 10:05:00.253099
2954 10:05:00.256716 Final TX Range 1 Vref 30
2955 10:05:00.256835
2956 10:05:00.256905 ==
2957 10:05:00.259333 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 10:05:00.262839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 10:05:00.262927 ==
2960 10:05:00.262994
2961 10:05:00.266185
2962 10:05:00.266269 TX Vref Scan disable
2963 10:05:00.269610 == TX Byte 0 ==
2964 10:05:00.272768 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2965 10:05:00.276201 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2966 10:05:00.280116 == TX Byte 1 ==
2967 10:05:00.282593 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2968 10:05:00.286120 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2969 10:05:00.286212
2970 10:05:00.289593 [DATLAT]
2971 10:05:00.289682 Freq=1200, CH0 RK1
2972 10:05:00.289750
2973 10:05:00.292787 DATLAT Default: 0xd
2974 10:05:00.292911 0, 0xFFFF, sum = 0
2975 10:05:00.296244 1, 0xFFFF, sum = 0
2976 10:05:00.296332 2, 0xFFFF, sum = 0
2977 10:05:00.299451 3, 0xFFFF, sum = 0
2978 10:05:00.299538 4, 0xFFFF, sum = 0
2979 10:05:00.302963 5, 0xFFFF, sum = 0
2980 10:05:00.303054 6, 0xFFFF, sum = 0
2981 10:05:00.306584 7, 0xFFFF, sum = 0
2982 10:05:00.306672 8, 0xFFFF, sum = 0
2983 10:05:00.309523 9, 0xFFFF, sum = 0
2984 10:05:00.309612 10, 0xFFFF, sum = 0
2985 10:05:00.312653 11, 0xFFFF, sum = 0
2986 10:05:00.312741 12, 0x0, sum = 1
2987 10:05:00.316557 13, 0x0, sum = 2
2988 10:05:00.316649 14, 0x0, sum = 3
2989 10:05:00.319795 15, 0x0, sum = 4
2990 10:05:00.319882 best_step = 13
2991 10:05:00.319949
2992 10:05:00.320010 ==
2993 10:05:00.322676 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 10:05:00.329809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 10:05:00.329911 ==
2996 10:05:00.329980 RX Vref Scan: 0
2997 10:05:00.330042
2998 10:05:00.332785 RX Vref 0 -> 0, step: 1
2999 10:05:00.332910
3000 10:05:00.336107 RX Delay -13 -> 252, step: 4
3001 10:05:00.339445 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3002 10:05:00.342933 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3003 10:05:00.349382 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3004 10:05:00.352950 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3005 10:05:00.356519 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3006 10:05:00.359441 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3007 10:05:00.362898 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3008 10:05:00.369813 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3009 10:05:00.373056 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3010 10:05:00.376097 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3011 10:05:00.379648 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3012 10:05:00.382848 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3013 10:05:00.390176 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3014 10:05:00.393061 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3015 10:05:00.396280 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3016 10:05:00.399530 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3017 10:05:00.399624 ==
3018 10:05:00.402912 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 10:05:00.406739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 10:05:00.409653 ==
3021 10:05:00.409753 DQS Delay:
3022 10:05:00.409840 DQS0 = 0, DQS1 = 0
3023 10:05:00.413155 DQM Delay:
3024 10:05:00.413241 DQM0 = 121, DQM1 = 110
3025 10:05:00.416570 DQ Delay:
3026 10:05:00.419669 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
3027 10:05:00.423077 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3028 10:05:00.426204 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =104
3029 10:05:00.429966 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3030 10:05:00.430060
3031 10:05:00.430146
3032 10:05:00.436303 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3033 10:05:00.439538 CH0 RK1: MR19=403, MR18=10F1
3034 10:05:00.446531 CH0_RK1: MR19=0x403, MR18=0x10F1, DQSOSC=403, MR23=63, INC=40, DEC=26
3035 10:05:00.449969 [RxdqsGatingPostProcess] freq 1200
3036 10:05:00.456716 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3037 10:05:00.456897 best DQS0 dly(2T, 0.5T) = (0, 11)
3038 10:05:00.460471 best DQS1 dly(2T, 0.5T) = (0, 12)
3039 10:05:00.463200 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3040 10:05:00.466754 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3041 10:05:00.470278 best DQS0 dly(2T, 0.5T) = (0, 11)
3042 10:05:00.473292 best DQS1 dly(2T, 0.5T) = (0, 11)
3043 10:05:00.476483 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3044 10:05:00.479933 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3045 10:05:00.483105 Pre-setting of DQS Precalculation
3046 10:05:00.486718 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3047 10:05:00.490005 ==
3048 10:05:00.493341 Dram Type= 6, Freq= 0, CH_1, rank 0
3049 10:05:00.497013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 10:05:00.497103 ==
3051 10:05:00.500085 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3052 10:05:00.506735 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3053 10:05:00.516085 [CA 0] Center 37 (7~68) winsize 62
3054 10:05:00.519008 [CA 1] Center 37 (7~68) winsize 62
3055 10:05:00.523021 [CA 2] Center 35 (5~65) winsize 61
3056 10:05:00.526145 [CA 3] Center 34 (4~64) winsize 61
3057 10:05:00.529214 [CA 4] Center 34 (4~64) winsize 61
3058 10:05:00.532737 [CA 5] Center 33 (3~63) winsize 61
3059 10:05:00.532857
3060 10:05:00.536084 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3061 10:05:00.536169
3062 10:05:00.539295 [CATrainingPosCal] consider 1 rank data
3063 10:05:00.542571 u2DelayCellTimex100 = 270/100 ps
3064 10:05:00.545980 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3065 10:05:00.549937 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3066 10:05:00.552462 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3067 10:05:00.559114 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3068 10:05:00.562825 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3069 10:05:00.565888 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3070 10:05:00.565978
3071 10:05:00.569406 CA PerBit enable=1, Macro0, CA PI delay=33
3072 10:05:00.569492
3073 10:05:00.572726 [CBTSetCACLKResult] CA Dly = 33
3074 10:05:00.572840 CS Dly: 7 (0~38)
3075 10:05:00.572909 ==
3076 10:05:00.576260 Dram Type= 6, Freq= 0, CH_1, rank 1
3077 10:05:00.582642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 10:05:00.582743 ==
3079 10:05:00.586021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3080 10:05:00.592768 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3081 10:05:00.601785 [CA 0] Center 37 (7~68) winsize 62
3082 10:05:00.604762 [CA 1] Center 38 (8~68) winsize 61
3083 10:05:00.608298 [CA 2] Center 35 (5~65) winsize 61
3084 10:05:00.611282 [CA 3] Center 34 (4~65) winsize 62
3085 10:05:00.615010 [CA 4] Center 35 (5~65) winsize 61
3086 10:05:00.618619 [CA 5] Center 34 (4~64) winsize 61
3087 10:05:00.618717
3088 10:05:00.621261 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3089 10:05:00.621346
3090 10:05:00.624851 [CATrainingPosCal] consider 2 rank data
3091 10:05:00.628368 u2DelayCellTimex100 = 270/100 ps
3092 10:05:00.631686 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3093 10:05:00.634860 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3094 10:05:00.638232 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3095 10:05:00.645092 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 10:05:00.648736 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3097 10:05:00.651731 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3098 10:05:00.651819
3099 10:05:00.655011 CA PerBit enable=1, Macro0, CA PI delay=33
3100 10:05:00.655095
3101 10:05:00.658850 [CBTSetCACLKResult] CA Dly = 33
3102 10:05:00.658935 CS Dly: 8 (0~41)
3103 10:05:00.659001
3104 10:05:00.661824 ----->DramcWriteLeveling(PI) begin...
3105 10:05:00.661911 ==
3106 10:05:00.665002 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 10:05:00.671598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 10:05:00.671702 ==
3109 10:05:00.675138 Write leveling (Byte 0): 26 => 26
3110 10:05:00.678425 Write leveling (Byte 1): 29 => 29
3111 10:05:00.678515 DramcWriteLeveling(PI) end<-----
3112 10:05:00.678581
3113 10:05:00.681852 ==
3114 10:05:00.684784 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 10:05:00.688272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 10:05:00.688363 ==
3117 10:05:00.691449 [Gating] SW mode calibration
3118 10:05:00.698241 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3119 10:05:00.701721 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3120 10:05:00.708181 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 10:05:00.711766 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 10:05:00.714768 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 10:05:00.721980 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 10:05:00.724724 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 10:05:00.728128 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 10:05:00.735659 0 15 24 | B1->B0 | 3434 2626 | 0 0 | (0 1) (1 0)
3127 10:05:00.738285 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 1) (1 0)
3128 10:05:00.741657 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 10:05:00.748607 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 10:05:00.751881 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 10:05:00.755357 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 10:05:00.758515 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 10:05:00.765471 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 10:05:00.769114 1 0 24 | B1->B0 | 2f2f 4040 | 0 1 | (0 0) (0 0)
3135 10:05:00.771937 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 10:05:00.778746 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 10:05:00.781791 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 10:05:00.785765 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 10:05:00.791916 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 10:05:00.795630 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 10:05:00.798572 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 10:05:00.805326 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3143 10:05:00.808540 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3144 10:05:00.811801 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 10:05:00.819020 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 10:05:00.822336 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 10:05:00.825523 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 10:05:00.828615 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 10:05:00.835765 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 10:05:00.838788 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 10:05:00.842180 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 10:05:00.848687 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 10:05:00.852246 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 10:05:00.855657 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 10:05:00.861938 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 10:05:00.865367 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 10:05:00.868931 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 10:05:00.875368 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3159 10:05:00.878906 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 10:05:00.882031 Total UI for P1: 0, mck2ui 16
3161 10:05:00.885728 best dqsien dly found for B0: ( 1, 3, 24)
3162 10:05:00.889288 Total UI for P1: 0, mck2ui 16
3163 10:05:00.892151 best dqsien dly found for B1: ( 1, 3, 24)
3164 10:05:00.895487 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3165 10:05:00.898931 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3166 10:05:00.899042
3167 10:05:00.902183 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3168 10:05:00.906337 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3169 10:05:00.909021 [Gating] SW calibration Done
3170 10:05:00.909119 ==
3171 10:05:00.912494 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 10:05:00.915783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 10:05:00.915887 ==
3174 10:05:00.919117 RX Vref Scan: 0
3175 10:05:00.919230
3176 10:05:00.922717 RX Vref 0 -> 0, step: 1
3177 10:05:00.922808
3178 10:05:00.922878 RX Delay -40 -> 252, step: 8
3179 10:05:00.929129 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3180 10:05:00.932631 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3181 10:05:00.935472 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3182 10:05:00.939013 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3183 10:05:00.942843 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3184 10:05:00.949111 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3185 10:05:00.952350 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3186 10:05:00.956135 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3187 10:05:00.959024 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3188 10:05:00.963099 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3189 10:05:00.965766 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3190 10:05:00.972286 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3191 10:05:00.975693 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3192 10:05:00.979059 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3193 10:05:00.982387 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3194 10:05:00.989745 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3195 10:05:00.989942 ==
3196 10:05:00.992763 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 10:05:00.995868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 10:05:00.995976 ==
3199 10:05:00.996047 DQS Delay:
3200 10:05:00.999337 DQS0 = 0, DQS1 = 0
3201 10:05:00.999427 DQM Delay:
3202 10:05:01.002843 DQM0 = 119, DQM1 = 116
3203 10:05:01.002938 DQ Delay:
3204 10:05:01.005954 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3205 10:05:01.009847 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3206 10:05:01.012800 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3207 10:05:01.015926 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3208 10:05:01.016032
3209 10:05:01.016098
3210 10:05:01.016158 ==
3211 10:05:01.019279 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 10:05:01.026154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 10:05:01.026268 ==
3214 10:05:01.026337
3215 10:05:01.026398
3216 10:05:01.026457 TX Vref Scan disable
3217 10:05:01.029896 == TX Byte 0 ==
3218 10:05:01.033088 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3219 10:05:01.039597 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3220 10:05:01.039739 == TX Byte 1 ==
3221 10:05:01.042877 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3222 10:05:01.049394 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3223 10:05:01.049502 ==
3224 10:05:01.052757 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 10:05:01.056179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 10:05:01.056284 ==
3227 10:05:01.067397 TX Vref=22, minBit 9, minWin=24, winSum=412
3228 10:05:01.070978 TX Vref=24, minBit 9, minWin=25, winSum=416
3229 10:05:01.074408 TX Vref=26, minBit 10, minWin=25, winSum=426
3230 10:05:01.077259 TX Vref=28, minBit 10, minWin=25, winSum=428
3231 10:05:01.081295 TX Vref=30, minBit 9, minWin=26, winSum=433
3232 10:05:01.087686 TX Vref=32, minBit 9, minWin=26, winSum=433
3233 10:05:01.090912 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3234 10:05:01.091009
3235 10:05:01.094278 Final TX Range 1 Vref 30
3236 10:05:01.094366
3237 10:05:01.094432 ==
3238 10:05:01.097871 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 10:05:01.101032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 10:05:01.101157 ==
3241 10:05:01.101267
3242 10:05:01.104217
3243 10:05:01.104301 TX Vref Scan disable
3244 10:05:01.107602 == TX Byte 0 ==
3245 10:05:01.111189 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3246 10:05:01.114363 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3247 10:05:01.117621 == TX Byte 1 ==
3248 10:05:01.120923 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3249 10:05:01.124194 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3250 10:05:01.124287
3251 10:05:01.127263 [DATLAT]
3252 10:05:01.127361 Freq=1200, CH1 RK0
3253 10:05:01.127449
3254 10:05:01.130950 DATLAT Default: 0xd
3255 10:05:01.131041 0, 0xFFFF, sum = 0
3256 10:05:01.133949 1, 0xFFFF, sum = 0
3257 10:05:01.134039 2, 0xFFFF, sum = 0
3258 10:05:01.137815 3, 0xFFFF, sum = 0
3259 10:05:01.137907 4, 0xFFFF, sum = 0
3260 10:05:01.140938 5, 0xFFFF, sum = 0
3261 10:05:01.141027 6, 0xFFFF, sum = 0
3262 10:05:01.144134 7, 0xFFFF, sum = 0
3263 10:05:01.147643 8, 0xFFFF, sum = 0
3264 10:05:01.147734 9, 0xFFFF, sum = 0
3265 10:05:01.150918 10, 0xFFFF, sum = 0
3266 10:05:01.151007 11, 0xFFFF, sum = 0
3267 10:05:01.154294 12, 0x0, sum = 1
3268 10:05:01.154384 13, 0x0, sum = 2
3269 10:05:01.157364 14, 0x0, sum = 3
3270 10:05:01.157453 15, 0x0, sum = 4
3271 10:05:01.157542 best_step = 13
3272 10:05:01.157622
3273 10:05:01.161089 ==
3274 10:05:01.164290 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 10:05:01.167939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 10:05:01.168032 ==
3277 10:05:01.168100 RX Vref Scan: 1
3278 10:05:01.168163
3279 10:05:01.170896 Set Vref Range= 32 -> 127
3280 10:05:01.170982
3281 10:05:01.174656 RX Vref 32 -> 127, step: 1
3282 10:05:01.174743
3283 10:05:01.177518 RX Delay -5 -> 252, step: 4
3284 10:05:01.177603
3285 10:05:01.180762 Set Vref, RX VrefLevel [Byte0]: 32
3286 10:05:01.184230 [Byte1]: 32
3287 10:05:01.184318
3288 10:05:01.187746 Set Vref, RX VrefLevel [Byte0]: 33
3289 10:05:01.191636 [Byte1]: 33
3290 10:05:01.191735
3291 10:05:01.194303 Set Vref, RX VrefLevel [Byte0]: 34
3292 10:05:01.197802 [Byte1]: 34
3293 10:05:01.201550
3294 10:05:01.201655 Set Vref, RX VrefLevel [Byte0]: 35
3295 10:05:01.204425 [Byte1]: 35
3296 10:05:01.209358
3297 10:05:01.209475 Set Vref, RX VrefLevel [Byte0]: 36
3298 10:05:01.212395 [Byte1]: 36
3299 10:05:01.217379
3300 10:05:01.217485 Set Vref, RX VrefLevel [Byte0]: 37
3301 10:05:01.220446 [Byte1]: 37
3302 10:05:01.225138
3303 10:05:01.225229 Set Vref, RX VrefLevel [Byte0]: 38
3304 10:05:01.228171 [Byte1]: 38
3305 10:05:01.232570
3306 10:05:01.232660 Set Vref, RX VrefLevel [Byte0]: 39
3307 10:05:01.236150 [Byte1]: 39
3308 10:05:01.240539
3309 10:05:01.240632 Set Vref, RX VrefLevel [Byte0]: 40
3310 10:05:01.243651 [Byte1]: 40
3311 10:05:01.248446
3312 10:05:01.248538 Set Vref, RX VrefLevel [Byte0]: 41
3313 10:05:01.252058 [Byte1]: 41
3314 10:05:01.256605
3315 10:05:01.256698 Set Vref, RX VrefLevel [Byte0]: 42
3316 10:05:01.259843 [Byte1]: 42
3317 10:05:01.264229
3318 10:05:01.264341 Set Vref, RX VrefLevel [Byte0]: 43
3319 10:05:01.267466 [Byte1]: 43
3320 10:05:01.271859
3321 10:05:01.271967 Set Vref, RX VrefLevel [Byte0]: 44
3322 10:05:01.275063 [Byte1]: 44
3323 10:05:01.280262
3324 10:05:01.280359 Set Vref, RX VrefLevel [Byte0]: 45
3325 10:05:01.283149 [Byte1]: 45
3326 10:05:01.287554
3327 10:05:01.287647 Set Vref, RX VrefLevel [Byte0]: 46
3328 10:05:01.291315 [Byte1]: 46
3329 10:05:01.295682
3330 10:05:01.295775 Set Vref, RX VrefLevel [Byte0]: 47
3331 10:05:01.299075 [Byte1]: 47
3332 10:05:01.303457
3333 10:05:01.303549 Set Vref, RX VrefLevel [Byte0]: 48
3334 10:05:01.306736 [Byte1]: 48
3335 10:05:01.311521
3336 10:05:01.311648 Set Vref, RX VrefLevel [Byte0]: 49
3337 10:05:01.314433 [Byte1]: 49
3338 10:05:01.319382
3339 10:05:01.319493 Set Vref, RX VrefLevel [Byte0]: 50
3340 10:05:01.322559 [Byte1]: 50
3341 10:05:01.326823
3342 10:05:01.326916 Set Vref, RX VrefLevel [Byte0]: 51
3343 10:05:01.330233 [Byte1]: 51
3344 10:05:01.334894
3345 10:05:01.334986 Set Vref, RX VrefLevel [Byte0]: 52
3346 10:05:01.338469 [Byte1]: 52
3347 10:05:01.342910
3348 10:05:01.343002 Set Vref, RX VrefLevel [Byte0]: 53
3349 10:05:01.346167 [Byte1]: 53
3350 10:05:01.350530
3351 10:05:01.350624 Set Vref, RX VrefLevel [Byte0]: 54
3352 10:05:01.353934 [Byte1]: 54
3353 10:05:01.358254
3354 10:05:01.358344 Set Vref, RX VrefLevel [Byte0]: 55
3355 10:05:01.361605 [Byte1]: 55
3356 10:05:01.366291
3357 10:05:01.366385 Set Vref, RX VrefLevel [Byte0]: 56
3358 10:05:01.369674 [Byte1]: 56
3359 10:05:01.374115
3360 10:05:01.374204 Set Vref, RX VrefLevel [Byte0]: 57
3361 10:05:01.377651 [Byte1]: 57
3362 10:05:01.382514
3363 10:05:01.382607 Set Vref, RX VrefLevel [Byte0]: 58
3364 10:05:01.385284 [Byte1]: 58
3365 10:05:01.389622
3366 10:05:01.389713 Set Vref, RX VrefLevel [Byte0]: 59
3367 10:05:01.393356 [Byte1]: 59
3368 10:05:01.397695
3369 10:05:01.397784 Set Vref, RX VrefLevel [Byte0]: 60
3370 10:05:01.400679 [Byte1]: 60
3371 10:05:01.405600
3372 10:05:01.405688 Set Vref, RX VrefLevel [Byte0]: 61
3373 10:05:01.408749 [Byte1]: 61
3374 10:05:01.413324
3375 10:05:01.413411 Set Vref, RX VrefLevel [Byte0]: 62
3376 10:05:01.416671 [Byte1]: 62
3377 10:05:01.421676
3378 10:05:01.421759 Set Vref, RX VrefLevel [Byte0]: 63
3379 10:05:01.424337 [Byte1]: 63
3380 10:05:01.429200
3381 10:05:01.429282 Set Vref, RX VrefLevel [Byte0]: 64
3382 10:05:01.432749 [Byte1]: 64
3383 10:05:01.436902
3384 10:05:01.436982 Set Vref, RX VrefLevel [Byte0]: 65
3385 10:05:01.440249 [Byte1]: 65
3386 10:05:01.445047
3387 10:05:01.445128 Set Vref, RX VrefLevel [Byte0]: 66
3388 10:05:01.448125 [Byte1]: 66
3389 10:05:01.452762
3390 10:05:01.452871 Set Vref, RX VrefLevel [Byte0]: 67
3391 10:05:01.456284 [Byte1]: 67
3392 10:05:01.460646
3393 10:05:01.460729 Set Vref, RX VrefLevel [Byte0]: 68
3394 10:05:01.464084 [Byte1]: 68
3395 10:05:01.468472
3396 10:05:01.468555 Final RX Vref Byte 0 = 54 to rank0
3397 10:05:01.471898 Final RX Vref Byte 1 = 56 to rank0
3398 10:05:01.474860 Final RX Vref Byte 0 = 54 to rank1
3399 10:05:01.478055 Final RX Vref Byte 1 = 56 to rank1==
3400 10:05:01.481554 Dram Type= 6, Freq= 0, CH_1, rank 0
3401 10:05:01.488372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3402 10:05:01.488470 ==
3403 10:05:01.488537 DQS Delay:
3404 10:05:01.488597 DQS0 = 0, DQS1 = 0
3405 10:05:01.491519 DQM Delay:
3406 10:05:01.491602 DQM0 = 120, DQM1 = 118
3407 10:05:01.495290 DQ Delay:
3408 10:05:01.498681 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3409 10:05:01.501867 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3410 10:05:01.505184 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3411 10:05:01.508461 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3412 10:05:01.508545
3413 10:05:01.508611
3414 10:05:01.515496 [DQSOSCAuto] RK0, (LSB)MR18= 0x316, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3415 10:05:01.518673 CH1 RK0: MR19=404, MR18=316
3416 10:05:01.525338 CH1_RK0: MR19=0x404, MR18=0x316, DQSOSC=401, MR23=63, INC=40, DEC=27
3417 10:05:01.525422
3418 10:05:01.528379 ----->DramcWriteLeveling(PI) begin...
3419 10:05:01.528464 ==
3420 10:05:01.532230 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 10:05:01.535577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 10:05:01.535661 ==
3423 10:05:01.538932 Write leveling (Byte 0): 25 => 25
3424 10:05:01.541839 Write leveling (Byte 1): 28 => 28
3425 10:05:01.545504 DramcWriteLeveling(PI) end<-----
3426 10:05:01.545587
3427 10:05:01.545653 ==
3428 10:05:01.548675 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 10:05:01.552216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 10:05:01.552300 ==
3431 10:05:01.555820 [Gating] SW mode calibration
3432 10:05:01.562023 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3433 10:05:01.568927 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3434 10:05:01.572376 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 10:05:01.579162 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 10:05:01.582502 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 10:05:01.585951 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 10:05:01.588821 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 10:05:01.595737 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3440 10:05:01.599152 0 15 24 | B1->B0 | 2929 3434 | 1 0 | (1 0) (0 0)
3441 10:05:01.602988 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3442 10:05:01.609101 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 10:05:01.612779 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 10:05:01.616424 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 10:05:01.622487 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 10:05:01.625903 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 10:05:01.629331 1 0 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3448 10:05:01.635618 1 0 24 | B1->B0 | 4141 2a2a | 0 1 | (0 0) (0 0)
3449 10:05:01.639059 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3450 10:05:01.642480 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 10:05:01.649145 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 10:05:01.652364 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 10:05:01.655924 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 10:05:01.662682 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 10:05:01.665992 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3456 10:05:01.669401 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3457 10:05:01.675423 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3458 10:05:01.679008 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 10:05:01.682420 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 10:05:01.685649 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 10:05:01.692057 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 10:05:01.695559 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 10:05:01.698957 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 10:05:01.705506 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 10:05:01.708912 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 10:05:01.712647 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 10:05:01.719113 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 10:05:01.721990 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 10:05:01.725300 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 10:05:01.732251 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 10:05:01.735683 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3472 10:05:01.738991 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3473 10:05:01.745192 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3474 10:05:01.748624 Total UI for P1: 0, mck2ui 16
3475 10:05:01.752015 best dqsien dly found for B1: ( 1, 3, 22)
3476 10:05:01.755100 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 10:05:01.758713 Total UI for P1: 0, mck2ui 16
3478 10:05:01.761956 best dqsien dly found for B0: ( 1, 3, 26)
3479 10:05:01.765257 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3480 10:05:01.768674 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3481 10:05:01.768781
3482 10:05:01.772104 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3483 10:05:01.775299 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3484 10:05:01.778403 [Gating] SW calibration Done
3485 10:05:01.778485 ==
3486 10:05:01.781861 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 10:05:01.785281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 10:05:01.788488 ==
3489 10:05:01.788570 RX Vref Scan: 0
3490 10:05:01.788635
3491 10:05:01.791627 RX Vref 0 -> 0, step: 1
3492 10:05:01.791708
3493 10:05:01.795513 RX Delay -40 -> 252, step: 8
3494 10:05:01.798766 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3495 10:05:01.801978 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3496 10:05:01.805344 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3497 10:05:01.808290 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3498 10:05:01.815411 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3499 10:05:01.818462 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3500 10:05:01.822040 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3501 10:05:01.824834 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3502 10:05:01.828290 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3503 10:05:01.835385 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3504 10:05:01.838834 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3505 10:05:01.841942 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3506 10:05:01.844912 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3507 10:05:01.848159 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3508 10:05:01.855340 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3509 10:05:01.858821 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3510 10:05:01.858903 ==
3511 10:05:01.862197 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 10:05:01.865101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 10:05:01.865185 ==
3514 10:05:01.868642 DQS Delay:
3515 10:05:01.868724 DQS0 = 0, DQS1 = 0
3516 10:05:01.868788 DQM Delay:
3517 10:05:01.871938 DQM0 = 120, DQM1 = 117
3518 10:05:01.872020 DQ Delay:
3519 10:05:01.875535 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =115
3520 10:05:01.878074 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3521 10:05:01.881459 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3522 10:05:01.888448 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3523 10:05:01.888531
3524 10:05:01.888595
3525 10:05:01.888654 ==
3526 10:05:01.891657 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 10:05:01.895286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 10:05:01.895369 ==
3529 10:05:01.895434
3530 10:05:01.895494
3531 10:05:01.898503 TX Vref Scan disable
3532 10:05:01.898585 == TX Byte 0 ==
3533 10:05:01.905066 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3534 10:05:01.908258 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3535 10:05:01.908341 == TX Byte 1 ==
3536 10:05:01.915195 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3537 10:05:01.918473 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3538 10:05:01.918555 ==
3539 10:05:01.921540 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 10:05:01.925123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 10:05:01.925210 ==
3542 10:05:01.937688 TX Vref=22, minBit 1, minWin=26, winSum=423
3543 10:05:01.940675 TX Vref=24, minBit 2, minWin=26, winSum=427
3544 10:05:01.944216 TX Vref=26, minBit 2, minWin=26, winSum=429
3545 10:05:01.947437 TX Vref=28, minBit 9, minWin=26, winSum=431
3546 10:05:01.950598 TX Vref=30, minBit 9, minWin=26, winSum=432
3547 10:05:01.957461 TX Vref=32, minBit 9, minWin=26, winSum=433
3548 10:05:01.960608 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 32
3549 10:05:01.960692
3550 10:05:01.964258 Final TX Range 1 Vref 32
3551 10:05:01.964342
3552 10:05:01.964407 ==
3553 10:05:01.967331 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 10:05:01.970506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 10:05:01.970590 ==
3556 10:05:01.974133
3557 10:05:01.974215
3558 10:05:01.974279 TX Vref Scan disable
3559 10:05:01.977370 == TX Byte 0 ==
3560 10:05:01.980690 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3561 10:05:01.987078 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3562 10:05:01.987161 == TX Byte 1 ==
3563 10:05:01.990311 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3564 10:05:01.997119 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3565 10:05:01.997210
3566 10:05:01.997276 [DATLAT]
3567 10:05:01.997336 Freq=1200, CH1 RK1
3568 10:05:01.997394
3569 10:05:02.000459 DATLAT Default: 0xd
3570 10:05:02.000541 0, 0xFFFF, sum = 0
3571 10:05:02.003852 1, 0xFFFF, sum = 0
3572 10:05:02.006852 2, 0xFFFF, sum = 0
3573 10:05:02.006935 3, 0xFFFF, sum = 0
3574 10:05:02.010084 4, 0xFFFF, sum = 0
3575 10:05:02.010168 5, 0xFFFF, sum = 0
3576 10:05:02.013540 6, 0xFFFF, sum = 0
3577 10:05:02.013624 7, 0xFFFF, sum = 0
3578 10:05:02.016700 8, 0xFFFF, sum = 0
3579 10:05:02.016786 9, 0xFFFF, sum = 0
3580 10:05:02.020456 10, 0xFFFF, sum = 0
3581 10:05:02.020542 11, 0xFFFF, sum = 0
3582 10:05:02.023672 12, 0x0, sum = 1
3583 10:05:02.023757 13, 0x0, sum = 2
3584 10:05:02.027160 14, 0x0, sum = 3
3585 10:05:02.027245 15, 0x0, sum = 4
3586 10:05:02.030486 best_step = 13
3587 10:05:02.030569
3588 10:05:02.030653 ==
3589 10:05:02.033869 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 10:05:02.036572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 10:05:02.036657 ==
3592 10:05:02.036758 RX Vref Scan: 0
3593 10:05:02.040158
3594 10:05:02.040241 RX Vref 0 -> 0, step: 1
3595 10:05:02.040326
3596 10:05:02.043494 RX Delay -5 -> 252, step: 4
3597 10:05:02.049690 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3598 10:05:02.053155 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3599 10:05:02.057031 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3600 10:05:02.059703 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3601 10:05:02.062962 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3602 10:05:02.066979 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3603 10:05:02.073328 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3604 10:05:02.076281 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3605 10:05:02.079619 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3606 10:05:02.082861 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3607 10:05:02.086335 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3608 10:05:02.093596 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3609 10:05:02.096698 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3610 10:05:02.099696 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3611 10:05:02.103243 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3612 10:05:02.109476 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3613 10:05:02.109563 ==
3614 10:05:02.113124 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 10:05:02.116458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 10:05:02.116549 ==
3617 10:05:02.116646 DQS Delay:
3618 10:05:02.119927 DQS0 = 0, DQS1 = 0
3619 10:05:02.120010 DQM Delay:
3620 10:05:02.123046 DQM0 = 120, DQM1 = 118
3621 10:05:02.123129 DQ Delay:
3622 10:05:02.126381 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3623 10:05:02.129624 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3624 10:05:02.133027 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3625 10:05:02.136574 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3626 10:05:02.136656
3627 10:05:02.136721
3628 10:05:02.146412 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 403 ps
3629 10:05:02.149329 CH1 RK1: MR19=403, MR18=10EC
3630 10:05:02.152910 CH1_RK1: MR19=0x403, MR18=0x10EC, DQSOSC=403, MR23=63, INC=40, DEC=26
3631 10:05:02.156413 [RxdqsGatingPostProcess] freq 1200
3632 10:05:02.162611 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3633 10:05:02.166076 best DQS0 dly(2T, 0.5T) = (0, 11)
3634 10:05:02.169432 best DQS1 dly(2T, 0.5T) = (0, 11)
3635 10:05:02.172706 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3636 10:05:02.176132 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3637 10:05:02.179578 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 10:05:02.182524 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 10:05:02.185954 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 10:05:02.189122 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 10:05:02.192379 Pre-setting of DQS Precalculation
3642 10:05:02.195774 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3643 10:05:02.202406 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3644 10:05:02.212542 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3645 10:05:02.212637
3646 10:05:02.212704
3647 10:05:02.216036 [Calibration Summary] 2400 Mbps
3648 10:05:02.216120 CH 0, Rank 0
3649 10:05:02.218883 SW Impedance : PASS
3650 10:05:02.218968 DUTY Scan : NO K
3651 10:05:02.222555 ZQ Calibration : PASS
3652 10:05:02.222638 Jitter Meter : NO K
3653 10:05:02.225889 CBT Training : PASS
3654 10:05:02.229314 Write leveling : PASS
3655 10:05:02.229398 RX DQS gating : PASS
3656 10:05:02.232205 RX DQ/DQS(RDDQC) : PASS
3657 10:05:02.235677 TX DQ/DQS : PASS
3658 10:05:02.235760 RX DATLAT : PASS
3659 10:05:02.238929 RX DQ/DQS(Engine): PASS
3660 10:05:02.242116 TX OE : NO K
3661 10:05:02.242201 All Pass.
3662 10:05:02.242267
3663 10:05:02.242327 CH 0, Rank 1
3664 10:05:02.245549 SW Impedance : PASS
3665 10:05:02.249022 DUTY Scan : NO K
3666 10:05:02.249105 ZQ Calibration : PASS
3667 10:05:02.252457 Jitter Meter : NO K
3668 10:05:02.255691 CBT Training : PASS
3669 10:05:02.255776 Write leveling : PASS
3670 10:05:02.258898 RX DQS gating : PASS
3671 10:05:02.262358 RX DQ/DQS(RDDQC) : PASS
3672 10:05:02.262440 TX DQ/DQS : PASS
3673 10:05:02.265754 RX DATLAT : PASS
3674 10:05:02.265837 RX DQ/DQS(Engine): PASS
3675 10:05:02.269606 TX OE : NO K
3676 10:05:02.269690 All Pass.
3677 10:05:02.269755
3678 10:05:02.272346 CH 1, Rank 0
3679 10:05:02.272443 SW Impedance : PASS
3680 10:05:02.275792 DUTY Scan : NO K
3681 10:05:02.278910 ZQ Calibration : PASS
3682 10:05:02.278995 Jitter Meter : NO K
3683 10:05:02.282434 CBT Training : PASS
3684 10:05:02.285522 Write leveling : PASS
3685 10:05:02.285605 RX DQS gating : PASS
3686 10:05:02.288906 RX DQ/DQS(RDDQC) : PASS
3687 10:05:02.291857 TX DQ/DQS : PASS
3688 10:05:02.291939 RX DATLAT : PASS
3689 10:05:02.295223 RX DQ/DQS(Engine): PASS
3690 10:05:02.298819 TX OE : NO K
3691 10:05:02.298902 All Pass.
3692 10:05:02.298968
3693 10:05:02.299029 CH 1, Rank 1
3694 10:05:02.302281 SW Impedance : PASS
3695 10:05:02.305264 DUTY Scan : NO K
3696 10:05:02.305347 ZQ Calibration : PASS
3697 10:05:02.308816 Jitter Meter : NO K
3698 10:05:02.311802 CBT Training : PASS
3699 10:05:02.311885 Write leveling : PASS
3700 10:05:02.315310 RX DQS gating : PASS
3701 10:05:02.318910 RX DQ/DQS(RDDQC) : PASS
3702 10:05:02.318995 TX DQ/DQS : PASS
3703 10:05:02.321815 RX DATLAT : PASS
3704 10:05:02.321898 RX DQ/DQS(Engine): PASS
3705 10:05:02.325361 TX OE : NO K
3706 10:05:02.325446 All Pass.
3707 10:05:02.325512
3708 10:05:02.328769 DramC Write-DBI off
3709 10:05:02.331645 PER_BANK_REFRESH: Hybrid Mode
3710 10:05:02.331728 TX_TRACKING: ON
3711 10:05:02.341636 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3712 10:05:02.344990 [FAST_K] Save calibration result to emmc
3713 10:05:02.348608 dramc_set_vcore_voltage set vcore to 650000
3714 10:05:02.351658 Read voltage for 600, 5
3715 10:05:02.351744 Vio18 = 0
3716 10:05:02.355113 Vcore = 650000
3717 10:05:02.355196 Vdram = 0
3718 10:05:02.355262 Vddq = 0
3719 10:05:02.355323 Vmddr = 0
3720 10:05:02.361759 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3721 10:05:02.368045 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3722 10:05:02.368133 MEM_TYPE=3, freq_sel=19
3723 10:05:02.371907 sv_algorithm_assistance_LP4_1600
3724 10:05:02.375323 ============ PULL DRAM RESETB DOWN ============
3725 10:05:02.381568 ========== PULL DRAM RESETB DOWN end =========
3726 10:05:02.384914 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3727 10:05:02.388430 ===================================
3728 10:05:02.391806 LPDDR4 DRAM CONFIGURATION
3729 10:05:02.395492 ===================================
3730 10:05:02.395576 EX_ROW_EN[0] = 0x0
3731 10:05:02.398803 EX_ROW_EN[1] = 0x0
3732 10:05:02.398886 LP4Y_EN = 0x0
3733 10:05:02.402577 WORK_FSP = 0x0
3734 10:05:02.402661 WL = 0x2
3735 10:05:02.405243 RL = 0x2
3736 10:05:02.405326 BL = 0x2
3737 10:05:02.408130 RPST = 0x0
3738 10:05:02.408213 RD_PRE = 0x0
3739 10:05:02.412042 WR_PRE = 0x1
3740 10:05:02.412125 WR_PST = 0x0
3741 10:05:02.414912 DBI_WR = 0x0
3742 10:05:02.417947 DBI_RD = 0x0
3743 10:05:02.418032 OTF = 0x1
3744 10:05:02.421662 ===================================
3745 10:05:02.424664 ===================================
3746 10:05:02.424748 ANA top config
3747 10:05:02.428119 ===================================
3748 10:05:02.431348 DLL_ASYNC_EN = 0
3749 10:05:02.435063 ALL_SLAVE_EN = 1
3750 10:05:02.438375 NEW_RANK_MODE = 1
3751 10:05:02.441659 DLL_IDLE_MODE = 1
3752 10:05:02.441742 LP45_APHY_COMB_EN = 1
3753 10:05:02.445123 TX_ODT_DIS = 1
3754 10:05:02.447737 NEW_8X_MODE = 1
3755 10:05:02.451392 ===================================
3756 10:05:02.454859 ===================================
3757 10:05:02.457983 data_rate = 1200
3758 10:05:02.461514 CKR = 1
3759 10:05:02.461599 DQ_P2S_RATIO = 8
3760 10:05:02.464507 ===================================
3761 10:05:02.468197 CA_P2S_RATIO = 8
3762 10:05:02.471372 DQ_CA_OPEN = 0
3763 10:05:02.474445 DQ_SEMI_OPEN = 0
3764 10:05:02.477719 CA_SEMI_OPEN = 0
3765 10:05:02.481021 CA_FULL_RATE = 0
3766 10:05:02.481105 DQ_CKDIV4_EN = 1
3767 10:05:02.484590 CA_CKDIV4_EN = 1
3768 10:05:02.488449 CA_PREDIV_EN = 0
3769 10:05:02.491287 PH8_DLY = 0
3770 10:05:02.494598 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3771 10:05:02.497486 DQ_AAMCK_DIV = 4
3772 10:05:02.497570 CA_AAMCK_DIV = 4
3773 10:05:02.501323 CA_ADMCK_DIV = 4
3774 10:05:02.504443 DQ_TRACK_CA_EN = 0
3775 10:05:02.507889 CA_PICK = 600
3776 10:05:02.511288 CA_MCKIO = 600
3777 10:05:02.514143 MCKIO_SEMI = 0
3778 10:05:02.517836 PLL_FREQ = 2288
3779 10:05:02.517921 DQ_UI_PI_RATIO = 32
3780 10:05:02.520934 CA_UI_PI_RATIO = 0
3781 10:05:02.524203 ===================================
3782 10:05:02.527321 ===================================
3783 10:05:02.530627 memory_type:LPDDR4
3784 10:05:02.533917 GP_NUM : 10
3785 10:05:02.534001 SRAM_EN : 1
3786 10:05:02.537578 MD32_EN : 0
3787 10:05:02.540811 ===================================
3788 10:05:02.544071 [ANA_INIT] >>>>>>>>>>>>>>
3789 10:05:02.544153 <<<<<< [CONFIGURE PHASE]: ANA_TX
3790 10:05:02.547367 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3791 10:05:02.550717 ===================================
3792 10:05:02.554878 data_rate = 1200,PCW = 0X5800
3793 10:05:02.557451 ===================================
3794 10:05:02.560898 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3795 10:05:02.567301 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 10:05:02.573856 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3797 10:05:02.577277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3798 10:05:02.580579 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3799 10:05:02.584066 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3800 10:05:02.587503 [ANA_INIT] flow start
3801 10:05:02.587589 [ANA_INIT] PLL >>>>>>>>
3802 10:05:02.591152 [ANA_INIT] PLL <<<<<<<<
3803 10:05:02.593802 [ANA_INIT] MIDPI >>>>>>>>
3804 10:05:02.593887 [ANA_INIT] MIDPI <<<<<<<<
3805 10:05:02.597282 [ANA_INIT] DLL >>>>>>>>
3806 10:05:02.600787 [ANA_INIT] flow end
3807 10:05:02.604114 ============ LP4 DIFF to SE enter ============
3808 10:05:02.607566 ============ LP4 DIFF to SE exit ============
3809 10:05:02.610700 [ANA_INIT] <<<<<<<<<<<<<
3810 10:05:02.614314 [Flow] Enable top DCM control >>>>>
3811 10:05:02.617646 [Flow] Enable top DCM control <<<<<
3812 10:05:02.620545 Enable DLL master slave shuffle
3813 10:05:02.623588 ==============================================================
3814 10:05:02.627802 Gating Mode config
3815 10:05:02.633760 ==============================================================
3816 10:05:02.633848 Config description:
3817 10:05:02.644040 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3818 10:05:02.650531 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3819 10:05:02.654081 SELPH_MODE 0: By rank 1: By Phase
3820 10:05:02.660553 ==============================================================
3821 10:05:02.663456 GAT_TRACK_EN = 1
3822 10:05:02.667289 RX_GATING_MODE = 2
3823 10:05:02.670185 RX_GATING_TRACK_MODE = 2
3824 10:05:02.674053 SELPH_MODE = 1
3825 10:05:02.676947 PICG_EARLY_EN = 1
3826 10:05:02.680455 VALID_LAT_VALUE = 1
3827 10:05:02.683497 ==============================================================
3828 10:05:02.687202 Enter into Gating configuration >>>>
3829 10:05:02.690758 Exit from Gating configuration <<<<
3830 10:05:02.693619 Enter into DVFS_PRE_config >>>>>
3831 10:05:02.707412 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3832 10:05:02.707530 Exit from DVFS_PRE_config <<<<<
3833 10:05:02.710392 Enter into PICG configuration >>>>
3834 10:05:02.713707 Exit from PICG configuration <<<<
3835 10:05:02.717296 [RX_INPUT] configuration >>>>>
3836 10:05:02.720286 [RX_INPUT] configuration <<<<<
3837 10:05:02.726714 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3838 10:05:02.730273 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3839 10:05:02.736741 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3840 10:05:02.743537 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3841 10:05:02.750385 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 10:05:02.757080 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 10:05:02.760019 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3844 10:05:02.763652 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3845 10:05:02.766999 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3846 10:05:02.773154 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3847 10:05:02.777219 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3848 10:05:02.779980 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3849 10:05:02.783587 ===================================
3850 10:05:02.786988 LPDDR4 DRAM CONFIGURATION
3851 10:05:02.790155 ===================================
3852 10:05:02.790237 EX_ROW_EN[0] = 0x0
3853 10:05:02.793363 EX_ROW_EN[1] = 0x0
3854 10:05:02.796737 LP4Y_EN = 0x0
3855 10:05:02.796848 WORK_FSP = 0x0
3856 10:05:02.799921 WL = 0x2
3857 10:05:02.800004 RL = 0x2
3858 10:05:02.803424 BL = 0x2
3859 10:05:02.803506 RPST = 0x0
3860 10:05:02.806948 RD_PRE = 0x0
3861 10:05:02.807031 WR_PRE = 0x1
3862 10:05:02.809825 WR_PST = 0x0
3863 10:05:02.809906 DBI_WR = 0x0
3864 10:05:02.813776 DBI_RD = 0x0
3865 10:05:02.813857 OTF = 0x1
3866 10:05:02.816467 ===================================
3867 10:05:02.819954 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3868 10:05:02.826578 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3869 10:05:02.830147 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 10:05:02.833306 ===================================
3871 10:05:02.836323 LPDDR4 DRAM CONFIGURATION
3872 10:05:02.839996 ===================================
3873 10:05:02.840078 EX_ROW_EN[0] = 0x10
3874 10:05:02.843130 EX_ROW_EN[1] = 0x0
3875 10:05:02.843214 LP4Y_EN = 0x0
3876 10:05:02.846627 WORK_FSP = 0x0
3877 10:05:02.850676 WL = 0x2
3878 10:05:02.850758 RL = 0x2
3879 10:05:02.853210 BL = 0x2
3880 10:05:02.853291 RPST = 0x0
3881 10:05:02.856329 RD_PRE = 0x0
3882 10:05:02.856411 WR_PRE = 0x1
3883 10:05:02.859907 WR_PST = 0x0
3884 10:05:02.859989 DBI_WR = 0x0
3885 10:05:02.863392 DBI_RD = 0x0
3886 10:05:02.863474 OTF = 0x1
3887 10:05:02.866452 ===================================
3888 10:05:02.873092 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3889 10:05:02.877072 nWR fixed to 30
3890 10:05:02.880777 [ModeRegInit_LP4] CH0 RK0
3891 10:05:02.880902 [ModeRegInit_LP4] CH0 RK1
3892 10:05:02.884379 [ModeRegInit_LP4] CH1 RK0
3893 10:05:02.887419 [ModeRegInit_LP4] CH1 RK1
3894 10:05:02.887501 match AC timing 17
3895 10:05:02.894080 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3896 10:05:02.897651 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3897 10:05:02.900786 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3898 10:05:02.907036 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3899 10:05:02.910706 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3900 10:05:02.910789 ==
3901 10:05:02.914138 Dram Type= 6, Freq= 0, CH_0, rank 0
3902 10:05:02.917159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3903 10:05:02.917246 ==
3904 10:05:02.923664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3905 10:05:02.930087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3906 10:05:02.933450 [CA 0] Center 35 (5~66) winsize 62
3907 10:05:02.936742 [CA 1] Center 35 (5~66) winsize 62
3908 10:05:02.940574 [CA 2] Center 33 (3~64) winsize 62
3909 10:05:02.943941 [CA 3] Center 33 (2~64) winsize 63
3910 10:05:02.947043 [CA 4] Center 33 (2~64) winsize 63
3911 10:05:02.950100 [CA 5] Center 32 (2~63) winsize 62
3912 10:05:02.950183
3913 10:05:02.953754 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3914 10:05:02.953836
3915 10:05:02.956635 [CATrainingPosCal] consider 1 rank data
3916 10:05:02.960065 u2DelayCellTimex100 = 270/100 ps
3917 10:05:02.963490 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3918 10:05:02.966735 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3919 10:05:02.969912 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3920 10:05:02.973418 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3921 10:05:02.976541 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3922 10:05:02.983407 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3923 10:05:02.983489
3924 10:05:02.986857 CA PerBit enable=1, Macro0, CA PI delay=32
3925 10:05:02.986939
3926 10:05:02.989965 [CBTSetCACLKResult] CA Dly = 32
3927 10:05:02.990047 CS Dly: 4 (0~35)
3928 10:05:02.990113 ==
3929 10:05:02.993386 Dram Type= 6, Freq= 0, CH_0, rank 1
3930 10:05:02.996951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 10:05:02.997035 ==
3932 10:05:03.003371 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 10:05:03.009678 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3934 10:05:03.013299 [CA 0] Center 35 (5~66) winsize 62
3935 10:05:03.016790 [CA 1] Center 35 (5~66) winsize 62
3936 10:05:03.019900 [CA 2] Center 34 (3~65) winsize 63
3937 10:05:03.023521 [CA 3] Center 33 (2~64) winsize 63
3938 10:05:03.026620 [CA 4] Center 33 (2~64) winsize 63
3939 10:05:03.030142 [CA 5] Center 32 (2~63) winsize 62
3940 10:05:03.030225
3941 10:05:03.033329 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3942 10:05:03.033412
3943 10:05:03.037012 [CATrainingPosCal] consider 2 rank data
3944 10:05:03.039628 u2DelayCellTimex100 = 270/100 ps
3945 10:05:03.042963 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3946 10:05:03.046460 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3947 10:05:03.049883 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3948 10:05:03.052778 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3949 10:05:03.059611 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3950 10:05:03.063444 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3951 10:05:03.063530
3952 10:05:03.066572 CA PerBit enable=1, Macro0, CA PI delay=32
3953 10:05:03.066656
3954 10:05:03.069759 [CBTSetCACLKResult] CA Dly = 32
3955 10:05:03.069842 CS Dly: 4 (0~36)
3956 10:05:03.069907
3957 10:05:03.073495 ----->DramcWriteLeveling(PI) begin...
3958 10:05:03.073579 ==
3959 10:05:03.076499 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 10:05:03.083108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 10:05:03.083197 ==
3962 10:05:03.086054 Write leveling (Byte 0): 33 => 33
3963 10:05:03.086138 Write leveling (Byte 1): 30 => 30
3964 10:05:03.089943 DramcWriteLeveling(PI) end<-----
3965 10:05:03.090065
3966 10:05:03.090131 ==
3967 10:05:03.092768 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 10:05:03.099377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 10:05:03.099470 ==
3970 10:05:03.103463 [Gating] SW mode calibration
3971 10:05:03.109423 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3972 10:05:03.113029 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3973 10:05:03.119643 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 10:05:03.123278 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 10:05:03.126338 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 10:05:03.133254 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
3977 10:05:03.136135 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
3978 10:05:03.139447 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 10:05:03.143115 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 10:05:03.149538 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 10:05:03.152633 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 10:05:03.156206 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 10:05:03.162865 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 10:05:03.166330 0 10 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
3985 10:05:03.169756 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
3986 10:05:03.176253 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 10:05:03.179683 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 10:05:03.183222 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 10:05:03.189441 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 10:05:03.192579 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 10:05:03.195855 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3992 10:05:03.202560 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3993 10:05:03.205937 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3994 10:05:03.209232 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 10:05:03.215823 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 10:05:03.219963 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 10:05:03.222711 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 10:05:03.229675 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 10:05:03.232549 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 10:05:03.235626 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 10:05:03.242631 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 10:05:03.246223 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 10:05:03.249262 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 10:05:03.255938 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 10:05:03.259024 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 10:05:03.262604 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 10:05:03.268840 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 10:05:03.272083 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4009 10:05:03.275602 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4010 10:05:03.279115 Total UI for P1: 0, mck2ui 16
4011 10:05:03.282259 best dqsien dly found for B0: ( 0, 13, 12)
4012 10:05:03.285978 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 10:05:03.289058 Total UI for P1: 0, mck2ui 16
4014 10:05:03.292630 best dqsien dly found for B1: ( 0, 13, 18)
4015 10:05:03.298604 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4016 10:05:03.301931 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4017 10:05:03.302020
4018 10:05:03.305487 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4019 10:05:03.308731 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4020 10:05:03.312438 [Gating] SW calibration Done
4021 10:05:03.312522 ==
4022 10:05:03.315452 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 10:05:03.318823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 10:05:03.318907 ==
4025 10:05:03.322473 RX Vref Scan: 0
4026 10:05:03.322556
4027 10:05:03.322621 RX Vref 0 -> 0, step: 1
4028 10:05:03.322680
4029 10:05:03.325745 RX Delay -230 -> 252, step: 16
4030 10:05:03.328943 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4031 10:05:03.335464 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4032 10:05:03.339050 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4033 10:05:03.341993 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4034 10:05:03.345488 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4035 10:05:03.352307 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4036 10:05:03.355847 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4037 10:05:03.358703 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4038 10:05:03.362200 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4039 10:05:03.365927 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4040 10:05:03.371764 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4041 10:05:03.375385 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4042 10:05:03.378691 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4043 10:05:03.381667 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4044 10:05:03.388608 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4045 10:05:03.392054 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4046 10:05:03.392143 ==
4047 10:05:03.395189 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 10:05:03.398509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 10:05:03.398596 ==
4050 10:05:03.401849 DQS Delay:
4051 10:05:03.401931 DQS0 = 0, DQS1 = 0
4052 10:05:03.401997 DQM Delay:
4053 10:05:03.404957 DQM0 = 51, DQM1 = 46
4054 10:05:03.405038 DQ Delay:
4055 10:05:03.408226 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4056 10:05:03.411633 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4057 10:05:03.415339 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4058 10:05:03.418269 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4059 10:05:03.418352
4060 10:05:03.418417
4061 10:05:03.418479 ==
4062 10:05:03.421720 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 10:05:03.427957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 10:05:03.428042 ==
4065 10:05:03.428109
4066 10:05:03.428168
4067 10:05:03.428229 TX Vref Scan disable
4068 10:05:03.432043 == TX Byte 0 ==
4069 10:05:03.435354 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4070 10:05:03.441751 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4071 10:05:03.441837 == TX Byte 1 ==
4072 10:05:03.445335 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4073 10:05:03.452222 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4074 10:05:03.452308 ==
4075 10:05:03.455080 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 10:05:03.458675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 10:05:03.458758 ==
4078 10:05:03.458823
4079 10:05:03.458883
4080 10:05:03.462312 TX Vref Scan disable
4081 10:05:03.465088 == TX Byte 0 ==
4082 10:05:03.468461 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4083 10:05:03.471917 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4084 10:05:03.475540 == TX Byte 1 ==
4085 10:05:03.478721 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4086 10:05:03.482359 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4087 10:05:03.482442
4088 10:05:03.482506 [DATLAT]
4089 10:05:03.485029 Freq=600, CH0 RK0
4090 10:05:03.485111
4091 10:05:03.485176 DATLAT Default: 0x9
4092 10:05:03.488739 0, 0xFFFF, sum = 0
4093 10:05:03.491745 1, 0xFFFF, sum = 0
4094 10:05:03.491828 2, 0xFFFF, sum = 0
4095 10:05:03.494980 3, 0xFFFF, sum = 0
4096 10:05:03.495063 4, 0xFFFF, sum = 0
4097 10:05:03.498846 5, 0xFFFF, sum = 0
4098 10:05:03.498931 6, 0xFFFF, sum = 0
4099 10:05:03.501612 7, 0xFFFF, sum = 0
4100 10:05:03.501695 8, 0x0, sum = 1
4101 10:05:03.501762 9, 0x0, sum = 2
4102 10:05:03.505238 10, 0x0, sum = 3
4103 10:05:03.505321 11, 0x0, sum = 4
4104 10:05:03.508396 best_step = 9
4105 10:05:03.508504
4106 10:05:03.508597 ==
4107 10:05:03.511453 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 10:05:03.515116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 10:05:03.515201 ==
4110 10:05:03.518693 RX Vref Scan: 1
4111 10:05:03.518818
4112 10:05:03.518883 RX Vref 0 -> 0, step: 1
4113 10:05:03.518944
4114 10:05:03.521680 RX Delay -163 -> 252, step: 8
4115 10:05:03.521765
4116 10:05:03.525113 Set Vref, RX VrefLevel [Byte0]: 55
4117 10:05:03.528124 [Byte1]: 50
4118 10:05:03.532244
4119 10:05:03.532326 Final RX Vref Byte 0 = 55 to rank0
4120 10:05:03.535499 Final RX Vref Byte 1 = 50 to rank0
4121 10:05:03.539049 Final RX Vref Byte 0 = 55 to rank1
4122 10:05:03.542841 Final RX Vref Byte 1 = 50 to rank1==
4123 10:05:03.545842 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 10:05:03.552182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 10:05:03.552266 ==
4126 10:05:03.552332 DQS Delay:
4127 10:05:03.552392 DQS0 = 0, DQS1 = 0
4128 10:05:03.555579 DQM Delay:
4129 10:05:03.555660 DQM0 = 53, DQM1 = 46
4130 10:05:03.559024 DQ Delay:
4131 10:05:03.562495 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4132 10:05:03.562577 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4133 10:05:03.565492 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4134 10:05:03.572491 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =52
4135 10:05:03.572574
4136 10:05:03.572640
4137 10:05:03.579151 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e61, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4138 10:05:03.582488 CH0 RK0: MR19=808, MR18=6E61
4139 10:05:03.589490 CH0_RK0: MR19=0x808, MR18=0x6E61, DQSOSC=389, MR23=63, INC=173, DEC=115
4140 10:05:03.589577
4141 10:05:03.592488 ----->DramcWriteLeveling(PI) begin...
4142 10:05:03.592571 ==
4143 10:05:03.595775 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 10:05:03.599008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 10:05:03.599092 ==
4146 10:05:03.602560 Write leveling (Byte 0): 36 => 36
4147 10:05:03.605578 Write leveling (Byte 1): 32 => 32
4148 10:05:03.609305 DramcWriteLeveling(PI) end<-----
4149 10:05:03.609389
4150 10:05:03.609455 ==
4151 10:05:03.612327 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 10:05:03.615963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 10:05:03.616048 ==
4154 10:05:03.618954 [Gating] SW mode calibration
4155 10:05:03.625599 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4156 10:05:03.632443 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4157 10:05:03.635930 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 10:05:03.639218 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 10:05:03.645505 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 10:05:03.649012 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4161 10:05:03.651995 0 9 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4162 10:05:03.658974 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 10:05:03.661894 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 10:05:03.665228 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 10:05:03.672068 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 10:05:03.675388 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 10:05:03.679277 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 10:05:03.685259 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4169 10:05:03.689382 0 10 16 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
4170 10:05:03.692016 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 10:05:03.698685 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 10:05:03.702393 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 10:05:03.705292 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 10:05:03.712371 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 10:05:03.715657 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 10:05:03.718673 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 10:05:03.725219 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4178 10:05:03.728920 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 10:05:03.731798 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 10:05:03.738591 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 10:05:03.742207 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 10:05:03.745612 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 10:05:03.748995 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 10:05:03.755521 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 10:05:03.758958 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 10:05:03.762465 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 10:05:03.769003 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 10:05:03.771875 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 10:05:03.775129 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 10:05:03.782258 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 10:05:03.785091 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4192 10:05:03.788521 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4193 10:05:03.795181 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4194 10:05:03.795265 Total UI for P1: 0, mck2ui 16
4195 10:05:03.802078 best dqsien dly found for B1: ( 0, 13, 12)
4196 10:05:03.805386 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 10:05:03.808371 Total UI for P1: 0, mck2ui 16
4198 10:05:03.811765 best dqsien dly found for B0: ( 0, 13, 12)
4199 10:05:03.815596 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4200 10:05:03.818690 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4201 10:05:03.818774
4202 10:05:03.822651 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4203 10:05:03.825126 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4204 10:05:03.828573 [Gating] SW calibration Done
4205 10:05:03.828657 ==
4206 10:05:03.831666 Dram Type= 6, Freq= 0, CH_0, rank 1
4207 10:05:03.835489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 10:05:03.838781 ==
4209 10:05:03.838864 RX Vref Scan: 0
4210 10:05:03.838931
4211 10:05:03.841634 RX Vref 0 -> 0, step: 1
4212 10:05:03.841717
4213 10:05:03.845248 RX Delay -230 -> 252, step: 16
4214 10:05:03.848507 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4215 10:05:03.851931 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4216 10:05:03.855078 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4217 10:05:03.861600 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4218 10:05:03.865001 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4219 10:05:03.868765 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4220 10:05:03.871639 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4221 10:05:03.875064 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4222 10:05:03.881473 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4223 10:05:03.885151 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4224 10:05:03.888652 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4225 10:05:03.891884 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4226 10:05:03.898310 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4227 10:05:03.901969 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4228 10:05:03.905097 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4229 10:05:03.908018 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4230 10:05:03.908106 ==
4231 10:05:03.911262 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 10:05:03.918579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 10:05:03.918666 ==
4234 10:05:03.918734 DQS Delay:
4235 10:05:03.921636 DQS0 = 0, DQS1 = 0
4236 10:05:03.921722 DQM Delay:
4237 10:05:03.921788 DQM0 = 51, DQM1 = 42
4238 10:05:03.924555 DQ Delay:
4239 10:05:03.928096 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4240 10:05:03.931612 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4241 10:05:03.934963 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4242 10:05:03.938723 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4243 10:05:03.938807
4244 10:05:03.938873
4245 10:05:03.938934 ==
4246 10:05:03.941641 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 10:05:03.944941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 10:05:03.945025 ==
4249 10:05:03.945092
4250 10:05:03.945152
4251 10:05:03.948070 TX Vref Scan disable
4252 10:05:03.948152 == TX Byte 0 ==
4253 10:05:03.954758 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4254 10:05:03.957967 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4255 10:05:03.961172 == TX Byte 1 ==
4256 10:05:03.964827 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4257 10:05:03.968558 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4258 10:05:03.968642 ==
4259 10:05:03.971381 Dram Type= 6, Freq= 0, CH_0, rank 1
4260 10:05:03.974869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4261 10:05:03.974954 ==
4262 10:05:03.977872
4263 10:05:03.977954
4264 10:05:03.978020 TX Vref Scan disable
4265 10:05:03.982162 == TX Byte 0 ==
4266 10:05:03.984843 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4267 10:05:03.991479 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4268 10:05:03.991562 == TX Byte 1 ==
4269 10:05:03.994973 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4270 10:05:04.001428 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4271 10:05:04.001512
4272 10:05:04.001578 [DATLAT]
4273 10:05:04.001642 Freq=600, CH0 RK1
4274 10:05:04.001701
4275 10:05:04.005132 DATLAT Default: 0x9
4276 10:05:04.005214 0, 0xFFFF, sum = 0
4277 10:05:04.007964 1, 0xFFFF, sum = 0
4278 10:05:04.011171 2, 0xFFFF, sum = 0
4279 10:05:04.011256 3, 0xFFFF, sum = 0
4280 10:05:04.014477 4, 0xFFFF, sum = 0
4281 10:05:04.014563 5, 0xFFFF, sum = 0
4282 10:05:04.017950 6, 0xFFFF, sum = 0
4283 10:05:04.018061 7, 0xFFFF, sum = 0
4284 10:05:04.021291 8, 0x0, sum = 1
4285 10:05:04.021377 9, 0x0, sum = 2
4286 10:05:04.021446 10, 0x0, sum = 3
4287 10:05:04.024888 11, 0x0, sum = 4
4288 10:05:04.024972 best_step = 9
4289 10:05:04.025039
4290 10:05:04.025102 ==
4291 10:05:04.028027 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 10:05:04.034687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 10:05:04.034773 ==
4294 10:05:04.034839 RX Vref Scan: 0
4295 10:05:04.034900
4296 10:05:04.037912 RX Vref 0 -> 0, step: 1
4297 10:05:04.037994
4298 10:05:04.041112 RX Delay -163 -> 252, step: 8
4299 10:05:04.044186 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4300 10:05:04.050853 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4301 10:05:04.054463 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4302 10:05:04.057483 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4303 10:05:04.060815 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4304 10:05:04.064700 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4305 10:05:04.070741 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4306 10:05:04.074307 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4307 10:05:04.077838 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4308 10:05:04.080739 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4309 10:05:04.084403 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4310 10:05:04.090985 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4311 10:05:04.093863 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4312 10:05:04.097722 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4313 10:05:04.100573 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4314 10:05:04.107400 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4315 10:05:04.107484 ==
4316 10:05:04.110685 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 10:05:04.114140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 10:05:04.114223 ==
4319 10:05:04.114288 DQS Delay:
4320 10:05:04.117578 DQS0 = 0, DQS1 = 0
4321 10:05:04.117661 DQM Delay:
4322 10:05:04.120555 DQM0 = 54, DQM1 = 47
4323 10:05:04.120661 DQ Delay:
4324 10:05:04.124073 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4325 10:05:04.127140 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =64
4326 10:05:04.130683 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4327 10:05:04.133861 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4328 10:05:04.133940
4329 10:05:04.134003
4330 10:05:04.140568 [DQSOSCAuto] RK1, (LSB)MR18= 0x6627, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4331 10:05:04.143817 CH0 RK1: MR19=808, MR18=6627
4332 10:05:04.150377 CH0_RK1: MR19=0x808, MR18=0x6627, DQSOSC=390, MR23=63, INC=172, DEC=114
4333 10:05:04.153782 [RxdqsGatingPostProcess] freq 600
4334 10:05:04.160572 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4335 10:05:04.163895 Pre-setting of DQS Precalculation
4336 10:05:04.167257 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4337 10:05:04.167341 ==
4338 10:05:04.170140 Dram Type= 6, Freq= 0, CH_1, rank 0
4339 10:05:04.173482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 10:05:04.173566 ==
4341 10:05:04.180225 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4342 10:05:04.187129 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4343 10:05:04.190218 [CA 0] Center 35 (5~66) winsize 62
4344 10:05:04.193560 [CA 1] Center 35 (5~66) winsize 62
4345 10:05:04.197019 [CA 2] Center 34 (4~65) winsize 62
4346 10:05:04.200458 [CA 3] Center 34 (3~65) winsize 63
4347 10:05:04.203814 [CA 4] Center 34 (4~65) winsize 62
4348 10:05:04.206936 [CA 5] Center 33 (3~64) winsize 62
4349 10:05:04.207020
4350 10:05:04.210022 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4351 10:05:04.210106
4352 10:05:04.213668 [CATrainingPosCal] consider 1 rank data
4353 10:05:04.217084 u2DelayCellTimex100 = 270/100 ps
4354 10:05:04.220214 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4355 10:05:04.223932 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4356 10:05:04.227223 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4357 10:05:04.230380 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4358 10:05:04.233792 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4359 10:05:04.237218 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4360 10:05:04.240387
4361 10:05:04.243495 CA PerBit enable=1, Macro0, CA PI delay=33
4362 10:05:04.243580
4363 10:05:04.246891 [CBTSetCACLKResult] CA Dly = 33
4364 10:05:04.246975 CS Dly: 5 (0~36)
4365 10:05:04.247042 ==
4366 10:05:04.250011 Dram Type= 6, Freq= 0, CH_1, rank 1
4367 10:05:04.253559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 10:05:04.253643 ==
4369 10:05:04.260391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4370 10:05:04.266810 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4371 10:05:04.270049 [CA 0] Center 36 (5~67) winsize 63
4372 10:05:04.273408 [CA 1] Center 36 (5~67) winsize 63
4373 10:05:04.276849 [CA 2] Center 34 (4~65) winsize 62
4374 10:05:04.280435 [CA 3] Center 34 (4~65) winsize 62
4375 10:05:04.283335 [CA 4] Center 34 (4~65) winsize 62
4376 10:05:04.286763 [CA 5] Center 34 (3~65) winsize 63
4377 10:05:04.286847
4378 10:05:04.290203 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4379 10:05:04.290287
4380 10:05:04.293329 [CATrainingPosCal] consider 2 rank data
4381 10:05:04.297158 u2DelayCellTimex100 = 270/100 ps
4382 10:05:04.300038 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4383 10:05:04.303363 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4384 10:05:04.306826 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4385 10:05:04.309674 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 10:05:04.316957 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4387 10:05:04.320240 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4388 10:05:04.320323
4389 10:05:04.323337 CA PerBit enable=1, Macro0, CA PI delay=33
4390 10:05:04.323421
4391 10:05:04.326616 [CBTSetCACLKResult] CA Dly = 33
4392 10:05:04.326699 CS Dly: 6 (0~38)
4393 10:05:04.326766
4394 10:05:04.329719 ----->DramcWriteLeveling(PI) begin...
4395 10:05:04.329803 ==
4396 10:05:04.333352 Dram Type= 6, Freq= 0, CH_1, rank 0
4397 10:05:04.340405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 10:05:04.340493 ==
4399 10:05:04.343608 Write leveling (Byte 0): 28 => 28
4400 10:05:04.343691 Write leveling (Byte 1): 31 => 31
4401 10:05:04.346876 DramcWriteLeveling(PI) end<-----
4402 10:05:04.346959
4403 10:05:04.347023 ==
4404 10:05:04.350337 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 10:05:04.356632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 10:05:04.356717 ==
4407 10:05:04.359768 [Gating] SW mode calibration
4408 10:05:04.366476 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4409 10:05:04.370075 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4410 10:05:04.376654 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 10:05:04.380226 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 10:05:04.383276 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4413 10:05:04.389989 0 9 12 | B1->B0 | 3030 2e2e | 0 1 | (1 0) (0 0)
4414 10:05:04.393677 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 10:05:04.396924 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 10:05:04.403097 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 10:05:04.406336 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 10:05:04.409525 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 10:05:04.413010 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 10:05:04.419666 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 10:05:04.423083 0 10 12 | B1->B0 | 3636 3939 | 0 0 | (0 0) (1 1)
4422 10:05:04.426645 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 10:05:04.433204 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 10:05:04.436626 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 10:05:04.439806 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 10:05:04.446860 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 10:05:04.449989 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 10:05:04.453456 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4429 10:05:04.460392 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 10:05:04.463082 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 10:05:04.466166 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 10:05:04.473724 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 10:05:04.476918 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 10:05:04.479599 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 10:05:04.486078 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 10:05:04.489650 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 10:05:04.493139 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 10:05:04.499690 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 10:05:04.503091 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 10:05:04.506495 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 10:05:04.509859 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 10:05:04.516582 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 10:05:04.519846 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 10:05:04.522776 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 10:05:04.529806 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4446 10:05:04.533466 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 10:05:04.536146 Total UI for P1: 0, mck2ui 16
4448 10:05:04.539436 best dqsien dly found for B0: ( 0, 13, 12)
4449 10:05:04.542979 Total UI for P1: 0, mck2ui 16
4450 10:05:04.546456 best dqsien dly found for B1: ( 0, 13, 12)
4451 10:05:04.549396 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4452 10:05:04.552794 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4453 10:05:04.552914
4454 10:05:04.556165 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4455 10:05:04.562522 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4456 10:05:04.562606 [Gating] SW calibration Done
4457 10:05:04.562672 ==
4458 10:05:04.565867 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 10:05:04.572541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 10:05:04.572627 ==
4461 10:05:04.572694 RX Vref Scan: 0
4462 10:05:04.572756
4463 10:05:04.575938 RX Vref 0 -> 0, step: 1
4464 10:05:04.576034
4465 10:05:04.579454 RX Delay -230 -> 252, step: 16
4466 10:05:04.582553 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4467 10:05:04.586215 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4468 10:05:04.589502 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4469 10:05:04.596022 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4470 10:05:04.599336 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4471 10:05:04.602565 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4472 10:05:04.605988 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4473 10:05:04.612351 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4474 10:05:04.616235 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4475 10:05:04.619104 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4476 10:05:04.622743 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4477 10:05:04.629568 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4478 10:05:04.633024 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4479 10:05:04.635866 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4480 10:05:04.639056 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4481 10:05:04.645786 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4482 10:05:04.645872 ==
4483 10:05:04.649086 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 10:05:04.652418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 10:05:04.652502 ==
4486 10:05:04.652568 DQS Delay:
4487 10:05:04.655283 DQS0 = 0, DQS1 = 0
4488 10:05:04.655366 DQM Delay:
4489 10:05:04.658960 DQM0 = 51, DQM1 = 48
4490 10:05:04.659043 DQ Delay:
4491 10:05:04.662328 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4492 10:05:04.665618 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4493 10:05:04.668567 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4494 10:05:04.671948 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4495 10:05:04.672032
4496 10:05:04.672098
4497 10:05:04.672159 ==
4498 10:05:04.675422 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 10:05:04.679068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 10:05:04.679152 ==
4501 10:05:04.679219
4502 10:05:04.679281
4503 10:05:04.682155 TX Vref Scan disable
4504 10:05:04.685466 == TX Byte 0 ==
4505 10:05:04.688994 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4506 10:05:04.692288 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4507 10:05:04.695046 == TX Byte 1 ==
4508 10:05:04.698725 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4509 10:05:04.702022 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4510 10:05:04.702106 ==
4511 10:05:04.705368 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 10:05:04.711738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 10:05:04.711825 ==
4514 10:05:04.711892
4515 10:05:04.711953
4516 10:05:04.712012 TX Vref Scan disable
4517 10:05:04.716666 == TX Byte 0 ==
4518 10:05:04.719599 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4519 10:05:04.726540 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4520 10:05:04.726629 == TX Byte 1 ==
4521 10:05:04.730139 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4522 10:05:04.733321 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4523 10:05:04.736142
4524 10:05:04.736225 [DATLAT]
4525 10:05:04.736291 Freq=600, CH1 RK0
4526 10:05:04.736353
4527 10:05:04.739661 DATLAT Default: 0x9
4528 10:05:04.739744 0, 0xFFFF, sum = 0
4529 10:05:04.743319 1, 0xFFFF, sum = 0
4530 10:05:04.743404 2, 0xFFFF, sum = 0
4531 10:05:04.746104 3, 0xFFFF, sum = 0
4532 10:05:04.746188 4, 0xFFFF, sum = 0
4533 10:05:04.749427 5, 0xFFFF, sum = 0
4534 10:05:04.749511 6, 0xFFFF, sum = 0
4535 10:05:04.752971 7, 0xFFFF, sum = 0
4536 10:05:04.753055 8, 0x0, sum = 1
4537 10:05:04.756387 9, 0x0, sum = 2
4538 10:05:04.756471 10, 0x0, sum = 3
4539 10:05:04.759622 11, 0x0, sum = 4
4540 10:05:04.759705 best_step = 9
4541 10:05:04.759771
4542 10:05:04.759832 ==
4543 10:05:04.762799 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 10:05:04.769521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 10:05:04.769619 ==
4546 10:05:04.769685 RX Vref Scan: 1
4547 10:05:04.769747
4548 10:05:04.773110 RX Vref 0 -> 0, step: 1
4549 10:05:04.773193
4550 10:05:04.776379 RX Delay -163 -> 252, step: 8
4551 10:05:04.776462
4552 10:05:04.779510 Set Vref, RX VrefLevel [Byte0]: 54
4553 10:05:04.782973 [Byte1]: 56
4554 10:05:04.783056
4555 10:05:04.786669 Final RX Vref Byte 0 = 54 to rank0
4556 10:05:04.789404 Final RX Vref Byte 1 = 56 to rank0
4557 10:05:04.793027 Final RX Vref Byte 0 = 54 to rank1
4558 10:05:04.796425 Final RX Vref Byte 1 = 56 to rank1==
4559 10:05:04.799934 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 10:05:04.802697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 10:05:04.802781 ==
4562 10:05:04.805833 DQS Delay:
4563 10:05:04.805917 DQS0 = 0, DQS1 = 0
4564 10:05:04.805983 DQM Delay:
4565 10:05:04.809632 DQM0 = 48, DQM1 = 44
4566 10:05:04.809716 DQ Delay:
4567 10:05:04.812771 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =44
4568 10:05:04.816252 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4569 10:05:04.819310 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4570 10:05:04.822709 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4571 10:05:04.822793
4572 10:05:04.822859
4573 10:05:04.832793 [DQSOSCAuto] RK0, (LSB)MR18= 0x466b, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4574 10:05:04.836416 CH1 RK0: MR19=808, MR18=466B
4575 10:05:04.839440 CH1_RK0: MR19=0x808, MR18=0x466B, DQSOSC=389, MR23=63, INC=173, DEC=115
4576 10:05:04.839524
4577 10:05:04.842431 ----->DramcWriteLeveling(PI) begin...
4578 10:05:04.845975 ==
4579 10:05:04.849568 Dram Type= 6, Freq= 0, CH_1, rank 1
4580 10:05:04.852683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 10:05:04.852768 ==
4582 10:05:04.856009 Write leveling (Byte 0): 29 => 29
4583 10:05:04.859930 Write leveling (Byte 1): 32 => 32
4584 10:05:04.862561 DramcWriteLeveling(PI) end<-----
4585 10:05:04.862645
4586 10:05:04.862711 ==
4587 10:05:04.866405 Dram Type= 6, Freq= 0, CH_1, rank 1
4588 10:05:04.869110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 10:05:04.869194 ==
4590 10:05:04.872832 [Gating] SW mode calibration
4591 10:05:04.879547 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4592 10:05:04.882582 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4593 10:05:04.889336 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4594 10:05:04.892640 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 10:05:04.896117 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4596 10:05:04.902729 0 9 12 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 0)
4597 10:05:04.905985 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 10:05:04.909586 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 10:05:04.915687 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 10:05:04.918963 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 10:05:04.922636 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 10:05:04.929184 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 10:05:04.932828 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 10:05:04.935798 0 10 12 | B1->B0 | 3b3b 3434 | 1 1 | (0 0) (0 0)
4605 10:05:04.942414 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 10:05:04.945894 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 10:05:04.949289 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 10:05:04.955703 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 10:05:04.959426 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 10:05:04.962418 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 10:05:04.969182 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 10:05:04.972838 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4613 10:05:04.975845 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 10:05:04.982005 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 10:05:04.985541 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 10:05:04.988793 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 10:05:04.995449 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 10:05:04.998992 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 10:05:05.002818 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 10:05:05.008692 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 10:05:05.012277 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 10:05:05.015823 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 10:05:05.018914 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 10:05:05.025565 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 10:05:05.029075 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 10:05:05.032331 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 10:05:05.038742 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4628 10:05:05.042161 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4629 10:05:05.045553 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 10:05:05.048646 Total UI for P1: 0, mck2ui 16
4631 10:05:05.052198 best dqsien dly found for B0: ( 0, 13, 10)
4632 10:05:05.055926 Total UI for P1: 0, mck2ui 16
4633 10:05:05.058698 best dqsien dly found for B1: ( 0, 13, 10)
4634 10:05:05.062284 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4635 10:05:05.065890 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4636 10:05:05.065975
4637 10:05:05.071962 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4638 10:05:05.075448 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4639 10:05:05.078950 [Gating] SW calibration Done
4640 10:05:05.079034 ==
4641 10:05:05.081848 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 10:05:05.085421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 10:05:05.085506 ==
4644 10:05:05.085573 RX Vref Scan: 0
4645 10:05:05.085636
4646 10:05:05.088932 RX Vref 0 -> 0, step: 1
4647 10:05:05.089016
4648 10:05:05.092122 RX Delay -230 -> 252, step: 16
4649 10:05:05.095516 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4650 10:05:05.098576 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4651 10:05:05.105356 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4652 10:05:05.108755 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4653 10:05:05.112046 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4654 10:05:05.115428 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4655 10:05:05.118702 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4656 10:05:05.125328 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4657 10:05:05.128841 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4658 10:05:05.131944 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4659 10:05:05.135360 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4660 10:05:05.141755 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4661 10:05:05.145715 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4662 10:05:05.148755 iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304
4663 10:05:05.152057 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4664 10:05:05.155365 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4665 10:05:05.158392 ==
4666 10:05:05.161854 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 10:05:05.165343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 10:05:05.165428 ==
4669 10:05:05.165495 DQS Delay:
4670 10:05:05.168290 DQS0 = 0, DQS1 = 0
4671 10:05:05.168373 DQM Delay:
4672 10:05:05.171715 DQM0 = 53, DQM1 = 50
4673 10:05:05.171800 DQ Delay:
4674 10:05:05.174988 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4675 10:05:05.178460 DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =49
4676 10:05:05.181916 DQ8 =33, DQ9 =41, DQ10 =41, DQ11 =41
4677 10:05:05.185558 DQ12 =65, DQ13 =65, DQ14 =49, DQ15 =65
4678 10:05:05.185641
4679 10:05:05.185708
4680 10:05:05.185769 ==
4681 10:05:05.188308 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 10:05:05.191819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 10:05:05.191903 ==
4684 10:05:05.191969
4685 10:05:05.192033
4686 10:05:05.195701 TX Vref Scan disable
4687 10:05:05.198854 == TX Byte 0 ==
4688 10:05:05.201810 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4689 10:05:05.205362 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4690 10:05:05.208633 == TX Byte 1 ==
4691 10:05:05.212130 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4692 10:05:05.214985 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4693 10:05:05.215069 ==
4694 10:05:05.218752 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 10:05:05.221986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 10:05:05.225247 ==
4697 10:05:05.225354
4698 10:05:05.225438
4699 10:05:05.225502 TX Vref Scan disable
4700 10:05:05.229297 == TX Byte 0 ==
4701 10:05:05.232599 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4702 10:05:05.239000 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4703 10:05:05.239085 == TX Byte 1 ==
4704 10:05:05.243036 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4705 10:05:05.248961 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4706 10:05:05.249045
4707 10:05:05.249111 [DATLAT]
4708 10:05:05.249172 Freq=600, CH1 RK1
4709 10:05:05.249233
4710 10:05:05.252876 DATLAT Default: 0x9
4711 10:05:05.252960 0, 0xFFFF, sum = 0
4712 10:05:05.256054 1, 0xFFFF, sum = 0
4713 10:05:05.256139 2, 0xFFFF, sum = 0
4714 10:05:05.258732 3, 0xFFFF, sum = 0
4715 10:05:05.262594 4, 0xFFFF, sum = 0
4716 10:05:05.262680 5, 0xFFFF, sum = 0
4717 10:05:05.265649 6, 0xFFFF, sum = 0
4718 10:05:05.265733 7, 0xFFFF, sum = 0
4719 10:05:05.268769 8, 0x0, sum = 1
4720 10:05:05.268910 9, 0x0, sum = 2
4721 10:05:05.268980 10, 0x0, sum = 3
4722 10:05:05.272527 11, 0x0, sum = 4
4723 10:05:05.272611 best_step = 9
4724 10:05:05.272678
4725 10:05:05.272739 ==
4726 10:05:05.275620 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 10:05:05.282026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 10:05:05.282111 ==
4729 10:05:05.282178 RX Vref Scan: 0
4730 10:05:05.282240
4731 10:05:05.285715 RX Vref 0 -> 0, step: 1
4732 10:05:05.285797
4733 10:05:05.288624 RX Delay -163 -> 252, step: 8
4734 10:05:05.292073 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4735 10:05:05.298749 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4736 10:05:05.302211 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4737 10:05:05.305418 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4738 10:05:05.308869 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4739 10:05:05.312160 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4740 10:05:05.318541 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4741 10:05:05.322061 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4742 10:05:05.325276 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4743 10:05:05.328595 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4744 10:05:05.332224 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4745 10:05:05.338726 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4746 10:05:05.342135 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4747 10:05:05.345327 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4748 10:05:05.348772 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4749 10:05:05.355362 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4750 10:05:05.355447 ==
4751 10:05:05.358741 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 10:05:05.361903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 10:05:05.361987 ==
4754 10:05:05.362053 DQS Delay:
4755 10:05:05.365766 DQS0 = 0, DQS1 = 0
4756 10:05:05.365849 DQM Delay:
4757 10:05:05.368790 DQM0 = 48, DQM1 = 45
4758 10:05:05.368932 DQ Delay:
4759 10:05:05.372271 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4760 10:05:05.375334 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4761 10:05:05.378616 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4762 10:05:05.382292 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4763 10:05:05.382376
4764 10:05:05.382441
4765 10:05:05.388725 [DQSOSCAuto] RK1, (LSB)MR18= 0x681f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4766 10:05:05.392151 CH1 RK1: MR19=808, MR18=681F
4767 10:05:05.398718 CH1_RK1: MR19=0x808, MR18=0x681F, DQSOSC=390, MR23=63, INC=172, DEC=114
4768 10:05:05.402009 [RxdqsGatingPostProcess] freq 600
4769 10:05:05.408826 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4770 10:05:05.408957 Pre-setting of DQS Precalculation
4771 10:05:05.415473 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4772 10:05:05.421913 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4773 10:05:05.428724 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4774 10:05:05.428884
4775 10:05:05.428955
4776 10:05:05.431714 [Calibration Summary] 1200 Mbps
4777 10:05:05.435164 CH 0, Rank 0
4778 10:05:05.435252 SW Impedance : PASS
4779 10:05:05.438867 DUTY Scan : NO K
4780 10:05:05.438955 ZQ Calibration : PASS
4781 10:05:05.442001 Jitter Meter : NO K
4782 10:05:05.445265 CBT Training : PASS
4783 10:05:05.445354 Write leveling : PASS
4784 10:05:05.449193 RX DQS gating : PASS
4785 10:05:05.452206 RX DQ/DQS(RDDQC) : PASS
4786 10:05:05.452304 TX DQ/DQS : PASS
4787 10:05:05.454874 RX DATLAT : PASS
4788 10:05:05.458334 RX DQ/DQS(Engine): PASS
4789 10:05:05.458425 TX OE : NO K
4790 10:05:05.462081 All Pass.
4791 10:05:05.462165
4792 10:05:05.462231 CH 0, Rank 1
4793 10:05:05.465434 SW Impedance : PASS
4794 10:05:05.465524 DUTY Scan : NO K
4795 10:05:05.468351 ZQ Calibration : PASS
4796 10:05:05.471658 Jitter Meter : NO K
4797 10:05:05.471757 CBT Training : PASS
4798 10:05:05.475016 Write leveling : PASS
4799 10:05:05.478209 RX DQS gating : PASS
4800 10:05:05.478304 RX DQ/DQS(RDDQC) : PASS
4801 10:05:05.481633 TX DQ/DQS : PASS
4802 10:05:05.485067 RX DATLAT : PASS
4803 10:05:05.485156 RX DQ/DQS(Engine): PASS
4804 10:05:05.488339 TX OE : NO K
4805 10:05:05.488428 All Pass.
4806 10:05:05.488495
4807 10:05:05.491655 CH 1, Rank 0
4808 10:05:05.491774 SW Impedance : PASS
4809 10:05:05.494549 DUTY Scan : NO K
4810 10:05:05.498118 ZQ Calibration : PASS
4811 10:05:05.498215 Jitter Meter : NO K
4812 10:05:05.501676 CBT Training : PASS
4813 10:05:05.501771 Write leveling : PASS
4814 10:05:05.504604 RX DQS gating : PASS
4815 10:05:05.508078 RX DQ/DQS(RDDQC) : PASS
4816 10:05:05.508246 TX DQ/DQS : PASS
4817 10:05:05.511544 RX DATLAT : PASS
4818 10:05:05.514638 RX DQ/DQS(Engine): PASS
4819 10:05:05.514729 TX OE : NO K
4820 10:05:05.518225 All Pass.
4821 10:05:05.518314
4822 10:05:05.518382 CH 1, Rank 1
4823 10:05:05.520965 SW Impedance : PASS
4824 10:05:05.521055 DUTY Scan : NO K
4825 10:05:05.524367 ZQ Calibration : PASS
4826 10:05:05.527684 Jitter Meter : NO K
4827 10:05:05.527776 CBT Training : PASS
4828 10:05:05.531246 Write leveling : PASS
4829 10:05:05.534744 RX DQS gating : PASS
4830 10:05:05.534864 RX DQ/DQS(RDDQC) : PASS
4831 10:05:05.538243 TX DQ/DQS : PASS
4832 10:05:05.540869 RX DATLAT : PASS
4833 10:05:05.540965 RX DQ/DQS(Engine): PASS
4834 10:05:05.544553 TX OE : NO K
4835 10:05:05.544651 All Pass.
4836 10:05:05.544719
4837 10:05:05.547916 DramC Write-DBI off
4838 10:05:05.551277 PER_BANK_REFRESH: Hybrid Mode
4839 10:05:05.551386 TX_TRACKING: ON
4840 10:05:05.560698 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4841 10:05:05.564589 [FAST_K] Save calibration result to emmc
4842 10:05:05.567777 dramc_set_vcore_voltage set vcore to 662500
4843 10:05:05.570838 Read voltage for 933, 3
4844 10:05:05.570937 Vio18 = 0
4845 10:05:05.571006 Vcore = 662500
4846 10:05:05.574286 Vdram = 0
4847 10:05:05.574394 Vddq = 0
4848 10:05:05.574464 Vmddr = 0
4849 10:05:05.580792 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4850 10:05:05.583901 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4851 10:05:05.587428 MEM_TYPE=3, freq_sel=17
4852 10:05:05.591048 sv_algorithm_assistance_LP4_1600
4853 10:05:05.593920 ============ PULL DRAM RESETB DOWN ============
4854 10:05:05.597279 ========== PULL DRAM RESETB DOWN end =========
4855 10:05:05.604199 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4856 10:05:05.607246 ===================================
4857 10:05:05.607427 LPDDR4 DRAM CONFIGURATION
4858 10:05:05.610733 ===================================
4859 10:05:05.613979 EX_ROW_EN[0] = 0x0
4860 10:05:05.617036 EX_ROW_EN[1] = 0x0
4861 10:05:05.617123 LP4Y_EN = 0x0
4862 10:05:05.620756 WORK_FSP = 0x0
4863 10:05:05.620881 WL = 0x3
4864 10:05:05.624059 RL = 0x3
4865 10:05:05.624144 BL = 0x2
4866 10:05:05.627037 RPST = 0x0
4867 10:05:05.627121 RD_PRE = 0x0
4868 10:05:05.630231 WR_PRE = 0x1
4869 10:05:05.630337 WR_PST = 0x0
4870 10:05:05.633943 DBI_WR = 0x0
4871 10:05:05.634052 DBI_RD = 0x0
4872 10:05:05.637610 OTF = 0x1
4873 10:05:05.640239 ===================================
4874 10:05:05.643758 ===================================
4875 10:05:05.643868 ANA top config
4876 10:05:05.647509 ===================================
4877 10:05:05.650731 DLL_ASYNC_EN = 0
4878 10:05:05.654115 ALL_SLAVE_EN = 1
4879 10:05:05.657361 NEW_RANK_MODE = 1
4880 10:05:05.657454 DLL_IDLE_MODE = 1
4881 10:05:05.660471 LP45_APHY_COMB_EN = 1
4882 10:05:05.663725 TX_ODT_DIS = 1
4883 10:05:05.667184 NEW_8X_MODE = 1
4884 10:05:05.670623 ===================================
4885 10:05:05.673607 ===================================
4886 10:05:05.677212 data_rate = 1866
4887 10:05:05.677355 CKR = 1
4888 10:05:05.680197 DQ_P2S_RATIO = 8
4889 10:05:05.684107 ===================================
4890 10:05:05.687036 CA_P2S_RATIO = 8
4891 10:05:05.690435 DQ_CA_OPEN = 0
4892 10:05:05.693594 DQ_SEMI_OPEN = 0
4893 10:05:05.693736 CA_SEMI_OPEN = 0
4894 10:05:05.697377 CA_FULL_RATE = 0
4895 10:05:05.700607 DQ_CKDIV4_EN = 1
4896 10:05:05.703620 CA_CKDIV4_EN = 1
4897 10:05:05.707024 CA_PREDIV_EN = 0
4898 10:05:05.710362 PH8_DLY = 0
4899 10:05:05.710506 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4900 10:05:05.714017 DQ_AAMCK_DIV = 4
4901 10:05:05.717248 CA_AAMCK_DIV = 4
4902 10:05:05.720471 CA_ADMCK_DIV = 4
4903 10:05:05.723864 DQ_TRACK_CA_EN = 0
4904 10:05:05.726827 CA_PICK = 933
4905 10:05:05.730474 CA_MCKIO = 933
4906 10:05:05.730621 MCKIO_SEMI = 0
4907 10:05:05.733478 PLL_FREQ = 3732
4908 10:05:05.737267 DQ_UI_PI_RATIO = 32
4909 10:05:05.740055 CA_UI_PI_RATIO = 0
4910 10:05:05.743955 ===================================
4911 10:05:05.747100 ===================================
4912 10:05:05.750467 memory_type:LPDDR4
4913 10:05:05.750609 GP_NUM : 10
4914 10:05:05.753818 SRAM_EN : 1
4915 10:05:05.753950 MD32_EN : 0
4916 10:05:05.757269 ===================================
4917 10:05:05.760636 [ANA_INIT] >>>>>>>>>>>>>>
4918 10:05:05.763528 <<<<<< [CONFIGURE PHASE]: ANA_TX
4919 10:05:05.766892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4920 10:05:05.770517 ===================================
4921 10:05:05.773780 data_rate = 1866,PCW = 0X8f00
4922 10:05:05.777127 ===================================
4923 10:05:05.780146 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4924 10:05:05.787340 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4925 10:05:05.790171 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4926 10:05:05.796663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4927 10:05:05.800153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4928 10:05:05.803736 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4929 10:05:05.803891 [ANA_INIT] flow start
4930 10:05:05.806924 [ANA_INIT] PLL >>>>>>>>
4931 10:05:05.810445 [ANA_INIT] PLL <<<<<<<<
4932 10:05:05.810618 [ANA_INIT] MIDPI >>>>>>>>
4933 10:05:05.813383 [ANA_INIT] MIDPI <<<<<<<<
4934 10:05:05.817277 [ANA_INIT] DLL >>>>>>>>
4935 10:05:05.817436 [ANA_INIT] flow end
4936 10:05:05.823311 ============ LP4 DIFF to SE enter ============
4937 10:05:05.826650 ============ LP4 DIFF to SE exit ============
4938 10:05:05.830190 [ANA_INIT] <<<<<<<<<<<<<
4939 10:05:05.830341 [Flow] Enable top DCM control >>>>>
4940 10:05:05.833406 [Flow] Enable top DCM control <<<<<
4941 10:05:05.837094 Enable DLL master slave shuffle
4942 10:05:05.843404 ==============================================================
4943 10:05:05.846920 Gating Mode config
4944 10:05:05.850490 ==============================================================
4945 10:05:05.853173 Config description:
4946 10:05:05.863382 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4947 10:05:05.870140 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4948 10:05:05.873197 SELPH_MODE 0: By rank 1: By Phase
4949 10:05:05.880327 ==============================================================
4950 10:05:05.883603 GAT_TRACK_EN = 1
4951 10:05:05.886632 RX_GATING_MODE = 2
4952 10:05:05.890092 RX_GATING_TRACK_MODE = 2
4953 10:05:05.890246 SELPH_MODE = 1
4954 10:05:05.893302 PICG_EARLY_EN = 1
4955 10:05:05.896594 VALID_LAT_VALUE = 1
4956 10:05:05.903306 ==============================================================
4957 10:05:05.906761 Enter into Gating configuration >>>>
4958 10:05:05.909980 Exit from Gating configuration <<<<
4959 10:05:05.913058 Enter into DVFS_PRE_config >>>>>
4960 10:05:05.922874 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4961 10:05:05.926271 Exit from DVFS_PRE_config <<<<<
4962 10:05:05.929583 Enter into PICG configuration >>>>
4963 10:05:05.933255 Exit from PICG configuration <<<<
4964 10:05:05.936321 [RX_INPUT] configuration >>>>>
4965 10:05:05.939507 [RX_INPUT] configuration <<<<<
4966 10:05:05.942869 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4967 10:05:05.949756 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4968 10:05:05.956080 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4969 10:05:05.962951 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4970 10:05:05.969613 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4971 10:05:05.972645 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4972 10:05:05.979560 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4973 10:05:05.982728 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4974 10:05:05.985425 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4975 10:05:05.988831 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4976 10:05:05.995608 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4977 10:05:05.999023 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4978 10:05:06.002440 ===================================
4979 10:05:06.006133 LPDDR4 DRAM CONFIGURATION
4980 10:05:06.009132 ===================================
4981 10:05:06.009308 EX_ROW_EN[0] = 0x0
4982 10:05:06.012679 EX_ROW_EN[1] = 0x0
4983 10:05:06.012854 LP4Y_EN = 0x0
4984 10:05:06.015796 WORK_FSP = 0x0
4985 10:05:06.015946 WL = 0x3
4986 10:05:06.019420 RL = 0x3
4987 10:05:06.019579 BL = 0x2
4988 10:05:06.022360 RPST = 0x0
4989 10:05:06.025554 RD_PRE = 0x0
4990 10:05:06.025696 WR_PRE = 0x1
4991 10:05:06.028775 WR_PST = 0x0
4992 10:05:06.028910 DBI_WR = 0x0
4993 10:05:06.032394 DBI_RD = 0x0
4994 10:05:06.032513 OTF = 0x1
4995 10:05:06.035601 ===================================
4996 10:05:06.039207 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4997 10:05:06.042406 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4998 10:05:06.048784 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4999 10:05:06.052413 ===================================
5000 10:05:06.055246 LPDDR4 DRAM CONFIGURATION
5001 10:05:06.058731 ===================================
5002 10:05:06.058846 EX_ROW_EN[0] = 0x10
5003 10:05:06.062350 EX_ROW_EN[1] = 0x0
5004 10:05:06.062471 LP4Y_EN = 0x0
5005 10:05:06.065569 WORK_FSP = 0x0
5006 10:05:06.065704 WL = 0x3
5007 10:05:06.069005 RL = 0x3
5008 10:05:06.069134 BL = 0x2
5009 10:05:06.072009 RPST = 0x0
5010 10:05:06.072119 RD_PRE = 0x0
5011 10:05:06.075436 WR_PRE = 0x1
5012 10:05:06.075577 WR_PST = 0x0
5013 10:05:06.078846 DBI_WR = 0x0
5014 10:05:06.082180 DBI_RD = 0x0
5015 10:05:06.082336 OTF = 0x1
5016 10:05:06.085305 ===================================
5017 10:05:06.091808 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5018 10:05:06.095572 nWR fixed to 30
5019 10:05:06.099068 [ModeRegInit_LP4] CH0 RK0
5020 10:05:06.099235 [ModeRegInit_LP4] CH0 RK1
5021 10:05:06.102608 [ModeRegInit_LP4] CH1 RK0
5022 10:05:06.105485 [ModeRegInit_LP4] CH1 RK1
5023 10:05:06.105665 match AC timing 9
5024 10:05:06.112312 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5025 10:05:06.115266 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5026 10:05:06.118940 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5027 10:05:06.125235 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5028 10:05:06.128978 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5029 10:05:06.129154 ==
5030 10:05:06.131888 Dram Type= 6, Freq= 0, CH_0, rank 0
5031 10:05:06.135642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5032 10:05:06.135815 ==
5033 10:05:06.142662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5034 10:05:06.148841 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5035 10:05:06.152262 [CA 0] Center 37 (6~68) winsize 63
5036 10:05:06.155524 [CA 1] Center 37 (7~68) winsize 62
5037 10:05:06.158473 [CA 2] Center 34 (4~65) winsize 62
5038 10:05:06.162195 [CA 3] Center 33 (3~64) winsize 62
5039 10:05:06.165508 [CA 4] Center 33 (3~64) winsize 62
5040 10:05:06.168325 [CA 5] Center 32 (2~62) winsize 61
5041 10:05:06.168475
5042 10:05:06.171582 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5043 10:05:06.171737
5044 10:05:06.175302 [CATrainingPosCal] consider 1 rank data
5045 10:05:06.178207 u2DelayCellTimex100 = 270/100 ps
5046 10:05:06.181943 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5047 10:05:06.185158 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5048 10:05:06.188482 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5049 10:05:06.191953 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5050 10:05:06.195119 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5051 10:05:06.198860 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5052 10:05:06.201686
5053 10:05:06.204932 CA PerBit enable=1, Macro0, CA PI delay=32
5054 10:05:06.205091
5055 10:05:06.208160 [CBTSetCACLKResult] CA Dly = 32
5056 10:05:06.208301 CS Dly: 5 (0~36)
5057 10:05:06.208403 ==
5058 10:05:06.211622 Dram Type= 6, Freq= 0, CH_0, rank 1
5059 10:05:06.214896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5060 10:05:06.215047 ==
5061 10:05:06.221740 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5062 10:05:06.228622 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5063 10:05:06.231665 [CA 0] Center 37 (6~68) winsize 63
5064 10:05:06.235218 [CA 1] Center 37 (7~68) winsize 62
5065 10:05:06.238538 [CA 2] Center 34 (4~65) winsize 62
5066 10:05:06.241536 [CA 3] Center 34 (3~65) winsize 63
5067 10:05:06.244736 [CA 4] Center 32 (2~63) winsize 62
5068 10:05:06.248280 [CA 5] Center 32 (2~62) winsize 61
5069 10:05:06.248431
5070 10:05:06.252126 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5071 10:05:06.252277
5072 10:05:06.254748 [CATrainingPosCal] consider 2 rank data
5073 10:05:06.258707 u2DelayCellTimex100 = 270/100 ps
5074 10:05:06.261524 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5075 10:05:06.264741 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5076 10:05:06.268334 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5077 10:05:06.271983 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5078 10:05:06.275032 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5079 10:05:06.278474 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5080 10:05:06.281698
5081 10:05:06.284962 CA PerBit enable=1, Macro0, CA PI delay=32
5082 10:05:06.285131
5083 10:05:06.288408 [CBTSetCACLKResult] CA Dly = 32
5084 10:05:06.288567 CS Dly: 5 (0~37)
5085 10:05:06.288670
5086 10:05:06.291439 ----->DramcWriteLeveling(PI) begin...
5087 10:05:06.291574 ==
5088 10:05:06.295080 Dram Type= 6, Freq= 0, CH_0, rank 0
5089 10:05:06.298376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 10:05:06.301345 ==
5091 10:05:06.301471 Write leveling (Byte 0): 34 => 34
5092 10:05:06.304770 Write leveling (Byte 1): 29 => 29
5093 10:05:06.308245 DramcWriteLeveling(PI) end<-----
5094 10:05:06.308369
5095 10:05:06.308441 ==
5096 10:05:06.311955 Dram Type= 6, Freq= 0, CH_0, rank 0
5097 10:05:06.318402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 10:05:06.318596 ==
5099 10:05:06.318760 [Gating] SW mode calibration
5100 10:05:06.328089 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5101 10:05:06.331459 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5102 10:05:06.337912 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5103 10:05:06.341534 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 10:05:06.344367 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 10:05:06.351008 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 10:05:06.354449 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 10:05:06.357690 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 10:05:06.361016 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5109 10:05:06.367888 0 14 28 | B1->B0 | 3333 2727 | 0 0 | (0 0) (0 0)
5110 10:05:06.371347 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5111 10:05:06.374206 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 10:05:06.381040 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 10:05:06.384969 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 10:05:06.387780 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 10:05:06.394239 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 10:05:06.397747 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 10:05:06.401517 0 15 28 | B1->B0 | 2727 3a3a | 0 0 | (0 0) (0 0)
5118 10:05:06.407834 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5119 10:05:06.410605 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 10:05:06.414058 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 10:05:06.420933 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 10:05:06.424178 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 10:05:06.427148 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 10:05:06.433909 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 10:05:06.436950 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5126 10:05:06.440577 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5127 10:05:06.447046 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 10:05:06.450557 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 10:05:06.453705 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 10:05:06.460702 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 10:05:06.463722 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 10:05:06.466925 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 10:05:06.473940 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 10:05:06.476826 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 10:05:06.480652 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 10:05:06.487305 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 10:05:06.489929 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 10:05:06.493510 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 10:05:06.500023 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 10:05:06.503647 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5141 10:05:06.506647 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5142 10:05:06.510071 Total UI for P1: 0, mck2ui 16
5143 10:05:06.513973 best dqsien dly found for B0: ( 1, 2, 24)
5144 10:05:06.520231 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 10:05:06.520384 Total UI for P1: 0, mck2ui 16
5146 10:05:06.523482 best dqsien dly found for B1: ( 1, 2, 30)
5147 10:05:06.530477 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5148 10:05:06.533495 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5149 10:05:06.533628
5150 10:05:06.537470 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5151 10:05:06.540539 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5152 10:05:06.543844 [Gating] SW calibration Done
5153 10:05:06.543968 ==
5154 10:05:06.547314 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 10:05:06.550551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 10:05:06.550708 ==
5157 10:05:06.550821 RX Vref Scan: 0
5158 10:05:06.553651
5159 10:05:06.553791 RX Vref 0 -> 0, step: 1
5160 10:05:06.553899
5161 10:05:06.557245 RX Delay -80 -> 252, step: 8
5162 10:05:06.560602 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5163 10:05:06.566832 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5164 10:05:06.570007 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5165 10:05:06.573866 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5166 10:05:06.576655 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5167 10:05:06.580492 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5168 10:05:06.584069 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5169 10:05:06.586909 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5170 10:05:06.593573 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5171 10:05:06.597170 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5172 10:05:06.600545 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5173 10:05:06.603327 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5174 10:05:06.607091 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5175 10:05:06.610471 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5176 10:05:06.616889 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5177 10:05:06.620340 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5178 10:05:06.620577 ==
5179 10:05:06.623260 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 10:05:06.627049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 10:05:06.627224 ==
5182 10:05:06.630238 DQS Delay:
5183 10:05:06.630379 DQS0 = 0, DQS1 = 0
5184 10:05:06.630483 DQM Delay:
5185 10:05:06.633549 DQM0 = 105, DQM1 = 94
5186 10:05:06.633678 DQ Delay:
5187 10:05:06.636699 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5188 10:05:06.640288 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5189 10:05:06.643624 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5190 10:05:06.646621 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5191 10:05:06.646762
5192 10:05:06.646889
5193 10:05:06.650317 ==
5194 10:05:06.650459 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 10:05:06.656924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 10:05:06.657120 ==
5197 10:05:06.657256
5198 10:05:06.657348
5199 10:05:06.660267 TX Vref Scan disable
5200 10:05:06.660401 == TX Byte 0 ==
5201 10:05:06.663581 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5202 10:05:06.670007 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5203 10:05:06.670195 == TX Byte 1 ==
5204 10:05:06.673509 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5205 10:05:06.680555 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5206 10:05:06.680761 ==
5207 10:05:06.683168 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 10:05:06.686917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 10:05:06.687078 ==
5210 10:05:06.687205
5211 10:05:06.687298
5212 10:05:06.689850 TX Vref Scan disable
5213 10:05:06.693546 == TX Byte 0 ==
5214 10:05:06.696839 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5215 10:05:06.699744 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5216 10:05:06.703127 == TX Byte 1 ==
5217 10:05:06.706905 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5218 10:05:06.710066 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5219 10:05:06.710256
5220 10:05:06.710369 [DATLAT]
5221 10:05:06.713323 Freq=933, CH0 RK0
5222 10:05:06.713472
5223 10:05:06.716589 DATLAT Default: 0xd
5224 10:05:06.716759 0, 0xFFFF, sum = 0
5225 10:05:06.719891 1, 0xFFFF, sum = 0
5226 10:05:06.720037 2, 0xFFFF, sum = 0
5227 10:05:06.722991 3, 0xFFFF, sum = 0
5228 10:05:06.723134 4, 0xFFFF, sum = 0
5229 10:05:06.726421 5, 0xFFFF, sum = 0
5230 10:05:06.726585 6, 0xFFFF, sum = 0
5231 10:05:06.730069 7, 0xFFFF, sum = 0
5232 10:05:06.730229 8, 0xFFFF, sum = 0
5233 10:05:06.732958 9, 0xFFFF, sum = 0
5234 10:05:06.733113 10, 0x0, sum = 1
5235 10:05:06.736646 11, 0x0, sum = 2
5236 10:05:06.736786 12, 0x0, sum = 3
5237 10:05:06.739878 13, 0x0, sum = 4
5238 10:05:06.739992 best_step = 11
5239 10:05:06.740065
5240 10:05:06.740127 ==
5241 10:05:06.743076 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 10:05:06.746515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 10:05:06.746696 ==
5244 10:05:06.750025 RX Vref Scan: 1
5245 10:05:06.750216
5246 10:05:06.753016 RX Vref 0 -> 0, step: 1
5247 10:05:06.753158
5248 10:05:06.753235 RX Delay -53 -> 252, step: 4
5249 10:05:06.753300
5250 10:05:06.756450 Set Vref, RX VrefLevel [Byte0]: 55
5251 10:05:06.759565 [Byte1]: 50
5252 10:05:06.764680
5253 10:05:06.764846 Final RX Vref Byte 0 = 55 to rank0
5254 10:05:06.768384 Final RX Vref Byte 1 = 50 to rank0
5255 10:05:06.771206 Final RX Vref Byte 0 = 55 to rank1
5256 10:05:06.774895 Final RX Vref Byte 1 = 50 to rank1==
5257 10:05:06.778033 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 10:05:06.784789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 10:05:06.784944 ==
5260 10:05:06.785013 DQS Delay:
5261 10:05:06.785077 DQS0 = 0, DQS1 = 0
5262 10:05:06.787951 DQM Delay:
5263 10:05:06.788044 DQM0 = 104, DQM1 = 95
5264 10:05:06.791523 DQ Delay:
5265 10:05:06.794792 DQ0 =106, DQ1 =106, DQ2 =102, DQ3 =102
5266 10:05:06.797950 DQ4 =104, DQ5 =94, DQ6 =112, DQ7 =110
5267 10:05:06.801608 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =88
5268 10:05:06.804533 DQ12 =102, DQ13 =98, DQ14 =106, DQ15 =102
5269 10:05:06.804685
5270 10:05:06.804786
5271 10:05:06.811035 [DQSOSCAuto] RK0, (LSB)MR18= 0x3229, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5272 10:05:06.814491 CH0 RK0: MR19=505, MR18=3229
5273 10:05:06.821329 CH0_RK0: MR19=0x505, MR18=0x3229, DQSOSC=406, MR23=63, INC=65, DEC=43
5274 10:05:06.821511
5275 10:05:06.824755 ----->DramcWriteLeveling(PI) begin...
5276 10:05:06.824921 ==
5277 10:05:06.827729 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 10:05:06.831391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 10:05:06.831533 ==
5280 10:05:06.834310 Write leveling (Byte 0): 35 => 35
5281 10:05:06.838046 Write leveling (Byte 1): 27 => 27
5282 10:05:06.841318 DramcWriteLeveling(PI) end<-----
5283 10:05:06.841473
5284 10:05:06.841573 ==
5285 10:05:06.844595 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 10:05:06.847662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 10:05:06.851417 ==
5288 10:05:06.851578 [Gating] SW mode calibration
5289 10:05:06.860939 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5290 10:05:06.864177 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5291 10:05:06.867580 0 14 0 | B1->B0 | 3333 3030 | 0 1 | (0 0) (1 1)
5292 10:05:06.874353 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 10:05:06.877362 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 10:05:06.880910 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 10:05:06.887576 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 10:05:06.890714 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 10:05:06.894457 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 10:05:06.900730 0 14 28 | B1->B0 | 2727 2929 | 0 0 | (0 1) (0 0)
5299 10:05:06.904287 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5300 10:05:06.907901 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 10:05:06.914008 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 10:05:06.917376 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 10:05:06.921227 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 10:05:06.927687 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 10:05:06.930688 0 15 24 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
5306 10:05:06.934352 0 15 28 | B1->B0 | 4343 3635 | 0 1 | (0 0) (1 1)
5307 10:05:06.940938 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 10:05:06.944427 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 10:05:06.947496 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 10:05:06.951012 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 10:05:06.957807 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 10:05:06.960900 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 10:05:06.963900 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 10:05:06.970553 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5315 10:05:06.973981 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 10:05:06.980254 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 10:05:06.983767 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 10:05:06.987292 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 10:05:06.990237 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 10:05:06.997113 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 10:05:07.000421 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 10:05:07.004020 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 10:05:07.010271 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 10:05:07.013832 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 10:05:07.016977 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 10:05:07.024032 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 10:05:07.027287 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 10:05:07.030226 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 10:05:07.036979 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 10:05:07.040007 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5331 10:05:07.043646 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5332 10:05:07.046696 Total UI for P1: 0, mck2ui 16
5333 10:05:07.050167 best dqsien dly found for B1: ( 1, 2, 28)
5334 10:05:07.056674 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 10:05:07.056894 Total UI for P1: 0, mck2ui 16
5336 10:05:07.063536 best dqsien dly found for B0: ( 1, 2, 30)
5337 10:05:07.067261 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5338 10:05:07.070199 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5339 10:05:07.070319
5340 10:05:07.073762 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5341 10:05:07.076544 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5342 10:05:07.080362 [Gating] SW calibration Done
5343 10:05:07.080494 ==
5344 10:05:07.083651 Dram Type= 6, Freq= 0, CH_0, rank 1
5345 10:05:07.086899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 10:05:07.087022 ==
5347 10:05:07.090108 RX Vref Scan: 0
5348 10:05:07.090273
5349 10:05:07.090358 RX Vref 0 -> 0, step: 1
5350 10:05:07.090452
5351 10:05:07.093848 RX Delay -80 -> 252, step: 8
5352 10:05:07.096581 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5353 10:05:07.103471 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5354 10:05:07.106924 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5355 10:05:07.109890 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5356 10:05:07.113370 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5357 10:05:07.117056 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5358 10:05:07.119673 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5359 10:05:07.126682 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5360 10:05:07.129702 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5361 10:05:07.133049 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5362 10:05:07.136750 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5363 10:05:07.139783 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5364 10:05:07.146455 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5365 10:05:07.149693 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5366 10:05:07.153308 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5367 10:05:07.156291 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5368 10:05:07.156414 ==
5369 10:05:07.159930 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 10:05:07.163210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 10:05:07.166784 ==
5372 10:05:07.166958 DQS Delay:
5373 10:05:07.167069 DQS0 = 0, DQS1 = 0
5374 10:05:07.169721 DQM Delay:
5375 10:05:07.169844 DQM0 = 104, DQM1 = 94
5376 10:05:07.173452 DQ Delay:
5377 10:05:07.176416 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5378 10:05:07.179407 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5379 10:05:07.183110 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5380 10:05:07.186048 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =103
5381 10:05:07.186204
5382 10:05:07.186319
5383 10:05:07.186423 ==
5384 10:05:07.189517 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 10:05:07.193089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 10:05:07.193259 ==
5387 10:05:07.193382
5388 10:05:07.193494
5389 10:05:07.196240 TX Vref Scan disable
5390 10:05:07.196405 == TX Byte 0 ==
5391 10:05:07.203096 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5392 10:05:07.206401 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5393 10:05:07.209645 == TX Byte 1 ==
5394 10:05:07.212731 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5395 10:05:07.215957 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5396 10:05:07.216088 ==
5397 10:05:07.219280 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 10:05:07.222510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 10:05:07.222663 ==
5400 10:05:07.226225
5401 10:05:07.226373
5402 10:05:07.226449 TX Vref Scan disable
5403 10:05:07.229858 == TX Byte 0 ==
5404 10:05:07.233293 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5405 10:05:07.239624 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5406 10:05:07.239745 == TX Byte 1 ==
5407 10:05:07.242780 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5408 10:05:07.249475 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5409 10:05:07.249608
5410 10:05:07.249683 [DATLAT]
5411 10:05:07.249746 Freq=933, CH0 RK1
5412 10:05:07.249805
5413 10:05:07.253391 DATLAT Default: 0xb
5414 10:05:07.253495 0, 0xFFFF, sum = 0
5415 10:05:07.256215 1, 0xFFFF, sum = 0
5416 10:05:07.256312 2, 0xFFFF, sum = 0
5417 10:05:07.259291 3, 0xFFFF, sum = 0
5418 10:05:07.262986 4, 0xFFFF, sum = 0
5419 10:05:07.263111 5, 0xFFFF, sum = 0
5420 10:05:07.265905 6, 0xFFFF, sum = 0
5421 10:05:07.266013 7, 0xFFFF, sum = 0
5422 10:05:07.269481 8, 0xFFFF, sum = 0
5423 10:05:07.269636 9, 0xFFFF, sum = 0
5424 10:05:07.272610 10, 0x0, sum = 1
5425 10:05:07.272721 11, 0x0, sum = 2
5426 10:05:07.275863 12, 0x0, sum = 3
5427 10:05:07.275977 13, 0x0, sum = 4
5428 10:05:07.276048 best_step = 11
5429 10:05:07.276110
5430 10:05:07.279542 ==
5431 10:05:07.282636 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 10:05:07.285683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 10:05:07.285794 ==
5434 10:05:07.285863 RX Vref Scan: 0
5435 10:05:07.285925
5436 10:05:07.289583 RX Vref 0 -> 0, step: 1
5437 10:05:07.289682
5438 10:05:07.292744 RX Delay -45 -> 252, step: 4
5439 10:05:07.295733 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5440 10:05:07.302463 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5441 10:05:07.305885 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5442 10:05:07.309267 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5443 10:05:07.312674 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5444 10:05:07.316243 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5445 10:05:07.322285 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5446 10:05:07.325525 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5447 10:05:07.328712 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5448 10:05:07.332200 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5449 10:05:07.335605 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5450 10:05:07.338972 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5451 10:05:07.345434 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5452 10:05:07.349213 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5453 10:05:07.352086 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5454 10:05:07.355836 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5455 10:05:07.355966 ==
5456 10:05:07.359027 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 10:05:07.365666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 10:05:07.365809 ==
5459 10:05:07.365884 DQS Delay:
5460 10:05:07.368627 DQS0 = 0, DQS1 = 0
5461 10:05:07.368721 DQM Delay:
5462 10:05:07.368787 DQM0 = 104, DQM1 = 94
5463 10:05:07.372167 DQ Delay:
5464 10:05:07.375180 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5465 10:05:07.378638 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =112
5466 10:05:07.382145 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =88
5467 10:05:07.385326 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5468 10:05:07.385445
5469 10:05:07.385515
5470 10:05:07.392043 [DQSOSCAuto] RK1, (LSB)MR18= 0x2902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5471 10:05:07.396054 CH0 RK1: MR19=505, MR18=2902
5472 10:05:07.401912 CH0_RK1: MR19=0x505, MR18=0x2902, DQSOSC=408, MR23=63, INC=65, DEC=43
5473 10:05:07.405429 [RxdqsGatingPostProcess] freq 933
5474 10:05:07.412193 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5475 10:05:07.415683 best DQS0 dly(2T, 0.5T) = (0, 10)
5476 10:05:07.415814 best DQS1 dly(2T, 0.5T) = (0, 10)
5477 10:05:07.418903 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5478 10:05:07.421913 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5479 10:05:07.425370 best DQS0 dly(2T, 0.5T) = (0, 10)
5480 10:05:07.428830 best DQS1 dly(2T, 0.5T) = (0, 10)
5481 10:05:07.432061 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5482 10:05:07.435373 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5483 10:05:07.438743 Pre-setting of DQS Precalculation
5484 10:05:07.445519 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5485 10:05:07.445665 ==
5486 10:05:07.448484 Dram Type= 6, Freq= 0, CH_1, rank 0
5487 10:05:07.451750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 10:05:07.451883 ==
5489 10:05:07.458861 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5490 10:05:07.461943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5491 10:05:07.465684 [CA 0] Center 36 (6~67) winsize 62
5492 10:05:07.469170 [CA 1] Center 37 (6~68) winsize 63
5493 10:05:07.472886 [CA 2] Center 34 (4~65) winsize 62
5494 10:05:07.475852 [CA 3] Center 34 (4~65) winsize 62
5495 10:05:07.479441 [CA 4] Center 34 (4~65) winsize 62
5496 10:05:07.482512 [CA 5] Center 33 (3~64) winsize 62
5497 10:05:07.482634
5498 10:05:07.485669 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5499 10:05:07.485808
5500 10:05:07.489019 [CATrainingPosCal] consider 1 rank data
5501 10:05:07.492346 u2DelayCellTimex100 = 270/100 ps
5502 10:05:07.496083 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5503 10:05:07.499019 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5504 10:05:07.506229 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5505 10:05:07.509189 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5506 10:05:07.512674 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5507 10:05:07.515614 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5508 10:05:07.515729
5509 10:05:07.519370 CA PerBit enable=1, Macro0, CA PI delay=33
5510 10:05:07.519490
5511 10:05:07.522721 [CBTSetCACLKResult] CA Dly = 33
5512 10:05:07.522938 CS Dly: 6 (0~37)
5513 10:05:07.526034 ==
5514 10:05:07.526162 Dram Type= 6, Freq= 0, CH_1, rank 1
5515 10:05:07.532207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 10:05:07.532374 ==
5517 10:05:07.535880 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5518 10:05:07.542380 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5519 10:05:07.546018 [CA 0] Center 36 (6~67) winsize 62
5520 10:05:07.549208 [CA 1] Center 37 (6~68) winsize 63
5521 10:05:07.552165 [CA 2] Center 35 (5~65) winsize 61
5522 10:05:07.556123 [CA 3] Center 34 (4~65) winsize 62
5523 10:05:07.559221 [CA 4] Center 34 (4~65) winsize 62
5524 10:05:07.562601 [CA 5] Center 34 (4~64) winsize 61
5525 10:05:07.562745
5526 10:05:07.565662 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5527 10:05:07.565785
5528 10:05:07.568749 [CATrainingPosCal] consider 2 rank data
5529 10:05:07.572385 u2DelayCellTimex100 = 270/100 ps
5530 10:05:07.575535 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5531 10:05:07.582517 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5532 10:05:07.585680 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5533 10:05:07.589149 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5534 10:05:07.592093 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5535 10:05:07.595303 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5536 10:05:07.595426
5537 10:05:07.598915 CA PerBit enable=1, Macro0, CA PI delay=34
5538 10:05:07.599035
5539 10:05:07.602411 [CBTSetCACLKResult] CA Dly = 34
5540 10:05:07.602530 CS Dly: 7 (0~39)
5541 10:05:07.605218
5542 10:05:07.608733 ----->DramcWriteLeveling(PI) begin...
5543 10:05:07.608899 ==
5544 10:05:07.612357 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 10:05:07.615441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 10:05:07.615581 ==
5547 10:05:07.618448 Write leveling (Byte 0): 25 => 25
5548 10:05:07.622213 Write leveling (Byte 1): 30 => 30
5549 10:05:07.625911 DramcWriteLeveling(PI) end<-----
5550 10:05:07.626053
5551 10:05:07.626128 ==
5552 10:05:07.628539 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 10:05:07.632095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 10:05:07.632229 ==
5555 10:05:07.635706 [Gating] SW mode calibration
5556 10:05:07.642310 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5557 10:05:07.648921 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5558 10:05:07.652479 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 10:05:07.655219 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 10:05:07.662325 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 10:05:07.665293 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 10:05:07.668660 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 10:05:07.672198 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 10:05:07.678987 0 14 24 | B1->B0 | 3333 2d2d | 0 0 | (1 0) (0 0)
5565 10:05:07.682009 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
5566 10:05:07.685564 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 10:05:07.691976 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 10:05:07.695600 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 10:05:07.698733 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 10:05:07.705210 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 10:05:07.708631 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 10:05:07.712444 0 15 24 | B1->B0 | 2525 3838 | 0 0 | (0 0) (0 0)
5573 10:05:07.718608 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5574 10:05:07.722084 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 10:05:07.725185 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 10:05:07.732063 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 10:05:07.735304 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 10:05:07.738309 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 10:05:07.745376 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 10:05:07.748645 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5581 10:05:07.751643 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5582 10:05:07.758524 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 10:05:07.761624 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 10:05:07.764921 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 10:05:07.772011 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 10:05:07.775150 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 10:05:07.778095 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 10:05:07.784887 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 10:05:07.788751 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 10:05:07.791506 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 10:05:07.798190 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 10:05:07.801314 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 10:05:07.804917 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 10:05:07.811368 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 10:05:07.814878 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 10:05:07.817883 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 10:05:07.824646 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 10:05:07.824856 Total UI for P1: 0, mck2ui 16
5599 10:05:07.828236 best dqsien dly found for B0: ( 1, 2, 26)
5600 10:05:07.831280 Total UI for P1: 0, mck2ui 16
5601 10:05:07.834762 best dqsien dly found for B1: ( 1, 2, 26)
5602 10:05:07.841244 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5603 10:05:07.844290 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5604 10:05:07.844397
5605 10:05:07.847975 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5606 10:05:07.851454 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5607 10:05:07.854686 [Gating] SW calibration Done
5608 10:05:07.854807 ==
5609 10:05:07.858111 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 10:05:07.860843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 10:05:07.860975 ==
5612 10:05:07.864239 RX Vref Scan: 0
5613 10:05:07.864356
5614 10:05:07.864425 RX Vref 0 -> 0, step: 1
5615 10:05:07.864487
5616 10:05:07.868003 RX Delay -80 -> 252, step: 8
5617 10:05:07.871026 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5618 10:05:07.874352 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5619 10:05:07.880900 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5620 10:05:07.884375 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5621 10:05:07.888220 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5622 10:05:07.890873 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5623 10:05:07.894474 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5624 10:05:07.897523 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5625 10:05:07.904066 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5626 10:05:07.907822 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5627 10:05:07.910839 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5628 10:05:07.914260 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5629 10:05:07.917385 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5630 10:05:07.920846 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5631 10:05:07.927949 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5632 10:05:07.930755 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5633 10:05:07.930911 ==
5634 10:05:07.934463 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 10:05:07.937435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 10:05:07.937600 ==
5637 10:05:07.941035 DQS Delay:
5638 10:05:07.941192 DQS0 = 0, DQS1 = 0
5639 10:05:07.941330 DQM Delay:
5640 10:05:07.943880 DQM0 = 103, DQM1 = 98
5641 10:05:07.944024 DQ Delay:
5642 10:05:07.947405 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5643 10:05:07.950843 DQ4 =99, DQ5 =119, DQ6 =111, DQ7 =103
5644 10:05:07.954324 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5645 10:05:07.957355 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5646 10:05:07.960865
5647 10:05:07.961039
5648 10:05:07.961148 ==
5649 10:05:07.964112 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 10:05:07.967545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 10:05:07.967709 ==
5652 10:05:07.967831
5653 10:05:07.967928
5654 10:05:07.970417 TX Vref Scan disable
5655 10:05:07.970550 == TX Byte 0 ==
5656 10:05:07.977579 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5657 10:05:07.980369 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5658 10:05:07.980524 == TX Byte 1 ==
5659 10:05:07.987234 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5660 10:05:07.990680 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5661 10:05:07.990850 ==
5662 10:05:07.993706 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 10:05:07.997307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 10:05:07.997463 ==
5665 10:05:07.997599
5666 10:05:07.997692
5667 10:05:08.000943 TX Vref Scan disable
5668 10:05:08.003825 == TX Byte 0 ==
5669 10:05:08.007398 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5670 10:05:08.010372 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5671 10:05:08.014030 == TX Byte 1 ==
5672 10:05:08.017168 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5673 10:05:08.021012 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5674 10:05:08.021151
5675 10:05:08.023780 [DATLAT]
5676 10:05:08.023874 Freq=933, CH1 RK0
5677 10:05:08.023944
5678 10:05:08.027074 DATLAT Default: 0xd
5679 10:05:08.027172 0, 0xFFFF, sum = 0
5680 10:05:08.030714 1, 0xFFFF, sum = 0
5681 10:05:08.030827 2, 0xFFFF, sum = 0
5682 10:05:08.033984 3, 0xFFFF, sum = 0
5683 10:05:08.034086 4, 0xFFFF, sum = 0
5684 10:05:08.037672 5, 0xFFFF, sum = 0
5685 10:05:08.037775 6, 0xFFFF, sum = 0
5686 10:05:08.040539 7, 0xFFFF, sum = 0
5687 10:05:08.040635 8, 0xFFFF, sum = 0
5688 10:05:08.043977 9, 0xFFFF, sum = 0
5689 10:05:08.044080 10, 0x0, sum = 1
5690 10:05:08.047476 11, 0x0, sum = 2
5691 10:05:08.047584 12, 0x0, sum = 3
5692 10:05:08.050537 13, 0x0, sum = 4
5693 10:05:08.050634 best_step = 11
5694 10:05:08.050702
5695 10:05:08.050764 ==
5696 10:05:08.054235 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 10:05:08.060834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 10:05:08.061007 ==
5699 10:05:08.061078 RX Vref Scan: 1
5700 10:05:08.061171
5701 10:05:08.063701 RX Vref 0 -> 0, step: 1
5702 10:05:08.063813
5703 10:05:08.067987 RX Delay -45 -> 252, step: 4
5704 10:05:08.068119
5705 10:05:08.070401 Set Vref, RX VrefLevel [Byte0]: 54
5706 10:05:08.074084 [Byte1]: 56
5707 10:05:08.074226
5708 10:05:08.077492 Final RX Vref Byte 0 = 54 to rank0
5709 10:05:08.080707 Final RX Vref Byte 1 = 56 to rank0
5710 10:05:08.084338 Final RX Vref Byte 0 = 54 to rank1
5711 10:05:08.087195 Final RX Vref Byte 1 = 56 to rank1==
5712 10:05:08.090480 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 10:05:08.093466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 10:05:08.093569 ==
5715 10:05:08.096924 DQS Delay:
5716 10:05:08.097024 DQS0 = 0, DQS1 = 0
5717 10:05:08.097092 DQM Delay:
5718 10:05:08.100455 DQM0 = 103, DQM1 = 99
5719 10:05:08.100564 DQ Delay:
5720 10:05:08.103464 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =98
5721 10:05:08.106655 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =104
5722 10:05:08.110374 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =92
5723 10:05:08.113682 DQ12 =104, DQ13 =106, DQ14 =108, DQ15 =106
5724 10:05:08.113823
5725 10:05:08.116821
5726 10:05:08.123615 [DQSOSCAuto] RK0, (LSB)MR18= 0x172e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5727 10:05:08.127214 CH1 RK0: MR19=505, MR18=172E
5728 10:05:08.133473 CH1_RK0: MR19=0x505, MR18=0x172E, DQSOSC=407, MR23=63, INC=65, DEC=43
5729 10:05:08.133631
5730 10:05:08.137082 ----->DramcWriteLeveling(PI) begin...
5731 10:05:08.137195 ==
5732 10:05:08.139946 Dram Type= 6, Freq= 0, CH_1, rank 1
5733 10:05:08.143535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 10:05:08.143645 ==
5735 10:05:08.146616 Write leveling (Byte 0): 30 => 30
5736 10:05:08.149945 Write leveling (Byte 1): 30 => 30
5737 10:05:08.153523 DramcWriteLeveling(PI) end<-----
5738 10:05:08.153636
5739 10:05:08.153708 ==
5740 10:05:08.157256 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 10:05:08.160258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 10:05:08.160370 ==
5743 10:05:08.163463 [Gating] SW mode calibration
5744 10:05:08.169957 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5745 10:05:08.176526 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5746 10:05:08.179830 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 10:05:08.183655 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 10:05:08.190266 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 10:05:08.193702 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 10:05:08.197186 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 10:05:08.203212 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 10:05:08.206494 0 14 24 | B1->B0 | 2d2d 3030 | 1 1 | (1 0) (1 1)
5753 10:05:08.209958 0 14 28 | B1->B0 | 2323 2626 | 0 0 | (1 0) (0 0)
5754 10:05:08.217360 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 10:05:08.220280 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 10:05:08.223298 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 10:05:08.230042 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 10:05:08.233222 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 10:05:08.236562 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 10:05:08.243825 0 15 24 | B1->B0 | 3434 2929 | 0 0 | (0 0) (0 0)
5761 10:05:08.247786 0 15 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5762 10:05:08.249624 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 10:05:08.256334 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 10:05:08.259824 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 10:05:08.263395 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 10:05:08.269448 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 10:05:08.273198 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 10:05:08.276329 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 10:05:08.279966 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 10:05:08.286674 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 10:05:08.289289 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 10:05:08.292706 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 10:05:08.299665 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 10:05:08.302535 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 10:05:08.305969 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 10:05:08.312730 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 10:05:08.315848 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 10:05:08.319605 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 10:05:08.326182 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 10:05:08.329758 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 10:05:08.332602 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 10:05:08.339011 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 10:05:08.342595 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5784 10:05:08.346099 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5785 10:05:08.352759 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5786 10:05:08.355604 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 10:05:08.359044 Total UI for P1: 0, mck2ui 16
5788 10:05:08.362447 best dqsien dly found for B0: ( 1, 2, 26)
5789 10:05:08.365976 Total UI for P1: 0, mck2ui 16
5790 10:05:08.368994 best dqsien dly found for B1: ( 1, 2, 24)
5791 10:05:08.372844 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5792 10:05:08.376020 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5793 10:05:08.376140
5794 10:05:08.379390 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5795 10:05:08.382528 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5796 10:05:08.385916 [Gating] SW calibration Done
5797 10:05:08.386040 ==
5798 10:05:08.388991 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 10:05:08.392406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 10:05:08.395744 ==
5801 10:05:08.395862 RX Vref Scan: 0
5802 10:05:08.395933
5803 10:05:08.399110 RX Vref 0 -> 0, step: 1
5804 10:05:08.399216
5805 10:05:08.399287 RX Delay -80 -> 252, step: 8
5806 10:05:08.406250 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5807 10:05:08.409780 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5808 10:05:08.412827 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5809 10:05:08.416509 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5810 10:05:08.419705 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5811 10:05:08.423134 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5812 10:05:08.429699 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5813 10:05:08.432680 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5814 10:05:08.436356 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5815 10:05:08.439496 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5816 10:05:08.442959 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5817 10:05:08.445954 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5818 10:05:08.452958 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5819 10:05:08.455888 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5820 10:05:08.459514 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5821 10:05:08.463119 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5822 10:05:08.463300 ==
5823 10:05:08.466248 Dram Type= 6, Freq= 0, CH_1, rank 1
5824 10:05:08.473256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 10:05:08.473445 ==
5826 10:05:08.473571 DQS Delay:
5827 10:05:08.473666 DQS0 = 0, DQS1 = 0
5828 10:05:08.476273 DQM Delay:
5829 10:05:08.476393 DQM0 = 103, DQM1 = 98
5830 10:05:08.479028 DQ Delay:
5831 10:05:08.482854 DQ0 =111, DQ1 =99, DQ2 =87, DQ3 =95
5832 10:05:08.485869 DQ4 =95, DQ5 =119, DQ6 =119, DQ7 =99
5833 10:05:08.489438 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5834 10:05:08.492360 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5835 10:05:08.492543
5836 10:05:08.492675
5837 10:05:08.492767 ==
5838 10:05:08.496092 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 10:05:08.499511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 10:05:08.499690 ==
5841 10:05:08.499802
5842 10:05:08.499911
5843 10:05:08.503060 TX Vref Scan disable
5844 10:05:08.505636 == TX Byte 0 ==
5845 10:05:08.508960 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5846 10:05:08.512439 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5847 10:05:08.512600 == TX Byte 1 ==
5848 10:05:08.519445 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5849 10:05:08.522367 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5850 10:05:08.522585 ==
5851 10:05:08.525773 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 10:05:08.529000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 10:05:08.529233 ==
5854 10:05:08.532644
5855 10:05:08.532791
5856 10:05:08.532926 TX Vref Scan disable
5857 10:05:08.535653 == TX Byte 0 ==
5858 10:05:08.538842 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5859 10:05:08.542532 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5860 10:05:08.545458 == TX Byte 1 ==
5861 10:05:08.549048 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5862 10:05:08.555542 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5863 10:05:08.555732
5864 10:05:08.555842 [DATLAT]
5865 10:05:08.555957 Freq=933, CH1 RK1
5866 10:05:08.556051
5867 10:05:08.559054 DATLAT Default: 0xb
5868 10:05:08.559199 0, 0xFFFF, sum = 0
5869 10:05:08.562238 1, 0xFFFF, sum = 0
5870 10:05:08.562395 2, 0xFFFF, sum = 0
5871 10:05:08.565313 3, 0xFFFF, sum = 0
5872 10:05:08.568852 4, 0xFFFF, sum = 0
5873 10:05:08.569005 5, 0xFFFF, sum = 0
5874 10:05:08.572615 6, 0xFFFF, sum = 0
5875 10:05:08.572737 7, 0xFFFF, sum = 0
5876 10:05:08.575636 8, 0xFFFF, sum = 0
5877 10:05:08.575806 9, 0xFFFF, sum = 0
5878 10:05:08.578587 10, 0x0, sum = 1
5879 10:05:08.578696 11, 0x0, sum = 2
5880 10:05:08.582042 12, 0x0, sum = 3
5881 10:05:08.582193 13, 0x0, sum = 4
5882 10:05:08.582289 best_step = 11
5883 10:05:08.582369
5884 10:05:08.585694 ==
5885 10:05:08.588733 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 10:05:08.592398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 10:05:08.592538 ==
5888 10:05:08.592633 RX Vref Scan: 0
5889 10:05:08.592732
5890 10:05:08.595833 RX Vref 0 -> 0, step: 1
5891 10:05:08.595943
5892 10:05:08.599086 RX Delay -45 -> 252, step: 4
5893 10:05:08.602118 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5894 10:05:08.608599 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5895 10:05:08.612222 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5896 10:05:08.615949 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5897 10:05:08.618795 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5898 10:05:08.622688 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5899 10:05:08.628740 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5900 10:05:08.632046 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5901 10:05:08.635469 iDelay=203, Bit 8, Center 88 (7 ~ 170) 164
5902 10:05:08.639042 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5903 10:05:08.642084 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5904 10:05:08.645731 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5905 10:05:08.652401 iDelay=203, Bit 12, Center 112 (27 ~ 198) 172
5906 10:05:08.655672 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5907 10:05:08.658742 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5908 10:05:08.662265 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5909 10:05:08.662432 ==
5910 10:05:08.665289 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 10:05:08.672021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 10:05:08.672206 ==
5913 10:05:08.672310 DQS Delay:
5914 10:05:08.675270 DQS0 = 0, DQS1 = 0
5915 10:05:08.675418 DQM Delay:
5916 10:05:08.675528 DQM0 = 105, DQM1 = 101
5917 10:05:08.679411 DQ Delay:
5918 10:05:08.682236 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5919 10:05:08.685814 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5920 10:05:08.688673 DQ8 =88, DQ9 =90, DQ10 =102, DQ11 =94
5921 10:05:08.692343 DQ12 =112, DQ13 =108, DQ14 =106, DQ15 =110
5922 10:05:08.692509
5923 10:05:08.692611
5924 10:05:08.698688 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5925 10:05:08.701877 CH1 RK1: MR19=505, MR18=2F02
5926 10:05:08.708686 CH1_RK1: MR19=0x505, MR18=0x2F02, DQSOSC=407, MR23=63, INC=65, DEC=43
5927 10:05:08.712396 [RxdqsGatingPostProcess] freq 933
5928 10:05:08.718661 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5929 10:05:08.721890 best DQS0 dly(2T, 0.5T) = (0, 10)
5930 10:05:08.722041 best DQS1 dly(2T, 0.5T) = (0, 10)
5931 10:05:08.725426 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5932 10:05:08.728688 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5933 10:05:08.732355 best DQS0 dly(2T, 0.5T) = (0, 10)
5934 10:05:08.735601 best DQS1 dly(2T, 0.5T) = (0, 10)
5935 10:05:08.738803 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5936 10:05:08.742293 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5937 10:05:08.745737 Pre-setting of DQS Precalculation
5938 10:05:08.752776 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5939 10:05:08.759175 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5940 10:05:08.765509 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5941 10:05:08.765661
5942 10:05:08.765764
5943 10:05:08.768416 [Calibration Summary] 1866 Mbps
5944 10:05:08.768544 CH 0, Rank 0
5945 10:05:08.772256 SW Impedance : PASS
5946 10:05:08.775541 DUTY Scan : NO K
5947 10:05:08.775676 ZQ Calibration : PASS
5948 10:05:08.778784 Jitter Meter : NO K
5949 10:05:08.782080 CBT Training : PASS
5950 10:05:08.782238 Write leveling : PASS
5951 10:05:08.785481 RX DQS gating : PASS
5952 10:05:08.785618 RX DQ/DQS(RDDQC) : PASS
5953 10:05:08.788355 TX DQ/DQS : PASS
5954 10:05:08.791789 RX DATLAT : PASS
5955 10:05:08.791916 RX DQ/DQS(Engine): PASS
5956 10:05:08.795281 TX OE : NO K
5957 10:05:08.795417 All Pass.
5958 10:05:08.795502
5959 10:05:08.798341 CH 0, Rank 1
5960 10:05:08.798475 SW Impedance : PASS
5961 10:05:08.801956 DUTY Scan : NO K
5962 10:05:08.805037 ZQ Calibration : PASS
5963 10:05:08.805171 Jitter Meter : NO K
5964 10:05:08.808171 CBT Training : PASS
5965 10:05:08.812247 Write leveling : PASS
5966 10:05:08.812390 RX DQS gating : PASS
5967 10:05:08.815106 RX DQ/DQS(RDDQC) : PASS
5968 10:05:08.818335 TX DQ/DQS : PASS
5969 10:05:08.818477 RX DATLAT : PASS
5970 10:05:08.821931 RX DQ/DQS(Engine): PASS
5971 10:05:08.825075 TX OE : NO K
5972 10:05:08.825206 All Pass.
5973 10:05:08.825290
5974 10:05:08.825368 CH 1, Rank 0
5975 10:05:08.828466 SW Impedance : PASS
5976 10:05:08.831941 DUTY Scan : NO K
5977 10:05:08.832064 ZQ Calibration : PASS
5978 10:05:08.834919 Jitter Meter : NO K
5979 10:05:08.835039 CBT Training : PASS
5980 10:05:08.838428 Write leveling : PASS
5981 10:05:08.842109 RX DQS gating : PASS
5982 10:05:08.842256 RX DQ/DQS(RDDQC) : PASS
5983 10:05:08.845031 TX DQ/DQS : PASS
5984 10:05:08.848130 RX DATLAT : PASS
5985 10:05:08.848276 RX DQ/DQS(Engine): PASS
5986 10:05:08.851571 TX OE : NO K
5987 10:05:08.851682 All Pass.
5988 10:05:08.851753
5989 10:05:08.854934 CH 1, Rank 1
5990 10:05:08.855053 SW Impedance : PASS
5991 10:05:08.858390 DUTY Scan : NO K
5992 10:05:08.861428 ZQ Calibration : PASS
5993 10:05:08.861578 Jitter Meter : NO K
5994 10:05:08.865064 CBT Training : PASS
5995 10:05:08.868665 Write leveling : PASS
5996 10:05:08.868830 RX DQS gating : PASS
5997 10:05:08.871682 RX DQ/DQS(RDDQC) : PASS
5998 10:05:08.875174 TX DQ/DQS : PASS
5999 10:05:08.875297 RX DATLAT : PASS
6000 10:05:08.878082 RX DQ/DQS(Engine): PASS
6001 10:05:08.878229 TX OE : NO K
6002 10:05:08.881868 All Pass.
6003 10:05:08.882025
6004 10:05:08.882135 DramC Write-DBI off
6005 10:05:08.884714 PER_BANK_REFRESH: Hybrid Mode
6006 10:05:08.888257 TX_TRACKING: ON
6007 10:05:08.894693 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6008 10:05:08.898155 [FAST_K] Save calibration result to emmc
6009 10:05:08.905172 dramc_set_vcore_voltage set vcore to 650000
6010 10:05:08.905383 Read voltage for 400, 6
6011 10:05:08.905492 Vio18 = 0
6012 10:05:08.908448 Vcore = 650000
6013 10:05:08.908607 Vdram = 0
6014 10:05:08.908705 Vddq = 0
6015 10:05:08.911394 Vmddr = 0
6016 10:05:08.915017 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6017 10:05:08.921826 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6018 10:05:08.922018 MEM_TYPE=3, freq_sel=20
6019 10:05:08.925246 sv_algorithm_assistance_LP4_800
6020 10:05:08.931318 ============ PULL DRAM RESETB DOWN ============
6021 10:05:08.935001 ========== PULL DRAM RESETB DOWN end =========
6022 10:05:08.938158 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6023 10:05:08.941262 ===================================
6024 10:05:08.944744 LPDDR4 DRAM CONFIGURATION
6025 10:05:08.948071 ===================================
6026 10:05:08.951516 EX_ROW_EN[0] = 0x0
6027 10:05:08.951685 EX_ROW_EN[1] = 0x0
6028 10:05:08.954411 LP4Y_EN = 0x0
6029 10:05:08.954546 WORK_FSP = 0x0
6030 10:05:08.958466 WL = 0x2
6031 10:05:08.958630 RL = 0x2
6032 10:05:08.961351 BL = 0x2
6033 10:05:08.961498 RPST = 0x0
6034 10:05:08.964458 RD_PRE = 0x0
6035 10:05:08.964604 WR_PRE = 0x1
6036 10:05:08.967986 WR_PST = 0x0
6037 10:05:08.968174 DBI_WR = 0x0
6038 10:05:08.970967 DBI_RD = 0x0
6039 10:05:08.971121 OTF = 0x1
6040 10:05:08.974706 ===================================
6041 10:05:08.977863 ===================================
6042 10:05:08.981328 ANA top config
6043 10:05:08.984508 ===================================
6044 10:05:08.987765 DLL_ASYNC_EN = 0
6045 10:05:08.987931 ALL_SLAVE_EN = 1
6046 10:05:08.990984 NEW_RANK_MODE = 1
6047 10:05:08.994676 DLL_IDLE_MODE = 1
6048 10:05:08.997818 LP45_APHY_COMB_EN = 1
6049 10:05:09.000759 TX_ODT_DIS = 1
6050 10:05:09.000947 NEW_8X_MODE = 1
6051 10:05:09.004621 ===================================
6052 10:05:09.008066 ===================================
6053 10:05:09.010797 data_rate = 800
6054 10:05:09.013829 CKR = 1
6055 10:05:09.017535 DQ_P2S_RATIO = 4
6056 10:05:09.020459 ===================================
6057 10:05:09.024085 CA_P2S_RATIO = 4
6058 10:05:09.027615 DQ_CA_OPEN = 0
6059 10:05:09.027803 DQ_SEMI_OPEN = 1
6060 10:05:09.030675 CA_SEMI_OPEN = 1
6061 10:05:09.034261 CA_FULL_RATE = 0
6062 10:05:09.037364 DQ_CKDIV4_EN = 0
6063 10:05:09.040713 CA_CKDIV4_EN = 1
6064 10:05:09.040935 CA_PREDIV_EN = 0
6065 10:05:09.044172 PH8_DLY = 0
6066 10:05:09.047672 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6067 10:05:09.050760 DQ_AAMCK_DIV = 0
6068 10:05:09.054379 CA_AAMCK_DIV = 0
6069 10:05:09.057240 CA_ADMCK_DIV = 4
6070 10:05:09.057418 DQ_TRACK_CA_EN = 0
6071 10:05:09.060761 CA_PICK = 800
6072 10:05:09.063811 CA_MCKIO = 400
6073 10:05:09.067349 MCKIO_SEMI = 400
6074 10:05:09.070558 PLL_FREQ = 3016
6075 10:05:09.073882 DQ_UI_PI_RATIO = 32
6076 10:05:09.077200 CA_UI_PI_RATIO = 32
6077 10:05:09.080800 ===================================
6078 10:05:09.084014 ===================================
6079 10:05:09.084172 memory_type:LPDDR4
6080 10:05:09.086875 GP_NUM : 10
6081 10:05:09.090499 SRAM_EN : 1
6082 10:05:09.090654 MD32_EN : 0
6083 10:05:09.093506 ===================================
6084 10:05:09.097306 [ANA_INIT] >>>>>>>>>>>>>>
6085 10:05:09.100172 <<<<<< [CONFIGURE PHASE]: ANA_TX
6086 10:05:09.103870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6087 10:05:09.107148 ===================================
6088 10:05:09.110386 data_rate = 800,PCW = 0X7400
6089 10:05:09.113629 ===================================
6090 10:05:09.117133 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6091 10:05:09.120238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6092 10:05:09.133831 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6093 10:05:09.137215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6094 10:05:09.140042 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6095 10:05:09.143647 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6096 10:05:09.147221 [ANA_INIT] flow start
6097 10:05:09.150692 [ANA_INIT] PLL >>>>>>>>
6098 10:05:09.150826 [ANA_INIT] PLL <<<<<<<<
6099 10:05:09.153807 [ANA_INIT] MIDPI >>>>>>>>
6100 10:05:09.157279 [ANA_INIT] MIDPI <<<<<<<<
6101 10:05:09.157406 [ANA_INIT] DLL >>>>>>>>
6102 10:05:09.160451 [ANA_INIT] flow end
6103 10:05:09.163481 ============ LP4 DIFF to SE enter ============
6104 10:05:09.166813 ============ LP4 DIFF to SE exit ============
6105 10:05:09.170064 [ANA_INIT] <<<<<<<<<<<<<
6106 10:05:09.173386 [Flow] Enable top DCM control >>>>>
6107 10:05:09.176663 [Flow] Enable top DCM control <<<<<
6108 10:05:09.179836 Enable DLL master slave shuffle
6109 10:05:09.186760 ==============================================================
6110 10:05:09.186919 Gating Mode config
6111 10:05:09.193248 ==============================================================
6112 10:05:09.193446 Config description:
6113 10:05:09.203190 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6114 10:05:09.209902 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6115 10:05:09.216353 SELPH_MODE 0: By rank 1: By Phase
6116 10:05:09.219756 ==============================================================
6117 10:05:09.222928 GAT_TRACK_EN = 0
6118 10:05:09.226357 RX_GATING_MODE = 2
6119 10:05:09.230146 RX_GATING_TRACK_MODE = 2
6120 10:05:09.232960 SELPH_MODE = 1
6121 10:05:09.236436 PICG_EARLY_EN = 1
6122 10:05:09.239986 VALID_LAT_VALUE = 1
6123 10:05:09.246639 ==============================================================
6124 10:05:09.249720 Enter into Gating configuration >>>>
6125 10:05:09.253140 Exit from Gating configuration <<<<
6126 10:05:09.256246 Enter into DVFS_PRE_config >>>>>
6127 10:05:09.266844 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6128 10:05:09.269522 Exit from DVFS_PRE_config <<<<<
6129 10:05:09.273196 Enter into PICG configuration >>>>
6130 10:05:09.276273 Exit from PICG configuration <<<<
6131 10:05:09.279657 [RX_INPUT] configuration >>>>>
6132 10:05:09.279830 [RX_INPUT] configuration <<<<<
6133 10:05:09.286269 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6134 10:05:09.293038 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6135 10:05:09.296449 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6136 10:05:09.302872 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6137 10:05:09.309449 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6138 10:05:09.315995 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6139 10:05:09.319641 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6140 10:05:09.322795 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6141 10:05:09.329689 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6142 10:05:09.332498 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6143 10:05:09.336325 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6144 10:05:09.342703 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6145 10:05:09.342884 ===================================
6146 10:05:09.346475 LPDDR4 DRAM CONFIGURATION
6147 10:05:09.349605 ===================================
6148 10:05:09.352557 EX_ROW_EN[0] = 0x0
6149 10:05:09.352716 EX_ROW_EN[1] = 0x0
6150 10:05:09.356090 LP4Y_EN = 0x0
6151 10:05:09.356253 WORK_FSP = 0x0
6152 10:05:09.359230 WL = 0x2
6153 10:05:09.359384 RL = 0x2
6154 10:05:09.362629 BL = 0x2
6155 10:05:09.362788 RPST = 0x0
6156 10:05:09.366042 RD_PRE = 0x0
6157 10:05:09.369536 WR_PRE = 0x1
6158 10:05:09.369700 WR_PST = 0x0
6159 10:05:09.372612 DBI_WR = 0x0
6160 10:05:09.372765 DBI_RD = 0x0
6161 10:05:09.375597 OTF = 0x1
6162 10:05:09.379294 ===================================
6163 10:05:09.382285 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6164 10:05:09.385682 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6165 10:05:09.389421 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6166 10:05:09.392137 ===================================
6167 10:05:09.395598 LPDDR4 DRAM CONFIGURATION
6168 10:05:09.399064 ===================================
6169 10:05:09.402319 EX_ROW_EN[0] = 0x10
6170 10:05:09.402497 EX_ROW_EN[1] = 0x0
6171 10:05:09.405668 LP4Y_EN = 0x0
6172 10:05:09.405838 WORK_FSP = 0x0
6173 10:05:09.408858 WL = 0x2
6174 10:05:09.409015 RL = 0x2
6175 10:05:09.412514 BL = 0x2
6176 10:05:09.412649 RPST = 0x0
6177 10:05:09.415746 RD_PRE = 0x0
6178 10:05:09.415911 WR_PRE = 0x1
6179 10:05:09.419056 WR_PST = 0x0
6180 10:05:09.419188 DBI_WR = 0x0
6181 10:05:09.422649 DBI_RD = 0x0
6182 10:05:09.425906 OTF = 0x1
6183 10:05:09.429298 ===================================
6184 10:05:09.432094 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6185 10:05:09.437473 nWR fixed to 30
6186 10:05:09.440935 [ModeRegInit_LP4] CH0 RK0
6187 10:05:09.441074 [ModeRegInit_LP4] CH0 RK1
6188 10:05:09.444246 [ModeRegInit_LP4] CH1 RK0
6189 10:05:09.446969 [ModeRegInit_LP4] CH1 RK1
6190 10:05:09.447094 match AC timing 19
6191 10:05:09.453658 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6192 10:05:09.457281 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6193 10:05:09.460671 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6194 10:05:09.467658 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6195 10:05:09.470252 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6196 10:05:09.470381 ==
6197 10:05:09.473753 Dram Type= 6, Freq= 0, CH_0, rank 0
6198 10:05:09.477347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6199 10:05:09.477495 ==
6200 10:05:09.484233 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6201 10:05:09.490773 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6202 10:05:09.493919 [CA 0] Center 36 (8~64) winsize 57
6203 10:05:09.497577 [CA 1] Center 36 (8~64) winsize 57
6204 10:05:09.500537 [CA 2] Center 36 (8~64) winsize 57
6205 10:05:09.500702 [CA 3] Center 36 (8~64) winsize 57
6206 10:05:09.503890 [CA 4] Center 36 (8~64) winsize 57
6207 10:05:09.507246 [CA 5] Center 36 (8~64) winsize 57
6208 10:05:09.507407
6209 10:05:09.513695 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6210 10:05:09.513865
6211 10:05:09.516938 [CATrainingPosCal] consider 1 rank data
6212 10:05:09.520486 u2DelayCellTimex100 = 270/100 ps
6213 10:05:09.523640 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 10:05:09.527063 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 10:05:09.530208 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 10:05:09.534020 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 10:05:09.536916 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 10:05:09.540151 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 10:05:09.540337
6220 10:05:09.543820 CA PerBit enable=1, Macro0, CA PI delay=36
6221 10:05:09.543949
6222 10:05:09.547443 [CBTSetCACLKResult] CA Dly = 36
6223 10:05:09.550379 CS Dly: 1 (0~32)
6224 10:05:09.550511 ==
6225 10:05:09.554014 Dram Type= 6, Freq= 0, CH_0, rank 1
6226 10:05:09.556955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6227 10:05:09.557082 ==
6228 10:05:09.564126 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6229 10:05:09.567297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6230 10:05:09.570280 [CA 0] Center 36 (8~64) winsize 57
6231 10:05:09.573912 [CA 1] Center 36 (8~64) winsize 57
6232 10:05:09.577204 [CA 2] Center 36 (8~64) winsize 57
6233 10:05:09.580718 [CA 3] Center 36 (8~64) winsize 57
6234 10:05:09.583627 [CA 4] Center 36 (8~64) winsize 57
6235 10:05:09.586753 [CA 5] Center 36 (8~64) winsize 57
6236 10:05:09.586911
6237 10:05:09.590529 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6238 10:05:09.590685
6239 10:05:09.594258 [CATrainingPosCal] consider 2 rank data
6240 10:05:09.597103 u2DelayCellTimex100 = 270/100 ps
6241 10:05:09.600237 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 10:05:09.604076 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 10:05:09.607346 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 10:05:09.613789 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 10:05:09.617469 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 10:05:09.620700 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 10:05:09.620864
6248 10:05:09.623623 CA PerBit enable=1, Macro0, CA PI delay=36
6249 10:05:09.623741
6250 10:05:09.627079 [CBTSetCACLKResult] CA Dly = 36
6251 10:05:09.627206 CS Dly: 1 (0~32)
6252 10:05:09.627278
6253 10:05:09.630355 ----->DramcWriteLeveling(PI) begin...
6254 10:05:09.630505 ==
6255 10:05:09.634005 Dram Type= 6, Freq= 0, CH_0, rank 0
6256 10:05:09.639971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 10:05:09.640121 ==
6258 10:05:09.643418 Write leveling (Byte 0): 40 => 8
6259 10:05:09.646874 Write leveling (Byte 1): 40 => 8
6260 10:05:09.646985 DramcWriteLeveling(PI) end<-----
6261 10:05:09.647054
6262 10:05:09.649820 ==
6263 10:05:09.653233 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 10:05:09.656946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 10:05:09.657060 ==
6266 10:05:09.659750 [Gating] SW mode calibration
6267 10:05:09.666507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6268 10:05:09.670462 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6269 10:05:09.677030 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6270 10:05:09.680031 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6271 10:05:09.683035 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 10:05:09.689842 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6273 10:05:09.693272 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 10:05:09.696555 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 10:05:09.703291 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 10:05:09.706767 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 10:05:09.709981 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 10:05:09.712792 Total UI for P1: 0, mck2ui 16
6279 10:05:09.716360 best dqsien dly found for B0: ( 0, 14, 24)
6280 10:05:09.720354 Total UI for P1: 0, mck2ui 16
6281 10:05:09.723536 best dqsien dly found for B1: ( 0, 14, 24)
6282 10:05:09.726337 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6283 10:05:09.729570 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6284 10:05:09.729702
6285 10:05:09.736366 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6286 10:05:09.739787 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6287 10:05:09.739921 [Gating] SW calibration Done
6288 10:05:09.743435 ==
6289 10:05:09.746209 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 10:05:09.749672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 10:05:09.749817 ==
6292 10:05:09.749904 RX Vref Scan: 0
6293 10:05:09.749988
6294 10:05:09.753271 RX Vref 0 -> 0, step: 1
6295 10:05:09.753390
6296 10:05:09.756246 RX Delay -410 -> 252, step: 16
6297 10:05:09.759858 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6298 10:05:09.763054 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6299 10:05:09.769725 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6300 10:05:09.772780 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6301 10:05:09.776693 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6302 10:05:09.779509 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6303 10:05:09.786353 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6304 10:05:09.789315 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6305 10:05:09.793085 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6306 10:05:09.796280 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6307 10:05:09.802928 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6308 10:05:09.805906 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6309 10:05:09.809673 iDelay=230, Bit 12, Center -11 (-234 ~ 213) 448
6310 10:05:09.812971 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6311 10:05:09.819431 iDelay=230, Bit 14, Center -3 (-234 ~ 229) 464
6312 10:05:09.822945 iDelay=230, Bit 15, Center -11 (-234 ~ 213) 448
6313 10:05:09.823084 ==
6314 10:05:09.825799 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 10:05:09.829440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 10:05:09.829568 ==
6317 10:05:09.832971 DQS Delay:
6318 10:05:09.833097 DQS0 = 27, DQS1 = 35
6319 10:05:09.835875 DQM Delay:
6320 10:05:09.835971 DQM0 = 14, DQM1 = 16
6321 10:05:09.836039 DQ Delay:
6322 10:05:09.839318 DQ0 =16, DQ1 =24, DQ2 =0, DQ3 =8
6323 10:05:09.842778 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6324 10:05:09.846049 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6325 10:05:09.849726 DQ12 =24, DQ13 =24, DQ14 =32, DQ15 =24
6326 10:05:09.849875
6327 10:05:09.849944
6328 10:05:09.850005 ==
6329 10:05:09.852832 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 10:05:09.859605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 10:05:09.859741 ==
6332 10:05:09.859809
6333 10:05:09.859872
6334 10:05:09.859931 TX Vref Scan disable
6335 10:05:09.862701 == TX Byte 0 ==
6336 10:05:09.866173 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6337 10:05:09.869632 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6338 10:05:09.872879 == TX Byte 1 ==
6339 10:05:09.875805 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6340 10:05:09.879583 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6341 10:05:09.879756 ==
6342 10:05:09.882560 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 10:05:09.889371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 10:05:09.889529 ==
6345 10:05:09.889599
6346 10:05:09.889661
6347 10:05:09.889719 TX Vref Scan disable
6348 10:05:09.892699 == TX Byte 0 ==
6349 10:05:09.895938 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6350 10:05:09.899734 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6351 10:05:09.902483 == TX Byte 1 ==
6352 10:05:09.906087 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 10:05:09.909467 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 10:05:09.909674
6355 10:05:09.912557 [DATLAT]
6356 10:05:09.912766 Freq=400, CH0 RK0
6357 10:05:09.912915
6358 10:05:09.915846 DATLAT Default: 0xf
6359 10:05:09.916049 0, 0xFFFF, sum = 0
6360 10:05:09.919519 1, 0xFFFF, sum = 0
6361 10:05:09.919686 2, 0xFFFF, sum = 0
6362 10:05:09.922680 3, 0xFFFF, sum = 0
6363 10:05:09.922803 4, 0xFFFF, sum = 0
6364 10:05:09.926494 5, 0xFFFF, sum = 0
6365 10:05:09.926674 6, 0xFFFF, sum = 0
6366 10:05:09.929657 7, 0xFFFF, sum = 0
6367 10:05:09.929823 8, 0xFFFF, sum = 0
6368 10:05:09.932597 9, 0xFFFF, sum = 0
6369 10:05:09.932733 10, 0xFFFF, sum = 0
6370 10:05:09.936177 11, 0xFFFF, sum = 0
6371 10:05:09.936363 12, 0xFFFF, sum = 0
6372 10:05:09.939658 13, 0x0, sum = 1
6373 10:05:09.939802 14, 0x0, sum = 2
6374 10:05:09.942724 15, 0x0, sum = 3
6375 10:05:09.942828 16, 0x0, sum = 4
6376 10:05:09.946424 best_step = 14
6377 10:05:09.946550
6378 10:05:09.946619 ==
6379 10:05:09.949604 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 10:05:09.952893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 10:05:09.953089 ==
6382 10:05:09.956392 RX Vref Scan: 1
6383 10:05:09.956548
6384 10:05:09.956645 RX Vref 0 -> 0, step: 1
6385 10:05:09.956750
6386 10:05:09.959168 RX Delay -311 -> 252, step: 8
6387 10:05:09.959295
6388 10:05:09.962611 Set Vref, RX VrefLevel [Byte0]: 55
6389 10:05:09.965822 [Byte1]: 50
6390 10:05:09.970528
6391 10:05:09.970683 Final RX Vref Byte 0 = 55 to rank0
6392 10:05:09.973723 Final RX Vref Byte 1 = 50 to rank0
6393 10:05:09.976826 Final RX Vref Byte 0 = 55 to rank1
6394 10:05:09.980223 Final RX Vref Byte 1 = 50 to rank1==
6395 10:05:09.983712 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 10:05:09.990546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 10:05:09.990691 ==
6398 10:05:09.990759 DQS Delay:
6399 10:05:09.990823 DQS0 = 28, DQS1 = 36
6400 10:05:09.994081 DQM Delay:
6401 10:05:09.994215 DQM0 = 11, DQM1 = 13
6402 10:05:09.997034 DQ Delay:
6403 10:05:10.000835 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6404 10:05:10.001041 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6405 10:05:10.003883 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6406 10:05:10.007357 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6407 10:05:10.007564
6408 10:05:10.007652
6409 10:05:10.016717 [DQSOSCAuto] RK0, (LSB)MR18= 0xcdba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6410 10:05:10.020077 CH0 RK0: MR19=C0C, MR18=CDBA
6411 10:05:10.026764 CH0_RK0: MR19=0xC0C, MR18=0xCDBA, DQSOSC=384, MR23=63, INC=400, DEC=267
6412 10:05:10.026919 ==
6413 10:05:10.030005 Dram Type= 6, Freq= 0, CH_0, rank 1
6414 10:05:10.033570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 10:05:10.033717 ==
6416 10:05:10.037209 [Gating] SW mode calibration
6417 10:05:10.043828 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6418 10:05:10.050272 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6419 10:05:10.053623 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6420 10:05:10.056963 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6421 10:05:10.060456 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 10:05:10.067175 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 10:05:10.070329 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 10:05:10.073564 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 10:05:10.080026 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 10:05:10.083631 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 10:05:10.087009 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 10:05:10.090186 Total UI for P1: 0, mck2ui 16
6429 10:05:10.093686 best dqsien dly found for B0: ( 0, 14, 24)
6430 10:05:10.096826 Total UI for P1: 0, mck2ui 16
6431 10:05:10.100492 best dqsien dly found for B1: ( 0, 14, 24)
6432 10:05:10.103523 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6433 10:05:10.107397 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6434 10:05:10.109914
6435 10:05:10.113609 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6436 10:05:10.116511 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6437 10:05:10.120109 [Gating] SW calibration Done
6438 10:05:10.120274 ==
6439 10:05:10.123635 Dram Type= 6, Freq= 0, CH_0, rank 1
6440 10:05:10.127094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 10:05:10.127256 ==
6442 10:05:10.127360 RX Vref Scan: 0
6443 10:05:10.127452
6444 10:05:10.130108 RX Vref 0 -> 0, step: 1
6445 10:05:10.130272
6446 10:05:10.133896 RX Delay -410 -> 252, step: 16
6447 10:05:10.137182 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6448 10:05:10.143519 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6449 10:05:10.146598 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6450 10:05:10.149811 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6451 10:05:10.153257 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6452 10:05:10.159732 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6453 10:05:10.163533 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6454 10:05:10.166966 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6455 10:05:10.170247 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6456 10:05:10.173482 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6457 10:05:10.179894 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6458 10:05:10.183701 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6459 10:05:10.186779 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6460 10:05:10.193754 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6461 10:05:10.196698 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6462 10:05:10.200822 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6463 10:05:10.200974 ==
6464 10:05:10.203352 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 10:05:10.207258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 10:05:10.207398 ==
6467 10:05:10.210500 DQS Delay:
6468 10:05:10.210613 DQS0 = 27, DQS1 = 35
6469 10:05:10.213541 DQM Delay:
6470 10:05:10.213657 DQM0 = 12, DQM1 = 11
6471 10:05:10.213762 DQ Delay:
6472 10:05:10.217015 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6473 10:05:10.219953 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6474 10:05:10.223658 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6475 10:05:10.226636 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6476 10:05:10.226779
6477 10:05:10.226886
6478 10:05:10.226974 ==
6479 10:05:10.230223 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 10:05:10.236414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 10:05:10.236605 ==
6482 10:05:10.236705
6483 10:05:10.236800
6484 10:05:10.236901 TX Vref Scan disable
6485 10:05:10.239900 == TX Byte 0 ==
6486 10:05:10.243258 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6487 10:05:10.246392 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6488 10:05:10.249968 == TX Byte 1 ==
6489 10:05:10.253005 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6490 10:05:10.256955 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6491 10:05:10.259782 ==
6492 10:05:10.259936 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 10:05:10.266555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 10:05:10.266751 ==
6495 10:05:10.266860
6496 10:05:10.266957
6497 10:05:10.269735 TX Vref Scan disable
6498 10:05:10.269873 == TX Byte 0 ==
6499 10:05:10.273313 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6500 10:05:10.280295 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6501 10:05:10.280485 == TX Byte 1 ==
6502 10:05:10.283134 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6503 10:05:10.290018 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6504 10:05:10.290219
6505 10:05:10.290336 [DATLAT]
6506 10:05:10.290428 Freq=400, CH0 RK1
6507 10:05:10.290517
6508 10:05:10.293241 DATLAT Default: 0xe
6509 10:05:10.293378 0, 0xFFFF, sum = 0
6510 10:05:10.296096 1, 0xFFFF, sum = 0
6511 10:05:10.299809 2, 0xFFFF, sum = 0
6512 10:05:10.299973 3, 0xFFFF, sum = 0
6513 10:05:10.303359 4, 0xFFFF, sum = 0
6514 10:05:10.303501 5, 0xFFFF, sum = 0
6515 10:05:10.306608 6, 0xFFFF, sum = 0
6516 10:05:10.306747 7, 0xFFFF, sum = 0
6517 10:05:10.309724 8, 0xFFFF, sum = 0
6518 10:05:10.309863 9, 0xFFFF, sum = 0
6519 10:05:10.312677 10, 0xFFFF, sum = 0
6520 10:05:10.312827 11, 0xFFFF, sum = 0
6521 10:05:10.316377 12, 0xFFFF, sum = 0
6522 10:05:10.316525 13, 0x0, sum = 1
6523 10:05:10.319906 14, 0x0, sum = 2
6524 10:05:10.320048 15, 0x0, sum = 3
6525 10:05:10.322783 16, 0x0, sum = 4
6526 10:05:10.322924 best_step = 14
6527 10:05:10.323018
6528 10:05:10.323118 ==
6529 10:05:10.326483 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 10:05:10.329440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 10:05:10.333178 ==
6532 10:05:10.333340 RX Vref Scan: 0
6533 10:05:10.333445
6534 10:05:10.336144 RX Vref 0 -> 0, step: 1
6535 10:05:10.336259
6536 10:05:10.339722 RX Delay -311 -> 252, step: 8
6537 10:05:10.342778 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6538 10:05:10.349547 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6539 10:05:10.352533 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6540 10:05:10.356320 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6541 10:05:10.359365 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6542 10:05:10.365968 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6543 10:05:10.369243 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6544 10:05:10.372928 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6545 10:05:10.376238 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6546 10:05:10.383126 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6547 10:05:10.386039 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6548 10:05:10.389813 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6549 10:05:10.392905 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6550 10:05:10.399857 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6551 10:05:10.402917 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6552 10:05:10.406085 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6553 10:05:10.406198 ==
6554 10:05:10.409860 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 10:05:10.416066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 10:05:10.416220 ==
6557 10:05:10.416293 DQS Delay:
6558 10:05:10.416364 DQS0 = 24, DQS1 = 32
6559 10:05:10.419256 DQM Delay:
6560 10:05:10.419373 DQM0 = 8, DQM1 = 8
6561 10:05:10.422990 DQ Delay:
6562 10:05:10.423116 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6563 10:05:10.426109 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6564 10:05:10.429536 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6565 10:05:10.432738 DQ12 =12, DQ13 =12, DQ14 =16, DQ15 =16
6566 10:05:10.432887
6567 10:05:10.433006
6568 10:05:10.442833 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6569 10:05:10.446402 CH0 RK1: MR19=C0C, MR18=BD5C
6570 10:05:10.449479 CH0_RK1: MR19=0xC0C, MR18=0xBD5C, DQSOSC=386, MR23=63, INC=396, DEC=264
6571 10:05:10.452701 [RxdqsGatingPostProcess] freq 400
6572 10:05:10.459629 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6573 10:05:10.462608 best DQS0 dly(2T, 0.5T) = (0, 10)
6574 10:05:10.466252 best DQS1 dly(2T, 0.5T) = (0, 10)
6575 10:05:10.469340 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6576 10:05:10.472961 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6577 10:05:10.476223 best DQS0 dly(2T, 0.5T) = (0, 10)
6578 10:05:10.479595 best DQS1 dly(2T, 0.5T) = (0, 10)
6579 10:05:10.482446 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6580 10:05:10.485847 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6581 10:05:10.489639 Pre-setting of DQS Precalculation
6582 10:05:10.492427 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6583 10:05:10.492540 ==
6584 10:05:10.495879 Dram Type= 6, Freq= 0, CH_1, rank 0
6585 10:05:10.499142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 10:05:10.499279 ==
6587 10:05:10.505743 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6588 10:05:10.512420 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6589 10:05:10.515819 [CA 0] Center 36 (8~64) winsize 57
6590 10:05:10.519356 [CA 1] Center 36 (8~64) winsize 57
6591 10:05:10.522130 [CA 2] Center 36 (8~64) winsize 57
6592 10:05:10.525757 [CA 3] Center 36 (8~64) winsize 57
6593 10:05:10.528919 [CA 4] Center 36 (8~64) winsize 57
6594 10:05:10.529116 [CA 5] Center 36 (8~64) winsize 57
6595 10:05:10.532190
6596 10:05:10.535906 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6597 10:05:10.536098
6598 10:05:10.539245 [CATrainingPosCal] consider 1 rank data
6599 10:05:10.542865 u2DelayCellTimex100 = 270/100 ps
6600 10:05:10.545582 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 10:05:10.549176 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 10:05:10.552124 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 10:05:10.555761 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 10:05:10.558700 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 10:05:10.562426 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 10:05:10.562554
6607 10:05:10.565892 CA PerBit enable=1, Macro0, CA PI delay=36
6608 10:05:10.566024
6609 10:05:10.569121 [CBTSetCACLKResult] CA Dly = 36
6610 10:05:10.572596 CS Dly: 1 (0~32)
6611 10:05:10.572718 ==
6612 10:05:10.576056 Dram Type= 6, Freq= 0, CH_1, rank 1
6613 10:05:10.579348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 10:05:10.579472 ==
6615 10:05:10.585899 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6616 10:05:10.588887 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6617 10:05:10.592670 [CA 0] Center 36 (8~64) winsize 57
6618 10:05:10.595626 [CA 1] Center 36 (8~64) winsize 57
6619 10:05:10.598847 [CA 2] Center 36 (8~64) winsize 57
6620 10:05:10.602091 [CA 3] Center 36 (8~64) winsize 57
6621 10:05:10.605340 [CA 4] Center 36 (8~64) winsize 57
6622 10:05:10.609050 [CA 5] Center 36 (8~64) winsize 57
6623 10:05:10.609241
6624 10:05:10.612525 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6625 10:05:10.612668
6626 10:05:10.615292 [CATrainingPosCal] consider 2 rank data
6627 10:05:10.618902 u2DelayCellTimex100 = 270/100 ps
6628 10:05:10.622427 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 10:05:10.625659 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 10:05:10.631888 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 10:05:10.635268 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 10:05:10.638913 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 10:05:10.641883 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 10:05:10.642007
6635 10:05:10.645831 CA PerBit enable=1, Macro0, CA PI delay=36
6636 10:05:10.645958
6637 10:05:10.648351 [CBTSetCACLKResult] CA Dly = 36
6638 10:05:10.648497 CS Dly: 1 (0~32)
6639 10:05:10.648609
6640 10:05:10.655305 ----->DramcWriteLeveling(PI) begin...
6641 10:05:10.655459 ==
6642 10:05:10.658381 Dram Type= 6, Freq= 0, CH_1, rank 0
6643 10:05:10.661903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 10:05:10.662029 ==
6645 10:05:10.664916 Write leveling (Byte 0): 40 => 8
6646 10:05:10.668394 Write leveling (Byte 1): 40 => 8
6647 10:05:10.671647 DramcWriteLeveling(PI) end<-----
6648 10:05:10.671782
6649 10:05:10.671854 ==
6650 10:05:10.674982 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 10:05:10.678618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 10:05:10.678750 ==
6653 10:05:10.681690 [Gating] SW mode calibration
6654 10:05:10.688581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6655 10:05:10.695191 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6656 10:05:10.698205 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6657 10:05:10.701872 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6658 10:05:10.705132 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 10:05:10.711535 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 10:05:10.714952 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 10:05:10.718445 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 10:05:10.725116 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 10:05:10.728008 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 10:05:10.731597 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 10:05:10.735014 Total UI for P1: 0, mck2ui 16
6666 10:05:10.738279 best dqsien dly found for B0: ( 0, 14, 24)
6667 10:05:10.741741 Total UI for P1: 0, mck2ui 16
6668 10:05:10.744656 best dqsien dly found for B1: ( 0, 14, 24)
6669 10:05:10.748202 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6670 10:05:10.754941 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6671 10:05:10.755092
6672 10:05:10.758027 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6673 10:05:10.761675 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6674 10:05:10.764939 [Gating] SW calibration Done
6675 10:05:10.765063 ==
6676 10:05:10.768432 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 10:05:10.771427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 10:05:10.771553 ==
6679 10:05:10.774765 RX Vref Scan: 0
6680 10:05:10.774878
6681 10:05:10.774950 RX Vref 0 -> 0, step: 1
6682 10:05:10.775014
6683 10:05:10.777766 RX Delay -410 -> 252, step: 16
6684 10:05:10.781121 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6685 10:05:10.787880 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6686 10:05:10.791429 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6687 10:05:10.794467 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6688 10:05:10.798089 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6689 10:05:10.804565 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6690 10:05:10.808425 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6691 10:05:10.811204 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6692 10:05:10.815152 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6693 10:05:10.821524 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6694 10:05:10.824988 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6695 10:05:10.828029 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6696 10:05:10.831321 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6697 10:05:10.838328 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6698 10:05:10.841041 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6699 10:05:10.844281 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6700 10:05:10.844485 ==
6701 10:05:10.847927 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 10:05:10.851290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 10:05:10.854278 ==
6704 10:05:10.854491 DQS Delay:
6705 10:05:10.854624 DQS0 = 27, DQS1 = 35
6706 10:05:10.857721 DQM Delay:
6707 10:05:10.857881 DQM0 = 10, DQM1 = 13
6708 10:05:10.861047 DQ Delay:
6709 10:05:10.864751 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6710 10:05:10.864917 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6711 10:05:10.867808 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6712 10:05:10.870849 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6713 10:05:10.870980
6714 10:05:10.871053
6715 10:05:10.874321 ==
6716 10:05:10.874508 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 10:05:10.880937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 10:05:10.881123 ==
6719 10:05:10.881200
6720 10:05:10.881263
6721 10:05:10.884518 TX Vref Scan disable
6722 10:05:10.884632 == TX Byte 0 ==
6723 10:05:10.887891 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6724 10:05:10.894497 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6725 10:05:10.894662 == TX Byte 1 ==
6726 10:05:10.897598 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6727 10:05:10.901176 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6728 10:05:10.904346 ==
6729 10:05:10.908341 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 10:05:10.911007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 10:05:10.911130 ==
6732 10:05:10.911202
6733 10:05:10.911265
6734 10:05:10.914054 TX Vref Scan disable
6735 10:05:10.914155 == TX Byte 0 ==
6736 10:05:10.917371 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6737 10:05:10.924109 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6738 10:05:10.924258 == TX Byte 1 ==
6739 10:05:10.927340 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 10:05:10.934305 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 10:05:10.934457
6742 10:05:10.934530 [DATLAT]
6743 10:05:10.934595 Freq=400, CH1 RK0
6744 10:05:10.934657
6745 10:05:10.937559 DATLAT Default: 0xf
6746 10:05:10.937670 0, 0xFFFF, sum = 0
6747 10:05:10.940931 1, 0xFFFF, sum = 0
6748 10:05:10.941047 2, 0xFFFF, sum = 0
6749 10:05:10.944516 3, 0xFFFF, sum = 0
6750 10:05:10.947298 4, 0xFFFF, sum = 0
6751 10:05:10.947418 5, 0xFFFF, sum = 0
6752 10:05:10.950905 6, 0xFFFF, sum = 0
6753 10:05:10.951020 7, 0xFFFF, sum = 0
6754 10:05:10.954285 8, 0xFFFF, sum = 0
6755 10:05:10.954419 9, 0xFFFF, sum = 0
6756 10:05:10.957891 10, 0xFFFF, sum = 0
6757 10:05:10.958028 11, 0xFFFF, sum = 0
6758 10:05:10.961076 12, 0xFFFF, sum = 0
6759 10:05:10.961218 13, 0x0, sum = 1
6760 10:05:10.964469 14, 0x0, sum = 2
6761 10:05:10.964639 15, 0x0, sum = 3
6762 10:05:10.967494 16, 0x0, sum = 4
6763 10:05:10.967632 best_step = 14
6764 10:05:10.967707
6765 10:05:10.967771 ==
6766 10:05:10.970577 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 10:05:10.974270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 10:05:10.974416 ==
6769 10:05:10.977207 RX Vref Scan: 1
6770 10:05:10.977324
6771 10:05:10.980986 RX Vref 0 -> 0, step: 1
6772 10:05:10.981132
6773 10:05:10.983854 RX Delay -311 -> 252, step: 8
6774 10:05:10.983977
6775 10:05:10.984053 Set Vref, RX VrefLevel [Byte0]: 54
6776 10:05:10.987395 [Byte1]: 56
6777 10:05:10.992733
6778 10:05:10.992896 Final RX Vref Byte 0 = 54 to rank0
6779 10:05:10.996277 Final RX Vref Byte 1 = 56 to rank0
6780 10:05:10.999336 Final RX Vref Byte 0 = 54 to rank1
6781 10:05:11.002652 Final RX Vref Byte 1 = 56 to rank1==
6782 10:05:11.006151 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 10:05:11.013013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 10:05:11.013175 ==
6785 10:05:11.013252 DQS Delay:
6786 10:05:11.016208 DQS0 = 28, DQS1 = 32
6787 10:05:11.016322 DQM Delay:
6788 10:05:11.016394 DQM0 = 10, DQM1 = 9
6789 10:05:11.019383 DQ Delay:
6790 10:05:11.022871 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6791 10:05:11.022999 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6792 10:05:11.025861 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6793 10:05:11.029569 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6794 10:05:11.029704
6795 10:05:11.029779
6796 10:05:11.039336 [DQSOSCAuto] RK0, (LSB)MR18= 0x92ca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6797 10:05:11.042867 CH1 RK0: MR19=C0C, MR18=92CA
6798 10:05:11.049158 CH1_RK0: MR19=0xC0C, MR18=0x92CA, DQSOSC=384, MR23=63, INC=400, DEC=267
6799 10:05:11.049307 ==
6800 10:05:11.052992 Dram Type= 6, Freq= 0, CH_1, rank 1
6801 10:05:11.055872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 10:05:11.056033 ==
6803 10:05:11.059276 [Gating] SW mode calibration
6804 10:05:11.066064 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6805 10:05:11.069203 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6806 10:05:11.075766 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6807 10:05:11.079737 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6808 10:05:11.082368 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6809 10:05:11.089685 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6810 10:05:11.092507 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 10:05:11.096101 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 10:05:11.102605 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 10:05:11.105658 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 10:05:11.109134 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 10:05:11.112826 Total UI for P1: 0, mck2ui 16
6816 10:05:11.115632 best dqsien dly found for B0: ( 0, 14, 24)
6817 10:05:11.119335 Total UI for P1: 0, mck2ui 16
6818 10:05:11.122310 best dqsien dly found for B1: ( 0, 14, 24)
6819 10:05:11.126042 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6820 10:05:11.129084 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6821 10:05:11.129219
6822 10:05:11.135664 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6823 10:05:11.139235 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6824 10:05:11.142135 [Gating] SW calibration Done
6825 10:05:11.142265 ==
6826 10:05:11.145498 Dram Type= 6, Freq= 0, CH_1, rank 1
6827 10:05:11.149194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 10:05:11.149330 ==
6829 10:05:11.149404 RX Vref Scan: 0
6830 10:05:11.149468
6831 10:05:11.152387 RX Vref 0 -> 0, step: 1
6832 10:05:11.152493
6833 10:05:11.155392 RX Delay -410 -> 252, step: 16
6834 10:05:11.158645 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6835 10:05:11.165309 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6836 10:05:11.168728 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6837 10:05:11.171930 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6838 10:05:11.175169 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6839 10:05:11.181989 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6840 10:05:11.185505 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6841 10:05:11.188389 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6842 10:05:11.191786 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6843 10:05:11.198514 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6844 10:05:11.202197 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6845 10:05:11.205116 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6846 10:05:11.208697 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6847 10:05:11.214804 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6848 10:05:11.218420 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6849 10:05:11.221413 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6850 10:05:11.221534 ==
6851 10:05:11.224795 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 10:05:11.231630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 10:05:11.231782 ==
6854 10:05:11.231858 DQS Delay:
6855 10:05:11.234559 DQS0 = 35, DQS1 = 35
6856 10:05:11.234684 DQM Delay:
6857 10:05:11.234795 DQM0 = 18, DQM1 = 15
6858 10:05:11.238022 DQ Delay:
6859 10:05:11.241592 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6860 10:05:11.244671 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6861 10:05:11.244825 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6862 10:05:11.248123 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6863 10:05:11.251405
6864 10:05:11.251519
6865 10:05:11.251588 ==
6866 10:05:11.254843 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 10:05:11.258224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 10:05:11.258352 ==
6869 10:05:11.258427
6870 10:05:11.258490
6871 10:05:11.261627 TX Vref Scan disable
6872 10:05:11.261734 == TX Byte 0 ==
6873 10:05:11.268086 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6874 10:05:11.271125 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6875 10:05:11.271266 == TX Byte 1 ==
6876 10:05:11.275057 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6877 10:05:11.281077 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6878 10:05:11.281268 ==
6879 10:05:11.284910 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 10:05:11.287942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 10:05:11.288099 ==
6882 10:05:11.288203
6883 10:05:11.288299
6884 10:05:11.291065 TX Vref Scan disable
6885 10:05:11.291196 == TX Byte 0 ==
6886 10:05:11.297913 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6887 10:05:11.301573 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6888 10:05:11.301721 == TX Byte 1 ==
6889 10:05:11.307734 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6890 10:05:11.311201 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6891 10:05:11.311407
6892 10:05:11.311533 [DATLAT]
6893 10:05:11.314617 Freq=400, CH1 RK1
6894 10:05:11.314729
6895 10:05:11.314801 DATLAT Default: 0xe
6896 10:05:11.317816 0, 0xFFFF, sum = 0
6897 10:05:11.317935 1, 0xFFFF, sum = 0
6898 10:05:11.321174 2, 0xFFFF, sum = 0
6899 10:05:11.321307 3, 0xFFFF, sum = 0
6900 10:05:11.324108 4, 0xFFFF, sum = 0
6901 10:05:11.324218 5, 0xFFFF, sum = 0
6902 10:05:11.327612 6, 0xFFFF, sum = 0
6903 10:05:11.327797 7, 0xFFFF, sum = 0
6904 10:05:11.331348 8, 0xFFFF, sum = 0
6905 10:05:11.334592 9, 0xFFFF, sum = 0
6906 10:05:11.334710 10, 0xFFFF, sum = 0
6907 10:05:11.337537 11, 0xFFFF, sum = 0
6908 10:05:11.337661 12, 0xFFFF, sum = 0
6909 10:05:11.340915 13, 0x0, sum = 1
6910 10:05:11.341041 14, 0x0, sum = 2
6911 10:05:11.344409 15, 0x0, sum = 3
6912 10:05:11.344526 16, 0x0, sum = 4
6913 10:05:11.344595 best_step = 14
6914 10:05:11.344658
6915 10:05:11.347589 ==
6916 10:05:11.351188 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 10:05:11.354209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 10:05:11.354374 ==
6919 10:05:11.354498 RX Vref Scan: 0
6920 10:05:11.354611
6921 10:05:11.357259 RX Vref 0 -> 0, step: 1
6922 10:05:11.357360
6923 10:05:11.360759 RX Delay -311 -> 252, step: 8
6924 10:05:11.367727 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6925 10:05:11.371362 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6926 10:05:11.374571 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6927 10:05:11.377827 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6928 10:05:11.384295 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6929 10:05:11.388105 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6930 10:05:11.391038 iDelay=217, Bit 6, Center -4 (-223 ~ 216) 440
6931 10:05:11.394660 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6932 10:05:11.401259 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6933 10:05:11.404327 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6934 10:05:11.407371 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6935 10:05:11.411189 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6936 10:05:11.417432 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6937 10:05:11.420831 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6938 10:05:11.424632 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6939 10:05:11.431078 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6940 10:05:11.431266 ==
6941 10:05:11.434177 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 10:05:11.437716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 10:05:11.437907 ==
6944 10:05:11.438035 DQS Delay:
6945 10:05:11.440720 DQS0 = 28, DQS1 = 36
6946 10:05:11.440890 DQM Delay:
6947 10:05:11.444260 DQM0 = 11, DQM1 = 15
6948 10:05:11.444454 DQ Delay:
6949 10:05:11.447585 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6950 10:05:11.450920 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =12
6951 10:05:11.454389 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
6952 10:05:11.457275 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6953 10:05:11.457460
6954 10:05:11.457587
6955 10:05:11.464128 [DQSOSCAuto] RK1, (LSB)MR18= 0xc859, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6956 10:05:11.467636 CH1 RK1: MR19=C0C, MR18=C859
6957 10:05:11.474105 CH1_RK1: MR19=0xC0C, MR18=0xC859, DQSOSC=385, MR23=63, INC=398, DEC=265
6958 10:05:11.477811 [RxdqsGatingPostProcess] freq 400
6959 10:05:11.484092 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6960 10:05:11.484280 best DQS0 dly(2T, 0.5T) = (0, 10)
6961 10:05:11.487060 best DQS1 dly(2T, 0.5T) = (0, 10)
6962 10:05:11.490740 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6963 10:05:11.494132 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6964 10:05:11.497209 best DQS0 dly(2T, 0.5T) = (0, 10)
6965 10:05:11.500624 best DQS1 dly(2T, 0.5T) = (0, 10)
6966 10:05:11.503998 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6967 10:05:11.506991 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6968 10:05:11.510724 Pre-setting of DQS Precalculation
6969 10:05:11.513863 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6970 10:05:11.523790 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6971 10:05:11.531019 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6972 10:05:11.531176
6973 10:05:11.531252
6974 10:05:11.533725 [Calibration Summary] 800 Mbps
6975 10:05:11.533829 CH 0, Rank 0
6976 10:05:11.537538 SW Impedance : PASS
6977 10:05:11.537666 DUTY Scan : NO K
6978 10:05:11.540601 ZQ Calibration : PASS
6979 10:05:11.544039 Jitter Meter : NO K
6980 10:05:11.544156 CBT Training : PASS
6981 10:05:11.547147 Write leveling : PASS
6982 10:05:11.550977 RX DQS gating : PASS
6983 10:05:11.551109 RX DQ/DQS(RDDQC) : PASS
6984 10:05:11.553833 TX DQ/DQS : PASS
6985 10:05:11.557431 RX DATLAT : PASS
6986 10:05:11.557558 RX DQ/DQS(Engine): PASS
6987 10:05:11.560501 TX OE : NO K
6988 10:05:11.560606 All Pass.
6989 10:05:11.560678
6990 10:05:11.560742 CH 0, Rank 1
6991 10:05:11.564308 SW Impedance : PASS
6992 10:05:11.567338 DUTY Scan : NO K
6993 10:05:11.567456 ZQ Calibration : PASS
6994 10:05:11.570975 Jitter Meter : NO K
6995 10:05:11.574240 CBT Training : PASS
6996 10:05:11.574366 Write leveling : NO K
6997 10:05:11.577551 RX DQS gating : PASS
6998 10:05:11.580835 RX DQ/DQS(RDDQC) : PASS
6999 10:05:11.580999 TX DQ/DQS : PASS
7000 10:05:11.583901 RX DATLAT : PASS
7001 10:05:11.587142 RX DQ/DQS(Engine): PASS
7002 10:05:11.587299 TX OE : NO K
7003 10:05:11.590923 All Pass.
7004 10:05:11.591100
7005 10:05:11.591203 CH 1, Rank 0
7006 10:05:11.594144 SW Impedance : PASS
7007 10:05:11.594328 DUTY Scan : NO K
7008 10:05:11.596962 ZQ Calibration : PASS
7009 10:05:11.600514 Jitter Meter : NO K
7010 10:05:11.600714 CBT Training : PASS
7011 10:05:11.604243 Write leveling : PASS
7012 10:05:11.607279 RX DQS gating : PASS
7013 10:05:11.607474 RX DQ/DQS(RDDQC) : PASS
7014 10:05:11.610815 TX DQ/DQS : PASS
7015 10:05:11.610986 RX DATLAT : PASS
7016 10:05:11.614271 RX DQ/DQS(Engine): PASS
7017 10:05:11.617238 TX OE : NO K
7018 10:05:11.617373 All Pass.
7019 10:05:11.617451
7020 10:05:11.617548 CH 1, Rank 1
7021 10:05:11.620233 SW Impedance : PASS
7022 10:05:11.623870 DUTY Scan : NO K
7023 10:05:11.624045 ZQ Calibration : PASS
7024 10:05:11.627000 Jitter Meter : NO K
7025 10:05:11.630483 CBT Training : PASS
7026 10:05:11.630644 Write leveling : NO K
7027 10:05:11.633863 RX DQS gating : PASS
7028 10:05:11.637217 RX DQ/DQS(RDDQC) : PASS
7029 10:05:11.637370 TX DQ/DQS : PASS
7030 10:05:11.640255 RX DATLAT : PASS
7031 10:05:11.643863 RX DQ/DQS(Engine): PASS
7032 10:05:11.644008 TX OE : NO K
7033 10:05:11.644095 All Pass.
7034 10:05:11.647428
7035 10:05:11.647556 DramC Write-DBI off
7036 10:05:11.650448 PER_BANK_REFRESH: Hybrid Mode
7037 10:05:11.650603 TX_TRACKING: ON
7038 10:05:11.660334 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7039 10:05:11.663446 [FAST_K] Save calibration result to emmc
7040 10:05:11.667172 dramc_set_vcore_voltage set vcore to 725000
7041 10:05:11.670235 Read voltage for 1600, 0
7042 10:05:11.670331 Vio18 = 0
7043 10:05:11.674016 Vcore = 725000
7044 10:05:11.674110 Vdram = 0
7045 10:05:11.674178 Vddq = 0
7046 10:05:11.676826 Vmddr = 0
7047 10:05:11.680511 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7048 10:05:11.686829 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7049 10:05:11.687000 MEM_TYPE=3, freq_sel=13
7050 10:05:11.690513 sv_algorithm_assistance_LP4_3733
7051 10:05:11.693513 ============ PULL DRAM RESETB DOWN ============
7052 10:05:11.700314 ========== PULL DRAM RESETB DOWN end =========
7053 10:05:11.703837 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7054 10:05:11.706817 ===================================
7055 10:05:11.710228 LPDDR4 DRAM CONFIGURATION
7056 10:05:11.713731 ===================================
7057 10:05:11.713832 EX_ROW_EN[0] = 0x0
7058 10:05:11.716640 EX_ROW_EN[1] = 0x0
7059 10:05:11.719998 LP4Y_EN = 0x0
7060 10:05:11.720097 WORK_FSP = 0x1
7061 10:05:11.723560 WL = 0x5
7062 10:05:11.723680 RL = 0x5
7063 10:05:11.726518 BL = 0x2
7064 10:05:11.726658 RPST = 0x0
7065 10:05:11.730236 RD_PRE = 0x0
7066 10:05:11.730365 WR_PRE = 0x1
7067 10:05:11.733205 WR_PST = 0x1
7068 10:05:11.733335 DBI_WR = 0x0
7069 10:05:11.736769 DBI_RD = 0x0
7070 10:05:11.736933 OTF = 0x1
7071 10:05:11.740009 ===================================
7072 10:05:11.743308 ===================================
7073 10:05:11.746581 ANA top config
7074 10:05:11.749830 ===================================
7075 10:05:11.749979 DLL_ASYNC_EN = 0
7076 10:05:11.753435 ALL_SLAVE_EN = 0
7077 10:05:11.756490 NEW_RANK_MODE = 1
7078 10:05:11.760117 DLL_IDLE_MODE = 1
7079 10:05:11.760246 LP45_APHY_COMB_EN = 1
7080 10:05:11.763643 TX_ODT_DIS = 0
7081 10:05:11.767012 NEW_8X_MODE = 1
7082 10:05:11.769872 ===================================
7083 10:05:11.773119 ===================================
7084 10:05:11.776637 data_rate = 3200
7085 10:05:11.780120 CKR = 1
7086 10:05:11.783594 DQ_P2S_RATIO = 8
7087 10:05:11.786473 ===================================
7088 10:05:11.786612 CA_P2S_RATIO = 8
7089 10:05:11.790245 DQ_CA_OPEN = 0
7090 10:05:11.793546 DQ_SEMI_OPEN = 0
7091 10:05:11.796394 CA_SEMI_OPEN = 0
7092 10:05:11.800114 CA_FULL_RATE = 0
7093 10:05:11.800253 DQ_CKDIV4_EN = 0
7094 10:05:11.803647 CA_CKDIV4_EN = 0
7095 10:05:11.806572 CA_PREDIV_EN = 0
7096 10:05:11.809943 PH8_DLY = 12
7097 10:05:11.813454 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7098 10:05:11.816423 DQ_AAMCK_DIV = 4
7099 10:05:11.816532 CA_AAMCK_DIV = 4
7100 10:05:11.820117 CA_ADMCK_DIV = 4
7101 10:05:11.823146 DQ_TRACK_CA_EN = 0
7102 10:05:11.826328 CA_PICK = 1600
7103 10:05:11.829764 CA_MCKIO = 1600
7104 10:05:11.833430 MCKIO_SEMI = 0
7105 10:05:11.836373 PLL_FREQ = 3068
7106 10:05:11.840257 DQ_UI_PI_RATIO = 32
7107 10:05:11.840347 CA_UI_PI_RATIO = 0
7108 10:05:11.843212 ===================================
7109 10:05:11.846313 ===================================
7110 10:05:11.849537 memory_type:LPDDR4
7111 10:05:11.853125 GP_NUM : 10
7112 10:05:11.853281 SRAM_EN : 1
7113 10:05:11.856776 MD32_EN : 0
7114 10:05:11.860046 ===================================
7115 10:05:11.863245 [ANA_INIT] >>>>>>>>>>>>>>
7116 10:05:11.866601 <<<<<< [CONFIGURE PHASE]: ANA_TX
7117 10:05:11.869623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7118 10:05:11.872740 ===================================
7119 10:05:11.872849 data_rate = 3200,PCW = 0X7600
7120 10:05:11.876408 ===================================
7121 10:05:11.879339 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7122 10:05:11.886407 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7123 10:05:11.892643 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7124 10:05:11.896305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7125 10:05:11.899299 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7126 10:05:11.902959 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7127 10:05:11.905881 [ANA_INIT] flow start
7128 10:05:11.905979 [ANA_INIT] PLL >>>>>>>>
7129 10:05:11.909200 [ANA_INIT] PLL <<<<<<<<
7130 10:05:11.912855 [ANA_INIT] MIDPI >>>>>>>>
7131 10:05:11.916106 [ANA_INIT] MIDPI <<<<<<<<
7132 10:05:11.916200 [ANA_INIT] DLL >>>>>>>>
7133 10:05:11.919519 [ANA_INIT] DLL <<<<<<<<
7134 10:05:11.923054 [ANA_INIT] flow end
7135 10:05:11.926072 ============ LP4 DIFF to SE enter ============
7136 10:05:11.929077 ============ LP4 DIFF to SE exit ============
7137 10:05:11.932767 [ANA_INIT] <<<<<<<<<<<<<
7138 10:05:11.935986 [Flow] Enable top DCM control >>>>>
7139 10:05:11.939610 [Flow] Enable top DCM control <<<<<
7140 10:05:11.942709 Enable DLL master slave shuffle
7141 10:05:11.946314 ==============================================================
7142 10:05:11.949707 Gating Mode config
7143 10:05:11.952945 ==============================================================
7144 10:05:11.956089 Config description:
7145 10:05:11.966352 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7146 10:05:11.972303 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7147 10:05:11.975871 SELPH_MODE 0: By rank 1: By Phase
7148 10:05:11.982416 ==============================================================
7149 10:05:11.986022 GAT_TRACK_EN = 1
7150 10:05:11.989062 RX_GATING_MODE = 2
7151 10:05:11.992342 RX_GATING_TRACK_MODE = 2
7152 10:05:11.995599 SELPH_MODE = 1
7153 10:05:11.999210 PICG_EARLY_EN = 1
7154 10:05:12.002443 VALID_LAT_VALUE = 1
7155 10:05:12.006296 ==============================================================
7156 10:05:12.008975 Enter into Gating configuration >>>>
7157 10:05:12.012673 Exit from Gating configuration <<<<
7158 10:05:12.015876 Enter into DVFS_PRE_config >>>>>
7159 10:05:12.025648 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7160 10:05:12.029358 Exit from DVFS_PRE_config <<<<<
7161 10:05:12.032194 Enter into PICG configuration >>>>
7162 10:05:12.036042 Exit from PICG configuration <<<<
7163 10:05:12.039241 [RX_INPUT] configuration >>>>>
7164 10:05:12.043292 [RX_INPUT] configuration <<<<<
7165 10:05:12.049216 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7166 10:05:12.052254 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7167 10:05:12.059337 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7168 10:05:12.065255 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7169 10:05:12.071958 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7170 10:05:12.078642 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7171 10:05:12.082170 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7172 10:05:12.085339 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7173 10:05:12.088603 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7174 10:05:12.095614 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7175 10:05:12.098412 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7176 10:05:12.101962 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7177 10:05:12.105011 ===================================
7178 10:05:12.108683 LPDDR4 DRAM CONFIGURATION
7179 10:05:12.111954 ===================================
7180 10:05:12.112064 EX_ROW_EN[0] = 0x0
7181 10:05:12.115241 EX_ROW_EN[1] = 0x0
7182 10:05:12.115341 LP4Y_EN = 0x0
7183 10:05:12.118974 WORK_FSP = 0x1
7184 10:05:12.121576 WL = 0x5
7185 10:05:12.121659 RL = 0x5
7186 10:05:12.125124 BL = 0x2
7187 10:05:12.125207 RPST = 0x0
7188 10:05:12.128707 RD_PRE = 0x0
7189 10:05:12.128791 WR_PRE = 0x1
7190 10:05:12.131739 WR_PST = 0x1
7191 10:05:12.131821 DBI_WR = 0x0
7192 10:05:12.135076 DBI_RD = 0x0
7193 10:05:12.135157 OTF = 0x1
7194 10:05:12.138284 ===================================
7195 10:05:12.141790 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7196 10:05:12.148369 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7197 10:05:12.151684 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7198 10:05:12.155321 ===================================
7199 10:05:12.158370 LPDDR4 DRAM CONFIGURATION
7200 10:05:12.161741 ===================================
7201 10:05:12.161823 EX_ROW_EN[0] = 0x10
7202 10:05:12.165000 EX_ROW_EN[1] = 0x0
7203 10:05:12.165082 LP4Y_EN = 0x0
7204 10:05:12.168518 WORK_FSP = 0x1
7205 10:05:12.168600 WL = 0x5
7206 10:05:12.171442 RL = 0x5
7207 10:05:12.174792 BL = 0x2
7208 10:05:12.174874 RPST = 0x0
7209 10:05:12.178216 RD_PRE = 0x0
7210 10:05:12.178296 WR_PRE = 0x1
7211 10:05:12.181652 WR_PST = 0x1
7212 10:05:12.181733 DBI_WR = 0x0
7213 10:05:12.184982 DBI_RD = 0x0
7214 10:05:12.185063 OTF = 0x1
7215 10:05:12.187850 ===================================
7216 10:05:12.194855 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7217 10:05:12.194964 ==
7218 10:05:12.197896 Dram Type= 6, Freq= 0, CH_0, rank 0
7219 10:05:12.201461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7220 10:05:12.201555 ==
7221 10:05:12.204767 [Duty_Offset_Calibration]
7222 10:05:12.207849 B0:2 B1:1 CA:1
7223 10:05:12.207935
7224 10:05:12.211518 [DutyScan_Calibration_Flow] k_type=0
7225 10:05:12.219690
7226 10:05:12.219775 ==CLK 0==
7227 10:05:12.223289 Final CLK duty delay cell = 0
7228 10:05:12.226737 [0] MAX Duty = 5156%(X100), DQS PI = 22
7229 10:05:12.230034 [0] MIN Duty = 4907%(X100), DQS PI = 0
7230 10:05:12.230118 [0] AVG Duty = 5031%(X100)
7231 10:05:12.233007
7232 10:05:12.233093 CH0 CLK Duty spec in!! Max-Min= 249%
7233 10:05:12.239618 [DutyScan_Calibration_Flow] ====Done====
7234 10:05:12.239704
7235 10:05:12.243076 [DutyScan_Calibration_Flow] k_type=1
7236 10:05:12.258689
7237 10:05:12.258856 ==DQS 0 ==
7238 10:05:12.262402 Final DQS duty delay cell = -4
7239 10:05:12.265300 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7240 10:05:12.268925 [-4] MIN Duty = 4688%(X100), DQS PI = 0
7241 10:05:12.271913 [-4] AVG Duty = 4906%(X100)
7242 10:05:12.272016
7243 10:05:12.272096 ==DQS 1 ==
7244 10:05:12.275594 Final DQS duty delay cell = 0
7245 10:05:12.279175 [0] MAX Duty = 5187%(X100), DQS PI = 20
7246 10:05:12.282520 [0] MIN Duty = 5031%(X100), DQS PI = 52
7247 10:05:12.285383 [0] AVG Duty = 5109%(X100)
7248 10:05:12.285469
7249 10:05:12.288765 CH0 DQS 0 Duty spec in!! Max-Min= 437%
7250 10:05:12.288884
7251 10:05:12.292345 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7252 10:05:12.295545 [DutyScan_Calibration_Flow] ====Done====
7253 10:05:12.295630
7254 10:05:12.298688 [DutyScan_Calibration_Flow] k_type=3
7255 10:05:12.315439
7256 10:05:12.315540 ==DQM 0 ==
7257 10:05:12.319057 Final DQM duty delay cell = 0
7258 10:05:12.322245 [0] MAX Duty = 5218%(X100), DQS PI = 34
7259 10:05:12.326008 [0] MIN Duty = 4876%(X100), DQS PI = 60
7260 10:05:12.328947 [0] AVG Duty = 5047%(X100)
7261 10:05:12.329040
7262 10:05:12.329126 ==DQM 1 ==
7263 10:05:12.331877 Final DQM duty delay cell = -4
7264 10:05:12.335434 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7265 10:05:12.339051 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7266 10:05:12.342132 [-4] AVG Duty = 4906%(X100)
7267 10:05:12.342219
7268 10:05:12.345415 CH0 DQM 0 Duty spec in!! Max-Min= 342%
7269 10:05:12.345525
7270 10:05:12.349001 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7271 10:05:12.351860 [DutyScan_Calibration_Flow] ====Done====
7272 10:05:12.351945
7273 10:05:12.355326 [DutyScan_Calibration_Flow] k_type=2
7274 10:05:12.373237
7275 10:05:12.373373 ==DQ 0 ==
7276 10:05:12.376219 Final DQ duty delay cell = 0
7277 10:05:12.379639 [0] MAX Duty = 5062%(X100), DQS PI = 26
7278 10:05:12.383196 [0] MIN Duty = 4907%(X100), DQS PI = 0
7279 10:05:12.383303 [0] AVG Duty = 4984%(X100)
7280 10:05:12.383397
7281 10:05:12.386562 ==DQ 1 ==
7282 10:05:12.389936 Final DQ duty delay cell = 0
7283 10:05:12.392792 [0] MAX Duty = 5156%(X100), DQS PI = 22
7284 10:05:12.396249 [0] MIN Duty = 4938%(X100), DQS PI = 34
7285 10:05:12.396358 [0] AVG Duty = 5047%(X100)
7286 10:05:12.396454
7287 10:05:12.399752 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7288 10:05:12.402851
7289 10:05:12.406400 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7290 10:05:12.409760 [DutyScan_Calibration_Flow] ====Done====
7291 10:05:12.409843 ==
7292 10:05:12.413021 Dram Type= 6, Freq= 0, CH_1, rank 0
7293 10:05:12.415982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7294 10:05:12.416107 ==
7295 10:05:12.419721 [Duty_Offset_Calibration]
7296 10:05:12.419808 B0:1 B1:0 CA:0
7297 10:05:12.419873
7298 10:05:12.422704 [DutyScan_Calibration_Flow] k_type=0
7299 10:05:12.432559
7300 10:05:12.432679 ==CLK 0==
7301 10:05:12.435555 Final CLK duty delay cell = -4
7302 10:05:12.439388 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7303 10:05:12.442643 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7304 10:05:12.445910 [-4] AVG Duty = 4922%(X100)
7305 10:05:12.446012
7306 10:05:12.448925 CH1 CLK Duty spec in!! Max-Min= 156%
7307 10:05:12.452235 [DutyScan_Calibration_Flow] ====Done====
7308 10:05:12.452384
7309 10:05:12.455825 [DutyScan_Calibration_Flow] k_type=1
7310 10:05:12.472566
7311 10:05:12.472683 ==DQS 0 ==
7312 10:05:12.475577 Final DQS duty delay cell = 0
7313 10:05:12.479311 [0] MAX Duty = 5094%(X100), DQS PI = 16
7314 10:05:12.482337 [0] MIN Duty = 4844%(X100), DQS PI = 50
7315 10:05:12.485516 [0] AVG Duty = 4969%(X100)
7316 10:05:12.485618
7317 10:05:12.485717 ==DQS 1 ==
7318 10:05:12.489332 Final DQS duty delay cell = 0
7319 10:05:12.492281 [0] MAX Duty = 5249%(X100), DQS PI = 16
7320 10:05:12.495811 [0] MIN Duty = 4938%(X100), DQS PI = 8
7321 10:05:12.495942 [0] AVG Duty = 5093%(X100)
7322 10:05:12.499312
7323 10:05:12.502279 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7324 10:05:12.502415
7325 10:05:12.506084 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7326 10:05:12.508985 [DutyScan_Calibration_Flow] ====Done====
7327 10:05:12.509115
7328 10:05:12.512486 [DutyScan_Calibration_Flow] k_type=3
7329 10:05:12.529594
7330 10:05:12.529691 ==DQM 0 ==
7331 10:05:12.532475 Final DQM duty delay cell = 0
7332 10:05:12.536067 [0] MAX Duty = 5187%(X100), DQS PI = 8
7333 10:05:12.539351 [0] MIN Duty = 4969%(X100), DQS PI = 48
7334 10:05:12.539434 [0] AVG Duty = 5078%(X100)
7335 10:05:12.543000
7336 10:05:12.543082 ==DQM 1 ==
7337 10:05:12.545939 Final DQM duty delay cell = 0
7338 10:05:12.549482 [0] MAX Duty = 5062%(X100), DQS PI = 14
7339 10:05:12.552530 [0] MIN Duty = 4907%(X100), DQS PI = 52
7340 10:05:12.552626 [0] AVG Duty = 4984%(X100)
7341 10:05:12.556126
7342 10:05:12.560066 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7343 10:05:12.560151
7344 10:05:12.562992 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7345 10:05:12.565811 [DutyScan_Calibration_Flow] ====Done====
7346 10:05:12.565895
7347 10:05:12.569190 [DutyScan_Calibration_Flow] k_type=2
7348 10:05:12.585664
7349 10:05:12.585760 ==DQ 0 ==
7350 10:05:12.588488 Final DQ duty delay cell = -4
7351 10:05:12.592005 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7352 10:05:12.595217 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7353 10:05:12.598749 [-4] AVG Duty = 4968%(X100)
7354 10:05:12.598830
7355 10:05:12.598895 ==DQ 1 ==
7356 10:05:12.602218 Final DQ duty delay cell = 0
7357 10:05:12.605134 [0] MAX Duty = 5124%(X100), DQS PI = 18
7358 10:05:12.608479 [0] MIN Duty = 4938%(X100), DQS PI = 8
7359 10:05:12.611994 [0] AVG Duty = 5031%(X100)
7360 10:05:12.612075
7361 10:05:12.615119 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7362 10:05:12.615201
7363 10:05:12.618458 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7364 10:05:12.621796 [DutyScan_Calibration_Flow] ====Done====
7365 10:05:12.625217 nWR fixed to 30
7366 10:05:12.628553 [ModeRegInit_LP4] CH0 RK0
7367 10:05:12.628634 [ModeRegInit_LP4] CH0 RK1
7368 10:05:12.631470 [ModeRegInit_LP4] CH1 RK0
7369 10:05:12.635444 [ModeRegInit_LP4] CH1 RK1
7370 10:05:12.635525 match AC timing 5
7371 10:05:12.641284 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7372 10:05:12.645022 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7373 10:05:12.648054 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7374 10:05:12.654579 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7375 10:05:12.658238 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7376 10:05:12.658334 [MiockJmeterHQA]
7377 10:05:12.658402
7378 10:05:12.661144 [DramcMiockJmeter] u1RxGatingPI = 0
7379 10:05:12.664676 0 : 4363, 4137
7380 10:05:12.664760 4 : 4252, 4027
7381 10:05:12.667939 8 : 4252, 4027
7382 10:05:12.668022 12 : 4370, 4143
7383 10:05:12.671359 16 : 4257, 4029
7384 10:05:12.671442 20 : 4253, 4027
7385 10:05:12.671508 24 : 4253, 4027
7386 10:05:12.674615 28 : 4253, 4027
7387 10:05:12.674697 32 : 4366, 4140
7388 10:05:12.677769 36 : 4252, 4027
7389 10:05:12.677852 40 : 4255, 4029
7390 10:05:12.681402 44 : 4252, 4027
7391 10:05:12.681487 48 : 4363, 4137
7392 10:05:12.684635 52 : 4255, 4030
7393 10:05:12.684718 56 : 4363, 4137
7394 10:05:12.684784 60 : 4253, 4027
7395 10:05:12.688016 64 : 4253, 4026
7396 10:05:12.688126 68 : 4250, 4027
7397 10:05:12.691030 72 : 4253, 4029
7398 10:05:12.691113 76 : 4360, 4137
7399 10:05:12.694437 80 : 4250, 4027
7400 10:05:12.694520 84 : 4360, 4137
7401 10:05:12.694588 88 : 4250, 64
7402 10:05:12.697905 92 : 4250, 0
7403 10:05:12.697988 96 : 4252, 0
7404 10:05:12.700904 100 : 4250, 0
7405 10:05:12.700986 104 : 4250, 0
7406 10:05:12.701052 108 : 4250, 0
7407 10:05:12.704546 112 : 4253, 0
7408 10:05:12.704628 116 : 4360, 0
7409 10:05:12.708227 120 : 4250, 0
7410 10:05:12.708310 124 : 4250, 0
7411 10:05:12.708376 128 : 4361, 0
7412 10:05:12.711150 132 : 4361, 0
7413 10:05:12.711233 136 : 4250, 0
7414 10:05:12.714250 140 : 4250, 0
7415 10:05:12.714333 144 : 4250, 0
7416 10:05:12.714398 148 : 4250, 0
7417 10:05:12.717543 152 : 4250, 0
7418 10:05:12.717627 156 : 4250, 0
7419 10:05:12.717693 160 : 4250, 0
7420 10:05:12.720993 164 : 4252, 0
7421 10:05:12.721075 168 : 4250, 0
7422 10:05:12.724626 172 : 4250, 0
7423 10:05:12.724711 176 : 4253, 0
7424 10:05:12.724778 180 : 4250, 0
7425 10:05:12.727993 184 : 4361, 0
7426 10:05:12.728076 188 : 4361, 0
7427 10:05:12.731149 192 : 4250, 0
7428 10:05:12.731231 196 : 4360, 0
7429 10:05:12.731298 200 : 4361, 0
7430 10:05:12.734196 204 : 4250, 1276
7431 10:05:12.734279 208 : 4360, 4117
7432 10:05:12.737453 212 : 4250, 4027
7433 10:05:12.737536 216 : 4252, 4027
7434 10:05:12.740737 220 : 4250, 4027
7435 10:05:12.740846 224 : 4253, 4029
7436 10:05:12.744019 228 : 4250, 4026
7437 10:05:12.744101 232 : 4250, 4027
7438 10:05:12.747564 236 : 4250, 4027
7439 10:05:12.747648 240 : 4253, 4029
7440 10:05:12.747714 244 : 4250, 4026
7441 10:05:12.750694 248 : 4360, 4137
7442 10:05:12.750777 252 : 4360, 4137
7443 10:05:12.754478 256 : 4250, 4027
7444 10:05:12.754560 260 : 4363, 4140
7445 10:05:12.757303 264 : 4360, 4138
7446 10:05:12.757385 268 : 4252, 4027
7447 10:05:12.761004 272 : 4250, 4027
7448 10:05:12.761086 276 : 4253, 4029
7449 10:05:12.764006 280 : 4250, 4026
7450 10:05:12.764088 284 : 4250, 4027
7451 10:05:12.767572 288 : 4250, 4027
7452 10:05:12.767656 292 : 4253, 4029
7453 10:05:12.771142 296 : 4250, 4026
7454 10:05:12.771225 300 : 4361, 4138
7455 10:05:12.774494 304 : 4360, 4138
7456 10:05:12.774578 308 : 4249, 3959
7457 10:05:12.774644 312 : 4364, 2026
7458 10:05:12.777243
7459 10:05:12.777348 MIOCK jitter meter ch=0
7460 10:05:12.777435
7461 10:05:12.780524 1T = (312-88) = 224 dly cells
7462 10:05:12.787400 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7463 10:05:12.787546 ==
7464 10:05:12.790369 Dram Type= 6, Freq= 0, CH_0, rank 0
7465 10:05:12.793887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7466 10:05:12.793973 ==
7467 10:05:12.800508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7468 10:05:12.804035 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7469 10:05:12.807357 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7470 10:05:12.814101 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7471 10:05:12.822857 [CA 0] Center 42 (12~73) winsize 62
7472 10:05:12.826415 [CA 1] Center 42 (12~73) winsize 62
7473 10:05:12.829541 [CA 2] Center 37 (8~67) winsize 60
7474 10:05:12.832590 [CA 3] Center 37 (7~67) winsize 61
7475 10:05:12.835771 [CA 4] Center 36 (6~66) winsize 61
7476 10:05:12.839225 [CA 5] Center 35 (6~64) winsize 59
7477 10:05:12.839310
7478 10:05:12.843087 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7479 10:05:12.843187
7480 10:05:12.846003 [CATrainingPosCal] consider 1 rank data
7481 10:05:12.849416 u2DelayCellTimex100 = 290/100 ps
7482 10:05:12.852901 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7483 10:05:12.859097 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7484 10:05:12.862676 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7485 10:05:12.866474 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7486 10:05:12.869723 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7487 10:05:12.873025 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7488 10:05:12.873108
7489 10:05:12.876480 CA PerBit enable=1, Macro0, CA PI delay=35
7490 10:05:12.876562
7491 10:05:12.879499 [CBTSetCACLKResult] CA Dly = 35
7492 10:05:12.879583 CS Dly: 9 (0~40)
7493 10:05:12.886240 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7494 10:05:12.889566 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7495 10:05:12.889650 ==
7496 10:05:12.893219 Dram Type= 6, Freq= 0, CH_0, rank 1
7497 10:05:12.896204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7498 10:05:12.896287 ==
7499 10:05:12.902773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7500 10:05:12.906470 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7501 10:05:12.912937 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7502 10:05:12.916126 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7503 10:05:12.926253 [CA 0] Center 42 (12~73) winsize 62
7504 10:05:12.929810 [CA 1] Center 42 (12~73) winsize 62
7505 10:05:12.933099 [CA 2] Center 38 (8~68) winsize 61
7506 10:05:12.936035 [CA 3] Center 37 (8~67) winsize 60
7507 10:05:12.939602 [CA 4] Center 36 (6~66) winsize 61
7508 10:05:12.942666 [CA 5] Center 35 (5~65) winsize 61
7509 10:05:12.942764
7510 10:05:12.946103 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7511 10:05:12.946186
7512 10:05:12.949710 [CATrainingPosCal] consider 2 rank data
7513 10:05:12.952964 u2DelayCellTimex100 = 290/100 ps
7514 10:05:12.955928 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7515 10:05:12.962973 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7516 10:05:12.965855 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7517 10:05:12.969475 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7518 10:05:12.972509 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7519 10:05:12.975945 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7520 10:05:12.976028
7521 10:05:12.979639 CA PerBit enable=1, Macro0, CA PI delay=35
7522 10:05:12.979721
7523 10:05:12.982629 [CBTSetCACLKResult] CA Dly = 35
7524 10:05:12.985661 CS Dly: 10 (0~42)
7525 10:05:12.989389 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7526 10:05:12.992643 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7527 10:05:12.992725
7528 10:05:12.996202 ----->DramcWriteLeveling(PI) begin...
7529 10:05:12.996286 ==
7530 10:05:12.999537 Dram Type= 6, Freq= 0, CH_0, rank 0
7531 10:05:13.002667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7532 10:05:13.005762 ==
7533 10:05:13.005875 Write leveling (Byte 0): 37 => 37
7534 10:05:13.009723 Write leveling (Byte 1): 29 => 29
7535 10:05:13.012839 DramcWriteLeveling(PI) end<-----
7536 10:05:13.012951
7537 10:05:13.013052 ==
7538 10:05:13.016123 Dram Type= 6, Freq= 0, CH_0, rank 0
7539 10:05:13.022391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7540 10:05:13.022510 ==
7541 10:05:13.022615 [Gating] SW mode calibration
7542 10:05:13.032428 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7543 10:05:13.036242 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7544 10:05:13.042170 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7545 10:05:13.045662 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7546 10:05:13.049256 1 4 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7547 10:05:13.052252 1 4 12 | B1->B0 | 2323 3635 | 0 1 | (0 0) (0 0)
7548 10:05:13.059032 1 4 16 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
7549 10:05:13.062861 1 4 20 | B1->B0 | 3333 3737 | 0 0 | (0 0) (0 0)
7550 10:05:13.065796 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7551 10:05:13.072144 1 4 28 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7552 10:05:13.075631 1 5 0 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7553 10:05:13.079138 1 5 4 | B1->B0 | 3434 3534 | 1 1 | (1 1) (1 1)
7554 10:05:13.085747 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7555 10:05:13.088865 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7556 10:05:13.092528 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
7557 10:05:13.099252 1 5 20 | B1->B0 | 2a2a 2828 | 1 0 | (1 0) (0 0)
7558 10:05:13.101952 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 10:05:13.105458 1 5 28 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7560 10:05:13.112154 1 6 0 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7561 10:05:13.115554 1 6 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7562 10:05:13.118846 1 6 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7563 10:05:13.125542 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7564 10:05:13.129198 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7565 10:05:13.132478 1 6 20 | B1->B0 | 4444 4645 | 0 1 | (0 0) (1 1)
7566 10:05:13.138986 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 10:05:13.142542 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 10:05:13.145520 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 10:05:13.152262 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 10:05:13.155844 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 10:05:13.159178 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7572 10:05:13.162584 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7573 10:05:13.169023 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 10:05:13.172237 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 10:05:13.175567 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 10:05:13.182589 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 10:05:13.185399 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 10:05:13.189143 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 10:05:13.195488 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 10:05:13.198797 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 10:05:13.202579 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 10:05:13.209173 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 10:05:13.212117 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 10:05:13.215644 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 10:05:13.222177 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 10:05:13.225620 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7587 10:05:13.229013 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7588 10:05:13.235836 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7589 10:05:13.235923 Total UI for P1: 0, mck2ui 16
7590 10:05:13.241981 best dqsien dly found for B0: ( 1, 9, 10)
7591 10:05:13.245336 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7592 10:05:13.248726 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7593 10:05:13.252160 Total UI for P1: 0, mck2ui 16
7594 10:05:13.255307 best dqsien dly found for B1: ( 1, 9, 18)
7595 10:05:13.258826 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7596 10:05:13.261812 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7597 10:05:13.261946
7598 10:05:13.268565 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7599 10:05:13.272189 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7600 10:05:13.275303 [Gating] SW calibration Done
7601 10:05:13.275395 ==
7602 10:05:13.278207 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 10:05:13.281619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 10:05:13.281731 ==
7605 10:05:13.281832 RX Vref Scan: 0
7606 10:05:13.281927
7607 10:05:13.285469 RX Vref 0 -> 0, step: 1
7608 10:05:13.285583
7609 10:05:13.288588 RX Delay 0 -> 252, step: 8
7610 10:05:13.291487 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7611 10:05:13.295502 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7612 10:05:13.298894 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7613 10:05:13.305356 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7614 10:05:13.308616 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7615 10:05:13.311477 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7616 10:05:13.315668 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7617 10:05:13.318348 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7618 10:05:13.325188 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7619 10:05:13.328196 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7620 10:05:13.331837 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7621 10:05:13.335051 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7622 10:05:13.338296 iDelay=200, Bit 12, Center 135 (88 ~ 183) 96
7623 10:05:13.345029 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7624 10:05:13.348211 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7625 10:05:13.352020 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7626 10:05:13.352125 ==
7627 10:05:13.354990 Dram Type= 6, Freq= 0, CH_0, rank 0
7628 10:05:13.358827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7629 10:05:13.358911 ==
7630 10:05:13.361522 DQS Delay:
7631 10:05:13.361606 DQS0 = 0, DQS1 = 0
7632 10:05:13.365424 DQM Delay:
7633 10:05:13.365506 DQM0 = 136, DQM1 = 129
7634 10:05:13.365571 DQ Delay:
7635 10:05:13.371474 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7636 10:05:13.375249 DQ4 =135, DQ5 =123, DQ6 =147, DQ7 =143
7637 10:05:13.378183 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7638 10:05:13.381771 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7639 10:05:13.381854
7640 10:05:13.381920
7641 10:05:13.381980 ==
7642 10:05:13.384724 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 10:05:13.388465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 10:05:13.388548 ==
7645 10:05:13.388614
7646 10:05:13.388675
7647 10:05:13.391187 TX Vref Scan disable
7648 10:05:13.394521 == TX Byte 0 ==
7649 10:05:13.397797 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7650 10:05:13.401548 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7651 10:05:13.404442 == TX Byte 1 ==
7652 10:05:13.407753 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7653 10:05:13.411370 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7654 10:05:13.411464 ==
7655 10:05:13.414932 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 10:05:13.418011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 10:05:13.421188 ==
7658 10:05:13.433273
7659 10:05:13.436567 TX Vref early break, caculate TX vref
7660 10:05:13.439920 TX Vref=16, minBit 0, minWin=22, winSum=376
7661 10:05:13.443035 TX Vref=18, minBit 0, minWin=23, winSum=384
7662 10:05:13.446627 TX Vref=20, minBit 0, minWin=23, winSum=396
7663 10:05:13.450179 TX Vref=22, minBit 2, minWin=24, winSum=406
7664 10:05:13.452978 TX Vref=24, minBit 4, minWin=24, winSum=416
7665 10:05:13.459851 TX Vref=26, minBit 2, minWin=25, winSum=424
7666 10:05:13.463457 TX Vref=28, minBit 2, minWin=25, winSum=422
7667 10:05:13.466866 TX Vref=30, minBit 0, minWin=24, winSum=407
7668 10:05:13.469933 TX Vref=32, minBit 0, minWin=24, winSum=403
7669 10:05:13.473012 TX Vref=34, minBit 1, minWin=23, winSum=396
7670 10:05:13.479846 [TxChooseVref] Worse bit 2, Min win 25, Win sum 424, Final Vref 26
7671 10:05:13.479927
7672 10:05:13.483263 Final TX Range 0 Vref 26
7673 10:05:13.483347
7674 10:05:13.483413 ==
7675 10:05:13.486891 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 10:05:13.489925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 10:05:13.490000 ==
7678 10:05:13.490062
7679 10:05:13.490123
7680 10:05:13.493457 TX Vref Scan disable
7681 10:05:13.500071 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7682 10:05:13.500154 == TX Byte 0 ==
7683 10:05:13.503344 u2DelayCellOfst[0]=13 cells (4 PI)
7684 10:05:13.506514 u2DelayCellOfst[1]=16 cells (5 PI)
7685 10:05:13.510211 u2DelayCellOfst[2]=10 cells (3 PI)
7686 10:05:13.513570 u2DelayCellOfst[3]=10 cells (3 PI)
7687 10:05:13.516559 u2DelayCellOfst[4]=10 cells (3 PI)
7688 10:05:13.520138 u2DelayCellOfst[5]=0 cells (0 PI)
7689 10:05:13.520246 u2DelayCellOfst[6]=16 cells (5 PI)
7690 10:05:13.523024 u2DelayCellOfst[7]=20 cells (6 PI)
7691 10:05:13.529823 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7692 10:05:13.533020 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7693 10:05:13.533128 == TX Byte 1 ==
7694 10:05:13.536857 u2DelayCellOfst[8]=0 cells (0 PI)
7695 10:05:13.539962 u2DelayCellOfst[9]=0 cells (0 PI)
7696 10:05:13.543663 u2DelayCellOfst[10]=6 cells (2 PI)
7697 10:05:13.546500 u2DelayCellOfst[11]=6 cells (2 PI)
7698 10:05:13.549595 u2DelayCellOfst[12]=10 cells (3 PI)
7699 10:05:13.553170 u2DelayCellOfst[13]=10 cells (3 PI)
7700 10:05:13.556587 u2DelayCellOfst[14]=13 cells (4 PI)
7701 10:05:13.559833 u2DelayCellOfst[15]=10 cells (3 PI)
7702 10:05:13.562942 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7703 10:05:13.566972 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7704 10:05:13.569580 DramC Write-DBI on
7705 10:05:13.569662 ==
7706 10:05:13.573336 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 10:05:13.576336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 10:05:13.576418 ==
7709 10:05:13.576484
7710 10:05:13.579477
7711 10:05:13.579559 TX Vref Scan disable
7712 10:05:13.582854 == TX Byte 0 ==
7713 10:05:13.586598 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7714 10:05:13.589470 == TX Byte 1 ==
7715 10:05:13.593200 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7716 10:05:13.593282 DramC Write-DBI off
7717 10:05:13.593347
7718 10:05:13.596594 [DATLAT]
7719 10:05:13.596676 Freq=1600, CH0 RK0
7720 10:05:13.596742
7721 10:05:13.599933 DATLAT Default: 0xf
7722 10:05:13.600014 0, 0xFFFF, sum = 0
7723 10:05:13.603134 1, 0xFFFF, sum = 0
7724 10:05:13.603217 2, 0xFFFF, sum = 0
7725 10:05:13.606058 3, 0xFFFF, sum = 0
7726 10:05:13.606141 4, 0xFFFF, sum = 0
7727 10:05:13.609613 5, 0xFFFF, sum = 0
7728 10:05:13.613056 6, 0xFFFF, sum = 0
7729 10:05:13.613139 7, 0xFFFF, sum = 0
7730 10:05:13.617064 8, 0xFFFF, sum = 0
7731 10:05:13.617174 9, 0xFFFF, sum = 0
7732 10:05:13.619751 10, 0xFFFF, sum = 0
7733 10:05:13.619834 11, 0xFFFF, sum = 0
7734 10:05:13.623213 12, 0xFFFF, sum = 0
7735 10:05:13.623296 13, 0xFFFF, sum = 0
7736 10:05:13.626588 14, 0x0, sum = 1
7737 10:05:13.626671 15, 0x0, sum = 2
7738 10:05:13.629741 16, 0x0, sum = 3
7739 10:05:13.629824 17, 0x0, sum = 4
7740 10:05:13.632896 best_step = 15
7741 10:05:13.632978
7742 10:05:13.633044 ==
7743 10:05:13.636201 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 10:05:13.639541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 10:05:13.639656 ==
7746 10:05:13.639782 RX Vref Scan: 1
7747 10:05:13.643018
7748 10:05:13.643099 Set Vref Range= 24 -> 127
7749 10:05:13.643164
7750 10:05:13.646587 RX Vref 24 -> 127, step: 1
7751 10:05:13.646669
7752 10:05:13.649309 RX Delay 19 -> 252, step: 4
7753 10:05:13.649407
7754 10:05:13.653045 Set Vref, RX VrefLevel [Byte0]: 24
7755 10:05:13.656143 [Byte1]: 24
7756 10:05:13.656225
7757 10:05:13.659399 Set Vref, RX VrefLevel [Byte0]: 25
7758 10:05:13.662598 [Byte1]: 25
7759 10:05:13.662680
7760 10:05:13.665980 Set Vref, RX VrefLevel [Byte0]: 26
7761 10:05:13.668756 [Byte1]: 26
7762 10:05:13.672848
7763 10:05:13.672944 Set Vref, RX VrefLevel [Byte0]: 27
7764 10:05:13.676109 [Byte1]: 27
7765 10:05:13.680365
7766 10:05:13.680447 Set Vref, RX VrefLevel [Byte0]: 28
7767 10:05:13.683969 [Byte1]: 28
7768 10:05:13.688042
7769 10:05:13.688125 Set Vref, RX VrefLevel [Byte0]: 29
7770 10:05:13.691830 [Byte1]: 29
7771 10:05:13.696086
7772 10:05:13.696172 Set Vref, RX VrefLevel [Byte0]: 30
7773 10:05:13.699045 [Byte1]: 30
7774 10:05:13.703221
7775 10:05:13.703308 Set Vref, RX VrefLevel [Byte0]: 31
7776 10:05:13.706556 [Byte1]: 31
7777 10:05:13.711156
7778 10:05:13.711247 Set Vref, RX VrefLevel [Byte0]: 32
7779 10:05:13.714753 [Byte1]: 32
7780 10:05:13.718252
7781 10:05:13.718379 Set Vref, RX VrefLevel [Byte0]: 33
7782 10:05:13.721579 [Byte1]: 33
7783 10:05:13.725982
7784 10:05:13.726074 Set Vref, RX VrefLevel [Byte0]: 34
7785 10:05:13.729416 [Byte1]: 34
7786 10:05:13.733478
7787 10:05:13.733561 Set Vref, RX VrefLevel [Byte0]: 35
7788 10:05:13.737456 [Byte1]: 35
7789 10:05:13.740985
7790 10:05:13.741068 Set Vref, RX VrefLevel [Byte0]: 36
7791 10:05:13.744422 [Byte1]: 36
7792 10:05:13.748991
7793 10:05:13.749089 Set Vref, RX VrefLevel [Byte0]: 37
7794 10:05:13.752290 [Byte1]: 37
7795 10:05:13.756525
7796 10:05:13.756607 Set Vref, RX VrefLevel [Byte0]: 38
7797 10:05:13.759583 [Byte1]: 38
7798 10:05:13.764050
7799 10:05:13.764131 Set Vref, RX VrefLevel [Byte0]: 39
7800 10:05:13.767282 [Byte1]: 39
7801 10:05:13.772019
7802 10:05:13.772100 Set Vref, RX VrefLevel [Byte0]: 40
7803 10:05:13.774600 [Byte1]: 40
7804 10:05:13.779345
7805 10:05:13.779427 Set Vref, RX VrefLevel [Byte0]: 41
7806 10:05:13.782650 [Byte1]: 41
7807 10:05:13.786500
7808 10:05:13.786598 Set Vref, RX VrefLevel [Byte0]: 42
7809 10:05:13.789951 [Byte1]: 42
7810 10:05:13.794455
7811 10:05:13.794537 Set Vref, RX VrefLevel [Byte0]: 43
7812 10:05:13.797600 [Byte1]: 43
7813 10:05:13.801748
7814 10:05:13.801829 Set Vref, RX VrefLevel [Byte0]: 44
7815 10:05:13.805521 [Byte1]: 44
7816 10:05:13.809738
7817 10:05:13.809820 Set Vref, RX VrefLevel [Byte0]: 45
7818 10:05:13.812720 [Byte1]: 45
7819 10:05:13.816746
7820 10:05:13.816853 Set Vref, RX VrefLevel [Byte0]: 46
7821 10:05:13.820356 [Byte1]: 46
7822 10:05:13.824606
7823 10:05:13.824687 Set Vref, RX VrefLevel [Byte0]: 47
7824 10:05:13.828160 [Byte1]: 47
7825 10:05:13.832035
7826 10:05:13.832117 Set Vref, RX VrefLevel [Byte0]: 48
7827 10:05:13.835502 [Byte1]: 48
7828 10:05:13.839588
7829 10:05:13.839670 Set Vref, RX VrefLevel [Byte0]: 49
7830 10:05:13.842815 [Byte1]: 49
7831 10:05:13.847540
7832 10:05:13.847622 Set Vref, RX VrefLevel [Byte0]: 50
7833 10:05:13.850788 [Byte1]: 50
7834 10:05:13.854853
7835 10:05:13.854989 Set Vref, RX VrefLevel [Byte0]: 51
7836 10:05:13.858223 [Byte1]: 51
7837 10:05:13.862130
7838 10:05:13.862266 Set Vref, RX VrefLevel [Byte0]: 52
7839 10:05:13.866036 [Byte1]: 52
7840 10:05:13.870085
7841 10:05:13.870192 Set Vref, RX VrefLevel [Byte0]: 53
7842 10:05:13.873087 [Byte1]: 53
7843 10:05:13.877726
7844 10:05:13.877835 Set Vref, RX VrefLevel [Byte0]: 54
7845 10:05:13.880779 [Byte1]: 54
7846 10:05:13.884791
7847 10:05:13.884896 Set Vref, RX VrefLevel [Byte0]: 55
7848 10:05:13.888406 [Byte1]: 55
7849 10:05:13.892675
7850 10:05:13.892806 Set Vref, RX VrefLevel [Byte0]: 56
7851 10:05:13.896247 [Byte1]: 56
7852 10:05:13.900389
7853 10:05:13.900499 Set Vref, RX VrefLevel [Byte0]: 57
7854 10:05:13.903549 [Byte1]: 57
7855 10:05:13.907714
7856 10:05:13.907822 Set Vref, RX VrefLevel [Byte0]: 58
7857 10:05:13.911325 [Byte1]: 58
7858 10:05:13.915649
7859 10:05:13.915757 Set Vref, RX VrefLevel [Byte0]: 59
7860 10:05:13.918684 [Byte1]: 59
7861 10:05:13.922810
7862 10:05:13.922919 Set Vref, RX VrefLevel [Byte0]: 60
7863 10:05:13.926347 [Byte1]: 60
7864 10:05:13.930619
7865 10:05:13.930732 Set Vref, RX VrefLevel [Byte0]: 61
7866 10:05:13.933845 [Byte1]: 61
7867 10:05:13.938095
7868 10:05:13.938193 Set Vref, RX VrefLevel [Byte0]: 62
7869 10:05:13.941151 [Byte1]: 62
7870 10:05:13.945579
7871 10:05:13.945663 Set Vref, RX VrefLevel [Byte0]: 63
7872 10:05:13.949122 [Byte1]: 63
7873 10:05:13.953412
7874 10:05:13.953495 Set Vref, RX VrefLevel [Byte0]: 64
7875 10:05:13.956422 [Byte1]: 64
7876 10:05:13.960688
7877 10:05:13.960786 Set Vref, RX VrefLevel [Byte0]: 65
7878 10:05:13.964115 [Byte1]: 65
7879 10:05:13.968140
7880 10:05:13.968222 Set Vref, RX VrefLevel [Byte0]: 66
7881 10:05:13.971853 [Byte1]: 66
7882 10:05:13.975992
7883 10:05:13.976074 Set Vref, RX VrefLevel [Byte0]: 67
7884 10:05:13.979443 [Byte1]: 67
7885 10:05:13.983319
7886 10:05:13.983401 Set Vref, RX VrefLevel [Byte0]: 68
7887 10:05:13.987134 [Byte1]: 68
7888 10:05:13.991030
7889 10:05:13.991143 Set Vref, RX VrefLevel [Byte0]: 69
7890 10:05:13.994487 [Byte1]: 69
7891 10:05:13.998712
7892 10:05:13.998804 Set Vref, RX VrefLevel [Byte0]: 70
7893 10:05:14.002279 [Byte1]: 70
7894 10:05:14.006438
7895 10:05:14.006529 Set Vref, RX VrefLevel [Byte0]: 71
7896 10:05:14.009480 [Byte1]: 71
7897 10:05:14.013998
7898 10:05:14.014128 Set Vref, RX VrefLevel [Byte0]: 72
7899 10:05:14.017481 [Byte1]: 72
7900 10:05:14.021564
7901 10:05:14.024843 Set Vref, RX VrefLevel [Byte0]: 73
7902 10:05:14.024957 [Byte1]: 73
7903 10:05:14.028704
7904 10:05:14.028822 Set Vref, RX VrefLevel [Byte0]: 74
7905 10:05:14.032504 [Byte1]: 74
7906 10:05:14.036517
7907 10:05:14.036600 Set Vref, RX VrefLevel [Byte0]: 75
7908 10:05:14.039939 [Byte1]: 75
7909 10:05:14.044420
7910 10:05:14.044536 Set Vref, RX VrefLevel [Byte0]: 76
7911 10:05:14.047244 [Byte1]: 76
7912 10:05:14.051733
7913 10:05:14.051830 Set Vref, RX VrefLevel [Byte0]: 77
7914 10:05:14.055409 [Byte1]: 77
7915 10:05:14.059116
7916 10:05:14.059198 Set Vref, RX VrefLevel [Byte0]: 78
7917 10:05:14.062709 [Byte1]: 78
7918 10:05:14.066752
7919 10:05:14.066835 Final RX Vref Byte 0 = 51 to rank0
7920 10:05:14.070126 Final RX Vref Byte 1 = 62 to rank0
7921 10:05:14.073934 Final RX Vref Byte 0 = 51 to rank1
7922 10:05:14.077010 Final RX Vref Byte 1 = 62 to rank1==
7923 10:05:14.080386 Dram Type= 6, Freq= 0, CH_0, rank 0
7924 10:05:14.083498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7925 10:05:14.087254 ==
7926 10:05:14.087337 DQS Delay:
7927 10:05:14.087404 DQS0 = 0, DQS1 = 0
7928 10:05:14.090331 DQM Delay:
7929 10:05:14.090415 DQM0 = 133, DQM1 = 127
7930 10:05:14.093800 DQ Delay:
7931 10:05:14.096981 DQ0 =134, DQ1 =138, DQ2 =132, DQ3 =130
7932 10:05:14.100144 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =138
7933 10:05:14.103780 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7934 10:05:14.106916 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
7935 10:05:14.106999
7936 10:05:14.107065
7937 10:05:14.107126
7938 10:05:14.110182 [DramC_TX_OE_Calibration] TA2
7939 10:05:14.113827 Original DQ_B0 (3 6) =30, OEN = 27
7940 10:05:14.117136 Original DQ_B1 (3 6) =30, OEN = 27
7941 10:05:14.120643 24, 0x0, End_B0=24 End_B1=24
7942 10:05:14.120727 25, 0x0, End_B0=25 End_B1=25
7943 10:05:14.123475 26, 0x0, End_B0=26 End_B1=26
7944 10:05:14.126770 27, 0x0, End_B0=27 End_B1=27
7945 10:05:14.130074 28, 0x0, End_B0=28 End_B1=28
7946 10:05:14.130158 29, 0x0, End_B0=29 End_B1=29
7947 10:05:14.133593 30, 0x0, End_B0=30 End_B1=30
7948 10:05:14.137033 31, 0x4141, End_B0=30 End_B1=30
7949 10:05:14.140465 Byte0 end_step=30 best_step=27
7950 10:05:14.143561 Byte1 end_step=30 best_step=27
7951 10:05:14.147388 Byte0 TX OE(2T, 0.5T) = (3, 3)
7952 10:05:14.147475 Byte1 TX OE(2T, 0.5T) = (3, 3)
7953 10:05:14.147542
7954 10:05:14.150411
7955 10:05:14.157078 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7956 10:05:14.160283 CH0 RK0: MR19=303, MR18=2420
7957 10:05:14.166813 CH0_RK0: MR19=0x303, MR18=0x2420, DQSOSC=391, MR23=63, INC=24, DEC=16
7958 10:05:14.166908
7959 10:05:14.169986 ----->DramcWriteLeveling(PI) begin...
7960 10:05:14.170071 ==
7961 10:05:14.173962 Dram Type= 6, Freq= 0, CH_0, rank 1
7962 10:05:14.176539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7963 10:05:14.176623 ==
7964 10:05:14.180440 Write leveling (Byte 0): 34 => 34
7965 10:05:14.183276 Write leveling (Byte 1): 28 => 28
7966 10:05:14.186833 DramcWriteLeveling(PI) end<-----
7967 10:05:14.186917
7968 10:05:14.186982 ==
7969 10:05:14.189928 Dram Type= 6, Freq= 0, CH_0, rank 1
7970 10:05:14.193705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7971 10:05:14.193812 ==
7972 10:05:14.196823 [Gating] SW mode calibration
7973 10:05:14.203605 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7974 10:05:14.210140 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7975 10:05:14.213138 1 4 0 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7976 10:05:14.216387 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7977 10:05:14.222999 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7978 10:05:14.226599 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (1 1) (0 0)
7979 10:05:14.229817 1 4 16 | B1->B0 | 2c2c 3938 | 0 1 | (0 0) (0 0)
7980 10:05:14.236370 1 4 20 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7981 10:05:14.239774 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7982 10:05:14.243430 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7983 10:05:14.250032 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7984 10:05:14.253086 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7985 10:05:14.256349 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7986 10:05:14.263209 1 5 12 | B1->B0 | 3434 3332 | 1 1 | (1 0) (0 1)
7987 10:05:14.266792 1 5 16 | B1->B0 | 2d2d 2928 | 0 1 | (0 0) (0 0)
7988 10:05:14.269754 1 5 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7989 10:05:14.276228 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7990 10:05:14.279867 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7991 10:05:14.282910 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7992 10:05:14.289912 1 6 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7993 10:05:14.292853 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7994 10:05:14.296282 1 6 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7995 10:05:14.302818 1 6 16 | B1->B0 | 3e3e 4646 | 0 1 | (0 0) (0 0)
7996 10:05:14.306237 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 10:05:14.309386 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 10:05:14.312859 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7999 10:05:14.319711 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 10:05:14.322690 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 10:05:14.326178 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 10:05:14.332777 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8003 10:05:14.336371 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8004 10:05:14.339377 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 10:05:14.346753 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 10:05:14.349323 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 10:05:14.353065 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 10:05:14.359509 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 10:05:14.362929 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 10:05:14.366353 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 10:05:14.372579 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 10:05:14.375934 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 10:05:14.379443 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 10:05:14.386376 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 10:05:14.389296 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 10:05:14.392335 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 10:05:14.399085 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8018 10:05:14.402899 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8019 10:05:14.405890 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8020 10:05:14.412474 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 10:05:14.412558 Total UI for P1: 0, mck2ui 16
8022 10:05:14.419132 best dqsien dly found for B0: ( 1, 9, 12)
8023 10:05:14.419215 Total UI for P1: 0, mck2ui 16
8024 10:05:14.422621 best dqsien dly found for B1: ( 1, 9, 14)
8025 10:05:14.429358 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8026 10:05:14.432368 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8027 10:05:14.432452
8028 10:05:14.435658 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8029 10:05:14.439136 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8030 10:05:14.442367 [Gating] SW calibration Done
8031 10:05:14.442455 ==
8032 10:05:14.445742 Dram Type= 6, Freq= 0, CH_0, rank 1
8033 10:05:14.449098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8034 10:05:14.449182 ==
8035 10:05:14.452179 RX Vref Scan: 0
8036 10:05:14.452280
8037 10:05:14.452379 RX Vref 0 -> 0, step: 1
8038 10:05:14.452474
8039 10:05:14.455797 RX Delay 0 -> 252, step: 8
8040 10:05:14.458910 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8041 10:05:14.465363 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8042 10:05:14.469067 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8043 10:05:14.472542 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8044 10:05:14.475577 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8045 10:05:14.479213 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8046 10:05:14.482258 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8047 10:05:14.488915 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8048 10:05:14.492457 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8049 10:05:14.495997 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8050 10:05:14.498694 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8051 10:05:14.505318 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8052 10:05:14.509024 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8053 10:05:14.512032 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8054 10:05:14.515645 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8055 10:05:14.519043 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8056 10:05:14.519127 ==
8057 10:05:14.522094 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 10:05:14.528538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 10:05:14.528625 ==
8060 10:05:14.528692 DQS Delay:
8061 10:05:14.531911 DQS0 = 0, DQS1 = 0
8062 10:05:14.532007 DQM Delay:
8063 10:05:14.535520 DQM0 = 136, DQM1 = 128
8064 10:05:14.535603 DQ Delay:
8065 10:05:14.538970 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8066 10:05:14.542509 DQ4 =135, DQ5 =127, DQ6 =139, DQ7 =143
8067 10:05:14.545327 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8068 10:05:14.548674 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8069 10:05:14.548774
8070 10:05:14.548865
8071 10:05:14.548927 ==
8072 10:05:14.551921 Dram Type= 6, Freq= 0, CH_0, rank 1
8073 10:05:14.558994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8074 10:05:14.559077 ==
8075 10:05:14.559144
8076 10:05:14.559206
8077 10:05:14.559266 TX Vref Scan disable
8078 10:05:14.562003 == TX Byte 0 ==
8079 10:05:14.565689 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8080 10:05:14.568728 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8081 10:05:14.571869 == TX Byte 1 ==
8082 10:05:14.575498 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8083 10:05:14.578503 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8084 10:05:14.582310 ==
8085 10:05:14.585366 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 10:05:14.588915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 10:05:14.589024 ==
8088 10:05:14.601768
8089 10:05:14.605136 TX Vref early break, caculate TX vref
8090 10:05:14.608728 TX Vref=16, minBit 2, minWin=23, winSum=384
8091 10:05:14.611535 TX Vref=18, minBit 1, minWin=23, winSum=400
8092 10:05:14.615195 TX Vref=20, minBit 1, minWin=23, winSum=408
8093 10:05:14.618169 TX Vref=22, minBit 0, minWin=24, winSum=409
8094 10:05:14.621701 TX Vref=24, minBit 0, minWin=25, winSum=424
8095 10:05:14.627985 TX Vref=26, minBit 1, minWin=25, winSum=431
8096 10:05:14.631519 TX Vref=28, minBit 7, minWin=25, winSum=426
8097 10:05:14.634772 TX Vref=30, minBit 0, minWin=25, winSum=416
8098 10:05:14.638313 TX Vref=32, minBit 7, minWin=24, winSum=412
8099 10:05:14.641347 TX Vref=34, minBit 0, minWin=24, winSum=405
8100 10:05:14.648266 [TxChooseVref] Worse bit 1, Min win 25, Win sum 431, Final Vref 26
8101 10:05:14.648375
8102 10:05:14.651423 Final TX Range 0 Vref 26
8103 10:05:14.651530
8104 10:05:14.651622 ==
8105 10:05:14.654796 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 10:05:14.658467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 10:05:14.658549 ==
8108 10:05:14.658615
8109 10:05:14.658674
8110 10:05:14.661814 TX Vref Scan disable
8111 10:05:14.667984 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8112 10:05:14.668073 == TX Byte 0 ==
8113 10:05:14.671958 u2DelayCellOfst[0]=13 cells (4 PI)
8114 10:05:14.675165 u2DelayCellOfst[1]=13 cells (4 PI)
8115 10:05:14.678173 u2DelayCellOfst[2]=10 cells (3 PI)
8116 10:05:14.681971 u2DelayCellOfst[3]=10 cells (3 PI)
8117 10:05:14.685047 u2DelayCellOfst[4]=6 cells (2 PI)
8118 10:05:14.688589 u2DelayCellOfst[5]=0 cells (0 PI)
8119 10:05:14.688676 u2DelayCellOfst[6]=16 cells (5 PI)
8120 10:05:14.691549 u2DelayCellOfst[7]=13 cells (4 PI)
8121 10:05:14.698206 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8122 10:05:14.702012 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8123 10:05:14.702094 == TX Byte 1 ==
8124 10:05:14.705083 u2DelayCellOfst[8]=0 cells (0 PI)
8125 10:05:14.708399 u2DelayCellOfst[9]=0 cells (0 PI)
8126 10:05:14.711292 u2DelayCellOfst[10]=6 cells (2 PI)
8127 10:05:14.714693 u2DelayCellOfst[11]=6 cells (2 PI)
8128 10:05:14.718041 u2DelayCellOfst[12]=10 cells (3 PI)
8129 10:05:14.721511 u2DelayCellOfst[13]=13 cells (4 PI)
8130 10:05:14.724539 u2DelayCellOfst[14]=13 cells (4 PI)
8131 10:05:14.728217 u2DelayCellOfst[15]=10 cells (3 PI)
8132 10:05:14.731276 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8133 10:05:14.735029 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8134 10:05:14.738400 DramC Write-DBI on
8135 10:05:14.738507 ==
8136 10:05:14.741681 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 10:05:14.744555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 10:05:14.744654 ==
8139 10:05:14.744745
8140 10:05:14.748170
8141 10:05:14.748303 TX Vref Scan disable
8142 10:05:14.751449 == TX Byte 0 ==
8143 10:05:14.754632 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8144 10:05:14.758268 == TX Byte 1 ==
8145 10:05:14.761167 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8146 10:05:14.761249 DramC Write-DBI off
8147 10:05:14.761314
8148 10:05:14.764471 [DATLAT]
8149 10:05:14.764569 Freq=1600, CH0 RK1
8150 10:05:14.764659
8151 10:05:14.768028 DATLAT Default: 0xf
8152 10:05:14.768128 0, 0xFFFF, sum = 0
8153 10:05:14.771484 1, 0xFFFF, sum = 0
8154 10:05:14.771585 2, 0xFFFF, sum = 0
8155 10:05:14.774389 3, 0xFFFF, sum = 0
8156 10:05:14.774499 4, 0xFFFF, sum = 0
8157 10:05:14.777920 5, 0xFFFF, sum = 0
8158 10:05:14.778003 6, 0xFFFF, sum = 0
8159 10:05:14.781692 7, 0xFFFF, sum = 0
8160 10:05:14.784722 8, 0xFFFF, sum = 0
8161 10:05:14.784865 9, 0xFFFF, sum = 0
8162 10:05:14.788375 10, 0xFFFF, sum = 0
8163 10:05:14.788484 11, 0xFFFF, sum = 0
8164 10:05:14.791297 12, 0xFFFF, sum = 0
8165 10:05:14.791379 13, 0xFFFF, sum = 0
8166 10:05:14.794523 14, 0x0, sum = 1
8167 10:05:14.794633 15, 0x0, sum = 2
8168 10:05:14.797886 16, 0x0, sum = 3
8169 10:05:14.797969 17, 0x0, sum = 4
8170 10:05:14.798036 best_step = 15
8171 10:05:14.798095
8172 10:05:14.801326 ==
8173 10:05:14.805008 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 10:05:14.807863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 10:05:14.807945 ==
8176 10:05:14.808010 RX Vref Scan: 0
8177 10:05:14.808069
8178 10:05:14.811301 RX Vref 0 -> 0, step: 1
8179 10:05:14.811382
8180 10:05:14.814811 RX Delay 19 -> 252, step: 4
8181 10:05:14.818220 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8182 10:05:14.821254 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8183 10:05:14.828334 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8184 10:05:14.831430 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8185 10:05:14.834412 iDelay=191, Bit 4, Center 136 (83 ~ 190) 108
8186 10:05:14.838190 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8187 10:05:14.841040 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8188 10:05:14.848255 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8189 10:05:14.851247 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8190 10:05:14.854560 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8191 10:05:14.858140 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8192 10:05:14.861009 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8193 10:05:14.868413 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8194 10:05:14.871192 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8195 10:05:14.874364 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8196 10:05:14.878139 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8197 10:05:14.878220 ==
8198 10:05:14.881506 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 10:05:14.887932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 10:05:14.888015 ==
8201 10:05:14.888082 DQS Delay:
8202 10:05:14.888142 DQS0 = 0, DQS1 = 0
8203 10:05:14.891505 DQM Delay:
8204 10:05:14.891612 DQM0 = 134, DQM1 = 127
8205 10:05:14.894553 DQ Delay:
8206 10:05:14.898243 DQ0 =134, DQ1 =136, DQ2 =132, DQ3 =134
8207 10:05:14.901214 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =142
8208 10:05:14.904595 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8209 10:05:14.908171 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8210 10:05:14.908277
8211 10:05:14.908370
8212 10:05:14.908458
8213 10:05:14.911256 [DramC_TX_OE_Calibration] TA2
8214 10:05:14.914201 Original DQ_B0 (3 6) =30, OEN = 27
8215 10:05:14.917624 Original DQ_B1 (3 6) =30, OEN = 27
8216 10:05:14.921212 24, 0x0, End_B0=24 End_B1=24
8217 10:05:14.921336 25, 0x0, End_B0=25 End_B1=25
8218 10:05:14.924098 26, 0x0, End_B0=26 End_B1=26
8219 10:05:14.927642 27, 0x0, End_B0=27 End_B1=27
8220 10:05:14.930846 28, 0x0, End_B0=28 End_B1=28
8221 10:05:14.934241 29, 0x0, End_B0=29 End_B1=29
8222 10:05:14.934329 30, 0x0, End_B0=30 End_B1=30
8223 10:05:14.937836 31, 0x4141, End_B0=30 End_B1=30
8224 10:05:14.940743 Byte0 end_step=30 best_step=27
8225 10:05:14.943870 Byte1 end_step=30 best_step=27
8226 10:05:14.947743 Byte0 TX OE(2T, 0.5T) = (3, 3)
8227 10:05:14.950312 Byte1 TX OE(2T, 0.5T) = (3, 3)
8228 10:05:14.950416
8229 10:05:14.950488
8230 10:05:14.957120 [DQSOSCAuto] RK1, (LSB)MR18= 0x220a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8231 10:05:14.960752 CH0 RK1: MR19=303, MR18=220A
8232 10:05:14.967521 CH0_RK1: MR19=0x303, MR18=0x220A, DQSOSC=392, MR23=63, INC=24, DEC=16
8233 10:05:14.970606 [RxdqsGatingPostProcess] freq 1600
8234 10:05:14.974213 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8235 10:05:14.977519 best DQS0 dly(2T, 0.5T) = (1, 1)
8236 10:05:14.980741 best DQS1 dly(2T, 0.5T) = (1, 1)
8237 10:05:14.984156 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8238 10:05:14.986921 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8239 10:05:14.990347 best DQS0 dly(2T, 0.5T) = (1, 1)
8240 10:05:14.993652 best DQS1 dly(2T, 0.5T) = (1, 1)
8241 10:05:14.996874 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8242 10:05:15.000616 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8243 10:05:15.003550 Pre-setting of DQS Precalculation
8244 10:05:15.007122 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8245 10:05:15.007205 ==
8246 10:05:15.010012 Dram Type= 6, Freq= 0, CH_1, rank 0
8247 10:05:15.013858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8248 10:05:15.017561 ==
8249 10:05:15.020878 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8250 10:05:15.023520 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8251 10:05:15.030354 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8252 10:05:15.034021 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8253 10:05:15.044097 [CA 0] Center 42 (13~72) winsize 60
8254 10:05:15.047274 [CA 1] Center 42 (13~72) winsize 60
8255 10:05:15.050706 [CA 2] Center 39 (10~68) winsize 59
8256 10:05:15.053697 [CA 3] Center 38 (9~68) winsize 60
8257 10:05:15.057419 [CA 4] Center 38 (9~68) winsize 60
8258 10:05:15.060259 [CA 5] Center 37 (8~67) winsize 60
8259 10:05:15.060342
8260 10:05:15.064207 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8261 10:05:15.064290
8262 10:05:15.067022 [CATrainingPosCal] consider 1 rank data
8263 10:05:15.070406 u2DelayCellTimex100 = 290/100 ps
8264 10:05:15.074217 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8265 10:05:15.080476 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8266 10:05:15.083799 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8267 10:05:15.087412 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
8268 10:05:15.090318 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8269 10:05:15.093846 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8270 10:05:15.093929
8271 10:05:15.097335 CA PerBit enable=1, Macro0, CA PI delay=37
8272 10:05:15.097418
8273 10:05:15.100390 [CBTSetCACLKResult] CA Dly = 37
8274 10:05:15.103690 CS Dly: 10 (0~41)
8275 10:05:15.107217 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8276 10:05:15.110819 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8277 10:05:15.110902 ==
8278 10:05:15.113595 Dram Type= 6, Freq= 0, CH_1, rank 1
8279 10:05:15.117253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8280 10:05:15.120367 ==
8281 10:05:15.123963 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8282 10:05:15.127192 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8283 10:05:15.133882 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8284 10:05:15.136831 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8285 10:05:15.147655 [CA 0] Center 42 (12~72) winsize 61
8286 10:05:15.151188 [CA 1] Center 41 (12~71) winsize 60
8287 10:05:15.153724 [CA 2] Center 38 (9~68) winsize 60
8288 10:05:15.157242 [CA 3] Center 37 (8~67) winsize 60
8289 10:05:15.160766 [CA 4] Center 38 (9~68) winsize 60
8290 10:05:15.163845 [CA 5] Center 37 (8~67) winsize 60
8291 10:05:15.163928
8292 10:05:15.167502 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8293 10:05:15.167582
8294 10:05:15.170516 [CATrainingPosCal] consider 2 rank data
8295 10:05:15.173716 u2DelayCellTimex100 = 290/100 ps
8296 10:05:15.177223 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8297 10:05:15.183862 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8298 10:05:15.187499 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8299 10:05:15.190936 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8300 10:05:15.194176 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8301 10:05:15.196983 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8302 10:05:15.197089
8303 10:05:15.200408 CA PerBit enable=1, Macro0, CA PI delay=37
8304 10:05:15.200514
8305 10:05:15.203443 [CBTSetCACLKResult] CA Dly = 37
8306 10:05:15.207190 CS Dly: 12 (0~45)
8307 10:05:15.210143 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8308 10:05:15.213736 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8309 10:05:15.213816
8310 10:05:15.217256 ----->DramcWriteLeveling(PI) begin...
8311 10:05:15.217332 ==
8312 10:05:15.220219 Dram Type= 6, Freq= 0, CH_1, rank 0
8313 10:05:15.223845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 10:05:15.226966 ==
8315 10:05:15.227050 Write leveling (Byte 0): 25 => 25
8316 10:05:15.230756 Write leveling (Byte 1): 27 => 27
8317 10:05:15.233656 DramcWriteLeveling(PI) end<-----
8318 10:05:15.233735
8319 10:05:15.233806 ==
8320 10:05:15.237124 Dram Type= 6, Freq= 0, CH_1, rank 0
8321 10:05:15.243723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8322 10:05:15.243803 ==
8323 10:05:15.246868 [Gating] SW mode calibration
8324 10:05:15.253816 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8325 10:05:15.257183 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8326 10:05:15.263801 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 10:05:15.266789 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 10:05:15.270021 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8329 10:05:15.276676 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 10:05:15.280570 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 10:05:15.283476 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 10:05:15.290125 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 10:05:15.293359 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 10:05:15.296760 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 10:05:15.303643 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 10:05:15.306591 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8337 10:05:15.309765 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
8338 10:05:15.316428 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 10:05:15.320307 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 10:05:15.323434 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 10:05:15.326474 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 10:05:15.332943 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 10:05:15.336152 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8344 10:05:15.339736 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8345 10:05:15.346408 1 6 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
8346 10:05:15.349484 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 10:05:15.353257 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 10:05:15.359411 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 10:05:15.363499 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 10:05:15.366495 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 10:05:15.372953 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 10:05:15.376568 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8353 10:05:15.379772 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8354 10:05:15.386051 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 10:05:15.389724 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 10:05:15.393170 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 10:05:15.399727 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 10:05:15.403080 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 10:05:15.406565 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 10:05:15.413110 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 10:05:15.416140 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 10:05:15.419244 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 10:05:15.426585 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 10:05:15.429212 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 10:05:15.432974 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 10:05:15.439660 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 10:05:15.442914 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 10:05:15.446049 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8369 10:05:15.452521 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8370 10:05:15.455549 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 10:05:15.458999 Total UI for P1: 0, mck2ui 16
8372 10:05:15.462494 best dqsien dly found for B0: ( 1, 9, 10)
8373 10:05:15.465606 Total UI for P1: 0, mck2ui 16
8374 10:05:15.469194 best dqsien dly found for B1: ( 1, 9, 10)
8375 10:05:15.472237 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8376 10:05:15.475710 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8377 10:05:15.475792
8378 10:05:15.479738 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8379 10:05:15.482405 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8380 10:05:15.485928 [Gating] SW calibration Done
8381 10:05:15.486011 ==
8382 10:05:15.489287 Dram Type= 6, Freq= 0, CH_1, rank 0
8383 10:05:15.492139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8384 10:05:15.492234 ==
8385 10:05:15.495743 RX Vref Scan: 0
8386 10:05:15.495825
8387 10:05:15.499229 RX Vref 0 -> 0, step: 1
8388 10:05:15.499311
8389 10:05:15.499377 RX Delay 0 -> 252, step: 8
8390 10:05:15.505600 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8391 10:05:15.509124 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8392 10:05:15.512233 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8393 10:05:15.515561 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8394 10:05:15.518791 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8395 10:05:15.525991 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8396 10:05:15.529010 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8397 10:05:15.532436 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8398 10:05:15.535775 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8399 10:05:15.539300 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8400 10:05:15.542208 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8401 10:05:15.548796 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8402 10:05:15.552469 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8403 10:05:15.555438 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8404 10:05:15.558900 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8405 10:05:15.565469 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8406 10:05:15.565551 ==
8407 10:05:15.569116 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 10:05:15.572136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 10:05:15.572218 ==
8410 10:05:15.572284 DQS Delay:
8411 10:05:15.575284 DQS0 = 0, DQS1 = 0
8412 10:05:15.575366 DQM Delay:
8413 10:05:15.578694 DQM0 = 136, DQM1 = 132
8414 10:05:15.578776 DQ Delay:
8415 10:05:15.582057 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8416 10:05:15.585490 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8417 10:05:15.588763 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8418 10:05:15.591764 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8419 10:05:15.591847
8420 10:05:15.591912
8421 10:05:15.595458 ==
8422 10:05:15.598988 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 10:05:15.601948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 10:05:15.602030 ==
8425 10:05:15.602096
8426 10:05:15.602156
8427 10:05:15.605520 TX Vref Scan disable
8428 10:05:15.605602 == TX Byte 0 ==
8429 10:05:15.608597 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8430 10:05:15.615457 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8431 10:05:15.615540 == TX Byte 1 ==
8432 10:05:15.618635 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8433 10:05:15.625220 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8434 10:05:15.625304 ==
8435 10:05:15.628320 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 10:05:15.631843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 10:05:15.631952 ==
8438 10:05:15.645276
8439 10:05:15.690698 TX Vref early break, caculate TX vref
8440 10:05:15.690800 TX Vref=16, minBit 9, minWin=22, winSum=377
8441 10:05:15.690870 TX Vref=18, minBit 11, minWin=22, winSum=384
8442 10:05:15.690932 TX Vref=20, minBit 0, minWin=24, winSum=399
8443 10:05:15.690991 TX Vref=22, minBit 0, minWin=25, winSum=410
8444 10:05:15.691049 TX Vref=24, minBit 1, minWin=25, winSum=419
8445 10:05:15.691108 TX Vref=26, minBit 0, minWin=25, winSum=428
8446 10:05:15.691165 TX Vref=28, minBit 0, minWin=25, winSum=424
8447 10:05:15.691220 TX Vref=30, minBit 0, minWin=25, winSum=424
8448 10:05:15.691274 TX Vref=32, minBit 0, minWin=24, winSum=414
8449 10:05:15.691328 TX Vref=34, minBit 6, minWin=23, winSum=405
8450 10:05:15.691601 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 26
8451 10:05:15.691669
8452 10:05:15.694437 Final TX Range 0 Vref 26
8453 10:05:15.694520
8454 10:05:15.694585 ==
8455 10:05:15.697970 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 10:05:15.701260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 10:05:15.701343 ==
8458 10:05:15.701475
8459 10:05:15.701584
8460 10:05:15.704473 TX Vref Scan disable
8461 10:05:15.711232 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8462 10:05:15.711377 == TX Byte 0 ==
8463 10:05:15.714727 u2DelayCellOfst[0]=16 cells (5 PI)
8464 10:05:15.718169 u2DelayCellOfst[1]=10 cells (3 PI)
8465 10:05:15.721111 u2DelayCellOfst[2]=0 cells (0 PI)
8466 10:05:15.724405 u2DelayCellOfst[3]=6 cells (2 PI)
8467 10:05:15.727581 u2DelayCellOfst[4]=10 cells (3 PI)
8468 10:05:15.731519 u2DelayCellOfst[5]=13 cells (4 PI)
8469 10:05:15.734668 u2DelayCellOfst[6]=16 cells (5 PI)
8470 10:05:15.734755 u2DelayCellOfst[7]=3 cells (1 PI)
8471 10:05:15.741021 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8472 10:05:15.744261 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8473 10:05:15.744350 == TX Byte 1 ==
8474 10:05:15.747813 u2DelayCellOfst[8]=0 cells (0 PI)
8475 10:05:15.751261 u2DelayCellOfst[9]=3 cells (1 PI)
8476 10:05:15.754507 u2DelayCellOfst[10]=13 cells (4 PI)
8477 10:05:15.758111 u2DelayCellOfst[11]=6 cells (2 PI)
8478 10:05:15.761211 u2DelayCellOfst[12]=13 cells (4 PI)
8479 10:05:15.764497 u2DelayCellOfst[13]=16 cells (5 PI)
8480 10:05:15.767844 u2DelayCellOfst[14]=16 cells (5 PI)
8481 10:05:15.770828 u2DelayCellOfst[15]=16 cells (5 PI)
8482 10:05:15.774623 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8483 10:05:15.781692 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8484 10:05:15.781776 DramC Write-DBI on
8485 10:05:15.781843 ==
8486 10:05:15.784395 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 10:05:15.787403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 10:05:15.790993 ==
8489 10:05:15.791075
8490 10:05:15.791140
8491 10:05:15.791200 TX Vref Scan disable
8492 10:05:15.794222 == TX Byte 0 ==
8493 10:05:15.797250 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8494 10:05:15.800931 == TX Byte 1 ==
8495 10:05:15.804519 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8496 10:05:15.807277 DramC Write-DBI off
8497 10:05:15.807359
8498 10:05:15.807424 [DATLAT]
8499 10:05:15.807484 Freq=1600, CH1 RK0
8500 10:05:15.807596
8501 10:05:15.810835 DATLAT Default: 0xf
8502 10:05:15.810917 0, 0xFFFF, sum = 0
8503 10:05:15.814233 1, 0xFFFF, sum = 0
8504 10:05:15.817366 2, 0xFFFF, sum = 0
8505 10:05:15.817449 3, 0xFFFF, sum = 0
8506 10:05:15.820654 4, 0xFFFF, sum = 0
8507 10:05:15.820737 5, 0xFFFF, sum = 0
8508 10:05:15.824389 6, 0xFFFF, sum = 0
8509 10:05:15.824472 7, 0xFFFF, sum = 0
8510 10:05:15.827221 8, 0xFFFF, sum = 0
8511 10:05:15.827305 9, 0xFFFF, sum = 0
8512 10:05:15.830653 10, 0xFFFF, sum = 0
8513 10:05:15.830736 11, 0xFFFF, sum = 0
8514 10:05:15.834092 12, 0xFFFF, sum = 0
8515 10:05:15.834176 13, 0xFFFF, sum = 0
8516 10:05:15.837368 14, 0x0, sum = 1
8517 10:05:15.837451 15, 0x0, sum = 2
8518 10:05:15.840676 16, 0x0, sum = 3
8519 10:05:15.840759 17, 0x0, sum = 4
8520 10:05:15.844206 best_step = 15
8521 10:05:15.844290
8522 10:05:15.844355 ==
8523 10:05:15.847251 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 10:05:15.850778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 10:05:15.850861 ==
8526 10:05:15.850926 RX Vref Scan: 1
8527 10:05:15.854311
8528 10:05:15.854394 Set Vref Range= 24 -> 127
8529 10:05:15.854459
8530 10:05:15.857490 RX Vref 24 -> 127, step: 1
8531 10:05:15.857573
8532 10:05:15.861043 RX Delay 27 -> 252, step: 4
8533 10:05:15.861125
8534 10:05:15.863979 Set Vref, RX VrefLevel [Byte0]: 24
8535 10:05:15.867168 [Byte1]: 24
8536 10:05:15.867250
8537 10:05:15.871087 Set Vref, RX VrefLevel [Byte0]: 25
8538 10:05:15.874125 [Byte1]: 25
8539 10:05:15.874208
8540 10:05:15.877445 Set Vref, RX VrefLevel [Byte0]: 26
8541 10:05:15.880426 [Byte1]: 26
8542 10:05:15.884276
8543 10:05:15.884358 Set Vref, RX VrefLevel [Byte0]: 27
8544 10:05:15.887748 [Byte1]: 27
8545 10:05:15.892183
8546 10:05:15.892265 Set Vref, RX VrefLevel [Byte0]: 28
8547 10:05:15.895109 [Byte1]: 28
8548 10:05:15.899404
8549 10:05:15.902949 Set Vref, RX VrefLevel [Byte0]: 29
8550 10:05:15.905991 [Byte1]: 29
8551 10:05:15.906074
8552 10:05:15.909100 Set Vref, RX VrefLevel [Byte0]: 30
8553 10:05:15.912562 [Byte1]: 30
8554 10:05:15.912644
8555 10:05:15.915947 Set Vref, RX VrefLevel [Byte0]: 31
8556 10:05:15.919173 [Byte1]: 31
8557 10:05:15.919270
8558 10:05:15.922557 Set Vref, RX VrefLevel [Byte0]: 32
8559 10:05:15.925527 [Byte1]: 32
8560 10:05:15.929881
8561 10:05:15.929972 Set Vref, RX VrefLevel [Byte0]: 33
8562 10:05:15.933104 [Byte1]: 33
8563 10:05:15.936773
8564 10:05:15.936892 Set Vref, RX VrefLevel [Byte0]: 34
8565 10:05:15.940675 [Byte1]: 34
8566 10:05:15.944800
8567 10:05:15.944932 Set Vref, RX VrefLevel [Byte0]: 35
8568 10:05:15.947714 [Byte1]: 35
8569 10:05:15.951985
8570 10:05:15.952073 Set Vref, RX VrefLevel [Byte0]: 36
8571 10:05:15.955776 [Byte1]: 36
8572 10:05:15.959626
8573 10:05:15.959714 Set Vref, RX VrefLevel [Byte0]: 37
8574 10:05:15.962716 [Byte1]: 37
8575 10:05:15.967057
8576 10:05:15.967151 Set Vref, RX VrefLevel [Byte0]: 38
8577 10:05:15.971004 [Byte1]: 38
8578 10:05:15.974464
8579 10:05:15.974551 Set Vref, RX VrefLevel [Byte0]: 39
8580 10:05:15.978217 [Byte1]: 39
8581 10:05:15.982503
8582 10:05:15.982593 Set Vref, RX VrefLevel [Byte0]: 40
8583 10:05:15.986254 [Byte1]: 40
8584 10:05:15.989853
8585 10:05:15.989941 Set Vref, RX VrefLevel [Byte0]: 41
8586 10:05:15.992752 [Byte1]: 41
8587 10:05:15.997286
8588 10:05:15.997373 Set Vref, RX VrefLevel [Byte0]: 42
8589 10:05:16.000644 [Byte1]: 42
8590 10:05:16.004929
8591 10:05:16.005017 Set Vref, RX VrefLevel [Byte0]: 43
8592 10:05:16.007897 [Byte1]: 43
8593 10:05:16.012334
8594 10:05:16.012419 Set Vref, RX VrefLevel [Byte0]: 44
8595 10:05:16.015920 [Byte1]: 44
8596 10:05:16.020181
8597 10:05:16.020270 Set Vref, RX VrefLevel [Byte0]: 45
8598 10:05:16.023029 [Byte1]: 45
8599 10:05:16.027400
8600 10:05:16.027490 Set Vref, RX VrefLevel [Byte0]: 46
8601 10:05:16.031046 [Byte1]: 46
8602 10:05:16.034929
8603 10:05:16.035020 Set Vref, RX VrefLevel [Byte0]: 47
8604 10:05:16.038067 [Byte1]: 47
8605 10:05:16.042678
8606 10:05:16.042766 Set Vref, RX VrefLevel [Byte0]: 48
8607 10:05:16.045859 [Byte1]: 48
8608 10:05:16.050051
8609 10:05:16.050140 Set Vref, RX VrefLevel [Byte0]: 49
8610 10:05:16.053522 [Byte1]: 49
8611 10:05:16.057885
8612 10:05:16.057974 Set Vref, RX VrefLevel [Byte0]: 50
8613 10:05:16.060838 [Byte1]: 50
8614 10:05:16.065141
8615 10:05:16.065262 Set Vref, RX VrefLevel [Byte0]: 51
8616 10:05:16.068532 [Byte1]: 51
8617 10:05:16.072480
8618 10:05:16.072587 Set Vref, RX VrefLevel [Byte0]: 52
8619 10:05:16.076349 [Byte1]: 52
8620 10:05:16.080475
8621 10:05:16.080573 Set Vref, RX VrefLevel [Byte0]: 53
8622 10:05:16.083466 [Byte1]: 53
8623 10:05:16.087821
8624 10:05:16.087924 Set Vref, RX VrefLevel [Byte0]: 54
8625 10:05:16.090733 [Byte1]: 54
8626 10:05:16.095362
8627 10:05:16.095470 Set Vref, RX VrefLevel [Byte0]: 55
8628 10:05:16.098726 [Byte1]: 55
8629 10:05:16.102881
8630 10:05:16.102985 Set Vref, RX VrefLevel [Byte0]: 56
8631 10:05:16.105880 [Byte1]: 56
8632 10:05:16.110538
8633 10:05:16.110650 Set Vref, RX VrefLevel [Byte0]: 57
8634 10:05:16.113775 [Byte1]: 57
8635 10:05:16.117921
8636 10:05:16.118015 Set Vref, RX VrefLevel [Byte0]: 58
8637 10:05:16.120742 [Byte1]: 58
8638 10:05:16.125272
8639 10:05:16.125374 Set Vref, RX VrefLevel [Byte0]: 59
8640 10:05:16.128385 [Byte1]: 59
8641 10:05:16.132946
8642 10:05:16.133049 Set Vref, RX VrefLevel [Byte0]: 60
8643 10:05:16.136321 [Byte1]: 60
8644 10:05:16.140659
8645 10:05:16.140761 Set Vref, RX VrefLevel [Byte0]: 61
8646 10:05:16.143553 [Byte1]: 61
8647 10:05:16.148092
8648 10:05:16.148227 Set Vref, RX VrefLevel [Byte0]: 62
8649 10:05:16.151587 [Byte1]: 62
8650 10:05:16.155415
8651 10:05:16.155528 Set Vref, RX VrefLevel [Byte0]: 63
8652 10:05:16.158690 [Byte1]: 63
8653 10:05:16.162917
8654 10:05:16.163020 Set Vref, RX VrefLevel [Byte0]: 64
8655 10:05:16.166327 [Byte1]: 64
8656 10:05:16.170538
8657 10:05:16.170634 Set Vref, RX VrefLevel [Byte0]: 65
8658 10:05:16.173677 [Byte1]: 65
8659 10:05:16.178209
8660 10:05:16.178307 Set Vref, RX VrefLevel [Byte0]: 66
8661 10:05:16.181695 [Byte1]: 66
8662 10:05:16.185943
8663 10:05:16.186038 Set Vref, RX VrefLevel [Byte0]: 67
8664 10:05:16.188838 [Byte1]: 67
8665 10:05:16.193287
8666 10:05:16.193383 Set Vref, RX VrefLevel [Byte0]: 68
8667 10:05:16.196215 [Byte1]: 68
8668 10:05:16.200763
8669 10:05:16.200924 Set Vref, RX VrefLevel [Byte0]: 69
8670 10:05:16.204210 [Byte1]: 69
8671 10:05:16.208553
8672 10:05:16.208654 Set Vref, RX VrefLevel [Byte0]: 70
8673 10:05:16.211446 [Byte1]: 70
8674 10:05:16.215645
8675 10:05:16.215758 Set Vref, RX VrefLevel [Byte0]: 71
8676 10:05:16.219203 [Byte1]: 71
8677 10:05:16.223260
8678 10:05:16.223383 Set Vref, RX VrefLevel [Byte0]: 72
8679 10:05:16.226723 [Byte1]: 72
8680 10:05:16.230840
8681 10:05:16.230935 Set Vref, RX VrefLevel [Byte0]: 73
8682 10:05:16.233887 [Byte1]: 73
8683 10:05:16.238490
8684 10:05:16.238649 Set Vref, RX VrefLevel [Byte0]: 74
8685 10:05:16.241484 [Byte1]: 74
8686 10:05:16.246094
8687 10:05:16.246256 Set Vref, RX VrefLevel [Byte0]: 75
8688 10:05:16.249180 [Byte1]: 75
8689 10:05:16.253504
8690 10:05:16.253647 Set Vref, RX VrefLevel [Byte0]: 76
8691 10:05:16.256548 [Byte1]: 76
8692 10:05:16.260771
8693 10:05:16.260943 Set Vref, RX VrefLevel [Byte0]: 77
8694 10:05:16.263968 [Byte1]: 77
8695 10:05:16.268667
8696 10:05:16.268814 Set Vref, RX VrefLevel [Byte0]: 78
8697 10:05:16.271940 [Byte1]: 78
8698 10:05:16.276302
8699 10:05:16.276446 Set Vref, RX VrefLevel [Byte0]: 79
8700 10:05:16.279317 [Byte1]: 79
8701 10:05:16.283455
8702 10:05:16.283598 Final RX Vref Byte 0 = 58 to rank0
8703 10:05:16.287109 Final RX Vref Byte 1 = 55 to rank0
8704 10:05:16.290197 Final RX Vref Byte 0 = 58 to rank1
8705 10:05:16.293169 Final RX Vref Byte 1 = 55 to rank1==
8706 10:05:16.296868 Dram Type= 6, Freq= 0, CH_1, rank 0
8707 10:05:16.303396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8708 10:05:16.303575 ==
8709 10:05:16.303712 DQS Delay:
8710 10:05:16.303837 DQS0 = 0, DQS1 = 0
8711 10:05:16.306629 DQM Delay:
8712 10:05:16.306762 DQM0 = 134, DQM1 = 131
8713 10:05:16.310000 DQ Delay:
8714 10:05:16.313836 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8715 10:05:16.316784 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8716 10:05:16.320199 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8717 10:05:16.323167 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8718 10:05:16.323322
8719 10:05:16.323447
8720 10:05:16.323596
8721 10:05:16.326814 [DramC_TX_OE_Calibration] TA2
8722 10:05:16.329711 Original DQ_B0 (3 6) =30, OEN = 27
8723 10:05:16.333587 Original DQ_B1 (3 6) =30, OEN = 27
8724 10:05:16.336875 24, 0x0, End_B0=24 End_B1=24
8725 10:05:16.337030 25, 0x0, End_B0=25 End_B1=25
8726 10:05:16.340212 26, 0x0, End_B0=26 End_B1=26
8727 10:05:16.343399 27, 0x0, End_B0=27 End_B1=27
8728 10:05:16.346878 28, 0x0, End_B0=28 End_B1=28
8729 10:05:16.349995 29, 0x0, End_B0=29 End_B1=29
8730 10:05:16.350181 30, 0x0, End_B0=30 End_B1=30
8731 10:05:16.353382 31, 0x4141, End_B0=30 End_B1=30
8732 10:05:16.356459 Byte0 end_step=30 best_step=27
8733 10:05:16.359952 Byte1 end_step=30 best_step=27
8734 10:05:16.363480 Byte0 TX OE(2T, 0.5T) = (3, 3)
8735 10:05:16.363642 Byte1 TX OE(2T, 0.5T) = (3, 3)
8736 10:05:16.366423
8737 10:05:16.366581
8738 10:05:16.373249 [DQSOSCAuto] RK0, (LSB)MR18= 0x1724, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8739 10:05:16.376369 CH1 RK0: MR19=303, MR18=1724
8740 10:05:16.382944 CH1_RK0: MR19=0x303, MR18=0x1724, DQSOSC=391, MR23=63, INC=24, DEC=16
8741 10:05:16.383152
8742 10:05:16.386610 ----->DramcWriteLeveling(PI) begin...
8743 10:05:16.386780 ==
8744 10:05:16.389768 Dram Type= 6, Freq= 0, CH_1, rank 1
8745 10:05:16.393030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8746 10:05:16.393203 ==
8747 10:05:16.396439 Write leveling (Byte 0): 25 => 25
8748 10:05:16.399659 Write leveling (Byte 1): 27 => 27
8749 10:05:16.403269 DramcWriteLeveling(PI) end<-----
8750 10:05:16.403437
8751 10:05:16.403572 ==
8752 10:05:16.406386 Dram Type= 6, Freq= 0, CH_1, rank 1
8753 10:05:16.410036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8754 10:05:16.410214 ==
8755 10:05:16.413437 [Gating] SW mode calibration
8756 10:05:16.419503 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8757 10:05:16.426398 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8758 10:05:16.429935 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 10:05:16.432968 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 10:05:16.439505 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8761 10:05:16.442898 1 4 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
8762 10:05:16.446761 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 10:05:16.452780 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 10:05:16.456388 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 10:05:16.459792 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 10:05:16.466519 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 10:05:16.469715 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8768 10:05:16.472715 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8769 10:05:16.479370 1 5 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 0)
8770 10:05:16.482807 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8771 10:05:16.486356 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 10:05:16.493053 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 10:05:16.496176 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 10:05:16.499590 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 10:05:16.506479 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 10:05:16.509550 1 6 8 | B1->B0 | 3535 2626 | 0 0 | (0 0) (0 0)
8777 10:05:16.513273 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 10:05:16.516264 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 10:05:16.523101 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 10:05:16.526639 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 10:05:16.529614 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 10:05:16.536976 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 10:05:16.539529 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8784 10:05:16.542720 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8785 10:05:16.550069 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8786 10:05:16.553110 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 10:05:16.557012 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 10:05:16.652847 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 10:05:16.653495 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 10:05:16.653996 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 10:05:16.654481 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 10:05:16.654963 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 10:05:16.655456 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 10:05:16.655952 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 10:05:16.656454 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 10:05:16.656971 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 10:05:16.657459 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 10:05:16.657773 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 10:05:16.658031 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8800 10:05:16.658090 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8801 10:05:16.658148 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8802 10:05:16.658204 Total UI for P1: 0, mck2ui 16
8803 10:05:16.658260 best dqsien dly found for B1: ( 1, 9, 6)
8804 10:05:16.658316 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 10:05:16.658372 Total UI for P1: 0, mck2ui 16
8806 10:05:16.658428 best dqsien dly found for B0: ( 1, 9, 12)
8807 10:05:16.658483 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8808 10:05:16.658538 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8809 10:05:16.658593
8810 10:05:16.658648 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8811 10:05:16.658716 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8812 10:05:16.658774 [Gating] SW calibration Done
8813 10:05:16.658830 ==
8814 10:05:16.658885 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 10:05:16.662580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 10:05:16.662665 ==
8817 10:05:16.662731 RX Vref Scan: 0
8818 10:05:16.662793
8819 10:05:16.666169 RX Vref 0 -> 0, step: 1
8820 10:05:16.666252
8821 10:05:16.669043 RX Delay 0 -> 252, step: 8
8822 10:05:16.672635 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8823 10:05:16.675942 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8824 10:05:16.679524 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8825 10:05:16.682650 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8826 10:05:16.689032 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8827 10:05:16.692479 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8828 10:05:16.695988 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8829 10:05:16.699108 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8830 10:05:16.702408 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8831 10:05:16.709116 iDelay=208, Bit 9, Center 127 (72 ~ 183) 112
8832 10:05:16.712530 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8833 10:05:16.715777 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8834 10:05:16.719237 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8835 10:05:16.722506 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8836 10:05:16.729367 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8837 10:05:16.732207 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8838 10:05:16.732345 ==
8839 10:05:16.735668 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 10:05:16.739428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 10:05:16.739568 ==
8842 10:05:16.742392 DQS Delay:
8843 10:05:16.742499 DQS0 = 0, DQS1 = 0
8844 10:05:16.742571 DQM Delay:
8845 10:05:16.745952 DQM0 = 136, DQM1 = 134
8846 10:05:16.746078 DQ Delay:
8847 10:05:16.749334 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8848 10:05:16.752480 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8849 10:05:16.759318 DQ8 =119, DQ9 =127, DQ10 =135, DQ11 =127
8850 10:05:16.762234 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8851 10:05:16.762366
8852 10:05:16.762436
8853 10:05:16.762498 ==
8854 10:05:16.766029 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 10:05:16.769473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 10:05:16.769608 ==
8857 10:05:16.769685
8858 10:05:16.769747
8859 10:05:16.772060 TX Vref Scan disable
8860 10:05:16.775648 == TX Byte 0 ==
8861 10:05:16.779011 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8862 10:05:16.782402 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8863 10:05:16.782541 == TX Byte 1 ==
8864 10:05:16.788934 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8865 10:05:16.792302 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8866 10:05:16.792442 ==
8867 10:05:16.795739 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 10:05:16.799018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 10:05:16.799174 ==
8870 10:05:16.813734
8871 10:05:16.817158 TX Vref early break, caculate TX vref
8872 10:05:16.820197 TX Vref=16, minBit 0, minWin=22, winSum=383
8873 10:05:16.823921 TX Vref=18, minBit 0, minWin=23, winSum=391
8874 10:05:16.826911 TX Vref=20, minBit 0, minWin=23, winSum=402
8875 10:05:16.830568 TX Vref=22, minBit 1, minWin=24, winSum=411
8876 10:05:16.834107 TX Vref=24, minBit 0, minWin=25, winSum=419
8877 10:05:16.840771 TX Vref=26, minBit 0, minWin=25, winSum=423
8878 10:05:16.843572 TX Vref=28, minBit 0, minWin=25, winSum=426
8879 10:05:16.847153 TX Vref=30, minBit 0, minWin=25, winSum=424
8880 10:05:16.850849 TX Vref=32, minBit 0, minWin=25, winSum=414
8881 10:05:16.853791 TX Vref=34, minBit 0, minWin=24, winSum=406
8882 10:05:16.857333 TX Vref=36, minBit 0, minWin=23, winSum=400
8883 10:05:16.863931 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8884 10:05:16.864080
8885 10:05:16.867316 Final TX Range 0 Vref 28
8886 10:05:16.867438
8887 10:05:16.867509 ==
8888 10:05:16.870318 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 10:05:16.873691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 10:05:16.873829 ==
8891 10:05:16.873902
8892 10:05:16.873964
8893 10:05:16.877313 TX Vref Scan disable
8894 10:05:16.883548 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8895 10:05:16.883701 == TX Byte 0 ==
8896 10:05:16.887068 u2DelayCellOfst[0]=16 cells (5 PI)
8897 10:05:16.890342 u2DelayCellOfst[1]=10 cells (3 PI)
8898 10:05:16.893902 u2DelayCellOfst[2]=0 cells (0 PI)
8899 10:05:16.897010 u2DelayCellOfst[3]=6 cells (2 PI)
8900 10:05:16.900535 u2DelayCellOfst[4]=10 cells (3 PI)
8901 10:05:16.903728 u2DelayCellOfst[5]=16 cells (5 PI)
8902 10:05:16.906937 u2DelayCellOfst[6]=20 cells (6 PI)
8903 10:05:16.910455 u2DelayCellOfst[7]=6 cells (2 PI)
8904 10:05:16.913496 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8905 10:05:16.916871 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8906 10:05:16.920531 == TX Byte 1 ==
8907 10:05:16.923526 u2DelayCellOfst[8]=0 cells (0 PI)
8908 10:05:16.923653 u2DelayCellOfst[9]=3 cells (1 PI)
8909 10:05:16.926720 u2DelayCellOfst[10]=10 cells (3 PI)
8910 10:05:16.930347 u2DelayCellOfst[11]=3 cells (1 PI)
8911 10:05:16.933340 u2DelayCellOfst[12]=13 cells (4 PI)
8912 10:05:16.937036 u2DelayCellOfst[13]=13 cells (4 PI)
8913 10:05:16.939976 u2DelayCellOfst[14]=16 cells (5 PI)
8914 10:05:16.943459 u2DelayCellOfst[15]=16 cells (5 PI)
8915 10:05:16.947137 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8916 10:05:16.953897 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8917 10:05:16.954050 DramC Write-DBI on
8918 10:05:16.954123 ==
8919 10:05:16.956860 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 10:05:16.960084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 10:05:16.963665 ==
8922 10:05:16.963804
8923 10:05:16.963873
8924 10:05:16.963935 TX Vref Scan disable
8925 10:05:16.967080 == TX Byte 0 ==
8926 10:05:16.970105 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8927 10:05:16.973972 == TX Byte 1 ==
8928 10:05:16.977277 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8929 10:05:16.980180 DramC Write-DBI off
8930 10:05:16.980311
8931 10:05:16.980382 [DATLAT]
8932 10:05:16.980445 Freq=1600, CH1 RK1
8933 10:05:16.980505
8934 10:05:16.983310 DATLAT Default: 0xf
8935 10:05:16.983411 0, 0xFFFF, sum = 0
8936 10:05:16.986759 1, 0xFFFF, sum = 0
8937 10:05:16.990324 2, 0xFFFF, sum = 0
8938 10:05:16.990451 3, 0xFFFF, sum = 0
8939 10:05:16.993766 4, 0xFFFF, sum = 0
8940 10:05:16.993884 5, 0xFFFF, sum = 0
8941 10:05:16.997110 6, 0xFFFF, sum = 0
8942 10:05:16.997235 7, 0xFFFF, sum = 0
8943 10:05:16.999976 8, 0xFFFF, sum = 0
8944 10:05:17.000092 9, 0xFFFF, sum = 0
8945 10:05:17.003602 10, 0xFFFF, sum = 0
8946 10:05:17.003719 11, 0xFFFF, sum = 0
8947 10:05:17.007292 12, 0xFFFF, sum = 0
8948 10:05:17.007414 13, 0xFFFF, sum = 0
8949 10:05:17.010055 14, 0x0, sum = 1
8950 10:05:17.010164 15, 0x0, sum = 2
8951 10:05:17.014145 16, 0x0, sum = 3
8952 10:05:17.014284 17, 0x0, sum = 4
8953 10:05:17.016748 best_step = 15
8954 10:05:17.016907
8955 10:05:17.016981 ==
8956 10:05:17.020195 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 10:05:17.023912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 10:05:17.024084 ==
8959 10:05:17.024155 RX Vref Scan: 0
8960 10:05:17.027278
8961 10:05:17.027392 RX Vref 0 -> 0, step: 1
8962 10:05:17.027462
8963 10:05:17.030402 RX Delay 19 -> 252, step: 4
8964 10:05:17.033497 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8965 10:05:17.040097 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8966 10:05:17.043877 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8967 10:05:17.047115 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8968 10:05:17.049951 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8969 10:05:17.054032 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8970 10:05:17.056704 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8971 10:05:17.063341 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8972 10:05:17.067016 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8973 10:05:17.069916 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
8974 10:05:17.073455 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8975 10:05:17.076689 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8976 10:05:17.083312 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8977 10:05:17.086911 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8978 10:05:17.089874 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8979 10:05:17.093449 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
8980 10:05:17.093601 ==
8981 10:05:17.096874 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 10:05:17.103233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 10:05:17.103388 ==
8984 10:05:17.103461 DQS Delay:
8985 10:05:17.106744 DQS0 = 0, DQS1 = 0
8986 10:05:17.106868 DQM Delay:
8987 10:05:17.106938 DQM0 = 134, DQM1 = 130
8988 10:05:17.110601 DQ Delay:
8989 10:05:17.113416 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8990 10:05:17.116603 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8991 10:05:17.119781 DQ8 =116, DQ9 =120, DQ10 =130, DQ11 =124
8992 10:05:17.123534 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =142
8993 10:05:17.123678
8994 10:05:17.123753
8995 10:05:17.123832
8996 10:05:17.126692 [DramC_TX_OE_Calibration] TA2
8997 10:05:17.130162 Original DQ_B0 (3 6) =30, OEN = 27
8998 10:05:17.133271 Original DQ_B1 (3 6) =30, OEN = 27
8999 10:05:17.136577 24, 0x0, End_B0=24 End_B1=24
9000 10:05:17.136740 25, 0x0, End_B0=25 End_B1=25
9001 10:05:17.139591 26, 0x0, End_B0=26 End_B1=26
9002 10:05:17.143280 27, 0x0, End_B0=27 End_B1=27
9003 10:05:17.146277 28, 0x0, End_B0=28 End_B1=28
9004 10:05:17.149788 29, 0x0, End_B0=29 End_B1=29
9005 10:05:17.149931 30, 0x0, End_B0=30 End_B1=30
9006 10:05:17.152758 31, 0x4141, End_B0=30 End_B1=30
9007 10:05:17.156257 Byte0 end_step=30 best_step=27
9008 10:05:17.159807 Byte1 end_step=30 best_step=27
9009 10:05:17.162935 Byte0 TX OE(2T, 0.5T) = (3, 3)
9010 10:05:17.166589 Byte1 TX OE(2T, 0.5T) = (3, 3)
9011 10:05:17.166725
9012 10:05:17.166801
9013 10:05:17.172891 [DQSOSCAuto] RK1, (LSB)MR18= 0x2309, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9014 10:05:17.176423 CH1 RK1: MR19=303, MR18=2309
9015 10:05:17.182847 CH1_RK1: MR19=0x303, MR18=0x2309, DQSOSC=392, MR23=63, INC=24, DEC=16
9016 10:05:17.186314 [RxdqsGatingPostProcess] freq 1600
9017 10:05:17.190069 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9018 10:05:17.193359 best DQS0 dly(2T, 0.5T) = (1, 1)
9019 10:05:17.196183 best DQS1 dly(2T, 0.5T) = (1, 1)
9020 10:05:17.199943 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9021 10:05:17.202733 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9022 10:05:17.206025 best DQS0 dly(2T, 0.5T) = (1, 1)
9023 10:05:17.209297 best DQS1 dly(2T, 0.5T) = (1, 1)
9024 10:05:17.212797 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9025 10:05:17.216104 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9026 10:05:17.219507 Pre-setting of DQS Precalculation
9027 10:05:17.222435 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9028 10:05:17.229557 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9029 10:05:17.239133 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9030 10:05:17.239312
9031 10:05:17.239417
9032 10:05:17.242360 [Calibration Summary] 3200 Mbps
9033 10:05:17.242492 CH 0, Rank 0
9034 10:05:17.245875 SW Impedance : PASS
9035 10:05:17.246030 DUTY Scan : NO K
9036 10:05:17.249318 ZQ Calibration : PASS
9037 10:05:17.252274 Jitter Meter : NO K
9038 10:05:17.252419 CBT Training : PASS
9039 10:05:17.255751 Write leveling : PASS
9040 10:05:17.255884 RX DQS gating : PASS
9041 10:05:17.259270 RX DQ/DQS(RDDQC) : PASS
9042 10:05:17.262435 TX DQ/DQS : PASS
9043 10:05:17.262583 RX DATLAT : PASS
9044 10:05:17.265576 RX DQ/DQS(Engine): PASS
9045 10:05:17.268975 TX OE : PASS
9046 10:05:17.269122 All Pass.
9047 10:05:17.269217
9048 10:05:17.269308 CH 0, Rank 1
9049 10:05:17.272730 SW Impedance : PASS
9050 10:05:17.275761 DUTY Scan : NO K
9051 10:05:17.275897 ZQ Calibration : PASS
9052 10:05:17.279221 Jitter Meter : NO K
9053 10:05:17.282341 CBT Training : PASS
9054 10:05:17.282487 Write leveling : PASS
9055 10:05:17.285805 RX DQS gating : PASS
9056 10:05:17.289243 RX DQ/DQS(RDDQC) : PASS
9057 10:05:17.289391 TX DQ/DQS : PASS
9058 10:05:17.292267 RX DATLAT : PASS
9059 10:05:17.295565 RX DQ/DQS(Engine): PASS
9060 10:05:17.295714 TX OE : PASS
9061 10:05:17.295813 All Pass.
9062 10:05:17.295917
9063 10:05:17.299140 CH 1, Rank 0
9064 10:05:17.299265 SW Impedance : PASS
9065 10:05:17.302280 DUTY Scan : NO K
9066 10:05:17.305867 ZQ Calibration : PASS
9067 10:05:17.305993 Jitter Meter : NO K
9068 10:05:17.308828 CBT Training : PASS
9069 10:05:17.312508 Write leveling : PASS
9070 10:05:17.312671 RX DQS gating : PASS
9071 10:05:17.315738 RX DQ/DQS(RDDQC) : PASS
9072 10:05:17.319194 TX DQ/DQS : PASS
9073 10:05:17.319349 RX DATLAT : PASS
9074 10:05:17.322080 RX DQ/DQS(Engine): PASS
9075 10:05:17.325713 TX OE : PASS
9076 10:05:17.325851 All Pass.
9077 10:05:17.325922
9078 10:05:17.325992 CH 1, Rank 1
9079 10:05:17.328726 SW Impedance : PASS
9080 10:05:17.332174 DUTY Scan : NO K
9081 10:05:17.332337 ZQ Calibration : PASS
9082 10:05:17.335271 Jitter Meter : NO K
9083 10:05:17.338877 CBT Training : PASS
9084 10:05:17.339085 Write leveling : PASS
9085 10:05:17.341897 RX DQS gating : PASS
9086 10:05:17.345417 RX DQ/DQS(RDDQC) : PASS
9087 10:05:17.345626 TX DQ/DQS : PASS
9088 10:05:17.348400 RX DATLAT : PASS
9089 10:05:17.351578 RX DQ/DQS(Engine): PASS
9090 10:05:17.351779 TX OE : PASS
9091 10:05:17.351926 All Pass.
9092 10:05:17.355090
9093 10:05:17.355268 DramC Write-DBI on
9094 10:05:17.358508 PER_BANK_REFRESH: Hybrid Mode
9095 10:05:17.358715 TX_TRACKING: ON
9096 10:05:17.368494 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9097 10:05:17.375217 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9098 10:05:17.385210 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9099 10:05:17.388253 [FAST_K] Save calibration result to emmc
9100 10:05:17.391666 sync common calibartion params.
9101 10:05:17.391848 sync cbt_mode0:1, 1:1
9102 10:05:17.394846 dram_init: ddr_geometry: 2
9103 10:05:17.398677 dram_init: ddr_geometry: 2
9104 10:05:17.398811 dram_init: ddr_geometry: 2
9105 10:05:17.402055 0:dram_rank_size:100000000
9106 10:05:17.404679 1:dram_rank_size:100000000
9107 10:05:17.411636 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9108 10:05:17.411786 DFS_SHUFFLE_HW_MODE: ON
9109 10:05:17.414762 dramc_set_vcore_voltage set vcore to 725000
9110 10:05:17.418192 Read voltage for 1600, 0
9111 10:05:17.418340 Vio18 = 0
9112 10:05:17.421130 Vcore = 725000
9113 10:05:17.421238 Vdram = 0
9114 10:05:17.421308 Vddq = 0
9115 10:05:17.424479 Vmddr = 0
9116 10:05:17.424661 switch to 3200 Mbps bootup
9117 10:05:17.428008 [DramcRunTimeConfig]
9118 10:05:17.428167 PHYPLL
9119 10:05:17.431491 DPM_CONTROL_AFTERK: ON
9120 10:05:17.431624 PER_BANK_REFRESH: ON
9121 10:05:17.434701 REFRESH_OVERHEAD_REDUCTION: ON
9122 10:05:17.437885 CMD_PICG_NEW_MODE: OFF
9123 10:05:17.438021 XRTWTW_NEW_MODE: ON
9124 10:05:17.441535 XRTRTR_NEW_MODE: ON
9125 10:05:17.441660 TX_TRACKING: ON
9126 10:05:17.444553 RDSEL_TRACKING: OFF
9127 10:05:17.447771 DQS Precalculation for DVFS: ON
9128 10:05:17.447898 RX_TRACKING: OFF
9129 10:05:17.451112 HW_GATING DBG: ON
9130 10:05:17.451207 ZQCS_ENABLE_LP4: ON
9131 10:05:17.454918 RX_PICG_NEW_MODE: ON
9132 10:05:17.455026 TX_PICG_NEW_MODE: ON
9133 10:05:17.457792 ENABLE_RX_DCM_DPHY: ON
9134 10:05:17.461229 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9135 10:05:17.464467 DUMMY_READ_FOR_TRACKING: OFF
9136 10:05:17.464627 !!! SPM_CONTROL_AFTERK: OFF
9137 10:05:17.468112 !!! SPM could not control APHY
9138 10:05:17.471393 IMPEDANCE_TRACKING: ON
9139 10:05:17.471530 TEMP_SENSOR: ON
9140 10:05:17.474367 HW_SAVE_FOR_SR: OFF
9141 10:05:17.478004 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9142 10:05:17.481019 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9143 10:05:17.481156 Read ODT Tracking: ON
9144 10:05:17.484455 Refresh Rate DeBounce: ON
9145 10:05:17.487787 DFS_NO_QUEUE_FLUSH: ON
9146 10:05:17.491256 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9147 10:05:17.491471 ENABLE_DFS_RUNTIME_MRW: OFF
9148 10:05:17.494573 DDR_RESERVE_NEW_MODE: ON
9149 10:05:17.497447 MR_CBT_SWITCH_FREQ: ON
9150 10:05:17.497629 =========================
9151 10:05:17.518213 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9152 10:05:17.521251 dram_init: ddr_geometry: 2
9153 10:05:17.539612 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9154 10:05:17.543328 dram_init: dram init end (result: 0)
9155 10:05:17.549684 DRAM-K: Full calibration passed in 24508 msecs
9156 10:05:17.553254 MRC: failed to locate region type 0.
9157 10:05:17.553383 DRAM rank0 size:0x100000000,
9158 10:05:17.556739 DRAM rank1 size=0x100000000
9159 10:05:17.565980 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9160 10:05:17.572787 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9161 10:05:17.579269 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9162 10:05:17.585771 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9163 10:05:17.589366 DRAM rank0 size:0x100000000,
9164 10:05:17.592558 DRAM rank1 size=0x100000000
9165 10:05:17.592703 CBMEM:
9166 10:05:17.596339 IMD: root @ 0xfffff000 254 entries.
9167 10:05:17.599344 IMD: root @ 0xffffec00 62 entries.
9168 10:05:17.602535 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9169 10:05:17.606251 WARNING: RO_VPD is uninitialized or empty.
9170 10:05:17.612752 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9171 10:05:17.619505 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9172 10:05:17.632448 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9173 10:05:17.643867 BS: romstage times (exec / console): total (unknown) / 24033 ms
9174 10:05:17.644023
9175 10:05:17.644117
9176 10:05:17.653786 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9177 10:05:17.657265 ARM64: Exception handlers installed.
9178 10:05:17.660212 ARM64: Testing exception
9179 10:05:17.663577 ARM64: Done test exception
9180 10:05:17.663700 Enumerating buses...
9181 10:05:17.666783 Show all devs... Before device enumeration.
9182 10:05:17.670163 Root Device: enabled 1
9183 10:05:17.673908 CPU_CLUSTER: 0: enabled 1
9184 10:05:17.674016 CPU: 00: enabled 1
9185 10:05:17.676896 Compare with tree...
9186 10:05:17.676995 Root Device: enabled 1
9187 10:05:17.680537 CPU_CLUSTER: 0: enabled 1
9188 10:05:17.683806 CPU: 00: enabled 1
9189 10:05:17.683924 Root Device scanning...
9190 10:05:17.686810 scan_static_bus for Root Device
9191 10:05:17.690080 CPU_CLUSTER: 0 enabled
9192 10:05:17.693756 scan_static_bus for Root Device done
9193 10:05:17.696894 scan_bus: bus Root Device finished in 8 msecs
9194 10:05:17.696980 done
9195 10:05:17.703764 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9196 10:05:17.706856 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9197 10:05:17.713370 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9198 10:05:17.716966 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9199 10:05:17.719884 Allocating resources...
9200 10:05:17.723154 Reading resources...
9201 10:05:17.726815 Root Device read_resources bus 0 link: 0
9202 10:05:17.726971 DRAM rank0 size:0x100000000,
9203 10:05:17.730265 DRAM rank1 size=0x100000000
9204 10:05:17.733438 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9205 10:05:17.736486 CPU: 00 missing read_resources
9206 10:05:17.739956 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9207 10:05:17.746683 Root Device read_resources bus 0 link: 0 done
9208 10:05:17.746858 Done reading resources.
9209 10:05:17.753513 Show resources in subtree (Root Device)...After reading.
9210 10:05:17.756430 Root Device child on link 0 CPU_CLUSTER: 0
9211 10:05:17.759794 CPU_CLUSTER: 0 child on link 0 CPU: 00
9212 10:05:17.769880 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9213 10:05:17.770054 CPU: 00
9214 10:05:17.773289 Root Device assign_resources, bus 0 link: 0
9215 10:05:17.776848 CPU_CLUSTER: 0 missing set_resources
9216 10:05:17.780501 Root Device assign_resources, bus 0 link: 0 done
9217 10:05:17.783216 Done setting resources.
9218 10:05:17.790539 Show resources in subtree (Root Device)...After assigning values.
9219 10:05:17.793131 Root Device child on link 0 CPU_CLUSTER: 0
9220 10:05:17.796441 CPU_CLUSTER: 0 child on link 0 CPU: 00
9221 10:05:17.806737 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9222 10:05:17.806899 CPU: 00
9223 10:05:17.809997 Done allocating resources.
9224 10:05:17.813697 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9225 10:05:17.816511 Enabling resources...
9226 10:05:17.816620 done.
9227 10:05:17.823108 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9228 10:05:17.823280 Initializing devices...
9229 10:05:17.827028 Root Device init
9230 10:05:17.827177 init hardware done!
9231 10:05:17.829538 0x00000018: ctrlr->caps
9232 10:05:17.833021 52.000 MHz: ctrlr->f_max
9233 10:05:17.833129 0.400 MHz: ctrlr->f_min
9234 10:05:17.836534 0x40ff8080: ctrlr->voltages
9235 10:05:17.836631 sclk: 390625
9236 10:05:17.839485 Bus Width = 1
9237 10:05:17.839602 sclk: 390625
9238 10:05:17.843026 Bus Width = 1
9239 10:05:17.843143 Early init status = 3
9240 10:05:17.849684 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9241 10:05:17.853004 in-header: 03 fc 00 00 01 00 00 00
9242 10:05:17.853148 in-data: 00
9243 10:05:17.859669 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9244 10:05:17.863177 in-header: 03 fd 00 00 00 00 00 00
9245 10:05:17.866132 in-data:
9246 10:05:17.869416 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9247 10:05:17.872808 in-header: 03 fc 00 00 01 00 00 00
9248 10:05:17.875834 in-data: 00
9249 10:05:17.879309 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9250 10:05:17.883732 in-header: 03 fd 00 00 00 00 00 00
9251 10:05:17.887119 in-data:
9252 10:05:17.890430 [SSUSB] Setting up USB HOST controller...
9253 10:05:17.893973 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9254 10:05:17.897320 [SSUSB] phy power-on done.
9255 10:05:17.900682 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9256 10:05:17.907447 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9257 10:05:17.910678 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9258 10:05:17.917271 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9259 10:05:17.923858 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9260 10:05:17.930531 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9261 10:05:17.937155 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9262 10:05:17.943854 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9263 10:05:17.946867 SPM: binary array size = 0x9dc
9264 10:05:17.950597 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9265 10:05:17.957176 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9266 10:05:17.963705 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9267 10:05:17.967322 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9268 10:05:17.973590 configure_display: Starting display init
9269 10:05:18.007167 anx7625_power_on_init: Init interface.
9270 10:05:18.010807 anx7625_disable_pd_protocol: Disabled PD feature.
9271 10:05:18.013801 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9272 10:05:18.041462 anx7625_start_dp_work: Secure OCM version=00
9273 10:05:18.044975 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9274 10:05:18.059777 sp_tx_get_edid_block: EDID Block = 1
9275 10:05:18.162369 Extracted contents:
9276 10:05:18.165858 header: 00 ff ff ff ff ff ff 00
9277 10:05:18.168993 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9278 10:05:18.172515 version: 01 04
9279 10:05:18.175874 basic params: 95 1f 11 78 0a
9280 10:05:18.178689 chroma info: 76 90 94 55 54 90 27 21 50 54
9281 10:05:18.182197 established: 00 00 00
9282 10:05:18.189124 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9283 10:05:18.192209 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9284 10:05:18.198703 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9285 10:05:18.205533 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9286 10:05:18.211840 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9287 10:05:18.215745 extensions: 00
9288 10:05:18.215864 checksum: fb
9289 10:05:18.215972
9290 10:05:18.218785 Manufacturer: IVO Model 57d Serial Number 0
9291 10:05:18.221796 Made week 0 of 2020
9292 10:05:18.221906 EDID version: 1.4
9293 10:05:18.224991 Digital display
9294 10:05:18.228716 6 bits per primary color channel
9295 10:05:18.228824 DisplayPort interface
9296 10:05:18.231837 Maximum image size: 31 cm x 17 cm
9297 10:05:18.235508 Gamma: 220%
9298 10:05:18.235628 Check DPMS levels
9299 10:05:18.238558 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9300 10:05:18.242214 First detailed timing is preferred timing
9301 10:05:18.245640 Established timings supported:
9302 10:05:18.248492 Standard timings supported:
9303 10:05:18.251754 Detailed timings
9304 10:05:18.255602 Hex of detail: 383680a07038204018303c0035ae10000019
9305 10:05:18.258407 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9306 10:05:18.265438 0780 0798 07c8 0820 hborder 0
9307 10:05:18.268508 0438 043b 0447 0458 vborder 0
9308 10:05:18.271987 -hsync -vsync
9309 10:05:18.272087 Did detailed timing
9310 10:05:18.275007 Hex of detail: 000000000000000000000000000000000000
9311 10:05:18.278609 Manufacturer-specified data, tag 0
9312 10:05:18.285389 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9313 10:05:18.285478 ASCII string: InfoVision
9314 10:05:18.291674 Hex of detail: 000000fe00523134304e574635205248200a
9315 10:05:18.295662 ASCII string: R140NWF5 RH
9316 10:05:18.295798 Checksum
9317 10:05:18.295926 Checksum: 0xfb (valid)
9318 10:05:18.301623 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9319 10:05:18.305116 DSI data_rate: 832800000 bps
9320 10:05:18.308336 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9321 10:05:18.315084 anx7625_parse_edid: pixelclock(138800).
9322 10:05:18.318183 hactive(1920), hsync(48), hfp(24), hbp(88)
9323 10:05:18.321755 vactive(1080), vsync(12), vfp(3), vbp(17)
9324 10:05:18.325223 anx7625_dsi_config: config dsi.
9325 10:05:18.331337 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9326 10:05:18.344271 anx7625_dsi_config: success to config DSI
9327 10:05:18.347837 anx7625_dp_start: MIPI phy setup OK.
9328 10:05:18.350876 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9329 10:05:18.354504 mtk_ddp_mode_set invalid vrefresh 60
9330 10:05:18.357754 main_disp_path_setup
9331 10:05:18.357844 ovl_layer_smi_id_en
9332 10:05:18.360755 ovl_layer_smi_id_en
9333 10:05:18.360886 ccorr_config
9334 10:05:18.360986 aal_config
9335 10:05:18.363977 gamma_config
9336 10:05:18.364077 postmask_config
9337 10:05:18.367828 dither_config
9338 10:05:18.370782 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9339 10:05:18.377457 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9340 10:05:18.380774 Root Device init finished in 551 msecs
9341 10:05:18.384382 CPU_CLUSTER: 0 init
9342 10:05:18.390557 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9343 10:05:18.394006 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9344 10:05:18.397423 APU_MBOX 0x190000b0 = 0x10001
9345 10:05:18.400492 APU_MBOX 0x190001b0 = 0x10001
9346 10:05:18.404241 APU_MBOX 0x190005b0 = 0x10001
9347 10:05:18.407096 APU_MBOX 0x190006b0 = 0x10001
9348 10:05:18.410407 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9349 10:05:18.423348 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9350 10:05:18.435727 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9351 10:05:18.442706 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9352 10:05:18.453805 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9353 10:05:18.463109 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9354 10:05:18.466095 CPU_CLUSTER: 0 init finished in 81 msecs
9355 10:05:18.469886 Devices initialized
9356 10:05:18.473269 Show all devs... After init.
9357 10:05:18.473382 Root Device: enabled 1
9358 10:05:18.476409 CPU_CLUSTER: 0: enabled 1
9359 10:05:18.479702 CPU: 00: enabled 1
9360 10:05:18.483011 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9361 10:05:18.486459 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9362 10:05:18.489608 ELOG: NV offset 0x57f000 size 0x1000
9363 10:05:18.496059 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9364 10:05:18.502606 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9365 10:05:18.506243 ELOG: Event(17) added with size 13 at 2023-06-10 10:05:05 UTC
9366 10:05:18.509553 out: cmd=0x121: 03 db 21 01 00 00 00 00
9367 10:05:18.513441 in-header: 03 a4 00 00 2c 00 00 00
9368 10:05:18.526833 in-data: bb 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9369 10:05:18.533462 ELOG: Event(A1) added with size 10 at 2023-06-10 10:05:05 UTC
9370 10:05:18.539750 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9371 10:05:18.546700 ELOG: Event(A0) added with size 9 at 2023-06-10 10:05:05 UTC
9372 10:05:18.550181 elog_add_boot_reason: Logged dev mode boot
9373 10:05:18.553329 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9374 10:05:18.556564 Finalize devices...
9375 10:05:18.556685 Devices finalized
9376 10:05:18.563006 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9377 10:05:18.566836 Writing coreboot table at 0xffe64000
9378 10:05:18.569731 0. 000000000010a000-0000000000113fff: RAMSTAGE
9379 10:05:18.573513 1. 0000000040000000-00000000400fffff: RAM
9380 10:05:18.576340 2. 0000000040100000-000000004032afff: RAMSTAGE
9381 10:05:18.582965 3. 000000004032b000-00000000545fffff: RAM
9382 10:05:18.586470 4. 0000000054600000-000000005465ffff: BL31
9383 10:05:18.589521 5. 0000000054660000-00000000ffe63fff: RAM
9384 10:05:18.593244 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9385 10:05:18.599844 7. 0000000100000000-000000023fffffff: RAM
9386 10:05:18.599975 Passing 5 GPIOs to payload:
9387 10:05:18.606312 NAME | PORT | POLARITY | VALUE
9388 10:05:18.609944 EC in RW | 0x000000aa | low | undefined
9389 10:05:18.616586 EC interrupt | 0x00000005 | low | undefined
9390 10:05:18.619633 TPM interrupt | 0x000000ab | high | undefined
9391 10:05:18.623113 SD card detect | 0x00000011 | high | undefined
9392 10:05:18.629866 speaker enable | 0x00000093 | high | undefined
9393 10:05:18.633384 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9394 10:05:18.636129 in-header: 03 f9 00 00 02 00 00 00
9395 10:05:18.636224 in-data: 02 00
9396 10:05:18.639477 ADC[4]: Raw value=905096 ID=7
9397 10:05:18.642928 ADC[3]: Raw value=213441 ID=1
9398 10:05:18.643024 RAM Code: 0x71
9399 10:05:18.646641 ADC[6]: Raw value=75332 ID=0
9400 10:05:18.649904 ADC[5]: Raw value=213072 ID=1
9401 10:05:18.650046 SKU Code: 0x1
9402 10:05:18.656465 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4e98
9403 10:05:18.659390 coreboot table: 964 bytes.
9404 10:05:18.662868 IMD ROOT 0. 0xfffff000 0x00001000
9405 10:05:18.666656 IMD SMALL 1. 0xffffe000 0x00001000
9406 10:05:18.669932 RO MCACHE 2. 0xffffc000 0x00001104
9407 10:05:18.672742 CONSOLE 3. 0xfff7c000 0x00080000
9408 10:05:18.676561 FMAP 4. 0xfff7b000 0x00000452
9409 10:05:18.679527 TIME STAMP 5. 0xfff7a000 0x00000910
9410 10:05:18.683126 VBOOT WORK 6. 0xfff66000 0x00014000
9411 10:05:18.686076 RAMOOPS 7. 0xffe66000 0x00100000
9412 10:05:18.689516 COREBOOT 8. 0xffe64000 0x00002000
9413 10:05:18.689604 IMD small region:
9414 10:05:18.692911 IMD ROOT 0. 0xffffec00 0x00000400
9415 10:05:18.696030 VPD 1. 0xffffeba0 0x0000004c
9416 10:05:18.699542 MMC STATUS 2. 0xffffeb80 0x00000004
9417 10:05:18.706725 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9418 10:05:18.706821 Probing TPM: done!
9419 10:05:18.713361 Connected to device vid:did:rid of 1ae0:0028:00
9420 10:05:18.720440 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9421 10:05:18.727166 Initialized TPM device CR50 revision 0
9422 10:05:18.727339 Checking cr50 for pending updates
9423 10:05:18.733077 Reading cr50 TPM mode
9424 10:05:18.741464 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9425 10:05:18.748148 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9426 10:05:18.788129 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9427 10:05:18.791680 Checking segment from ROM address 0x40100000
9428 10:05:18.794950 Checking segment from ROM address 0x4010001c
9429 10:05:18.801711 Loading segment from ROM address 0x40100000
9430 10:05:18.801812 code (compression=0)
9431 10:05:18.808483 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9432 10:05:18.818249 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9433 10:05:18.818359 it's not compressed!
9434 10:05:18.824821 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9435 10:05:18.828684 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9436 10:05:18.848682 Loading segment from ROM address 0x4010001c
9437 10:05:18.848853 Entry Point 0x80000000
9438 10:05:18.852369 Loaded segments
9439 10:05:18.855354 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9440 10:05:18.861921 Jumping to boot code at 0x80000000(0xffe64000)
9441 10:05:18.868656 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9442 10:05:18.875385 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9443 10:05:18.883202 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9444 10:05:18.886400 Checking segment from ROM address 0x40100000
9445 10:05:18.889931 Checking segment from ROM address 0x4010001c
9446 10:05:18.896381 Loading segment from ROM address 0x40100000
9447 10:05:18.896474 code (compression=1)
9448 10:05:18.903451 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9449 10:05:18.913095 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9450 10:05:18.913210 using LZMA
9451 10:05:18.921464 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9452 10:05:18.928254 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9453 10:05:18.931665 Loading segment from ROM address 0x4010001c
9454 10:05:18.931758 Entry Point 0x54601000
9455 10:05:18.934888 Loaded segments
9456 10:05:18.938385 NOTICE: MT8192 bl31_setup
9457 10:05:18.945861 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9458 10:05:18.948627 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9459 10:05:18.952011 WARNING: region 0:
9460 10:05:18.955199 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 10:05:18.955307 WARNING: region 1:
9462 10:05:18.962004 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9463 10:05:18.965504 WARNING: region 2:
9464 10:05:18.968789 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9465 10:05:18.971799 WARNING: region 3:
9466 10:05:18.975032 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9467 10:05:18.978399 WARNING: region 4:
9468 10:05:18.982144 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9469 10:05:18.985141 WARNING: region 5:
9470 10:05:18.988697 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 10:05:18.991705 WARNING: region 6:
9472 10:05:18.995484 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 10:05:18.995568 WARNING: region 7:
9474 10:05:19.001654 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 10:05:19.008645 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9476 10:05:19.011706 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9477 10:05:19.015149 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9478 10:05:19.022005 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9479 10:05:19.025458 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9480 10:05:19.028450 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9481 10:05:19.035456 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9482 10:05:19.038524 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9483 10:05:19.042416 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9484 10:05:19.048817 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9485 10:05:19.052199 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9486 10:05:19.055225 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9487 10:05:19.061690 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9488 10:05:19.065093 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9489 10:05:19.072118 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9490 10:05:19.075542 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9491 10:05:19.078636 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9492 10:05:19.085129 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9493 10:05:19.088864 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9494 10:05:19.091920 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9495 10:05:19.098518 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9496 10:05:19.102497 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9497 10:05:19.109206 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9498 10:05:19.112169 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9499 10:05:19.115488 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9500 10:05:19.122438 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9501 10:05:19.125262 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9502 10:05:19.132395 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9503 10:05:19.135283 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9504 10:05:19.139067 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9505 10:05:19.145867 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9506 10:05:19.148720 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9507 10:05:19.152075 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9508 10:05:19.158701 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9509 10:05:19.161996 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9510 10:05:19.165406 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9511 10:05:19.168506 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9512 10:05:19.175457 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9513 10:05:19.178889 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9514 10:05:19.182318 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9515 10:05:19.185690 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9516 10:05:19.192034 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9517 10:05:19.195780 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9518 10:05:19.199189 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9519 10:05:19.202472 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9520 10:05:19.209364 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9521 10:05:19.212253 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9522 10:05:19.216041 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9523 10:05:19.222291 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9524 10:05:19.225424 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9525 10:05:19.228739 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9526 10:05:19.235621 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9527 10:05:19.239062 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9528 10:05:19.245976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9529 10:05:19.249077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9530 10:05:19.255815 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9531 10:05:19.258964 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9532 10:05:19.262230 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9533 10:05:19.269139 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9534 10:05:19.272677 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9535 10:05:19.279497 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9536 10:05:19.282335 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9537 10:05:19.289373 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9538 10:05:19.292439 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9539 10:05:19.295624 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9540 10:05:19.302331 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9541 10:05:19.305955 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9542 10:05:19.312764 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9543 10:05:19.316267 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9544 10:05:19.319195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9545 10:05:19.325881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9546 10:05:19.329229 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9547 10:05:19.336082 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9548 10:05:19.339521 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9549 10:05:19.345868 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9550 10:05:19.349599 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9551 10:05:19.355580 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9552 10:05:19.359346 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9553 10:05:19.362413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9554 10:05:19.368997 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9555 10:05:19.372504 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9556 10:05:19.379619 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9557 10:05:19.383070 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9558 10:05:19.389047 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9559 10:05:19.392895 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9560 10:05:19.395827 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9561 10:05:19.402594 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9562 10:05:19.406107 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9563 10:05:19.412809 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9564 10:05:19.415832 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9565 10:05:19.422386 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9566 10:05:19.425623 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9567 10:05:19.429149 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9568 10:05:19.436358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9569 10:05:19.439412 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9570 10:05:19.445837 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9571 10:05:19.449033 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9572 10:05:19.452423 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9573 10:05:19.456236 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9574 10:05:19.462406 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9575 10:05:19.465954 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9576 10:05:19.469290 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9577 10:05:19.476089 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9578 10:05:19.479588 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9579 10:05:19.485828 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9580 10:05:19.490064 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9581 10:05:19.493173 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9582 10:05:19.499377 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9583 10:05:19.502870 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9584 10:05:19.509561 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9585 10:05:19.513112 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9586 10:05:19.516789 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9587 10:05:19.522922 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9588 10:05:19.526608 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9589 10:05:19.529559 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9590 10:05:19.536235 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9591 10:05:19.539737 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9592 10:05:19.542954 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9593 10:05:19.549994 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9594 10:05:19.553067 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9595 10:05:19.556452 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9596 10:05:19.559638 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9597 10:05:19.566442 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9598 10:05:19.569670 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9599 10:05:19.573064 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9600 10:05:19.579812 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9601 10:05:19.583003 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9602 10:05:19.586626 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9603 10:05:19.593456 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9604 10:05:19.596580 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9605 10:05:19.603066 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9606 10:05:19.606356 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9607 10:05:19.609876 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9608 10:05:19.616555 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9609 10:05:19.620466 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9610 10:05:19.623021 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9611 10:05:19.630238 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9612 10:05:19.633223 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9613 10:05:19.639878 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9614 10:05:19.643040 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9615 10:05:19.646626 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9616 10:05:19.653389 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9617 10:05:19.656232 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9618 10:05:19.663084 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9619 10:05:19.666415 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9620 10:05:19.669972 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9621 10:05:19.676524 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9622 10:05:19.680285 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9623 10:05:19.683522 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9624 10:05:19.690261 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9625 10:05:19.693743 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9626 10:05:19.700504 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9627 10:05:19.703259 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9628 10:05:19.706855 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9629 10:05:19.713080 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9630 10:05:19.716900 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9631 10:05:19.723105 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9632 10:05:19.726639 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9633 10:05:19.730197 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9634 10:05:19.736420 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9635 10:05:19.739708 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9636 10:05:19.745943 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9637 10:05:19.749871 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9638 10:05:19.753307 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9639 10:05:19.759836 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9640 10:05:19.763046 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9641 10:05:19.766283 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9642 10:05:19.773253 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9643 10:05:19.776195 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9644 10:05:19.783363 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9645 10:05:19.786333 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9646 10:05:19.789988 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9647 10:05:19.796143 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9648 10:05:19.799490 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9649 10:05:19.803103 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9650 10:05:19.809883 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9651 10:05:19.813227 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9652 10:05:19.819464 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9653 10:05:19.823788 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9654 10:05:19.826532 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9655 10:05:19.832791 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9656 10:05:19.836469 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9657 10:05:19.842802 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9658 10:05:19.846204 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9659 10:05:19.849687 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9660 10:05:19.856648 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9661 10:05:19.859658 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9662 10:05:19.866549 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9663 10:05:19.869416 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9664 10:05:19.872794 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9665 10:05:19.879505 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9666 10:05:19.882837 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9667 10:05:19.889485 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9668 10:05:19.893021 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9669 10:05:19.895972 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9670 10:05:19.903192 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9671 10:05:19.906907 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9672 10:05:19.912684 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9673 10:05:19.915959 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9674 10:05:19.922709 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9675 10:05:19.925992 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9676 10:05:19.929287 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9677 10:05:19.936007 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9678 10:05:19.939143 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9679 10:05:19.946206 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9680 10:05:19.949248 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9681 10:05:19.953001 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9682 10:05:19.959492 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9683 10:05:19.962611 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9684 10:05:19.969102 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9685 10:05:19.972863 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9686 10:05:19.979310 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9687 10:05:19.982459 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9688 10:05:19.985888 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9689 10:05:19.992324 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9690 10:05:19.995949 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9691 10:05:20.002372 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9692 10:05:20.006006 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9693 10:05:20.009222 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9694 10:05:20.016217 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9695 10:05:20.019435 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9696 10:05:20.026384 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9697 10:05:20.029204 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9698 10:05:20.032710 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9699 10:05:20.038952 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9700 10:05:20.042376 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9701 10:05:20.049128 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9702 10:05:20.052397 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9703 10:05:20.059387 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9704 10:05:20.062407 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9705 10:05:20.065938 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9706 10:05:20.068967 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9707 10:05:20.072547 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9708 10:05:20.079786 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9709 10:05:20.082175 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9710 10:05:20.085605 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9711 10:05:20.092329 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9712 10:05:20.095832 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9713 10:05:20.098870 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9714 10:05:20.105887 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9715 10:05:20.108738 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9716 10:05:20.115957 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9717 10:05:20.119274 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9718 10:05:20.122257 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9719 10:05:20.128645 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9720 10:05:20.132359 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9721 10:05:20.135342 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9722 10:05:20.142320 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9723 10:05:20.145416 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9724 10:05:20.148727 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9725 10:05:20.155620 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9726 10:05:20.158619 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9727 10:05:20.165332 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9728 10:05:20.168766 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9729 10:05:20.171873 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9730 10:05:20.178523 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9731 10:05:20.182151 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9732 10:05:20.186232 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9733 10:05:20.192027 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9734 10:05:20.195153 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9735 10:05:20.199082 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9736 10:05:20.205697 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9737 10:05:20.208569 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9738 10:05:20.211959 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9739 10:05:20.218743 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9740 10:05:20.222249 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9741 10:05:20.228366 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9742 10:05:20.231804 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9743 10:05:20.235195 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9744 10:05:20.242124 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9745 10:05:20.246074 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9746 10:05:20.248356 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9747 10:05:20.251999 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9748 10:05:20.255010 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9749 10:05:20.261686 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9750 10:05:20.264812 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9751 10:05:20.268338 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9752 10:05:20.271780 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9753 10:05:20.278259 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9754 10:05:20.281468 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9755 10:05:20.285110 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9756 10:05:20.291864 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9757 10:05:20.295460 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9758 10:05:20.298259 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9759 10:05:20.304481 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9760 10:05:20.307913 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9761 10:05:20.314766 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9762 10:05:20.317830 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9763 10:05:20.324412 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9764 10:05:20.327899 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9765 10:05:20.331200 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9766 10:05:20.338023 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9767 10:05:20.341098 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9768 10:05:20.347575 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9769 10:05:20.351164 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9770 10:05:20.354476 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9771 10:05:20.361217 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9772 10:05:20.364220 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9773 10:05:20.370985 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9774 10:05:20.374094 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9775 10:05:20.377671 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9776 10:05:20.384163 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9777 10:05:20.387746 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9778 10:05:20.394253 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9779 10:05:20.397766 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9780 10:05:20.401120 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9781 10:05:20.407497 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9782 10:05:20.411125 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9783 10:05:20.417537 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9784 10:05:20.421003 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9785 10:05:20.427390 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9786 10:05:20.430783 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9787 10:05:20.434665 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9788 10:05:20.440766 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9789 10:05:20.444062 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9790 10:05:20.450749 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9791 10:05:20.454093 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9792 10:05:20.457780 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9793 10:05:20.464994 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9794 10:05:20.467648 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9795 10:05:20.474203 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9796 10:05:20.477297 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9797 10:05:20.480681 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9798 10:05:20.487583 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9799 10:05:20.490688 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9800 10:05:20.497503 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9801 10:05:20.500728 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9802 10:05:20.504240 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9803 10:05:20.510756 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9804 10:05:20.514301 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9805 10:05:20.520786 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9806 10:05:20.524083 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9807 10:05:20.528095 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9808 10:05:20.534389 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9809 10:05:20.537627 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9810 10:05:20.543871 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9811 10:05:20.547355 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9812 10:05:20.550405 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9813 10:05:20.557466 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9814 10:05:20.560872 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9815 10:05:20.566989 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9816 10:05:20.570289 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9817 10:05:20.576924 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9818 10:05:20.580098 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9819 10:05:20.583858 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9820 10:05:20.590162 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9821 10:05:20.593839 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9822 10:05:20.600667 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9823 10:05:20.604055 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9824 10:05:20.607017 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9825 10:05:20.613750 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9826 10:05:20.617129 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9827 10:05:20.623555 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9828 10:05:20.627230 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9829 10:05:20.630524 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9830 10:05:20.636641 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9831 10:05:20.640207 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9832 10:05:20.646674 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9833 10:05:20.649900 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9834 10:05:20.656849 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9835 10:05:20.660425 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9836 10:05:20.663822 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9837 10:05:20.670253 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9838 10:05:20.673409 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9839 10:05:20.679992 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9840 10:05:20.683710 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9841 10:05:20.690161 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9842 10:05:20.693092 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9843 10:05:20.699877 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9844 10:05:20.703501 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9845 10:05:20.706615 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9846 10:05:20.713348 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9847 10:05:20.716900 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9848 10:05:20.723452 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9849 10:05:20.726590 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9850 10:05:20.733635 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9851 10:05:20.736713 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9852 10:05:20.739682 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9853 10:05:20.746311 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9854 10:05:20.749769 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9855 10:05:20.756302 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9856 10:05:20.760012 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9857 10:05:20.766554 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9858 10:05:20.769892 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9859 10:05:20.776406 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9860 10:05:20.779723 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9861 10:05:20.782980 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9862 10:05:20.789535 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9863 10:05:20.792904 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9864 10:05:20.799538 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9865 10:05:20.802764 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9866 10:05:20.809834 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9867 10:05:20.812779 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9868 10:05:20.816453 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9869 10:05:20.822915 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9870 10:05:20.826176 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9871 10:05:20.832716 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9872 10:05:20.836485 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9873 10:05:20.842946 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9874 10:05:20.846038 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9875 10:05:20.849334 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9876 10:05:20.856237 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9877 10:05:20.859238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9878 10:05:20.862950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9879 10:05:20.869439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9880 10:05:20.872905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9881 10:05:20.879610 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9882 10:05:20.882538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9883 10:05:20.889610 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9884 10:05:20.893147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9885 10:05:20.899056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9886 10:05:20.902782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9887 10:05:20.909714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9888 10:05:20.912940 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9889 10:05:20.919502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9890 10:05:20.922590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9891 10:05:20.929072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9892 10:05:20.932298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9893 10:05:20.938738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9894 10:05:20.942315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9895 10:05:20.948785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9896 10:05:20.952316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9897 10:05:20.958800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9898 10:05:20.962341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9899 10:05:20.969132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9900 10:05:20.972439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9901 10:05:20.978678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9902 10:05:20.981951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9903 10:05:20.989219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9904 10:05:20.991874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9905 10:05:20.998624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9906 10:05:21.002392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9907 10:05:21.008774 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9908 10:05:21.012119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9909 10:05:21.015123 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9910 10:05:21.018535 INFO: [APUAPC] vio 0
9911 10:05:21.025369 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9912 10:05:21.028376 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9913 10:05:21.031946 INFO: [APUAPC] D0_APC_0: 0x400510
9914 10:05:21.035089 INFO: [APUAPC] D0_APC_1: 0x0
9915 10:05:21.038506 INFO: [APUAPC] D0_APC_2: 0x1540
9916 10:05:21.042164 INFO: [APUAPC] D0_APC_3: 0x0
9917 10:05:21.045046 INFO: [APUAPC] D1_APC_0: 0xffffffff
9918 10:05:21.048710 INFO: [APUAPC] D1_APC_1: 0xffffffff
9919 10:05:21.051787 INFO: [APUAPC] D1_APC_2: 0x3fffff
9920 10:05:21.055141 INFO: [APUAPC] D1_APC_3: 0x0
9921 10:05:21.058466 INFO: [APUAPC] D2_APC_0: 0xffffffff
9922 10:05:21.061764 INFO: [APUAPC] D2_APC_1: 0xffffffff
9923 10:05:21.065133 INFO: [APUAPC] D2_APC_2: 0x3fffff
9924 10:05:21.065214 INFO: [APUAPC] D2_APC_3: 0x0
9925 10:05:21.071716 INFO: [APUAPC] D3_APC_0: 0xffffffff
9926 10:05:21.075053 INFO: [APUAPC] D3_APC_1: 0xffffffff
9927 10:05:21.075170 INFO: [APUAPC] D3_APC_2: 0x3fffff
9928 10:05:21.078633 INFO: [APUAPC] D3_APC_3: 0x0
9929 10:05:21.081853 INFO: [APUAPC] D4_APC_0: 0xffffffff
9930 10:05:21.085534 INFO: [APUAPC] D4_APC_1: 0xffffffff
9931 10:05:21.088499 INFO: [APUAPC] D4_APC_2: 0x3fffff
9932 10:05:21.091649 INFO: [APUAPC] D4_APC_3: 0x0
9933 10:05:21.095176 INFO: [APUAPC] D5_APC_0: 0xffffffff
9934 10:05:21.098741 INFO: [APUAPC] D5_APC_1: 0xffffffff
9935 10:05:21.101569 INFO: [APUAPC] D5_APC_2: 0x3fffff
9936 10:05:21.105608 INFO: [APUAPC] D5_APC_3: 0x0
9937 10:05:21.109026 INFO: [APUAPC] D6_APC_0: 0xffffffff
9938 10:05:21.111758 INFO: [APUAPC] D6_APC_1: 0xffffffff
9939 10:05:21.115051 INFO: [APUAPC] D6_APC_2: 0x3fffff
9940 10:05:21.118575 INFO: [APUAPC] D6_APC_3: 0x0
9941 10:05:21.121960 INFO: [APUAPC] D7_APC_0: 0xffffffff
9942 10:05:21.125024 INFO: [APUAPC] D7_APC_1: 0xffffffff
9943 10:05:21.129014 INFO: [APUAPC] D7_APC_2: 0x3fffff
9944 10:05:21.131870 INFO: [APUAPC] D7_APC_3: 0x0
9945 10:05:21.134891 INFO: [APUAPC] D8_APC_0: 0xffffffff
9946 10:05:21.138620 INFO: [APUAPC] D8_APC_1: 0xffffffff
9947 10:05:21.141429 INFO: [APUAPC] D8_APC_2: 0x3fffff
9948 10:05:21.145186 INFO: [APUAPC] D8_APC_3: 0x0
9949 10:05:21.148218 INFO: [APUAPC] D9_APC_0: 0xffffffff
9950 10:05:21.151816 INFO: [APUAPC] D9_APC_1: 0xffffffff
9951 10:05:21.154957 INFO: [APUAPC] D9_APC_2: 0x3fffff
9952 10:05:21.158452 INFO: [APUAPC] D9_APC_3: 0x0
9953 10:05:21.161620 INFO: [APUAPC] D10_APC_0: 0xffffffff
9954 10:05:21.164725 INFO: [APUAPC] D10_APC_1: 0xffffffff
9955 10:05:21.168634 INFO: [APUAPC] D10_APC_2: 0x3fffff
9956 10:05:21.171411 INFO: [APUAPC] D10_APC_3: 0x0
9957 10:05:21.174606 INFO: [APUAPC] D11_APC_0: 0xffffffff
9958 10:05:21.178057 INFO: [APUAPC] D11_APC_1: 0xffffffff
9959 10:05:21.181530 INFO: [APUAPC] D11_APC_2: 0x3fffff
9960 10:05:21.184541 INFO: [APUAPC] D11_APC_3: 0x0
9961 10:05:21.188200 INFO: [APUAPC] D12_APC_0: 0xffffffff
9962 10:05:21.191032 INFO: [APUAPC] D12_APC_1: 0xffffffff
9963 10:05:21.194828 INFO: [APUAPC] D12_APC_2: 0x3fffff
9964 10:05:21.197600 INFO: [APUAPC] D12_APC_3: 0x0
9965 10:05:21.201764 INFO: [APUAPC] D13_APC_0: 0xffffffff
9966 10:05:21.204466 INFO: [APUAPC] D13_APC_1: 0xffffffff
9967 10:05:21.208378 INFO: [APUAPC] D13_APC_2: 0x3fffff
9968 10:05:21.210907 INFO: [APUAPC] D13_APC_3: 0x0
9969 10:05:21.214364 INFO: [APUAPC] D14_APC_0: 0xffffffff
9970 10:05:21.218036 INFO: [APUAPC] D14_APC_1: 0xffffffff
9971 10:05:21.220963 INFO: [APUAPC] D14_APC_2: 0x3fffff
9972 10:05:21.224398 INFO: [APUAPC] D14_APC_3: 0x0
9973 10:05:21.227832 INFO: [APUAPC] D15_APC_0: 0xffffffff
9974 10:05:21.230857 INFO: [APUAPC] D15_APC_1: 0xffffffff
9975 10:05:21.234176 INFO: [APUAPC] D15_APC_2: 0x3fffff
9976 10:05:21.238169 INFO: [APUAPC] D15_APC_3: 0x0
9977 10:05:21.241337 INFO: [APUAPC] APC_CON: 0x4
9978 10:05:21.244320 INFO: [NOCDAPC] D0_APC_0: 0x0
9979 10:05:21.247986 INFO: [NOCDAPC] D0_APC_1: 0x0
9980 10:05:21.251014 INFO: [NOCDAPC] D1_APC_0: 0x0
9981 10:05:21.251124 INFO: [NOCDAPC] D1_APC_1: 0xfff
9982 10:05:21.254213 INFO: [NOCDAPC] D2_APC_0: 0x0
9983 10:05:21.257584 INFO: [NOCDAPC] D2_APC_1: 0xfff
9984 10:05:21.260987 INFO: [NOCDAPC] D3_APC_0: 0x0
9985 10:05:21.264083 INFO: [NOCDAPC] D3_APC_1: 0xfff
9986 10:05:21.267579 INFO: [NOCDAPC] D4_APC_0: 0x0
9987 10:05:21.271368 INFO: [NOCDAPC] D4_APC_1: 0xfff
9988 10:05:21.274532 INFO: [NOCDAPC] D5_APC_0: 0x0
9989 10:05:21.277541 INFO: [NOCDAPC] D5_APC_1: 0xfff
9990 10:05:21.280791 INFO: [NOCDAPC] D6_APC_0: 0x0
9991 10:05:21.284201 INFO: [NOCDAPC] D6_APC_1: 0xfff
9992 10:05:21.284368 INFO: [NOCDAPC] D7_APC_0: 0x0
9993 10:05:21.287599 INFO: [NOCDAPC] D7_APC_1: 0xfff
9994 10:05:21.291238 INFO: [NOCDAPC] D8_APC_0: 0x0
9995 10:05:21.294127 INFO: [NOCDAPC] D8_APC_1: 0xfff
9996 10:05:21.297714 INFO: [NOCDAPC] D9_APC_0: 0x0
9997 10:05:21.300721 INFO: [NOCDAPC] D9_APC_1: 0xfff
9998 10:05:21.304252 INFO: [NOCDAPC] D10_APC_0: 0x0
9999 10:05:21.307701 INFO: [NOCDAPC] D10_APC_1: 0xfff
10000 10:05:21.311198 INFO: [NOCDAPC] D11_APC_0: 0x0
10001 10:05:21.314232 INFO: [NOCDAPC] D11_APC_1: 0xfff
10002 10:05:21.317465 INFO: [NOCDAPC] D12_APC_0: 0x0
10003 10:05:21.320992 INFO: [NOCDAPC] D12_APC_1: 0xfff
10004 10:05:21.321168 INFO: [NOCDAPC] D13_APC_0: 0x0
10005 10:05:21.324215 INFO: [NOCDAPC] D13_APC_1: 0xfff
10006 10:05:21.327637 INFO: [NOCDAPC] D14_APC_0: 0x0
10007 10:05:21.330683 INFO: [NOCDAPC] D14_APC_1: 0xfff
10008 10:05:21.334070 INFO: [NOCDAPC] D15_APC_0: 0x0
10009 10:05:21.337452 INFO: [NOCDAPC] D15_APC_1: 0xfff
10010 10:05:21.340841 INFO: [NOCDAPC] APC_CON: 0x4
10011 10:05:21.344238 INFO: [APUAPC] set_apusys_apc done
10012 10:05:21.347565 INFO: [DEVAPC] devapc_init done
10013 10:05:21.350457 INFO: GICv3 without legacy support detected.
10014 10:05:21.354181 INFO: ARM GICv3 driver initialized in EL3
10015 10:05:21.360421 INFO: Maximum SPI INTID supported: 639
10016 10:05:21.363792 INFO: BL31: Initializing runtime services
10017 10:05:21.371003 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10018 10:05:21.371155 INFO: SPM: enable CPC mode
10019 10:05:21.377152 INFO: mcdi ready for mcusys-off-idle and system suspend
10020 10:05:21.380781 INFO: BL31: Preparing for EL3 exit to normal world
10021 10:05:21.384140 INFO: Entry point address = 0x80000000
10022 10:05:21.387252 INFO: SPSR = 0x8
10023 10:05:21.393345
10024 10:05:21.393499
10025 10:05:21.393571
10026 10:05:21.396155 Starting depthcharge on Spherion...
10027 10:05:21.396261
10028 10:05:21.396331 Wipe memory regions:
10029 10:05:21.396395
10030 10:05:21.397086 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10031 10:05:21.397195 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10032 10:05:21.397282 Setting prompt string to ['asurada:']
10033 10:05:21.397362 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10034 10:05:21.399859 [0x00000040000000, 0x00000054600000)
10035 10:05:21.521807
10036 10:05:21.521987 [0x00000054660000, 0x00000080000000)
10037 10:05:21.782642
10038 10:05:21.782841 [0x000000821a7280, 0x000000ffe64000)
10039 10:05:22.527183
10040 10:05:22.527355 [0x00000100000000, 0x00000240000000)
10041 10:05:24.416567
10042 10:05:24.420139 Initializing XHCI USB controller at 0x11200000.
10043 10:05:25.457697
10044 10:05:25.461260 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10045 10:05:25.461380
10046 10:05:25.461487
10047 10:05:25.461579
10048 10:05:25.461890 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10050 10:05:25.562235 asurada: tftpboot 192.168.201.1 10670697/tftp-deploy-artaceso/kernel/image.itb 10670697/tftp-deploy-artaceso/kernel/cmdline
10051 10:05:25.562368 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10052 10:05:25.562460 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10053 10:05:25.566339 tftpboot 192.168.201.1 10670697/tftp-deploy-artaceso/kernel/image.ittp-deploy-artaceso/kernel/cmdline
10054 10:05:25.566456
10055 10:05:25.566552 Waiting for link
10056 10:05:25.727195
10057 10:05:25.727348 R8152: Initializing
10058 10:05:25.727458
10059 10:05:25.730237 Version 9 (ocp_data = 6010)
10060 10:05:25.730338
10061 10:05:25.733497 R8152: Done initializing
10062 10:05:25.733572
10063 10:05:25.733636 Adding net device
10064 10:05:27.606211
10065 10:05:27.606358 done.
10066 10:05:27.606466
10067 10:05:27.606559 MAC: 00:e0:4c:78:7a:aa
10068 10:05:27.606649
10069 10:05:27.609407 Sending DHCP discover... done.
10070 10:05:27.609520
10071 10:05:27.613220 Waiting for reply... done.
10072 10:05:27.613305
10073 10:05:27.616451 Sending DHCP request... done.
10074 10:05:27.616555
10075 10:05:27.623787 Waiting for reply... done.
10076 10:05:27.623893
10077 10:05:27.623993 My ip is 192.168.201.12
10078 10:05:27.624063
10079 10:05:27.627130 The DHCP server ip is 192.168.201.1
10080 10:05:27.627229
10081 10:05:27.633845 TFTP server IP predefined by user: 192.168.201.1
10082 10:05:27.633979
10083 10:05:27.640352 Bootfile predefined by user: 10670697/tftp-deploy-artaceso/kernel/image.itb
10084 10:05:27.640461
10085 10:05:27.640554 Sending tftp read request... done.
10086 10:05:27.643837
10087 10:05:27.646869 Waiting for the transfer...
10088 10:05:27.646978
10089 10:05:27.896430 00000000 ################################################################
10090 10:05:27.896594
10091 10:05:28.146018 00080000 ################################################################
10092 10:05:28.146154
10093 10:05:28.401311 00100000 ################################################################
10094 10:05:28.401449
10095 10:05:28.654165 00180000 ################################################################
10096 10:05:28.654313
10097 10:05:28.903555 00200000 ################################################################
10098 10:05:28.903692
10099 10:05:29.152404 00280000 ################################################################
10100 10:05:29.152541
10101 10:05:29.397151 00300000 ################################################################
10102 10:05:29.397311
10103 10:05:29.641638 00380000 ################################################################
10104 10:05:29.641817
10105 10:05:29.894492 00400000 ################################################################
10106 10:05:29.894653
10107 10:05:30.145583 00480000 ################################################################
10108 10:05:30.145723
10109 10:05:30.394344 00500000 ################################################################
10110 10:05:30.394508
10111 10:05:30.655264 00580000 ################################################################
10112 10:05:30.655465
10113 10:05:30.908797 00600000 ################################################################
10114 10:05:30.908979
10115 10:05:31.153697 00680000 ################################################################
10116 10:05:31.153863
10117 10:05:31.402342 00700000 ################################################################
10118 10:05:31.402474
10119 10:05:31.660190 00780000 ################################################################
10120 10:05:31.660355
10121 10:05:31.916453 00800000 ################################################################
10122 10:05:31.916612
10123 10:05:32.176507 00880000 ################################################################
10124 10:05:32.176676
10125 10:05:32.424748 00900000 ################################################################
10126 10:05:32.424918
10127 10:05:35.311958 00980000 ################################################################
10128 10:05:35.312173
10129 10:05:35.312293 00a00000 ################################################################
10130 10:05:35.312389
10131 10:05:35.312480 00a80000 ################################################################
10132 10:05:35.312580
10133 10:05:35.312698 00b00000 ################################################################
10134 10:05:35.312791
10135 10:05:35.312866 00b80000 ################################################################
10136 10:05:35.312925
10137 10:05:35.312982 00c00000 ################################################################
10138 10:05:35.313039
10139 10:05:35.313093 00c80000 ################################################################
10140 10:05:35.313148
10141 10:05:35.313201 00d00000 ################################################################
10142 10:05:35.313261
10143 10:05:35.313320 00d80000 ################################################################
10144 10:05:35.313376
10145 10:05:35.313429 00e00000 ################################################################
10146 10:05:35.313484
10147 10:05:35.313537 00e80000 ################################################################
10148 10:05:35.313592
10149 10:05:35.412903 00f00000 ################################################################
10150 10:05:35.413040
10151 10:05:35.664759 00f80000 ################################################################
10152 10:05:35.664922
10153 10:05:35.908145 01000000 ################################################################
10154 10:05:35.908282
10155 10:05:36.149242 01080000 ################################################################
10156 10:05:36.149378
10157 10:05:36.391046 01100000 ################################################################
10158 10:05:36.391184
10159 10:05:36.633511 01180000 ################################################################
10160 10:05:36.633664
10161 10:05:36.874978 01200000 ################################################################
10162 10:05:36.875153
10163 10:05:37.116765 01280000 ################################################################
10164 10:05:37.116956
10165 10:05:37.368983 01300000 ################################################################
10166 10:05:37.369131
10167 10:05:37.626339 01380000 ################################################################
10168 10:05:37.626487
10169 10:05:37.873277 01400000 ################################################################
10170 10:05:37.873427
10171 10:05:38.115632 01480000 ################################################################
10172 10:05:38.115786
10173 10:05:38.359650 01500000 ################################################################
10174 10:05:38.359804
10175 10:05:38.609980 01580000 ################################################################
10176 10:05:38.610142
10177 10:05:38.864477 01600000 ################################################################
10178 10:05:38.864632
10179 10:05:39.111482 01680000 ################################################################
10180 10:05:39.111661
10181 10:05:39.363534 01700000 ################################################################
10182 10:05:39.363683
10183 10:05:39.609219 01780000 ################################################################
10184 10:05:39.609398
10185 10:05:39.855840 01800000 ################################################################
10186 10:05:39.855986
10187 10:05:40.110681 01880000 ################################################################
10188 10:05:40.110840
10189 10:05:40.354968 01900000 ################################################################
10190 10:05:40.355147
10191 10:05:40.599912 01980000 ################################################################
10192 10:05:40.600075
10193 10:05:40.846982 01a00000 ################################################################
10194 10:05:40.847145
10195 10:05:41.096093 01a80000 ################################################################
10196 10:05:41.096231
10197 10:05:41.350526 01b00000 ################################################################
10198 10:05:41.350698
10199 10:05:41.603296 01b80000 ################################################################
10200 10:05:41.603434
10201 10:05:41.862391 01c00000 ################################################################
10202 10:05:41.862569
10203 10:05:42.125567 01c80000 ################################################################
10204 10:05:42.125719
10205 10:05:42.375375 01d00000 ################################################################
10206 10:05:42.375528
10207 10:05:42.631742 01d80000 ################################################################
10208 10:05:42.631880
10209 10:05:42.888475 01e00000 ################################################################
10210 10:05:42.888624
10211 10:05:43.160045 01e80000 ################################################################
10212 10:05:43.160215
10213 10:05:43.429811 01f00000 ################################################################
10214 10:05:43.429962
10215 10:05:43.684909 01f80000 ################################################################
10216 10:05:43.685052
10217 10:05:43.946507 02000000 ################################################################
10218 10:05:43.946679
10219 10:05:44.190778 02080000 ################################################################
10220 10:05:44.190926
10221 10:05:44.439272 02100000 ################################################################
10222 10:05:44.439402
10223 10:05:44.685835 02180000 ################################################################
10224 10:05:44.685980
10225 10:05:44.939751 02200000 ################################################################
10226 10:05:44.939924
10227 10:05:45.207055 02280000 ################################################################
10228 10:05:45.207194
10229 10:05:45.458838 02300000 ################################################################
10230 10:05:45.458979
10231 10:05:45.739911 02380000 ################################################################
10232 10:05:45.740049
10233 10:05:46.001023 02400000 ################################################################
10234 10:05:46.001159
10235 10:05:46.282196 02480000 ################################################################
10236 10:05:46.282333
10237 10:05:46.560093 02500000 ################################################################
10238 10:05:46.560257
10239 10:05:46.827053 02580000 ################################################################
10240 10:05:46.827194
10241 10:05:47.103132 02600000 ################################################################
10242 10:05:47.103275
10243 10:05:47.391483 02680000 ################################################################
10244 10:05:47.391634
10245 10:05:47.681602 02700000 ################################################################
10246 10:05:47.681737
10247 10:05:47.959811 02780000 ################################################################
10248 10:05:47.959967
10249 10:05:48.239290 02800000 ################################################################
10250 10:05:48.239452
10251 10:05:48.507656 02880000 ################################################################
10252 10:05:48.507806
10253 10:05:48.780643 02900000 ################################################################
10254 10:05:48.780852
10255 10:05:49.045231 02980000 ################################################################
10256 10:05:49.045391
10257 10:05:49.299400 02a00000 ################################################################
10258 10:05:49.299543
10259 10:05:49.565897 02a80000 ################################################################
10260 10:05:49.566072
10261 10:05:49.828323 02b00000 ################################################################
10262 10:05:49.828467
10263 10:05:50.082607 02b80000 ################################################################
10264 10:05:50.082750
10265 10:05:50.339415 02c00000 ################################################################
10266 10:05:50.339555
10267 10:05:50.590513 02c80000 ################################################################
10268 10:05:50.590644
10269 10:05:50.841811 02d00000 ################################################################
10270 10:05:50.841951
10271 10:05:51.095875 02d80000 ################################################################
10272 10:05:51.096027
10273 10:05:51.352799 02e00000 ################################################################
10274 10:05:51.352982
10275 10:05:51.610938 02e80000 ################################################################
10276 10:05:51.611128
10277 10:05:51.880052 02f00000 ################################################################
10278 10:05:51.880219
10279 10:05:52.144444 02f80000 ################################################################
10280 10:05:52.144619
10281 10:05:52.406885 03000000 ################################################################
10282 10:05:52.407035
10283 10:05:52.664973 03080000 ################################################################
10284 10:05:52.665130
10285 10:05:52.925239 03100000 ################################################################
10286 10:05:52.925456
10287 10:05:53.197260 03180000 ################################################################
10288 10:05:53.197404
10289 10:05:53.480382 03200000 ################################################################
10290 10:05:53.480519
10291 10:05:53.732550 03280000 ################################################################
10292 10:05:53.732710
10293 10:05:53.979919 03300000 ################################################################
10294 10:05:53.980083
10295 10:05:54.258468 03380000 ################################################################
10296 10:05:54.258604
10297 10:05:54.548685 03400000 ################################################################
10298 10:05:54.548859
10299 10:05:54.797721 03480000 ################################################################
10300 10:05:54.797859
10301 10:05:55.062371 03500000 ################################################################
10302 10:05:55.062504
10303 10:05:55.337094 03580000 ################################################################
10304 10:05:55.337229
10305 10:05:55.592114 03600000 ################################################################
10306 10:05:55.592255
10307 10:05:55.779724 03680000 ############################################### done.
10308 10:05:55.779887
10309 10:05:55.783246 The bootfile was 57524774 bytes long.
10310 10:05:55.783333
10311 10:05:55.786762 Sending tftp read request... done.
10312 10:05:55.786848
10313 10:05:55.786916 Waiting for the transfer...
10314 10:05:55.789682
10315 10:05:55.789772 00000000 # done.
10316 10:05:55.789841
10317 10:05:55.796432 Command line loaded dynamically from TFTP file: 10670697/tftp-deploy-artaceso/kernel/cmdline
10318 10:05:55.796516
10319 10:05:55.809520 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10320 10:05:55.809606
10321 10:05:55.809674 Loading FIT.
10322 10:05:55.809748
10323 10:05:55.812714 Image ramdisk-1 has 47388497 bytes.
10324 10:05:55.812856
10325 10:05:55.816329 Image fdt-1 has 46924 bytes.
10326 10:05:55.816411
10327 10:05:55.819438 Image kernel-1 has 10087317 bytes.
10328 10:05:55.819520
10329 10:05:55.829683 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10330 10:05:55.829795
10331 10:05:55.846211 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10332 10:05:55.846300
10333 10:05:55.849485 Choosing best match conf-1 for compat google,spherion-rev2.
10334 10:05:55.854932
10335 10:05:55.859937 Connected to device vid:did:rid of 1ae0:0028:00
10336 10:05:55.867983
10337 10:05:55.871046 tpm_get_response: command 0x17b, return code 0x0
10338 10:05:55.871136
10339 10:05:55.874127 ec_init: CrosEC protocol v3 supported (256, 248)
10340 10:05:55.878651
10341 10:05:55.881856 tpm_cleanup: add release locality here.
10342 10:05:55.881939
10343 10:05:55.882005 Shutting down all USB controllers.
10344 10:05:55.884933
10345 10:05:55.885032 Removing current net device
10346 10:05:55.885098
10347 10:05:55.891621 Exiting depthcharge with code 4 at timestamp: 63825068
10348 10:05:55.891704
10349 10:05:55.895039 LZMA decompressing kernel-1 to 0x821a6718
10350 10:05:55.895121
10351 10:05:55.898204 LZMA decompressing kernel-1 to 0x40000000
10352 10:05:57.451702
10353 10:05:57.451927 jumping to kernel
10354 10:05:57.452069
10355 10:05:57.452204 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10356 10:05:57.452339 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j19381-arm64-gcc-10-defconfig-arm64-chromebook-d6qsg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023
10357 10:05:57.452462 [ 0.000000] random: crng init done
10358 10:05:57.452574 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10359 10:05:57.452722 [ 0.000000] efi: UEFI not found.
10360 10:05:57.452878 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10361 10:05:57.452992 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10362 10:05:57.453107 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10363 10:05:57.453181 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10364 10:05:57.453240 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10365 10:05:57.453297 [ 0.000000] printk: bootconsole [mtk8250] enabled
10366 10:05:57.453352 [ 0.000000] NUMA: No NUMA configuration found
10367 10:05:57.453407 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10368 10:05:57.453461 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10369 10:05:57.453514 [ 0.000000] Zone ranges:
10370 10:05:57.453568 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10371 10:05:57.453622 [ 0.000000] DMA32 empty
10372 10:05:57.453675 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10373 10:05:57.453729 [ 0.000000] Movable zone start for each node
10374 10:05:57.453783 [ 0.000000] Early memory node ranges
10375 10:05:57.453903 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10376 10:05:57.453988 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10377 10:05:57.454072 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10378 10:05:57.454155 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10379 10:05:57.454239 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10380 10:05:57.454322 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10381 10:05:57.455023 end: 2.2.4 bootloader-commands (duration 00:00:36) [common]
10382 10:05:57.455153 start: 2.2.5 auto-login-action (timeout 00:03:49) [common]
10383 10:05:57.455255 Setting prompt string to ['Linux version [0-9]']
10384 10:05:57.455352 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10385 10:05:57.455447 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10386 10:05:57.455866 start: 2.2.5.1 login-action (timeout 00:03:49) [common]
10387 10:05:57.455991 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10388 10:05:57.456115 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10389 10:05:57.456217 Using line separator: #'\n'#
10390 10:05:57.456305 No login prompt set.
10391 10:05:57.456394 Parsing kernel messages
10392 10:05:57.456476 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10393 10:05:57.456643 [login-action] Waiting for messages, (timeout 00:03:49)
10394 10:05:57.471028 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10395 10:05:57.477917 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10396 10:05:57.484607 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10397 10:05:57.487927 [ 0.000000] psci: probing for conduit method from DT.
10398 10:05:57.494816 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10399 10:05:57.497981 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10400 10:05:57.504236 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10401 10:05:57.507761 [ 0.000000] psci: SMC Calling Convention v1.2
10402 10:05:57.514443 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10403 10:05:57.517882 [ 0.000000] Detected VIPT I-cache on CPU0
10404 10:05:57.524214 [ 0.000000] CPU features: detected: GIC system register CPU interface
10405 10:05:57.530845 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10406 10:05:57.537818 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10407 10:05:57.544107 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10408 10:05:57.551496 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10409 10:05:57.557687 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10410 10:05:57.564205 [ 0.000000] alternatives: applying boot alternatives
10411 10:05:57.567606 [ 0.000000] Fallback order for Node 0: 0
10412 10:05:57.577095 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10413 10:05:57.577236 [ 0.000000] Policy zone: Normal
10414 10:05:57.590481 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10415 10:05:57.600869 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10416 10:05:57.613152 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10417 10:05:57.623185 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10418 10:05:57.630242 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10419 10:05:57.633321 <6>[ 0.000000] software IO TLB: area num 8.
10420 10:05:57.690518 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10421 10:05:57.839369 <6>[ 0.000000] Memory: 7926664K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 426104K reserved, 32768K cma-reserved)
10422 10:05:57.846255 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10423 10:05:57.852535 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10424 10:05:57.856118 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10425 10:05:57.862684 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10426 10:05:57.869601 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10427 10:05:57.872567 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10428 10:05:57.882519 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10429 10:05:57.889384 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10430 10:05:57.892734 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10431 10:05:57.900284 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10432 10:05:57.903755 <6>[ 0.000000] GICv3: 608 SPIs implemented
10433 10:05:57.910157 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10434 10:05:57.913674 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10435 10:05:57.917117 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10436 10:05:57.927021 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10437 10:05:57.936667 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10438 10:05:57.950263 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10439 10:05:57.956511 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10440 10:05:57.966304 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10441 10:05:57.979372 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10442 10:05:57.986258 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10443 10:05:57.992539 <6>[ 0.009173] Console: colour dummy device 80x25
10444 10:05:58.002289 <6>[ 0.013931] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10445 10:05:58.005562 <6>[ 0.024373] pid_max: default: 32768 minimum: 301
10446 10:05:58.012506 <6>[ 0.029247] LSM: Security Framework initializing
10447 10:05:58.019080 <6>[ 0.034186] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10448 10:05:58.028767 <6>[ 0.042049] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10449 10:05:58.035523 <6>[ 0.051530] cblist_init_generic: Setting adjustable number of callback queues.
10450 10:05:58.042543 <6>[ 0.058982] cblist_init_generic: Setting shift to 3 and lim to 1.
10451 10:05:58.048966 <6>[ 0.065320] cblist_init_generic: Setting shift to 3 and lim to 1.
10452 10:05:58.055265 <6>[ 0.071766] rcu: Hierarchical SRCU implementation.
10453 10:05:58.061747 <6>[ 0.076811] rcu: Max phase no-delay instances is 1000.
10454 10:05:58.065118 <6>[ 0.083831] EFI services will not be available.
10455 10:05:58.071649 <6>[ 0.088802] smp: Bringing up secondary CPUs ...
10456 10:05:58.079658 <6>[ 0.093853] Detected VIPT I-cache on CPU1
10457 10:05:58.085902 <6>[ 0.093925] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10458 10:05:58.092730 <6>[ 0.093958] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10459 10:05:58.095892 <6>[ 0.094296] Detected VIPT I-cache on CPU2
10460 10:05:58.102901 <6>[ 0.094345] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10461 10:05:58.112354 <6>[ 0.094361] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10462 10:05:58.116100 <6>[ 0.094623] Detected VIPT I-cache on CPU3
10463 10:05:58.122282 <6>[ 0.094669] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10464 10:05:58.129307 <6>[ 0.094683] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10465 10:05:58.132529 <6>[ 0.094990] CPU features: detected: Spectre-v4
10466 10:05:58.138854 <6>[ 0.094996] CPU features: detected: Spectre-BHB
10467 10:05:58.142202 <6>[ 0.095002] Detected PIPT I-cache on CPU4
10468 10:05:58.149065 <6>[ 0.095061] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10469 10:05:58.156098 <6>[ 0.095077] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10470 10:05:58.162471 <6>[ 0.095374] Detected PIPT I-cache on CPU5
10471 10:05:58.168953 <6>[ 0.095439] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10472 10:05:58.175598 <6>[ 0.095455] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10473 10:05:58.178766 <6>[ 0.095739] Detected PIPT I-cache on CPU6
10474 10:05:58.185636 <6>[ 0.095805] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10475 10:05:58.192331 <6>[ 0.095821] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10476 10:05:58.198751 <6>[ 0.096119] Detected PIPT I-cache on CPU7
10477 10:05:58.205722 <6>[ 0.096184] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10478 10:05:58.211922 <6>[ 0.096200] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10479 10:05:58.215492 <6>[ 0.096249] smp: Brought up 1 node, 8 CPUs
10480 10:05:58.222164 <6>[ 0.237565] SMP: Total of 8 processors activated.
10481 10:05:58.225228 <6>[ 0.242516] CPU features: detected: 32-bit EL0 Support
10482 10:05:58.235129 <6>[ 0.247879] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10483 10:05:58.241941 <6>[ 0.256678] CPU features: detected: Common not Private translations
10484 10:05:58.245355 <6>[ 0.263154] CPU features: detected: CRC32 instructions
10485 10:05:58.251811 <6>[ 0.268506] CPU features: detected: RCpc load-acquire (LDAPR)
10486 10:05:58.258081 <6>[ 0.274503] CPU features: detected: LSE atomic instructions
10487 10:05:58.264838 <6>[ 0.280320] CPU features: detected: Privileged Access Never
10488 10:05:58.271501 <6>[ 0.286136] CPU features: detected: RAS Extension Support
10489 10:05:58.278151 <6>[ 0.291779] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10490 10:05:58.281544 <6>[ 0.299042] CPU: All CPU(s) started at EL2
10491 10:05:58.288117 <6>[ 0.303359] alternatives: applying system-wide alternatives
10492 10:05:58.297500 <6>[ 0.314075] devtmpfs: initialized
10493 10:05:58.309493 <6>[ 0.323020] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10494 10:05:58.319976 <6>[ 0.332985] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10495 10:05:58.326593 <6>[ 0.340999] pinctrl core: initialized pinctrl subsystem
10496 10:05:58.329431 <6>[ 0.347654] DMI not present or invalid.
10497 10:05:58.336075 <6>[ 0.352066] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10498 10:05:58.346165 <6>[ 0.358891] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10499 10:05:58.352671 <6>[ 0.366473] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10500 10:05:58.362624 <6>[ 0.374691] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10501 10:05:58.366036 <6>[ 0.382935] audit: initializing netlink subsys (disabled)
10502 10:05:58.376014 <5>[ 0.388630] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10503 10:05:58.382497 <6>[ 0.389343] thermal_sys: Registered thermal governor 'step_wise'
10504 10:05:58.388927 <6>[ 0.396597] thermal_sys: Registered thermal governor 'power_allocator'
10505 10:05:58.392990 <6>[ 0.402850] cpuidle: using governor menu
10506 10:05:58.395723 <6>[ 0.413812] NET: Registered PF_QIPCRTR protocol family
10507 10:05:58.405817 <6>[ 0.419286] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10508 10:05:58.408970 <6>[ 0.426385] ASID allocator initialised with 32768 entries
10509 10:05:58.415891 <6>[ 0.432961] Serial: AMBA PL011 UART driver
10510 10:05:58.425022 <4>[ 0.441670] Trying to register duplicate clock ID: 134
10511 10:05:58.481095 <6>[ 0.501039] KASLR enabled
10512 10:05:58.495182 <6>[ 0.508831] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10513 10:05:58.501722 <6>[ 0.515845] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10514 10:05:58.508564 <6>[ 0.522331] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10515 10:05:58.514970 <6>[ 0.529333] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10516 10:05:58.522115 <6>[ 0.535820] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10517 10:05:58.528732 <6>[ 0.542825] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10518 10:05:58.534914 <6>[ 0.549308] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10519 10:05:58.541534 <6>[ 0.556315] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10520 10:05:58.545018 <6>[ 0.563853] ACPI: Interpreter disabled.
10521 10:05:58.553278 <6>[ 0.570256] iommu: Default domain type: Translated
10522 10:05:58.560152 <6>[ 0.575369] iommu: DMA domain TLB invalidation policy: strict mode
10523 10:05:58.563109 <5>[ 0.582024] SCSI subsystem initialized
10524 10:05:58.570204 <6>[ 0.586193] usbcore: registered new interface driver usbfs
10525 10:05:58.576359 <6>[ 0.591924] usbcore: registered new interface driver hub
10526 10:05:58.579954 <6>[ 0.597475] usbcore: registered new device driver usb
10527 10:05:58.586717 <6>[ 0.603572] pps_core: LinuxPPS API ver. 1 registered
10528 10:05:58.596304 <6>[ 0.608767] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10529 10:05:58.599830 <6>[ 0.618115] PTP clock support registered
10530 10:05:58.602961 <6>[ 0.622356] EDAC MC: Ver: 3.0.0
10531 10:05:58.610976 <6>[ 0.627504] FPGA manager framework
10532 10:05:58.614264 <6>[ 0.631187] Advanced Linux Sound Architecture Driver Initialized.
10533 10:05:58.618115 <6>[ 0.637968] vgaarb: loaded
10534 10:05:58.624375 <6>[ 0.641130] clocksource: Switched to clocksource arch_sys_counter
10535 10:05:58.631059 <5>[ 0.647574] VFS: Disk quotas dquot_6.6.0
10536 10:05:58.637873 <6>[ 0.651761] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10537 10:05:58.641079 <6>[ 0.658949] pnp: PnP ACPI: disabled
10538 10:05:58.648935 <6>[ 0.665733] NET: Registered PF_INET protocol family
10539 10:05:58.658655 <6>[ 0.671328] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10540 10:05:58.670226 <6>[ 0.683648] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10541 10:05:58.680170 <6>[ 0.692467] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10542 10:05:58.686397 <6>[ 0.700438] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10543 10:05:58.693243 <6>[ 0.709143] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10544 10:05:58.705156 <6>[ 0.718882] TCP: Hash tables configured (established 65536 bind 65536)
10545 10:05:58.712148 <6>[ 0.725745] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10546 10:05:58.718506 <6>[ 0.732946] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10547 10:05:58.725392 <6>[ 0.740648] NET: Registered PF_UNIX/PF_LOCAL protocol family
10548 10:05:58.732140 <6>[ 0.746793] RPC: Registered named UNIX socket transport module.
10549 10:05:58.735153 <6>[ 0.752946] RPC: Registered udp transport module.
10550 10:05:58.741857 <6>[ 0.757877] RPC: Registered tcp transport module.
10551 10:05:58.748749 <6>[ 0.762809] RPC: Registered tcp NFSv4.1 backchannel transport module.
10552 10:05:58.751906 <6>[ 0.769471] PCI: CLS 0 bytes, default 64
10553 10:05:58.755478 <6>[ 0.773822] Unpacking initramfs...
10554 10:05:58.765770 <6>[ 0.777899] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10555 10:05:58.772142 <6>[ 0.786545] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10556 10:05:58.778550 <6>[ 0.795380] kvm [1]: IPA Size Limit: 40 bits
10557 10:05:58.781817 <6>[ 0.799908] kvm [1]: GICv3: no GICV resource entry
10558 10:05:58.788143 <6>[ 0.804929] kvm [1]: disabling GICv2 emulation
10559 10:05:58.794801 <6>[ 0.809618] kvm [1]: GIC system register CPU interface enabled
10560 10:05:58.798354 <6>[ 0.815796] kvm [1]: vgic interrupt IRQ18
10561 10:05:58.804717 <6>[ 0.820155] kvm [1]: VHE mode initialized successfully
10562 10:05:58.807994 <5>[ 0.826578] Initialise system trusted keyrings
10563 10:05:58.814831 <6>[ 0.831373] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10564 10:05:58.824465 <6>[ 0.841372] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10565 10:05:58.830927 <5>[ 0.847781] NFS: Registering the id_resolver key type
10566 10:05:58.834666 <5>[ 0.853084] Key type id_resolver registered
10567 10:05:58.841220 <5>[ 0.857501] Key type id_legacy registered
10568 10:05:58.847596 <6>[ 0.861775] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10569 10:05:58.854388 <6>[ 0.868695] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10570 10:05:58.860725 <6>[ 0.876400] 9p: Installing v9fs 9p2000 file system support
10571 10:05:58.897356 <5>[ 0.914263] Key type asymmetric registered
10572 10:05:58.900459 <5>[ 0.918595] Asymmetric key parser 'x509' registered
10573 10:05:58.910637 <6>[ 0.923740] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10574 10:05:58.913802 <6>[ 0.931354] io scheduler mq-deadline registered
10575 10:05:58.916986 <6>[ 0.936115] io scheduler kyber registered
10576 10:05:58.935661 <6>[ 0.952869] EINJ: ACPI disabled.
10577 10:05:58.967926 <4>[ 0.978099] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10578 10:05:58.977848 <4>[ 0.988742] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10579 10:05:58.992302 <6>[ 1.009258] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10580 10:05:59.000292 <6>[ 1.017280] printk: console [ttyS0] disabled
10581 10:05:59.028544 <6>[ 1.041933] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10582 10:05:59.034907 <6>[ 1.051418] printk: console [ttyS0] enabled
10583 10:05:59.038614 <6>[ 1.051418] printk: console [ttyS0] enabled
10584 10:05:59.044982 <6>[ 1.060310] printk: bootconsole [mtk8250] disabled
10585 10:05:59.048450 <6>[ 1.060310] printk: bootconsole [mtk8250] disabled
10586 10:05:59.055285 <6>[ 1.071563] SuperH (H)SCI(F) driver initialized
10587 10:05:59.058358 <6>[ 1.076841] msm_serial: driver initialized
10588 10:05:59.072299 <6>[ 1.085773] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10589 10:05:59.082015 <6>[ 1.094318] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10590 10:05:59.088682 <6>[ 1.102862] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10591 10:05:59.098561 <6>[ 1.111491] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10592 10:05:59.105285 <6>[ 1.120196] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10593 10:05:59.115246 <6>[ 1.128910] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10594 10:05:59.125214 <6>[ 1.137451] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10595 10:05:59.132180 <6>[ 1.146276] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10596 10:05:59.141745 <6>[ 1.154824] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10597 10:05:59.150429 <6>[ 1.170568] loop: module loaded
10598 10:05:59.159554 <6>[ 1.176521] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10599 10:05:59.182640 <4>[ 1.199849] mtk-pmic-keys: Failed to locate of_node [id: -1]
10600 10:05:59.189374 <6>[ 1.206636] megasas: 07.719.03.00-rc1
10601 10:05:59.199397 <6>[ 1.216046] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10602 10:05:59.207424 <6>[ 1.224496] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10603 10:05:59.224771 <6>[ 1.241233] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10604 10:05:59.281323 <6>[ 1.291787] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10605 10:06:00.742580 <6>[ 2.759369] Freeing initrd memory: 46272K
10606 10:06:00.752511 <6>[ 2.769671] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10607 10:06:00.763443 <6>[ 2.780598] tun: Universal TUN/TAP device driver, 1.6
10608 10:06:00.766815 <6>[ 2.786650] thunder_xcv, ver 1.0
10609 10:06:00.769828 <6>[ 2.790155] thunder_bgx, ver 1.0
10610 10:06:00.773168 <6>[ 2.793651] nicpf, ver 1.0
10611 10:06:00.783984 <6>[ 2.797658] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10612 10:06:00.787132 <6>[ 2.805135] hns3: Copyright (c) 2017 Huawei Corporation.
10613 10:06:00.794011 <6>[ 2.810722] hclge is initializing
10614 10:06:00.797209 <6>[ 2.814308] e1000: Intel(R) PRO/1000 Network Driver
10615 10:06:00.803514 <6>[ 2.819438] e1000: Copyright (c) 1999-2006 Intel Corporation.
10616 10:06:00.807283 <6>[ 2.825455] e1000e: Intel(R) PRO/1000 Network Driver
10617 10:06:00.813593 <6>[ 2.830671] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10618 10:06:00.820367 <6>[ 2.836856] igb: Intel(R) Gigabit Ethernet Network Driver
10619 10:06:00.827120 <6>[ 2.842506] igb: Copyright (c) 2007-2014 Intel Corporation.
10620 10:06:00.833823 <6>[ 2.848341] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10621 10:06:00.839994 <6>[ 2.854859] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10622 10:06:00.843595 <6>[ 2.861324] sky2: driver version 1.30
10623 10:06:00.849877 <6>[ 2.866299] VFIO - User Level meta-driver version: 0.3
10624 10:06:00.857338 <6>[ 2.874507] usbcore: registered new interface driver usb-storage
10625 10:06:00.863844 <6>[ 2.880950] usbcore: registered new device driver onboard-usb-hub
10626 10:06:00.872990 <6>[ 2.890027] mt6397-rtc mt6359-rtc: registered as rtc0
10627 10:06:00.883173 <6>[ 2.895495] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-10T10:05:48 UTC (1686391548)
10628 10:06:00.885963 <6>[ 2.905063] i2c_dev: i2c /dev entries driver
10629 10:06:00.902684 <6>[ 2.916731] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10630 10:06:00.910187 <6>[ 2.926930] sdhci: Secure Digital Host Controller Interface driver
10631 10:06:00.916418 <6>[ 2.933368] sdhci: Copyright(c) Pierre Ossman
10632 10:06:00.923246 <6>[ 2.938762] Synopsys Designware Multimedia Card Interface Driver
10633 10:06:00.926342 <6>[ 2.945394] mmc0: CQHCI version 5.10
10634 10:06:00.932691 <6>[ 2.945924] sdhci-pltfm: SDHCI platform and OF driver helper
10635 10:06:00.939977 <6>[ 2.957414] ledtrig-cpu: registered to indicate activity on CPUs
10636 10:06:00.951277 <6>[ 2.964917] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10637 10:06:00.957705 <6>[ 2.972330] usbcore: registered new interface driver usbhid
10638 10:06:00.961161 <6>[ 2.978165] usbhid: USB HID core driver
10639 10:06:00.967724 <6>[ 2.982407] spi_master spi0: will run message pump with realtime priority
10640 10:06:01.011211 <6>[ 3.021458] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10641 10:06:01.029202 <6>[ 3.036725] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10642 10:06:01.033067 <6>[ 3.050327] mmc0: Command Queue Engine enabled
10643 10:06:01.039663 <6>[ 3.055084] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10644 10:06:01.046727 <6>[ 3.062017] cros-ec-spi spi0.0: Chrome EC device registered
10645 10:06:01.049642 <6>[ 3.062412] mmcblk0: mmc0:0001 DA4128 116 GiB
10646 10:06:01.060062 <6>[ 3.077310] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10647 10:06:01.067548 <6>[ 3.084602] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10648 10:06:01.074267 <6>[ 3.090591] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10649 10:06:01.080649 <6>[ 3.096597] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10650 10:06:01.090593 <6>[ 3.104097] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10651 10:06:01.098348 <6>[ 3.115530] NET: Registered PF_PACKET protocol family
10652 10:06:01.104774 <6>[ 3.120986] 9pnet: Installing 9P2000 support
10653 10:06:01.108503 <5>[ 3.125564] Key type dns_resolver registered
10654 10:06:01.111756 <6>[ 3.130624] registered taskstats version 1
10655 10:06:01.118064 <5>[ 3.135022] Loading compiled-in X.509 certificates
10656 10:06:01.151807 <4>[ 3.162363] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10657 10:06:01.161891 <4>[ 3.173069] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10658 10:06:01.172003 <3>[ 3.185779] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10659 10:06:01.184277 <6>[ 3.201245] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10660 10:06:01.190814 <6>[ 3.208017] xhci-mtk 11200000.usb: xHCI Host Controller
10661 10:06:01.197479 <6>[ 3.213525] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10662 10:06:01.207778 <6>[ 3.221390] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10663 10:06:01.214492 <6>[ 3.230822] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10664 10:06:01.220695 <6>[ 3.237041] xhci-mtk 11200000.usb: xHCI Host Controller
10665 10:06:01.227703 <6>[ 3.242552] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10666 10:06:01.234569 <6>[ 3.250210] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10667 10:06:01.241083 <6>[ 3.258086] hub 1-0:1.0: USB hub found
10668 10:06:01.244309 <6>[ 3.262124] hub 1-0:1.0: 1 port detected
10669 10:06:01.254046 <6>[ 3.266478] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10670 10:06:01.257501 <6>[ 3.275246] hub 2-0:1.0: USB hub found
10671 10:06:01.260712 <6>[ 3.279284] hub 2-0:1.0: 1 port detected
10672 10:06:01.269528 <6>[ 3.286484] mtk-msdc 11f70000.mmc: Got CD GPIO
10673 10:06:01.285973 <6>[ 3.299800] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10674 10:06:01.292515 <6>[ 3.307839] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10675 10:06:01.302319 <4>[ 3.315811] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10676 10:06:01.312353 <6>[ 3.325477] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10677 10:06:01.319050 <6>[ 3.333560] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10678 10:06:01.326182 <6>[ 3.341577] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10679 10:06:01.336227 <6>[ 3.349491] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10680 10:06:01.342458 <6>[ 3.357317] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10681 10:06:01.352314 <6>[ 3.365146] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10682 10:06:01.362068 <6>[ 3.375715] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10683 10:06:01.368703 <6>[ 3.384080] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10684 10:06:01.379174 <6>[ 3.392433] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10685 10:06:01.385559 <6>[ 3.400779] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10686 10:06:01.395571 <6>[ 3.409123] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10687 10:06:01.402356 <6>[ 3.417466] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10688 10:06:01.412223 <6>[ 3.425809] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10689 10:06:01.419151 <6>[ 3.434152] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10690 10:06:01.428630 <6>[ 3.442495] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10691 10:06:01.438476 <6>[ 3.450837] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10692 10:06:01.445355 <6>[ 3.459179] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10693 10:06:01.455414 <6>[ 3.467522] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10694 10:06:01.461578 <6>[ 3.475866] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10695 10:06:01.471795 <6>[ 3.484209] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10696 10:06:01.478392 <6>[ 3.492554] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10697 10:06:01.484650 <6>[ 3.501485] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10698 10:06:01.491528 <6>[ 3.508916] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10699 10:06:01.498645 <6>[ 3.515960] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10700 10:06:01.509238 <6>[ 3.523062] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10701 10:06:01.515450 <6>[ 3.530355] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10702 10:06:01.525730 <6>[ 3.537282] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10703 10:06:01.532573 <6>[ 3.546423] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10704 10:06:01.542352 <6>[ 3.555553] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10705 10:06:01.552440 <6>[ 3.564857] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10706 10:06:01.561862 <6>[ 3.574334] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10707 10:06:01.572167 <6>[ 3.583808] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10708 10:06:01.578914 <6>[ 3.592935] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10709 10:06:01.588896 <6>[ 3.602408] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10710 10:06:01.598583 <6>[ 3.611540] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10711 10:06:01.608586 <6>[ 3.620844] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10712 10:06:01.618625 <6>[ 3.631011] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10713 10:06:01.628568 <6>[ 3.642521] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10714 10:06:01.655452 <6>[ 3.669602] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10715 10:06:01.682571 <6>[ 3.699969] hub 2-1:1.0: USB hub found
10716 10:06:01.686314 <6>[ 3.704373] hub 2-1:1.0: 3 ports detected
10717 10:06:01.807427 <6>[ 3.821401] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10718 10:06:01.961348 <6>[ 3.978565] hub 1-1:1.0: USB hub found
10719 10:06:01.964323 <6>[ 3.983048] hub 1-1:1.0: 4 ports detected
10720 10:06:02.039627 <6>[ 4.053645] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10721 10:06:02.287250 <6>[ 4.301399] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10722 10:06:02.420597 <6>[ 4.437693] hub 1-1.4:1.0: USB hub found
10723 10:06:02.423764 <6>[ 4.442385] hub 1-1.4:1.0: 2 ports detected
10724 10:06:02.723467 <6>[ 4.737400] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10725 10:06:02.914994 <6>[ 4.929401] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10726 10:06:13.900871 <6>[ 15.921960] ALSA device list:
10727 10:06:13.907119 <6>[ 15.925218] No soundcards found.
10728 10:06:13.919212 <6>[ 15.937489] Freeing unused kernel memory: 8384K
10729 10:06:13.922754 <6>[ 15.942399] Run /init as init process
10730 10:06:13.952932 <6>[ 15.971140] NET: Registered PF_INET6 protocol family
10731 10:06:13.959901 <6>[ 15.977265] Segment Routing with IPv6
10732 10:06:13.962781 <6>[ 15.981214] In-situ OAM (IOAM) with IPv6
10733 10:06:13.994082 <30>[ 15.995527] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10734 10:06:14.001328 <30>[ 16.019258] systemd[1]: Detected architecture arm64.
10735 10:06:14.001784
10736 10:06:14.007740 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10737 10:06:14.008172
10738 10:06:14.023243 <30>[ 16.041577] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10739 10:06:14.162978 <30>[ 16.177594] systemd[1]: Queued start job for default target Graphical Interface.
10740 10:06:14.192573 <30>[ 16.210576] systemd[1]: Created slice system-getty.slice.
10741 10:06:14.198811 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10742 10:06:14.215689 <30>[ 16.234028] systemd[1]: Created slice system-modprobe.slice.
10743 10:06:14.222651 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10744 10:06:14.240619 <30>[ 16.258537] systemd[1]: Created slice system-serial\x2dgetty.slice.
10745 10:06:14.251156 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10746 10:06:14.263751 <30>[ 16.281880] systemd[1]: Created slice User and Session Slice.
10747 10:06:14.270483 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10748 10:06:14.290343 <30>[ 16.305640] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10749 10:06:14.300871 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10750 10:06:14.314768 <30>[ 16.329530] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10751 10:06:14.321250 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10752 10:06:14.342128 <30>[ 16.353439] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10753 10:06:14.348760 <30>[ 16.365464] systemd[1]: Reached target Local Encrypted Volumes.
10754 10:06:14.355332 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10755 10:06:14.371799 <30>[ 16.389744] systemd[1]: Reached target Paths.
10756 10:06:14.375031 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10757 10:06:14.391017 <30>[ 16.409416] systemd[1]: Reached target Remote File Systems.
10758 10:06:14.397586 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10759 10:06:14.410784 <30>[ 16.429402] systemd[1]: Reached target Slices.
10760 10:06:14.414799 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10761 10:06:14.430910 <30>[ 16.449441] systemd[1]: Reached target Swap.
10762 10:06:14.434233 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10763 10:06:14.454910 <30>[ 16.469710] systemd[1]: Listening on initctl Compatibility Named Pipe.
10764 10:06:14.461341 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10765 10:06:14.468108 <30>[ 16.484407] systemd[1]: Listening on Journal Audit Socket.
10766 10:06:14.474523 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10767 10:06:14.487310 <30>[ 16.505687] systemd[1]: Listening on Journal Socket (/dev/log).
10768 10:06:14.493953 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10769 10:06:14.511552 <30>[ 16.529732] systemd[1]: Listening on Journal Socket.
10770 10:06:14.518382 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10771 10:06:14.531517 <30>[ 16.549687] systemd[1]: Listening on Network Service Netlink Socket.
10772 10:06:14.541454 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10773 10:06:14.556299 <30>[ 16.574197] systemd[1]: Listening on udev Control Socket.
10774 10:06:14.562520 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10775 10:06:14.579817 <30>[ 16.598116] systemd[1]: Listening on udev Kernel Socket.
10776 10:06:14.586198 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10777 10:06:14.623676 <30>[ 16.641807] systemd[1]: Mounting Huge Pages File System...
10778 10:06:14.630377 Mounting [0;1;39mHuge Pages File System[0m...
10779 10:06:14.645049 <30>[ 16.663461] systemd[1]: Mounting POSIX Message Queue File System...
10780 10:06:14.651934 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10781 10:06:14.669386 <30>[ 16.687636] systemd[1]: Mounting Kernel Debug File System...
10782 10:06:14.675928 Mounting [0;1;39mKernel Debug File System[0m...
10783 10:06:14.694988 <30>[ 16.709731] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10784 10:06:14.727275 <30>[ 16.741944] systemd[1]: Starting Create list of static device nodes for the current kernel...
10785 10:06:14.733490 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10786 10:06:14.753605 <30>[ 16.771956] systemd[1]: Starting Load Kernel Module configfs...
10787 10:06:14.760961 Starting [0;1;39mLoad Kernel Module configfs[0m...
10788 10:06:14.777859 <30>[ 16.795973] systemd[1]: Starting Load Kernel Module drm...
10789 10:06:14.783734 Starting [0;1;39mLoad Kernel Module drm[0m...
10790 10:06:14.802209 <30>[ 16.817663] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10791 10:06:14.813128 <30>[ 16.831413] systemd[1]: Starting Journal Service...
10792 10:06:14.815989 Starting [0;1;39mJournal Service[0m...
10793 10:06:14.833612 <30>[ 16.852095] systemd[1]: Starting Load Kernel Modules...
10794 10:06:14.839846 Starting [0;1;39mLoad Kernel Modules[0m...
10795 10:06:14.861136 <30>[ 16.876181] systemd[1]: Starting Remount Root and Kernel File Systems...
10796 10:06:14.867581 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10797 10:06:14.882168 <30>[ 16.899991] systemd[1]: Starting Coldplug All udev Devices...
10798 10:06:14.888712 Starting [0;1;39mColdplug All udev Devices[0m...
10799 10:06:14.906173 <30>[ 16.924668] systemd[1]: Mounted Huge Pages File System.
10800 10:06:14.912968 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10801 10:06:14.927513 <30>[ 16.946217] systemd[1]: Started Journal Service.
10802 10:06:14.934204 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10803 10:06:14.949357 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10804 10:06:14.964238 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10805 10:06:14.983896 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10806 10:06:15.001638 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10807 10:06:15.020853 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10808 10:06:15.036506 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10809 10:06:15.056643 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10810 10:06:15.071747 See 'systemctl status systemd-remount-fs.service' for details.
10811 10:06:15.139959 Mounting [0;1;39mKernel Configuration File System[0m...
10812 10:06:15.157662 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10813 10:06:15.175387 <46>[ 17.190336] systemd-journald[173]: Received client request to flush runtime journal.
10814 10:06:15.183538 Starting [0;1;39mLoad/Save Random Seed[0m...
10815 10:06:15.202371 Starting [0;1;39mApply Kernel Variables[0m...
10816 10:06:15.218134 Starting [0;1;39mCreate System Users[0m...
10817 10:06:15.233011 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10818 10:06:15.255674 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10819 10:06:15.267970 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10820 10:06:15.283678 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10821 10:06:15.300186 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10822 10:06:15.319853 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10823 10:06:15.375787 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10824 10:06:15.398486 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10825 10:06:15.411697 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10826 10:06:15.427004 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10827 10:06:15.463323 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10828 10:06:15.490709 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10829 10:06:15.511684 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10830 10:06:15.531233 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10831 10:06:15.608396 Starting [0;1;39mNetwork Service[0m...
10832 10:06:15.632367 Starting [0;1;39mNetwork Time Synchronization[0m...
10833 10:06:15.655797 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10834 10:06:15.694513 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10835 10:06:15.712793 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10836 10:06:15.743829 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10837 10:06:15.765559 <6>[ 17.781307] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10838 10:06:15.787374 <6>[ 17.805820] remoteproc remoteproc0: scp is available
10839 10:06:15.793620 <6>[ 17.809323] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10840 10:06:15.803648 <3>[ 17.810749] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10841 10:06:15.810252 <3>[ 17.810771] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10842 10:06:15.820237 <3>[ 17.810780] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10843 10:06:15.829985 <4>[ 17.811244] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10844 10:06:15.836782 <6>[ 17.818784] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10845 10:06:15.844060 <6>[ 17.826757] remoteproc remoteproc0: powering up scp
10846 10:06:15.850651 <6>[ 17.834815] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10847 10:06:15.860471 <4>[ 17.842940] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10848 10:06:15.870130 <3>[ 17.867192] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10849 10:06:15.877139 <3>[ 17.875223] remoteproc remoteproc0: request_firmware failed: -2
10850 10:06:15.880261 <6>[ 17.889042] mc: Linux media interface: v0.10
10851 10:06:15.887400 <3>[ 17.893227] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10852 10:06:15.897041 <4>[ 17.901139] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10853 10:06:15.903717 <3>[ 17.903867] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 10:06:15.913504 <3>[ 17.927319] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10855 10:06:15.919807 <3>[ 17.927328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 10:06:15.926718 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10857 10:06:15.939093 <4>[ 17.954450] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10858 10:06:15.945841 <3>[ 17.956296] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 10:06:15.952338 <6>[ 17.969748] usbcore: registered new interface driver r8152
10860 10:06:15.959096 <3>[ 17.972370] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10861 10:06:15.970300 <6>[ 17.975921] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10862 10:06:15.976418 <6>[ 17.981398] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10863 10:06:15.982961 <3>[ 17.984158] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10864 10:06:15.993216 <3>[ 17.984168] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10865 10:06:15.999993 <3>[ 17.984354] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10866 10:06:16.010343 <3>[ 17.984369] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10867 10:06:16.016750 <3>[ 17.984379] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10868 10:06:16.026342 <3>[ 17.984401] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10869 10:06:16.033498 <3>[ 17.984413] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10870 10:06:16.042906 <3>[ 17.988166] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10871 10:06:16.049498 <6>[ 17.993330] pci_bus 0000:00: root bus resource [bus 00-ff]
10872 10:06:16.053153 <6>[ 18.001067] videodev: Linux video capture interface: v2.00
10873 10:06:16.062925 <6>[ 18.008760] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10874 10:06:16.073434 <6>[ 18.085397] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10875 10:06:16.083423 <6>[ 18.087367] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10876 10:06:16.089572 <6>[ 18.089253] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10877 10:06:16.096770 <6>[ 18.095517] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10878 10:06:16.106742 [[0;32m OK [<6>[ 18.106011] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10879 10:06:16.116889 0m] Started [0;<6>[ 18.114764] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10880 10:06:16.123082 1;39mNetwork Ser<6>[ 18.140458] pci 0000:00:00.0: supports D1 D2
10881 10:06:16.123779 vice[0m.
10882 10:06:16.129593 <6>[ 18.146895] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10883 10:06:16.136004 <6>[ 18.147273] usbcore: registered new interface driver cdc_ether
10884 10:06:16.142958 <6>[ 18.156728] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10885 10:06:16.153213 <6>[ 18.156985] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10886 10:06:16.159752 <6>[ 18.157203] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10887 10:06:16.165736 <6>[ 18.157242] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10888 10:06:16.172762 <6>[ 18.157267] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10889 10:06:16.182646 <6>[ 18.157286] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10890 10:06:16.185892 <6>[ 18.157415] pci 0000:01:00.0: supports D1 D2
10891 10:06:16.192627 <6>[ 18.157420] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10892 10:06:16.199178 <6>[ 18.165365] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10893 10:06:16.202639 <6>[ 18.169045] Bluetooth: Core ver 2.22
10894 10:06:16.212518 <6>[ 18.176165] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10895 10:06:16.219590 <6>[ 18.176809] usbcore: registered new interface driver r8153_ecm
10896 10:06:16.226072 <6>[ 18.177485] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10897 10:06:16.236726 <6>[ 18.179551] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10898 10:06:16.243502 <6>[ 18.179709] usbcore: registered new interface driver uvcvideo
10899 10:06:16.250303 <6>[ 18.182507] NET: Registered PF_BLUETOOTH protocol family
10900 10:06:16.257546 <6>[ 18.190117] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10901 10:06:16.264373 <6>[ 18.197345] Bluetooth: HCI device and connection manager initialized
10902 10:06:16.270578 <6>[ 18.197370] Bluetooth: HCI socket layer initialized
10903 10:06:16.277033 <6>[ 18.198309] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10904 10:06:16.280454 <6>[ 18.202376] remoteproc remoteproc0: powering up scp
10905 10:06:16.290725 <4>[ 18.202425] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10906 10:06:16.297044 <3>[ 18.202433] remoteproc remoteproc0: request_firmware failed: -2
10907 10:06:16.303950 <3>[ 18.202436] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10908 10:06:16.310485 <6>[ 18.204853] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10909 10:06:16.317197 <6>[ 18.205405] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10910 10:06:16.325066 <6>[ 18.209344] Bluetooth: L2CAP socket layer initialized
10911 10:06:16.331832 <4>[ 18.216222] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10912 10:06:16.339005 <4>[ 18.216222] Fallback method does not support PEC.
10913 10:06:16.345369 <6>[ 18.216824] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10914 10:06:16.354959 <6>[ 18.216844] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10915 10:06:16.357872 <6>[ 18.216863] pci 0000:00:00.0: PCI bridge to [bus 01]
10916 10:06:16.368051 <6>[ 18.216872] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10917 10:06:16.375060 <6>[ 18.217269] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10918 10:06:16.378275 <6>[ 18.218722] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10919 10:06:16.385266 <6>[ 18.218996] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10920 10:06:16.392093 <6>[ 18.223101] Bluetooth: SCO socket layer initialized
10921 10:06:16.398411 <5>[ 18.238496] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10922 10:06:16.408691 <3>[ 18.256953] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 10:06:16.415788 <3>[ 18.257660] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10924 10:06:16.425682 <3>[ 18.267721] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 10:06:16.430383 <6>[ 18.269640] r8152 2-1.3:1.0 eth0: v1.12.13
10926 10:06:16.436737 <5>[ 18.274200] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10927 10:06:16.443359 <6>[ 18.282052] usbcore: registered new interface driver btusb
10928 10:06:16.447024 <6>[ 18.283490] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10929 10:06:16.459723 <4>[ 18.304272] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10930 10:06:16.466584 <4>[ 18.318054] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10931 10:06:16.473386 <3>[ 18.320181] Bluetooth: hci0: Failed to load firmware file (-2)
10932 10:06:16.477171 <6>[ 18.327701] cfg80211: failed to load regulatory.db
10933 10:06:16.486832 <3>[ 18.328802] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 10:06:16.497219 <3>[ 18.331436] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10935 10:06:16.500276 <3>[ 18.335720] Bluetooth: hci0: Failed to set up firmware (-2)
10936 10:06:16.510251 <3>[ 18.351319] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 10:06:16.520245 <4>[ 18.361351] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10938 10:06:16.526678 <6>[ 18.396413] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10939 10:06:16.536500 <3>[ 18.418726] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 10:06:16.543389 <6>[ 18.422245] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10941 10:06:16.553554 <3>[ 18.453696] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 10:06:16.556616 <6>[ 18.480029] mt7921e 0000:01:00.0: ASIC revision: 79610010
10943 10:06:16.566871 <3>[ 18.502466] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 10:06:16.573338 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10945 10:06:16.594996 <4>[ 18.605889] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10946 10:06:16.601712 <3>[ 18.615393] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 10:06:16.611917 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10948 10:06:16.717210 <4>[ 18.728465] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10949 10:06:16.785717 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10950 10:06:16.799442 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10951 10:06:16.818717 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10952 10:06:16.836894 <4>[ 18.848327] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10953 10:06:16.842814 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10954 10:06:16.852893 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10955 10:06:16.870623 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10956 10:06:16.883276 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10957 10:06:16.902711 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10958 10:06:16.914936 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10959 10:06:16.931435 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10960 10:06:16.955157 [[0;32m OK [<4>[ 18.967868] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10961 10:06:16.961483 0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10962 10:06:16.999505 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10963 10:06:17.025843 Starting [0;1;39mUser Login Management[0m...
10964 10:06:17.043313 Starting [0;1;39mNetwork Name Resolution[0m...
10965 10:06:17.076861 Startin<4>[ 19.090193] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10966 10:06:17.083826 g [0;1;39mLoad/Save RF Kill Switch Status[0m...
10967 10:06:17.101397 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10968 10:06:17.128104 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10969 10:06:17.204620 [[0;32m OK [<4>[ 19.216269] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10970 10:06:17.210570 0m] Started [0;1;39mNetwork Name Resolution[0m.
10971 10:06:17.217505 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10972 10:06:17.238868 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10973 10:06:17.276552 Starting [0;1;39mPermit User Sessions[0m...
10974 10:06:17.293476 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10975 10:06:17.323929 <4>[ 19.336009] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10976 10:06:17.330850 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10977 10:06:17.348090 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10978 10:06:17.367576 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10979 10:06:17.387544 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10980 10:06:17.407011 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10981 10:06:17.447872 <4>[ 19.459831] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10982 10:06:17.462725 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10983 10:06:17.493324 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10984 10:06:17.524120
10985 10:06:17.524661
10986 10:06:17.527321 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10987 10:06:17.527851
10988 10:06:17.530264 debian-bullseye-arm64 login: root (automatic login)
10989 10:06:17.530688
10990 10:06:17.531023
10991 10:06:17.546353 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023 aarch64
10992 10:06:17.546887
10993 10:06:17.552838 The programs included with the Debian GNU/Linux system are free software;
10994 10:06:17.559082 the exact distribution terms for each program are described in the
10995 10:06:17.563235 individual files in /usr/share/doc/*/copyright.
10996 10:06:17.563405
10997 10:06:17.575972 Debian GNU/Linux com<4>[ 19.587789] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10998 10:06:17.579343 es with ABSOLUTELY NO WARRANTY, to the extent
10999 10:06:17.582736 permitted by applicable law.
11000 10:06:17.583307 Matched prompt #10: / #
11002 10:06:17.583645 Setting prompt string to ['/ #']
11003 10:06:17.583781 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11005 10:06:17.584066 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11006 10:06:17.584198 start: 2.2.6 expect-shell-connection (timeout 00:03:29) [common]
11007 10:06:17.584305 Setting prompt string to ['/ #']
11008 10:06:17.584395 Forcing a shell prompt, looking for ['/ #']
11010 10:06:17.634764 / #
11011 10:06:17.635408 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11012 10:06:17.635800 Waiting using forced prompt support (timeout 00:02:30)
11013 10:06:17.641753
11014 10:06:17.642643 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11015 10:06:17.643145 start: 2.2.7 export-device-env (timeout 00:03:29) [common]
11016 10:06:17.643621 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11017 10:06:17.644057 end: 2.2 depthcharge-retry (duration 00:01:31) [common]
11018 10:06:17.644480 end: 2 depthcharge-action (duration 00:01:31) [common]
11019 10:06:17.644942 start: 3 lava-test-retry (timeout 00:05:00) [common]
11020 10:06:17.645384 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11021 10:06:17.645757 Using namespace: common
11023 10:06:17.746954 / # #
11024 10:06:17.747566 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11025 10:06:17.748102 <4>[ 19.707221] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11026 10:06:17.753625 #
11027 10:06:17.754461 Using /lava-10670697
11029 10:06:17.855558 / # export SHELL=/bin/sh
11030 10:06:17.856280 <3>[ 19.825160] mt7921e 0000:01:00.0: hardware init failed
11031 10:06:17.861842 export SHELL=/bin/sh
11033 10:06:17.963256 / # . /lava-10670697/environment
11034 10:06:17.964009 <6>[ 19.918800] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
11035 10:06:17.964382 <6>[ 19.926713] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
11036 10:06:17.970111 . /lava-10670697/environment
11038 10:06:18.071864 / # /lava-10670697/bin/lava-test-runner /lava-10670697/0
11039 10:06:18.072457 Test shell timeout: 10s (minimum of the action and connection timeout)
11040 10:06:18.078556 /lava-10670697/bin/lava-test-runner /lava-10670697/0
11041 10:06:18.097469 + export TESTRUN_ID=0_cros-ec
11042 10:06:18.104137 +<8>[ 20.120401] <LAVA_SIGNAL_STARTRUN 0_cros-ec 10670697_1.5.2.3.1>
11043 10:06:18.104938 Received signal: <STARTRUN> 0_cros-ec 10670697_1.5.2.3.1
11044 10:06:18.105353 Starting test lava.0_cros-ec (10670697_1.5.2.3.1)
11045 10:06:18.105822 Skipping test definition patterns.
11046 10:06:18.106734 cd /lava-10670697/0/tests/0_cros-ec
11047 10:06:18.110097 + cat uuid
11048 10:06:18.110530 + UUID=10670697_1.5.2.3.1
11049 10:06:18.110876 + set +x
11050 10:06:18.116502 + python3 -m cros.runners.lava_runner -v
11051 10:06:18.816348 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11052 10:06:18.823034 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11053 10:06:18.825899
11054 10:06:18.829378 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11056 10:06:18.832244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11057 10:06:18.839073 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11058 10:06:18.845791 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11059 10:06:18.846213
11060 10:06:18.856134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11061 10:06:18.856936 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11063 10:06:18.859257 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11064 10:06:18.865544 Checks t<8>[ 20.884024] <LAVA_SIGNAL_ENDRUN 0_cros-ec 10670697_1.5.2.3.1>
11065 10:06:18.866398 Received signal: <ENDRUN> 0_cros-ec 10670697_1.5.2.3.1
11066 10:06:18.866835 Ending use of test pattern.
11067 10:06:18.867156 Ending test lava.0_cros-ec (10670697_1.5.2.3.1), duration 0.76
11069 10:06:18.872759 he cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11070 10:06:18.873329
11071 10:06:18.879191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11072 10:06:18.879980 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11074 10:06:18.885473 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11075 10:06:18.891778 Checks the standard ABI for the main Embedded Controller. ... ok
11076 10:06:18.892202
11077 10:06:18.894954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11078 10:06:18.895625 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11080 10:06:18.901395 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11081 10:06:18.907784 Checks the main Embedded controller character device. ... ok
11082 10:06:18.907866
11083 10:06:18.912043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11084 10:06:18.912399 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11086 10:06:18.917723 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11087 10:06:18.924607 Checks basic comunication with the main Embedded controller. ... ok
11088 10:06:18.924706
11089 10:06:18.931354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11090 10:06:18.931738 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11092 10:06:18.934476 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11093 10:06:18.940981 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11094 10:06:18.944329
11095 10:06:18.948215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11096 10:06:18.948667 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11098 10:06:18.954272 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11099 10:06:18.961471 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11100 10:06:18.961787
11101 10:06:18.967787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11102 10:06:18.968495 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11104 10:06:18.974524 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11105 10:06:18.980841 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11106 10:06:18.981265
11107 10:06:18.988004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11108 10:06:18.988793 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11110 10:06:18.991312 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11111 10:06:19.001031 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11112 10:06:19.001566
11113 10:06:19.004640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11114 10:06:19.005356 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11116 10:06:19.011047 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11117 10:06:19.017526 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11118 10:06:19.020617
11119 10:06:19.024334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11120 10:06:19.025008 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11122 10:06:19.031008 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11123 10:06:19.038017 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11124 10:06:19.038466
11125 10:06:19.043754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11126 10:06:19.044460 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11128 10:06:19.047364 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11129 10:06:19.057531 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11130 10:06:19.057975
11131 10:06:19.063835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11132 10:06:19.064534 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11134 10:06:19.068026 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11135 10:06:19.077386 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11136 10:06:19.077904
11137 10:06:19.084271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11138 10:06:19.085053 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11140 10:06:19.090449 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11141 10:06:19.093492 Check the cros battery ABI. ... skipped 'No BAT found'
11142 10:06:19.093927
11143 10:06:19.100660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11144 10:06:19.101504 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11146 10:06:19.107168 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11147 10:06:19.113698 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11148 10:06:19.114230
11149 10:06:19.123241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11150 10:06:19.123927 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11152 10:06:19.126545 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11153 10:06:19.133071 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11154 10:06:19.133507
11155 10:06:19.140141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11156 10:06:19.140935 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11158 10:06:19.146584 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11159 10:06:19.153272 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11160 10:06:19.153798
11161 10:06:19.160546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11162 10:06:19.161141
11163 10:06:19.161752 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11165 10:06:19.166698 ----------------------------------------------------------------------
11166 10:06:19.169823 Ran 18 tests in 0.010s
11167 10:06:19.170346
11168 10:06:19.170685 OK (skipped=15)
11169 10:06:19.171003 + set +x
11170 10:06:19.173351 <LAVA_TEST_RUNNER EXIT>
11171 10:06:19.174138 ok: lava_test_shell seems to have completed
11172 10:06:19.175035 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11173 10:06:19.175492 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11174 10:06:19.175937 end: 3 lava-test-retry (duration 00:00:02) [common]
11175 10:06:19.176394 start: 4 finalize (timeout 00:08:08) [common]
11176 10:06:19.176884 start: 4.1 power-off (timeout 00:00:30) [common]
11177 10:06:19.177648 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11178 10:06:19.293515 >> Command sent successfully.
11179 10:06:19.295999 Returned 0 in 0 seconds
11180 10:06:19.396798 end: 4.1 power-off (duration 00:00:00) [common]
11182 10:06:19.398308 start: 4.2 read-feedback (timeout 00:08:07) [common]
11183 10:06:19.399505 Listened to connection for namespace 'common' for up to 1s
11184 10:06:20.400055 Finalising connection for namespace 'common'
11185 10:06:20.400231 Disconnecting from shell: Finalise
11186 10:06:20.400325 / #
11187 10:06:20.500637 end: 4.2 read-feedback (duration 00:00:01) [common]
11188 10:06:20.500856 end: 4 finalize (duration 00:00:01) [common]
11189 10:06:20.500990 Cleaning after the job
11190 10:06:20.501093 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670697/tftp-deploy-artaceso/ramdisk
11191 10:06:20.506406 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670697/tftp-deploy-artaceso/kernel
11192 10:06:20.512486 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670697/tftp-deploy-artaceso/dtb
11193 10:06:20.512667 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670697/tftp-deploy-artaceso/modules
11194 10:06:20.518222 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10670697
11195 10:06:20.628033 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10670697
11196 10:06:20.628223 Job finished correctly