Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 50
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
- Errors: 0
1 10:00:54.559724 lava-dispatcher, installed at version: 2023.05.1
2 10:00:54.559922 start: 0 validate
3 10:00:54.560045 Start time: 2023-06-10 10:00:54.560036+00:00 (UTC)
4 10:00:54.560167 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:00:54.560291 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 10:00:54.821579 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:00:54.822489 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:01:14.092852 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:01:14.093620 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:01:14.363371 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:01:14.364098 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:01:14.891076 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:01:14.891788 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:01:17.402344 validate duration: 22.84
16 10:01:17.402601 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:01:17.402696 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:01:17.402786 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:01:17.402910 Not decompressing ramdisk as can be used compressed.
20 10:01:17.402995 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 10:01:17.403061 saving as /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/ramdisk/initrd.cpio.gz
22 10:01:17.403123 total size: 4665601 (4MB)
23 10:01:17.668617 progress 0% (0MB)
24 10:01:17.670875 progress 5% (0MB)
25 10:01:17.672905 progress 10% (0MB)
26 10:01:17.674847 progress 15% (0MB)
27 10:01:17.676778 progress 20% (0MB)
28 10:01:17.678773 progress 25% (1MB)
29 10:01:17.680686 progress 30% (1MB)
30 10:01:17.682672 progress 35% (1MB)
31 10:01:17.684595 progress 40% (1MB)
32 10:01:17.686819 progress 45% (2MB)
33 10:01:17.688780 progress 50% (2MB)
34 10:01:17.690815 progress 55% (2MB)
35 10:01:17.692901 progress 60% (2MB)
36 10:01:17.694888 progress 65% (2MB)
37 10:01:17.696892 progress 70% (3MB)
38 10:01:17.698809 progress 75% (3MB)
39 10:01:17.700752 progress 80% (3MB)
40 10:01:17.702972 progress 85% (3MB)
41 10:01:17.704951 progress 90% (4MB)
42 10:01:17.706944 progress 95% (4MB)
43 10:01:17.708933 progress 100% (4MB)
44 10:01:17.709166 4MB downloaded in 0.31s (14.54MB/s)
45 10:01:17.709371 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:01:17.709743 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:01:17.709868 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:01:17.709996 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:01:17.710179 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:01:17.710285 saving as /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/kernel/Image
52 10:01:17.710382 total size: 45746688 (43MB)
53 10:01:17.710516 No compression specified
54 10:01:17.712056 progress 0% (0MB)
55 10:01:17.727047 progress 5% (2MB)
56 10:01:17.738613 progress 10% (4MB)
57 10:01:17.750064 progress 15% (6MB)
58 10:01:17.761436 progress 20% (8MB)
59 10:01:17.772803 progress 25% (10MB)
60 10:01:17.784027 progress 30% (13MB)
61 10:01:17.795616 progress 35% (15MB)
62 10:01:17.807195 progress 40% (17MB)
63 10:01:17.818663 progress 45% (19MB)
64 10:01:17.830363 progress 50% (21MB)
65 10:01:17.841716 progress 55% (24MB)
66 10:01:17.853160 progress 60% (26MB)
67 10:01:17.864555 progress 65% (28MB)
68 10:01:17.875908 progress 70% (30MB)
69 10:01:17.887291 progress 75% (32MB)
70 10:01:17.898560 progress 80% (34MB)
71 10:01:17.910020 progress 85% (37MB)
72 10:01:17.921397 progress 90% (39MB)
73 10:01:17.932801 progress 95% (41MB)
74 10:01:17.944047 progress 100% (43MB)
75 10:01:17.944167 43MB downloaded in 0.23s (186.62MB/s)
76 10:01:17.944312 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:01:17.944550 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:01:17.944640 start: 1.3 download-retry (timeout 00:09:59) [common]
80 10:01:17.944727 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 10:01:17.944868 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:01:17.944939 saving as /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/dtb/mt8192-asurada-spherion-r0.dtb
83 10:01:17.944999 total size: 46924 (0MB)
84 10:01:17.945058 No compression specified
85 10:01:17.946132 progress 69% (0MB)
86 10:01:17.946406 progress 100% (0MB)
87 10:01:17.946557 0MB downloaded in 0.00s (28.78MB/s)
88 10:01:17.946677 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:01:17.946904 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:01:17.946989 start: 1.4 download-retry (timeout 00:09:59) [common]
92 10:01:17.947073 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 10:01:17.947182 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 10:01:17.947250 saving as /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/nfsrootfs/full.rootfs.tar
95 10:01:17.947311 total size: 200770336 (191MB)
96 10:01:17.947371 Using unxz to decompress xz
97 10:01:17.950783 progress 0% (0MB)
98 10:01:18.473129 progress 5% (9MB)
99 10:01:18.980276 progress 10% (19MB)
100 10:01:19.555267 progress 15% (28MB)
101 10:01:19.918027 progress 20% (38MB)
102 10:01:20.237636 progress 25% (47MB)
103 10:01:20.835916 progress 30% (57MB)
104 10:01:21.382053 progress 35% (67MB)
105 10:01:21.962945 progress 40% (76MB)
106 10:01:22.514958 progress 45% (86MB)
107 10:01:23.086482 progress 50% (95MB)
108 10:01:23.703626 progress 55% (105MB)
109 10:01:24.363338 progress 60% (114MB)
110 10:01:24.485372 progress 65% (124MB)
111 10:01:24.624519 progress 70% (134MB)
112 10:01:24.719231 progress 75% (143MB)
113 10:01:24.791984 progress 80% (153MB)
114 10:01:24.859274 progress 85% (162MB)
115 10:01:24.955368 progress 90% (172MB)
116 10:01:25.228199 progress 95% (181MB)
117 10:01:25.798956 progress 100% (191MB)
118 10:01:25.803579 191MB downloaded in 7.86s (24.37MB/s)
119 10:01:25.803865 end: 1.4.1 http-download (duration 00:00:08) [common]
121 10:01:25.804124 end: 1.4 download-retry (duration 00:00:08) [common]
122 10:01:25.804216 start: 1.5 download-retry (timeout 00:09:52) [common]
123 10:01:25.804304 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 10:01:25.804440 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:01:25.804511 saving as /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/modules/modules.tar
126 10:01:25.804574 total size: 8540248 (8MB)
127 10:01:25.804637 Using unxz to decompress xz
128 10:01:26.071931 progress 0% (0MB)
129 10:01:26.093855 progress 5% (0MB)
130 10:01:26.118158 progress 10% (0MB)
131 10:01:26.142208 progress 15% (1MB)
132 10:01:26.167922 progress 20% (1MB)
133 10:01:26.192755 progress 25% (2MB)
134 10:01:26.215653 progress 30% (2MB)
135 10:01:26.241495 progress 35% (2MB)
136 10:01:26.266283 progress 40% (3MB)
137 10:01:26.290198 progress 45% (3MB)
138 10:01:26.317347 progress 50% (4MB)
139 10:01:26.342357 progress 55% (4MB)
140 10:01:26.368189 progress 60% (4MB)
141 10:01:26.394070 progress 65% (5MB)
142 10:01:26.418939 progress 70% (5MB)
143 10:01:26.442922 progress 75% (6MB)
144 10:01:26.466498 progress 80% (6MB)
145 10:01:26.490692 progress 85% (6MB)
146 10:01:26.519763 progress 90% (7MB)
147 10:01:26.545343 progress 95% (7MB)
148 10:01:26.570512 progress 100% (8MB)
149 10:01:26.575788 8MB downloaded in 0.77s (10.56MB/s)
150 10:01:26.576060 end: 1.5.1 http-download (duration 00:00:01) [common]
152 10:01:26.576339 end: 1.5 download-retry (duration 00:00:01) [common]
153 10:01:26.576435 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 10:01:26.576532 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 10:01:29.749495 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10670651/extract-nfsrootfs-69r0vlv_
156 10:01:29.749712 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 10:01:29.749820 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 10:01:29.749993 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b
159 10:01:29.750127 makedir: /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin
160 10:01:29.750227 makedir: /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/tests
161 10:01:29.750322 makedir: /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/results
162 10:01:29.750422 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-add-keys
163 10:01:29.750559 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-add-sources
164 10:01:29.750698 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-background-process-start
165 10:01:29.750826 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-background-process-stop
166 10:01:29.750952 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-common-functions
167 10:01:29.751072 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-echo-ipv4
168 10:01:29.751191 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-install-packages
169 10:01:29.751308 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-installed-packages
170 10:01:29.751429 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-os-build
171 10:01:29.751547 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-probe-channel
172 10:01:29.751663 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-probe-ip
173 10:01:29.751780 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-target-ip
174 10:01:29.751897 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-target-mac
175 10:01:29.752014 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-target-storage
176 10:01:29.752132 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-test-case
177 10:01:29.752254 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-test-event
178 10:01:29.752370 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-test-feedback
179 10:01:29.752486 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-test-raise
180 10:01:29.752602 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-test-reference
181 10:01:29.752718 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-test-runner
182 10:01:29.752985 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-test-set
183 10:01:29.753108 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-test-shell
184 10:01:29.753231 Updating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-add-keys (debian)
185 10:01:29.753380 Updating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-add-sources (debian)
186 10:01:29.753524 Updating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-install-packages (debian)
187 10:01:29.753663 Updating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-installed-packages (debian)
188 10:01:29.753799 Updating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/bin/lava-os-build (debian)
189 10:01:29.753919 Creating /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/environment
190 10:01:29.754017 LAVA metadata
191 10:01:29.754087 - LAVA_JOB_ID=10670651
192 10:01:29.754149 - LAVA_DISPATCHER_IP=192.168.201.1
193 10:01:29.754250 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 10:01:29.754315 skipped lava-vland-overlay
195 10:01:29.754388 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 10:01:29.754465 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 10:01:29.754525 skipped lava-multinode-overlay
198 10:01:29.754596 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 10:01:29.754674 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 10:01:29.754746 Loading test definitions
201 10:01:29.754835 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 10:01:29.754904 Using /lava-10670651 at stage 0
203 10:01:29.755178 uuid=10670651_1.6.2.3.1 testdef=None
204 10:01:29.755264 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 10:01:29.755347 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 10:01:29.755782 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 10:01:29.756000 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 10:01:29.756541 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 10:01:29.756777 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 10:01:29.757304 runner path: /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/0/tests/0_timesync-off test_uuid 10670651_1.6.2.3.1
213 10:01:29.757454 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 10:01:29.757679 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 10:01:29.757749 Using /lava-10670651 at stage 0
217 10:01:29.757843 Fetching tests from https://github.com/kernelci/test-definitions.git
218 10:01:29.757918 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/0/tests/1_kselftest-tpm2'
219 10:01:33.600935 Running '/usr/bin/git checkout kernelci.org
220 10:01:33.744072 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 10:01:33.744821 uuid=10670651_1.6.2.3.5 testdef=None
222 10:01:33.744995 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 10:01:33.745244 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 10:01:33.745980 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 10:01:33.746211 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 10:01:33.747185 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 10:01:33.747422 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 10:01:33.748433 runner path: /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/0/tests/1_kselftest-tpm2 test_uuid 10670651_1.6.2.3.5
232 10:01:33.748633 BOARD='mt8192-asurada-spherion-r0'
233 10:01:33.748700 BRANCH='cip'
234 10:01:33.748761 SKIPFILE='/dev/null'
235 10:01:33.748857 SKIP_INSTALL='True'
236 10:01:33.748914 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 10:01:33.748973 TST_CASENAME=''
238 10:01:33.749029 TST_CMDFILES='tpm2'
239 10:01:33.749174 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 10:01:33.749381 Creating lava-test-runner.conf files
242 10:01:33.749446 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10670651/lava-overlay-sfsu5s6b/lava-10670651/0 for stage 0
243 10:01:33.749539 - 0_timesync-off
244 10:01:33.749610 - 1_kselftest-tpm2
245 10:01:33.749707 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 10:01:33.749796 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 10:01:41.248033 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 10:01:41.248198 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 10:01:41.248292 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 10:01:41.248391 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 10:01:41.248482 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 10:01:41.362568 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 10:01:41.362921 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 10:01:41.363033 extracting modules file /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670651/extract-nfsrootfs-69r0vlv_
255 10:01:41.561379 extracting modules file /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670651/extract-overlay-ramdisk-t29jdbs9/ramdisk
256 10:01:41.762048 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 10:01:41.762224 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 10:01:41.762312 [common] Applying overlay to NFS
259 10:01:41.762380 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670651/compress-overlay-p6px__h8/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10670651/extract-nfsrootfs-69r0vlv_
260 10:01:42.638899 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 10:01:42.639064 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 10:01:42.639159 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 10:01:42.639248 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 10:01:42.639328 Building ramdisk /var/lib/lava/dispatcher/tmp/10670651/extract-overlay-ramdisk-t29jdbs9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10670651/extract-overlay-ramdisk-t29jdbs9/ramdisk
265 10:01:42.933678 >> 117806 blocks
266 10:01:44.777368 rename /var/lib/lava/dispatcher/tmp/10670651/extract-overlay-ramdisk-t29jdbs9/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/ramdisk/ramdisk.cpio.gz
267 10:01:44.777785 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 10:01:44.777903 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 10:01:44.778007 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 10:01:44.778110 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/kernel/Image'
271 10:01:56.193260 Returned 0 in 11 seconds
272 10:01:56.293862 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/kernel/image.itb
273 10:01:56.610786 output: FIT description: Kernel Image image with one or more FDT blobs
274 10:01:56.611137 output: Created: Sat Jun 10 11:01:56 2023
275 10:01:56.611220 output: Image 0 (kernel-1)
276 10:01:56.611294 output: Description:
277 10:01:56.611358 output: Created: Sat Jun 10 11:01:56 2023
278 10:01:56.611423 output: Type: Kernel Image
279 10:01:56.611489 output: Compression: lzma compressed
280 10:01:56.611570 output: Data Size: 10087317 Bytes = 9850.90 KiB = 9.62 MiB
281 10:01:56.611632 output: Architecture: AArch64
282 10:01:56.611691 output: OS: Linux
283 10:01:56.611747 output: Load Address: 0x00000000
284 10:01:56.611812 output: Entry Point: 0x00000000
285 10:01:56.611872 output: Hash algo: crc32
286 10:01:56.611929 output: Hash value: c9e456fd
287 10:01:56.611983 output: Image 1 (fdt-1)
288 10:01:56.612036 output: Description: mt8192-asurada-spherion-r0
289 10:01:56.612094 output: Created: Sat Jun 10 11:01:56 2023
290 10:01:56.612150 output: Type: Flat Device Tree
291 10:01:56.612208 output: Compression: uncompressed
292 10:01:56.612262 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 10:01:56.612316 output: Architecture: AArch64
294 10:01:56.612370 output: Hash algo: crc32
295 10:01:56.612431 output: Hash value: 1df858fa
296 10:01:56.612500 output: Image 2 (ramdisk-1)
297 10:01:56.612584 output: Description: unavailable
298 10:01:56.612667 output: Created: Sat Jun 10 11:01:56 2023
299 10:01:56.612753 output: Type: RAMDisk Image
300 10:01:56.612858 output: Compression: Unknown Compression
301 10:01:56.612913 output: Data Size: 17645313 Bytes = 17231.75 KiB = 16.83 MiB
302 10:01:56.612968 output: Architecture: AArch64
303 10:01:56.613027 output: OS: Linux
304 10:01:56.613084 output: Load Address: unavailable
305 10:01:56.613138 output: Entry Point: unavailable
306 10:01:56.613192 output: Hash algo: crc32
307 10:01:56.613245 output: Hash value: f375f2f6
308 10:01:56.613305 output: Default Configuration: 'conf-1'
309 10:01:56.613362 output: Configuration 0 (conf-1)
310 10:01:56.613416 output: Description: mt8192-asurada-spherion-r0
311 10:01:56.613470 output: Kernel: kernel-1
312 10:01:56.613523 output: Init Ramdisk: ramdisk-1
313 10:01:56.613579 output: FDT: fdt-1
314 10:01:56.613635 output: Loadables: kernel-1
315 10:01:56.613691 output:
316 10:01:56.613882 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 10:01:56.613984 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 10:01:56.614088 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 10:01:56.614193 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 10:01:56.614277 No LXC device requested
321 10:01:56.614357 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 10:01:56.614447 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 10:01:56.614528 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 10:01:56.614600 Checking files for TFTP limit of 4294967296 bytes.
325 10:01:56.615093 end: 1 tftp-deploy (duration 00:00:39) [common]
326 10:01:56.615208 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 10:01:56.615302 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 10:01:56.615440 substitutions:
329 10:01:56.615512 - {DTB}: 10670651/tftp-deploy-ehdb4tg6/dtb/mt8192-asurada-spherion-r0.dtb
330 10:01:56.615576 - {INITRD}: 10670651/tftp-deploy-ehdb4tg6/ramdisk/ramdisk.cpio.gz
331 10:01:56.615646 - {KERNEL}: 10670651/tftp-deploy-ehdb4tg6/kernel/Image
332 10:01:56.615711 - {LAVA_MAC}: None
333 10:01:56.615769 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10670651/extract-nfsrootfs-69r0vlv_
334 10:01:56.615827 - {NFS_SERVER_IP}: 192.168.201.1
335 10:01:56.615884 - {PRESEED_CONFIG}: None
336 10:01:56.615946 - {PRESEED_LOCAL}: None
337 10:01:56.616007 - {RAMDISK}: 10670651/tftp-deploy-ehdb4tg6/ramdisk/ramdisk.cpio.gz
338 10:01:56.616065 - {ROOT_PART}: None
339 10:01:56.616121 - {ROOT}: None
340 10:01:56.616177 - {SERVER_IP}: 192.168.201.1
341 10:01:56.616238 - {TEE}: None
342 10:01:56.616307 Parsed boot commands:
343 10:01:56.616367 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 10:01:56.616555 Parsed boot commands: tftpboot 192.168.201.1 10670651/tftp-deploy-ehdb4tg6/kernel/image.itb 10670651/tftp-deploy-ehdb4tg6/kernel/cmdline
345 10:01:56.616679 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 10:01:56.616830 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 10:01:56.616927 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 10:01:56.617018 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 10:01:56.617092 Not connected, no need to disconnect.
350 10:01:56.617172 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 10:01:56.617259 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 10:01:56.617329 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
353 10:01:56.620709 Setting prompt string to ['lava-test: # ']
354 10:01:56.621092 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 10:01:56.621206 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 10:01:56.621317 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 10:01:56.621411 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 10:01:56.621607 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 10:02:01.757166 >> Command sent successfully.
360 10:02:01.759650 Returned 0 in 5 seconds
361 10:02:01.860032 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 10:02:01.860465 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 10:02:01.860597 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 10:02:01.860726 Setting prompt string to 'Starting depthcharge on Spherion...'
366 10:02:01.860817 Changing prompt to 'Starting depthcharge on Spherion...'
367 10:02:01.860891 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 10:02:01.861167 [Enter `^Ec?' for help]
369 10:02:02.034113
370 10:02:02.034237
371 10:02:02.034309 F0: 102B 0000
372 10:02:02.034377
373 10:02:02.034440 F3: 1001 0000 [0200]
374 10:02:02.037397
375 10:02:02.037474 F3: 1001 0000
376 10:02:02.037545
377 10:02:02.037610 F7: 102D 0000
378 10:02:02.037670
379 10:02:02.040813 F1: 0000 0000
380 10:02:02.040881
381 10:02:02.040943 V0: 0000 0000 [0001]
382 10:02:02.041010
383 10:02:02.044018 00: 0007 8000
384 10:02:02.044117
385 10:02:02.044210 01: 0000 0000
386 10:02:02.044300
387 10:02:02.047635 BP: 0C00 0209 [0000]
388 10:02:02.047733
389 10:02:02.047822 G0: 1182 0000
390 10:02:02.047909
391 10:02:02.050852 EC: 0000 0021 [4000]
392 10:02:02.050949
393 10:02:02.051038 S7: 0000 0000 [0000]
394 10:02:02.051124
395 10:02:02.054486 CC: 0000 0000 [0001]
396 10:02:02.054583
397 10:02:02.054673 T0: 0000 0040 [010F]
398 10:02:02.054761
399 10:02:02.054852 Jump to BL
400 10:02:02.054937
401 10:02:02.080938
402 10:02:02.081044
403 10:02:02.081142
404 10:02:02.088287 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 10:02:02.092998 ARM64: Exception handlers installed.
406 10:02:02.095673 ARM64: Testing exception
407 10:02:02.098921 ARM64: Done test exception
408 10:02:02.105463 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 10:02:02.115569 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 10:02:02.122372 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 10:02:02.132288 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 10:02:02.138728 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 10:02:02.145848 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 10:02:02.157404 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 10:02:02.164459 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 10:02:02.183683 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 10:02:02.186842 WDT: Last reset was cold boot
418 10:02:02.190618 SPI1(PAD0) initialized at 2873684 Hz
419 10:02:02.193871 SPI5(PAD0) initialized at 992727 Hz
420 10:02:02.197023 VBOOT: Loading verstage.
421 10:02:02.203678 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 10:02:02.207078 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 10:02:02.210420 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 10:02:02.213723 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 10:02:02.221278 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 10:02:02.227769 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 10:02:02.238848 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 10:02:02.238937
429 10:02:02.239007
430 10:02:02.248660 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 10:02:02.252096 ARM64: Exception handlers installed.
432 10:02:02.255321 ARM64: Testing exception
433 10:02:02.255405 ARM64: Done test exception
434 10:02:02.261849 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 10:02:02.265395 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 10:02:02.279799 Probing TPM: . done!
437 10:02:02.279877 TPM ready after 0 ms
438 10:02:02.286547 Connected to device vid:did:rid of 1ae0:0028:00
439 10:02:02.293737 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 10:02:02.297369 Initialized TPM device CR50 revision 0
441 10:02:02.363946 tlcl_send_startup: Startup return code is 0
442 10:02:02.364049 TPM: setup succeeded
443 10:02:02.375009 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 10:02:02.384166 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 10:02:02.390679 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 10:02:02.403581 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 10:02:02.406883 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 10:02:02.412474 in-header: 03 07 00 00 08 00 00 00
449 10:02:02.415976 in-data: aa e4 47 04 13 02 00 00
450 10:02:02.419671 Chrome EC: UHEPI supported
451 10:02:02.426801 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 10:02:02.430488 in-header: 03 ad 00 00 08 00 00 00
453 10:02:02.434342 in-data: 00 20 20 08 00 00 00 00
454 10:02:02.434431 Phase 1
455 10:02:02.437929 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 10:02:02.445143 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 10:02:02.448591 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 10:02:02.452723 Recovery requested (1009000e)
459 10:02:02.462049 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 10:02:02.468371 tlcl_extend: response is 0
461 10:02:02.479955 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 10:02:02.483598 tlcl_extend: response is 0
463 10:02:02.490812 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 10:02:02.510700 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 10:02:02.517614 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 10:02:02.517701
467 10:02:02.517767
468 10:02:02.527372 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 10:02:02.530469 ARM64: Exception handlers installed.
470 10:02:02.534131 ARM64: Testing exception
471 10:02:02.534220 ARM64: Done test exception
472 10:02:02.555692 pmic_efuse_setting: Set efuses in 11 msecs
473 10:02:02.559345 pmwrap_interface_init: Select PMIF_VLD_RDY
474 10:02:02.565725 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 10:02:02.569371 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 10:02:02.576512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 10:02:02.579542 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 10:02:02.582631 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 10:02:02.589765 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 10:02:02.593435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 10:02:02.597482 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 10:02:02.604911 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 10:02:02.608710 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 10:02:02.612000 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 10:02:02.615672 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 10:02:02.622266 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 10:02:02.628587 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 10:02:02.632125 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 10:02:02.638964 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 10:02:02.646650 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 10:02:02.649745 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 10:02:02.656982 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 10:02:02.663705 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 10:02:02.666856 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 10:02:02.673768 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 10:02:02.680322 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 10:02:02.683865 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 10:02:02.690687 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 10:02:02.693683 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 10:02:02.700546 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 10:02:02.703676 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 10:02:02.710346 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 10:02:02.713877 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 10:02:02.720246 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 10:02:02.724095 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 10:02:02.730544 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 10:02:02.734201 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 10:02:02.740580 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 10:02:02.743535 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 10:02:02.750229 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 10:02:02.753639 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 10:02:02.760350 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 10:02:02.763946 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 10:02:02.767316 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 10:02:02.771117 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 10:02:02.777465 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 10:02:02.780673 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 10:02:02.784240 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 10:02:02.791046 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 10:02:02.794374 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 10:02:02.797540 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 10:02:02.804175 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 10:02:02.807320 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 10:02:02.810802 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 10:02:02.817431 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 10:02:02.827499 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 10:02:02.830713 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 10:02:02.841085 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 10:02:02.847544 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 10:02:02.854477 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 10:02:02.857473 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 10:02:02.860632 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 10:02:02.868707 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x13
534 10:02:02.875187 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 10:02:02.878520 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 10:02:02.884838 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 10:02:02.893436 [RTC]rtc_get_frequency_meter,154: input=15, output=772
538 10:02:02.902443 [RTC]rtc_get_frequency_meter,154: input=23, output=957
539 10:02:02.912398 [RTC]rtc_get_frequency_meter,154: input=19, output=864
540 10:02:02.921898 [RTC]rtc_get_frequency_meter,154: input=17, output=819
541 10:02:02.931209 [RTC]rtc_get_frequency_meter,154: input=16, output=795
542 10:02:02.934748 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 10:02:02.941290 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 10:02:02.944370 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
545 10:02:02.947794 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 10:02:02.951352 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
547 10:02:02.954410 ADC[4]: Raw value=902876 ID=7
548 10:02:02.957697 ADC[3]: Raw value=212810 ID=1
549 10:02:02.961361 RAM Code: 0x71
550 10:02:02.964689 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 10:02:02.967945 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 10:02:02.977873 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 10:02:02.984194 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 10:02:02.987501 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 10:02:02.991035 in-header: 03 07 00 00 08 00 00 00
556 10:02:02.994366 in-data: aa e4 47 04 13 02 00 00
557 10:02:02.997808 Chrome EC: UHEPI supported
558 10:02:03.004224 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 10:02:03.007708 in-header: 03 ed 00 00 08 00 00 00
560 10:02:03.010781 in-data: 80 20 60 08 00 00 00 00
561 10:02:03.014621 MRC: failed to locate region type 0.
562 10:02:03.021680 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 10:02:03.021766 DRAM-K: Running full calibration
564 10:02:03.028648 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 10:02:03.032518 header.status = 0x0
566 10:02:03.035727 header.version = 0x6 (expected: 0x6)
567 10:02:03.039089 header.size = 0xd00 (expected: 0xd00)
568 10:02:03.039174 header.flags = 0x0
569 10:02:03.046480 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 10:02:03.063875 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
571 10:02:03.071507 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 10:02:03.075164 dram_init: ddr_geometry: 2
573 10:02:03.075253 [EMI] MDL number = 2
574 10:02:03.078980 [EMI] Get MDL freq = 0
575 10:02:03.079068 dram_init: ddr_type: 0
576 10:02:03.083006 is_discrete_lpddr4: 1
577 10:02:03.085683 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 10:02:03.085771
579 10:02:03.085858
580 10:02:03.088930 [Bian_co] ETT version 0.0.0.1
581 10:02:03.092457 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 10:02:03.092545
583 10:02:03.095569 dramc_set_vcore_voltage set vcore to 650000
584 10:02:03.098908 Read voltage for 800, 4
585 10:02:03.098996 Vio18 = 0
586 10:02:03.102426 Vcore = 650000
587 10:02:03.102514 Vdram = 0
588 10:02:03.102601 Vddq = 0
589 10:02:03.102684 Vmddr = 0
590 10:02:03.105688 dram_init: config_dvfs: 1
591 10:02:03.112074 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 10:02:03.115455 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 10:02:03.118944 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
594 10:02:03.125338 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
595 10:02:03.128576 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 10:02:03.132072 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 10:02:03.135748 MEM_TYPE=3, freq_sel=18
598 10:02:03.135836 sv_algorithm_assistance_LP4_1600
599 10:02:03.139435 ============ PULL DRAM RESETB DOWN ============
600 10:02:03.147133 ========== PULL DRAM RESETB DOWN end =========
601 10:02:03.151318 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 10:02:03.154282 ===================================
603 10:02:03.154401 LPDDR4 DRAM CONFIGURATION
604 10:02:03.158432 ===================================
605 10:02:03.161967 EX_ROW_EN[0] = 0x0
606 10:02:03.162076 EX_ROW_EN[1] = 0x0
607 10:02:03.165455 LP4Y_EN = 0x0
608 10:02:03.165561 WORK_FSP = 0x0
609 10:02:03.168660 WL = 0x2
610 10:02:03.168769 RL = 0x2
611 10:02:03.171899 BL = 0x2
612 10:02:03.172000 RPST = 0x0
613 10:02:03.175736 RD_PRE = 0x0
614 10:02:03.175843 WR_PRE = 0x1
615 10:02:03.178498 WR_PST = 0x0
616 10:02:03.178601 DBI_WR = 0x0
617 10:02:03.182319 DBI_RD = 0x0
618 10:02:03.182432 OTF = 0x1
619 10:02:03.185578 ===================================
620 10:02:03.188600 ===================================
621 10:02:03.191835 ANA top config
622 10:02:03.195546 ===================================
623 10:02:03.198525 DLL_ASYNC_EN = 0
624 10:02:03.198631 ALL_SLAVE_EN = 1
625 10:02:03.201733 NEW_RANK_MODE = 1
626 10:02:03.205131 DLL_IDLE_MODE = 1
627 10:02:03.208387 LP45_APHY_COMB_EN = 1
628 10:02:03.211617 TX_ODT_DIS = 1
629 10:02:03.211722 NEW_8X_MODE = 1
630 10:02:03.215242 ===================================
631 10:02:03.218377 ===================================
632 10:02:03.221831 data_rate = 1600
633 10:02:03.225461 CKR = 1
634 10:02:03.228646 DQ_P2S_RATIO = 8
635 10:02:03.231850 ===================================
636 10:02:03.235031 CA_P2S_RATIO = 8
637 10:02:03.235140 DQ_CA_OPEN = 0
638 10:02:03.238622 DQ_SEMI_OPEN = 0
639 10:02:03.241825 CA_SEMI_OPEN = 0
640 10:02:03.245373 CA_FULL_RATE = 0
641 10:02:03.248866 DQ_CKDIV4_EN = 1
642 10:02:03.251982 CA_CKDIV4_EN = 1
643 10:02:03.252084 CA_PREDIV_EN = 0
644 10:02:03.255348 PH8_DLY = 0
645 10:02:03.258614 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 10:02:03.262328 DQ_AAMCK_DIV = 4
647 10:02:03.265587 CA_AAMCK_DIV = 4
648 10:02:03.268829 CA_ADMCK_DIV = 4
649 10:02:03.268906 DQ_TRACK_CA_EN = 0
650 10:02:03.271848 CA_PICK = 800
651 10:02:03.275175 CA_MCKIO = 800
652 10:02:03.278817 MCKIO_SEMI = 0
653 10:02:03.281967 PLL_FREQ = 3068
654 10:02:03.285182 DQ_UI_PI_RATIO = 32
655 10:02:03.285288 CA_UI_PI_RATIO = 0
656 10:02:03.288598 ===================================
657 10:02:03.291864 ===================================
658 10:02:03.295544 memory_type:LPDDR4
659 10:02:03.298486 GP_NUM : 10
660 10:02:03.298600 SRAM_EN : 1
661 10:02:03.302123 MD32_EN : 0
662 10:02:03.305761 ===================================
663 10:02:03.309167 [ANA_INIT] >>>>>>>>>>>>>>
664 10:02:03.309283 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 10:02:03.313009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 10:02:03.316178 ===================================
667 10:02:03.319245 data_rate = 1600,PCW = 0X7600
668 10:02:03.322806 ===================================
669 10:02:03.326438 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 10:02:03.333501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 10:02:03.337210 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 10:02:03.340784 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 10:02:03.344164 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 10:02:03.347322 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 10:02:03.350886 [ANA_INIT] flow start
676 10:02:03.354225 [ANA_INIT] PLL >>>>>>>>
677 10:02:03.354329 [ANA_INIT] PLL <<<<<<<<
678 10:02:03.358461 [ANA_INIT] MIDPI >>>>>>>>
679 10:02:03.361206 [ANA_INIT] MIDPI <<<<<<<<
680 10:02:03.364198 [ANA_INIT] DLL >>>>>>>>
681 10:02:03.364306 [ANA_INIT] flow end
682 10:02:03.367574 ============ LP4 DIFF to SE enter ============
683 10:02:03.374052 ============ LP4 DIFF to SE exit ============
684 10:02:03.374128 [ANA_INIT] <<<<<<<<<<<<<
685 10:02:03.377626 [Flow] Enable top DCM control >>>>>
686 10:02:03.381164 [Flow] Enable top DCM control <<<<<
687 10:02:03.384039 Enable DLL master slave shuffle
688 10:02:03.391146 ==============================================================
689 10:02:03.391250 Gating Mode config
690 10:02:03.397404 ==============================================================
691 10:02:03.401077 Config description:
692 10:02:03.410813 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 10:02:03.417338 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 10:02:03.420742 SELPH_MODE 0: By rank 1: By Phase
695 10:02:03.427598 ==============================================================
696 10:02:03.430828 GAT_TRACK_EN = 1
697 10:02:03.430935 RX_GATING_MODE = 2
698 10:02:03.434084 RX_GATING_TRACK_MODE = 2
699 10:02:03.437318 SELPH_MODE = 1
700 10:02:03.440928 PICG_EARLY_EN = 1
701 10:02:03.444660 VALID_LAT_VALUE = 1
702 10:02:03.448266 ==============================================================
703 10:02:03.451868 Enter into Gating configuration >>>>
704 10:02:03.455498 Exit from Gating configuration <<<<
705 10:02:03.459180 Enter into DVFS_PRE_config >>>>>
706 10:02:03.470052 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 10:02:03.473575 Exit from DVFS_PRE_config <<<<<
708 10:02:03.477025 Enter into PICG configuration >>>>
709 10:02:03.480859 Exit from PICG configuration <<<<
710 10:02:03.484467 [RX_INPUT] configuration >>>>>
711 10:02:03.484551 [RX_INPUT] configuration <<<<<
712 10:02:03.492019 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 10:02:03.495699 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 10:02:03.502782 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 10:02:03.510918 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 10:02:03.513646 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 10:02:03.520966 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 10:02:03.524428 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 10:02:03.528468 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 10:02:03.531821 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 10:02:03.535696 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 10:02:03.539702 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 10:02:03.546891 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 10:02:03.550236 ===================================
725 10:02:03.550315 LPDDR4 DRAM CONFIGURATION
726 10:02:03.553839 ===================================
727 10:02:03.557428 EX_ROW_EN[0] = 0x0
728 10:02:03.557512 EX_ROW_EN[1] = 0x0
729 10:02:03.561231 LP4Y_EN = 0x0
730 10:02:03.561315 WORK_FSP = 0x0
731 10:02:03.564912 WL = 0x2
732 10:02:03.564996 RL = 0x2
733 10:02:03.568575 BL = 0x2
734 10:02:03.568659 RPST = 0x0
735 10:02:03.572124 RD_PRE = 0x0
736 10:02:03.572208 WR_PRE = 0x1
737 10:02:03.576426 WR_PST = 0x0
738 10:02:03.576511 DBI_WR = 0x0
739 10:02:03.579498 DBI_RD = 0x0
740 10:02:03.579591 OTF = 0x1
741 10:02:03.583562 ===================================
742 10:02:03.587570 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 10:02:03.591266 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 10:02:03.594306 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 10:02:03.598102 ===================================
746 10:02:03.602070 LPDDR4 DRAM CONFIGURATION
747 10:02:03.605570 ===================================
748 10:02:03.605654 EX_ROW_EN[0] = 0x10
749 10:02:03.610102 EX_ROW_EN[1] = 0x0
750 10:02:03.610187 LP4Y_EN = 0x0
751 10:02:03.613069 WORK_FSP = 0x0
752 10:02:03.613153 WL = 0x2
753 10:02:03.617026 RL = 0x2
754 10:02:03.617110 BL = 0x2
755 10:02:03.617176 RPST = 0x0
756 10:02:03.620520 RD_PRE = 0x0
757 10:02:03.620604 WR_PRE = 0x1
758 10:02:03.624939 WR_PST = 0x0
759 10:02:03.625024 DBI_WR = 0x0
760 10:02:03.628681 DBI_RD = 0x0
761 10:02:03.628826 OTF = 0x1
762 10:02:03.632082 ===================================
763 10:02:03.639448 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 10:02:03.643307 nWR fixed to 40
765 10:02:03.643392 [ModeRegInit_LP4] CH0 RK0
766 10:02:03.647152 [ModeRegInit_LP4] CH0 RK1
767 10:02:03.650537 [ModeRegInit_LP4] CH1 RK0
768 10:02:03.650622 [ModeRegInit_LP4] CH1 RK1
769 10:02:03.654278 match AC timing 13
770 10:02:03.658352 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 10:02:03.661997 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 10:02:03.665977 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 10:02:03.673046 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 10:02:03.676902 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 10:02:03.676988 [EMI DOE] emi_dcm 0
776 10:02:03.680691 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 10:02:03.680834 ==
778 10:02:03.683932 Dram Type= 6, Freq= 0, CH_0, rank 0
779 10:02:03.688033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 10:02:03.688118 ==
781 10:02:03.695202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 10:02:03.699103 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 10:02:03.710217 [CA 0] Center 38 (7~69) winsize 63
784 10:02:03.713351 [CA 1] Center 38 (7~69) winsize 63
785 10:02:03.716682 [CA 2] Center 35 (5~66) winsize 62
786 10:02:03.719873 [CA 3] Center 35 (4~66) winsize 63
787 10:02:03.724080 [CA 4] Center 34 (4~65) winsize 62
788 10:02:03.727631 [CA 5] Center 33 (3~64) winsize 62
789 10:02:03.727716
790 10:02:03.731416 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 10:02:03.731500
792 10:02:03.734712 [CATrainingPosCal] consider 1 rank data
793 10:02:03.739576 u2DelayCellTimex100 = 270/100 ps
794 10:02:03.742213 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
795 10:02:03.745421 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 10:02:03.749058 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 10:02:03.752108 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
798 10:02:03.755599 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 10:02:03.758821 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 10:02:03.758906
801 10:02:03.762182 CA PerBit enable=1, Macro0, CA PI delay=33
802 10:02:03.762267
803 10:02:03.765497 [CBTSetCACLKResult] CA Dly = 33
804 10:02:03.768738 CS Dly: 6 (0~37)
805 10:02:03.768842 ==
806 10:02:03.772160 Dram Type= 6, Freq= 0, CH_0, rank 1
807 10:02:03.775358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 10:02:03.775436 ==
809 10:02:03.783239 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 10:02:03.785756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 10:02:03.796102 [CA 0] Center 38 (7~69) winsize 63
812 10:02:03.799403 [CA 1] Center 38 (7~69) winsize 63
813 10:02:03.802736 [CA 2] Center 36 (5~67) winsize 63
814 10:02:03.806345 [CA 3] Center 35 (5~66) winsize 62
815 10:02:03.809608 [CA 4] Center 35 (4~66) winsize 63
816 10:02:03.812927 [CA 5] Center 34 (4~65) winsize 62
817 10:02:03.813013
818 10:02:03.816123 [CmdBusTrainingLP45] Vref(ca) range 1: 34
819 10:02:03.816209
820 10:02:03.819508 [CATrainingPosCal] consider 2 rank data
821 10:02:03.822869 u2DelayCellTimex100 = 270/100 ps
822 10:02:03.825963 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 10:02:03.832724 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 10:02:03.836122 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
825 10:02:03.839746 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 10:02:03.842920 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 10:02:03.845836 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 10:02:03.845922
829 10:02:03.849134 CA PerBit enable=1, Macro0, CA PI delay=34
830 10:02:03.849220
831 10:02:03.852430 [CBTSetCACLKResult] CA Dly = 34
832 10:02:03.852515 CS Dly: 6 (0~38)
833 10:02:03.852583
834 10:02:03.859072 ----->DramcWriteLeveling(PI) begin...
835 10:02:03.859160 ==
836 10:02:03.862211 Dram Type= 6, Freq= 0, CH_0, rank 0
837 10:02:03.865751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 10:02:03.865837 ==
839 10:02:03.869013 Write leveling (Byte 0): 33 => 33
840 10:02:03.872300 Write leveling (Byte 1): 29 => 29
841 10:02:03.875500 DramcWriteLeveling(PI) end<-----
842 10:02:03.875585
843 10:02:03.875653 ==
844 10:02:03.879059 Dram Type= 6, Freq= 0, CH_0, rank 0
845 10:02:03.882343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 10:02:03.882429 ==
847 10:02:03.885715 [Gating] SW mode calibration
848 10:02:03.892976 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 10:02:03.897283 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 10:02:03.900380 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
851 10:02:03.907470 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
852 10:02:03.910648 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
853 10:02:03.914426 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 10:02:03.921464 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 10:02:03.925007 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 10:02:03.927812 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 10:02:03.931460 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 10:02:03.938122 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 10:02:03.940978 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:02:03.944636 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:02:03.950916 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 10:02:03.954592 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 10:02:03.958101 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 10:02:03.964430 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 10:02:03.968151 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 10:02:03.971415 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
867 10:02:03.977668 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
868 10:02:03.980983 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
869 10:02:03.984434 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 10:02:03.991242 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 10:02:03.994406 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 10:02:03.997422 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 10:02:04.004214 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 10:02:04.007740 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 10:02:04.010931 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
876 10:02:04.017223 0 9 8 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
877 10:02:04.020631 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
878 10:02:04.024626 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 10:02:04.030651 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 10:02:04.034214 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 10:02:04.037180 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 10:02:04.044167 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 10:02:04.047567 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
884 10:02:04.050538 0 10 8 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
885 10:02:04.057532 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 10:02:04.060570 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 10:02:04.064101 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 10:02:04.067398 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 10:02:04.074186 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 10:02:04.077334 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 10:02:04.080615 0 11 4 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
892 10:02:04.087032 0 11 8 | B1->B0 | 2f2f 4646 | 1 0 | (1 1) (0 0)
893 10:02:04.090800 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
894 10:02:04.093735 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 10:02:04.100408 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 10:02:04.104234 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 10:02:04.106962 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 10:02:04.114335 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 10:02:04.117518 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 10:02:04.120229 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
901 10:02:04.126901 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 10:02:04.130652 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 10:02:04.133619 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 10:02:04.140085 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 10:02:04.143625 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 10:02:04.147022 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 10:02:04.153602 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 10:02:04.156890 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 10:02:04.160387 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 10:02:04.166840 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 10:02:04.170076 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 10:02:04.173303 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 10:02:04.179932 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 10:02:04.183599 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 10:02:04.186839 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
916 10:02:04.193536 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
917 10:02:04.193622 Total UI for P1: 0, mck2ui 16
918 10:02:04.197207 best dqsien dly found for B0: ( 0, 14, 4)
919 10:02:04.203607 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 10:02:04.206664 Total UI for P1: 0, mck2ui 16
921 10:02:04.210114 best dqsien dly found for B1: ( 0, 14, 8)
922 10:02:04.213604 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
923 10:02:04.216710 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
924 10:02:04.216832
925 10:02:04.219711 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
926 10:02:04.223125 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
927 10:02:04.226565 [Gating] SW calibration Done
928 10:02:04.226650 ==
929 10:02:04.230259 Dram Type= 6, Freq= 0, CH_0, rank 0
930 10:02:04.233142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 10:02:04.233227 ==
932 10:02:04.236882 RX Vref Scan: 0
933 10:02:04.236966
934 10:02:04.237033 RX Vref 0 -> 0, step: 1
935 10:02:04.240103
936 10:02:04.240188 RX Delay -130 -> 252, step: 16
937 10:02:04.246777 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
938 10:02:04.249936 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 10:02:04.252975 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
940 10:02:04.256529 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
941 10:02:04.259862 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
942 10:02:04.266834 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
943 10:02:04.269657 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
944 10:02:04.272904 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 10:02:04.276623 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 10:02:04.279792 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
947 10:02:04.286412 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
948 10:02:04.290005 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 10:02:04.292823 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
950 10:02:04.296289 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 10:02:04.299668 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 10:02:04.306280 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
953 10:02:04.306386 ==
954 10:02:04.309790 Dram Type= 6, Freq= 0, CH_0, rank 0
955 10:02:04.313137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 10:02:04.313240 ==
957 10:02:04.313343 DQS Delay:
958 10:02:04.316488 DQS0 = 0, DQS1 = 0
959 10:02:04.316592 DQM Delay:
960 10:02:04.320032 DQM0 = 89, DQM1 = 80
961 10:02:04.320132 DQ Delay:
962 10:02:04.322662 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
963 10:02:04.326068 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
964 10:02:04.329990 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
965 10:02:04.333061 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
966 10:02:04.333137
967 10:02:04.333224
968 10:02:04.333323 ==
969 10:02:04.336097 Dram Type= 6, Freq= 0, CH_0, rank 0
970 10:02:04.339535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 10:02:04.343080 ==
972 10:02:04.343182
973 10:02:04.343284
974 10:02:04.343381 TX Vref Scan disable
975 10:02:04.345900 == TX Byte 0 ==
976 10:02:04.349188 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
977 10:02:04.352955 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
978 10:02:04.356274 == TX Byte 1 ==
979 10:02:04.359306 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
980 10:02:04.362690 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
981 10:02:04.366463 ==
982 10:02:04.369904 Dram Type= 6, Freq= 0, CH_0, rank 0
983 10:02:04.372675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 10:02:04.372783 ==
985 10:02:04.385325 TX Vref=22, minBit 11, minWin=26, winSum=440
986 10:02:04.388853 TX Vref=24, minBit 6, minWin=27, winSum=443
987 10:02:04.392502 TX Vref=26, minBit 11, minWin=27, winSum=447
988 10:02:04.395448 TX Vref=28, minBit 8, minWin=27, winSum=451
989 10:02:04.398913 TX Vref=30, minBit 5, minWin=28, winSum=455
990 10:02:04.405209 TX Vref=32, minBit 3, minWin=28, winSum=454
991 10:02:04.408663 [TxChooseVref] Worse bit 5, Min win 28, Win sum 455, Final Vref 30
992 10:02:04.408793
993 10:02:04.412287 Final TX Range 1 Vref 30
994 10:02:04.412389
995 10:02:04.412492 ==
996 10:02:04.415207 Dram Type= 6, Freq= 0, CH_0, rank 0
997 10:02:04.419119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 10:02:04.422000 ==
999 10:02:04.422101
1000 10:02:04.422204
1001 10:02:04.422303 TX Vref Scan disable
1002 10:02:04.425727 == TX Byte 0 ==
1003 10:02:04.429032 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1004 10:02:04.432337 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1005 10:02:04.435717 == TX Byte 1 ==
1006 10:02:04.439109 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1007 10:02:04.442249 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1008 10:02:04.445778
1009 10:02:04.445879 [DATLAT]
1010 10:02:04.445980 Freq=800, CH0 RK0
1011 10:02:04.446080
1012 10:02:04.448999 DATLAT Default: 0xa
1013 10:02:04.449102 0, 0xFFFF, sum = 0
1014 10:02:04.452594 1, 0xFFFF, sum = 0
1015 10:02:04.452695 2, 0xFFFF, sum = 0
1016 10:02:04.455477 3, 0xFFFF, sum = 0
1017 10:02:04.455579 4, 0xFFFF, sum = 0
1018 10:02:04.458946 5, 0xFFFF, sum = 0
1019 10:02:04.459048 6, 0xFFFF, sum = 0
1020 10:02:04.462714 7, 0xFFFF, sum = 0
1021 10:02:04.465815 8, 0xFFFF, sum = 0
1022 10:02:04.465917 9, 0x0, sum = 1
1023 10:02:04.466024 10, 0x0, sum = 2
1024 10:02:04.469249 11, 0x0, sum = 3
1025 10:02:04.469333 12, 0x0, sum = 4
1026 10:02:04.472364 best_step = 10
1027 10:02:04.472462
1028 10:02:04.472563 ==
1029 10:02:04.475624 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 10:02:04.479333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 10:02:04.479437 ==
1032 10:02:04.482080 RX Vref Scan: 1
1033 10:02:04.482182
1034 10:02:04.482280 Set Vref Range= 32 -> 127
1035 10:02:04.482381
1036 10:02:04.485498 RX Vref 32 -> 127, step: 1
1037 10:02:04.485599
1038 10:02:04.488708 RX Delay -79 -> 252, step: 8
1039 10:02:04.488813
1040 10:02:04.492191 Set Vref, RX VrefLevel [Byte0]: 32
1041 10:02:04.495599 [Byte1]: 32
1042 10:02:04.495704
1043 10:02:04.498748 Set Vref, RX VrefLevel [Byte0]: 33
1044 10:02:04.502022 [Byte1]: 33
1045 10:02:04.505619
1046 10:02:04.505719 Set Vref, RX VrefLevel [Byte0]: 34
1047 10:02:04.508883 [Byte1]: 34
1048 10:02:04.513214
1049 10:02:04.513317 Set Vref, RX VrefLevel [Byte0]: 35
1050 10:02:04.516475 [Byte1]: 35
1051 10:02:04.521598
1052 10:02:04.521676 Set Vref, RX VrefLevel [Byte0]: 36
1053 10:02:04.524689 [Byte1]: 36
1054 10:02:04.528283
1055 10:02:04.528382 Set Vref, RX VrefLevel [Byte0]: 37
1056 10:02:04.531679 [Byte1]: 37
1057 10:02:04.535956
1058 10:02:04.536047 Set Vref, RX VrefLevel [Byte0]: 38
1059 10:02:04.539548 [Byte1]: 38
1060 10:02:04.543450
1061 10:02:04.543549 Set Vref, RX VrefLevel [Byte0]: 39
1062 10:02:04.546821 [Byte1]: 39
1063 10:02:04.551061
1064 10:02:04.551161 Set Vref, RX VrefLevel [Byte0]: 40
1065 10:02:04.554209 [Byte1]: 40
1066 10:02:04.558834
1067 10:02:04.558934 Set Vref, RX VrefLevel [Byte0]: 41
1068 10:02:04.562331 [Byte1]: 41
1069 10:02:04.566859
1070 10:02:04.566960 Set Vref, RX VrefLevel [Byte0]: 42
1071 10:02:04.569816 [Byte1]: 42
1072 10:02:04.574372
1073 10:02:04.574482 Set Vref, RX VrefLevel [Byte0]: 43
1074 10:02:04.577508 [Byte1]: 43
1075 10:02:04.582185
1076 10:02:04.582286 Set Vref, RX VrefLevel [Byte0]: 44
1077 10:02:04.585522 [Byte1]: 44
1078 10:02:04.589139
1079 10:02:04.589218 Set Vref, RX VrefLevel [Byte0]: 45
1080 10:02:04.592205 [Byte1]: 45
1081 10:02:04.596495
1082 10:02:04.596574 Set Vref, RX VrefLevel [Byte0]: 46
1083 10:02:04.599576 [Byte1]: 46
1084 10:02:04.604218
1085 10:02:04.604320 Set Vref, RX VrefLevel [Byte0]: 47
1086 10:02:04.607112 [Byte1]: 47
1087 10:02:04.611401
1088 10:02:04.611507 Set Vref, RX VrefLevel [Byte0]: 48
1089 10:02:04.614882 [Byte1]: 48
1090 10:02:04.618960
1091 10:02:04.619063 Set Vref, RX VrefLevel [Byte0]: 49
1092 10:02:04.622257 [Byte1]: 49
1093 10:02:04.626620
1094 10:02:04.626719 Set Vref, RX VrefLevel [Byte0]: 50
1095 10:02:04.629866 [Byte1]: 50
1096 10:02:04.634053
1097 10:02:04.634154 Set Vref, RX VrefLevel [Byte0]: 51
1098 10:02:04.637686 [Byte1]: 51
1099 10:02:04.641779
1100 10:02:04.641877 Set Vref, RX VrefLevel [Byte0]: 52
1101 10:02:04.645190 [Byte1]: 52
1102 10:02:04.649349
1103 10:02:04.649423 Set Vref, RX VrefLevel [Byte0]: 53
1104 10:02:04.652746 [Byte1]: 53
1105 10:02:04.656569
1106 10:02:04.656672 Set Vref, RX VrefLevel [Byte0]: 54
1107 10:02:04.659848 [Byte1]: 54
1108 10:02:04.664494
1109 10:02:04.664594 Set Vref, RX VrefLevel [Byte0]: 55
1110 10:02:04.667696 [Byte1]: 55
1111 10:02:04.671808
1112 10:02:04.671886 Set Vref, RX VrefLevel [Byte0]: 56
1113 10:02:04.675162 [Byte1]: 56
1114 10:02:04.679298
1115 10:02:04.679397 Set Vref, RX VrefLevel [Byte0]: 57
1116 10:02:04.682982 [Byte1]: 57
1117 10:02:04.687298
1118 10:02:04.687401 Set Vref, RX VrefLevel [Byte0]: 58
1119 10:02:04.690038 [Byte1]: 58
1120 10:02:04.694453
1121 10:02:04.694552 Set Vref, RX VrefLevel [Byte0]: 59
1122 10:02:04.697903 [Byte1]: 59
1123 10:02:04.702030
1124 10:02:04.702133 Set Vref, RX VrefLevel [Byte0]: 60
1125 10:02:04.705570 [Byte1]: 60
1126 10:02:04.709465
1127 10:02:04.709572 Set Vref, RX VrefLevel [Byte0]: 61
1128 10:02:04.712754 [Byte1]: 61
1129 10:02:04.716996
1130 10:02:04.717095 Set Vref, RX VrefLevel [Byte0]: 62
1131 10:02:04.720742 [Byte1]: 62
1132 10:02:04.724493
1133 10:02:04.724593 Set Vref, RX VrefLevel [Byte0]: 63
1134 10:02:04.728267 [Byte1]: 63
1135 10:02:04.732376
1136 10:02:04.732475 Set Vref, RX VrefLevel [Byte0]: 64
1137 10:02:04.735567 [Byte1]: 64
1138 10:02:04.739629
1139 10:02:04.739731 Set Vref, RX VrefLevel [Byte0]: 65
1140 10:02:04.742914 [Byte1]: 65
1141 10:02:04.747232
1142 10:02:04.747331 Set Vref, RX VrefLevel [Byte0]: 66
1143 10:02:04.750652 [Byte1]: 66
1144 10:02:04.755300
1145 10:02:04.755399 Set Vref, RX VrefLevel [Byte0]: 67
1146 10:02:04.758475 [Byte1]: 67
1147 10:02:04.762468
1148 10:02:04.762546 Set Vref, RX VrefLevel [Byte0]: 68
1149 10:02:04.765957 [Byte1]: 68
1150 10:02:04.770273
1151 10:02:04.770348 Set Vref, RX VrefLevel [Byte0]: 69
1152 10:02:04.773251 [Byte1]: 69
1153 10:02:04.777503
1154 10:02:04.777599 Set Vref, RX VrefLevel [Byte0]: 70
1155 10:02:04.781207 [Byte1]: 70
1156 10:02:04.784980
1157 10:02:04.785080 Set Vref, RX VrefLevel [Byte0]: 71
1158 10:02:04.788297 [Byte1]: 71
1159 10:02:04.792407
1160 10:02:04.792510 Set Vref, RX VrefLevel [Byte0]: 72
1161 10:02:04.795970 [Byte1]: 72
1162 10:02:04.800156
1163 10:02:04.800259 Set Vref, RX VrefLevel [Byte0]: 73
1164 10:02:04.803289 [Byte1]: 73
1165 10:02:04.807600
1166 10:02:04.807706 Set Vref, RX VrefLevel [Byte0]: 74
1167 10:02:04.811131 [Byte1]: 74
1168 10:02:04.815141
1169 10:02:04.815244 Set Vref, RX VrefLevel [Byte0]: 75
1170 10:02:04.818744 [Byte1]: 75
1171 10:02:04.822727
1172 10:02:04.822829 Set Vref, RX VrefLevel [Byte0]: 76
1173 10:02:04.826456 [Byte1]: 76
1174 10:02:04.830670
1175 10:02:04.830770 Set Vref, RX VrefLevel [Byte0]: 77
1176 10:02:04.833512 [Byte1]: 77
1177 10:02:04.838268
1178 10:02:04.838369 Final RX Vref Byte 0 = 62 to rank0
1179 10:02:04.841100 Final RX Vref Byte 1 = 61 to rank0
1180 10:02:04.844861 Final RX Vref Byte 0 = 62 to rank1
1181 10:02:04.848119 Final RX Vref Byte 1 = 61 to rank1==
1182 10:02:04.851089 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 10:02:04.858158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 10:02:04.858264 ==
1185 10:02:04.858365 DQS Delay:
1186 10:02:04.858466 DQS0 = 0, DQS1 = 0
1187 10:02:04.861482 DQM Delay:
1188 10:02:04.861581 DQM0 = 93, DQM1 = 82
1189 10:02:04.864677 DQ Delay:
1190 10:02:04.867914 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1191 10:02:04.871327 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1192 10:02:04.871431 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1193 10:02:04.877782 DQ12 =88, DQ13 =80, DQ14 =92, DQ15 =92
1194 10:02:04.877883
1195 10:02:04.877967
1196 10:02:04.884435 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 393 ps
1197 10:02:04.887709 CH0 RK0: MR19=606, MR18=3F3A
1198 10:02:04.894550 CH0_RK0: MR19=0x606, MR18=0x3F3A, DQSOSC=393, MR23=63, INC=95, DEC=63
1199 10:02:04.894656
1200 10:02:04.897868 ----->DramcWriteLeveling(PI) begin...
1201 10:02:04.897973 ==
1202 10:02:04.901137 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 10:02:04.904380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 10:02:04.904480 ==
1205 10:02:04.907755 Write leveling (Byte 0): 34 => 34
1206 10:02:04.911519 Write leveling (Byte 1): 28 => 28
1207 10:02:04.914595 DramcWriteLeveling(PI) end<-----
1208 10:02:04.914700
1209 10:02:04.914802 ==
1210 10:02:04.918268 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 10:02:04.921382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 10:02:04.921484 ==
1213 10:02:04.924489 [Gating] SW mode calibration
1214 10:02:04.931003 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 10:02:04.937897 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 10:02:04.940960 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 10:02:04.944556 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1218 10:02:04.950922 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 10:02:04.954468 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 10:02:04.957938 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 10:02:05.004932 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 10:02:05.005045 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 10:02:05.005341 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 10:02:05.005444 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 10:02:05.005733 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 10:02:05.006050 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 10:02:05.006150 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 10:02:05.006437 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 10:02:05.006554 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 10:02:05.006704 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 10:02:05.034338 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 10:02:05.034456 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1233 10:02:05.034737 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1234 10:02:05.034846 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1235 10:02:05.035241 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 10:02:05.035799 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 10:02:05.035899 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 10:02:05.038229 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 10:02:05.041507 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 10:02:05.048384 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 10:02:05.051658 0 9 4 | B1->B0 | 2322 2424 | 1 1 | (0 0) (1 1)
1242 10:02:05.054948 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1243 10:02:05.061582 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 10:02:05.064778 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 10:02:05.068007 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 10:02:05.074513 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 10:02:05.077842 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 10:02:05.081023 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 10:02:05.087878 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
1250 10:02:05.090861 0 10 8 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1251 10:02:05.094384 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 10:02:05.101022 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 10:02:05.104554 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 10:02:05.107884 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 10:02:05.114327 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 10:02:05.117752 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 10:02:05.121117 0 11 4 | B1->B0 | 2929 3131 | 0 0 | (0 0) (0 0)
1258 10:02:05.124200 0 11 8 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
1259 10:02:05.131243 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 10:02:05.134125 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 10:02:05.138297 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 10:02:05.145065 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 10:02:05.148754 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 10:02:05.152429 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 10:02:05.155831 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1266 10:02:05.162456 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 10:02:05.165704 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 10:02:05.169476 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 10:02:05.172664 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 10:02:05.179765 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 10:02:05.182735 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 10:02:05.186346 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 10:02:05.193109 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 10:02:05.195976 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 10:02:05.199467 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 10:02:05.205958 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 10:02:05.209025 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 10:02:05.212939 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 10:02:05.219034 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 10:02:05.222505 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 10:02:05.225780 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1282 10:02:05.232412 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 10:02:05.232495 Total UI for P1: 0, mck2ui 16
1284 10:02:05.239373 best dqsien dly found for B0: ( 0, 14, 4)
1285 10:02:05.239461 Total UI for P1: 0, mck2ui 16
1286 10:02:05.245733 best dqsien dly found for B1: ( 0, 14, 4)
1287 10:02:05.248947 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1288 10:02:05.252144 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1289 10:02:05.252227
1290 10:02:05.255829 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1291 10:02:05.259915 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1292 10:02:05.262493 [Gating] SW calibration Done
1293 10:02:05.262581 ==
1294 10:02:05.266094 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 10:02:05.269349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 10:02:05.269526 ==
1297 10:02:05.272856 RX Vref Scan: 0
1298 10:02:05.273040
1299 10:02:05.273141 RX Vref 0 -> 0, step: 1
1300 10:02:05.273226
1301 10:02:05.276657 RX Delay -130 -> 252, step: 16
1302 10:02:05.279456 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1303 10:02:05.285946 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1304 10:02:05.289219 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1305 10:02:05.293034 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1306 10:02:05.296065 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1307 10:02:05.299437 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1308 10:02:05.305937 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1309 10:02:05.309266 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1310 10:02:05.313132 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1311 10:02:05.316347 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1312 10:02:05.319603 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1313 10:02:05.326542 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1314 10:02:05.329579 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1315 10:02:05.332809 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1316 10:02:05.336188 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1317 10:02:05.339559 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1318 10:02:05.343046 ==
1319 10:02:05.346566 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 10:02:05.349610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 10:02:05.350180 ==
1322 10:02:05.350550 DQS Delay:
1323 10:02:05.353040 DQS0 = 0, DQS1 = 0
1324 10:02:05.353610 DQM Delay:
1325 10:02:05.355958 DQM0 = 88, DQM1 = 80
1326 10:02:05.356434 DQ Delay:
1327 10:02:05.359238 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1328 10:02:05.362535 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1329 10:02:05.366163 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1330 10:02:05.369326 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1331 10:02:05.369914
1332 10:02:05.370287
1333 10:02:05.370630 ==
1334 10:02:05.373058 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 10:02:05.376212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 10:02:05.376818 ==
1337 10:02:05.377205
1338 10:02:05.377556
1339 10:02:05.379623 TX Vref Scan disable
1340 10:02:05.382864 == TX Byte 0 ==
1341 10:02:05.386254 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1342 10:02:05.389566 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1343 10:02:05.392335 == TX Byte 1 ==
1344 10:02:05.395912 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1345 10:02:05.399537 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1346 10:02:05.400121 ==
1347 10:02:05.403350 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 10:02:05.408740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 10:02:05.409345 ==
1350 10:02:05.421743 TX Vref=22, minBit 1, minWin=27, winSum=444
1351 10:02:05.425082 TX Vref=24, minBit 8, minWin=27, winSum=449
1352 10:02:05.428159 TX Vref=26, minBit 8, minWin=27, winSum=452
1353 10:02:05.431747 TX Vref=28, minBit 8, minWin=27, winSum=455
1354 10:02:05.435065 TX Vref=30, minBit 8, minWin=27, winSum=455
1355 10:02:05.441726 TX Vref=32, minBit 8, minWin=27, winSum=459
1356 10:02:05.445493 [TxChooseVref] Worse bit 8, Min win 27, Win sum 459, Final Vref 32
1357 10:02:05.446092
1358 10:02:05.447995 Final TX Range 1 Vref 32
1359 10:02:05.448471
1360 10:02:05.448866 ==
1361 10:02:05.451269 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 10:02:05.454540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 10:02:05.455062 ==
1364 10:02:05.457902
1365 10:02:05.458363
1366 10:02:05.458720 TX Vref Scan disable
1367 10:02:05.461484 == TX Byte 0 ==
1368 10:02:05.464498 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1369 10:02:05.471006 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1370 10:02:05.471470 == TX Byte 1 ==
1371 10:02:05.474630 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1372 10:02:05.481499 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1373 10:02:05.481933
1374 10:02:05.482206 [DATLAT]
1375 10:02:05.482443 Freq=800, CH0 RK1
1376 10:02:05.482672
1377 10:02:05.485213 DATLAT Default: 0xa
1378 10:02:05.485744 0, 0xFFFF, sum = 0
1379 10:02:05.487812 1, 0xFFFF, sum = 0
1380 10:02:05.491593 2, 0xFFFF, sum = 0
1381 10:02:05.492023 3, 0xFFFF, sum = 0
1382 10:02:05.494358 4, 0xFFFF, sum = 0
1383 10:02:05.494781 5, 0xFFFF, sum = 0
1384 10:02:05.497670 6, 0xFFFF, sum = 0
1385 10:02:05.498045 7, 0xFFFF, sum = 0
1386 10:02:05.501184 8, 0xFFFF, sum = 0
1387 10:02:05.501514 9, 0x0, sum = 1
1388 10:02:05.504539 10, 0x0, sum = 2
1389 10:02:05.504893 11, 0x0, sum = 3
1390 10:02:05.505159 12, 0x0, sum = 4
1391 10:02:05.507552 best_step = 10
1392 10:02:05.507815
1393 10:02:05.508048 ==
1394 10:02:05.510802 Dram Type= 6, Freq= 0, CH_0, rank 1
1395 10:02:05.514261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 10:02:05.514683 ==
1397 10:02:05.518131 RX Vref Scan: 0
1398 10:02:05.518549
1399 10:02:05.518877 RX Vref 0 -> 0, step: 1
1400 10:02:05.520963
1401 10:02:05.521380 RX Delay -79 -> 252, step: 8
1402 10:02:05.528539 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1403 10:02:05.531795 iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224
1404 10:02:05.534616 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1405 10:02:05.537903 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1406 10:02:05.541619 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1407 10:02:05.548059 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1408 10:02:05.551176 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1409 10:02:05.555145 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1410 10:02:05.557538 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1411 10:02:05.561270 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1412 10:02:05.567936 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1413 10:02:05.571947 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1414 10:02:05.574386 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1415 10:02:05.578519 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1416 10:02:05.585206 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1417 10:02:05.587821 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1418 10:02:05.588292 ==
1419 10:02:05.591368 Dram Type= 6, Freq= 0, CH_0, rank 1
1420 10:02:05.594501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 10:02:05.595060 ==
1422 10:02:05.595425 DQS Delay:
1423 10:02:05.597946 DQS0 = 0, DQS1 = 0
1424 10:02:05.598483 DQM Delay:
1425 10:02:05.601375 DQM0 = 91, DQM1 = 81
1426 10:02:05.601945 DQ Delay:
1427 10:02:05.604827 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =84
1428 10:02:05.608073 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1429 10:02:05.611405 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1430 10:02:05.614720 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1431 10:02:05.615277
1432 10:02:05.615639
1433 10:02:05.624892 [DQSOSCAuto] RK1, (LSB)MR18= 0x421c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1434 10:02:05.625440 CH0 RK1: MR19=606, MR18=421C
1435 10:02:05.630935 CH0_RK1: MR19=0x606, MR18=0x421C, DQSOSC=393, MR23=63, INC=95, DEC=63
1436 10:02:05.634605 [RxdqsGatingPostProcess] freq 800
1437 10:02:05.641235 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1438 10:02:05.644727 Pre-setting of DQS Precalculation
1439 10:02:05.648147 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1440 10:02:05.648705 ==
1441 10:02:05.650635 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 10:02:05.657642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 10:02:05.658215 ==
1444 10:02:05.660757 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1445 10:02:05.667477 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1446 10:02:05.676976 [CA 0] Center 36 (6~67) winsize 62
1447 10:02:05.680104 [CA 1] Center 37 (6~68) winsize 63
1448 10:02:05.683232 [CA 2] Center 35 (5~65) winsize 61
1449 10:02:05.686233 [CA 3] Center 34 (4~65) winsize 62
1450 10:02:05.690033 [CA 4] Center 34 (4~65) winsize 62
1451 10:02:05.693637 [CA 5] Center 33 (3~64) winsize 62
1452 10:02:05.694206
1453 10:02:05.696563 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1454 10:02:05.697092
1455 10:02:05.700284 [CATrainingPosCal] consider 1 rank data
1456 10:02:05.702875 u2DelayCellTimex100 = 270/100 ps
1457 10:02:05.706739 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1458 10:02:05.709568 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1459 10:02:05.716549 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1460 10:02:05.719933 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1461 10:02:05.723404 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1462 10:02:05.726343 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1463 10:02:05.726914
1464 10:02:05.730021 CA PerBit enable=1, Macro0, CA PI delay=33
1465 10:02:05.730592
1466 10:02:05.732962 [CBTSetCACLKResult] CA Dly = 33
1467 10:02:05.736743 CS Dly: 4 (0~35)
1468 10:02:05.737343 ==
1469 10:02:05.739926 Dram Type= 6, Freq= 0, CH_1, rank 1
1470 10:02:05.743055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1471 10:02:05.743624 ==
1472 10:02:05.746426 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1473 10:02:05.752933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1474 10:02:05.763273 [CA 0] Center 37 (7~68) winsize 62
1475 10:02:05.766294 [CA 1] Center 37 (6~68) winsize 63
1476 10:02:05.770064 [CA 2] Center 35 (5~66) winsize 62
1477 10:02:05.772891 [CA 3] Center 34 (4~65) winsize 62
1478 10:02:05.776277 [CA 4] Center 34 (4~65) winsize 62
1479 10:02:05.779821 [CA 5] Center 34 (4~64) winsize 61
1480 10:02:05.780400
1481 10:02:05.783146 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1482 10:02:05.783616
1483 10:02:05.785744 [CATrainingPosCal] consider 2 rank data
1484 10:02:05.789450 u2DelayCellTimex100 = 270/100 ps
1485 10:02:05.792602 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1486 10:02:05.795795 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1487 10:02:05.802370 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1488 10:02:05.805827 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1489 10:02:05.809754 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1490 10:02:05.813469 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1491 10:02:05.813937
1492 10:02:05.817505 CA PerBit enable=1, Macro0, CA PI delay=34
1493 10:02:05.818000
1494 10:02:05.821108 [CBTSetCACLKResult] CA Dly = 34
1495 10:02:05.821528 CS Dly: 5 (0~37)
1496 10:02:05.821855
1497 10:02:05.825275 ----->DramcWriteLeveling(PI) begin...
1498 10:02:05.825701 ==
1499 10:02:05.828744 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 10:02:05.832231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1501 10:02:05.832929 ==
1502 10:02:05.835690 Write leveling (Byte 0): 25 => 25
1503 10:02:05.839320 Write leveling (Byte 1): 31 => 31
1504 10:02:05.842864 DramcWriteLeveling(PI) end<-----
1505 10:02:05.843445
1506 10:02:05.843813 ==
1507 10:02:05.846284 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 10:02:05.849638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 10:02:05.850180 ==
1510 10:02:05.853601 [Gating] SW mode calibration
1511 10:02:05.859135 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1512 10:02:05.862619 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1513 10:02:05.869820 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1514 10:02:05.875646 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1515 10:02:05.876132 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 10:02:05.883043 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 10:02:05.885997 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 10:02:05.888814 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 10:02:05.895658 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 10:02:05.899072 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 10:02:05.902605 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 10:02:05.909260 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 10:02:05.912240 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 10:02:05.915866 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 10:02:05.922614 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 10:02:05.926109 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 10:02:05.929316 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 10:02:05.935809 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 10:02:05.939048 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1530 10:02:05.942411 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1531 10:02:05.948991 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1532 10:02:05.952245 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 10:02:05.955549 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 10:02:05.962398 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 10:02:05.965238 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 10:02:05.968889 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 10:02:05.975503 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 10:02:05.978869 0 9 4 | B1->B0 | 2323 2828 | 1 0 | (1 1) (1 1)
1539 10:02:05.981893 0 9 8 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
1540 10:02:05.988853 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 10:02:05.991839 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 10:02:05.994970 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 10:02:06.001624 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 10:02:06.005391 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 10:02:06.008353 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1546 10:02:06.015243 0 10 4 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (1 1)
1547 10:02:06.018450 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1548 10:02:06.021509 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 10:02:06.028576 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 10:02:06.031772 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 10:02:06.035398 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 10:02:06.038187 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 10:02:06.045115 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 10:02:06.048826 0 11 4 | B1->B0 | 2d2d 3535 | 0 1 | (0 0) (0 0)
1555 10:02:06.052290 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1556 10:02:06.058188 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 10:02:06.061945 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 10:02:06.065764 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 10:02:06.071893 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 10:02:06.075308 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 10:02:06.078679 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 10:02:06.085102 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1563 10:02:06.088264 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 10:02:06.091630 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 10:02:06.098087 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 10:02:06.101385 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 10:02:06.105028 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 10:02:06.111564 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 10:02:06.114444 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 10:02:06.117922 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 10:02:06.124602 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 10:02:06.128114 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 10:02:06.131544 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 10:02:06.138158 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 10:02:06.141522 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 10:02:06.145315 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 10:02:06.151914 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 10:02:06.154696 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1579 10:02:06.157914 Total UI for P1: 0, mck2ui 16
1580 10:02:06.161316 best dqsien dly found for B0: ( 0, 14, 2)
1581 10:02:06.164538 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 10:02:06.167900 Total UI for P1: 0, mck2ui 16
1583 10:02:06.170996 best dqsien dly found for B1: ( 0, 14, 4)
1584 10:02:06.174865 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1585 10:02:06.178070 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1586 10:02:06.178649
1587 10:02:06.181511 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1588 10:02:06.184733 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1589 10:02:06.187636 [Gating] SW calibration Done
1590 10:02:06.188104 ==
1591 10:02:06.190987 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 10:02:06.197899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 10:02:06.198491 ==
1594 10:02:06.198864 RX Vref Scan: 0
1595 10:02:06.199211
1596 10:02:06.201196 RX Vref 0 -> 0, step: 1
1597 10:02:06.201663
1598 10:02:06.204194 RX Delay -130 -> 252, step: 16
1599 10:02:06.207576 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1600 10:02:06.211271 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1601 10:02:06.214477 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1602 10:02:06.220946 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1603 10:02:06.224098 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1604 10:02:06.227531 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1605 10:02:06.230909 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1606 10:02:06.233957 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1607 10:02:06.238289 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1608 10:02:06.244523 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1609 10:02:06.247850 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1610 10:02:06.251250 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1611 10:02:06.254073 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1612 10:02:06.260867 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1613 10:02:06.264217 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1614 10:02:06.267112 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1615 10:02:06.267619 ==
1616 10:02:06.270892 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 10:02:06.274160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 10:02:06.274694 ==
1619 10:02:06.277499 DQS Delay:
1620 10:02:06.278026 DQS0 = 0, DQS1 = 0
1621 10:02:06.280906 DQM Delay:
1622 10:02:06.281445 DQM0 = 93, DQM1 = 87
1623 10:02:06.281826 DQ Delay:
1624 10:02:06.283977 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1625 10:02:06.287753 DQ4 =85, DQ5 =101, DQ6 =109, DQ7 =93
1626 10:02:06.290787 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1627 10:02:06.293725 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1628 10:02:06.294318
1629 10:02:06.297031
1630 10:02:06.297468 ==
1631 10:02:06.300662 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 10:02:06.304152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 10:02:06.304577 ==
1634 10:02:06.304940
1635 10:02:06.305253
1636 10:02:06.307058 TX Vref Scan disable
1637 10:02:06.307481 == TX Byte 0 ==
1638 10:02:06.313960 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1639 10:02:06.316998 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1640 10:02:06.317427 == TX Byte 1 ==
1641 10:02:06.323961 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1642 10:02:06.327104 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1643 10:02:06.327627 ==
1644 10:02:06.330449 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 10:02:06.333745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 10:02:06.334319 ==
1647 10:02:06.347863 TX Vref=22, minBit 8, minWin=27, winSum=446
1648 10:02:06.351249 TX Vref=24, minBit 8, minWin=27, winSum=449
1649 10:02:06.354665 TX Vref=26, minBit 8, minWin=27, winSum=451
1650 10:02:06.358026 TX Vref=28, minBit 15, minWin=27, winSum=454
1651 10:02:06.361330 TX Vref=30, minBit 8, minWin=27, winSum=457
1652 10:02:06.368307 TX Vref=32, minBit 8, minWin=27, winSum=454
1653 10:02:06.370949 [TxChooseVref] Worse bit 8, Min win 27, Win sum 457, Final Vref 30
1654 10:02:06.371506
1655 10:02:06.374398 Final TX Range 1 Vref 30
1656 10:02:06.374925
1657 10:02:06.375258 ==
1658 10:02:06.377932 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 10:02:06.381014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1660 10:02:06.384310 ==
1661 10:02:06.384870
1662 10:02:06.385208
1663 10:02:06.385513 TX Vref Scan disable
1664 10:02:06.388480 == TX Byte 0 ==
1665 10:02:06.391526 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1666 10:02:06.394565 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1667 10:02:06.398011 == TX Byte 1 ==
1668 10:02:06.401639 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1669 10:02:06.404928 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1670 10:02:06.408102
1671 10:02:06.408626 [DATLAT]
1672 10:02:06.409003 Freq=800, CH1 RK0
1673 10:02:06.409319
1674 10:02:06.411419 DATLAT Default: 0xa
1675 10:02:06.411953 0, 0xFFFF, sum = 0
1676 10:02:06.414682 1, 0xFFFF, sum = 0
1677 10:02:06.415115 2, 0xFFFF, sum = 0
1678 10:02:06.418259 3, 0xFFFF, sum = 0
1679 10:02:06.418800 4, 0xFFFF, sum = 0
1680 10:02:06.421021 5, 0xFFFF, sum = 0
1681 10:02:06.425037 6, 0xFFFF, sum = 0
1682 10:02:06.425573 7, 0xFFFF, sum = 0
1683 10:02:06.427730 8, 0xFFFF, sum = 0
1684 10:02:06.428264 9, 0x0, sum = 1
1685 10:02:06.431182 10, 0x0, sum = 2
1686 10:02:06.431614 11, 0x0, sum = 3
1687 10:02:06.431950 12, 0x0, sum = 4
1688 10:02:06.434211 best_step = 10
1689 10:02:06.434647
1690 10:02:06.434982 ==
1691 10:02:06.437961 Dram Type= 6, Freq= 0, CH_1, rank 0
1692 10:02:06.441223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1693 10:02:06.441649 ==
1694 10:02:06.444334 RX Vref Scan: 1
1695 10:02:06.444759
1696 10:02:06.447536 Set Vref Range= 32 -> 127
1697 10:02:06.448068
1698 10:02:06.448470 RX Vref 32 -> 127, step: 1
1699 10:02:06.448855
1700 10:02:06.450775 RX Delay -79 -> 252, step: 8
1701 10:02:06.451287
1702 10:02:06.454522 Set Vref, RX VrefLevel [Byte0]: 32
1703 10:02:06.457564 [Byte1]: 32
1704 10:02:06.458097
1705 10:02:06.461357 Set Vref, RX VrefLevel [Byte0]: 33
1706 10:02:06.464250 [Byte1]: 33
1707 10:02:06.468754
1708 10:02:06.469320 Set Vref, RX VrefLevel [Byte0]: 34
1709 10:02:06.471906 [Byte1]: 34
1710 10:02:06.475759
1711 10:02:06.476335 Set Vref, RX VrefLevel [Byte0]: 35
1712 10:02:06.479193 [Byte1]: 35
1713 10:02:06.483277
1714 10:02:06.483838 Set Vref, RX VrefLevel [Byte0]: 36
1715 10:02:06.486931 [Byte1]: 36
1716 10:02:06.490893
1717 10:02:06.491315 Set Vref, RX VrefLevel [Byte0]: 37
1718 10:02:06.496991 [Byte1]: 37
1719 10:02:06.497511
1720 10:02:06.500553 Set Vref, RX VrefLevel [Byte0]: 38
1721 10:02:06.504114 [Byte1]: 38
1722 10:02:06.504642
1723 10:02:06.507731 Set Vref, RX VrefLevel [Byte0]: 39
1724 10:02:06.510963 [Byte1]: 39
1725 10:02:06.511495
1726 10:02:06.514029 Set Vref, RX VrefLevel [Byte0]: 40
1727 10:02:06.517158 [Byte1]: 40
1728 10:02:06.521440
1729 10:02:06.521969 Set Vref, RX VrefLevel [Byte0]: 41
1730 10:02:06.524933 [Byte1]: 41
1731 10:02:06.528944
1732 10:02:06.529466 Set Vref, RX VrefLevel [Byte0]: 42
1733 10:02:06.532204 [Byte1]: 42
1734 10:02:06.535967
1735 10:02:06.536497 Set Vref, RX VrefLevel [Byte0]: 43
1736 10:02:06.539451 [Byte1]: 43
1737 10:02:06.543860
1738 10:02:06.544432 Set Vref, RX VrefLevel [Byte0]: 44
1739 10:02:06.547348 [Byte1]: 44
1740 10:02:06.551197
1741 10:02:06.551782 Set Vref, RX VrefLevel [Byte0]: 45
1742 10:02:06.554456 [Byte1]: 45
1743 10:02:06.558848
1744 10:02:06.559389 Set Vref, RX VrefLevel [Byte0]: 46
1745 10:02:06.561968 [Byte1]: 46
1746 10:02:06.566183
1747 10:02:06.566744 Set Vref, RX VrefLevel [Byte0]: 47
1748 10:02:06.570122 [Byte1]: 47
1749 10:02:06.574472
1750 10:02:06.575041 Set Vref, RX VrefLevel [Byte0]: 48
1751 10:02:06.577443 [Byte1]: 48
1752 10:02:06.581678
1753 10:02:06.582246 Set Vref, RX VrefLevel [Byte0]: 49
1754 10:02:06.584977 [Byte1]: 49
1755 10:02:06.589172
1756 10:02:06.589830 Set Vref, RX VrefLevel [Byte0]: 50
1757 10:02:06.592229 [Byte1]: 50
1758 10:02:06.596564
1759 10:02:06.597182 Set Vref, RX VrefLevel [Byte0]: 51
1760 10:02:06.600611 [Byte1]: 51
1761 10:02:06.604172
1762 10:02:06.604738 Set Vref, RX VrefLevel [Byte0]: 52
1763 10:02:06.607567 [Byte1]: 52
1764 10:02:06.611617
1765 10:02:06.612187 Set Vref, RX VrefLevel [Byte0]: 53
1766 10:02:06.614954 [Byte1]: 53
1767 10:02:06.619290
1768 10:02:06.619859 Set Vref, RX VrefLevel [Byte0]: 54
1769 10:02:06.622538 [Byte1]: 54
1770 10:02:06.627128
1771 10:02:06.627698 Set Vref, RX VrefLevel [Byte0]: 55
1772 10:02:06.630167 [Byte1]: 55
1773 10:02:06.634212
1774 10:02:06.634783 Set Vref, RX VrefLevel [Byte0]: 56
1775 10:02:06.637317 [Byte1]: 56
1776 10:02:06.642014
1777 10:02:06.642583 Set Vref, RX VrefLevel [Byte0]: 57
1778 10:02:06.644970 [Byte1]: 57
1779 10:02:06.649360
1780 10:02:06.649893 Set Vref, RX VrefLevel [Byte0]: 58
1781 10:02:06.652694 [Byte1]: 58
1782 10:02:06.656715
1783 10:02:06.657209 Set Vref, RX VrefLevel [Byte0]: 59
1784 10:02:06.660150 [Byte1]: 59
1785 10:02:06.664687
1786 10:02:06.665290 Set Vref, RX VrefLevel [Byte0]: 60
1787 10:02:06.667569 [Byte1]: 60
1788 10:02:06.672004
1789 10:02:06.672574 Set Vref, RX VrefLevel [Byte0]: 61
1790 10:02:06.675521 [Byte1]: 61
1791 10:02:06.679962
1792 10:02:06.680525 Set Vref, RX VrefLevel [Byte0]: 62
1793 10:02:06.682973 [Byte1]: 62
1794 10:02:06.686956
1795 10:02:06.687864 Set Vref, RX VrefLevel [Byte0]: 63
1796 10:02:06.690132 [Byte1]: 63
1797 10:02:06.694986
1798 10:02:06.695732 Set Vref, RX VrefLevel [Byte0]: 64
1799 10:02:06.697878 [Byte1]: 64
1800 10:02:06.702388
1801 10:02:06.703056 Set Vref, RX VrefLevel [Byte0]: 65
1802 10:02:06.705028 [Byte1]: 65
1803 10:02:06.709435
1804 10:02:06.709920 Set Vref, RX VrefLevel [Byte0]: 66
1805 10:02:06.712240 [Byte1]: 66
1806 10:02:06.716604
1807 10:02:06.716908 Set Vref, RX VrefLevel [Byte0]: 67
1808 10:02:06.720161 [Byte1]: 67
1809 10:02:06.724196
1810 10:02:06.724448 Set Vref, RX VrefLevel [Byte0]: 68
1811 10:02:06.727338 [Byte1]: 68
1812 10:02:06.731590
1813 10:02:06.731728 Set Vref, RX VrefLevel [Byte0]: 69
1814 10:02:06.735127 [Byte1]: 69
1815 10:02:06.739393
1816 10:02:06.739556 Set Vref, RX VrefLevel [Byte0]: 70
1817 10:02:06.742779 [Byte1]: 70
1818 10:02:06.747101
1819 10:02:06.747282 Set Vref, RX VrefLevel [Byte0]: 71
1820 10:02:06.750094 [Byte1]: 71
1821 10:02:06.754568
1822 10:02:06.754696 Set Vref, RX VrefLevel [Byte0]: 72
1823 10:02:06.757624 [Byte1]: 72
1824 10:02:06.762354
1825 10:02:06.762893 Set Vref, RX VrefLevel [Byte0]: 73
1826 10:02:06.765743 [Byte1]: 73
1827 10:02:06.769639
1828 10:02:06.770148 Set Vref, RX VrefLevel [Byte0]: 74
1829 10:02:06.773228 [Byte1]: 74
1830 10:02:06.777208
1831 10:02:06.777687 Set Vref, RX VrefLevel [Byte0]: 75
1832 10:02:06.780842 [Byte1]: 75
1833 10:02:06.785041
1834 10:02:06.785667 Final RX Vref Byte 0 = 51 to rank0
1835 10:02:06.788558 Final RX Vref Byte 1 = 61 to rank0
1836 10:02:06.791420 Final RX Vref Byte 0 = 51 to rank1
1837 10:02:06.794890 Final RX Vref Byte 1 = 61 to rank1==
1838 10:02:06.798367 Dram Type= 6, Freq= 0, CH_1, rank 0
1839 10:02:06.805125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 10:02:06.805661 ==
1841 10:02:06.805998 DQS Delay:
1842 10:02:06.808424 DQS0 = 0, DQS1 = 0
1843 10:02:06.808982 DQM Delay:
1844 10:02:06.809323 DQM0 = 92, DQM1 = 83
1845 10:02:06.812035 DQ Delay:
1846 10:02:06.814937 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
1847 10:02:06.818004 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1848 10:02:06.821454 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1849 10:02:06.825113 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1850 10:02:06.825642
1851 10:02:06.825974
1852 10:02:06.832167 [DQSOSCAuto] RK0, (LSB)MR18= 0x3351, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1853 10:02:06.834816 CH1 RK0: MR19=606, MR18=3351
1854 10:02:06.841353 CH1_RK0: MR19=0x606, MR18=0x3351, DQSOSC=389, MR23=63, INC=97, DEC=65
1855 10:02:06.841877
1856 10:02:06.844352 ----->DramcWriteLeveling(PI) begin...
1857 10:02:06.844803 ==
1858 10:02:06.848084 Dram Type= 6, Freq= 0, CH_1, rank 1
1859 10:02:06.851337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1860 10:02:06.851865 ==
1861 10:02:06.854804 Write leveling (Byte 0): 27 => 27
1862 10:02:06.858041 Write leveling (Byte 1): 32 => 32
1863 10:02:06.861045 DramcWriteLeveling(PI) end<-----
1864 10:02:06.861467
1865 10:02:06.861798 ==
1866 10:02:06.864631 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 10:02:06.867743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 10:02:06.871549 ==
1869 10:02:06.872114 [Gating] SW mode calibration
1870 10:02:06.877696 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1871 10:02:06.884551 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1872 10:02:06.887709 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1873 10:02:06.894085 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1874 10:02:06.897326 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 10:02:06.901250 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 10:02:06.908097 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 10:02:06.911314 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 10:02:06.914235 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 10:02:06.921011 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 10:02:06.924051 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 10:02:06.927150 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 10:02:06.934480 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 10:02:06.937025 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 10:02:06.940702 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 10:02:06.947444 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 10:02:06.951181 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 10:02:06.954363 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 10:02:06.960846 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1889 10:02:06.964005 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1890 10:02:06.967283 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 10:02:06.974121 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 10:02:06.977133 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 10:02:06.980309 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 10:02:06.983869 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 10:02:06.990173 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 10:02:06.993551 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 10:02:06.997089 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1898 10:02:07.003503 0 9 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1899 10:02:07.006655 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 10:02:07.010196 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 10:02:07.017128 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 10:02:07.020306 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 10:02:07.023694 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 10:02:07.030193 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 10:02:07.033356 0 10 4 | B1->B0 | 2f2f 3030 | 0 1 | (0 0) (0 0)
1906 10:02:07.036882 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 10:02:07.043282 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 10:02:07.046765 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 10:02:07.049998 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 10:02:07.056178 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 10:02:07.059828 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 10:02:07.063101 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 10:02:07.069684 0 11 4 | B1->B0 | 3131 2b2b | 1 0 | (0 0) (0 0)
1914 10:02:07.073138 0 11 8 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
1915 10:02:07.076342 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 10:02:07.083040 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 10:02:07.086284 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 10:02:07.089245 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 10:02:07.096503 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 10:02:07.099265 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 10:02:07.102680 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1922 10:02:07.109436 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 10:02:07.112833 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 10:02:07.116203 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 10:02:07.123038 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 10:02:07.125998 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 10:02:07.129623 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 10:02:07.136086 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 10:02:07.139526 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 10:02:07.143159 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 10:02:07.149166 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 10:02:07.152569 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 10:02:07.155637 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 10:02:07.162634 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 10:02:07.166367 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 10:02:07.169024 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 10:02:07.175935 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 10:02:07.176512 Total UI for P1: 0, mck2ui 16
1939 10:02:07.182461 best dqsien dly found for B0: ( 0, 14, 2)
1940 10:02:07.183036 Total UI for P1: 0, mck2ui 16
1941 10:02:07.185706 best dqsien dly found for B1: ( 0, 14, 2)
1942 10:02:07.191997 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1943 10:02:07.195371 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1944 10:02:07.195844
1945 10:02:07.199033 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1946 10:02:07.202393 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1947 10:02:07.205473 [Gating] SW calibration Done
1948 10:02:07.205939 ==
1949 10:02:07.209003 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 10:02:07.212071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 10:02:07.212546 ==
1952 10:02:07.212948 RX Vref Scan: 0
1953 10:02:07.215502
1954 10:02:07.215969 RX Vref 0 -> 0, step: 1
1955 10:02:07.216337
1956 10:02:07.218980 RX Delay -130 -> 252, step: 16
1957 10:02:07.222296 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1958 10:02:07.225231 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1959 10:02:07.232273 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1960 10:02:07.235555 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1961 10:02:07.238882 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1962 10:02:07.242194 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1963 10:02:07.245721 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1964 10:02:07.252136 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1965 10:02:07.255434 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1966 10:02:07.259112 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1967 10:02:07.262001 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1968 10:02:07.265610 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1969 10:02:07.272292 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1970 10:02:07.275931 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1971 10:02:07.278666 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1972 10:02:07.281981 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1973 10:02:07.282556 ==
1974 10:02:07.285392 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 10:02:07.292133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 10:02:07.292703 ==
1977 10:02:07.293108 DQS Delay:
1978 10:02:07.295824 DQS0 = 0, DQS1 = 0
1979 10:02:07.296406 DQM Delay:
1980 10:02:07.296814 DQM0 = 91, DQM1 = 84
1981 10:02:07.298253 DQ Delay:
1982 10:02:07.301556 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1983 10:02:07.305033 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1984 10:02:07.308614 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1985 10:02:07.311676 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1986 10:02:07.312142
1987 10:02:07.312505
1988 10:02:07.312878 ==
1989 10:02:07.314981 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 10:02:07.318712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 10:02:07.319184 ==
1992 10:02:07.319550
1993 10:02:07.319907
1994 10:02:07.321765 TX Vref Scan disable
1995 10:02:07.325078 == TX Byte 0 ==
1996 10:02:07.328920 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1997 10:02:07.332277 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1998 10:02:07.335366 == TX Byte 1 ==
1999 10:02:07.339167 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
2000 10:02:07.341783 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
2001 10:02:07.342259 ==
2002 10:02:07.344888 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 10:02:07.348672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 10:02:07.351952 ==
2005 10:02:07.363747 TX Vref=22, minBit 13, minWin=27, winSum=451
2006 10:02:07.366881 TX Vref=24, minBit 13, minWin=27, winSum=452
2007 10:02:07.370377 TX Vref=26, minBit 13, minWin=27, winSum=456
2008 10:02:07.372972 TX Vref=28, minBit 8, minWin=27, winSum=458
2009 10:02:07.376399 TX Vref=30, minBit 8, minWin=28, winSum=460
2010 10:02:07.382998 TX Vref=32, minBit 8, minWin=28, winSum=459
2011 10:02:07.386114 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
2012 10:02:07.386632
2013 10:02:07.389492 Final TX Range 1 Vref 30
2014 10:02:07.390075
2015 10:02:07.390519 ==
2016 10:02:07.393333 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 10:02:07.396092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 10:02:07.399619 ==
2019 10:02:07.399768
2020 10:02:07.399859
2021 10:02:07.399921 TX Vref Scan disable
2022 10:02:07.402626 == TX Byte 0 ==
2023 10:02:07.406262 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2024 10:02:07.412909 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2025 10:02:07.413048 == TX Byte 1 ==
2026 10:02:07.416024 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2027 10:02:07.422790 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2028 10:02:07.422895
2029 10:02:07.422962 [DATLAT]
2030 10:02:07.423025 Freq=800, CH1 RK1
2031 10:02:07.423084
2032 10:02:07.425893 DATLAT Default: 0xa
2033 10:02:07.425963 0, 0xFFFF, sum = 0
2034 10:02:07.429766 1, 0xFFFF, sum = 0
2035 10:02:07.432413 2, 0xFFFF, sum = 0
2036 10:02:07.432523 3, 0xFFFF, sum = 0
2037 10:02:07.435922 4, 0xFFFF, sum = 0
2038 10:02:07.436001 5, 0xFFFF, sum = 0
2039 10:02:07.439125 6, 0xFFFF, sum = 0
2040 10:02:07.439232 7, 0xFFFF, sum = 0
2041 10:02:07.442777 8, 0xFFFF, sum = 0
2042 10:02:07.442886 9, 0x0, sum = 1
2043 10:02:07.445628 10, 0x0, sum = 2
2044 10:02:07.445741 11, 0x0, sum = 3
2045 10:02:07.445841 12, 0x0, sum = 4
2046 10:02:07.449223 best_step = 10
2047 10:02:07.449314
2048 10:02:07.449418 ==
2049 10:02:07.452285 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 10:02:07.455630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 10:02:07.455745 ==
2052 10:02:07.458953 RX Vref Scan: 0
2053 10:02:07.459062
2054 10:02:07.462197 RX Vref 0 -> 0, step: 1
2055 10:02:07.462301
2056 10:02:07.462396 RX Delay -95 -> 252, step: 8
2057 10:02:07.469313 iDelay=209, Bit 0, Center 96 (1 ~ 192) 192
2058 10:02:07.472946 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2059 10:02:07.475988 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2060 10:02:07.479720 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2061 10:02:07.482893 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2062 10:02:07.489341 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2063 10:02:07.492508 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2064 10:02:07.495892 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2065 10:02:07.499421 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2066 10:02:07.502565 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2067 10:02:07.509313 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2068 10:02:07.512637 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2069 10:02:07.516410 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2070 10:02:07.519564 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2071 10:02:07.522722 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2072 10:02:07.529788 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2073 10:02:07.529958 ==
2074 10:02:07.532638 Dram Type= 6, Freq= 0, CH_1, rank 1
2075 10:02:07.535922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2076 10:02:07.536110 ==
2077 10:02:07.536281 DQS Delay:
2078 10:02:07.539491 DQS0 = 0, DQS1 = 0
2079 10:02:07.539696 DQM Delay:
2080 10:02:07.542593 DQM0 = 91, DQM1 = 85
2081 10:02:07.542787 DQ Delay:
2082 10:02:07.546191 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2083 10:02:07.549161 DQ4 =96, DQ5 =104, DQ6 =96, DQ7 =88
2084 10:02:07.552709 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2085 10:02:07.556355 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =96
2086 10:02:07.556624
2087 10:02:07.556891
2088 10:02:07.562840 [DQSOSCAuto] RK1, (LSB)MR18= 0x390e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2089 10:02:07.566009 CH1 RK1: MR19=606, MR18=390E
2090 10:02:07.572662 CH1_RK1: MR19=0x606, MR18=0x390E, DQSOSC=395, MR23=63, INC=94, DEC=63
2091 10:02:07.575851 [RxdqsGatingPostProcess] freq 800
2092 10:02:07.582792 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2093 10:02:07.585782 Pre-setting of DQS Precalculation
2094 10:02:07.589428 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2095 10:02:07.596229 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2096 10:02:07.602518 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2097 10:02:07.602937
2098 10:02:07.605851
2099 10:02:07.606234 [Calibration Summary] 1600 Mbps
2100 10:02:07.609363 CH 0, Rank 0
2101 10:02:07.609746 SW Impedance : PASS
2102 10:02:07.612251 DUTY Scan : NO K
2103 10:02:07.615845 ZQ Calibration : PASS
2104 10:02:07.615928 Jitter Meter : NO K
2105 10:02:07.618737 CBT Training : PASS
2106 10:02:07.622312 Write leveling : PASS
2107 10:02:07.622400 RX DQS gating : PASS
2108 10:02:07.625551 RX DQ/DQS(RDDQC) : PASS
2109 10:02:07.629220 TX DQ/DQS : PASS
2110 10:02:07.629299 RX DATLAT : PASS
2111 10:02:07.632020 RX DQ/DQS(Engine): PASS
2112 10:02:07.635556 TX OE : NO K
2113 10:02:07.635637 All Pass.
2114 10:02:07.635702
2115 10:02:07.635761 CH 0, Rank 1
2116 10:02:07.638891 SW Impedance : PASS
2117 10:02:07.642042 DUTY Scan : NO K
2118 10:02:07.642126 ZQ Calibration : PASS
2119 10:02:07.645416 Jitter Meter : NO K
2120 10:02:07.648841 CBT Training : PASS
2121 10:02:07.648925 Write leveling : PASS
2122 10:02:07.652146 RX DQS gating : PASS
2123 10:02:07.652230 RX DQ/DQS(RDDQC) : PASS
2124 10:02:07.655316 TX DQ/DQS : PASS
2125 10:02:07.658743 RX DATLAT : PASS
2126 10:02:07.658826 RX DQ/DQS(Engine): PASS
2127 10:02:07.662180 TX OE : NO K
2128 10:02:07.662264 All Pass.
2129 10:02:07.662330
2130 10:02:07.665075 CH 1, Rank 0
2131 10:02:07.665159 SW Impedance : PASS
2132 10:02:07.668546 DUTY Scan : NO K
2133 10:02:07.671899 ZQ Calibration : PASS
2134 10:02:07.671983 Jitter Meter : NO K
2135 10:02:07.675207 CBT Training : PASS
2136 10:02:07.679203 Write leveling : PASS
2137 10:02:07.679287 RX DQS gating : PASS
2138 10:02:07.681887 RX DQ/DQS(RDDQC) : PASS
2139 10:02:07.685300 TX DQ/DQS : PASS
2140 10:02:07.685384 RX DATLAT : PASS
2141 10:02:07.688633 RX DQ/DQS(Engine): PASS
2142 10:02:07.692021 TX OE : NO K
2143 10:02:07.692105 All Pass.
2144 10:02:07.692171
2145 10:02:07.692231 CH 1, Rank 1
2146 10:02:07.695468 SW Impedance : PASS
2147 10:02:07.698464 DUTY Scan : NO K
2148 10:02:07.698548 ZQ Calibration : PASS
2149 10:02:07.702049 Jitter Meter : NO K
2150 10:02:07.702132 CBT Training : PASS
2151 10:02:07.705479 Write leveling : PASS
2152 10:02:07.709301 RX DQS gating : PASS
2153 10:02:07.709384 RX DQ/DQS(RDDQC) : PASS
2154 10:02:07.712032 TX DQ/DQS : PASS
2155 10:02:07.715290 RX DATLAT : PASS
2156 10:02:07.715373 RX DQ/DQS(Engine): PASS
2157 10:02:07.718425 TX OE : NO K
2158 10:02:07.718509 All Pass.
2159 10:02:07.718591
2160 10:02:07.721687 DramC Write-DBI off
2161 10:02:07.724894 PER_BANK_REFRESH: Hybrid Mode
2162 10:02:07.724978 TX_TRACKING: ON
2163 10:02:07.728461 [GetDramInforAfterCalByMRR] Vendor 6.
2164 10:02:07.731484 [GetDramInforAfterCalByMRR] Revision 606.
2165 10:02:07.734964 [GetDramInforAfterCalByMRR] Revision 2 0.
2166 10:02:07.738469 MR0 0x3b3b
2167 10:02:07.738558 MR8 0x5151
2168 10:02:07.741604 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2169 10:02:07.741695
2170 10:02:07.745408 MR0 0x3b3b
2171 10:02:07.745491 MR8 0x5151
2172 10:02:07.748100 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 10:02:07.748173
2174 10:02:07.758011 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2175 10:02:07.761572 [FAST_K] Save calibration result to emmc
2176 10:02:07.765040 [FAST_K] Save calibration result to emmc
2177 10:02:07.768256 dram_init: config_dvfs: 1
2178 10:02:07.771456 dramc_set_vcore_voltage set vcore to 662500
2179 10:02:07.771539 Read voltage for 1200, 2
2180 10:02:07.774825 Vio18 = 0
2181 10:02:07.774908 Vcore = 662500
2182 10:02:07.774973 Vdram = 0
2183 10:02:07.778606 Vddq = 0
2184 10:02:07.778689 Vmddr = 0
2185 10:02:07.781864 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2186 10:02:07.788049 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2187 10:02:07.791672 MEM_TYPE=3, freq_sel=15
2188 10:02:07.794567 sv_algorithm_assistance_LP4_1600
2189 10:02:07.798431 ============ PULL DRAM RESETB DOWN ============
2190 10:02:07.801708 ========== PULL DRAM RESETB DOWN end =========
2191 10:02:07.808346 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2192 10:02:07.811616 ===================================
2193 10:02:07.811700 LPDDR4 DRAM CONFIGURATION
2194 10:02:07.815129 ===================================
2195 10:02:07.817933 EX_ROW_EN[0] = 0x0
2196 10:02:07.818072 EX_ROW_EN[1] = 0x0
2197 10:02:07.821479 LP4Y_EN = 0x0
2198 10:02:07.821575 WORK_FSP = 0x0
2199 10:02:07.824846 WL = 0x4
2200 10:02:07.824965 RL = 0x4
2201 10:02:07.828293 BL = 0x2
2202 10:02:07.828427 RPST = 0x0
2203 10:02:07.831213 RD_PRE = 0x0
2204 10:02:07.835127 WR_PRE = 0x1
2205 10:02:07.835313 WR_PST = 0x0
2206 10:02:07.838198 DBI_WR = 0x0
2207 10:02:07.838346 DBI_RD = 0x0
2208 10:02:07.841280 OTF = 0x1
2209 10:02:07.844623 ===================================
2210 10:02:07.847785 ===================================
2211 10:02:07.847965 ANA top config
2212 10:02:07.851237 ===================================
2213 10:02:07.854574 DLL_ASYNC_EN = 0
2214 10:02:07.857691 ALL_SLAVE_EN = 0
2215 10:02:07.857827 NEW_RANK_MODE = 1
2216 10:02:07.861147 DLL_IDLE_MODE = 1
2217 10:02:07.864664 LP45_APHY_COMB_EN = 1
2218 10:02:07.867704 TX_ODT_DIS = 1
2219 10:02:07.867849 NEW_8X_MODE = 1
2220 10:02:07.871121 ===================================
2221 10:02:07.874618 ===================================
2222 10:02:07.877922 data_rate = 2400
2223 10:02:07.880966 CKR = 1
2224 10:02:07.884575 DQ_P2S_RATIO = 8
2225 10:02:07.887631 ===================================
2226 10:02:07.891309 CA_P2S_RATIO = 8
2227 10:02:07.894681 DQ_CA_OPEN = 0
2228 10:02:07.894808 DQ_SEMI_OPEN = 0
2229 10:02:07.897673 CA_SEMI_OPEN = 0
2230 10:02:07.901121 CA_FULL_RATE = 0
2231 10:02:07.904373 DQ_CKDIV4_EN = 0
2232 10:02:07.907555 CA_CKDIV4_EN = 0
2233 10:02:07.911067 CA_PREDIV_EN = 0
2234 10:02:07.911205 PH8_DLY = 17
2235 10:02:07.914145 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2236 10:02:07.917631 DQ_AAMCK_DIV = 4
2237 10:02:07.920814 CA_AAMCK_DIV = 4
2238 10:02:07.923994 CA_ADMCK_DIV = 4
2239 10:02:07.927439 DQ_TRACK_CA_EN = 0
2240 10:02:07.930676 CA_PICK = 1200
2241 10:02:07.930844 CA_MCKIO = 1200
2242 10:02:07.934146 MCKIO_SEMI = 0
2243 10:02:07.937394 PLL_FREQ = 2366
2244 10:02:07.940918 DQ_UI_PI_RATIO = 32
2245 10:02:07.944184 CA_UI_PI_RATIO = 0
2246 10:02:07.947552 ===================================
2247 10:02:07.951050 ===================================
2248 10:02:07.954410 memory_type:LPDDR4
2249 10:02:07.954546 GP_NUM : 10
2250 10:02:07.957288 SRAM_EN : 1
2251 10:02:07.957432 MD32_EN : 0
2252 10:02:07.961167 ===================================
2253 10:02:07.964137 [ANA_INIT] >>>>>>>>>>>>>>
2254 10:02:07.967745 <<<<<< [CONFIGURE PHASE]: ANA_TX
2255 10:02:07.970801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2256 10:02:07.974462 ===================================
2257 10:02:07.977577 data_rate = 2400,PCW = 0X5b00
2258 10:02:07.981318 ===================================
2259 10:02:07.984148 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2260 10:02:07.990927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2261 10:02:07.994026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 10:02:08.000616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2263 10:02:08.003761 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2264 10:02:08.007160 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2265 10:02:08.007235 [ANA_INIT] flow start
2266 10:02:08.010565 [ANA_INIT] PLL >>>>>>>>
2267 10:02:08.013680 [ANA_INIT] PLL <<<<<<<<
2268 10:02:08.013776 [ANA_INIT] MIDPI >>>>>>>>
2269 10:02:08.017149 [ANA_INIT] MIDPI <<<<<<<<
2270 10:02:08.020411 [ANA_INIT] DLL >>>>>>>>
2271 10:02:08.020516 [ANA_INIT] DLL <<<<<<<<
2272 10:02:08.023708 [ANA_INIT] flow end
2273 10:02:08.026970 ============ LP4 DIFF to SE enter ============
2274 10:02:08.030499 ============ LP4 DIFF to SE exit ============
2275 10:02:08.033713 [ANA_INIT] <<<<<<<<<<<<<
2276 10:02:08.036732 [Flow] Enable top DCM control >>>>>
2277 10:02:08.040155 [Flow] Enable top DCM control <<<<<
2278 10:02:08.043687 Enable DLL master slave shuffle
2279 10:02:08.050136 ==============================================================
2280 10:02:08.050233 Gating Mode config
2281 10:02:08.056624 ==============================================================
2282 10:02:08.060249 Config description:
2283 10:02:08.067600 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2284 10:02:08.073191 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2285 10:02:08.079854 SELPH_MODE 0: By rank 1: By Phase
2286 10:02:08.086413 ==============================================================
2287 10:02:08.086497 GAT_TRACK_EN = 1
2288 10:02:08.090534 RX_GATING_MODE = 2
2289 10:02:08.093085 RX_GATING_TRACK_MODE = 2
2290 10:02:08.096740 SELPH_MODE = 1
2291 10:02:08.100158 PICG_EARLY_EN = 1
2292 10:02:08.103298 VALID_LAT_VALUE = 1
2293 10:02:08.110289 ==============================================================
2294 10:02:08.113404 Enter into Gating configuration >>>>
2295 10:02:08.116484 Exit from Gating configuration <<<<
2296 10:02:08.120456 Enter into DVFS_PRE_config >>>>>
2297 10:02:08.129871 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2298 10:02:08.133088 Exit from DVFS_PRE_config <<<<<
2299 10:02:08.136441 Enter into PICG configuration >>>>
2300 10:02:08.140078 Exit from PICG configuration <<<<
2301 10:02:08.143336 [RX_INPUT] configuration >>>>>
2302 10:02:08.143449 [RX_INPUT] configuration <<<<<
2303 10:02:08.149722 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2304 10:02:08.156226 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2305 10:02:08.162946 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2306 10:02:08.166777 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2307 10:02:08.172749 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2308 10:02:08.179660 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2309 10:02:08.182899 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2310 10:02:08.186189 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2311 10:02:08.192780 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2312 10:02:08.196043 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2313 10:02:08.199680 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2314 10:02:08.206054 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2315 10:02:08.209547 ===================================
2316 10:02:08.209630 LPDDR4 DRAM CONFIGURATION
2317 10:02:08.212573 ===================================
2318 10:02:08.215871 EX_ROW_EN[0] = 0x0
2319 10:02:08.219216 EX_ROW_EN[1] = 0x0
2320 10:02:08.219314 LP4Y_EN = 0x0
2321 10:02:08.222704 WORK_FSP = 0x0
2322 10:02:08.222787 WL = 0x4
2323 10:02:08.226231 RL = 0x4
2324 10:02:08.226320 BL = 0x2
2325 10:02:08.229232 RPST = 0x0
2326 10:02:08.229327 RD_PRE = 0x0
2327 10:02:08.232512 WR_PRE = 0x1
2328 10:02:08.232607 WR_PST = 0x0
2329 10:02:08.236090 DBI_WR = 0x0
2330 10:02:08.236173 DBI_RD = 0x0
2331 10:02:08.239744 OTF = 0x1
2332 10:02:08.242551 ===================================
2333 10:02:08.245854 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2334 10:02:08.249141 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2335 10:02:08.256028 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2336 10:02:08.256140 ===================================
2337 10:02:08.259782 LPDDR4 DRAM CONFIGURATION
2338 10:02:08.262511 ===================================
2339 10:02:08.265761 EX_ROW_EN[0] = 0x10
2340 10:02:08.265898 EX_ROW_EN[1] = 0x0
2341 10:02:08.269096 LP4Y_EN = 0x0
2342 10:02:08.269299 WORK_FSP = 0x0
2343 10:02:08.272794 WL = 0x4
2344 10:02:08.272973 RL = 0x4
2345 10:02:08.275841 BL = 0x2
2346 10:02:08.279408 RPST = 0x0
2347 10:02:08.279596 RD_PRE = 0x0
2348 10:02:08.282686 WR_PRE = 0x1
2349 10:02:08.282860 WR_PST = 0x0
2350 10:02:08.286245 DBI_WR = 0x0
2351 10:02:08.286419 DBI_RD = 0x0
2352 10:02:08.289225 OTF = 0x1
2353 10:02:08.292298 ===================================
2354 10:02:08.296028 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2355 10:02:08.299463 ==
2356 10:02:08.302668 Dram Type= 6, Freq= 0, CH_0, rank 0
2357 10:02:08.305871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 10:02:08.306048 ==
2359 10:02:08.309426 [Duty_Offset_Calibration]
2360 10:02:08.309597 B0:2 B1:0 CA:1
2361 10:02:08.309732
2362 10:02:08.312619 [DutyScan_Calibration_Flow] k_type=0
2363 10:02:08.321519
2364 10:02:08.321693 ==CLK 0==
2365 10:02:08.324506 Final CLK duty delay cell = -4
2366 10:02:08.327806 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2367 10:02:08.330813 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2368 10:02:08.334373 [-4] AVG Duty = 4953%(X100)
2369 10:02:08.334454
2370 10:02:08.337532 CH0 CLK Duty spec in!! Max-Min= 156%
2371 10:02:08.340989 [DutyScan_Calibration_Flow] ====Done====
2372 10:02:08.341070
2373 10:02:08.344156 [DutyScan_Calibration_Flow] k_type=1
2374 10:02:08.359911
2375 10:02:08.359992 ==DQS 0 ==
2376 10:02:08.363155 Final DQS duty delay cell = 0
2377 10:02:08.366496 [0] MAX Duty = 5187%(X100), DQS PI = 30
2378 10:02:08.369957 [0] MIN Duty = 4938%(X100), DQS PI = 0
2379 10:02:08.370050 [0] AVG Duty = 5062%(X100)
2380 10:02:08.373299
2381 10:02:08.373373 ==DQS 1 ==
2382 10:02:08.376797 Final DQS duty delay cell = -4
2383 10:02:08.380198 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2384 10:02:08.383612 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2385 10:02:08.386619 [-4] AVG Duty = 5031%(X100)
2386 10:02:08.386691
2387 10:02:08.389855 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2388 10:02:08.389939
2389 10:02:08.393034 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2390 10:02:08.396413 [DutyScan_Calibration_Flow] ====Done====
2391 10:02:08.396511
2392 10:02:08.399775 [DutyScan_Calibration_Flow] k_type=3
2393 10:02:08.415913
2394 10:02:08.416020 ==DQM 0 ==
2395 10:02:08.419391 Final DQM duty delay cell = 0
2396 10:02:08.422455 [0] MAX Duty = 5062%(X100), DQS PI = 24
2397 10:02:08.425787 [0] MIN Duty = 4875%(X100), DQS PI = 0
2398 10:02:08.425868 [0] AVG Duty = 4968%(X100)
2399 10:02:08.429352
2400 10:02:08.429432 ==DQM 1 ==
2401 10:02:08.432747 Final DQM duty delay cell = -4
2402 10:02:08.435986 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2403 10:02:08.439216 [-4] MIN Duty = 4813%(X100), DQS PI = 12
2404 10:02:08.442563 [-4] AVG Duty = 4906%(X100)
2405 10:02:08.442644
2406 10:02:08.445685 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2407 10:02:08.445766
2408 10:02:08.449116 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2409 10:02:08.452254 [DutyScan_Calibration_Flow] ====Done====
2410 10:02:08.452334
2411 10:02:08.455529 [DutyScan_Calibration_Flow] k_type=2
2412 10:02:08.471919
2413 10:02:08.472019 ==DQ 0 ==
2414 10:02:08.475243 Final DQ duty delay cell = -4
2415 10:02:08.478720 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2416 10:02:08.482480 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2417 10:02:08.485670 [-4] AVG Duty = 4953%(X100)
2418 10:02:08.485750
2419 10:02:08.485813 ==DQ 1 ==
2420 10:02:08.488417 Final DQ duty delay cell = 0
2421 10:02:08.491795 [0] MAX Duty = 4938%(X100), DQS PI = 4
2422 10:02:08.495227 [0] MIN Duty = 4907%(X100), DQS PI = 0
2423 10:02:08.495308 [0] AVG Duty = 4922%(X100)
2424 10:02:08.498659
2425 10:02:08.501971 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2426 10:02:08.502052
2427 10:02:08.505158 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2428 10:02:08.508457 [DutyScan_Calibration_Flow] ====Done====
2429 10:02:08.508538 ==
2430 10:02:08.511821 Dram Type= 6, Freq= 0, CH_1, rank 0
2431 10:02:08.514922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2432 10:02:08.515004 ==
2433 10:02:08.518630 [Duty_Offset_Calibration]
2434 10:02:08.518711 B0:0 B1:-1 CA:2
2435 10:02:08.518775
2436 10:02:08.521995 [DutyScan_Calibration_Flow] k_type=0
2437 10:02:08.532431
2438 10:02:08.532881 ==CLK 0==
2439 10:02:08.535616 Final CLK duty delay cell = 0
2440 10:02:08.539094 [0] MAX Duty = 5156%(X100), DQS PI = 16
2441 10:02:08.542450 [0] MIN Duty = 4938%(X100), DQS PI = 44
2442 10:02:08.542868 [0] AVG Duty = 5047%(X100)
2443 10:02:08.545751
2444 10:02:08.549034 CH1 CLK Duty spec in!! Max-Min= 218%
2445 10:02:08.552075 [DutyScan_Calibration_Flow] ====Done====
2446 10:02:08.552500
2447 10:02:08.556082 [DutyScan_Calibration_Flow] k_type=1
2448 10:02:08.571371
2449 10:02:08.571452 ==DQS 0 ==
2450 10:02:08.574899 Final DQS duty delay cell = 0
2451 10:02:08.578402 [0] MAX Duty = 5093%(X100), DQS PI = 24
2452 10:02:08.582003 [0] MIN Duty = 4969%(X100), DQS PI = 0
2453 10:02:08.582087 [0] AVG Duty = 5031%(X100)
2454 10:02:08.584798
2455 10:02:08.584895 ==DQS 1 ==
2456 10:02:08.588167 Final DQS duty delay cell = 0
2457 10:02:08.591779 [0] MAX Duty = 5156%(X100), DQS PI = 0
2458 10:02:08.595434 [0] MIN Duty = 4875%(X100), DQS PI = 34
2459 10:02:08.595524 [0] AVG Duty = 5015%(X100)
2460 10:02:08.598366
2461 10:02:08.601541 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2462 10:02:08.601653
2463 10:02:08.605234 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2464 10:02:08.608573 [DutyScan_Calibration_Flow] ====Done====
2465 10:02:08.608662
2466 10:02:08.611622 [DutyScan_Calibration_Flow] k_type=3
2467 10:02:08.628312
2468 10:02:08.628435 ==DQM 0 ==
2469 10:02:08.631434 Final DQM duty delay cell = 4
2470 10:02:08.634907 [4] MAX Duty = 5093%(X100), DQS PI = 6
2471 10:02:08.638340 [4] MIN Duty = 4969%(X100), DQS PI = 28
2472 10:02:08.638495 [4] AVG Duty = 5031%(X100)
2473 10:02:08.641786
2474 10:02:08.641939 ==DQM 1 ==
2475 10:02:08.644910 Final DQM duty delay cell = -4
2476 10:02:08.648005 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2477 10:02:08.651525 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2478 10:02:08.654600 [-4] AVG Duty = 4875%(X100)
2479 10:02:08.654776
2480 10:02:08.658194 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2481 10:02:08.658373
2482 10:02:08.662227 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2483 10:02:08.665093 [DutyScan_Calibration_Flow] ====Done====
2484 10:02:08.665269
2485 10:02:08.668122 [DutyScan_Calibration_Flow] k_type=2
2486 10:02:08.685382
2487 10:02:08.685471 ==DQ 0 ==
2488 10:02:08.688500 Final DQ duty delay cell = 0
2489 10:02:08.691880 [0] MAX Duty = 5062%(X100), DQS PI = 16
2490 10:02:08.694845 [0] MIN Duty = 4938%(X100), DQS PI = 46
2491 10:02:08.694922 [0] AVG Duty = 5000%(X100)
2492 10:02:08.698549
2493 10:02:08.698653 ==DQ 1 ==
2494 10:02:08.701622 Final DQ duty delay cell = 0
2495 10:02:08.704948 [0] MAX Duty = 5031%(X100), DQS PI = 0
2496 10:02:08.708408 [0] MIN Duty = 4813%(X100), DQS PI = 36
2497 10:02:08.708506 [0] AVG Duty = 4922%(X100)
2498 10:02:08.708585
2499 10:02:08.711611 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2500 10:02:08.714775
2501 10:02:08.718338 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2502 10:02:08.721693 [DutyScan_Calibration_Flow] ====Done====
2503 10:02:08.724600 nWR fixed to 30
2504 10:02:08.724709 [ModeRegInit_LP4] CH0 RK0
2505 10:02:08.728053 [ModeRegInit_LP4] CH0 RK1
2506 10:02:08.731534 [ModeRegInit_LP4] CH1 RK0
2507 10:02:08.731650 [ModeRegInit_LP4] CH1 RK1
2508 10:02:08.734543 match AC timing 7
2509 10:02:08.738227 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2510 10:02:08.741554 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2511 10:02:08.748190 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2512 10:02:08.751728 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2513 10:02:08.758218 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2514 10:02:08.758341 ==
2515 10:02:08.761675 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 10:02:08.764636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 10:02:08.764778 ==
2518 10:02:08.771671 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 10:02:08.778390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2520 10:02:08.785147 [CA 0] Center 38 (8~69) winsize 62
2521 10:02:08.788841 [CA 1] Center 38 (7~69) winsize 63
2522 10:02:08.791983 [CA 2] Center 35 (5~66) winsize 62
2523 10:02:08.795161 [CA 3] Center 35 (4~66) winsize 63
2524 10:02:08.798532 [CA 4] Center 34 (4~65) winsize 62
2525 10:02:08.801711 [CA 5] Center 33 (3~63) winsize 61
2526 10:02:08.802176
2527 10:02:08.805276 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2528 10:02:08.805852
2529 10:02:08.808272 [CATrainingPosCal] consider 1 rank data
2530 10:02:08.811729 u2DelayCellTimex100 = 270/100 ps
2531 10:02:08.814993 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2532 10:02:08.821841 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2533 10:02:08.825277 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2534 10:02:08.828133 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2535 10:02:08.831800 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2536 10:02:08.835016 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2537 10:02:08.835439
2538 10:02:08.838371 CA PerBit enable=1, Macro0, CA PI delay=33
2539 10:02:08.838793
2540 10:02:08.841600 [CBTSetCACLKResult] CA Dly = 33
2541 10:02:08.842071 CS Dly: 6 (0~37)
2542 10:02:08.845043 ==
2543 10:02:08.848156 Dram Type= 6, Freq= 0, CH_0, rank 1
2544 10:02:08.851464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2545 10:02:08.851891 ==
2546 10:02:08.854790 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2547 10:02:08.861720 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2548 10:02:08.871285 [CA 0] Center 39 (8~70) winsize 63
2549 10:02:08.874181 [CA 1] Center 38 (8~69) winsize 62
2550 10:02:08.877305 [CA 2] Center 35 (5~66) winsize 62
2551 10:02:08.881076 [CA 3] Center 35 (5~66) winsize 62
2552 10:02:08.884058 [CA 4] Center 34 (4~65) winsize 62
2553 10:02:08.887417 [CA 5] Center 34 (4~64) winsize 61
2554 10:02:08.887891
2555 10:02:08.890667 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2556 10:02:08.891143
2557 10:02:08.894234 [CATrainingPosCal] consider 2 rank data
2558 10:02:08.897033 u2DelayCellTimex100 = 270/100 ps
2559 10:02:08.900746 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2560 10:02:08.907362 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2561 10:02:08.910606 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2562 10:02:08.913880 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2563 10:02:08.917088 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2564 10:02:08.919950 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2565 10:02:08.920058
2566 10:02:08.923764 CA PerBit enable=1, Macro0, CA PI delay=33
2567 10:02:08.923850
2568 10:02:08.927201 [CBTSetCACLKResult] CA Dly = 33
2569 10:02:08.927313 CS Dly: 7 (0~39)
2570 10:02:08.927407
2571 10:02:08.930395 ----->DramcWriteLeveling(PI) begin...
2572 10:02:08.933794 ==
2573 10:02:08.937048 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 10:02:08.940087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 10:02:08.940188 ==
2576 10:02:08.943497 Write leveling (Byte 0): 34 => 34
2577 10:02:08.947101 Write leveling (Byte 1): 31 => 31
2578 10:02:08.950553 DramcWriteLeveling(PI) end<-----
2579 10:02:08.950633
2580 10:02:08.950696 ==
2581 10:02:08.953635 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 10:02:08.956984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 10:02:08.957070 ==
2584 10:02:08.960232 [Gating] SW mode calibration
2585 10:02:08.966770 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2586 10:02:08.973692 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2587 10:02:08.976615 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2588 10:02:08.980109 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2589 10:02:08.986784 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 10:02:08.990250 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 10:02:08.993594 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 10:02:09.000467 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 10:02:09.003524 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2594 10:02:09.007116 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2595 10:02:09.013145 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
2596 10:02:09.016933 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 10:02:09.019754 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 10:02:09.026640 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 10:02:09.030430 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 10:02:09.033509 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 10:02:09.036611 1 0 24 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
2602 10:02:09.042743 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2603 10:02:09.046109 1 1 0 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
2604 10:02:09.049957 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 10:02:09.056397 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 10:02:09.059762 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 10:02:09.062981 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 10:02:09.069619 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 10:02:09.072854 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 10:02:09.076303 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2611 10:02:09.083232 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2612 10:02:09.086626 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 10:02:09.089440 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 10:02:09.096377 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 10:02:09.099298 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 10:02:09.102620 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 10:02:09.109535 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 10:02:09.112875 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 10:02:09.116513 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 10:02:09.122919 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 10:02:09.126477 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 10:02:09.129562 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 10:02:09.136421 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 10:02:09.139619 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 10:02:09.143031 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2626 10:02:09.149458 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2627 10:02:09.152883 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 10:02:09.156167 Total UI for P1: 0, mck2ui 16
2629 10:02:09.159339 best dqsien dly found for B0: ( 1, 3, 26)
2630 10:02:09.162610 Total UI for P1: 0, mck2ui 16
2631 10:02:09.165787 best dqsien dly found for B1: ( 1, 3, 30)
2632 10:02:09.169138 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2633 10:02:09.172672 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2634 10:02:09.172755
2635 10:02:09.175809 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2636 10:02:09.179230 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2637 10:02:09.182513 [Gating] SW calibration Done
2638 10:02:09.182676 ==
2639 10:02:09.185887 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 10:02:09.189364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 10:02:09.189533 ==
2642 10:02:09.192754 RX Vref Scan: 0
2643 10:02:09.192941
2644 10:02:09.195778 RX Vref 0 -> 0, step: 1
2645 10:02:09.195901
2646 10:02:09.195978 RX Delay -40 -> 252, step: 8
2647 10:02:09.202596 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
2648 10:02:09.205943 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2649 10:02:09.209442 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2650 10:02:09.212578 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2651 10:02:09.216198 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2652 10:02:09.222492 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2653 10:02:09.225919 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2654 10:02:09.229326 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2655 10:02:09.232366 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2656 10:02:09.235922 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2657 10:02:09.242373 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2658 10:02:09.245960 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2659 10:02:09.249437 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2660 10:02:09.252896 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2661 10:02:09.256215 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2662 10:02:09.262984 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2663 10:02:09.263455 ==
2664 10:02:09.265994 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 10:02:09.269489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 10:02:09.270092 ==
2667 10:02:09.270469 DQS Delay:
2668 10:02:09.272550 DQS0 = 0, DQS1 = 0
2669 10:02:09.273049 DQM Delay:
2670 10:02:09.275594 DQM0 = 122, DQM1 = 110
2671 10:02:09.276219 DQ Delay:
2672 10:02:09.279248 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2673 10:02:09.282467 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2674 10:02:09.285525 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2675 10:02:09.288980 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2676 10:02:09.289608
2677 10:02:09.290180
2678 10:02:09.292212 ==
2679 10:02:09.295735 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 10:02:09.298837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 10:02:09.299307 ==
2682 10:02:09.299676
2683 10:02:09.300022
2684 10:02:09.302216 TX Vref Scan disable
2685 10:02:09.302807 == TX Byte 0 ==
2686 10:02:09.305464 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2687 10:02:09.312496 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2688 10:02:09.313227 == TX Byte 1 ==
2689 10:02:09.318969 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2690 10:02:09.322388 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2691 10:02:09.322992 ==
2692 10:02:09.325559 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 10:02:09.328342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 10:02:09.328739 ==
2695 10:02:09.340806 TX Vref=22, minBit 0, minWin=24, winSum=402
2696 10:02:09.344276 TX Vref=24, minBit 4, minWin=23, winSum=405
2697 10:02:09.347695 TX Vref=26, minBit 0, minWin=24, winSum=411
2698 10:02:09.350719 TX Vref=28, minBit 6, minWin=25, winSum=420
2699 10:02:09.354500 TX Vref=30, minBit 0, minWin=25, winSum=416
2700 10:02:09.360536 TX Vref=32, minBit 1, minWin=25, winSum=412
2701 10:02:09.364084 [TxChooseVref] Worse bit 6, Min win 25, Win sum 420, Final Vref 28
2702 10:02:09.364386
2703 10:02:09.367721 Final TX Range 1 Vref 28
2704 10:02:09.368132
2705 10:02:09.368412 ==
2706 10:02:09.370893 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 10:02:09.374396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 10:02:09.374699 ==
2709 10:02:09.377168
2710 10:02:09.377467
2711 10:02:09.377706 TX Vref Scan disable
2712 10:02:09.381084 == TX Byte 0 ==
2713 10:02:09.384444 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2714 10:02:09.390904 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2715 10:02:09.391399 == TX Byte 1 ==
2716 10:02:09.394139 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2717 10:02:09.401542 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2718 10:02:09.402112
2719 10:02:09.402489 [DATLAT]
2720 10:02:09.402835 Freq=1200, CH0 RK0
2721 10:02:09.403169
2722 10:02:09.403939 DATLAT Default: 0xd
2723 10:02:09.404322 0, 0xFFFF, sum = 0
2724 10:02:09.407560 1, 0xFFFF, sum = 0
2725 10:02:09.408133 2, 0xFFFF, sum = 0
2726 10:02:09.411036 3, 0xFFFF, sum = 0
2727 10:02:09.414364 4, 0xFFFF, sum = 0
2728 10:02:09.414936 5, 0xFFFF, sum = 0
2729 10:02:09.417596 6, 0xFFFF, sum = 0
2730 10:02:09.418170 7, 0xFFFF, sum = 0
2731 10:02:09.420709 8, 0xFFFF, sum = 0
2732 10:02:09.421319 9, 0xFFFF, sum = 0
2733 10:02:09.423818 10, 0xFFFF, sum = 0
2734 10:02:09.424296 11, 0xFFFF, sum = 0
2735 10:02:09.427509 12, 0x0, sum = 1
2736 10:02:09.428087 13, 0x0, sum = 2
2737 10:02:09.431117 14, 0x0, sum = 3
2738 10:02:09.431693 15, 0x0, sum = 4
2739 10:02:09.434089 best_step = 13
2740 10:02:09.434660
2741 10:02:09.435036 ==
2742 10:02:09.437177 Dram Type= 6, Freq= 0, CH_0, rank 0
2743 10:02:09.440477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2744 10:02:09.441081 ==
2745 10:02:09.441453 RX Vref Scan: 1
2746 10:02:09.441796
2747 10:02:09.444201 Set Vref Range= 32 -> 127
2748 10:02:09.444809
2749 10:02:09.447715 RX Vref 32 -> 127, step: 1
2750 10:02:09.448283
2751 10:02:09.450578 RX Delay -13 -> 252, step: 4
2752 10:02:09.451151
2753 10:02:09.453749 Set Vref, RX VrefLevel [Byte0]: 32
2754 10:02:09.457394 [Byte1]: 32
2755 10:02:09.457962
2756 10:02:09.460831 Set Vref, RX VrefLevel [Byte0]: 33
2757 10:02:09.463844 [Byte1]: 33
2758 10:02:09.467177
2759 10:02:09.467638 Set Vref, RX VrefLevel [Byte0]: 34
2760 10:02:09.470502 [Byte1]: 34
2761 10:02:09.475009
2762 10:02:09.475592 Set Vref, RX VrefLevel [Byte0]: 35
2763 10:02:09.478535 [Byte1]: 35
2764 10:02:09.483042
2765 10:02:09.483616 Set Vref, RX VrefLevel [Byte0]: 36
2766 10:02:09.486218 [Byte1]: 36
2767 10:02:09.491168
2768 10:02:09.491729 Set Vref, RX VrefLevel [Byte0]: 37
2769 10:02:09.494235 [Byte1]: 37
2770 10:02:09.498992
2771 10:02:09.499559 Set Vref, RX VrefLevel [Byte0]: 38
2772 10:02:09.502472 [Byte1]: 38
2773 10:02:09.506929
2774 10:02:09.507397 Set Vref, RX VrefLevel [Byte0]: 39
2775 10:02:09.509992 [Byte1]: 39
2776 10:02:09.514563
2777 10:02:09.515123 Set Vref, RX VrefLevel [Byte0]: 40
2778 10:02:09.517991 [Byte1]: 40
2779 10:02:09.522029
2780 10:02:09.522503 Set Vref, RX VrefLevel [Byte0]: 41
2781 10:02:09.525648 [Byte1]: 41
2782 10:02:09.530206
2783 10:02:09.530678 Set Vref, RX VrefLevel [Byte0]: 42
2784 10:02:09.533657 [Byte1]: 42
2785 10:02:09.538151
2786 10:02:09.538621 Set Vref, RX VrefLevel [Byte0]: 43
2787 10:02:09.544507 [Byte1]: 43
2788 10:02:09.545007
2789 10:02:09.547899 Set Vref, RX VrefLevel [Byte0]: 44
2790 10:02:09.551732 [Byte1]: 44
2791 10:02:09.552298
2792 10:02:09.554817 Set Vref, RX VrefLevel [Byte0]: 45
2793 10:02:09.557998 [Byte1]: 45
2794 10:02:09.562162
2795 10:02:09.562627 Set Vref, RX VrefLevel [Byte0]: 46
2796 10:02:09.565067 [Byte1]: 46
2797 10:02:09.569657
2798 10:02:09.570241 Set Vref, RX VrefLevel [Byte0]: 47
2799 10:02:09.572937 [Byte1]: 47
2800 10:02:09.578103
2801 10:02:09.578669 Set Vref, RX VrefLevel [Byte0]: 48
2802 10:02:09.580913 [Byte1]: 48
2803 10:02:09.585529
2804 10:02:09.586098 Set Vref, RX VrefLevel [Byte0]: 49
2805 10:02:09.588988 [Byte1]: 49
2806 10:02:09.593394
2807 10:02:09.593993 Set Vref, RX VrefLevel [Byte0]: 50
2808 10:02:09.596475 [Byte1]: 50
2809 10:02:09.601270
2810 10:02:09.601738 Set Vref, RX VrefLevel [Byte0]: 51
2811 10:02:09.604400 [Byte1]: 51
2812 10:02:09.608866
2813 10:02:09.609331 Set Vref, RX VrefLevel [Byte0]: 52
2814 10:02:09.612618 [Byte1]: 52
2815 10:02:09.617198
2816 10:02:09.617620 Set Vref, RX VrefLevel [Byte0]: 53
2817 10:02:09.620094 [Byte1]: 53
2818 10:02:09.624251
2819 10:02:09.624335 Set Vref, RX VrefLevel [Byte0]: 54
2820 10:02:09.627589 [Byte1]: 54
2821 10:02:09.632165
2822 10:02:09.632247 Set Vref, RX VrefLevel [Byte0]: 55
2823 10:02:09.635899 [Byte1]: 55
2824 10:02:09.640579
2825 10:02:09.640662 Set Vref, RX VrefLevel [Byte0]: 56
2826 10:02:09.643449 [Byte1]: 56
2827 10:02:09.648671
2828 10:02:09.648753 Set Vref, RX VrefLevel [Byte0]: 57
2829 10:02:09.651819 [Byte1]: 57
2830 10:02:09.655840
2831 10:02:09.655922 Set Vref, RX VrefLevel [Byte0]: 58
2832 10:02:09.659142 [Byte1]: 58
2833 10:02:09.663959
2834 10:02:09.664041 Set Vref, RX VrefLevel [Byte0]: 59
2835 10:02:09.667172 [Byte1]: 59
2836 10:02:09.671782
2837 10:02:09.671864 Set Vref, RX VrefLevel [Byte0]: 60
2838 10:02:09.674983 [Byte1]: 60
2839 10:02:09.679821
2840 10:02:09.679904 Set Vref, RX VrefLevel [Byte0]: 61
2841 10:02:09.682953 [Byte1]: 61
2842 10:02:09.687648
2843 10:02:09.687731 Set Vref, RX VrefLevel [Byte0]: 62
2844 10:02:09.691868 [Byte1]: 62
2845 10:02:09.695783
2846 10:02:09.695865 Set Vref, RX VrefLevel [Byte0]: 63
2847 10:02:09.698780 [Byte1]: 63
2848 10:02:09.703397
2849 10:02:09.703552 Set Vref, RX VrefLevel [Byte0]: 64
2850 10:02:09.706807 [Byte1]: 64
2851 10:02:09.711324
2852 10:02:09.711406 Set Vref, RX VrefLevel [Byte0]: 65
2853 10:02:09.714483 [Byte1]: 65
2854 10:02:09.719023
2855 10:02:09.719106 Set Vref, RX VrefLevel [Byte0]: 66
2856 10:02:09.722589 [Byte1]: 66
2857 10:02:09.727167
2858 10:02:09.727250 Set Vref, RX VrefLevel [Byte0]: 67
2859 10:02:09.730658 [Byte1]: 67
2860 10:02:09.735278
2861 10:02:09.735360 Set Vref, RX VrefLevel [Byte0]: 68
2862 10:02:09.738945 [Byte1]: 68
2863 10:02:09.743042
2864 10:02:09.743465 Final RX Vref Byte 0 = 59 to rank0
2865 10:02:09.746629 Final RX Vref Byte 1 = 49 to rank0
2866 10:02:09.749935 Final RX Vref Byte 0 = 59 to rank1
2867 10:02:09.753094 Final RX Vref Byte 1 = 49 to rank1==
2868 10:02:09.756446 Dram Type= 6, Freq= 0, CH_0, rank 0
2869 10:02:09.763368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2870 10:02:09.763797 ==
2871 10:02:09.764134 DQS Delay:
2872 10:02:09.764444 DQS0 = 0, DQS1 = 0
2873 10:02:09.766494 DQM Delay:
2874 10:02:09.766957 DQM0 = 123, DQM1 = 109
2875 10:02:09.769660 DQ Delay:
2876 10:02:09.772991 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2877 10:02:09.776301 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2878 10:02:09.779664 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2879 10:02:09.782926 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2880 10:02:09.783115
2881 10:02:09.783279
2882 10:02:09.789550 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2883 10:02:09.792703 CH0 RK0: MR19=404, MR18=D0A
2884 10:02:09.799486 CH0_RK0: MR19=0x404, MR18=0xD0A, DQSOSC=405, MR23=63, INC=39, DEC=26
2885 10:02:09.799633
2886 10:02:09.802765 ----->DramcWriteLeveling(PI) begin...
2887 10:02:09.802920 ==
2888 10:02:09.806171 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 10:02:09.809346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 10:02:09.812698 ==
2891 10:02:09.812860 Write leveling (Byte 0): 34 => 34
2892 10:02:09.816080 Write leveling (Byte 1): 32 => 32
2893 10:02:09.819368 DramcWriteLeveling(PI) end<-----
2894 10:02:09.819450
2895 10:02:09.819515 ==
2896 10:02:09.822533 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 10:02:09.829615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 10:02:09.829698 ==
2899 10:02:09.829762 [Gating] SW mode calibration
2900 10:02:09.839677 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2901 10:02:09.842981 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2902 10:02:09.846651 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2903 10:02:09.853276 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 10:02:09.856161 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 10:02:09.859495 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 10:02:09.866504 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 10:02:09.869447 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 10:02:09.872792 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 10:02:09.879817 0 15 28 | B1->B0 | 2f2f 2d2d | 0 1 | (1 0) (1 0)
2910 10:02:09.882784 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2911 10:02:09.886102 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 10:02:09.892884 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 10:02:09.896164 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 10:02:09.899521 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 10:02:09.906598 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 10:02:09.909521 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 10:02:09.913072 1 0 28 | B1->B0 | 3938 3e3e | 1 1 | (0 0) (0 0)
2918 10:02:09.919698 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 10:02:09.922915 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 10:02:09.925930 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 10:02:09.932603 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 10:02:09.936357 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 10:02:09.939669 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 10:02:09.946335 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 10:02:09.949632 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2926 10:02:09.952759 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2927 10:02:09.959129 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 10:02:09.962269 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 10:02:09.965760 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 10:02:09.972632 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 10:02:09.975945 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 10:02:09.978573 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 10:02:09.985213 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 10:02:09.988648 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 10:02:09.992513 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 10:02:09.995473 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 10:02:10.001866 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 10:02:10.005490 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 10:02:10.008418 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 10:02:10.014838 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 10:02:10.018175 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2942 10:02:10.021781 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2943 10:02:10.024730 Total UI for P1: 0, mck2ui 16
2944 10:02:10.028304 best dqsien dly found for B1: ( 1, 3, 28)
2945 10:02:10.035070 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 10:02:10.038238 Total UI for P1: 0, mck2ui 16
2947 10:02:10.041541 best dqsien dly found for B0: ( 1, 3, 30)
2948 10:02:10.044742 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2949 10:02:10.048120 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2950 10:02:10.048202
2951 10:02:10.051734 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2952 10:02:10.054880 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2953 10:02:10.058403 [Gating] SW calibration Done
2954 10:02:10.058485 ==
2955 10:02:10.061848 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 10:02:10.064812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 10:02:10.064895 ==
2958 10:02:10.068199 RX Vref Scan: 0
2959 10:02:10.068281
2960 10:02:10.068347 RX Vref 0 -> 0, step: 1
2961 10:02:10.071251
2962 10:02:10.071333 RX Delay -40 -> 252, step: 8
2963 10:02:10.077897 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2964 10:02:10.081169 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2965 10:02:10.084713 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2966 10:02:10.087847 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2967 10:02:10.091259 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2968 10:02:10.098198 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2969 10:02:10.101631 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2970 10:02:10.104625 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2971 10:02:10.108400 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2972 10:02:10.111747 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2973 10:02:10.115140 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2974 10:02:10.121833 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2975 10:02:10.124864 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2976 10:02:10.128069 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2977 10:02:10.131876 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2978 10:02:10.138498 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2979 10:02:10.138736 ==
2980 10:02:10.141898 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 10:02:10.145001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 10:02:10.145297 ==
2983 10:02:10.145473 DQS Delay:
2984 10:02:10.148520 DQS0 = 0, DQS1 = 0
2985 10:02:10.148819 DQM Delay:
2986 10:02:10.151800 DQM0 = 120, DQM1 = 108
2987 10:02:10.152134 DQ Delay:
2988 10:02:10.155175 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2989 10:02:10.158284 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2990 10:02:10.162009 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2991 10:02:10.165656 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2992 10:02:10.166213
2993 10:02:10.166582
2994 10:02:10.166923 ==
2995 10:02:10.168186 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 10:02:10.175492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 10:02:10.176052 ==
2998 10:02:10.176419
2999 10:02:10.176759
3000 10:02:10.177136 TX Vref Scan disable
3001 10:02:10.178525 == TX Byte 0 ==
3002 10:02:10.182418 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3003 10:02:10.185875 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3004 10:02:10.188912 == TX Byte 1 ==
3005 10:02:10.192621 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3006 10:02:10.195782 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3007 10:02:10.198713 ==
3008 10:02:10.201857 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 10:02:10.204962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 10:02:10.205446 ==
3011 10:02:10.216811 TX Vref=22, minBit 1, minWin=23, winSum=404
3012 10:02:10.220027 TX Vref=24, minBit 0, minWin=24, winSum=408
3013 10:02:10.223786 TX Vref=26, minBit 0, minWin=25, winSum=412
3014 10:02:10.226598 TX Vref=28, minBit 1, minWin=25, winSum=420
3015 10:02:10.230369 TX Vref=30, minBit 1, minWin=25, winSum=418
3016 10:02:10.237186 TX Vref=32, minBit 2, minWin=25, winSum=419
3017 10:02:10.239929 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 28
3018 10:02:10.240501
3019 10:02:10.243438 Final TX Range 1 Vref 28
3020 10:02:10.244014
3021 10:02:10.244385 ==
3022 10:02:10.246773 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 10:02:10.249707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 10:02:10.253130 ==
3025 10:02:10.253706
3026 10:02:10.254077
3027 10:02:10.254413 TX Vref Scan disable
3028 10:02:10.256529 == TX Byte 0 ==
3029 10:02:10.260240 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3030 10:02:10.266598 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3031 10:02:10.267172 == TX Byte 1 ==
3032 10:02:10.270271 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3033 10:02:10.276642 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3034 10:02:10.277260
3035 10:02:10.277633 [DATLAT]
3036 10:02:10.277972 Freq=1200, CH0 RK1
3037 10:02:10.278297
3038 10:02:10.279655 DATLAT Default: 0xd
3039 10:02:10.280124 0, 0xFFFF, sum = 0
3040 10:02:10.282986 1, 0xFFFF, sum = 0
3041 10:02:10.283565 2, 0xFFFF, sum = 0
3042 10:02:10.286328 3, 0xFFFF, sum = 0
3043 10:02:10.289537 4, 0xFFFF, sum = 0
3044 10:02:10.290120 5, 0xFFFF, sum = 0
3045 10:02:10.293186 6, 0xFFFF, sum = 0
3046 10:02:10.293765 7, 0xFFFF, sum = 0
3047 10:02:10.296384 8, 0xFFFF, sum = 0
3048 10:02:10.296893 9, 0xFFFF, sum = 0
3049 10:02:10.300034 10, 0xFFFF, sum = 0
3050 10:02:10.300611 11, 0xFFFF, sum = 0
3051 10:02:10.302893 12, 0x0, sum = 1
3052 10:02:10.303365 13, 0x0, sum = 2
3053 10:02:10.306262 14, 0x0, sum = 3
3054 10:02:10.306742 15, 0x0, sum = 4
3055 10:02:10.309736 best_step = 13
3056 10:02:10.310202
3057 10:02:10.310567 ==
3058 10:02:10.313141 Dram Type= 6, Freq= 0, CH_0, rank 1
3059 10:02:10.316237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 10:02:10.316950 ==
3061 10:02:10.317510 RX Vref Scan: 0
3062 10:02:10.317997
3063 10:02:10.319206 RX Vref 0 -> 0, step: 1
3064 10:02:10.319799
3065 10:02:10.322843 RX Delay -21 -> 252, step: 4
3066 10:02:10.326839 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3067 10:02:10.332708 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3068 10:02:10.336232 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3069 10:02:10.339254 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3070 10:02:10.343017 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3071 10:02:10.346260 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3072 10:02:10.353060 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3073 10:02:10.356410 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3074 10:02:10.359991 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3075 10:02:10.362944 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3076 10:02:10.366004 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3077 10:02:10.372924 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3078 10:02:10.376498 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3079 10:02:10.379887 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3080 10:02:10.382802 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3081 10:02:10.386258 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3082 10:02:10.389737 ==
3083 10:02:10.392310 Dram Type= 6, Freq= 0, CH_0, rank 1
3084 10:02:10.395832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 10:02:10.396303 ==
3086 10:02:10.396670 DQS Delay:
3087 10:02:10.399532 DQS0 = 0, DQS1 = 0
3088 10:02:10.400103 DQM Delay:
3089 10:02:10.402368 DQM0 = 119, DQM1 = 107
3090 10:02:10.402850 DQ Delay:
3091 10:02:10.405581 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3092 10:02:10.409115 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3093 10:02:10.413477 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3094 10:02:10.415837 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3095 10:02:10.416411
3096 10:02:10.416807
3097 10:02:10.425705 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3098 10:02:10.428883 CH0 RK1: MR19=403, MR18=10F7
3099 10:02:10.432557 CH0_RK1: MR19=0x403, MR18=0x10F7, DQSOSC=403, MR23=63, INC=40, DEC=26
3100 10:02:10.435638 [RxdqsGatingPostProcess] freq 1200
3101 10:02:10.441879 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3102 10:02:10.445431 best DQS0 dly(2T, 0.5T) = (0, 11)
3103 10:02:10.448732 best DQS1 dly(2T, 0.5T) = (0, 11)
3104 10:02:10.452425 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3105 10:02:10.455668 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3106 10:02:10.458960 best DQS0 dly(2T, 0.5T) = (0, 11)
3107 10:02:10.461747 best DQS1 dly(2T, 0.5T) = (0, 11)
3108 10:02:10.465047 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3109 10:02:10.468372 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3110 10:02:10.472687 Pre-setting of DQS Precalculation
3111 10:02:10.475138 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3112 10:02:10.475561 ==
3113 10:02:10.479293 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 10:02:10.482309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 10:02:10.482844 ==
3116 10:02:10.489191 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3117 10:02:10.495167 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3118 10:02:10.502932 [CA 0] Center 37 (7~68) winsize 62
3119 10:02:10.506281 [CA 1] Center 37 (7~68) winsize 62
3120 10:02:10.509791 [CA 2] Center 35 (5~65) winsize 61
3121 10:02:10.513431 [CA 3] Center 34 (4~65) winsize 62
3122 10:02:10.516902 [CA 4] Center 34 (4~64) winsize 61
3123 10:02:10.519460 [CA 5] Center 33 (3~64) winsize 62
3124 10:02:10.519947
3125 10:02:10.523250 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3126 10:02:10.523844
3127 10:02:10.526122 [CATrainingPosCal] consider 1 rank data
3128 10:02:10.529510 u2DelayCellTimex100 = 270/100 ps
3129 10:02:10.533096 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3130 10:02:10.535983 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3131 10:02:10.543119 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3132 10:02:10.546247 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3133 10:02:10.549536 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 10:02:10.553203 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3135 10:02:10.553795
3136 10:02:10.556280 CA PerBit enable=1, Macro0, CA PI delay=33
3137 10:02:10.556895
3138 10:02:10.559837 [CBTSetCACLKResult] CA Dly = 33
3139 10:02:10.560430 CS Dly: 5 (0~36)
3140 10:02:10.562500 ==
3141 10:02:10.563012 Dram Type= 6, Freq= 0, CH_1, rank 1
3142 10:02:10.569655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 10:02:10.570255 ==
3144 10:02:10.573014 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3145 10:02:10.579641 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3146 10:02:10.588896 [CA 0] Center 38 (8~68) winsize 61
3147 10:02:10.591999 [CA 1] Center 38 (7~69) winsize 63
3148 10:02:10.595393 [CA 2] Center 35 (5~66) winsize 62
3149 10:02:10.598522 [CA 3] Center 35 (5~65) winsize 61
3150 10:02:10.602397 [CA 4] Center 35 (5~65) winsize 61
3151 10:02:10.605403 [CA 5] Center 34 (4~64) winsize 61
3152 10:02:10.605983
3153 10:02:10.608605 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3154 10:02:10.609114
3155 10:02:10.611943 [CATrainingPosCal] consider 2 rank data
3156 10:02:10.615441 u2DelayCellTimex100 = 270/100 ps
3157 10:02:10.618577 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3158 10:02:10.621760 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3159 10:02:10.628902 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3160 10:02:10.631920 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3161 10:02:10.635476 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3162 10:02:10.638455 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3163 10:02:10.639022
3164 10:02:10.641674 CA PerBit enable=1, Macro0, CA PI delay=34
3165 10:02:10.642149
3166 10:02:10.645218 [CBTSetCACLKResult] CA Dly = 34
3167 10:02:10.645691 CS Dly: 6 (0~39)
3168 10:02:10.648452
3169 10:02:10.651660 ----->DramcWriteLeveling(PI) begin...
3170 10:02:10.652234 ==
3171 10:02:10.655158 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 10:02:10.658811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 10:02:10.659380 ==
3174 10:02:10.661555 Write leveling (Byte 0): 25 => 25
3175 10:02:10.665305 Write leveling (Byte 1): 29 => 29
3176 10:02:10.668191 DramcWriteLeveling(PI) end<-----
3177 10:02:10.668762
3178 10:02:10.669202 ==
3179 10:02:10.671444 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 10:02:10.674862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 10:02:10.675336 ==
3182 10:02:10.678943 [Gating] SW mode calibration
3183 10:02:10.684925 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3184 10:02:10.692047 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3185 10:02:10.695189 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 10:02:10.698390 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 10:02:10.705154 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 10:02:10.708061 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 10:02:10.711754 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 10:02:10.717795 0 15 20 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
3191 10:02:10.721352 0 15 24 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (0 0)
3192 10:02:10.724863 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3193 10:02:10.727846 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 10:02:10.734886 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 10:02:10.737857 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 10:02:10.741294 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 10:02:10.747958 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 10:02:10.750984 1 0 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
3199 10:02:10.754984 1 0 24 | B1->B0 | 3f3f 4444 | 1 0 | (0 0) (0 0)
3200 10:02:10.761441 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 10:02:10.764844 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 10:02:10.768196 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 10:02:10.774671 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 10:02:10.778198 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 10:02:10.780988 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 10:02:10.788059 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3207 10:02:10.791227 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3208 10:02:10.794542 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3209 10:02:10.801588 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 10:02:10.804490 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 10:02:10.807777 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 10:02:10.814975 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 10:02:10.817890 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 10:02:10.821170 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 10:02:10.827965 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 10:02:10.830960 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 10:02:10.834463 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 10:02:10.841002 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 10:02:10.844377 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 10:02:10.847573 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 10:02:10.854776 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 10:02:10.857740 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 10:02:10.861120 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3224 10:02:10.867874 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3225 10:02:10.868446 Total UI for P1: 0, mck2ui 16
3226 10:02:10.870862 best dqsien dly found for B0: ( 1, 3, 24)
3227 10:02:10.877248 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 10:02:10.880411 Total UI for P1: 0, mck2ui 16
3229 10:02:10.883953 best dqsien dly found for B1: ( 1, 3, 26)
3230 10:02:10.886914 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3231 10:02:10.890878 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3232 10:02:10.891464
3233 10:02:10.894238 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3234 10:02:10.897002 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3235 10:02:10.900461 [Gating] SW calibration Done
3236 10:02:10.901071 ==
3237 10:02:10.904013 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 10:02:10.906889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 10:02:10.907372 ==
3240 10:02:10.910882 RX Vref Scan: 0
3241 10:02:10.911455
3242 10:02:10.913796 RX Vref 0 -> 0, step: 1
3243 10:02:10.914269
3244 10:02:10.914645 RX Delay -40 -> 252, step: 8
3245 10:02:10.920510 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3246 10:02:10.924075 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3247 10:02:10.927305 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3248 10:02:10.930245 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3249 10:02:10.933433 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3250 10:02:10.940618 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3251 10:02:10.944124 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3252 10:02:10.947320 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3253 10:02:10.950488 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3254 10:02:10.953429 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3255 10:02:10.960277 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3256 10:02:10.963873 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3257 10:02:10.966739 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3258 10:02:10.970262 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3259 10:02:10.973824 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3260 10:02:10.980318 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3261 10:02:10.980923 ==
3262 10:02:10.983541 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 10:02:10.987171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 10:02:10.987743 ==
3265 10:02:10.988113 DQS Delay:
3266 10:02:10.990438 DQS0 = 0, DQS1 = 0
3267 10:02:10.991003 DQM Delay:
3268 10:02:10.994155 DQM0 = 120, DQM1 = 113
3269 10:02:10.994723 DQ Delay:
3270 10:02:10.996384 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3271 10:02:11.000300 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =123
3272 10:02:11.003564 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3273 10:02:11.006925 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3274 10:02:11.007500
3275 10:02:11.009884
3276 10:02:11.010343 ==
3277 10:02:11.013701 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 10:02:11.016460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 10:02:11.017066 ==
3280 10:02:11.017437
3281 10:02:11.017772
3282 10:02:11.020071 TX Vref Scan disable
3283 10:02:11.020641 == TX Byte 0 ==
3284 10:02:11.026759 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3285 10:02:11.029930 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3286 10:02:11.030506 == TX Byte 1 ==
3287 10:02:11.036981 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3288 10:02:11.040205 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3289 10:02:11.040824 ==
3290 10:02:11.043387 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 10:02:11.046370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 10:02:11.046945 ==
3293 10:02:11.058835 TX Vref=22, minBit 11, minWin=24, winSum=408
3294 10:02:11.061894 TX Vref=24, minBit 11, minWin=24, winSum=409
3295 10:02:11.065707 TX Vref=26, minBit 3, minWin=25, winSum=416
3296 10:02:11.068890 TX Vref=28, minBit 11, minWin=25, winSum=422
3297 10:02:11.072211 TX Vref=30, minBit 10, minWin=25, winSum=421
3298 10:02:11.078427 TX Vref=32, minBit 9, minWin=25, winSum=421
3299 10:02:11.081873 [TxChooseVref] Worse bit 11, Min win 25, Win sum 422, Final Vref 28
3300 10:02:11.082468
3301 10:02:11.085699 Final TX Range 1 Vref 28
3302 10:02:11.086290
3303 10:02:11.086780 ==
3304 10:02:11.088474 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 10:02:11.095263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 10:02:11.095852 ==
3307 10:02:11.096342
3308 10:02:11.096825
3309 10:02:11.097346 TX Vref Scan disable
3310 10:02:11.098570 == TX Byte 0 ==
3311 10:02:11.102365 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3312 10:02:11.108814 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3313 10:02:11.109410 == TX Byte 1 ==
3314 10:02:11.112451 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3315 10:02:11.118775 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3316 10:02:11.119349
3317 10:02:11.119838 [DATLAT]
3318 10:02:11.120293 Freq=1200, CH1 RK0
3319 10:02:11.120739
3320 10:02:11.122557 DATLAT Default: 0xd
3321 10:02:11.123145 0, 0xFFFF, sum = 0
3322 10:02:11.125867 1, 0xFFFF, sum = 0
3323 10:02:11.126465 2, 0xFFFF, sum = 0
3324 10:02:11.128683 3, 0xFFFF, sum = 0
3325 10:02:11.131897 4, 0xFFFF, sum = 0
3326 10:02:11.132391 5, 0xFFFF, sum = 0
3327 10:02:11.136207 6, 0xFFFF, sum = 0
3328 10:02:11.136836 7, 0xFFFF, sum = 0
3329 10:02:11.138862 8, 0xFFFF, sum = 0
3330 10:02:11.139464 9, 0xFFFF, sum = 0
3331 10:02:11.141850 10, 0xFFFF, sum = 0
3332 10:02:11.142337 11, 0xFFFF, sum = 0
3333 10:02:11.145214 12, 0x0, sum = 1
3334 10:02:11.145703 13, 0x0, sum = 2
3335 10:02:11.148988 14, 0x0, sum = 3
3336 10:02:11.149577 15, 0x0, sum = 4
3337 10:02:11.150070 best_step = 13
3338 10:02:11.151669
3339 10:02:11.152148 ==
3340 10:02:11.155136 Dram Type= 6, Freq= 0, CH_1, rank 0
3341 10:02:11.158747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3342 10:02:11.159337 ==
3343 10:02:11.159827 RX Vref Scan: 1
3344 10:02:11.161559
3345 10:02:11.162041 Set Vref Range= 32 -> 127
3346 10:02:11.162521
3347 10:02:11.165219 RX Vref 32 -> 127, step: 1
3348 10:02:11.165810
3349 10:02:11.168354 RX Delay -13 -> 252, step: 4
3350 10:02:11.168874
3351 10:02:11.171841 Set Vref, RX VrefLevel [Byte0]: 32
3352 10:02:11.174744 [Byte1]: 32
3353 10:02:11.175227
3354 10:02:11.178111 Set Vref, RX VrefLevel [Byte0]: 33
3355 10:02:11.181358 [Byte1]: 33
3356 10:02:11.184986
3357 10:02:11.185575 Set Vref, RX VrefLevel [Byte0]: 34
3358 10:02:11.188450 [Byte1]: 34
3359 10:02:11.193276
3360 10:02:11.193874 Set Vref, RX VrefLevel [Byte0]: 35
3361 10:02:11.196211 [Byte1]: 35
3362 10:02:11.200959
3363 10:02:11.201477 Set Vref, RX VrefLevel [Byte0]: 36
3364 10:02:11.204101 [Byte1]: 36
3365 10:02:11.208670
3366 10:02:11.208987 Set Vref, RX VrefLevel [Byte0]: 37
3367 10:02:11.211815 [Byte1]: 37
3368 10:02:11.216181
3369 10:02:11.216275 Set Vref, RX VrefLevel [Byte0]: 38
3370 10:02:11.219364 [Byte1]: 38
3371 10:02:11.224279
3372 10:02:11.224359 Set Vref, RX VrefLevel [Byte0]: 39
3373 10:02:11.227392 [Byte1]: 39
3374 10:02:11.231927
3375 10:02:11.232008 Set Vref, RX VrefLevel [Byte0]: 40
3376 10:02:11.235367 [Byte1]: 40
3377 10:02:11.240137
3378 10:02:11.240217 Set Vref, RX VrefLevel [Byte0]: 41
3379 10:02:11.243630 [Byte1]: 41
3380 10:02:11.248426
3381 10:02:11.248856 Set Vref, RX VrefLevel [Byte0]: 42
3382 10:02:11.251389 [Byte1]: 42
3383 10:02:11.256228
3384 10:02:11.256640 Set Vref, RX VrefLevel [Byte0]: 43
3385 10:02:11.259365 [Byte1]: 43
3386 10:02:11.264407
3387 10:02:11.264960 Set Vref, RX VrefLevel [Byte0]: 44
3388 10:02:11.267159 [Byte1]: 44
3389 10:02:11.271964
3390 10:02:11.272480 Set Vref, RX VrefLevel [Byte0]: 45
3391 10:02:11.274986 [Byte1]: 45
3392 10:02:11.280187
3393 10:02:11.280704 Set Vref, RX VrefLevel [Byte0]: 46
3394 10:02:11.283439 [Byte1]: 46
3395 10:02:11.287480
3396 10:02:11.287892 Set Vref, RX VrefLevel [Byte0]: 47
3397 10:02:11.291128 [Byte1]: 47
3398 10:02:11.295725
3399 10:02:11.296138 Set Vref, RX VrefLevel [Byte0]: 48
3400 10:02:11.298714 [Byte1]: 48
3401 10:02:11.303616
3402 10:02:11.304130 Set Vref, RX VrefLevel [Byte0]: 49
3403 10:02:11.306800 [Byte1]: 49
3404 10:02:11.311653
3405 10:02:11.312168 Set Vref, RX VrefLevel [Byte0]: 50
3406 10:02:11.314974 [Byte1]: 50
3407 10:02:11.319284
3408 10:02:11.319838 Set Vref, RX VrefLevel [Byte0]: 51
3409 10:02:11.322619 [Byte1]: 51
3410 10:02:11.327157
3411 10:02:11.327717 Set Vref, RX VrefLevel [Byte0]: 52
3412 10:02:11.330569 [Byte1]: 52
3413 10:02:11.335163
3414 10:02:11.335623 Set Vref, RX VrefLevel [Byte0]: 53
3415 10:02:11.338493 [Byte1]: 53
3416 10:02:11.342751
3417 10:02:11.343209 Set Vref, RX VrefLevel [Byte0]: 54
3418 10:02:11.346530 [Byte1]: 54
3419 10:02:11.350961
3420 10:02:11.351518 Set Vref, RX VrefLevel [Byte0]: 55
3421 10:02:11.354489 [Byte1]: 55
3422 10:02:11.358748
3423 10:02:11.359204 Set Vref, RX VrefLevel [Byte0]: 56
3424 10:02:11.362316 [Byte1]: 56
3425 10:02:11.366778
3426 10:02:11.367347 Set Vref, RX VrefLevel [Byte0]: 57
3427 10:02:11.370515 [Byte1]: 57
3428 10:02:11.374373
3429 10:02:11.375022 Set Vref, RX VrefLevel [Byte0]: 58
3430 10:02:11.377787 [Byte1]: 58
3431 10:02:11.382610
3432 10:02:11.383188 Set Vref, RX VrefLevel [Byte0]: 59
3433 10:02:11.385400 [Byte1]: 59
3434 10:02:11.390081
3435 10:02:11.390538 Set Vref, RX VrefLevel [Byte0]: 60
3436 10:02:11.393346 [Byte1]: 60
3437 10:02:11.398062
3438 10:02:11.398513 Set Vref, RX VrefLevel [Byte0]: 61
3439 10:02:11.401337 [Byte1]: 61
3440 10:02:11.406428
3441 10:02:11.406990 Set Vref, RX VrefLevel [Byte0]: 62
3442 10:02:11.409294 [Byte1]: 62
3443 10:02:11.414237
3444 10:02:11.414790 Set Vref, RX VrefLevel [Byte0]: 63
3445 10:02:11.417412 [Byte1]: 63
3446 10:02:11.422602
3447 10:02:11.423157 Set Vref, RX VrefLevel [Byte0]: 64
3448 10:02:11.425367 [Byte1]: 64
3449 10:02:11.430107
3450 10:02:11.430663 Set Vref, RX VrefLevel [Byte0]: 65
3451 10:02:11.432883 [Byte1]: 65
3452 10:02:11.437267
3453 10:02:11.437718 Set Vref, RX VrefLevel [Byte0]: 66
3454 10:02:11.440842 [Byte1]: 66
3455 10:02:11.445291
3456 10:02:11.445845 Final RX Vref Byte 0 = 51 to rank0
3457 10:02:11.448980 Final RX Vref Byte 1 = 49 to rank0
3458 10:02:11.452610 Final RX Vref Byte 0 = 51 to rank1
3459 10:02:11.456484 Final RX Vref Byte 1 = 49 to rank1==
3460 10:02:11.459003 Dram Type= 6, Freq= 0, CH_1, rank 0
3461 10:02:11.465515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 10:02:11.466087 ==
3463 10:02:11.466454 DQS Delay:
3464 10:02:11.466790 DQS0 = 0, DQS1 = 0
3465 10:02:11.468896 DQM Delay:
3466 10:02:11.469348 DQM0 = 119, DQM1 = 111
3467 10:02:11.472237 DQ Delay:
3468 10:02:11.475425 DQ0 =122, DQ1 =112, DQ2 =112, DQ3 =116
3469 10:02:11.478963 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3470 10:02:11.482324 DQ8 =98, DQ9 =100, DQ10 =114, DQ11 =104
3471 10:02:11.485515 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =116
3472 10:02:11.486081
3473 10:02:11.486449
3474 10:02:11.492566 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3475 10:02:11.495274 CH1 RK0: MR19=404, MR18=215
3476 10:02:11.501671 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3477 10:02:11.502135
3478 10:02:11.505415 ----->DramcWriteLeveling(PI) begin...
3479 10:02:11.505883 ==
3480 10:02:11.508499 Dram Type= 6, Freq= 0, CH_1, rank 1
3481 10:02:11.511792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 10:02:11.515497 ==
3483 10:02:11.516081 Write leveling (Byte 0): 23 => 23
3484 10:02:11.519043 Write leveling (Byte 1): 29 => 29
3485 10:02:11.522751 DramcWriteLeveling(PI) end<-----
3486 10:02:11.523325
3487 10:02:11.523695 ==
3488 10:02:11.525016 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 10:02:11.532226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 10:02:11.532834 ==
3491 10:02:11.533263 [Gating] SW mode calibration
3492 10:02:11.541927 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3493 10:02:11.545703 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3494 10:02:11.549285 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 10:02:11.555631 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 10:02:11.558990 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 10:02:11.561680 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 10:02:11.568358 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 10:02:11.571564 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 10:02:11.575201 0 15 24 | B1->B0 | 2828 3333 | 0 1 | (0 0) (1 0)
3501 10:02:11.581807 0 15 28 | B1->B0 | 2323 2c2c | 0 0 | (1 0) (0 1)
3502 10:02:11.585588 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 10:02:11.588475 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 10:02:11.595675 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 10:02:11.598428 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 10:02:11.601643 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 10:02:11.608566 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 10:02:11.612029 1 0 24 | B1->B0 | 3a3a 2626 | 0 0 | (0 0) (0 0)
3509 10:02:11.615392 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3510 10:02:11.622101 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 10:02:11.625408 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 10:02:11.628676 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 10:02:11.635406 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 10:02:11.638460 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 10:02:11.641604 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 10:02:11.645136 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3517 10:02:11.651506 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 10:02:11.655615 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 10:02:11.658402 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 10:02:11.665105 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 10:02:11.668596 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 10:02:11.671856 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 10:02:11.678652 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 10:02:11.682018 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 10:02:11.685110 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 10:02:11.691801 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 10:02:11.695339 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 10:02:11.698041 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 10:02:11.705064 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 10:02:11.708006 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 10:02:11.711211 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3532 10:02:11.717934 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3533 10:02:11.721275 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3534 10:02:11.724853 Total UI for P1: 0, mck2ui 16
3535 10:02:11.727981 best dqsien dly found for B0: ( 1, 3, 24)
3536 10:02:11.731289 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 10:02:11.734664 Total UI for P1: 0, mck2ui 16
3538 10:02:11.737624 best dqsien dly found for B1: ( 1, 3, 24)
3539 10:02:11.741237 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3540 10:02:11.744448 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3541 10:02:11.744949
3542 10:02:11.751390 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3543 10:02:11.755153 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3544 10:02:11.757652 [Gating] SW calibration Done
3545 10:02:11.758122 ==
3546 10:02:11.761211 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 10:02:11.764824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 10:02:11.765406 ==
3549 10:02:11.765778 RX Vref Scan: 0
3550 10:02:11.766125
3551 10:02:11.767612 RX Vref 0 -> 0, step: 1
3552 10:02:11.768164
3553 10:02:11.770912 RX Delay -40 -> 252, step: 8
3554 10:02:11.774267 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3555 10:02:11.777559 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3556 10:02:11.784112 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3557 10:02:11.787405 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3558 10:02:11.790840 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3559 10:02:11.793997 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3560 10:02:11.797611 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3561 10:02:11.804086 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3562 10:02:11.806936 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3563 10:02:11.810346 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3564 10:02:11.813606 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3565 10:02:11.816869 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3566 10:02:11.823749 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3567 10:02:11.826551 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3568 10:02:11.830129 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3569 10:02:11.833711 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3570 10:02:11.834184 ==
3571 10:02:11.836808 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 10:02:11.843251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 10:02:11.843713 ==
3574 10:02:11.844055 DQS Delay:
3575 10:02:11.846987 DQS0 = 0, DQS1 = 0
3576 10:02:11.847342 DQM Delay:
3577 10:02:11.849741 DQM0 = 120, DQM1 = 113
3578 10:02:11.850170 DQ Delay:
3579 10:02:11.853340 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =123
3580 10:02:11.856681 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3581 10:02:11.859639 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3582 10:02:11.862948 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3583 10:02:11.863206
3584 10:02:11.863389
3585 10:02:11.863557 ==
3586 10:02:11.866256 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 10:02:11.872580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 10:02:11.872782 ==
3589 10:02:11.872934
3590 10:02:11.873082
3591 10:02:11.873190 TX Vref Scan disable
3592 10:02:11.876446 == TX Byte 0 ==
3593 10:02:11.879703 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3594 10:02:11.886111 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3595 10:02:11.886229 == TX Byte 1 ==
3596 10:02:11.889823 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3597 10:02:11.896278 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3598 10:02:11.896372 ==
3599 10:02:11.899368 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 10:02:11.902608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 10:02:11.902694 ==
3602 10:02:11.914078 TX Vref=22, minBit 11, minWin=25, winSum=421
3603 10:02:11.917467 TX Vref=24, minBit 1, minWin=26, winSum=425
3604 10:02:11.921053 TX Vref=26, minBit 0, minWin=26, winSum=432
3605 10:02:11.924186 TX Vref=28, minBit 1, minWin=26, winSum=431
3606 10:02:11.927717 TX Vref=30, minBit 0, minWin=26, winSum=428
3607 10:02:11.934162 TX Vref=32, minBit 1, minWin=26, winSum=428
3608 10:02:11.937507 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 26
3609 10:02:11.937598
3610 10:02:11.940696 Final TX Range 1 Vref 26
3611 10:02:11.940806
3612 10:02:11.940884 ==
3613 10:02:11.943971 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 10:02:11.947680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 10:02:11.950699 ==
3616 10:02:11.950893
3617 10:02:11.950991
3618 10:02:11.951080 TX Vref Scan disable
3619 10:02:11.954279 == TX Byte 0 ==
3620 10:02:11.957766 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3621 10:02:11.964515 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3622 10:02:11.964751 == TX Byte 1 ==
3623 10:02:11.967913 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3624 10:02:11.974469 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3625 10:02:11.974758
3626 10:02:11.974933 [DATLAT]
3627 10:02:11.975093 Freq=1200, CH1 RK1
3628 10:02:11.975241
3629 10:02:11.977477 DATLAT Default: 0xd
3630 10:02:11.980818 0, 0xFFFF, sum = 0
3631 10:02:11.981115 1, 0xFFFF, sum = 0
3632 10:02:11.984135 2, 0xFFFF, sum = 0
3633 10:02:11.984537 3, 0xFFFF, sum = 0
3634 10:02:11.987633 4, 0xFFFF, sum = 0
3635 10:02:11.988089 5, 0xFFFF, sum = 0
3636 10:02:11.990834 6, 0xFFFF, sum = 0
3637 10:02:11.991368 7, 0xFFFF, sum = 0
3638 10:02:11.994318 8, 0xFFFF, sum = 0
3639 10:02:11.994851 9, 0xFFFF, sum = 0
3640 10:02:11.997623 10, 0xFFFF, sum = 0
3641 10:02:11.998199 11, 0xFFFF, sum = 0
3642 10:02:12.000634 12, 0x0, sum = 1
3643 10:02:12.001155 13, 0x0, sum = 2
3644 10:02:12.004187 14, 0x0, sum = 3
3645 10:02:12.004725 15, 0x0, sum = 4
3646 10:02:12.007406 best_step = 13
3647 10:02:12.007876
3648 10:02:12.008249 ==
3649 10:02:12.010382 Dram Type= 6, Freq= 0, CH_1, rank 1
3650 10:02:12.014083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3651 10:02:12.014656 ==
3652 10:02:12.017352 RX Vref Scan: 0
3653 10:02:12.017922
3654 10:02:12.018300 RX Vref 0 -> 0, step: 1
3655 10:02:12.018656
3656 10:02:12.020611 RX Delay -13 -> 252, step: 4
3657 10:02:12.027709 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3658 10:02:12.030454 iDelay=195, Bit 1, Center 116 (59 ~ 174) 116
3659 10:02:12.034362 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3660 10:02:12.036919 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3661 10:02:12.040683 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3662 10:02:12.046796 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3663 10:02:12.050477 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3664 10:02:12.053349 iDelay=195, Bit 7, Center 118 (59 ~ 178) 120
3665 10:02:12.056845 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3666 10:02:12.060054 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3667 10:02:12.067039 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3668 10:02:12.070704 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3669 10:02:12.073493 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3670 10:02:12.076964 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3671 10:02:12.083279 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3672 10:02:12.087230 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3673 10:02:12.087812 ==
3674 10:02:12.090187 Dram Type= 6, Freq= 0, CH_1, rank 1
3675 10:02:12.093312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3676 10:02:12.093890 ==
3677 10:02:12.094271 DQS Delay:
3678 10:02:12.096642 DQS0 = 0, DQS1 = 0
3679 10:02:12.097139 DQM Delay:
3680 10:02:12.099936 DQM0 = 120, DQM1 = 113
3681 10:02:12.100405 DQ Delay:
3682 10:02:12.103561 DQ0 =122, DQ1 =116, DQ2 =108, DQ3 =118
3683 10:02:12.106354 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =118
3684 10:02:12.109634 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3685 10:02:12.113136 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122
3686 10:02:12.116510
3687 10:02:12.117124
3688 10:02:12.123303 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps
3689 10:02:12.126227 CH1 RK1: MR19=403, MR18=CF0
3690 10:02:12.133128 CH1_RK1: MR19=0x403, MR18=0xCF0, DQSOSC=405, MR23=63, INC=39, DEC=26
3691 10:02:12.136062 [RxdqsGatingPostProcess] freq 1200
3692 10:02:12.139792 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3693 10:02:12.143234 best DQS0 dly(2T, 0.5T) = (0, 11)
3694 10:02:12.145961 best DQS1 dly(2T, 0.5T) = (0, 11)
3695 10:02:12.149320 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3696 10:02:12.152666 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3697 10:02:12.156135 best DQS0 dly(2T, 0.5T) = (0, 11)
3698 10:02:12.159799 best DQS1 dly(2T, 0.5T) = (0, 11)
3699 10:02:12.162771 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3700 10:02:12.165603 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3701 10:02:12.169226 Pre-setting of DQS Precalculation
3702 10:02:12.172543 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3703 10:02:12.182419 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3704 10:02:12.189520 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3705 10:02:12.190099
3706 10:02:12.190473
3707 10:02:12.192549 [Calibration Summary] 2400 Mbps
3708 10:02:12.193152 CH 0, Rank 0
3709 10:02:12.195807 SW Impedance : PASS
3710 10:02:12.196388 DUTY Scan : NO K
3711 10:02:12.199091 ZQ Calibration : PASS
3712 10:02:12.202697 Jitter Meter : NO K
3713 10:02:12.203273 CBT Training : PASS
3714 10:02:12.205906 Write leveling : PASS
3715 10:02:12.209210 RX DQS gating : PASS
3716 10:02:12.209796 RX DQ/DQS(RDDQC) : PASS
3717 10:02:12.212537 TX DQ/DQS : PASS
3718 10:02:12.213034 RX DATLAT : PASS
3719 10:02:12.216163 RX DQ/DQS(Engine): PASS
3720 10:02:12.219030 TX OE : NO K
3721 10:02:12.219608 All Pass.
3722 10:02:12.219983
3723 10:02:12.220330 CH 0, Rank 1
3724 10:02:12.222326 SW Impedance : PASS
3725 10:02:12.226241 DUTY Scan : NO K
3726 10:02:12.226823 ZQ Calibration : PASS
3727 10:02:12.229250 Jitter Meter : NO K
3728 10:02:12.231952 CBT Training : PASS
3729 10:02:12.232423 Write leveling : PASS
3730 10:02:12.235779 RX DQS gating : PASS
3731 10:02:12.239118 RX DQ/DQS(RDDQC) : PASS
3732 10:02:12.239696 TX DQ/DQS : PASS
3733 10:02:12.242515 RX DATLAT : PASS
3734 10:02:12.245447 RX DQ/DQS(Engine): PASS
3735 10:02:12.245921 TX OE : NO K
3736 10:02:12.248723 All Pass.
3737 10:02:12.249241
3738 10:02:12.249611 CH 1, Rank 0
3739 10:02:12.252029 SW Impedance : PASS
3740 10:02:12.252498 DUTY Scan : NO K
3741 10:02:12.255520 ZQ Calibration : PASS
3742 10:02:12.258874 Jitter Meter : NO K
3743 10:02:12.259444 CBT Training : PASS
3744 10:02:12.262355 Write leveling : PASS
3745 10:02:12.265522 RX DQS gating : PASS
3746 10:02:12.265998 RX DQ/DQS(RDDQC) : PASS
3747 10:02:12.268844 TX DQ/DQS : PASS
3748 10:02:12.272146 RX DATLAT : PASS
3749 10:02:12.272802 RX DQ/DQS(Engine): PASS
3750 10:02:12.275063 TX OE : NO K
3751 10:02:12.275649 All Pass.
3752 10:02:12.276021
3753 10:02:12.278381 CH 1, Rank 1
3754 10:02:12.278880 SW Impedance : PASS
3755 10:02:12.281837 DUTY Scan : NO K
3756 10:02:12.282419 ZQ Calibration : PASS
3757 10:02:12.285303 Jitter Meter : NO K
3758 10:02:12.288338 CBT Training : PASS
3759 10:02:12.288834 Write leveling : PASS
3760 10:02:12.292022 RX DQS gating : PASS
3761 10:02:12.295065 RX DQ/DQS(RDDQC) : PASS
3762 10:02:12.295645 TX DQ/DQS : PASS
3763 10:02:12.298604 RX DATLAT : PASS
3764 10:02:12.301612 RX DQ/DQS(Engine): PASS
3765 10:02:12.302084 TX OE : NO K
3766 10:02:12.305134 All Pass.
3767 10:02:12.305704
3768 10:02:12.306080 DramC Write-DBI off
3769 10:02:12.308347 PER_BANK_REFRESH: Hybrid Mode
3770 10:02:12.311662 TX_TRACKING: ON
3771 10:02:12.318320 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3772 10:02:12.321683 [FAST_K] Save calibration result to emmc
3773 10:02:12.325087 dramc_set_vcore_voltage set vcore to 650000
3774 10:02:12.328199 Read voltage for 600, 5
3775 10:02:12.328797 Vio18 = 0
3776 10:02:12.331510 Vcore = 650000
3777 10:02:12.332086 Vdram = 0
3778 10:02:12.332457 Vddq = 0
3779 10:02:12.334785 Vmddr = 0
3780 10:02:12.337684 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3781 10:02:12.344954 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3782 10:02:12.345524 MEM_TYPE=3, freq_sel=19
3783 10:02:12.347559 sv_algorithm_assistance_LP4_1600
3784 10:02:12.354466 ============ PULL DRAM RESETB DOWN ============
3785 10:02:12.357777 ========== PULL DRAM RESETB DOWN end =========
3786 10:02:12.360931 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3787 10:02:12.364357 ===================================
3788 10:02:12.368223 LPDDR4 DRAM CONFIGURATION
3789 10:02:12.370994 ===================================
3790 10:02:12.374507 EX_ROW_EN[0] = 0x0
3791 10:02:12.375080 EX_ROW_EN[1] = 0x0
3792 10:02:12.377271 LP4Y_EN = 0x0
3793 10:02:12.377780 WORK_FSP = 0x0
3794 10:02:12.381143 WL = 0x2
3795 10:02:12.381729 RL = 0x2
3796 10:02:12.384509 BL = 0x2
3797 10:02:12.385076 RPST = 0x0
3798 10:02:12.387610 RD_PRE = 0x0
3799 10:02:12.388075 WR_PRE = 0x1
3800 10:02:12.390945 WR_PST = 0x0
3801 10:02:12.391411 DBI_WR = 0x0
3802 10:02:12.394223 DBI_RD = 0x0
3803 10:02:12.394783 OTF = 0x1
3804 10:02:12.397594 ===================================
3805 10:02:12.400521 ===================================
3806 10:02:12.404622 ANA top config
3807 10:02:12.407560 ===================================
3808 10:02:12.410759 DLL_ASYNC_EN = 0
3809 10:02:12.411298 ALL_SLAVE_EN = 1
3810 10:02:12.414057 NEW_RANK_MODE = 1
3811 10:02:12.417267 DLL_IDLE_MODE = 1
3812 10:02:12.420689 LP45_APHY_COMB_EN = 1
3813 10:02:12.421300 TX_ODT_DIS = 1
3814 10:02:12.423903 NEW_8X_MODE = 1
3815 10:02:12.427510 ===================================
3816 10:02:12.430770 ===================================
3817 10:02:12.434044 data_rate = 1200
3818 10:02:12.437488 CKR = 1
3819 10:02:12.440352 DQ_P2S_RATIO = 8
3820 10:02:12.443929 ===================================
3821 10:02:12.447384 CA_P2S_RATIO = 8
3822 10:02:12.447947 DQ_CA_OPEN = 0
3823 10:02:12.450534 DQ_SEMI_OPEN = 0
3824 10:02:12.453944 CA_SEMI_OPEN = 0
3825 10:02:12.457271 CA_FULL_RATE = 0
3826 10:02:12.461032 DQ_CKDIV4_EN = 1
3827 10:02:12.463941 CA_CKDIV4_EN = 1
3828 10:02:12.464510 CA_PREDIV_EN = 0
3829 10:02:12.467172 PH8_DLY = 0
3830 10:02:12.470942 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3831 10:02:12.474203 DQ_AAMCK_DIV = 4
3832 10:02:12.477418 CA_AAMCK_DIV = 4
3833 10:02:12.480243 CA_ADMCK_DIV = 4
3834 10:02:12.480713 DQ_TRACK_CA_EN = 0
3835 10:02:12.483629 CA_PICK = 600
3836 10:02:12.487190 CA_MCKIO = 600
3837 10:02:12.490362 MCKIO_SEMI = 0
3838 10:02:12.493736 PLL_FREQ = 2288
3839 10:02:12.496881 DQ_UI_PI_RATIO = 32
3840 10:02:12.500108 CA_UI_PI_RATIO = 0
3841 10:02:12.503646 ===================================
3842 10:02:12.507209 ===================================
3843 10:02:12.507825 memory_type:LPDDR4
3844 10:02:12.510102 GP_NUM : 10
3845 10:02:12.513323 SRAM_EN : 1
3846 10:02:12.513871 MD32_EN : 0
3847 10:02:12.516669 ===================================
3848 10:02:12.520050 [ANA_INIT] >>>>>>>>>>>>>>
3849 10:02:12.523634 <<<<<< [CONFIGURE PHASE]: ANA_TX
3850 10:02:12.526759 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3851 10:02:12.530435 ===================================
3852 10:02:12.533294 data_rate = 1200,PCW = 0X5800
3853 10:02:12.536745 ===================================
3854 10:02:12.539901 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3855 10:02:12.543192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3856 10:02:12.550011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3857 10:02:12.553079 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3858 10:02:12.556502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3859 10:02:12.560187 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3860 10:02:12.563141 [ANA_INIT] flow start
3861 10:02:12.566385 [ANA_INIT] PLL >>>>>>>>
3862 10:02:12.566950 [ANA_INIT] PLL <<<<<<<<
3863 10:02:12.569580 [ANA_INIT] MIDPI >>>>>>>>
3864 10:02:12.572838 [ANA_INIT] MIDPI <<<<<<<<
3865 10:02:12.576160 [ANA_INIT] DLL >>>>>>>>
3866 10:02:12.576631 [ANA_INIT] flow end
3867 10:02:12.579336 ============ LP4 DIFF to SE enter ============
3868 10:02:12.586150 ============ LP4 DIFF to SE exit ============
3869 10:02:12.586721 [ANA_INIT] <<<<<<<<<<<<<
3870 10:02:12.589296 [Flow] Enable top DCM control >>>>>
3871 10:02:12.592942 [Flow] Enable top DCM control <<<<<
3872 10:02:12.596499 Enable DLL master slave shuffle
3873 10:02:12.602665 ==============================================================
3874 10:02:12.603144 Gating Mode config
3875 10:02:12.609409 ==============================================================
3876 10:02:12.612623 Config description:
3877 10:02:12.622821 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3878 10:02:12.629341 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3879 10:02:12.632508 SELPH_MODE 0: By rank 1: By Phase
3880 10:02:12.639237 ==============================================================
3881 10:02:12.642798 GAT_TRACK_EN = 1
3882 10:02:12.645455 RX_GATING_MODE = 2
3883 10:02:12.645929 RX_GATING_TRACK_MODE = 2
3884 10:02:12.649217 SELPH_MODE = 1
3885 10:02:12.652511 PICG_EARLY_EN = 1
3886 10:02:12.656173 VALID_LAT_VALUE = 1
3887 10:02:12.662626 ==============================================================
3888 10:02:12.665881 Enter into Gating configuration >>>>
3889 10:02:12.669156 Exit from Gating configuration <<<<
3890 10:02:12.672272 Enter into DVFS_PRE_config >>>>>
3891 10:02:12.682038 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3892 10:02:12.685439 Exit from DVFS_PRE_config <<<<<
3893 10:02:12.688673 Enter into PICG configuration >>>>
3894 10:02:12.691974 Exit from PICG configuration <<<<
3895 10:02:12.695404 [RX_INPUT] configuration >>>>>
3896 10:02:12.698433 [RX_INPUT] configuration <<<<<
3897 10:02:12.701905 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3898 10:02:12.708689 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3899 10:02:12.715237 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3900 10:02:12.721586 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3901 10:02:12.728651 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3902 10:02:12.731767 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3903 10:02:12.738808 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3904 10:02:12.741463 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3905 10:02:12.745140 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3906 10:02:12.748540 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3907 10:02:12.754963 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3908 10:02:12.758381 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3909 10:02:12.761512 ===================================
3910 10:02:12.764993 LPDDR4 DRAM CONFIGURATION
3911 10:02:12.768126 ===================================
3912 10:02:12.768698 EX_ROW_EN[0] = 0x0
3913 10:02:12.771603 EX_ROW_EN[1] = 0x0
3914 10:02:12.772171 LP4Y_EN = 0x0
3915 10:02:12.775035 WORK_FSP = 0x0
3916 10:02:12.775603 WL = 0x2
3917 10:02:12.777767 RL = 0x2
3918 10:02:12.778240 BL = 0x2
3919 10:02:12.781418 RPST = 0x0
3920 10:02:12.782115 RD_PRE = 0x0
3921 10:02:12.785007 WR_PRE = 0x1
3922 10:02:12.785569 WR_PST = 0x0
3923 10:02:12.788035 DBI_WR = 0x0
3924 10:02:12.791038 DBI_RD = 0x0
3925 10:02:12.791605 OTF = 0x1
3926 10:02:12.795169 ===================================
3927 10:02:12.798537 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3928 10:02:12.801336 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3929 10:02:12.808110 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3930 10:02:12.811156 ===================================
3931 10:02:12.814481 LPDDR4 DRAM CONFIGURATION
3932 10:02:12.817520 ===================================
3933 10:02:12.818085 EX_ROW_EN[0] = 0x10
3934 10:02:12.820996 EX_ROW_EN[1] = 0x0
3935 10:02:12.821565 LP4Y_EN = 0x0
3936 10:02:12.824504 WORK_FSP = 0x0
3937 10:02:12.825019 WL = 0x2
3938 10:02:12.827151 RL = 0x2
3939 10:02:12.827623 BL = 0x2
3940 10:02:12.831179 RPST = 0x0
3941 10:02:12.831742 RD_PRE = 0x0
3942 10:02:12.834032 WR_PRE = 0x1
3943 10:02:12.834503 WR_PST = 0x0
3944 10:02:12.837720 DBI_WR = 0x0
3945 10:02:12.840868 DBI_RD = 0x0
3946 10:02:12.841352 OTF = 0x1
3947 10:02:12.844643 ===================================
3948 10:02:12.850839 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3949 10:02:12.854432 nWR fixed to 30
3950 10:02:12.857913 [ModeRegInit_LP4] CH0 RK0
3951 10:02:12.858484 [ModeRegInit_LP4] CH0 RK1
3952 10:02:12.861059 [ModeRegInit_LP4] CH1 RK0
3953 10:02:12.864299 [ModeRegInit_LP4] CH1 RK1
3954 10:02:12.864913 match AC timing 17
3955 10:02:12.871078 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3956 10:02:12.874027 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3957 10:02:12.877619 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3958 10:02:12.884350 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3959 10:02:12.887408 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3960 10:02:12.887884 ==
3961 10:02:12.890640 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 10:02:12.893972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 10:02:12.894547 ==
3964 10:02:12.900452 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3965 10:02:12.906865 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3966 10:02:12.910186 [CA 0] Center 36 (5~67) winsize 63
3967 10:02:12.913353 [CA 1] Center 36 (6~67) winsize 62
3968 10:02:12.917069 [CA 2] Center 34 (4~65) winsize 62
3969 10:02:12.920039 [CA 3] Center 34 (3~65) winsize 63
3970 10:02:12.923862 [CA 4] Center 33 (3~64) winsize 62
3971 10:02:12.926764 [CA 5] Center 33 (2~64) winsize 63
3972 10:02:12.927238
3973 10:02:12.930579 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3974 10:02:12.931154
3975 10:02:12.933704 [CATrainingPosCal] consider 1 rank data
3976 10:02:12.937244 u2DelayCellTimex100 = 270/100 ps
3977 10:02:12.939954 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3978 10:02:12.943443 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3979 10:02:12.946729 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3980 10:02:12.950158 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3981 10:02:12.956948 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3982 10:02:12.960344 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3983 10:02:12.960948
3984 10:02:12.963582 CA PerBit enable=1, Macro0, CA PI delay=33
3985 10:02:12.964149
3986 10:02:12.966701 [CBTSetCACLKResult] CA Dly = 33
3987 10:02:12.967266 CS Dly: 4 (0~35)
3988 10:02:12.967640 ==
3989 10:02:12.970205 Dram Type= 6, Freq= 0, CH_0, rank 1
3990 10:02:12.976755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 10:02:12.977368 ==
3992 10:02:12.979865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3993 10:02:12.986412 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3994 10:02:12.989999 [CA 0] Center 36 (6~67) winsize 62
3995 10:02:12.992975 [CA 1] Center 36 (6~67) winsize 62
3996 10:02:12.996499 [CA 2] Center 35 (4~66) winsize 63
3997 10:02:13.000033 [CA 3] Center 35 (4~66) winsize 63
3998 10:02:13.003094 [CA 4] Center 34 (3~65) winsize 63
3999 10:02:13.006629 [CA 5] Center 34 (3~65) winsize 63
4000 10:02:13.007197
4001 10:02:13.009095 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4002 10:02:13.009579
4003 10:02:13.012626 [CATrainingPosCal] consider 2 rank data
4004 10:02:13.016075 u2DelayCellTimex100 = 270/100 ps
4005 10:02:13.019440 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4006 10:02:13.026274 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4007 10:02:13.029254 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4008 10:02:13.032480 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4009 10:02:13.035755 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4010 10:02:13.039737 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4011 10:02:13.040303
4012 10:02:13.042418 CA PerBit enable=1, Macro0, CA PI delay=33
4013 10:02:13.042890
4014 10:02:13.046419 [CBTSetCACLKResult] CA Dly = 33
4015 10:02:13.049217 CS Dly: 5 (0~37)
4016 10:02:13.049735
4017 10:02:13.052672 ----->DramcWriteLeveling(PI) begin...
4018 10:02:13.053311 ==
4019 10:02:13.056158 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 10:02:13.059201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 10:02:13.059772 ==
4022 10:02:13.062439 Write leveling (Byte 0): 35 => 35
4023 10:02:13.065438 Write leveling (Byte 1): 31 => 31
4024 10:02:13.069101 DramcWriteLeveling(PI) end<-----
4025 10:02:13.069667
4026 10:02:13.070036 ==
4027 10:02:13.073161 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 10:02:13.076079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 10:02:13.076650 ==
4030 10:02:13.078971 [Gating] SW mode calibration
4031 10:02:13.085664 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4032 10:02:13.092477 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4033 10:02:13.095691 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 10:02:13.099361 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4035 10:02:13.105900 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4036 10:02:13.108696 0 9 12 | B1->B0 | 3232 3030 | 1 0 | (0 0) (0 1)
4037 10:02:13.112250 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4038 10:02:13.118871 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 10:02:13.122451 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 10:02:13.125403 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 10:02:13.131912 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 10:02:13.135264 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 10:02:13.138091 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 10:02:13.145120 0 10 12 | B1->B0 | 2626 3c3c | 0 0 | (0 0) (0 0)
4045 10:02:13.148205 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
4046 10:02:13.151916 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 10:02:13.158682 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 10:02:13.161318 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 10:02:13.165093 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 10:02:13.171568 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 10:02:13.174999 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 10:02:13.177662 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4053 10:02:13.184879 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4054 10:02:13.187726 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 10:02:13.190850 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 10:02:13.197669 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 10:02:13.201048 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 10:02:13.204528 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 10:02:13.210800 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 10:02:13.214073 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 10:02:13.217872 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 10:02:13.224342 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 10:02:13.227330 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 10:02:13.230973 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 10:02:13.237379 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 10:02:13.240500 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 10:02:13.243504 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 10:02:13.250214 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4069 10:02:13.253540 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4070 10:02:13.256669 Total UI for P1: 0, mck2ui 16
4071 10:02:13.260123 best dqsien dly found for B0: ( 0, 13, 12)
4072 10:02:13.263405 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 10:02:13.266783 Total UI for P1: 0, mck2ui 16
4074 10:02:13.270182 best dqsien dly found for B1: ( 0, 13, 16)
4075 10:02:13.273719 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4076 10:02:13.276932 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4077 10:02:13.277493
4078 10:02:13.283807 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4079 10:02:13.286936 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4080 10:02:13.289942 [Gating] SW calibration Done
4081 10:02:13.290514 ==
4082 10:02:13.293558 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 10:02:13.297143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 10:02:13.297724 ==
4085 10:02:13.298098 RX Vref Scan: 0
4086 10:02:13.298448
4087 10:02:13.299632 RX Vref 0 -> 0, step: 1
4088 10:02:13.300096
4089 10:02:13.303412 RX Delay -230 -> 252, step: 16
4090 10:02:13.306564 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4091 10:02:13.312954 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4092 10:02:13.316730 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4093 10:02:13.319938 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4094 10:02:13.323061 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4095 10:02:13.326557 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4096 10:02:13.332959 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4097 10:02:13.336364 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4098 10:02:13.340095 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4099 10:02:13.342757 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4100 10:02:13.349654 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4101 10:02:13.352557 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4102 10:02:13.356240 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4103 10:02:13.359297 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4104 10:02:13.365852 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4105 10:02:13.369175 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4106 10:02:13.369643 ==
4107 10:02:13.372822 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 10:02:13.376115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 10:02:13.376706 ==
4110 10:02:13.379407 DQS Delay:
4111 10:02:13.379971 DQS0 = 0, DQS1 = 0
4112 10:02:13.380346 DQM Delay:
4113 10:02:13.382750 DQM0 = 52, DQM1 = 41
4114 10:02:13.383325 DQ Delay:
4115 10:02:13.385975 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4116 10:02:13.389319 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4117 10:02:13.392305 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4118 10:02:13.395656 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4119 10:02:13.396221
4120 10:02:13.396592
4121 10:02:13.396993 ==
4122 10:02:13.399293 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 10:02:13.405434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 10:02:13.406007 ==
4125 10:02:13.406381
4126 10:02:13.406724
4127 10:02:13.407050 TX Vref Scan disable
4128 10:02:13.409227 == TX Byte 0 ==
4129 10:02:13.412817 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4130 10:02:13.419615 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4131 10:02:13.420189 == TX Byte 1 ==
4132 10:02:13.422749 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4133 10:02:13.429109 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4134 10:02:13.429668 ==
4135 10:02:13.432474 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 10:02:13.435669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 10:02:13.436233 ==
4138 10:02:13.436607
4139 10:02:13.437014
4140 10:02:13.439081 TX Vref Scan disable
4141 10:02:13.442185 == TX Byte 0 ==
4142 10:02:13.445987 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4143 10:02:13.449172 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4144 10:02:13.452915 == TX Byte 1 ==
4145 10:02:13.455632 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4146 10:02:13.459587 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4147 10:02:13.460284
4148 10:02:13.460670 [DATLAT]
4149 10:02:13.462273 Freq=600, CH0 RK0
4150 10:02:13.462742
4151 10:02:13.463188 DATLAT Default: 0x9
4152 10:02:13.465637 0, 0xFFFF, sum = 0
4153 10:02:13.468941 1, 0xFFFF, sum = 0
4154 10:02:13.469417 2, 0xFFFF, sum = 0
4155 10:02:13.472683 3, 0xFFFF, sum = 0
4156 10:02:13.473297 4, 0xFFFF, sum = 0
4157 10:02:13.476308 5, 0xFFFF, sum = 0
4158 10:02:13.476912 6, 0xFFFF, sum = 0
4159 10:02:13.478844 7, 0xFFFF, sum = 0
4160 10:02:13.479423 8, 0x0, sum = 1
4161 10:02:13.482136 9, 0x0, sum = 2
4162 10:02:13.482612 10, 0x0, sum = 3
4163 10:02:13.482990 11, 0x0, sum = 4
4164 10:02:13.485596 best_step = 9
4165 10:02:13.486060
4166 10:02:13.486424 ==
4167 10:02:13.488888 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 10:02:13.492243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 10:02:13.492858 ==
4170 10:02:13.495753 RX Vref Scan: 1
4171 10:02:13.496318
4172 10:02:13.496688 RX Vref 0 -> 0, step: 1
4173 10:02:13.499457
4174 10:02:13.500024 RX Delay -179 -> 252, step: 8
4175 10:02:13.500391
4176 10:02:13.502083 Set Vref, RX VrefLevel [Byte0]: 59
4177 10:02:13.505073 [Byte1]: 49
4178 10:02:13.509873
4179 10:02:13.510453 Final RX Vref Byte 0 = 59 to rank0
4180 10:02:13.512818 Final RX Vref Byte 1 = 49 to rank0
4181 10:02:13.516387 Final RX Vref Byte 0 = 59 to rank1
4182 10:02:13.519969 Final RX Vref Byte 1 = 49 to rank1==
4183 10:02:13.523596 Dram Type= 6, Freq= 0, CH_0, rank 0
4184 10:02:13.529932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 10:02:13.530539 ==
4186 10:02:13.531026 DQS Delay:
4187 10:02:13.532591 DQS0 = 0, DQS1 = 0
4188 10:02:13.533117 DQM Delay:
4189 10:02:13.533589 DQM0 = 48, DQM1 = 39
4190 10:02:13.535949 DQ Delay:
4191 10:02:13.539680 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4192 10:02:13.542661 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4193 10:02:13.545908 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4194 10:02:13.549381 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4195 10:02:13.549966
4196 10:02:13.550446
4197 10:02:13.555955 [DQSOSCAuto] RK0, (LSB)MR18= 0x5953, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4198 10:02:13.559588 CH0 RK0: MR19=808, MR18=5953
4199 10:02:13.566087 CH0_RK0: MR19=0x808, MR18=0x5953, DQSOSC=393, MR23=63, INC=169, DEC=113
4200 10:02:13.566724
4201 10:02:13.569688 ----->DramcWriteLeveling(PI) begin...
4202 10:02:13.570280 ==
4203 10:02:13.572548 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 10:02:13.576059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 10:02:13.576646 ==
4206 10:02:13.579271 Write leveling (Byte 0): 33 => 33
4207 10:02:13.582446 Write leveling (Byte 1): 29 => 29
4208 10:02:13.585505 DramcWriteLeveling(PI) end<-----
4209 10:02:13.586085
4210 10:02:13.586567 ==
4211 10:02:13.589050 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 10:02:13.592449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 10:02:13.595311 ==
4214 10:02:13.595885 [Gating] SW mode calibration
4215 10:02:13.605639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4216 10:02:13.608915 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4217 10:02:13.612346 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4218 10:02:13.619276 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4219 10:02:13.622225 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 10:02:13.625703 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
4221 10:02:13.631769 0 9 16 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
4222 10:02:13.635339 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 10:02:13.638712 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 10:02:13.645158 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 10:02:13.648468 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 10:02:13.652271 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 10:02:13.658949 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 10:02:13.662312 0 10 12 | B1->B0 | 2e2e 2a2a | 1 1 | (0 0) (0 0)
4229 10:02:13.665684 0 10 16 | B1->B0 | 4242 4444 | 0 0 | (0 0) (0 0)
4230 10:02:13.672049 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 10:02:13.674842 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 10:02:13.678260 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 10:02:13.685064 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 10:02:13.688216 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 10:02:13.691621 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 10:02:13.698096 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4237 10:02:13.701756 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4238 10:02:13.705010 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 10:02:13.711352 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 10:02:13.714951 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 10:02:13.717985 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 10:02:13.724691 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 10:02:13.727876 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 10:02:13.731561 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 10:02:13.737944 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 10:02:13.741153 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 10:02:13.744522 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 10:02:13.751147 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 10:02:13.754224 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 10:02:13.757708 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 10:02:13.764082 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 10:02:13.767922 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4253 10:02:13.770807 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4254 10:02:13.774066 Total UI for P1: 0, mck2ui 16
4255 10:02:13.777631 best dqsien dly found for B1: ( 0, 13, 14)
4256 10:02:13.784020 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 10:02:13.784583 Total UI for P1: 0, mck2ui 16
4258 10:02:13.787126 best dqsien dly found for B0: ( 0, 13, 14)
4259 10:02:13.794022 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4260 10:02:13.797291 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4261 10:02:13.797892
4262 10:02:13.800416 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4263 10:02:13.803470 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4264 10:02:13.806973 [Gating] SW calibration Done
4265 10:02:13.807547 ==
4266 10:02:13.810168 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 10:02:13.813419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 10:02:13.813921 ==
4269 10:02:13.817344 RX Vref Scan: 0
4270 10:02:13.817818
4271 10:02:13.818193 RX Vref 0 -> 0, step: 1
4272 10:02:13.818541
4273 10:02:13.820682 RX Delay -230 -> 252, step: 16
4274 10:02:13.826827 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4275 10:02:13.830357 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4276 10:02:13.833667 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4277 10:02:13.836815 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4278 10:02:13.839787 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4279 10:02:13.846612 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4280 10:02:13.850454 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4281 10:02:13.853642 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4282 10:02:13.856913 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4283 10:02:13.862997 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4284 10:02:13.866661 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4285 10:02:13.869988 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4286 10:02:13.873610 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4287 10:02:13.880098 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4288 10:02:13.883132 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4289 10:02:13.886910 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4290 10:02:13.887478 ==
4291 10:02:13.890078 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 10:02:13.893537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 10:02:13.894114 ==
4294 10:02:13.896804 DQS Delay:
4295 10:02:13.897293 DQS0 = 0, DQS1 = 0
4296 10:02:13.900025 DQM Delay:
4297 10:02:13.900590 DQM0 = 47, DQM1 = 42
4298 10:02:13.901090 DQ Delay:
4299 10:02:13.903237 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4300 10:02:13.906525 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4301 10:02:13.909718 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4302 10:02:13.913034 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4303 10:02:13.913509
4304 10:02:13.913902
4305 10:02:13.915940 ==
4306 10:02:13.919911 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 10:02:13.923032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 10:02:13.923621 ==
4309 10:02:13.924004
4310 10:02:13.924351
4311 10:02:13.926042 TX Vref Scan disable
4312 10:02:13.926513 == TX Byte 0 ==
4313 10:02:13.933125 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4314 10:02:13.936044 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4315 10:02:13.936613 == TX Byte 1 ==
4316 10:02:13.942935 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4317 10:02:13.946494 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4318 10:02:13.946970 ==
4319 10:02:13.949502 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 10:02:13.952571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 10:02:13.953175 ==
4322 10:02:13.953553
4323 10:02:13.953899
4324 10:02:13.955922 TX Vref Scan disable
4325 10:02:13.958976 == TX Byte 0 ==
4326 10:02:13.962403 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4327 10:02:13.965557 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4328 10:02:13.969293 == TX Byte 1 ==
4329 10:02:13.972708 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4330 10:02:13.975975 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4331 10:02:13.976544
4332 10:02:13.979769 [DATLAT]
4333 10:02:13.980337 Freq=600, CH0 RK1
4334 10:02:13.980715
4335 10:02:13.982290 DATLAT Default: 0x9
4336 10:02:13.982761 0, 0xFFFF, sum = 0
4337 10:02:13.985500 1, 0xFFFF, sum = 0
4338 10:02:13.985981 2, 0xFFFF, sum = 0
4339 10:02:13.989335 3, 0xFFFF, sum = 0
4340 10:02:13.989912 4, 0xFFFF, sum = 0
4341 10:02:13.992340 5, 0xFFFF, sum = 0
4342 10:02:13.995662 6, 0xFFFF, sum = 0
4343 10:02:13.996238 7, 0xFFFF, sum = 0
4344 10:02:13.996620 8, 0x0, sum = 1
4345 10:02:13.999045 9, 0x0, sum = 2
4346 10:02:13.999651 10, 0x0, sum = 3
4347 10:02:14.002597 11, 0x0, sum = 4
4348 10:02:14.003145 best_step = 9
4349 10:02:14.003610
4350 10:02:14.004152 ==
4351 10:02:14.005388 Dram Type= 6, Freq= 0, CH_0, rank 1
4352 10:02:14.011805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 10:02:14.012362 ==
4354 10:02:14.012740 RX Vref Scan: 0
4355 10:02:14.013123
4356 10:02:14.015302 RX Vref 0 -> 0, step: 1
4357 10:02:14.015773
4358 10:02:14.018545 RX Delay -179 -> 252, step: 8
4359 10:02:14.022157 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4360 10:02:14.028552 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4361 10:02:14.031591 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4362 10:02:14.035175 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4363 10:02:14.038310 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4364 10:02:14.041608 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4365 10:02:14.048346 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4366 10:02:14.051979 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4367 10:02:14.054804 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4368 10:02:14.058520 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4369 10:02:14.064897 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4370 10:02:14.068429 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4371 10:02:14.071663 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4372 10:02:14.075387 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4373 10:02:14.077970 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4374 10:02:14.084732 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4375 10:02:14.085315 ==
4376 10:02:14.088385 Dram Type= 6, Freq= 0, CH_0, rank 1
4377 10:02:14.091928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 10:02:14.092487 ==
4379 10:02:14.092893 DQS Delay:
4380 10:02:14.095013 DQS0 = 0, DQS1 = 0
4381 10:02:14.095563 DQM Delay:
4382 10:02:14.098914 DQM0 = 48, DQM1 = 40
4383 10:02:14.099470 DQ Delay:
4384 10:02:14.101591 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4385 10:02:14.104472 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4386 10:02:14.108912 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4387 10:02:14.111260 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4388 10:02:14.111720
4389 10:02:14.112108
4390 10:02:14.121363 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a37, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
4391 10:02:14.121832 CH0 RK1: MR19=808, MR18=6A37
4392 10:02:14.128241 CH0_RK1: MR19=0x808, MR18=0x6A37, DQSOSC=389, MR23=63, INC=173, DEC=115
4393 10:02:14.131391 [RxdqsGatingPostProcess] freq 600
4394 10:02:14.138055 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4395 10:02:14.141585 Pre-setting of DQS Precalculation
4396 10:02:14.144610 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4397 10:02:14.145224 ==
4398 10:02:14.147734 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 10:02:14.151267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 10:02:14.154247 ==
4401 10:02:14.157746 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4402 10:02:14.164705 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4403 10:02:14.167958 [CA 0] Center 35 (5~66) winsize 62
4404 10:02:14.170963 [CA 1] Center 35 (5~66) winsize 62
4405 10:02:14.174199 [CA 2] Center 34 (3~65) winsize 63
4406 10:02:14.178199 [CA 3] Center 33 (3~64) winsize 62
4407 10:02:14.181139 [CA 4] Center 34 (3~65) winsize 63
4408 10:02:14.183796 [CA 5] Center 33 (3~64) winsize 62
4409 10:02:14.184252
4410 10:02:14.187930 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4411 10:02:14.188483
4412 10:02:14.191057 [CATrainingPosCal] consider 1 rank data
4413 10:02:14.193897 u2DelayCellTimex100 = 270/100 ps
4414 10:02:14.197517 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4415 10:02:14.200499 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4416 10:02:14.207297 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4417 10:02:14.210986 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 10:02:14.213728 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4419 10:02:14.216681 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4420 10:02:14.217235
4421 10:02:14.220740 CA PerBit enable=1, Macro0, CA PI delay=33
4422 10:02:14.221406
4423 10:02:14.223525 [CBTSetCACLKResult] CA Dly = 33
4424 10:02:14.224094 CS Dly: 5 (0~36)
4425 10:02:14.226798 ==
4426 10:02:14.227312 Dram Type= 6, Freq= 0, CH_1, rank 1
4427 10:02:14.233090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 10:02:14.233692 ==
4429 10:02:14.236805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4430 10:02:14.243590 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4431 10:02:14.246970 [CA 0] Center 35 (5~66) winsize 62
4432 10:02:14.250313 [CA 1] Center 35 (5~66) winsize 62
4433 10:02:14.253527 [CA 2] Center 34 (4~65) winsize 62
4434 10:02:14.257205 [CA 3] Center 34 (4~65) winsize 62
4435 10:02:14.260442 [CA 4] Center 34 (4~65) winsize 62
4436 10:02:14.263871 [CA 5] Center 34 (4~64) winsize 61
4437 10:02:14.264447
4438 10:02:14.267300 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4439 10:02:14.267868
4440 10:02:14.270264 [CATrainingPosCal] consider 2 rank data
4441 10:02:14.273503 u2DelayCellTimex100 = 270/100 ps
4442 10:02:14.277024 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4443 10:02:14.283225 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4444 10:02:14.286724 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4445 10:02:14.289754 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4446 10:02:14.293400 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4447 10:02:14.296532 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4448 10:02:14.297127
4449 10:02:14.300026 CA PerBit enable=1, Macro0, CA PI delay=34
4450 10:02:14.300596
4451 10:02:14.303353 [CBTSetCACLKResult] CA Dly = 34
4452 10:02:14.304120 CS Dly: 5 (0~36)
4453 10:02:14.306437
4454 10:02:14.309678 ----->DramcWriteLeveling(PI) begin...
4455 10:02:14.310253 ==
4456 10:02:14.312897 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 10:02:14.316565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 10:02:14.317065 ==
4459 10:02:14.320380 Write leveling (Byte 0): 29 => 29
4460 10:02:14.323009 Write leveling (Byte 1): 30 => 30
4461 10:02:14.326256 DramcWriteLeveling(PI) end<-----
4462 10:02:14.326821
4463 10:02:14.327190 ==
4464 10:02:14.329897 Dram Type= 6, Freq= 0, CH_1, rank 0
4465 10:02:14.332930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 10:02:14.333400 ==
4467 10:02:14.336338 [Gating] SW mode calibration
4468 10:02:14.342809 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4469 10:02:14.349424 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4470 10:02:14.353127 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4471 10:02:14.356346 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4472 10:02:14.362716 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4473 10:02:14.366221 0 9 12 | B1->B0 | 2f2f 2e2e | 0 0 | (1 0) (1 1)
4474 10:02:14.369109 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 10:02:14.375689 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 10:02:14.379297 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 10:02:14.382346 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 10:02:14.389174 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 10:02:14.392637 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 10:02:14.395942 0 10 8 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
4481 10:02:14.402600 0 10 12 | B1->B0 | 3737 3c3c | 1 0 | (0 0) (0 0)
4482 10:02:14.405704 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 10:02:14.409309 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 10:02:14.415296 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 10:02:14.418739 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 10:02:14.422196 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 10:02:14.429048 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 10:02:14.432275 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 10:02:14.435480 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 10:02:14.442267 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 10:02:14.445300 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 10:02:14.448546 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 10:02:14.454995 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 10:02:14.458119 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 10:02:14.461970 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 10:02:14.468862 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 10:02:14.471554 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 10:02:14.475189 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 10:02:14.482084 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 10:02:14.484549 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 10:02:14.488595 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 10:02:14.494941 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 10:02:14.498420 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 10:02:14.501299 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 10:02:14.507785 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 10:02:14.508352 Total UI for P1: 0, mck2ui 16
4507 10:02:14.514283 best dqsien dly found for B0: ( 0, 13, 10)
4508 10:02:14.514840 Total UI for P1: 0, mck2ui 16
4509 10:02:14.520831 best dqsien dly found for B1: ( 0, 13, 10)
4510 10:02:14.524134 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4511 10:02:14.528051 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4512 10:02:14.528619
4513 10:02:14.530905 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4514 10:02:14.534299 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4515 10:02:14.537572 [Gating] SW calibration Done
4516 10:02:14.538143 ==
4517 10:02:14.540928 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 10:02:14.543825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 10:02:14.544257 ==
4520 10:02:14.547475 RX Vref Scan: 0
4521 10:02:14.548046
4522 10:02:14.548422 RX Vref 0 -> 0, step: 1
4523 10:02:14.548820
4524 10:02:14.550880 RX Delay -230 -> 252, step: 16
4525 10:02:14.557022 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4526 10:02:14.560546 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4527 10:02:14.564410 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4528 10:02:14.567237 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4529 10:02:14.570400 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4530 10:02:14.577210 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4531 10:02:14.580759 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4532 10:02:14.583774 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4533 10:02:14.587239 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4534 10:02:14.593960 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4535 10:02:14.597208 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4536 10:02:14.600886 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4537 10:02:14.604049 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4538 10:02:14.610656 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4539 10:02:14.613489 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4540 10:02:14.617076 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4541 10:02:14.617563 ==
4542 10:02:14.620549 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 10:02:14.623741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 10:02:14.626903 ==
4545 10:02:14.627489 DQS Delay:
4546 10:02:14.627977 DQS0 = 0, DQS1 = 0
4547 10:02:14.630064 DQM Delay:
4548 10:02:14.630646 DQM0 = 50, DQM1 = 40
4549 10:02:14.633528 DQ Delay:
4550 10:02:14.634117 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4551 10:02:14.636600 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4552 10:02:14.640119 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =33
4553 10:02:14.643275 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =41
4554 10:02:14.646580
4555 10:02:14.647165
4556 10:02:14.647650 ==
4557 10:02:14.649572 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 10:02:14.653191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 10:02:14.653678 ==
4560 10:02:14.654154
4561 10:02:14.654605
4562 10:02:14.656350 TX Vref Scan disable
4563 10:02:14.656868 == TX Byte 0 ==
4564 10:02:14.663276 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4565 10:02:14.666672 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4566 10:02:14.667263 == TX Byte 1 ==
4567 10:02:14.673118 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4568 10:02:14.676368 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4569 10:02:14.677024 ==
4570 10:02:14.679780 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 10:02:14.683423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 10:02:14.683907 ==
4573 10:02:14.684383
4574 10:02:14.684870
4575 10:02:14.686230 TX Vref Scan disable
4576 10:02:14.689361 == TX Byte 0 ==
4577 10:02:14.692954 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4578 10:02:14.696436 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4579 10:02:14.699897 == TX Byte 1 ==
4580 10:02:14.702982 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4581 10:02:14.706315 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4582 10:02:14.706798
4583 10:02:14.709683 [DATLAT]
4584 10:02:14.710268 Freq=600, CH1 RK0
4585 10:02:14.710754
4586 10:02:14.712868 DATLAT Default: 0x9
4587 10:02:14.713350 0, 0xFFFF, sum = 0
4588 10:02:14.715990 1, 0xFFFF, sum = 0
4589 10:02:14.716497 2, 0xFFFF, sum = 0
4590 10:02:14.719849 3, 0xFFFF, sum = 0
4591 10:02:14.720451 4, 0xFFFF, sum = 0
4592 10:02:14.722758 5, 0xFFFF, sum = 0
4593 10:02:14.726148 6, 0xFFFF, sum = 0
4594 10:02:14.726746 7, 0xFFFF, sum = 0
4595 10:02:14.727243 8, 0x0, sum = 1
4596 10:02:14.729580 9, 0x0, sum = 2
4597 10:02:14.730069 10, 0x0, sum = 3
4598 10:02:14.732934 11, 0x0, sum = 4
4599 10:02:14.733533 best_step = 9
4600 10:02:14.734019
4601 10:02:14.734468 ==
4602 10:02:14.735620 Dram Type= 6, Freq= 0, CH_1, rank 0
4603 10:02:14.742753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 10:02:14.743347 ==
4605 10:02:14.743838 RX Vref Scan: 1
4606 10:02:14.744292
4607 10:02:14.745602 RX Vref 0 -> 0, step: 1
4608 10:02:14.746083
4609 10:02:14.749521 RX Delay -179 -> 252, step: 8
4610 10:02:14.750116
4611 10:02:14.752739 Set Vref, RX VrefLevel [Byte0]: 51
4612 10:02:14.755960 [Byte1]: 49
4613 10:02:14.756551
4614 10:02:14.759094 Final RX Vref Byte 0 = 51 to rank0
4615 10:02:14.762749 Final RX Vref Byte 1 = 49 to rank0
4616 10:02:14.765374 Final RX Vref Byte 0 = 51 to rank1
4617 10:02:14.769020 Final RX Vref Byte 1 = 49 to rank1==
4618 10:02:14.772167 Dram Type= 6, Freq= 0, CH_1, rank 0
4619 10:02:14.775460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 10:02:14.776042 ==
4621 10:02:14.778554 DQS Delay:
4622 10:02:14.779032 DQS0 = 0, DQS1 = 0
4623 10:02:14.781813 DQM Delay:
4624 10:02:14.782296 DQM0 = 50, DQM1 = 41
4625 10:02:14.782771 DQ Delay:
4626 10:02:14.785223 DQ0 =56, DQ1 =48, DQ2 =36, DQ3 =44
4627 10:02:14.788597 DQ4 =52, DQ5 =60, DQ6 =60, DQ7 =44
4628 10:02:14.791696 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =36
4629 10:02:14.795147 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4630 10:02:14.795628
4631 10:02:14.796102
4632 10:02:14.805718 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d74, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4633 10:02:14.808818 CH1 RK0: MR19=808, MR18=4D74
4634 10:02:14.815468 CH1_RK0: MR19=0x808, MR18=0x4D74, DQSOSC=388, MR23=63, INC=174, DEC=116
4635 10:02:14.816101
4636 10:02:14.818636 ----->DramcWriteLeveling(PI) begin...
4637 10:02:14.819225 ==
4638 10:02:14.821951 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 10:02:14.825338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 10:02:14.825921 ==
4641 10:02:14.828456 Write leveling (Byte 0): 31 => 31
4642 10:02:14.831812 Write leveling (Byte 1): 28 => 28
4643 10:02:14.835581 DramcWriteLeveling(PI) end<-----
4644 10:02:14.836160
4645 10:02:14.836639 ==
4646 10:02:14.837912 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 10:02:14.842083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 10:02:14.842667 ==
4649 10:02:14.845133 [Gating] SW mode calibration
4650 10:02:14.851531 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4651 10:02:14.858128 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4652 10:02:14.861393 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4653 10:02:14.864348 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4654 10:02:14.871399 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
4655 10:02:14.874096 0 9 12 | B1->B0 | 2a2a 3030 | 1 0 | (1 0) (0 1)
4656 10:02:14.877700 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 10:02:14.884321 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 10:02:14.887616 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 10:02:14.891173 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 10:02:14.897418 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 10:02:14.900889 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 10:02:14.904763 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 10:02:14.911084 0 10 12 | B1->B0 | 3a3a 2f2f | 0 1 | (0 0) (0 0)
4664 10:02:14.913909 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 10:02:14.917370 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 10:02:14.924096 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 10:02:14.927587 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 10:02:14.930762 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 10:02:14.937346 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 10:02:14.940852 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 10:02:14.944311 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4672 10:02:14.951006 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 10:02:14.954083 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 10:02:14.957122 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 10:02:14.963708 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 10:02:14.967185 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 10:02:14.970344 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 10:02:14.976707 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 10:02:14.980843 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 10:02:14.983600 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 10:02:14.990043 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 10:02:14.993921 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 10:02:14.997041 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 10:02:15.003176 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 10:02:15.006334 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 10:02:15.009678 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4687 10:02:15.016750 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4688 10:02:15.019487 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 10:02:15.023331 Total UI for P1: 0, mck2ui 16
4690 10:02:15.026458 best dqsien dly found for B0: ( 0, 13, 10)
4691 10:02:15.029697 Total UI for P1: 0, mck2ui 16
4692 10:02:15.032965 best dqsien dly found for B1: ( 0, 13, 12)
4693 10:02:15.036387 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4694 10:02:15.039732 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4695 10:02:15.040321
4696 10:02:15.043017 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4697 10:02:15.046356 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4698 10:02:15.049698 [Gating] SW calibration Done
4699 10:02:15.050286 ==
4700 10:02:15.052685 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 10:02:15.059545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 10:02:15.060126 ==
4703 10:02:15.060610 RX Vref Scan: 0
4704 10:02:15.061098
4705 10:02:15.062479 RX Vref 0 -> 0, step: 1
4706 10:02:15.062958
4707 10:02:15.066428 RX Delay -230 -> 252, step: 16
4708 10:02:15.069568 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4709 10:02:15.072810 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4710 10:02:15.075877 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4711 10:02:15.083055 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4712 10:02:15.085660 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4713 10:02:15.089339 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4714 10:02:15.092456 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4715 10:02:15.095899 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4716 10:02:15.102568 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4717 10:02:15.105759 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4718 10:02:15.109116 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4719 10:02:15.112997 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4720 10:02:15.118847 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4721 10:02:15.122408 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4722 10:02:15.125894 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4723 10:02:15.129216 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4724 10:02:15.129810 ==
4725 10:02:15.132507 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 10:02:15.138864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 10:02:15.139452 ==
4728 10:02:15.139939 DQS Delay:
4729 10:02:15.142274 DQS0 = 0, DQS1 = 0
4730 10:02:15.142859 DQM Delay:
4731 10:02:15.145555 DQM0 = 52, DQM1 = 47
4732 10:02:15.146144 DQ Delay:
4733 10:02:15.148979 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4734 10:02:15.152118 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4735 10:02:15.155371 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4736 10:02:15.158868 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4737 10:02:15.159456
4738 10:02:15.159945
4739 10:02:15.160392 ==
4740 10:02:15.161692 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 10:02:15.165496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 10:02:15.166087 ==
4743 10:02:15.166571
4744 10:02:15.167026
4745 10:02:15.168497 TX Vref Scan disable
4746 10:02:15.172085 == TX Byte 0 ==
4747 10:02:15.175192 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4748 10:02:15.178466 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4749 10:02:15.181682 == TX Byte 1 ==
4750 10:02:15.184843 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4751 10:02:15.188382 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4752 10:02:15.189015 ==
4753 10:02:15.191954 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 10:02:15.198022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 10:02:15.198612 ==
4756 10:02:15.199102
4757 10:02:15.199548
4758 10:02:15.199984 TX Vref Scan disable
4759 10:02:15.202614 == TX Byte 0 ==
4760 10:02:15.205616 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4761 10:02:15.212302 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4762 10:02:15.212811 == TX Byte 1 ==
4763 10:02:15.215367 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4764 10:02:15.221905 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4765 10:02:15.222417
4766 10:02:15.222902 [DATLAT]
4767 10:02:15.223346 Freq=600, CH1 RK1
4768 10:02:15.223786
4769 10:02:15.225597 DATLAT Default: 0x9
4770 10:02:15.226079 0, 0xFFFF, sum = 0
4771 10:02:15.228654 1, 0xFFFF, sum = 0
4772 10:02:15.232088 2, 0xFFFF, sum = 0
4773 10:02:15.232660 3, 0xFFFF, sum = 0
4774 10:02:15.236018 4, 0xFFFF, sum = 0
4775 10:02:15.236599 5, 0xFFFF, sum = 0
4776 10:02:15.238789 6, 0xFFFF, sum = 0
4777 10:02:15.239364 7, 0xFFFF, sum = 0
4778 10:02:15.242235 8, 0x0, sum = 1
4779 10:02:15.242820 9, 0x0, sum = 2
4780 10:02:15.243201 10, 0x0, sum = 3
4781 10:02:15.245654 11, 0x0, sum = 4
4782 10:02:15.246236 best_step = 9
4783 10:02:15.246608
4784 10:02:15.249062 ==
4785 10:02:15.249643 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 10:02:15.255535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 10:02:15.256006 ==
4788 10:02:15.256375 RX Vref Scan: 0
4789 10:02:15.256719
4790 10:02:15.258985 RX Vref 0 -> 0, step: 1
4791 10:02:15.259557
4792 10:02:15.261964 RX Delay -163 -> 252, step: 8
4793 10:02:15.265351 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4794 10:02:15.272255 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4795 10:02:15.275353 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4796 10:02:15.278683 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4797 10:02:15.281909 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4798 10:02:15.285491 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4799 10:02:15.291884 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4800 10:02:15.295231 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4801 10:02:15.298295 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4802 10:02:15.301650 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4803 10:02:15.308097 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4804 10:02:15.311687 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4805 10:02:15.314732 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4806 10:02:15.318117 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4807 10:02:15.321218 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4808 10:02:15.328637 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4809 10:02:15.329249 ==
4810 10:02:15.331698 Dram Type= 6, Freq= 0, CH_1, rank 1
4811 10:02:15.334732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4812 10:02:15.335304 ==
4813 10:02:15.335677 DQS Delay:
4814 10:02:15.338226 DQS0 = 0, DQS1 = 0
4815 10:02:15.338812 DQM Delay:
4816 10:02:15.342223 DQM0 = 48, DQM1 = 43
4817 10:02:15.342795 DQ Delay:
4818 10:02:15.344748 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4819 10:02:15.348299 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4820 10:02:15.351292 DQ8 =28, DQ9 =36, DQ10 =44, DQ11 =36
4821 10:02:15.354234 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =52
4822 10:02:15.354703
4823 10:02:15.355070
4824 10:02:15.364539 [DQSOSCAuto] RK1, (LSB)MR18= 0x581e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4825 10:02:15.365170 CH1 RK1: MR19=808, MR18=581E
4826 10:02:15.371205 CH1_RK1: MR19=0x808, MR18=0x581E, DQSOSC=393, MR23=63, INC=169, DEC=113
4827 10:02:15.374626 [RxdqsGatingPostProcess] freq 600
4828 10:02:15.381337 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4829 10:02:15.384419 Pre-setting of DQS Precalculation
4830 10:02:15.388017 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4831 10:02:15.394249 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4832 10:02:15.403984 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4833 10:02:15.404557
4834 10:02:15.404960
4835 10:02:15.407730 [Calibration Summary] 1200 Mbps
4836 10:02:15.408305 CH 0, Rank 0
4837 10:02:15.410511 SW Impedance : PASS
4838 10:02:15.410984 DUTY Scan : NO K
4839 10:02:15.414021 ZQ Calibration : PASS
4840 10:02:15.416977 Jitter Meter : NO K
4841 10:02:15.417444 CBT Training : PASS
4842 10:02:15.420346 Write leveling : PASS
4843 10:02:15.423888 RX DQS gating : PASS
4844 10:02:15.424461 RX DQ/DQS(RDDQC) : PASS
4845 10:02:15.427233 TX DQ/DQS : PASS
4846 10:02:15.427911 RX DATLAT : PASS
4847 10:02:15.429977 RX DQ/DQS(Engine): PASS
4848 10:02:15.433559 TX OE : NO K
4849 10:02:15.434136 All Pass.
4850 10:02:15.434512
4851 10:02:15.434855 CH 0, Rank 1
4852 10:02:15.436639 SW Impedance : PASS
4853 10:02:15.440360 DUTY Scan : NO K
4854 10:02:15.440973 ZQ Calibration : PASS
4855 10:02:15.443657 Jitter Meter : NO K
4856 10:02:15.446990 CBT Training : PASS
4857 10:02:15.447562 Write leveling : PASS
4858 10:02:15.450232 RX DQS gating : PASS
4859 10:02:15.453685 RX DQ/DQS(RDDQC) : PASS
4860 10:02:15.454263 TX DQ/DQS : PASS
4861 10:02:15.456826 RX DATLAT : PASS
4862 10:02:15.460481 RX DQ/DQS(Engine): PASS
4863 10:02:15.461095 TX OE : NO K
4864 10:02:15.463577 All Pass.
4865 10:02:15.464144
4866 10:02:15.464510 CH 1, Rank 0
4867 10:02:15.467162 SW Impedance : PASS
4868 10:02:15.467752 DUTY Scan : NO K
4869 10:02:15.470246 ZQ Calibration : PASS
4870 10:02:15.473504 Jitter Meter : NO K
4871 10:02:15.474078 CBT Training : PASS
4872 10:02:15.477072 Write leveling : PASS
4873 10:02:15.480252 RX DQS gating : PASS
4874 10:02:15.480861 RX DQ/DQS(RDDQC) : PASS
4875 10:02:15.483558 TX DQ/DQS : PASS
4876 10:02:15.487234 RX DATLAT : PASS
4877 10:02:15.487826 RX DQ/DQS(Engine): PASS
4878 10:02:15.489800 TX OE : NO K
4879 10:02:15.490380 All Pass.
4880 10:02:15.490755
4881 10:02:15.493470 CH 1, Rank 1
4882 10:02:15.494049 SW Impedance : PASS
4883 10:02:15.496568 DUTY Scan : NO K
4884 10:02:15.497201 ZQ Calibration : PASS
4885 10:02:15.500193 Jitter Meter : NO K
4886 10:02:15.503258 CBT Training : PASS
4887 10:02:15.503830 Write leveling : PASS
4888 10:02:15.506514 RX DQS gating : PASS
4889 10:02:15.509548 RX DQ/DQS(RDDQC) : PASS
4890 10:02:15.510015 TX DQ/DQS : PASS
4891 10:02:15.513007 RX DATLAT : PASS
4892 10:02:15.516230 RX DQ/DQS(Engine): PASS
4893 10:02:15.516824 TX OE : NO K
4894 10:02:15.519543 All Pass.
4895 10:02:15.520011
4896 10:02:15.520377 DramC Write-DBI off
4897 10:02:15.523025 PER_BANK_REFRESH: Hybrid Mode
4898 10:02:15.523515 TX_TRACKING: ON
4899 10:02:15.532792 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4900 10:02:15.536101 [FAST_K] Save calibration result to emmc
4901 10:02:15.539952 dramc_set_vcore_voltage set vcore to 662500
4902 10:02:15.543007 Read voltage for 933, 3
4903 10:02:15.543624 Vio18 = 0
4904 10:02:15.545989 Vcore = 662500
4905 10:02:15.546456 Vdram = 0
4906 10:02:15.546827 Vddq = 0
4907 10:02:15.549312 Vmddr = 0
4908 10:02:15.552550 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4909 10:02:15.559738 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4910 10:02:15.560316 MEM_TYPE=3, freq_sel=17
4911 10:02:15.562795 sv_algorithm_assistance_LP4_1600
4912 10:02:15.569672 ============ PULL DRAM RESETB DOWN ============
4913 10:02:15.573396 ========== PULL DRAM RESETB DOWN end =========
4914 10:02:15.575929 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4915 10:02:15.579343 ===================================
4916 10:02:15.582814 LPDDR4 DRAM CONFIGURATION
4917 10:02:15.585487 ===================================
4918 10:02:15.589196 EX_ROW_EN[0] = 0x0
4919 10:02:15.589768 EX_ROW_EN[1] = 0x0
4920 10:02:15.592717 LP4Y_EN = 0x0
4921 10:02:15.593326 WORK_FSP = 0x0
4922 10:02:15.595865 WL = 0x3
4923 10:02:15.596436 RL = 0x3
4924 10:02:15.599660 BL = 0x2
4925 10:02:15.600236 RPST = 0x0
4926 10:02:15.602438 RD_PRE = 0x0
4927 10:02:15.603011 WR_PRE = 0x1
4928 10:02:15.605620 WR_PST = 0x0
4929 10:02:15.606113 DBI_WR = 0x0
4930 10:02:15.609079 DBI_RD = 0x0
4931 10:02:15.609654 OTF = 0x1
4932 10:02:15.612759 ===================================
4933 10:02:15.615892 ===================================
4934 10:02:15.619415 ANA top config
4935 10:02:15.622204 ===================================
4936 10:02:15.625619 DLL_ASYNC_EN = 0
4937 10:02:15.626186 ALL_SLAVE_EN = 1
4938 10:02:15.628762 NEW_RANK_MODE = 1
4939 10:02:15.632420 DLL_IDLE_MODE = 1
4940 10:02:15.635549 LP45_APHY_COMB_EN = 1
4941 10:02:15.636116 TX_ODT_DIS = 1
4942 10:02:15.639078 NEW_8X_MODE = 1
4943 10:02:15.642045 ===================================
4944 10:02:15.645337 ===================================
4945 10:02:15.648729 data_rate = 1866
4946 10:02:15.652489 CKR = 1
4947 10:02:15.655319 DQ_P2S_RATIO = 8
4948 10:02:15.659299 ===================================
4949 10:02:15.661811 CA_P2S_RATIO = 8
4950 10:02:15.662279 DQ_CA_OPEN = 0
4951 10:02:15.665589 DQ_SEMI_OPEN = 0
4952 10:02:15.669054 CA_SEMI_OPEN = 0
4953 10:02:15.672416 CA_FULL_RATE = 0
4954 10:02:15.675273 DQ_CKDIV4_EN = 1
4955 10:02:15.679341 CA_CKDIV4_EN = 1
4956 10:02:15.679912 CA_PREDIV_EN = 0
4957 10:02:15.681821 PH8_DLY = 0
4958 10:02:15.685400 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4959 10:02:15.688342 DQ_AAMCK_DIV = 4
4960 10:02:15.691954 CA_AAMCK_DIV = 4
4961 10:02:15.695265 CA_ADMCK_DIV = 4
4962 10:02:15.695840 DQ_TRACK_CA_EN = 0
4963 10:02:15.698249 CA_PICK = 933
4964 10:02:15.701678 CA_MCKIO = 933
4965 10:02:15.705127 MCKIO_SEMI = 0
4966 10:02:15.708002 PLL_FREQ = 3732
4967 10:02:15.711867 DQ_UI_PI_RATIO = 32
4968 10:02:15.715146 CA_UI_PI_RATIO = 0
4969 10:02:15.717814 ===================================
4970 10:02:15.721532 ===================================
4971 10:02:15.722108 memory_type:LPDDR4
4972 10:02:15.725062 GP_NUM : 10
4973 10:02:15.728090 SRAM_EN : 1
4974 10:02:15.728714 MD32_EN : 0
4975 10:02:15.731380 ===================================
4976 10:02:15.734497 [ANA_INIT] >>>>>>>>>>>>>>
4977 10:02:15.737906 <<<<<< [CONFIGURE PHASE]: ANA_TX
4978 10:02:15.740899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4979 10:02:15.744451 ===================================
4980 10:02:15.748120 data_rate = 1866,PCW = 0X8f00
4981 10:02:15.751373 ===================================
4982 10:02:15.754312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4983 10:02:15.757706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4984 10:02:15.764524 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4985 10:02:15.767813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4986 10:02:15.771015 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4987 10:02:15.777423 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4988 10:02:15.777992 [ANA_INIT] flow start
4989 10:02:15.780686 [ANA_INIT] PLL >>>>>>>>
4990 10:02:15.784055 [ANA_INIT] PLL <<<<<<<<
4991 10:02:15.784620 [ANA_INIT] MIDPI >>>>>>>>
4992 10:02:15.787171 [ANA_INIT] MIDPI <<<<<<<<
4993 10:02:15.790661 [ANA_INIT] DLL >>>>>>>>
4994 10:02:15.791240 [ANA_INIT] flow end
4995 10:02:15.797680 ============ LP4 DIFF to SE enter ============
4996 10:02:15.800877 ============ LP4 DIFF to SE exit ============
4997 10:02:15.801448 [ANA_INIT] <<<<<<<<<<<<<
4998 10:02:15.803855 [Flow] Enable top DCM control >>>>>
4999 10:02:15.806906 [Flow] Enable top DCM control <<<<<
5000 10:02:15.810602 Enable DLL master slave shuffle
5001 10:02:15.816945 ==============================================================
5002 10:02:15.820191 Gating Mode config
5003 10:02:15.823717 ==============================================================
5004 10:02:15.827542 Config description:
5005 10:02:15.837203 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5006 10:02:15.843485 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5007 10:02:15.846703 SELPH_MODE 0: By rank 1: By Phase
5008 10:02:15.853395 ==============================================================
5009 10:02:15.856922 GAT_TRACK_EN = 1
5010 10:02:15.859561 RX_GATING_MODE = 2
5011 10:02:15.863035 RX_GATING_TRACK_MODE = 2
5012 10:02:15.866347 SELPH_MODE = 1
5013 10:02:15.866816 PICG_EARLY_EN = 1
5014 10:02:15.869466 VALID_LAT_VALUE = 1
5015 10:02:15.876522 ==============================================================
5016 10:02:15.881873 Enter into Gating configuration >>>>
5017 10:02:15.882923 Exit from Gating configuration <<<<
5018 10:02:15.886419 Enter into DVFS_PRE_config >>>>>
5019 10:02:15.896306 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5020 10:02:15.899575 Exit from DVFS_PRE_config <<<<<
5021 10:02:15.903038 Enter into PICG configuration >>>>
5022 10:02:15.906569 Exit from PICG configuration <<<<
5023 10:02:15.909654 [RX_INPUT] configuration >>>>>
5024 10:02:15.913108 [RX_INPUT] configuration <<<<<
5025 10:02:15.916447 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5026 10:02:15.922661 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5027 10:02:15.929840 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5028 10:02:15.936224 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5029 10:02:15.942860 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5030 10:02:15.946133 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5031 10:02:15.952815 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5032 10:02:15.956037 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5033 10:02:15.958889 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5034 10:02:15.962893 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5035 10:02:15.969191 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5036 10:02:15.972224 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5037 10:02:15.975858 ===================================
5038 10:02:15.978996 LPDDR4 DRAM CONFIGURATION
5039 10:02:15.982549 ===================================
5040 10:02:15.983121 EX_ROW_EN[0] = 0x0
5041 10:02:15.985650 EX_ROW_EN[1] = 0x0
5042 10:02:15.986218 LP4Y_EN = 0x0
5043 10:02:15.989122 WORK_FSP = 0x0
5044 10:02:15.989689 WL = 0x3
5045 10:02:15.992465 RL = 0x3
5046 10:02:15.995564 BL = 0x2
5047 10:02:15.996129 RPST = 0x0
5048 10:02:15.999173 RD_PRE = 0x0
5049 10:02:15.999640 WR_PRE = 0x1
5050 10:02:16.002067 WR_PST = 0x0
5051 10:02:16.002638 DBI_WR = 0x0
5052 10:02:16.005693 DBI_RD = 0x0
5053 10:02:16.006259 OTF = 0x1
5054 10:02:16.008964 ===================================
5055 10:02:16.012089 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5056 10:02:16.018602 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5057 10:02:16.022299 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5058 10:02:16.025240 ===================================
5059 10:02:16.029261 LPDDR4 DRAM CONFIGURATION
5060 10:02:16.032156 ===================================
5061 10:02:16.032726 EX_ROW_EN[0] = 0x10
5062 10:02:16.035653 EX_ROW_EN[1] = 0x0
5063 10:02:16.036221 LP4Y_EN = 0x0
5064 10:02:16.038431 WORK_FSP = 0x0
5065 10:02:16.039000 WL = 0x3
5066 10:02:16.042046 RL = 0x3
5067 10:02:16.045007 BL = 0x2
5068 10:02:16.045471 RPST = 0x0
5069 10:02:16.048748 RD_PRE = 0x0
5070 10:02:16.049339 WR_PRE = 0x1
5071 10:02:16.051546 WR_PST = 0x0
5072 10:02:16.052113 DBI_WR = 0x0
5073 10:02:16.054993 DBI_RD = 0x0
5074 10:02:16.055516 OTF = 0x1
5075 10:02:16.058209 ===================================
5076 10:02:16.064656 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5077 10:02:16.068909 nWR fixed to 30
5078 10:02:16.072365 [ModeRegInit_LP4] CH0 RK0
5079 10:02:16.072973 [ModeRegInit_LP4] CH0 RK1
5080 10:02:16.075311 [ModeRegInit_LP4] CH1 RK0
5081 10:02:16.078892 [ModeRegInit_LP4] CH1 RK1
5082 10:02:16.079361 match AC timing 9
5083 10:02:16.085840 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5084 10:02:16.088513 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5085 10:02:16.091760 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5086 10:02:16.098812 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5087 10:02:16.101612 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5088 10:02:16.102085 ==
5089 10:02:16.104968 Dram Type= 6, Freq= 0, CH_0, rank 0
5090 10:02:16.107925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 10:02:16.108403 ==
5092 10:02:16.115045 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5093 10:02:16.121526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5094 10:02:16.124667 [CA 0] Center 38 (7~69) winsize 63
5095 10:02:16.128446 [CA 1] Center 38 (8~69) winsize 62
5096 10:02:16.131575 [CA 2] Center 35 (5~66) winsize 62
5097 10:02:16.135372 [CA 3] Center 34 (4~65) winsize 62
5098 10:02:16.137814 [CA 4] Center 34 (4~65) winsize 62
5099 10:02:16.141647 [CA 5] Center 33 (3~64) winsize 62
5100 10:02:16.142227
5101 10:02:16.144742 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5102 10:02:16.145353
5103 10:02:16.147863 [CATrainingPosCal] consider 1 rank data
5104 10:02:16.151187 u2DelayCellTimex100 = 270/100 ps
5105 10:02:16.154648 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5106 10:02:16.157707 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5107 10:02:16.160849 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5108 10:02:16.167694 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5109 10:02:16.170877 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5110 10:02:16.174177 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5111 10:02:16.174744
5112 10:02:16.177447 CA PerBit enable=1, Macro0, CA PI delay=33
5113 10:02:16.177943
5114 10:02:16.180667 [CBTSetCACLKResult] CA Dly = 33
5115 10:02:16.181181 CS Dly: 7 (0~38)
5116 10:02:16.181559 ==
5117 10:02:16.183955 Dram Type= 6, Freq= 0, CH_0, rank 1
5118 10:02:16.190693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 10:02:16.191168 ==
5120 10:02:16.194311 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5121 10:02:16.200723 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5122 10:02:16.204147 [CA 0] Center 38 (8~69) winsize 62
5123 10:02:16.207261 [CA 1] Center 38 (8~69) winsize 62
5124 10:02:16.210186 [CA 2] Center 36 (6~66) winsize 61
5125 10:02:16.213675 [CA 3] Center 35 (5~66) winsize 62
5126 10:02:16.217468 [CA 4] Center 34 (4~65) winsize 62
5127 10:02:16.220296 [CA 5] Center 34 (4~64) winsize 61
5128 10:02:16.220799
5129 10:02:16.223794 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5130 10:02:16.224364
5131 10:02:16.227011 [CATrainingPosCal] consider 2 rank data
5132 10:02:16.230623 u2DelayCellTimex100 = 270/100 ps
5133 10:02:16.233703 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5134 10:02:16.240391 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5135 10:02:16.243566 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5136 10:02:16.246894 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5137 10:02:16.250995 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5138 10:02:16.253310 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5139 10:02:16.253803
5140 10:02:16.256800 CA PerBit enable=1, Macro0, CA PI delay=34
5141 10:02:16.257371
5142 10:02:16.260210 [CBTSetCACLKResult] CA Dly = 34
5143 10:02:16.264481 CS Dly: 7 (0~39)
5144 10:02:16.265135
5145 10:02:16.267564 ----->DramcWriteLeveling(PI) begin...
5146 10:02:16.268142 ==
5147 10:02:16.270284 Dram Type= 6, Freq= 0, CH_0, rank 0
5148 10:02:16.273042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5149 10:02:16.273519 ==
5150 10:02:16.276676 Write leveling (Byte 0): 33 => 33
5151 10:02:16.280203 Write leveling (Byte 1): 30 => 30
5152 10:02:16.283549 DramcWriteLeveling(PI) end<-----
5153 10:02:16.284122
5154 10:02:16.284493 ==
5155 10:02:16.286783 Dram Type= 6, Freq= 0, CH_0, rank 0
5156 10:02:16.289872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 10:02:16.290347 ==
5158 10:02:16.293206 [Gating] SW mode calibration
5159 10:02:16.299639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5160 10:02:16.306593 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5161 10:02:16.309925 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5162 10:02:16.313141 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 10:02:16.319863 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 10:02:16.323059 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 10:02:16.326092 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 10:02:16.333102 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 10:02:16.336029 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5168 10:02:16.339653 0 14 28 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
5169 10:02:16.345908 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 10:02:16.349287 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 10:02:16.352884 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 10:02:16.359452 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 10:02:16.363037 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 10:02:16.365535 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 10:02:16.372700 0 15 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5176 10:02:16.375902 0 15 28 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
5177 10:02:16.378974 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5178 10:02:16.385604 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 10:02:16.388802 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 10:02:16.391892 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 10:02:16.398901 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 10:02:16.401849 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 10:02:16.405412 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 10:02:16.411963 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5185 10:02:16.415198 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5186 10:02:16.418711 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 10:02:16.425187 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 10:02:16.428355 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 10:02:16.431896 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 10:02:16.438693 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 10:02:16.441710 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 10:02:16.445204 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 10:02:16.452131 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 10:02:16.455061 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 10:02:16.458146 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 10:02:16.464851 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 10:02:16.468460 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 10:02:16.471685 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 10:02:16.478108 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5200 10:02:16.481443 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5201 10:02:16.484692 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5202 10:02:16.487911 Total UI for P1: 0, mck2ui 16
5203 10:02:16.491543 best dqsien dly found for B0: ( 1, 2, 26)
5204 10:02:16.497716 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 10:02:16.498298 Total UI for P1: 0, mck2ui 16
5206 10:02:16.504552 best dqsien dly found for B1: ( 1, 3, 0)
5207 10:02:16.507643 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5208 10:02:16.511421 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5209 10:02:16.511996
5210 10:02:16.514542 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5211 10:02:16.517615 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5212 10:02:16.520727 [Gating] SW calibration Done
5213 10:02:16.521230 ==
5214 10:02:16.524309 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 10:02:16.527972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 10:02:16.528545 ==
5217 10:02:16.531185 RX Vref Scan: 0
5218 10:02:16.531760
5219 10:02:16.532135 RX Vref 0 -> 0, step: 1
5220 10:02:16.532482
5221 10:02:16.534408 RX Delay -80 -> 252, step: 8
5222 10:02:16.537538 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5223 10:02:16.543973 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5224 10:02:16.547338 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5225 10:02:16.551190 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5226 10:02:16.554086 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5227 10:02:16.557143 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5228 10:02:16.564152 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5229 10:02:16.567439 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5230 10:02:16.570937 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5231 10:02:16.573478 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5232 10:02:16.576897 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5233 10:02:16.580729 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5234 10:02:16.587383 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5235 10:02:16.590210 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5236 10:02:16.593449 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5237 10:02:16.596657 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5238 10:02:16.597177 ==
5239 10:02:16.599909 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 10:02:16.603915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 10:02:16.606882 ==
5242 10:02:16.607461 DQS Delay:
5243 10:02:16.607834 DQS0 = 0, DQS1 = 0
5244 10:02:16.610199 DQM Delay:
5245 10:02:16.610669 DQM0 = 105, DQM1 = 90
5246 10:02:16.613444 DQ Delay:
5247 10:02:16.616638 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5248 10:02:16.620210 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5249 10:02:16.623138 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5250 10:02:16.626644 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =99
5251 10:02:16.627227
5252 10:02:16.627599
5253 10:02:16.627940 ==
5254 10:02:16.629943 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 10:02:16.633607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 10:02:16.634184 ==
5257 10:02:16.634556
5258 10:02:16.634898
5259 10:02:16.636353 TX Vref Scan disable
5260 10:02:16.636920 == TX Byte 0 ==
5261 10:02:16.642844 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5262 10:02:16.646383 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5263 10:02:16.649815 == TX Byte 1 ==
5264 10:02:16.652926 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5265 10:02:16.656315 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5266 10:02:16.656815 ==
5267 10:02:16.660000 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 10:02:16.663003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 10:02:16.663478 ==
5270 10:02:16.665985
5271 10:02:16.666449
5272 10:02:16.666821 TX Vref Scan disable
5273 10:02:16.669324 == TX Byte 0 ==
5274 10:02:16.672759 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5275 10:02:16.679455 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5276 10:02:16.679987 == TX Byte 1 ==
5277 10:02:16.682785 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5278 10:02:16.689423 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5279 10:02:16.689954
5280 10:02:16.690291 [DATLAT]
5281 10:02:16.690612 Freq=933, CH0 RK0
5282 10:02:16.690919
5283 10:02:16.692743 DATLAT Default: 0xd
5284 10:02:16.693304 0, 0xFFFF, sum = 0
5285 10:02:16.696323 1, 0xFFFF, sum = 0
5286 10:02:16.696894 2, 0xFFFF, sum = 0
5287 10:02:16.699030 3, 0xFFFF, sum = 0
5288 10:02:16.702673 4, 0xFFFF, sum = 0
5289 10:02:16.703212 5, 0xFFFF, sum = 0
5290 10:02:16.705702 6, 0xFFFF, sum = 0
5291 10:02:16.706133 7, 0xFFFF, sum = 0
5292 10:02:16.708964 8, 0xFFFF, sum = 0
5293 10:02:16.709452 9, 0xFFFF, sum = 0
5294 10:02:16.712389 10, 0x0, sum = 1
5295 10:02:16.712945 11, 0x0, sum = 2
5296 10:02:16.715777 12, 0x0, sum = 3
5297 10:02:16.716354 13, 0x0, sum = 4
5298 10:02:16.716708 best_step = 11
5299 10:02:16.718873
5300 10:02:16.719296 ==
5301 10:02:16.722110 Dram Type= 6, Freq= 0, CH_0, rank 0
5302 10:02:16.725854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 10:02:16.726384 ==
5304 10:02:16.726730 RX Vref Scan: 1
5305 10:02:16.727051
5306 10:02:16.728901 RX Vref 0 -> 0, step: 1
5307 10:02:16.729463
5308 10:02:16.732237 RX Delay -53 -> 252, step: 4
5309 10:02:16.732746
5310 10:02:16.735900 Set Vref, RX VrefLevel [Byte0]: 59
5311 10:02:16.738831 [Byte1]: 49
5312 10:02:16.739257
5313 10:02:16.742363 Final RX Vref Byte 0 = 59 to rank0
5314 10:02:16.745670 Final RX Vref Byte 1 = 49 to rank0
5315 10:02:16.749327 Final RX Vref Byte 0 = 59 to rank1
5316 10:02:16.752231 Final RX Vref Byte 1 = 49 to rank1==
5317 10:02:16.755914 Dram Type= 6, Freq= 0, CH_0, rank 0
5318 10:02:16.758649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 10:02:16.762184 ==
5320 10:02:16.762724 DQS Delay:
5321 10:02:16.763282 DQS0 = 0, DQS1 = 0
5322 10:02:16.765408 DQM Delay:
5323 10:02:16.765871 DQM0 = 107, DQM1 = 92
5324 10:02:16.768536 DQ Delay:
5325 10:02:16.772404 DQ0 =108, DQ1 =106, DQ2 =102, DQ3 =106
5326 10:02:16.776035 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =114
5327 10:02:16.778650 DQ8 =86, DQ9 =76, DQ10 =92, DQ11 =92
5328 10:02:16.781943 DQ12 =98, DQ13 =96, DQ14 =102, DQ15 =100
5329 10:02:16.782508
5330 10:02:16.782880
5331 10:02:16.788820 [DQSOSCAuto] RK0, (LSB)MR18= 0x221e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5332 10:02:16.792088 CH0 RK0: MR19=505, MR18=221E
5333 10:02:16.798746 CH0_RK0: MR19=0x505, MR18=0x221E, DQSOSC=411, MR23=63, INC=64, DEC=42
5334 10:02:16.799313
5335 10:02:16.802143 ----->DramcWriteLeveling(PI) begin...
5336 10:02:16.802718 ==
5337 10:02:16.805027 Dram Type= 6, Freq= 0, CH_0, rank 1
5338 10:02:16.808443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 10:02:16.809198 ==
5340 10:02:16.811670 Write leveling (Byte 0): 34 => 34
5341 10:02:16.815164 Write leveling (Byte 1): 32 => 32
5342 10:02:16.818192 DramcWriteLeveling(PI) end<-----
5343 10:02:16.818663
5344 10:02:16.819038 ==
5345 10:02:16.821779 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 10:02:16.828522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 10:02:16.829139 ==
5348 10:02:16.829521 [Gating] SW mode calibration
5349 10:02:16.838505 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5350 10:02:16.841469 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5351 10:02:16.845152 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 10:02:16.852119 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 10:02:16.854895 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 10:02:16.858342 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 10:02:16.864996 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 10:02:16.868027 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 10:02:16.871256 0 14 24 | B1->B0 | 3232 3232 | 1 0 | (1 0) (1 0)
5358 10:02:16.878059 0 14 28 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (1 0)
5359 10:02:16.881091 0 15 0 | B1->B0 | 2424 2424 | 1 0 | (1 0) (1 0)
5360 10:02:16.884230 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 10:02:16.891119 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 10:02:16.894674 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 10:02:16.897472 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 10:02:16.904539 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 10:02:16.907755 0 15 24 | B1->B0 | 2727 2d2d | 0 0 | (0 0) (0 0)
5366 10:02:16.910592 0 15 28 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
5367 10:02:16.917816 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 10:02:16.920938 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 10:02:16.923867 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 10:02:16.930636 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 10:02:16.934139 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 10:02:16.937488 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 10:02:16.943790 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 10:02:16.947622 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5375 10:02:16.950709 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 10:02:16.957281 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 10:02:16.960254 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 10:02:16.963535 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 10:02:16.970454 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 10:02:16.973494 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 10:02:16.977047 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 10:02:16.983482 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 10:02:16.986693 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 10:02:16.990021 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 10:02:16.996455 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 10:02:16.999877 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 10:02:17.003196 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 10:02:17.009839 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 10:02:17.013120 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 10:02:17.016195 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 10:02:17.019861 Total UI for P1: 0, mck2ui 16
5392 10:02:17.023141 best dqsien dly found for B0: ( 1, 2, 26)
5393 10:02:17.026317 Total UI for P1: 0, mck2ui 16
5394 10:02:17.029457 best dqsien dly found for B1: ( 1, 2, 26)
5395 10:02:17.033046 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5396 10:02:17.036174 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5397 10:02:17.036400
5398 10:02:17.042802 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5399 10:02:17.046137 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5400 10:02:17.049591 [Gating] SW calibration Done
5401 10:02:17.049847 ==
5402 10:02:17.052747 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 10:02:17.056663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 10:02:17.056969 ==
5405 10:02:17.057135 RX Vref Scan: 0
5406 10:02:17.057283
5407 10:02:17.059383 RX Vref 0 -> 0, step: 1
5408 10:02:17.059617
5409 10:02:17.062500 RX Delay -80 -> 252, step: 8
5410 10:02:17.065793 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5411 10:02:17.069280 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5412 10:02:17.072925 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5413 10:02:17.079611 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5414 10:02:17.082750 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5415 10:02:17.086176 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5416 10:02:17.089195 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5417 10:02:17.092611 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5418 10:02:17.099587 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5419 10:02:17.102568 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5420 10:02:17.106124 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5421 10:02:17.109164 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5422 10:02:17.112953 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5423 10:02:17.116045 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5424 10:02:17.122527 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5425 10:02:17.125346 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5426 10:02:17.125888 ==
5427 10:02:17.129144 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 10:02:17.132692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 10:02:17.133291 ==
5430 10:02:17.135579 DQS Delay:
5431 10:02:17.136027 DQS0 = 0, DQS1 = 0
5432 10:02:17.136443 DQM Delay:
5433 10:02:17.138771 DQM0 = 104, DQM1 = 91
5434 10:02:17.139225 DQ Delay:
5435 10:02:17.142285 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5436 10:02:17.145671 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5437 10:02:17.148632 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5438 10:02:17.151970 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5439 10:02:17.152449
5440 10:02:17.152799
5441 10:02:17.155120 ==
5442 10:02:17.155528 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 10:02:17.161817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 10:02:17.162231 ==
5445 10:02:17.162554
5446 10:02:17.162852
5447 10:02:17.164880 TX Vref Scan disable
5448 10:02:17.165298 == TX Byte 0 ==
5449 10:02:17.168529 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5450 10:02:17.175130 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5451 10:02:17.175691 == TX Byte 1 ==
5452 10:02:17.178415 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5453 10:02:17.185177 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5454 10:02:17.185752 ==
5455 10:02:17.188934 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 10:02:17.191937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 10:02:17.192512 ==
5458 10:02:17.192928
5459 10:02:17.193277
5460 10:02:17.195194 TX Vref Scan disable
5461 10:02:17.198366 == TX Byte 0 ==
5462 10:02:17.201570 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5463 10:02:17.205435 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5464 10:02:17.208257 == TX Byte 1 ==
5465 10:02:17.211198 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5466 10:02:17.214964 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5467 10:02:17.215537
5468 10:02:17.218361 [DATLAT]
5469 10:02:17.218932 Freq=933, CH0 RK1
5470 10:02:17.219306
5471 10:02:17.221474 DATLAT Default: 0xb
5472 10:02:17.221942 0, 0xFFFF, sum = 0
5473 10:02:17.225131 1, 0xFFFF, sum = 0
5474 10:02:17.225713 2, 0xFFFF, sum = 0
5475 10:02:17.227961 3, 0xFFFF, sum = 0
5476 10:02:17.228435 4, 0xFFFF, sum = 0
5477 10:02:17.231464 5, 0xFFFF, sum = 0
5478 10:02:17.232045 6, 0xFFFF, sum = 0
5479 10:02:17.235007 7, 0xFFFF, sum = 0
5480 10:02:17.235589 8, 0xFFFF, sum = 0
5481 10:02:17.238102 9, 0xFFFF, sum = 0
5482 10:02:17.238683 10, 0x0, sum = 1
5483 10:02:17.241494 11, 0x0, sum = 2
5484 10:02:17.242090 12, 0x0, sum = 3
5485 10:02:17.244941 13, 0x0, sum = 4
5486 10:02:17.245545 best_step = 11
5487 10:02:17.245924
5488 10:02:17.246271 ==
5489 10:02:17.247716 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 10:02:17.251694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 10:02:17.254350 ==
5492 10:02:17.254821 RX Vref Scan: 0
5493 10:02:17.255193
5494 10:02:17.257786 RX Vref 0 -> 0, step: 1
5495 10:02:17.258258
5496 10:02:17.261157 RX Delay -53 -> 252, step: 4
5497 10:02:17.264478 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5498 10:02:17.267247 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5499 10:02:17.274360 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5500 10:02:17.277528 iDelay=199, Bit 3, Center 96 (11 ~ 182) 172
5501 10:02:17.280853 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5502 10:02:17.284215 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5503 10:02:17.288077 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5504 10:02:17.293744 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5505 10:02:17.297675 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5506 10:02:17.300659 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5507 10:02:17.304137 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5508 10:02:17.307197 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5509 10:02:17.313666 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5510 10:02:17.317368 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5511 10:02:17.320618 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5512 10:02:17.323866 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5513 10:02:17.324357 ==
5514 10:02:17.327017 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 10:02:17.330571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 10:02:17.333653 ==
5517 10:02:17.334227 DQS Delay:
5518 10:02:17.334599 DQS0 = 0, DQS1 = 0
5519 10:02:17.337131 DQM Delay:
5520 10:02:17.337697 DQM0 = 104, DQM1 = 92
5521 10:02:17.340554 DQ Delay:
5522 10:02:17.343735 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =96
5523 10:02:17.346971 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =112
5524 10:02:17.350092 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5525 10:02:17.353731 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5526 10:02:17.354297
5527 10:02:17.354667
5528 10:02:17.359959 [DQSOSCAuto] RK1, (LSB)MR18= 0x2808, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5529 10:02:17.363335 CH0 RK1: MR19=505, MR18=2808
5530 10:02:17.370037 CH0_RK1: MR19=0x505, MR18=0x2808, DQSOSC=409, MR23=63, INC=64, DEC=43
5531 10:02:17.373173 [RxdqsGatingPostProcess] freq 933
5532 10:02:17.379870 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5533 10:02:17.380447 best DQS0 dly(2T, 0.5T) = (0, 10)
5534 10:02:17.383122 best DQS1 dly(2T, 0.5T) = (0, 11)
5535 10:02:17.386273 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5536 10:02:17.389999 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5537 10:02:17.392812 best DQS0 dly(2T, 0.5T) = (0, 10)
5538 10:02:17.396562 best DQS1 dly(2T, 0.5T) = (0, 10)
5539 10:02:17.399407 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5540 10:02:17.402744 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5541 10:02:17.406082 Pre-setting of DQS Precalculation
5542 10:02:17.412870 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5543 10:02:17.413447 ==
5544 10:02:17.416057 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 10:02:17.419880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 10:02:17.420460 ==
5547 10:02:17.426117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5548 10:02:17.429574 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5549 10:02:17.433512 [CA 0] Center 37 (7~68) winsize 62
5550 10:02:17.436926 [CA 1] Center 37 (7~68) winsize 62
5551 10:02:17.439987 [CA 2] Center 36 (6~66) winsize 61
5552 10:02:17.443438 [CA 3] Center 34 (4~65) winsize 62
5553 10:02:17.446531 [CA 4] Center 35 (5~66) winsize 62
5554 10:02:17.450187 [CA 5] Center 34 (4~65) winsize 62
5555 10:02:17.450782
5556 10:02:17.453415 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5557 10:02:17.453993
5558 10:02:17.456692 [CATrainingPosCal] consider 1 rank data
5559 10:02:17.460056 u2DelayCellTimex100 = 270/100 ps
5560 10:02:17.463444 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5561 10:02:17.469838 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5562 10:02:17.473025 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5563 10:02:17.476482 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5564 10:02:17.479620 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5565 10:02:17.483033 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5566 10:02:17.483607
5567 10:02:17.486544 CA PerBit enable=1, Macro0, CA PI delay=34
5568 10:02:17.487013
5569 10:02:17.489460 [CBTSetCACLKResult] CA Dly = 34
5570 10:02:17.493219 CS Dly: 6 (0~37)
5571 10:02:17.493645 ==
5572 10:02:17.496669 Dram Type= 6, Freq= 0, CH_1, rank 1
5573 10:02:17.499891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5574 10:02:17.500426 ==
5575 10:02:17.506378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5576 10:02:17.509686 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5577 10:02:17.514276 [CA 0] Center 38 (8~69) winsize 62
5578 10:02:17.516900 [CA 1] Center 38 (8~69) winsize 62
5579 10:02:17.520114 [CA 2] Center 35 (5~66) winsize 62
5580 10:02:17.523292 [CA 3] Center 35 (5~65) winsize 61
5581 10:02:17.526819 [CA 4] Center 35 (5~65) winsize 61
5582 10:02:17.530161 [CA 5] Center 35 (5~65) winsize 61
5583 10:02:17.530697
5584 10:02:17.533752 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5585 10:02:17.534288
5586 10:02:17.536850 [CATrainingPosCal] consider 2 rank data
5587 10:02:17.540139 u2DelayCellTimex100 = 270/100 ps
5588 10:02:17.543515 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5589 10:02:17.549932 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5590 10:02:17.553394 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5591 10:02:17.556694 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5592 10:02:17.559632 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5593 10:02:17.562995 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5594 10:02:17.563552
5595 10:02:17.566021 CA PerBit enable=1, Macro0, CA PI delay=35
5596 10:02:17.566450
5597 10:02:17.569829 [CBTSetCACLKResult] CA Dly = 35
5598 10:02:17.573260 CS Dly: 7 (0~39)
5599 10:02:17.573782
5600 10:02:17.576090 ----->DramcWriteLeveling(PI) begin...
5601 10:02:17.576517 ==
5602 10:02:17.579820 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 10:02:17.583090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 10:02:17.583616 ==
5605 10:02:17.586604 Write leveling (Byte 0): 26 => 26
5606 10:02:17.589726 Write leveling (Byte 1): 31 => 31
5607 10:02:17.593147 DramcWriteLeveling(PI) end<-----
5608 10:02:17.593671
5609 10:02:17.594016 ==
5610 10:02:17.596093 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 10:02:17.599492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 10:02:17.600017 ==
5613 10:02:17.602483 [Gating] SW mode calibration
5614 10:02:17.609496 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5615 10:02:17.616287 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5616 10:02:17.619134 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 10:02:17.622525 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 10:02:17.629198 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 10:02:17.632312 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 10:02:17.635579 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 10:02:17.642771 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5622 10:02:17.645296 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5623 10:02:17.648894 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5624 10:02:17.655455 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 10:02:17.658352 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 10:02:17.662236 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 10:02:17.668359 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 10:02:17.671708 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 10:02:17.675347 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 10:02:17.682077 0 15 24 | B1->B0 | 2929 2e2e | 1 0 | (0 0) (0 0)
5631 10:02:17.684807 0 15 28 | B1->B0 | 3e3e 4141 | 0 0 | (1 1) (0 0)
5632 10:02:17.688312 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 10:02:17.694668 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 10:02:17.698307 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 10:02:17.701623 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 10:02:17.708280 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 10:02:17.711193 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 10:02:17.714786 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5639 10:02:17.721695 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 10:02:17.724965 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 10:02:17.728203 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 10:02:17.734626 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 10:02:17.738376 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 10:02:17.741669 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 10:02:17.747792 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 10:02:17.750988 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 10:02:17.754602 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 10:02:17.760862 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 10:02:17.764854 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 10:02:17.768402 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 10:02:17.774117 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 10:02:17.777677 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 10:02:17.780878 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 10:02:17.787295 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5655 10:02:17.790618 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 10:02:17.793985 Total UI for P1: 0, mck2ui 16
5657 10:02:17.797112 best dqsien dly found for B0: ( 1, 2, 24)
5658 10:02:17.800547 Total UI for P1: 0, mck2ui 16
5659 10:02:17.803807 best dqsien dly found for B1: ( 1, 2, 26)
5660 10:02:17.807376 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5661 10:02:17.810357 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5662 10:02:17.810987
5663 10:02:17.813916 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5664 10:02:17.817142 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5665 10:02:17.821225 [Gating] SW calibration Done
5666 10:02:17.821808 ==
5667 10:02:17.823892 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 10:02:17.827271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 10:02:17.831032 ==
5670 10:02:17.831606 RX Vref Scan: 0
5671 10:02:17.831978
5672 10:02:17.834519 RX Vref 0 -> 0, step: 1
5673 10:02:17.835093
5674 10:02:17.837265 RX Delay -80 -> 252, step: 8
5675 10:02:17.840654 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5676 10:02:17.843773 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5677 10:02:17.847307 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5678 10:02:17.850514 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5679 10:02:17.856934 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5680 10:02:17.860174 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5681 10:02:17.863469 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5682 10:02:17.866900 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5683 10:02:17.869946 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5684 10:02:17.873865 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5685 10:02:17.880113 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5686 10:02:17.883330 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5687 10:02:17.886424 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5688 10:02:17.889915 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5689 10:02:17.893151 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5690 10:02:17.899656 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5691 10:02:17.900228 ==
5692 10:02:17.903276 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 10:02:17.906293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 10:02:17.906772 ==
5695 10:02:17.907142 DQS Delay:
5696 10:02:17.909901 DQS0 = 0, DQS1 = 0
5697 10:02:17.910472 DQM Delay:
5698 10:02:17.912824 DQM0 = 102, DQM1 = 95
5699 10:02:17.913297 DQ Delay:
5700 10:02:17.916744 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =103
5701 10:02:17.920008 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5702 10:02:17.922986 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5703 10:02:17.927109 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5704 10:02:17.927685
5705 10:02:17.928053
5706 10:02:17.928390 ==
5707 10:02:17.929735 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 10:02:17.936680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 10:02:17.937287 ==
5710 10:02:17.937661
5711 10:02:17.938003
5712 10:02:17.938327 TX Vref Scan disable
5713 10:02:17.939646 == TX Byte 0 ==
5714 10:02:17.943783 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5715 10:02:17.949763 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5716 10:02:17.950340 == TX Byte 1 ==
5717 10:02:17.952852 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5718 10:02:17.959870 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5719 10:02:17.960448 ==
5720 10:02:17.963560 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 10:02:17.966032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 10:02:17.966506 ==
5723 10:02:17.966879
5724 10:02:17.967226
5725 10:02:17.969179 TX Vref Scan disable
5726 10:02:17.969645 == TX Byte 0 ==
5727 10:02:17.976158 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5728 10:02:17.979483 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5729 10:02:17.983424 == TX Byte 1 ==
5730 10:02:17.986018 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5731 10:02:17.989575 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5732 10:02:17.990155
5733 10:02:17.990527 [DATLAT]
5734 10:02:17.992391 Freq=933, CH1 RK0
5735 10:02:17.992900
5736 10:02:17.993289 DATLAT Default: 0xd
5737 10:02:17.995851 0, 0xFFFF, sum = 0
5738 10:02:17.999010 1, 0xFFFF, sum = 0
5739 10:02:17.999563 2, 0xFFFF, sum = 0
5740 10:02:18.002563 3, 0xFFFF, sum = 0
5741 10:02:18.003143 4, 0xFFFF, sum = 0
5742 10:02:18.005528 5, 0xFFFF, sum = 0
5743 10:02:18.006005 6, 0xFFFF, sum = 0
5744 10:02:18.008874 7, 0xFFFF, sum = 0
5745 10:02:18.009346 8, 0xFFFF, sum = 0
5746 10:02:18.012017 9, 0xFFFF, sum = 0
5747 10:02:18.012494 10, 0x0, sum = 1
5748 10:02:18.015832 11, 0x0, sum = 2
5749 10:02:18.016418 12, 0x0, sum = 3
5750 10:02:18.018789 13, 0x0, sum = 4
5751 10:02:18.019369 best_step = 11
5752 10:02:18.019741
5753 10:02:18.020082 ==
5754 10:02:18.022111 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 10:02:18.025447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 10:02:18.025921 ==
5757 10:02:18.028497 RX Vref Scan: 1
5758 10:02:18.029003
5759 10:02:18.032395 RX Vref 0 -> 0, step: 1
5760 10:02:18.033002
5761 10:02:18.033374 RX Delay -53 -> 252, step: 4
5762 10:02:18.035562
5763 10:02:18.036031 Set Vref, RX VrefLevel [Byte0]: 51
5764 10:02:18.039146 [Byte1]: 49
5765 10:02:18.043678
5766 10:02:18.044245 Final RX Vref Byte 0 = 51 to rank0
5767 10:02:18.047549 Final RX Vref Byte 1 = 49 to rank0
5768 10:02:18.050258 Final RX Vref Byte 0 = 51 to rank1
5769 10:02:18.053605 Final RX Vref Byte 1 = 49 to rank1==
5770 10:02:18.056884 Dram Type= 6, Freq= 0, CH_1, rank 0
5771 10:02:18.063696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 10:02:18.064269 ==
5773 10:02:18.064644 DQS Delay:
5774 10:02:18.066886 DQS0 = 0, DQS1 = 0
5775 10:02:18.067459 DQM Delay:
5776 10:02:18.067913 DQM0 = 104, DQM1 = 97
5777 10:02:18.069652 DQ Delay:
5778 10:02:18.073353 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5779 10:02:18.076224 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5780 10:02:18.080027 DQ8 =88, DQ9 =86, DQ10 =100, DQ11 =90
5781 10:02:18.083275 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =102
5782 10:02:18.083848
5783 10:02:18.084217
5784 10:02:18.093489 [DQSOSCAuto] RK0, (LSB)MR18= 0x1931, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5785 10:02:18.094057 CH1 RK0: MR19=505, MR18=1931
5786 10:02:18.099853 CH1_RK0: MR19=0x505, MR18=0x1931, DQSOSC=406, MR23=63, INC=65, DEC=43
5787 10:02:18.100461
5788 10:02:18.103014 ----->DramcWriteLeveling(PI) begin...
5789 10:02:18.103489 ==
5790 10:02:18.106062 Dram Type= 6, Freq= 0, CH_1, rank 1
5791 10:02:18.112716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 10:02:18.113297 ==
5793 10:02:18.116493 Write leveling (Byte 0): 27 => 27
5794 10:02:18.117096 Write leveling (Byte 1): 29 => 29
5795 10:02:18.119329 DramcWriteLeveling(PI) end<-----
5796 10:02:18.119864
5797 10:02:18.122948 ==
5798 10:02:18.123425 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 10:02:18.129548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 10:02:18.130129 ==
5801 10:02:18.133211 [Gating] SW mode calibration
5802 10:02:18.139562 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5803 10:02:18.143103 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5804 10:02:18.149615 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5805 10:02:18.152989 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 10:02:18.155956 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 10:02:18.162747 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 10:02:18.166140 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 10:02:18.168951 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 10:02:18.176228 0 14 24 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)
5811 10:02:18.179497 0 14 28 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
5812 10:02:18.182475 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 10:02:18.189400 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 10:02:18.192719 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 10:02:18.195538 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 10:02:18.202336 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 10:02:18.205408 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 10:02:18.208656 0 15 24 | B1->B0 | 3030 2a2a | 0 0 | (1 1) (1 1)
5819 10:02:18.215288 0 15 28 | B1->B0 | 3f3f 3b3b | 0 1 | (0 0) (0 0)
5820 10:02:18.218808 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5821 10:02:18.221771 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 10:02:18.228666 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 10:02:18.231929 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 10:02:18.235366 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 10:02:18.241424 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 10:02:18.245080 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5827 10:02:18.248388 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5828 10:02:18.255390 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 10:02:18.258181 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 10:02:18.261404 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 10:02:18.268380 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 10:02:18.271339 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 10:02:18.274836 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 10:02:18.281468 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 10:02:18.284884 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 10:02:18.288410 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 10:02:18.295253 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 10:02:18.297846 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 10:02:18.301582 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 10:02:18.308139 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 10:02:18.311098 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5842 10:02:18.314391 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5843 10:02:18.321089 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5844 10:02:18.321650 Total UI for P1: 0, mck2ui 16
5845 10:02:18.324091 best dqsien dly found for B1: ( 1, 2, 22)
5846 10:02:18.331026 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 10:02:18.334191 Total UI for P1: 0, mck2ui 16
5848 10:02:18.337474 best dqsien dly found for B0: ( 1, 2, 26)
5849 10:02:18.340654 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5850 10:02:18.344376 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5851 10:02:18.344985
5852 10:02:18.347435 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5853 10:02:18.350888 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5854 10:02:18.354473 [Gating] SW calibration Done
5855 10:02:18.355041 ==
5856 10:02:18.357298 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 10:02:18.361000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 10:02:18.361577 ==
5859 10:02:18.364170 RX Vref Scan: 0
5860 10:02:18.364737
5861 10:02:18.367249 RX Vref 0 -> 0, step: 1
5862 10:02:18.367869
5863 10:02:18.368254 RX Delay -80 -> 252, step: 8
5864 10:02:18.374327 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5865 10:02:18.377484 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5866 10:02:18.380928 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5867 10:02:18.384164 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5868 10:02:18.387402 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5869 10:02:18.394405 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5870 10:02:18.397168 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5871 10:02:18.400590 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5872 10:02:18.404314 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5873 10:02:18.407122 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5874 10:02:18.410724 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5875 10:02:18.417051 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5876 10:02:18.420628 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5877 10:02:18.423654 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5878 10:02:18.427287 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5879 10:02:18.430418 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5880 10:02:18.430895 ==
5881 10:02:18.433656 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 10:02:18.440296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 10:02:18.440929 ==
5884 10:02:18.441317 DQS Delay:
5885 10:02:18.443631 DQS0 = 0, DQS1 = 0
5886 10:02:18.444204 DQM Delay:
5887 10:02:18.444581 DQM0 = 102, DQM1 = 95
5888 10:02:18.447515 DQ Delay:
5889 10:02:18.450648 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5890 10:02:18.453718 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =103
5891 10:02:18.457164 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5892 10:02:18.460467 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =107
5893 10:02:18.461096
5894 10:02:18.461481
5895 10:02:18.461829 ==
5896 10:02:18.463602 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 10:02:18.467131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 10:02:18.467713 ==
5899 10:02:18.468089
5900 10:02:18.468435
5901 10:02:18.470382 TX Vref Scan disable
5902 10:02:18.473300 == TX Byte 0 ==
5903 10:02:18.476651 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5904 10:02:18.480067 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5905 10:02:18.483349 == TX Byte 1 ==
5906 10:02:18.487054 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5907 10:02:18.490363 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5908 10:02:18.490942 ==
5909 10:02:18.493314 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 10:02:18.499943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 10:02:18.500528 ==
5912 10:02:18.500964
5913 10:02:18.501318
5914 10:02:18.501648 TX Vref Scan disable
5915 10:02:18.504214 == TX Byte 0 ==
5916 10:02:18.507448 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5917 10:02:18.514231 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5918 10:02:18.514813 == TX Byte 1 ==
5919 10:02:18.517039 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5920 10:02:18.523735 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5921 10:02:18.524295
5922 10:02:18.524668 [DATLAT]
5923 10:02:18.525070 Freq=933, CH1 RK1
5924 10:02:18.525421
5925 10:02:18.527103 DATLAT Default: 0xb
5926 10:02:18.527577 0, 0xFFFF, sum = 0
5927 10:02:18.530515 1, 0xFFFF, sum = 0
5928 10:02:18.533568 2, 0xFFFF, sum = 0
5929 10:02:18.534041 3, 0xFFFF, sum = 0
5930 10:02:18.537403 4, 0xFFFF, sum = 0
5931 10:02:18.538020 5, 0xFFFF, sum = 0
5932 10:02:18.540471 6, 0xFFFF, sum = 0
5933 10:02:18.541107 7, 0xFFFF, sum = 0
5934 10:02:18.543658 8, 0xFFFF, sum = 0
5935 10:02:18.544225 9, 0xFFFF, sum = 0
5936 10:02:18.546797 10, 0x0, sum = 1
5937 10:02:18.547295 11, 0x0, sum = 2
5938 10:02:18.550362 12, 0x0, sum = 3
5939 10:02:18.550975 13, 0x0, sum = 4
5940 10:02:18.551359 best_step = 11
5941 10:02:18.554238
5942 10:02:18.554802 ==
5943 10:02:18.557291 Dram Type= 6, Freq= 0, CH_1, rank 1
5944 10:02:18.560363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5945 10:02:18.560959 ==
5946 10:02:18.561334 RX Vref Scan: 0
5947 10:02:18.561681
5948 10:02:18.563447 RX Vref 0 -> 0, step: 1
5949 10:02:18.564016
5950 10:02:18.566968 RX Delay -53 -> 252, step: 4
5951 10:02:18.573133 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5952 10:02:18.576682 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5953 10:02:18.580174 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5954 10:02:18.583621 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5955 10:02:18.586776 iDelay=199, Bit 4, Center 104 (23 ~ 186) 164
5956 10:02:18.590052 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5957 10:02:18.596666 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5958 10:02:18.600407 iDelay=199, Bit 7, Center 100 (19 ~ 182) 164
5959 10:02:18.603776 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5960 10:02:18.607305 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5961 10:02:18.610185 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5962 10:02:18.616395 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5963 10:02:18.620393 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5964 10:02:18.623392 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5965 10:02:18.626282 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5966 10:02:18.629634 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5967 10:02:18.632881 ==
5968 10:02:18.636390 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 10:02:18.639582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 10:02:18.640153 ==
5971 10:02:18.640525 DQS Delay:
5972 10:02:18.642826 DQS0 = 0, DQS1 = 0
5973 10:02:18.643391 DQM Delay:
5974 10:02:18.646521 DQM0 = 104, DQM1 = 97
5975 10:02:18.647217 DQ Delay:
5976 10:02:18.649479 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =102
5977 10:02:18.652791 DQ4 =104, DQ5 =114, DQ6 =112, DQ7 =100
5978 10:02:18.655996 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =92
5979 10:02:18.659421 DQ12 =104, DQ13 =104, DQ14 =106, DQ15 =106
5980 10:02:18.659988
5981 10:02:18.660356
5982 10:02:18.669439 [DQSOSCAuto] RK1, (LSB)MR18= 0x2603, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
5983 10:02:18.670005 CH1 RK1: MR19=505, MR18=2603
5984 10:02:18.676079 CH1_RK1: MR19=0x505, MR18=0x2603, DQSOSC=409, MR23=63, INC=64, DEC=43
5985 10:02:18.679679 [RxdqsGatingPostProcess] freq 933
5986 10:02:18.686170 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5987 10:02:18.689293 best DQS0 dly(2T, 0.5T) = (0, 10)
5988 10:02:18.692875 best DQS1 dly(2T, 0.5T) = (0, 10)
5989 10:02:18.696329 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5990 10:02:18.699175 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5991 10:02:18.702697 best DQS0 dly(2T, 0.5T) = (0, 10)
5992 10:02:18.705666 best DQS1 dly(2T, 0.5T) = (0, 10)
5993 10:02:18.709165 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5994 10:02:18.712252 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5995 10:02:18.712958 Pre-setting of DQS Precalculation
5996 10:02:18.719494 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5997 10:02:18.725555 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5998 10:02:18.732428 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5999 10:02:18.733050
6000 10:02:18.733425
6001 10:02:18.735563 [Calibration Summary] 1866 Mbps
6002 10:02:18.739106 CH 0, Rank 0
6003 10:02:18.739721 SW Impedance : PASS
6004 10:02:18.742435 DUTY Scan : NO K
6005 10:02:18.745369 ZQ Calibration : PASS
6006 10:02:18.746023 Jitter Meter : NO K
6007 10:02:18.748967 CBT Training : PASS
6008 10:02:18.752177 Write leveling : PASS
6009 10:02:18.752742 RX DQS gating : PASS
6010 10:02:18.755237 RX DQ/DQS(RDDQC) : PASS
6011 10:02:18.755824 TX DQ/DQS : PASS
6012 10:02:18.758838 RX DATLAT : PASS
6013 10:02:18.761971 RX DQ/DQS(Engine): PASS
6014 10:02:18.762439 TX OE : NO K
6015 10:02:18.765351 All Pass.
6016 10:02:18.765964
6017 10:02:18.766340 CH 0, Rank 1
6018 10:02:18.768493 SW Impedance : PASS
6019 10:02:18.769120 DUTY Scan : NO K
6020 10:02:18.772161 ZQ Calibration : PASS
6021 10:02:18.775136 Jitter Meter : NO K
6022 10:02:18.775598 CBT Training : PASS
6023 10:02:18.778986 Write leveling : PASS
6024 10:02:18.782176 RX DQS gating : PASS
6025 10:02:18.782742 RX DQ/DQS(RDDQC) : PASS
6026 10:02:18.785266 TX DQ/DQS : PASS
6027 10:02:18.788748 RX DATLAT : PASS
6028 10:02:18.789370 RX DQ/DQS(Engine): PASS
6029 10:02:18.791982 TX OE : NO K
6030 10:02:18.792551 All Pass.
6031 10:02:18.792971
6032 10:02:18.794819 CH 1, Rank 0
6033 10:02:18.795280 SW Impedance : PASS
6034 10:02:18.798812 DUTY Scan : NO K
6035 10:02:18.801821 ZQ Calibration : PASS
6036 10:02:18.802387 Jitter Meter : NO K
6037 10:02:18.805442 CBT Training : PASS
6038 10:02:18.808629 Write leveling : PASS
6039 10:02:18.809241 RX DQS gating : PASS
6040 10:02:18.812071 RX DQ/DQS(RDDQC) : PASS
6041 10:02:18.815004 TX DQ/DQS : PASS
6042 10:02:18.815573 RX DATLAT : PASS
6043 10:02:18.818181 RX DQ/DQS(Engine): PASS
6044 10:02:18.818753 TX OE : NO K
6045 10:02:18.821475 All Pass.
6046 10:02:18.821957
6047 10:02:18.822323 CH 1, Rank 1
6048 10:02:18.824635 SW Impedance : PASS
6049 10:02:18.825143 DUTY Scan : NO K
6050 10:02:18.828411 ZQ Calibration : PASS
6051 10:02:18.831942 Jitter Meter : NO K
6052 10:02:18.832511 CBT Training : PASS
6053 10:02:18.835354 Write leveling : PASS
6054 10:02:18.838697 RX DQS gating : PASS
6055 10:02:18.839302 RX DQ/DQS(RDDQC) : PASS
6056 10:02:18.841760 TX DQ/DQS : PASS
6057 10:02:18.844875 RX DATLAT : PASS
6058 10:02:18.845465 RX DQ/DQS(Engine): PASS
6059 10:02:18.847862 TX OE : NO K
6060 10:02:18.848435 All Pass.
6061 10:02:18.848837
6062 10:02:18.851381 DramC Write-DBI off
6063 10:02:18.854430 PER_BANK_REFRESH: Hybrid Mode
6064 10:02:18.854897 TX_TRACKING: ON
6065 10:02:18.864293 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6066 10:02:18.867930 [FAST_K] Save calibration result to emmc
6067 10:02:18.871111 dramc_set_vcore_voltage set vcore to 650000
6068 10:02:18.874433 Read voltage for 400, 6
6069 10:02:18.874898 Vio18 = 0
6070 10:02:18.875312 Vcore = 650000
6071 10:02:18.877947 Vdram = 0
6072 10:02:18.878408 Vddq = 0
6073 10:02:18.878771 Vmddr = 0
6074 10:02:18.884659 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6075 10:02:18.887418 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6076 10:02:18.891079 MEM_TYPE=3, freq_sel=20
6077 10:02:18.894531 sv_algorithm_assistance_LP4_800
6078 10:02:18.897902 ============ PULL DRAM RESETB DOWN ============
6079 10:02:18.901433 ========== PULL DRAM RESETB DOWN end =========
6080 10:02:18.907702 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6081 10:02:18.911134 ===================================
6082 10:02:18.914339 LPDDR4 DRAM CONFIGURATION
6083 10:02:18.917708 ===================================
6084 10:02:18.918281 EX_ROW_EN[0] = 0x0
6085 10:02:18.920914 EX_ROW_EN[1] = 0x0
6086 10:02:18.921474 LP4Y_EN = 0x0
6087 10:02:18.924475 WORK_FSP = 0x0
6088 10:02:18.925094 WL = 0x2
6089 10:02:18.927353 RL = 0x2
6090 10:02:18.927920 BL = 0x2
6091 10:02:18.930991 RPST = 0x0
6092 10:02:18.931557 RD_PRE = 0x0
6093 10:02:18.934234 WR_PRE = 0x1
6094 10:02:18.934802 WR_PST = 0x0
6095 10:02:18.937617 DBI_WR = 0x0
6096 10:02:18.938180 DBI_RD = 0x0
6097 10:02:18.941060 OTF = 0x1
6098 10:02:18.944466 ===================================
6099 10:02:18.947370 ===================================
6100 10:02:18.947851 ANA top config
6101 10:02:18.951118 ===================================
6102 10:02:18.953961 DLL_ASYNC_EN = 0
6103 10:02:18.957337 ALL_SLAVE_EN = 1
6104 10:02:18.960724 NEW_RANK_MODE = 1
6105 10:02:18.961334 DLL_IDLE_MODE = 1
6106 10:02:18.964189 LP45_APHY_COMB_EN = 1
6107 10:02:18.967528 TX_ODT_DIS = 1
6108 10:02:18.970474 NEW_8X_MODE = 1
6109 10:02:18.973673 ===================================
6110 10:02:18.976866 ===================================
6111 10:02:18.980427 data_rate = 800
6112 10:02:18.983660 CKR = 1
6113 10:02:18.984256 DQ_P2S_RATIO = 4
6114 10:02:18.987010 ===================================
6115 10:02:18.990381 CA_P2S_RATIO = 4
6116 10:02:18.993698 DQ_CA_OPEN = 0
6117 10:02:18.996909 DQ_SEMI_OPEN = 1
6118 10:02:19.000481 CA_SEMI_OPEN = 1
6119 10:02:19.003607 CA_FULL_RATE = 0
6120 10:02:19.004174 DQ_CKDIV4_EN = 0
6121 10:02:19.006856 CA_CKDIV4_EN = 1
6122 10:02:19.010794 CA_PREDIV_EN = 0
6123 10:02:19.013454 PH8_DLY = 0
6124 10:02:19.017133 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6125 10:02:19.020260 DQ_AAMCK_DIV = 0
6126 10:02:19.020861 CA_AAMCK_DIV = 0
6127 10:02:19.023654 CA_ADMCK_DIV = 4
6128 10:02:19.026756 DQ_TRACK_CA_EN = 0
6129 10:02:19.029804 CA_PICK = 800
6130 10:02:19.034272 CA_MCKIO = 400
6131 10:02:19.036883 MCKIO_SEMI = 400
6132 10:02:19.040376 PLL_FREQ = 3016
6133 10:02:19.040980 DQ_UI_PI_RATIO = 32
6134 10:02:19.043547 CA_UI_PI_RATIO = 32
6135 10:02:19.047261 ===================================
6136 10:02:19.050029 ===================================
6137 10:02:19.053295 memory_type:LPDDR4
6138 10:02:19.056335 GP_NUM : 10
6139 10:02:19.056883 SRAM_EN : 1
6140 10:02:19.059765 MD32_EN : 0
6141 10:02:19.063110 ===================================
6142 10:02:19.066269 [ANA_INIT] >>>>>>>>>>>>>>
6143 10:02:19.069824 <<<<<< [CONFIGURE PHASE]: ANA_TX
6144 10:02:19.073119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6145 10:02:19.076213 ===================================
6146 10:02:19.076685 data_rate = 800,PCW = 0X7400
6147 10:02:19.079503 ===================================
6148 10:02:19.083115 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6149 10:02:19.089648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6150 10:02:19.099767 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6151 10:02:19.106540 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6152 10:02:19.109597 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6153 10:02:19.113023 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6154 10:02:19.116368 [ANA_INIT] flow start
6155 10:02:19.116971 [ANA_INIT] PLL >>>>>>>>
6156 10:02:19.119508 [ANA_INIT] PLL <<<<<<<<
6157 10:02:19.122733 [ANA_INIT] MIDPI >>>>>>>>
6158 10:02:19.123308 [ANA_INIT] MIDPI <<<<<<<<
6159 10:02:19.125634 [ANA_INIT] DLL >>>>>>>>
6160 10:02:19.129745 [ANA_INIT] flow end
6161 10:02:19.132700 ============ LP4 DIFF to SE enter ============
6162 10:02:19.136043 ============ LP4 DIFF to SE exit ============
6163 10:02:19.139328 [ANA_INIT] <<<<<<<<<<<<<
6164 10:02:19.142723 [Flow] Enable top DCM control >>>>>
6165 10:02:19.145644 [Flow] Enable top DCM control <<<<<
6166 10:02:19.149350 Enable DLL master slave shuffle
6167 10:02:19.153297 ==============================================================
6168 10:02:19.156144 Gating Mode config
6169 10:02:19.162120 ==============================================================
6170 10:02:19.162683 Config description:
6171 10:02:19.172468 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6172 10:02:19.179004 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6173 10:02:19.182770 SELPH_MODE 0: By rank 1: By Phase
6174 10:02:19.189015 ==============================================================
6175 10:02:19.192112 GAT_TRACK_EN = 0
6176 10:02:19.195743 RX_GATING_MODE = 2
6177 10:02:19.198640 RX_GATING_TRACK_MODE = 2
6178 10:02:19.202374 SELPH_MODE = 1
6179 10:02:19.205361 PICG_EARLY_EN = 1
6180 10:02:19.208823 VALID_LAT_VALUE = 1
6181 10:02:19.212431 ==============================================================
6182 10:02:19.215801 Enter into Gating configuration >>>>
6183 10:02:19.218560 Exit from Gating configuration <<<<
6184 10:02:19.221806 Enter into DVFS_PRE_config >>>>>
6185 10:02:19.235158 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6186 10:02:19.238473 Exit from DVFS_PRE_config <<<<<
6187 10:02:19.241686 Enter into PICG configuration >>>>
6188 10:02:19.242264 Exit from PICG configuration <<<<
6189 10:02:19.245305 [RX_INPUT] configuration >>>>>
6190 10:02:19.248438 [RX_INPUT] configuration <<<<<
6191 10:02:19.254993 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6192 10:02:19.258133 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6193 10:02:19.265458 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6194 10:02:19.271554 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6195 10:02:19.277804 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6196 10:02:19.284314 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6197 10:02:19.287557 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6198 10:02:19.291142 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6199 10:02:19.297632 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6200 10:02:19.301171 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6201 10:02:19.304478 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6202 10:02:19.308018 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6203 10:02:19.311471 ===================================
6204 10:02:19.314141 LPDDR4 DRAM CONFIGURATION
6205 10:02:19.317680 ===================================
6206 10:02:19.321015 EX_ROW_EN[0] = 0x0
6207 10:02:19.321590 EX_ROW_EN[1] = 0x0
6208 10:02:19.324144 LP4Y_EN = 0x0
6209 10:02:19.324719 WORK_FSP = 0x0
6210 10:02:19.327229 WL = 0x2
6211 10:02:19.327700 RL = 0x2
6212 10:02:19.330735 BL = 0x2
6213 10:02:19.331311 RPST = 0x0
6214 10:02:19.334019 RD_PRE = 0x0
6215 10:02:19.337662 WR_PRE = 0x1
6216 10:02:19.338236 WR_PST = 0x0
6217 10:02:19.340634 DBI_WR = 0x0
6218 10:02:19.341239 DBI_RD = 0x0
6219 10:02:19.344347 OTF = 0x1
6220 10:02:19.347544 ===================================
6221 10:02:19.350603 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6222 10:02:19.354012 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6223 10:02:19.357336 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6224 10:02:19.360701 ===================================
6225 10:02:19.363608 LPDDR4 DRAM CONFIGURATION
6226 10:02:19.367453 ===================================
6227 10:02:19.370390 EX_ROW_EN[0] = 0x10
6228 10:02:19.370969 EX_ROW_EN[1] = 0x0
6229 10:02:19.373884 LP4Y_EN = 0x0
6230 10:02:19.374462 WORK_FSP = 0x0
6231 10:02:19.376816 WL = 0x2
6232 10:02:19.377288 RL = 0x2
6233 10:02:19.380389 BL = 0x2
6234 10:02:19.381238 RPST = 0x0
6235 10:02:19.383830 RD_PRE = 0x0
6236 10:02:19.386980 WR_PRE = 0x1
6237 10:02:19.387553 WR_PST = 0x0
6238 10:02:19.389947 DBI_WR = 0x0
6239 10:02:19.390454 DBI_RD = 0x0
6240 10:02:19.393363 OTF = 0x1
6241 10:02:19.396668 ===================================
6242 10:02:19.400242 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6243 10:02:19.405544 nWR fixed to 30
6244 10:02:19.408946 [ModeRegInit_LP4] CH0 RK0
6245 10:02:19.409584 [ModeRegInit_LP4] CH0 RK1
6246 10:02:19.411876 [ModeRegInit_LP4] CH1 RK0
6247 10:02:19.415185 [ModeRegInit_LP4] CH1 RK1
6248 10:02:19.415764 match AC timing 19
6249 10:02:19.422310 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6250 10:02:19.425419 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6251 10:02:19.428325 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6252 10:02:19.434795 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6253 10:02:19.438115 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6254 10:02:19.438689 ==
6255 10:02:19.441690 Dram Type= 6, Freq= 0, CH_0, rank 0
6256 10:02:19.445310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 10:02:19.445881 ==
6258 10:02:19.451690 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6259 10:02:19.458220 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6260 10:02:19.461961 [CA 0] Center 36 (8~64) winsize 57
6261 10:02:19.465211 [CA 1] Center 36 (8~64) winsize 57
6262 10:02:19.468352 [CA 2] Center 36 (8~64) winsize 57
6263 10:02:19.471491 [CA 3] Center 36 (8~64) winsize 57
6264 10:02:19.475615 [CA 4] Center 36 (8~64) winsize 57
6265 10:02:19.477788 [CA 5] Center 36 (8~64) winsize 57
6266 10:02:19.478257
6267 10:02:19.481147 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6268 10:02:19.481617
6269 10:02:19.484183 [CATrainingPosCal] consider 1 rank data
6270 10:02:19.487954 u2DelayCellTimex100 = 270/100 ps
6271 10:02:19.491131 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 10:02:19.494489 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 10:02:19.497881 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 10:02:19.500859 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 10:02:19.504602 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 10:02:19.508040 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 10:02:19.508617
6278 10:02:19.510667 CA PerBit enable=1, Macro0, CA PI delay=36
6279 10:02:19.514203
6280 10:02:19.514674 [CBTSetCACLKResult] CA Dly = 36
6281 10:02:19.517897 CS Dly: 1 (0~32)
6282 10:02:19.518472 ==
6283 10:02:19.520842 Dram Type= 6, Freq= 0, CH_0, rank 1
6284 10:02:19.524508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 10:02:19.525123 ==
6286 10:02:19.530703 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6287 10:02:19.537546 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6288 10:02:19.540864 [CA 0] Center 36 (8~64) winsize 57
6289 10:02:19.544355 [CA 1] Center 36 (8~64) winsize 57
6290 10:02:19.544956 [CA 2] Center 36 (8~64) winsize 57
6291 10:02:19.547868 [CA 3] Center 36 (8~64) winsize 57
6292 10:02:19.551732 [CA 4] Center 36 (8~64) winsize 57
6293 10:02:19.553900 [CA 5] Center 36 (8~64) winsize 57
6294 10:02:19.554372
6295 10:02:19.560718 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6296 10:02:19.561313
6297 10:02:19.564001 [CATrainingPosCal] consider 2 rank data
6298 10:02:19.567571 u2DelayCellTimex100 = 270/100 ps
6299 10:02:19.570415 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 10:02:19.573647 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 10:02:19.576887 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 10:02:19.580656 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 10:02:19.583990 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 10:02:19.587541 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 10:02:19.588114
6306 10:02:19.590328 CA PerBit enable=1, Macro0, CA PI delay=36
6307 10:02:19.590827
6308 10:02:19.593429 [CBTSetCACLKResult] CA Dly = 36
6309 10:02:19.596725 CS Dly: 1 (0~32)
6310 10:02:19.597374
6311 10:02:19.600110 ----->DramcWriteLeveling(PI) begin...
6312 10:02:19.600805 ==
6313 10:02:19.603161 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 10:02:19.606604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 10:02:19.607191 ==
6316 10:02:19.609761 Write leveling (Byte 0): 40 => 8
6317 10:02:19.613268 Write leveling (Byte 1): 32 => 0
6318 10:02:19.616919 DramcWriteLeveling(PI) end<-----
6319 10:02:19.617497
6320 10:02:19.617870 ==
6321 10:02:19.620316 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 10:02:19.623234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 10:02:19.623810 ==
6324 10:02:19.626340 [Gating] SW mode calibration
6325 10:02:19.633205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6326 10:02:19.639681 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6327 10:02:19.643148 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6328 10:02:19.649803 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6329 10:02:19.653116 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 10:02:19.656530 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6331 10:02:19.662814 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 10:02:19.666299 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 10:02:19.669445 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 10:02:19.675710 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 10:02:19.678865 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 10:02:19.682742 Total UI for P1: 0, mck2ui 16
6337 10:02:19.685903 best dqsien dly found for B0: ( 0, 14, 24)
6338 10:02:19.689217 Total UI for P1: 0, mck2ui 16
6339 10:02:19.692520 best dqsien dly found for B1: ( 0, 14, 24)
6340 10:02:19.695476 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6341 10:02:19.699116 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6342 10:02:19.699710
6343 10:02:19.702110 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6344 10:02:19.705828 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6345 10:02:19.708634 [Gating] SW calibration Done
6346 10:02:19.709136 ==
6347 10:02:19.712174 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 10:02:19.715250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 10:02:19.719080 ==
6350 10:02:19.719655 RX Vref Scan: 0
6351 10:02:19.720077
6352 10:02:19.722297 RX Vref 0 -> 0, step: 1
6353 10:02:19.722876
6354 10:02:19.725153 RX Delay -410 -> 252, step: 16
6355 10:02:19.728404 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6356 10:02:19.731942 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6357 10:02:19.735152 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6358 10:02:19.741953 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6359 10:02:19.745041 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6360 10:02:19.748158 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6361 10:02:19.751936 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6362 10:02:19.758201 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6363 10:02:19.761342 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6364 10:02:19.765100 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6365 10:02:19.767954 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6366 10:02:19.774939 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6367 10:02:19.778090 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6368 10:02:19.781381 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6369 10:02:19.788193 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6370 10:02:19.791280 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6371 10:02:19.791740 ==
6372 10:02:19.795191 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 10:02:19.797944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 10:02:19.798492 ==
6375 10:02:19.801133 DQS Delay:
6376 10:02:19.801594 DQS0 = 27, DQS1 = 35
6377 10:02:19.801978 DQM Delay:
6378 10:02:19.804641 DQM0 = 13, DQM1 = 6
6379 10:02:19.805131 DQ Delay:
6380 10:02:19.808516 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6381 10:02:19.811096 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6382 10:02:19.814700 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6383 10:02:19.817803 DQ12 =8, DQ13 =8, DQ14 =16, DQ15 =8
6384 10:02:19.818366
6385 10:02:19.818728
6386 10:02:19.819062 ==
6387 10:02:19.821074 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 10:02:19.824294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 10:02:19.827652 ==
6390 10:02:19.828115
6391 10:02:19.828491
6392 10:02:19.828877 TX Vref Scan disable
6393 10:02:19.830629 == TX Byte 0 ==
6394 10:02:19.834537 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 10:02:19.838083 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 10:02:19.841119 == TX Byte 1 ==
6397 10:02:19.844241 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6398 10:02:19.847591 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6399 10:02:19.848153 ==
6400 10:02:19.851057 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 10:02:19.857659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 10:02:19.858223 ==
6403 10:02:19.858590
6404 10:02:19.858925
6405 10:02:19.859245 TX Vref Scan disable
6406 10:02:19.860514 == TX Byte 0 ==
6407 10:02:19.864204 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 10:02:19.867386 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 10:02:19.870747 == TX Byte 1 ==
6410 10:02:19.874191 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6411 10:02:19.877505 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6412 10:02:19.878101
6413 10:02:19.880749 [DATLAT]
6414 10:02:19.881239 Freq=400, CH0 RK0
6415 10:02:19.881602
6416 10:02:19.884027 DATLAT Default: 0xf
6417 10:02:19.884588 0, 0xFFFF, sum = 0
6418 10:02:19.887561 1, 0xFFFF, sum = 0
6419 10:02:19.888133 2, 0xFFFF, sum = 0
6420 10:02:19.890415 3, 0xFFFF, sum = 0
6421 10:02:19.890990 4, 0xFFFF, sum = 0
6422 10:02:19.893702 5, 0xFFFF, sum = 0
6423 10:02:19.894172 6, 0xFFFF, sum = 0
6424 10:02:19.896944 7, 0xFFFF, sum = 0
6425 10:02:19.900207 8, 0xFFFF, sum = 0
6426 10:02:19.900812 9, 0xFFFF, sum = 0
6427 10:02:19.903629 10, 0xFFFF, sum = 0
6428 10:02:19.904097 11, 0xFFFF, sum = 0
6429 10:02:19.906765 12, 0xFFFF, sum = 0
6430 10:02:19.907272 13, 0x0, sum = 1
6431 10:02:19.910018 14, 0x0, sum = 2
6432 10:02:19.910496 15, 0x0, sum = 3
6433 10:02:19.913166 16, 0x0, sum = 4
6434 10:02:19.913715 best_step = 14
6435 10:02:19.914096
6436 10:02:19.914440 ==
6437 10:02:19.916618 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 10:02:19.920317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 10:02:19.920945 ==
6440 10:02:19.923449 RX Vref Scan: 1
6441 10:02:19.924073
6442 10:02:19.926785 RX Vref 0 -> 0, step: 1
6443 10:02:19.927258
6444 10:02:19.927633 RX Delay -311 -> 252, step: 8
6445 10:02:19.929896
6446 10:02:19.930367 Set Vref, RX VrefLevel [Byte0]: 59
6447 10:02:19.933015 [Byte1]: 49
6448 10:02:19.938897
6449 10:02:19.939483 Final RX Vref Byte 0 = 59 to rank0
6450 10:02:19.941924 Final RX Vref Byte 1 = 49 to rank0
6451 10:02:19.945363 Final RX Vref Byte 0 = 59 to rank1
6452 10:02:19.948520 Final RX Vref Byte 1 = 49 to rank1==
6453 10:02:19.951941 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 10:02:19.958674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 10:02:19.959262 ==
6456 10:02:19.959640 DQS Delay:
6457 10:02:19.962396 DQS0 = 28, DQS1 = 48
6458 10:02:19.962974 DQM Delay:
6459 10:02:19.963350 DQM0 = 12, DQM1 = 16
6460 10:02:19.965379 DQ Delay:
6461 10:02:19.968665 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6462 10:02:19.971902 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6463 10:02:19.975171 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6464 10:02:19.978360 DQ12 =24, DQ13 =16, DQ14 =28, DQ15 =24
6465 10:02:19.978836
6466 10:02:19.979208
6467 10:02:19.985192 [DQSOSCAuto] RK0, (LSB)MR18= 0xb4ab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6468 10:02:19.988180 CH0 RK0: MR19=C0C, MR18=B4AB
6469 10:02:19.994954 CH0_RK0: MR19=0xC0C, MR18=0xB4AB, DQSOSC=387, MR23=63, INC=394, DEC=262
6470 10:02:19.995534 ==
6471 10:02:19.998167 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 10:02:20.001477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 10:02:20.001954 ==
6474 10:02:20.004849 [Gating] SW mode calibration
6475 10:02:20.011576 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6476 10:02:20.017827 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6477 10:02:20.021126 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6478 10:02:20.024366 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6479 10:02:20.031350 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 10:02:20.034289 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6481 10:02:20.037793 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 10:02:20.044746 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 10:02:20.047607 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 10:02:20.051368 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 10:02:20.057790 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 10:02:20.060936 Total UI for P1: 0, mck2ui 16
6487 10:02:20.064606 best dqsien dly found for B0: ( 0, 14, 24)
6488 10:02:20.065223 Total UI for P1: 0, mck2ui 16
6489 10:02:20.070893 best dqsien dly found for B1: ( 0, 14, 24)
6490 10:02:20.074102 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6491 10:02:20.077484 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6492 10:02:20.078063
6493 10:02:20.080417 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6494 10:02:20.084251 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6495 10:02:20.087144 [Gating] SW calibration Done
6496 10:02:20.087723 ==
6497 10:02:20.090817 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 10:02:20.093945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 10:02:20.094524 ==
6500 10:02:20.097587 RX Vref Scan: 0
6501 10:02:20.098174
6502 10:02:20.100468 RX Vref 0 -> 0, step: 1
6503 10:02:20.101094
6504 10:02:20.101478 RX Delay -410 -> 252, step: 16
6505 10:02:20.107249 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6506 10:02:20.110656 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6507 10:02:20.114236 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6508 10:02:20.116894 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6509 10:02:20.123918 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6510 10:02:20.127156 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6511 10:02:20.130027 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6512 10:02:20.133749 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6513 10:02:20.140403 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6514 10:02:20.144028 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6515 10:02:20.146678 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6516 10:02:20.153647 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6517 10:02:20.156676 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6518 10:02:20.160201 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6519 10:02:20.163202 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6520 10:02:20.169840 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6521 10:02:20.170412 ==
6522 10:02:20.173173 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 10:02:20.176464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 10:02:20.177081 ==
6525 10:02:20.177467 DQS Delay:
6526 10:02:20.179900 DQS0 = 27, DQS1 = 43
6527 10:02:20.180370 DQM Delay:
6528 10:02:20.182814 DQM0 = 9, DQM1 = 16
6529 10:02:20.183287 DQ Delay:
6530 10:02:20.186751 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6531 10:02:20.189596 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6532 10:02:20.193136 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6533 10:02:20.196264 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6534 10:02:20.196870
6535 10:02:20.197248
6536 10:02:20.197599 ==
6537 10:02:20.199529 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 10:02:20.203079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 10:02:20.203659 ==
6540 10:02:20.204034
6541 10:02:20.206005
6542 10:02:20.206571 TX Vref Scan disable
6543 10:02:20.209337 == TX Byte 0 ==
6544 10:02:20.213252 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6545 10:02:20.216009 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6546 10:02:20.219745 == TX Byte 1 ==
6547 10:02:20.222736 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6548 10:02:20.226018 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6549 10:02:20.226592 ==
6550 10:02:20.228913 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 10:02:20.232257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 10:02:20.235890 ==
6553 10:02:20.236385
6554 10:02:20.236756
6555 10:02:20.237165 TX Vref Scan disable
6556 10:02:20.239267 == TX Byte 0 ==
6557 10:02:20.242132 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6558 10:02:20.245699 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6559 10:02:20.248934 == TX Byte 1 ==
6560 10:02:20.252321 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6561 10:02:20.255498 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6562 10:02:20.256025
6563 10:02:20.258907 [DATLAT]
6564 10:02:20.259486 Freq=400, CH0 RK1
6565 10:02:20.259862
6566 10:02:20.262040 DATLAT Default: 0xe
6567 10:02:20.262699 0, 0xFFFF, sum = 0
6568 10:02:20.265370 1, 0xFFFF, sum = 0
6569 10:02:20.265850 2, 0xFFFF, sum = 0
6570 10:02:20.268696 3, 0xFFFF, sum = 0
6571 10:02:20.269308 4, 0xFFFF, sum = 0
6572 10:02:20.272257 5, 0xFFFF, sum = 0
6573 10:02:20.272874 6, 0xFFFF, sum = 0
6574 10:02:20.275676 7, 0xFFFF, sum = 0
6575 10:02:20.276261 8, 0xFFFF, sum = 0
6576 10:02:20.278636 9, 0xFFFF, sum = 0
6577 10:02:20.279219 10, 0xFFFF, sum = 0
6578 10:02:20.281626 11, 0xFFFF, sum = 0
6579 10:02:20.282108 12, 0xFFFF, sum = 0
6580 10:02:20.285364 13, 0x0, sum = 1
6581 10:02:20.285844 14, 0x0, sum = 2
6582 10:02:20.288223 15, 0x0, sum = 3
6583 10:02:20.288701 16, 0x0, sum = 4
6584 10:02:20.291895 best_step = 14
6585 10:02:20.292462
6586 10:02:20.292877 ==
6587 10:02:20.295564 Dram Type= 6, Freq= 0, CH_0, rank 1
6588 10:02:20.298273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 10:02:20.298749 ==
6590 10:02:20.301522 RX Vref Scan: 0
6591 10:02:20.301990
6592 10:02:20.302360 RX Vref 0 -> 0, step: 1
6593 10:02:20.302708
6594 10:02:20.305258 RX Delay -327 -> 252, step: 8
6595 10:02:20.313621 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6596 10:02:20.316151 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6597 10:02:20.319723 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6598 10:02:20.326474 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6599 10:02:20.329568 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6600 10:02:20.333019 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6601 10:02:20.336553 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6602 10:02:20.339720 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6603 10:02:20.345931 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6604 10:02:20.349338 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6605 10:02:20.352570 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6606 10:02:20.359515 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6607 10:02:20.362801 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6608 10:02:20.366220 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6609 10:02:20.369242 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6610 10:02:20.375805 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6611 10:02:20.376393 ==
6612 10:02:20.379155 Dram Type= 6, Freq= 0, CH_0, rank 1
6613 10:02:20.382470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 10:02:20.382948 ==
6615 10:02:20.383321 DQS Delay:
6616 10:02:20.385575 DQS0 = 28, DQS1 = 44
6617 10:02:20.386045 DQM Delay:
6618 10:02:20.389938 DQM0 = 10, DQM1 = 15
6619 10:02:20.390511 DQ Delay:
6620 10:02:20.392156 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6621 10:02:20.395975 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6622 10:02:20.398987 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6623 10:02:20.402173 DQ12 =20, DQ13 =24, DQ14 =24, DQ15 =20
6624 10:02:20.402649
6625 10:02:20.403024
6626 10:02:20.409491 [DQSOSCAuto] RK1, (LSB)MR18= 0xc174, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 385 ps
6627 10:02:20.412953 CH0 RK1: MR19=C0C, MR18=C174
6628 10:02:20.419160 CH0_RK1: MR19=0xC0C, MR18=0xC174, DQSOSC=385, MR23=63, INC=398, DEC=265
6629 10:02:20.422604 [RxdqsGatingPostProcess] freq 400
6630 10:02:20.429032 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6631 10:02:20.432358 best DQS0 dly(2T, 0.5T) = (0, 10)
6632 10:02:20.432965 best DQS1 dly(2T, 0.5T) = (0, 10)
6633 10:02:20.435742 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6634 10:02:20.439180 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6635 10:02:20.442322 best DQS0 dly(2T, 0.5T) = (0, 10)
6636 10:02:20.445697 best DQS1 dly(2T, 0.5T) = (0, 10)
6637 10:02:20.448937 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6638 10:02:20.452235 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6639 10:02:20.455785 Pre-setting of DQS Precalculation
6640 10:02:20.462353 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6641 10:02:20.462955 ==
6642 10:02:20.465192 Dram Type= 6, Freq= 0, CH_1, rank 0
6643 10:02:20.468699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 10:02:20.469206 ==
6645 10:02:20.475402 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6646 10:02:20.481707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6647 10:02:20.482188 [CA 0] Center 36 (8~64) winsize 57
6648 10:02:20.485129 [CA 1] Center 36 (8~64) winsize 57
6649 10:02:20.488180 [CA 2] Center 36 (8~64) winsize 57
6650 10:02:20.491778 [CA 3] Center 36 (8~64) winsize 57
6651 10:02:20.495233 [CA 4] Center 36 (8~64) winsize 57
6652 10:02:20.497990 [CA 5] Center 36 (8~64) winsize 57
6653 10:02:20.498467
6654 10:02:20.501798 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6655 10:02:20.502271
6656 10:02:20.504967 [CATrainingPosCal] consider 1 rank data
6657 10:02:20.508270 u2DelayCellTimex100 = 270/100 ps
6658 10:02:20.511831 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 10:02:20.518242 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 10:02:20.521623 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 10:02:20.524855 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 10:02:20.528444 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 10:02:20.531618 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 10:02:20.532098
6665 10:02:20.534827 CA PerBit enable=1, Macro0, CA PI delay=36
6666 10:02:20.535409
6667 10:02:20.538104 [CBTSetCACLKResult] CA Dly = 36
6668 10:02:20.541447 CS Dly: 1 (0~32)
6669 10:02:20.542029 ==
6670 10:02:20.544429 Dram Type= 6, Freq= 0, CH_1, rank 1
6671 10:02:20.548049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 10:02:20.548631 ==
6673 10:02:20.555024 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6674 10:02:20.557785 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6675 10:02:20.560904 [CA 0] Center 36 (8~64) winsize 57
6676 10:02:20.564336 [CA 1] Center 36 (8~64) winsize 57
6677 10:02:20.567675 [CA 2] Center 36 (8~64) winsize 57
6678 10:02:20.571181 [CA 3] Center 36 (8~64) winsize 57
6679 10:02:20.574246 [CA 4] Center 36 (8~64) winsize 57
6680 10:02:20.577403 [CA 5] Center 36 (8~64) winsize 57
6681 10:02:20.577879
6682 10:02:20.580831 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6683 10:02:20.581310
6684 10:02:20.584012 [CATrainingPosCal] consider 2 rank data
6685 10:02:20.587341 u2DelayCellTimex100 = 270/100 ps
6686 10:02:20.591045 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 10:02:20.594272 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 10:02:20.597479 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 10:02:20.603863 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 10:02:20.607617 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 10:02:20.610397 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 10:02:20.610977
6693 10:02:20.613752 CA PerBit enable=1, Macro0, CA PI delay=36
6694 10:02:20.614328
6695 10:02:20.616986 [CBTSetCACLKResult] CA Dly = 36
6696 10:02:20.617460 CS Dly: 1 (0~32)
6697 10:02:20.617829
6698 10:02:20.620825 ----->DramcWriteLeveling(PI) begin...
6699 10:02:20.623802 ==
6700 10:02:20.627272 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 10:02:20.630522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 10:02:20.631002 ==
6703 10:02:20.633975 Write leveling (Byte 0): 40 => 8
6704 10:02:20.636982 Write leveling (Byte 1): 32 => 0
6705 10:02:20.640761 DramcWriteLeveling(PI) end<-----
6706 10:02:20.641372
6707 10:02:20.641742 ==
6708 10:02:20.643606 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 10:02:20.647037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 10:02:20.647619 ==
6711 10:02:20.650441 [Gating] SW mode calibration
6712 10:02:20.657229 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6713 10:02:20.663649 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6714 10:02:20.666676 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6715 10:02:20.669816 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6716 10:02:20.676567 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 10:02:20.680203 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6718 10:02:20.683079 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 10:02:20.690106 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 10:02:20.692975 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 10:02:20.696165 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 10:02:20.702646 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 10:02:20.703125 Total UI for P1: 0, mck2ui 16
6724 10:02:20.706517 best dqsien dly found for B0: ( 0, 14, 24)
6725 10:02:20.709976 Total UI for P1: 0, mck2ui 16
6726 10:02:20.713142 best dqsien dly found for B1: ( 0, 14, 24)
6727 10:02:20.719882 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6728 10:02:20.723288 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6729 10:02:20.723857
6730 10:02:20.726001 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6731 10:02:20.729665 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6732 10:02:20.732598 [Gating] SW calibration Done
6733 10:02:20.733118 ==
6734 10:02:20.736533 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 10:02:20.739423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 10:02:20.739995 ==
6737 10:02:20.742678 RX Vref Scan: 0
6738 10:02:20.743265
6739 10:02:20.743642 RX Vref 0 -> 0, step: 1
6740 10:02:20.743987
6741 10:02:20.745519 RX Delay -410 -> 252, step: 16
6742 10:02:20.752500 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6743 10:02:20.755840 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6744 10:02:20.759851 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6745 10:02:20.762183 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6746 10:02:20.769375 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6747 10:02:20.772244 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6748 10:02:20.775640 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6749 10:02:20.778684 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6750 10:02:20.785339 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6751 10:02:20.788882 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6752 10:02:20.792588 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6753 10:02:20.795216 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6754 10:02:20.802127 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6755 10:02:20.805133 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6756 10:02:20.808632 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6757 10:02:20.811769 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6758 10:02:20.815539 ==
6759 10:02:20.818664 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 10:02:20.821757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 10:02:20.822335 ==
6762 10:02:20.822705 DQS Delay:
6763 10:02:20.825442 DQS0 = 27, DQS1 = 43
6764 10:02:20.826020 DQM Delay:
6765 10:02:20.828974 DQM0 = 9, DQM1 = 17
6766 10:02:20.829564 DQ Delay:
6767 10:02:20.831644 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6768 10:02:20.835167 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =0
6769 10:02:20.838835 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6770 10:02:20.842168 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6771 10:02:20.842742
6772 10:02:20.843114
6773 10:02:20.843476 ==
6774 10:02:20.844919 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 10:02:20.848613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 10:02:20.849226 ==
6777 10:02:20.849599
6778 10:02:20.849939
6779 10:02:20.851784 TX Vref Scan disable
6780 10:02:20.852359 == TX Byte 0 ==
6781 10:02:20.859196 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 10:02:20.861410 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 10:02:20.861880 == TX Byte 1 ==
6784 10:02:20.867873 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6785 10:02:20.871387 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6786 10:02:20.871987 ==
6787 10:02:20.874717 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 10:02:20.878068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 10:02:20.878649 ==
6790 10:02:20.879023
6791 10:02:20.879366
6792 10:02:20.882543 TX Vref Scan disable
6793 10:02:20.884817 == TX Byte 0 ==
6794 10:02:20.887932 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 10:02:20.891416 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 10:02:20.892018 == TX Byte 1 ==
6797 10:02:20.898031 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6798 10:02:20.901023 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6799 10:02:20.901511
6800 10:02:20.901988 [DATLAT]
6801 10:02:20.904052 Freq=400, CH1 RK0
6802 10:02:20.904536
6803 10:02:20.905107 DATLAT Default: 0xf
6804 10:02:20.907451 0, 0xFFFF, sum = 0
6805 10:02:20.907943 1, 0xFFFF, sum = 0
6806 10:02:20.910888 2, 0xFFFF, sum = 0
6807 10:02:20.914872 3, 0xFFFF, sum = 0
6808 10:02:20.915394 4, 0xFFFF, sum = 0
6809 10:02:20.917566 5, 0xFFFF, sum = 0
6810 10:02:20.918059 6, 0xFFFF, sum = 0
6811 10:02:20.921166 7, 0xFFFF, sum = 0
6812 10:02:20.921657 8, 0xFFFF, sum = 0
6813 10:02:20.924929 9, 0xFFFF, sum = 0
6814 10:02:20.925511 10, 0xFFFF, sum = 0
6815 10:02:20.927733 11, 0xFFFF, sum = 0
6816 10:02:20.928226 12, 0xFFFF, sum = 0
6817 10:02:20.931068 13, 0x0, sum = 1
6818 10:02:20.931563 14, 0x0, sum = 2
6819 10:02:20.934084 15, 0x0, sum = 3
6820 10:02:20.934578 16, 0x0, sum = 4
6821 10:02:20.937485 best_step = 14
6822 10:02:20.937973
6823 10:02:20.938460 ==
6824 10:02:20.941077 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 10:02:20.943988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 10:02:20.944476 ==
6827 10:02:20.945075 RX Vref Scan: 1
6828 10:02:20.947999
6829 10:02:20.948587 RX Vref 0 -> 0, step: 1
6830 10:02:20.949118
6831 10:02:20.950623 RX Delay -327 -> 252, step: 8
6832 10:02:20.951107
6833 10:02:20.954309 Set Vref, RX VrefLevel [Byte0]: 51
6834 10:02:20.957762 [Byte1]: 49
6835 10:02:20.961595
6836 10:02:20.962173 Final RX Vref Byte 0 = 51 to rank0
6837 10:02:20.965499 Final RX Vref Byte 1 = 49 to rank0
6838 10:02:20.968444 Final RX Vref Byte 0 = 51 to rank1
6839 10:02:20.971997 Final RX Vref Byte 1 = 49 to rank1==
6840 10:02:20.974579 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 10:02:20.981331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 10:02:20.981900 ==
6843 10:02:20.982389 DQS Delay:
6844 10:02:20.984302 DQS0 = 32, DQS1 = 40
6845 10:02:20.985026 DQM Delay:
6846 10:02:20.985511 DQM0 = 12, DQM1 = 12
6847 10:02:20.987764 DQ Delay:
6848 10:02:20.991373 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6849 10:02:20.994319 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6850 10:02:20.994903 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6851 10:02:20.997662 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6852 10:02:21.001069
6853 10:02:21.001552
6854 10:02:21.007690 [DQSOSCAuto] RK0, (LSB)MR18= 0x9fd8, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 389 ps
6855 10:02:21.011087 CH1 RK0: MR19=C0C, MR18=9FD8
6856 10:02:21.017363 CH1_RK0: MR19=0xC0C, MR18=0x9FD8, DQSOSC=383, MR23=63, INC=402, DEC=268
6857 10:02:21.017920 ==
6858 10:02:21.020709 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 10:02:21.024059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 10:02:21.024549 ==
6861 10:02:21.027737 [Gating] SW mode calibration
6862 10:02:21.033940 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6863 10:02:21.041097 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6864 10:02:21.043992 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6865 10:02:21.047533 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6866 10:02:21.054274 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 10:02:21.057626 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6868 10:02:21.060898 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 10:02:21.067673 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 10:02:21.071112 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 10:02:21.073844 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 10:02:21.080614 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 10:02:21.081225 Total UI for P1: 0, mck2ui 16
6874 10:02:21.087013 best dqsien dly found for B0: ( 0, 14, 24)
6875 10:02:21.087579 Total UI for P1: 0, mck2ui 16
6876 10:02:21.093748 best dqsien dly found for B1: ( 0, 14, 24)
6877 10:02:21.096805 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6878 10:02:21.100714 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6879 10:02:21.101338
6880 10:02:21.103447 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6881 10:02:21.107549 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6882 10:02:21.110026 [Gating] SW calibration Done
6883 10:02:21.110499 ==
6884 10:02:21.113199 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 10:02:21.116721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 10:02:21.117563 ==
6887 10:02:21.119970 RX Vref Scan: 0
6888 10:02:21.120531
6889 10:02:21.120956 RX Vref 0 -> 0, step: 1
6890 10:02:21.121312
6891 10:02:21.123517 RX Delay -410 -> 252, step: 16
6892 10:02:21.129798 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6893 10:02:21.133198 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6894 10:02:21.136472 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6895 10:02:21.139887 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6896 10:02:21.146650 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6897 10:02:21.149920 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6898 10:02:21.153328 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6899 10:02:21.156654 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6900 10:02:21.163263 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6901 10:02:21.166577 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6902 10:02:21.169884 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6903 10:02:21.173419 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6904 10:02:21.180188 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6905 10:02:21.183098 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6906 10:02:21.186536 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6907 10:02:21.189624 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6908 10:02:21.193098 ==
6909 10:02:21.196755 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 10:02:21.199740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 10:02:21.200317 ==
6912 10:02:21.200948 DQS Delay:
6913 10:02:21.203110 DQS0 = 35, DQS1 = 35
6914 10:02:21.203685 DQM Delay:
6915 10:02:21.206108 DQM0 = 17, DQM1 = 12
6916 10:02:21.206594 DQ Delay:
6917 10:02:21.209439 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6918 10:02:21.213122 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6919 10:02:21.216853 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6920 10:02:21.219984 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =24
6921 10:02:21.220561
6922 10:02:21.221085
6923 10:02:21.221542 ==
6924 10:02:21.222583 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 10:02:21.226150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 10:02:21.226733 ==
6927 10:02:21.227219
6928 10:02:21.227671
6929 10:02:21.229346 TX Vref Scan disable
6930 10:02:21.229835 == TX Byte 0 ==
6931 10:02:21.236353 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6932 10:02:21.239682 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6933 10:02:21.240283 == TX Byte 1 ==
6934 10:02:21.246042 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6935 10:02:21.249223 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6936 10:02:21.249802 ==
6937 10:02:21.252879 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 10:02:21.256336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 10:02:21.256953 ==
6940 10:02:21.257448
6941 10:02:21.257900
6942 10:02:21.259946 TX Vref Scan disable
6943 10:02:21.262520 == TX Byte 0 ==
6944 10:02:21.265974 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6945 10:02:21.269076 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6946 10:02:21.272294 == TX Byte 1 ==
6947 10:02:21.275698 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6948 10:02:21.279276 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6949 10:02:21.279865
6950 10:02:21.280356 [DATLAT]
6951 10:02:21.282184 Freq=400, CH1 RK1
6952 10:02:21.282767
6953 10:02:21.283256 DATLAT Default: 0xe
6954 10:02:21.285731 0, 0xFFFF, sum = 0
6955 10:02:21.286445 1, 0xFFFF, sum = 0
6956 10:02:21.289151 2, 0xFFFF, sum = 0
6957 10:02:21.291939 3, 0xFFFF, sum = 0
6958 10:02:21.292533 4, 0xFFFF, sum = 0
6959 10:02:21.295966 5, 0xFFFF, sum = 0
6960 10:02:21.296555 6, 0xFFFF, sum = 0
6961 10:02:21.299507 7, 0xFFFF, sum = 0
6962 10:02:21.300093 8, 0xFFFF, sum = 0
6963 10:02:21.301856 9, 0xFFFF, sum = 0
6964 10:02:21.302353 10, 0xFFFF, sum = 0
6965 10:02:21.305238 11, 0xFFFF, sum = 0
6966 10:02:21.305829 12, 0xFFFF, sum = 0
6967 10:02:21.308301 13, 0x0, sum = 1
6968 10:02:21.308822 14, 0x0, sum = 2
6969 10:02:21.311893 15, 0x0, sum = 3
6970 10:02:21.312479 16, 0x0, sum = 4
6971 10:02:21.315131 best_step = 14
6972 10:02:21.315706
6973 10:02:21.316195 ==
6974 10:02:21.318247 Dram Type= 6, Freq= 0, CH_1, rank 1
6975 10:02:21.321894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6976 10:02:21.322476 ==
6977 10:02:21.325252 RX Vref Scan: 0
6978 10:02:21.325736
6979 10:02:21.326219 RX Vref 0 -> 0, step: 1
6980 10:02:21.326677
6981 10:02:21.328101 RX Delay -311 -> 252, step: 8
6982 10:02:21.335765 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6983 10:02:21.339186 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6984 10:02:21.342711 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6985 10:02:21.349005 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6986 10:02:21.352580 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6987 10:02:21.355351 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6988 10:02:21.359173 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6989 10:02:21.365529 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6990 10:02:21.368676 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6991 10:02:21.372229 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6992 10:02:21.375678 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6993 10:02:21.381779 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6994 10:02:21.385543 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6995 10:02:21.388192 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6996 10:02:21.394892 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6997 10:02:21.398276 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6998 10:02:21.398858 ==
6999 10:02:21.401323 Dram Type= 6, Freq= 0, CH_1, rank 1
7000 10:02:21.404948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7001 10:02:21.405435 ==
7002 10:02:21.408526 DQS Delay:
7003 10:02:21.409192 DQS0 = 32, DQS1 = 36
7004 10:02:21.409686 DQM Delay:
7005 10:02:21.411459 DQM0 = 11, DQM1 = 12
7006 10:02:21.412041 DQ Delay:
7007 10:02:21.414930 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7008 10:02:21.417846 DQ4 =16, DQ5 =20, DQ6 =20, DQ7 =8
7009 10:02:21.420962 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7010 10:02:21.424813 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =24
7011 10:02:21.425386
7012 10:02:21.425870
7013 10:02:21.434653 [DQSOSCAuto] RK1, (LSB)MR18= 0xab54, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7014 10:02:21.435226 CH1 RK1: MR19=C0C, MR18=AB54
7015 10:02:21.441242 CH1_RK1: MR19=0xC0C, MR18=0xAB54, DQSOSC=388, MR23=63, INC=392, DEC=261
7016 10:02:21.444567 [RxdqsGatingPostProcess] freq 400
7017 10:02:21.451064 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7018 10:02:21.454660 best DQS0 dly(2T, 0.5T) = (0, 10)
7019 10:02:21.457482 best DQS1 dly(2T, 0.5T) = (0, 10)
7020 10:02:21.461323 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7021 10:02:21.464128 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7022 10:02:21.467933 best DQS0 dly(2T, 0.5T) = (0, 10)
7023 10:02:21.471094 best DQS1 dly(2T, 0.5T) = (0, 10)
7024 10:02:21.474342 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7025 10:02:21.477566 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7026 10:02:21.478140 Pre-setting of DQS Precalculation
7027 10:02:21.484695 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7028 10:02:21.490972 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7029 10:02:21.497248 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7030 10:02:21.497823
7031 10:02:21.498193
7032 10:02:21.500545 [Calibration Summary] 800 Mbps
7033 10:02:21.503834 CH 0, Rank 0
7034 10:02:21.504297 SW Impedance : PASS
7035 10:02:21.506908 DUTY Scan : NO K
7036 10:02:21.510461 ZQ Calibration : PASS
7037 10:02:21.511020 Jitter Meter : NO K
7038 10:02:21.513846 CBT Training : PASS
7039 10:02:21.514412 Write leveling : PASS
7040 10:02:21.517174 RX DQS gating : PASS
7041 10:02:21.520988 RX DQ/DQS(RDDQC) : PASS
7042 10:02:21.521556 TX DQ/DQS : PASS
7043 10:02:21.523718 RX DATLAT : PASS
7044 10:02:21.527201 RX DQ/DQS(Engine): PASS
7045 10:02:21.527773 TX OE : NO K
7046 10:02:21.530687 All Pass.
7047 10:02:21.531279
7048 10:02:21.531710 CH 0, Rank 1
7049 10:02:21.534106 SW Impedance : PASS
7050 10:02:21.534584 DUTY Scan : NO K
7051 10:02:21.537160 ZQ Calibration : PASS
7052 10:02:21.540723 Jitter Meter : NO K
7053 10:02:21.541333 CBT Training : PASS
7054 10:02:21.543880 Write leveling : NO K
7055 10:02:21.546845 RX DQS gating : PASS
7056 10:02:21.547422 RX DQ/DQS(RDDQC) : PASS
7057 10:02:21.550346 TX DQ/DQS : PASS
7058 10:02:21.553556 RX DATLAT : PASS
7059 10:02:21.554136 RX DQ/DQS(Engine): PASS
7060 10:02:21.556796 TX OE : NO K
7061 10:02:21.557276 All Pass.
7062 10:02:21.557688
7063 10:02:21.560105 CH 1, Rank 0
7064 10:02:21.560674 SW Impedance : PASS
7065 10:02:21.563203 DUTY Scan : NO K
7066 10:02:21.566845 ZQ Calibration : PASS
7067 10:02:21.567419 Jitter Meter : NO K
7068 10:02:21.569932 CBT Training : PASS
7069 10:02:21.573492 Write leveling : PASS
7070 10:02:21.574098 RX DQS gating : PASS
7071 10:02:21.576724 RX DQ/DQS(RDDQC) : PASS
7072 10:02:21.577347 TX DQ/DQS : PASS
7073 10:02:21.579995 RX DATLAT : PASS
7074 10:02:21.583416 RX DQ/DQS(Engine): PASS
7075 10:02:21.583994 TX OE : NO K
7076 10:02:21.586405 All Pass.
7077 10:02:21.587062
7078 10:02:21.587498 CH 1, Rank 1
7079 10:02:21.589726 SW Impedance : PASS
7080 10:02:21.590195 DUTY Scan : NO K
7081 10:02:21.593466 ZQ Calibration : PASS
7082 10:02:21.596516 Jitter Meter : NO K
7083 10:02:21.597136 CBT Training : PASS
7084 10:02:21.599385 Write leveling : NO K
7085 10:02:21.603001 RX DQS gating : PASS
7086 10:02:21.603470 RX DQ/DQS(RDDQC) : PASS
7087 10:02:21.606233 TX DQ/DQS : PASS
7088 10:02:21.609692 RX DATLAT : PASS
7089 10:02:21.610265 RX DQ/DQS(Engine): PASS
7090 10:02:21.613284 TX OE : NO K
7091 10:02:21.613859 All Pass.
7092 10:02:21.614233
7093 10:02:21.616147 DramC Write-DBI off
7094 10:02:21.619373 PER_BANK_REFRESH: Hybrid Mode
7095 10:02:21.619895 TX_TRACKING: ON
7096 10:02:21.629664 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7097 10:02:21.632920 [FAST_K] Save calibration result to emmc
7098 10:02:21.636334 dramc_set_vcore_voltage set vcore to 725000
7099 10:02:21.639232 Read voltage for 1600, 0
7100 10:02:21.639703 Vio18 = 0
7101 10:02:21.640072 Vcore = 725000
7102 10:02:21.643165 Vdram = 0
7103 10:02:21.643734 Vddq = 0
7104 10:02:21.644108 Vmddr = 0
7105 10:02:21.649436 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7106 10:02:21.652630 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7107 10:02:21.656280 MEM_TYPE=3, freq_sel=13
7108 10:02:21.659286 sv_algorithm_assistance_LP4_3733
7109 10:02:21.662837 ============ PULL DRAM RESETB DOWN ============
7110 10:02:21.669248 ========== PULL DRAM RESETB DOWN end =========
7111 10:02:21.672933 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7112 10:02:21.675881 ===================================
7113 10:02:21.679414 LPDDR4 DRAM CONFIGURATION
7114 10:02:21.682608 ===================================
7115 10:02:21.683332 EX_ROW_EN[0] = 0x0
7116 10:02:21.685941 EX_ROW_EN[1] = 0x0
7117 10:02:21.686408 LP4Y_EN = 0x0
7118 10:02:21.689376 WORK_FSP = 0x1
7119 10:02:21.689846 WL = 0x5
7120 10:02:21.692623 RL = 0x5
7121 10:02:21.693240 BL = 0x2
7122 10:02:21.695897 RPST = 0x0
7123 10:02:21.696470 RD_PRE = 0x0
7124 10:02:21.699122 WR_PRE = 0x1
7125 10:02:21.699693 WR_PST = 0x1
7126 10:02:21.702124 DBI_WR = 0x0
7127 10:02:21.705373 DBI_RD = 0x0
7128 10:02:21.705842 OTF = 0x1
7129 10:02:21.709000 ===================================
7130 10:02:21.712480 ===================================
7131 10:02:21.713096 ANA top config
7132 10:02:21.715561 ===================================
7133 10:02:21.718726 DLL_ASYNC_EN = 0
7134 10:02:21.722291 ALL_SLAVE_EN = 0
7135 10:02:21.725568 NEW_RANK_MODE = 1
7136 10:02:21.729285 DLL_IDLE_MODE = 1
7137 10:02:21.729853 LP45_APHY_COMB_EN = 1
7138 10:02:21.732042 TX_ODT_DIS = 0
7139 10:02:21.735397 NEW_8X_MODE = 1
7140 10:02:21.738918 ===================================
7141 10:02:21.742127 ===================================
7142 10:02:21.745824 data_rate = 3200
7143 10:02:21.749074 CKR = 1
7144 10:02:21.749647 DQ_P2S_RATIO = 8
7145 10:02:21.752217 ===================================
7146 10:02:21.755193 CA_P2S_RATIO = 8
7147 10:02:21.758609 DQ_CA_OPEN = 0
7148 10:02:21.762303 DQ_SEMI_OPEN = 0
7149 10:02:21.765488 CA_SEMI_OPEN = 0
7150 10:02:21.768106 CA_FULL_RATE = 0
7151 10:02:21.768669 DQ_CKDIV4_EN = 0
7152 10:02:21.771889 CA_CKDIV4_EN = 0
7153 10:02:21.774618 CA_PREDIV_EN = 0
7154 10:02:21.778499 PH8_DLY = 12
7155 10:02:21.781610 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7156 10:02:21.784665 DQ_AAMCK_DIV = 4
7157 10:02:21.787817 CA_AAMCK_DIV = 4
7158 10:02:21.788515 CA_ADMCK_DIV = 4
7159 10:02:21.791451 DQ_TRACK_CA_EN = 0
7160 10:02:21.795041 CA_PICK = 1600
7161 10:02:21.798009 CA_MCKIO = 1600
7162 10:02:21.801462 MCKIO_SEMI = 0
7163 10:02:21.805143 PLL_FREQ = 3068
7164 10:02:21.808089 DQ_UI_PI_RATIO = 32
7165 10:02:21.808653 CA_UI_PI_RATIO = 0
7166 10:02:21.811408 ===================================
7167 10:02:21.814660 ===================================
7168 10:02:21.818508 memory_type:LPDDR4
7169 10:02:21.821720 GP_NUM : 10
7170 10:02:21.822283 SRAM_EN : 1
7171 10:02:21.824645 MD32_EN : 0
7172 10:02:21.827934 ===================================
7173 10:02:21.832097 [ANA_INIT] >>>>>>>>>>>>>>
7174 10:02:21.834533 <<<<<< [CONFIGURE PHASE]: ANA_TX
7175 10:02:21.838465 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7176 10:02:21.841478 ===================================
7177 10:02:21.842046 data_rate = 3200,PCW = 0X7600
7178 10:02:21.844432 ===================================
7179 10:02:21.847694 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7180 10:02:21.854458 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7181 10:02:21.861064 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7182 10:02:21.864910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7183 10:02:21.867821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7184 10:02:21.871419 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7185 10:02:21.874133 [ANA_INIT] flow start
7186 10:02:21.877120 [ANA_INIT] PLL >>>>>>>>
7187 10:02:21.877590 [ANA_INIT] PLL <<<<<<<<
7188 10:02:21.880502 [ANA_INIT] MIDPI >>>>>>>>
7189 10:02:21.883757 [ANA_INIT] MIDPI <<<<<<<<
7190 10:02:21.884329 [ANA_INIT] DLL >>>>>>>>
7191 10:02:21.887241 [ANA_INIT] DLL <<<<<<<<
7192 10:02:21.890896 [ANA_INIT] flow end
7193 10:02:21.893659 ============ LP4 DIFF to SE enter ============
7194 10:02:21.897158 ============ LP4 DIFF to SE exit ============
7195 10:02:21.900479 [ANA_INIT] <<<<<<<<<<<<<
7196 10:02:21.903433 [Flow] Enable top DCM control >>>>>
7197 10:02:21.906917 [Flow] Enable top DCM control <<<<<
7198 10:02:21.910128 Enable DLL master slave shuffle
7199 10:02:21.913610 ==============================================================
7200 10:02:21.916939 Gating Mode config
7201 10:02:21.923660 ==============================================================
7202 10:02:21.924227 Config description:
7203 10:02:21.933415 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7204 10:02:21.940119 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7205 10:02:21.947020 SELPH_MODE 0: By rank 1: By Phase
7206 10:02:21.949745 ==============================================================
7207 10:02:21.953364 GAT_TRACK_EN = 1
7208 10:02:21.956619 RX_GATING_MODE = 2
7209 10:02:21.960301 RX_GATING_TRACK_MODE = 2
7210 10:02:21.963265 SELPH_MODE = 1
7211 10:02:21.966463 PICG_EARLY_EN = 1
7212 10:02:21.969952 VALID_LAT_VALUE = 1
7213 10:02:21.976173 ==============================================================
7214 10:02:21.979850 Enter into Gating configuration >>>>
7215 10:02:21.982804 Exit from Gating configuration <<<<
7216 10:02:21.983334 Enter into DVFS_PRE_config >>>>>
7217 10:02:21.995831 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7218 10:02:21.999727 Exit from DVFS_PRE_config <<<<<
7219 10:02:22.002546 Enter into PICG configuration >>>>
7220 10:02:22.005657 Exit from PICG configuration <<<<
7221 10:02:22.006181 [RX_INPUT] configuration >>>>>
7222 10:02:22.009331 [RX_INPUT] configuration <<<<<
7223 10:02:22.016368 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7224 10:02:22.022403 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7225 10:02:22.025719 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7226 10:02:22.032677 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7227 10:02:22.039231 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7228 10:02:22.045985 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7229 10:02:22.049437 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7230 10:02:22.052564 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7231 10:02:22.059143 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7232 10:02:22.062459 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7233 10:02:22.065692 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7234 10:02:22.072461 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7235 10:02:22.075740 ===================================
7236 10:02:22.076304 LPDDR4 DRAM CONFIGURATION
7237 10:02:22.079076 ===================================
7238 10:02:22.082602 EX_ROW_EN[0] = 0x0
7239 10:02:22.083171 EX_ROW_EN[1] = 0x0
7240 10:02:22.085783 LP4Y_EN = 0x0
7241 10:02:22.086279 WORK_FSP = 0x1
7242 10:02:22.088874 WL = 0x5
7243 10:02:22.089468 RL = 0x5
7244 10:02:22.092106 BL = 0x2
7245 10:02:22.095225 RPST = 0x0
7246 10:02:22.095789 RD_PRE = 0x0
7247 10:02:22.098860 WR_PRE = 0x1
7248 10:02:22.099430 WR_PST = 0x1
7249 10:02:22.102047 DBI_WR = 0x0
7250 10:02:22.102511 DBI_RD = 0x0
7251 10:02:22.105461 OTF = 0x1
7252 10:02:22.108583 ===================================
7253 10:02:22.111758 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7254 10:02:22.115005 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7255 10:02:22.118502 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7256 10:02:22.121969 ===================================
7257 10:02:22.124831 LPDDR4 DRAM CONFIGURATION
7258 10:02:22.128600 ===================================
7259 10:02:22.131825 EX_ROW_EN[0] = 0x10
7260 10:02:22.132417 EX_ROW_EN[1] = 0x0
7261 10:02:22.134853 LP4Y_EN = 0x0
7262 10:02:22.135338 WORK_FSP = 0x1
7263 10:02:22.138389 WL = 0x5
7264 10:02:22.138984 RL = 0x5
7265 10:02:22.141609 BL = 0x2
7266 10:02:22.145274 RPST = 0x0
7267 10:02:22.145868 RD_PRE = 0x0
7268 10:02:22.148156 WR_PRE = 0x1
7269 10:02:22.148640 WR_PST = 0x1
7270 10:02:22.151419 DBI_WR = 0x0
7271 10:02:22.151904 DBI_RD = 0x0
7272 10:02:22.155145 OTF = 0x1
7273 10:02:22.158566 ===================================
7274 10:02:22.161471 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7275 10:02:22.164807 ==
7276 10:02:22.168366 Dram Type= 6, Freq= 0, CH_0, rank 0
7277 10:02:22.171416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7278 10:02:22.171909 ==
7279 10:02:22.175149 [Duty_Offset_Calibration]
7280 10:02:22.175740 B0:2 B1:0 CA:1
7281 10:02:22.176235
7282 10:02:22.177627 [DutyScan_Calibration_Flow] k_type=0
7283 10:02:22.187644
7284 10:02:22.188233 ==CLK 0==
7285 10:02:22.190511 Final CLK duty delay cell = -4
7286 10:02:22.193911 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7287 10:02:22.196865 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7288 10:02:22.200406 [-4] AVG Duty = 4906%(X100)
7289 10:02:22.201057
7290 10:02:22.204394 CH0 CLK Duty spec in!! Max-Min= 187%
7291 10:02:22.207148 [DutyScan_Calibration_Flow] ====Done====
7292 10:02:22.207756
7293 10:02:22.210479 [DutyScan_Calibration_Flow] k_type=1
7294 10:02:22.226974
7295 10:02:22.227564 ==DQS 0 ==
7296 10:02:22.229949 Final DQS duty delay cell = 0
7297 10:02:22.232914 [0] MAX Duty = 5249%(X100), DQS PI = 34
7298 10:02:22.236484 [0] MIN Duty = 4969%(X100), DQS PI = 0
7299 10:02:22.240642 [0] AVG Duty = 5109%(X100)
7300 10:02:22.241277
7301 10:02:22.241767 ==DQS 1 ==
7302 10:02:22.243935 Final DQS duty delay cell = -4
7303 10:02:22.247236 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7304 10:02:22.249725 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7305 10:02:22.253449 [-4] AVG Duty = 4984%(X100)
7306 10:02:22.254043
7307 10:02:22.256809 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7308 10:02:22.257405
7309 10:02:22.260233 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7310 10:02:22.263292 [DutyScan_Calibration_Flow] ====Done====
7311 10:02:22.263885
7312 10:02:22.266882 [DutyScan_Calibration_Flow] k_type=3
7313 10:02:22.284297
7314 10:02:22.284922 ==DQM 0 ==
7315 10:02:22.287413 Final DQM duty delay cell = 0
7316 10:02:22.290381 [0] MAX Duty = 5093%(X100), DQS PI = 26
7317 10:02:22.293900 [0] MIN Duty = 4844%(X100), DQS PI = 0
7318 10:02:22.297445 [0] AVG Duty = 4968%(X100)
7319 10:02:22.298039
7320 10:02:22.298530 ==DQM 1 ==
7321 10:02:22.300276 Final DQM duty delay cell = 0
7322 10:02:22.304734 [0] MAX Duty = 5249%(X100), DQS PI = 44
7323 10:02:22.307126 [0] MIN Duty = 5031%(X100), DQS PI = 20
7324 10:02:22.310805 [0] AVG Duty = 5140%(X100)
7325 10:02:22.311368
7326 10:02:22.313980 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7327 10:02:22.314449
7328 10:02:22.317072 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7329 10:02:22.320319 [DutyScan_Calibration_Flow] ====Done====
7330 10:02:22.320837
7331 10:02:22.323929 [DutyScan_Calibration_Flow] k_type=2
7332 10:02:22.341465
7333 10:02:22.342043 ==DQ 0 ==
7334 10:02:22.344538 Final DQ duty delay cell = 0
7335 10:02:22.348170 [0] MAX Duty = 5156%(X100), DQS PI = 38
7336 10:02:22.351440 [0] MIN Duty = 5000%(X100), DQS PI = 0
7337 10:02:22.352009 [0] AVG Duty = 5078%(X100)
7338 10:02:22.354956
7339 10:02:22.355522 ==DQ 1 ==
7340 10:02:22.357518 Final DQ duty delay cell = 0
7341 10:02:22.361513 [0] MAX Duty = 4969%(X100), DQS PI = 28
7342 10:02:22.364617 [0] MIN Duty = 4875%(X100), DQS PI = 10
7343 10:02:22.365225 [0] AVG Duty = 4922%(X100)
7344 10:02:22.367804
7345 10:02:22.371057 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7346 10:02:22.371625
7347 10:02:22.374526 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7348 10:02:22.377628 [DutyScan_Calibration_Flow] ====Done====
7349 10:02:22.378194 ==
7350 10:02:22.381205 Dram Type= 6, Freq= 0, CH_1, rank 0
7351 10:02:22.384578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7352 10:02:22.385187 ==
7353 10:02:22.388012 [Duty_Offset_Calibration]
7354 10:02:22.388579 B0:0 B1:-1 CA:2
7355 10:02:22.388996
7356 10:02:22.390753 [DutyScan_Calibration_Flow] k_type=0
7357 10:02:22.401752
7358 10:02:22.402314 ==CLK 0==
7359 10:02:22.405635 Final CLK duty delay cell = 0
7360 10:02:22.408071 [0] MAX Duty = 5156%(X100), DQS PI = 8
7361 10:02:22.411690 [0] MIN Duty = 4938%(X100), DQS PI = 44
7362 10:02:22.412149 [0] AVG Duty = 5047%(X100)
7363 10:02:22.414308
7364 10:02:22.417609 CH1 CLK Duty spec in!! Max-Min= 218%
7365 10:02:22.421321 [DutyScan_Calibration_Flow] ====Done====
7366 10:02:22.421776
7367 10:02:22.424625 [DutyScan_Calibration_Flow] k_type=1
7368 10:02:22.440730
7369 10:02:22.441211 ==DQS 0 ==
7370 10:02:22.444506 Final DQS duty delay cell = 0
7371 10:02:22.447665 [0] MAX Duty = 5124%(X100), DQS PI = 42
7372 10:02:22.450858 [0] MIN Duty = 4969%(X100), DQS PI = 0
7373 10:02:22.454008 [0] AVG Duty = 5046%(X100)
7374 10:02:22.454470
7375 10:02:22.454828 ==DQS 1 ==
7376 10:02:22.457601 Final DQS duty delay cell = 0
7377 10:02:22.460654 [0] MAX Duty = 5187%(X100), DQS PI = 0
7378 10:02:22.463894 [0] MIN Duty = 4844%(X100), DQS PI = 34
7379 10:02:22.467862 [0] AVG Duty = 5015%(X100)
7380 10:02:22.468318
7381 10:02:22.470596 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7382 10:02:22.471052
7383 10:02:22.474039 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7384 10:02:22.477315 [DutyScan_Calibration_Flow] ====Done====
7385 10:02:22.477872
7386 10:02:22.480662 [DutyScan_Calibration_Flow] k_type=3
7387 10:02:22.499029
7388 10:02:22.499577 ==DQM 0 ==
7389 10:02:22.502070 Final DQM duty delay cell = 4
7390 10:02:22.505095 [4] MAX Duty = 5156%(X100), DQS PI = 24
7391 10:02:22.508719 [4] MIN Duty = 4938%(X100), DQS PI = 48
7392 10:02:22.511922 [4] AVG Duty = 5047%(X100)
7393 10:02:22.512472
7394 10:02:22.512888 ==DQM 1 ==
7395 10:02:22.515479 Final DQM duty delay cell = 0
7396 10:02:22.518697 [0] MAX Duty = 5281%(X100), DQS PI = 58
7397 10:02:22.521497 [0] MIN Duty = 4876%(X100), DQS PI = 34
7398 10:02:22.524999 [0] AVG Duty = 5078%(X100)
7399 10:02:22.525559
7400 10:02:22.528837 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7401 10:02:22.529417
7402 10:02:22.532031 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7403 10:02:22.535190 [DutyScan_Calibration_Flow] ====Done====
7404 10:02:22.535649
7405 10:02:22.538086 [DutyScan_Calibration_Flow] k_type=2
7406 10:02:22.555621
7407 10:02:22.556169 ==DQ 0 ==
7408 10:02:22.558893 Final DQ duty delay cell = 0
7409 10:02:22.562088 [0] MAX Duty = 5062%(X100), DQS PI = 16
7410 10:02:22.565936 [0] MIN Duty = 4969%(X100), DQS PI = 46
7411 10:02:22.566493 [0] AVG Duty = 5015%(X100)
7412 10:02:22.569125
7413 10:02:22.569675 ==DQ 1 ==
7414 10:02:22.572127 Final DQ duty delay cell = 0
7415 10:02:22.575685 [0] MAX Duty = 5062%(X100), DQS PI = 2
7416 10:02:22.578897 [0] MIN Duty = 4844%(X100), DQS PI = 32
7417 10:02:22.579449 [0] AVG Duty = 4953%(X100)
7418 10:02:22.581958
7419 10:02:22.585287 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7420 10:02:22.585865
7421 10:02:22.588550 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7422 10:02:22.592252 [DutyScan_Calibration_Flow] ====Done====
7423 10:02:22.595269 nWR fixed to 30
7424 10:02:22.595842 [ModeRegInit_LP4] CH0 RK0
7425 10:02:22.598314 [ModeRegInit_LP4] CH0 RK1
7426 10:02:22.601640 [ModeRegInit_LP4] CH1 RK0
7427 10:02:22.604944 [ModeRegInit_LP4] CH1 RK1
7428 10:02:22.605505 match AC timing 5
7429 10:02:22.611812 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7430 10:02:22.615252 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7431 10:02:22.618780 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7432 10:02:22.625086 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7433 10:02:22.628336 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7434 10:02:22.628950 [MiockJmeterHQA]
7435 10:02:22.629328
7436 10:02:22.632666 [DramcMiockJmeter] u1RxGatingPI = 0
7437 10:02:22.634863 0 : 4255, 4027
7438 10:02:22.635337 4 : 4253, 4026
7439 10:02:22.638408 8 : 4252, 4027
7440 10:02:22.638885 12 : 4363, 4137
7441 10:02:22.639259 16 : 4252, 4027
7442 10:02:22.641819 20 : 4252, 4027
7443 10:02:22.642407 24 : 4252, 4027
7444 10:02:22.644873 28 : 4363, 4137
7445 10:02:22.645446 32 : 4252, 4027
7446 10:02:22.648590 36 : 4363, 4137
7447 10:02:22.649212 40 : 4250, 4026
7448 10:02:22.651654 44 : 4252, 4027
7449 10:02:22.652232 48 : 4253, 4026
7450 10:02:22.652618 52 : 4252, 4027
7451 10:02:22.655385 56 : 4363, 4137
7452 10:02:22.655958 60 : 4250, 4026
7453 10:02:22.658562 64 : 4361, 4138
7454 10:02:22.659140 68 : 4250, 4026
7455 10:02:22.661449 72 : 4250, 4027
7456 10:02:22.661926 76 : 4250, 4027
7457 10:02:22.662300 80 : 4360, 4137
7458 10:02:22.664870 84 : 4250, 4027
7459 10:02:22.665444 88 : 4363, 3196
7460 10:02:22.668362 92 : 4250, 0
7461 10:02:22.668987 96 : 4250, 0
7462 10:02:22.669368 100 : 4249, 0
7463 10:02:22.671419 104 : 4250, 0
7464 10:02:22.671994 108 : 4250, 0
7465 10:02:22.674487 112 : 4250, 0
7466 10:02:22.674962 116 : 4250, 0
7467 10:02:22.675334 120 : 4250, 0
7468 10:02:22.678367 124 : 4361, 0
7469 10:02:22.678943 128 : 4360, 0
7470 10:02:22.681393 132 : 4248, 0
7471 10:02:22.681962 136 : 4252, 0
7472 10:02:22.682339 140 : 4361, 0
7473 10:02:22.684950 144 : 4361, 0
7474 10:02:22.685519 148 : 4253, 0
7475 10:02:22.688085 152 : 4250, 0
7476 10:02:22.688658 156 : 4250, 0
7477 10:02:22.689091 160 : 4250, 0
7478 10:02:22.691252 164 : 4250, 0
7479 10:02:22.691723 168 : 4250, 0
7480 10:02:22.692095 172 : 4250, 0
7481 10:02:22.694488 176 : 4361, 0
7482 10:02:22.694960 180 : 4360, 0
7483 10:02:22.697668 184 : 4250, 0
7484 10:02:22.698175 188 : 4361, 0
7485 10:02:22.698555 192 : 4360, 0
7486 10:02:22.700979 196 : 4363, 0
7487 10:02:22.701449 200 : 4250, 5
7488 10:02:22.704326 204 : 4250, 2392
7489 10:02:22.704860 208 : 4250, 4027
7490 10:02:22.708219 212 : 4250, 4027
7491 10:02:22.708838 216 : 4250, 4027
7492 10:02:22.711111 220 : 4360, 4137
7493 10:02:22.711684 224 : 4361, 4138
7494 10:02:22.714439 228 : 4247, 4025
7495 10:02:22.715011 232 : 4361, 4138
7496 10:02:22.717418 236 : 4360, 4137
7497 10:02:22.717889 240 : 4250, 4026
7498 10:02:22.718266 244 : 4250, 4027
7499 10:02:22.720941 248 : 4250, 4027
7500 10:02:22.721434 252 : 4250, 4027
7501 10:02:22.724355 256 : 4250, 4026
7502 10:02:22.724969 260 : 4250, 4027
7503 10:02:22.727408 264 : 4250, 4027
7504 10:02:22.727987 268 : 4250, 4027
7505 10:02:22.731163 272 : 4360, 4137
7506 10:02:22.731744 276 : 4361, 4137
7507 10:02:22.734392 280 : 4247, 4025
7508 10:02:22.735031 284 : 4361, 4138
7509 10:02:22.737194 288 : 4360, 4137
7510 10:02:22.737676 292 : 4250, 4026
7511 10:02:22.741338 296 : 4250, 4027
7512 10:02:22.741912 300 : 4250, 4027
7513 10:02:22.744118 304 : 4250, 4027
7514 10:02:22.744600 308 : 4250, 4026
7515 10:02:22.745032 312 : 4250, 3809
7516 10:02:22.747450 316 : 4250, 2057
7517 10:02:22.748032
7518 10:02:22.750736 MIOCK jitter meter ch=0
7519 10:02:22.751325
7520 10:02:22.753943 1T = (316-92) = 224 dly cells
7521 10:02:22.757374 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7522 10:02:22.757943 ==
7523 10:02:22.760446 Dram Type= 6, Freq= 0, CH_0, rank 0
7524 10:02:22.766898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7525 10:02:22.767495 ==
7526 10:02:22.769997 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7527 10:02:22.776534 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7528 10:02:22.779875 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7529 10:02:22.787025 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7530 10:02:22.794547 [CA 0] Center 42 (12~72) winsize 61
7531 10:02:22.797656 [CA 1] Center 42 (13~72) winsize 60
7532 10:02:22.800877 [CA 2] Center 37 (7~67) winsize 61
7533 10:02:22.804207 [CA 3] Center 37 (7~67) winsize 61
7534 10:02:22.807833 [CA 4] Center 36 (6~66) winsize 61
7535 10:02:22.810396 [CA 5] Center 35 (5~65) winsize 61
7536 10:02:22.810871
7537 10:02:22.814368 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7538 10:02:22.814945
7539 10:02:22.820652 [CATrainingPosCal] consider 1 rank data
7540 10:02:22.821412 u2DelayCellTimex100 = 290/100 ps
7541 10:02:22.827424 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7542 10:02:22.830940 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7543 10:02:22.833859 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7544 10:02:22.836940 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7545 10:02:22.840626 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7546 10:02:22.843843 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7547 10:02:22.844417
7548 10:02:22.847052 CA PerBit enable=1, Macro0, CA PI delay=35
7549 10:02:22.847628
7550 10:02:22.850411 [CBTSetCACLKResult] CA Dly = 35
7551 10:02:22.853672 CS Dly: 9 (0~40)
7552 10:02:22.857087 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7553 10:02:22.860343 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7554 10:02:22.860946 ==
7555 10:02:22.863813 Dram Type= 6, Freq= 0, CH_0, rank 1
7556 10:02:22.870582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 10:02:22.871191 ==
7558 10:02:22.873399 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7559 10:02:22.880254 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7560 10:02:22.883465 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7561 10:02:22.889918 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7562 10:02:22.897691 [CA 0] Center 43 (13~73) winsize 61
7563 10:02:22.900989 [CA 1] Center 43 (13~73) winsize 61
7564 10:02:22.904371 [CA 2] Center 38 (9~67) winsize 59
7565 10:02:22.907645 [CA 3] Center 38 (8~68) winsize 61
7566 10:02:22.910942 [CA 4] Center 37 (7~67) winsize 61
7567 10:02:22.914360 [CA 5] Center 36 (6~66) winsize 61
7568 10:02:22.914927
7569 10:02:22.917374 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7570 10:02:22.917850
7571 10:02:22.920829 [CATrainingPosCal] consider 2 rank data
7572 10:02:22.923837 u2DelayCellTimex100 = 290/100 ps
7573 10:02:22.930592 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7574 10:02:22.934432 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7575 10:02:22.937306 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7576 10:02:22.940850 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7577 10:02:22.944099 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7578 10:02:22.947561 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7579 10:02:22.948129
7580 10:02:22.950793 CA PerBit enable=1, Macro0, CA PI delay=35
7581 10:02:22.951364
7582 10:02:22.953550 [CBTSetCACLKResult] CA Dly = 35
7583 10:02:22.957171 CS Dly: 10 (0~43)
7584 10:02:22.960493 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7585 10:02:22.963776 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7586 10:02:22.964341
7587 10:02:22.966724 ----->DramcWriteLeveling(PI) begin...
7588 10:02:22.967300 ==
7589 10:02:22.970463 Dram Type= 6, Freq= 0, CH_0, rank 0
7590 10:02:22.976430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 10:02:22.976993 ==
7592 10:02:22.980205 Write leveling (Byte 0): 36 => 36
7593 10:02:22.982990 Write leveling (Byte 1): 33 => 33
7594 10:02:22.983468 DramcWriteLeveling(PI) end<-----
7595 10:02:22.987119
7596 10:02:22.987699 ==
7597 10:02:22.989711 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 10:02:22.993387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 10:02:22.993959 ==
7600 10:02:22.996476 [Gating] SW mode calibration
7601 10:02:23.003328 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7602 10:02:23.006056 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7603 10:02:23.013373 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 10:02:23.016490 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 10:02:23.019564 1 4 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
7606 10:02:23.026538 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7607 10:02:23.029434 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7608 10:02:23.032862 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7609 10:02:23.039696 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 10:02:23.042735 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 10:02:23.049024 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 10:02:23.052377 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 10:02:23.055742 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7614 10:02:23.062487 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7615 10:02:23.065598 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7616 10:02:23.068868 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
7617 10:02:23.075716 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 10:02:23.078932 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 10:02:23.082622 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 10:02:23.085389 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 10:02:23.092041 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7622 10:02:23.095539 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7623 10:02:23.098956 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7624 10:02:23.105152 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7625 10:02:23.108827 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 10:02:23.111869 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 10:02:23.118621 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 10:02:23.121652 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 10:02:23.125604 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7630 10:02:23.132634 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7631 10:02:23.135185 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7632 10:02:23.138628 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7633 10:02:23.145322 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7634 10:02:23.148741 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 10:02:23.151740 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 10:02:23.158313 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 10:02:23.161607 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 10:02:23.165137 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 10:02:23.171665 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 10:02:23.174708 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 10:02:23.178161 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 10:02:23.184631 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 10:02:23.187663 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 10:02:23.191044 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 10:02:23.197929 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7646 10:02:23.200977 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7647 10:02:23.204514 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7648 10:02:23.208470 Total UI for P1: 0, mck2ui 16
7649 10:02:23.210943 best dqsien dly found for B0: ( 1, 9, 10)
7650 10:02:23.217876 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7651 10:02:23.221006 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7652 10:02:23.224626 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 10:02:23.227767 Total UI for P1: 0, mck2ui 16
7654 10:02:23.231161 best dqsien dly found for B1: ( 1, 9, 22)
7655 10:02:23.234193 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7656 10:02:23.237619 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7657 10:02:23.238108
7658 10:02:23.244751 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7659 10:02:23.247845 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7660 10:02:23.251261 [Gating] SW calibration Done
7661 10:02:23.251854 ==
7662 10:02:23.254229 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 10:02:23.257393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 10:02:23.257989 ==
7665 10:02:23.258481 RX Vref Scan: 0
7666 10:02:23.258940
7667 10:02:23.260910 RX Vref 0 -> 0, step: 1
7668 10:02:23.261492
7669 10:02:23.264460 RX Delay 0 -> 252, step: 8
7670 10:02:23.267853 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7671 10:02:23.271127 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7672 10:02:23.277206 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7673 10:02:23.280547 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7674 10:02:23.283786 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7675 10:02:23.287063 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7676 10:02:23.290498 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7677 10:02:23.293947 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7678 10:02:23.300405 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7679 10:02:23.303765 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7680 10:02:23.306808 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7681 10:02:23.310102 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7682 10:02:23.317353 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7683 10:02:23.320942 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7684 10:02:23.323794 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7685 10:02:23.327484 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7686 10:02:23.328076 ==
7687 10:02:23.330755 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 10:02:23.334158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 10:02:23.337128 ==
7690 10:02:23.337750 DQS Delay:
7691 10:02:23.338144 DQS0 = 0, DQS1 = 0
7692 10:02:23.340241 DQM Delay:
7693 10:02:23.340853 DQM0 = 138, DQM1 = 126
7694 10:02:23.343703 DQ Delay:
7695 10:02:23.346799 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7696 10:02:23.350204 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7697 10:02:23.353550 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =119
7698 10:02:23.356927 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7699 10:02:23.357485
7700 10:02:23.357854
7701 10:02:23.358190 ==
7702 10:02:23.360183 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 10:02:23.363604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 10:02:23.364181 ==
7705 10:02:23.366840
7706 10:02:23.367402
7707 10:02:23.367769 TX Vref Scan disable
7708 10:02:23.369922 == TX Byte 0 ==
7709 10:02:23.373516 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7710 10:02:23.377025 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7711 10:02:23.380218 == TX Byte 1 ==
7712 10:02:23.383088 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7713 10:02:23.386376 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7714 10:02:23.386936 ==
7715 10:02:23.389789 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 10:02:23.396340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 10:02:23.396986 ==
7718 10:02:23.408506
7719 10:02:23.411413 TX Vref early break, caculate TX vref
7720 10:02:23.414793 TX Vref=16, minBit 8, minWin=22, winSum=379
7721 10:02:23.418180 TX Vref=18, minBit 6, minWin=23, winSum=385
7722 10:02:23.421621 TX Vref=20, minBit 4, minWin=24, winSum=395
7723 10:02:23.424713 TX Vref=22, minBit 7, minWin=24, winSum=402
7724 10:02:23.428259 TX Vref=24, minBit 0, minWin=25, winSum=416
7725 10:02:23.434776 TX Vref=26, minBit 2, minWin=25, winSum=422
7726 10:02:23.437749 TX Vref=28, minBit 0, minWin=26, winSum=431
7727 10:02:23.441382 TX Vref=30, minBit 0, minWin=25, winSum=416
7728 10:02:23.444409 TX Vref=32, minBit 0, minWin=25, winSum=415
7729 10:02:23.448023 TX Vref=34, minBit 2, minWin=24, winSum=405
7730 10:02:23.455052 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
7731 10:02:23.455619
7732 10:02:23.457919 Final TX Range 0 Vref 28
7733 10:02:23.458485
7734 10:02:23.458856 ==
7735 10:02:23.461025 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 10:02:23.464350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 10:02:23.464956 ==
7738 10:02:23.465331
7739 10:02:23.465699
7740 10:02:23.468194 TX Vref Scan disable
7741 10:02:23.474154 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7742 10:02:23.474721 == TX Byte 0 ==
7743 10:02:23.477683 u2DelayCellOfst[0]=13 cells (4 PI)
7744 10:02:23.480927 u2DelayCellOfst[1]=16 cells (5 PI)
7745 10:02:23.484234 u2DelayCellOfst[2]=10 cells (3 PI)
7746 10:02:23.487606 u2DelayCellOfst[3]=13 cells (4 PI)
7747 10:02:23.490514 u2DelayCellOfst[4]=6 cells (2 PI)
7748 10:02:23.494067 u2DelayCellOfst[5]=0 cells (0 PI)
7749 10:02:23.497170 u2DelayCellOfst[6]=16 cells (5 PI)
7750 10:02:23.500748 u2DelayCellOfst[7]=13 cells (4 PI)
7751 10:02:23.503788 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7752 10:02:23.507055 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7753 10:02:23.510319 == TX Byte 1 ==
7754 10:02:23.514073 u2DelayCellOfst[8]=0 cells (0 PI)
7755 10:02:23.516743 u2DelayCellOfst[9]=0 cells (0 PI)
7756 10:02:23.517272 u2DelayCellOfst[10]=6 cells (2 PI)
7757 10:02:23.520021 u2DelayCellOfst[11]=3 cells (1 PI)
7758 10:02:23.523489 u2DelayCellOfst[12]=10 cells (3 PI)
7759 10:02:23.526903 u2DelayCellOfst[13]=13 cells (4 PI)
7760 10:02:23.530652 u2DelayCellOfst[14]=13 cells (4 PI)
7761 10:02:23.533887 u2DelayCellOfst[15]=10 cells (3 PI)
7762 10:02:23.539924 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7763 10:02:23.543550 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7764 10:02:23.544123 DramC Write-DBI on
7765 10:02:23.544493 ==
7766 10:02:23.547035 Dram Type= 6, Freq= 0, CH_0, rank 0
7767 10:02:23.554047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7768 10:02:23.554616 ==
7769 10:02:23.554987
7770 10:02:23.555329
7771 10:02:23.555652 TX Vref Scan disable
7772 10:02:23.557577 == TX Byte 0 ==
7773 10:02:23.561101 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7774 10:02:23.564402 == TX Byte 1 ==
7775 10:02:23.567586 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7776 10:02:23.571181 DramC Write-DBI off
7777 10:02:23.571746
7778 10:02:23.572115 [DATLAT]
7779 10:02:23.572452 Freq=1600, CH0 RK0
7780 10:02:23.572878
7781 10:02:23.573829 DATLAT Default: 0xf
7782 10:02:23.574290 0, 0xFFFF, sum = 0
7783 10:02:23.577646 1, 0xFFFF, sum = 0
7784 10:02:23.580898 2, 0xFFFF, sum = 0
7785 10:02:23.581493 3, 0xFFFF, sum = 0
7786 10:02:23.583855 4, 0xFFFF, sum = 0
7787 10:02:23.584355 5, 0xFFFF, sum = 0
7788 10:02:23.587560 6, 0xFFFF, sum = 0
7789 10:02:23.588135 7, 0xFFFF, sum = 0
7790 10:02:23.591230 8, 0xFFFF, sum = 0
7791 10:02:23.591803 9, 0xFFFF, sum = 0
7792 10:02:23.593922 10, 0xFFFF, sum = 0
7793 10:02:23.594496 11, 0xFFFF, sum = 0
7794 10:02:23.597400 12, 0xFFFF, sum = 0
7795 10:02:23.597980 13, 0xFFFF, sum = 0
7796 10:02:23.600277 14, 0x0, sum = 1
7797 10:02:23.600904 15, 0x0, sum = 2
7798 10:02:23.604016 16, 0x0, sum = 3
7799 10:02:23.604489 17, 0x0, sum = 4
7800 10:02:23.607115 best_step = 15
7801 10:02:23.607576
7802 10:02:23.607938 ==
7803 10:02:23.610301 Dram Type= 6, Freq= 0, CH_0, rank 0
7804 10:02:23.614511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7805 10:02:23.615109 ==
7806 10:02:23.616861 RX Vref Scan: 1
7807 10:02:23.617349
7808 10:02:23.617712 Set Vref Range= 24 -> 127
7809 10:02:23.618050
7810 10:02:23.620192 RX Vref 24 -> 127, step: 1
7811 10:02:23.620656
7812 10:02:23.623466 RX Delay 19 -> 252, step: 4
7813 10:02:23.623960
7814 10:02:23.626999 Set Vref, RX VrefLevel [Byte0]: 24
7815 10:02:23.629934 [Byte1]: 24
7816 10:02:23.630502
7817 10:02:23.633364 Set Vref, RX VrefLevel [Byte0]: 25
7818 10:02:23.636571 [Byte1]: 25
7819 10:02:23.641176
7820 10:02:23.641637 Set Vref, RX VrefLevel [Byte0]: 26
7821 10:02:23.644190 [Byte1]: 26
7822 10:02:23.648059
7823 10:02:23.648624 Set Vref, RX VrefLevel [Byte0]: 27
7824 10:02:23.651462 [Byte1]: 27
7825 10:02:23.656005
7826 10:02:23.656577 Set Vref, RX VrefLevel [Byte0]: 28
7827 10:02:23.658965 [Byte1]: 28
7828 10:02:23.663194
7829 10:02:23.663759 Set Vref, RX VrefLevel [Byte0]: 29
7830 10:02:23.666844 [Byte1]: 29
7831 10:02:23.670626
7832 10:02:23.671191 Set Vref, RX VrefLevel [Byte0]: 30
7833 10:02:23.674017 [Byte1]: 30
7834 10:02:23.678169
7835 10:02:23.678740 Set Vref, RX VrefLevel [Byte0]: 31
7836 10:02:23.681656 [Byte1]: 31
7837 10:02:23.686403
7838 10:02:23.686969 Set Vref, RX VrefLevel [Byte0]: 32
7839 10:02:23.689017 [Byte1]: 32
7840 10:02:23.693397
7841 10:02:23.693958 Set Vref, RX VrefLevel [Byte0]: 33
7842 10:02:23.696670 [Byte1]: 33
7843 10:02:23.700611
7844 10:02:23.701114 Set Vref, RX VrefLevel [Byte0]: 34
7845 10:02:23.704503 [Byte1]: 34
7846 10:02:23.708544
7847 10:02:23.709056 Set Vref, RX VrefLevel [Byte0]: 35
7848 10:02:23.711769 [Byte1]: 35
7849 10:02:23.715976
7850 10:02:23.716544 Set Vref, RX VrefLevel [Byte0]: 36
7851 10:02:23.719488 [Byte1]: 36
7852 10:02:23.723502
7853 10:02:23.724033 Set Vref, RX VrefLevel [Byte0]: 37
7854 10:02:23.726944 [Byte1]: 37
7855 10:02:23.731437
7856 10:02:23.732023 Set Vref, RX VrefLevel [Byte0]: 38
7857 10:02:23.734318 [Byte1]: 38
7858 10:02:23.738444
7859 10:02:23.738908 Set Vref, RX VrefLevel [Byte0]: 39
7860 10:02:23.741897 [Byte1]: 39
7861 10:02:23.746378
7862 10:02:23.746946 Set Vref, RX VrefLevel [Byte0]: 40
7863 10:02:23.750002 [Byte1]: 40
7864 10:02:23.754175
7865 10:02:23.754736 Set Vref, RX VrefLevel [Byte0]: 41
7866 10:02:23.757197 [Byte1]: 41
7867 10:02:23.761703
7868 10:02:23.762267 Set Vref, RX VrefLevel [Byte0]: 42
7869 10:02:23.765080 [Byte1]: 42
7870 10:02:23.769411
7871 10:02:23.769974 Set Vref, RX VrefLevel [Byte0]: 43
7872 10:02:23.772599 [Byte1]: 43
7873 10:02:23.776603
7874 10:02:23.777220 Set Vref, RX VrefLevel [Byte0]: 44
7875 10:02:23.779857 [Byte1]: 44
7876 10:02:23.784754
7877 10:02:23.785368 Set Vref, RX VrefLevel [Byte0]: 45
7878 10:02:23.787753 [Byte1]: 45
7879 10:02:23.791968
7880 10:02:23.792533 Set Vref, RX VrefLevel [Byte0]: 46
7881 10:02:23.795270 [Byte1]: 46
7882 10:02:23.799700
7883 10:02:23.800287 Set Vref, RX VrefLevel [Byte0]: 47
7884 10:02:23.802542 [Byte1]: 47
7885 10:02:23.806928
7886 10:02:23.807492 Set Vref, RX VrefLevel [Byte0]: 48
7887 10:02:23.810619 [Byte1]: 48
7888 10:02:23.814248
7889 10:02:23.814857 Set Vref, RX VrefLevel [Byte0]: 49
7890 10:02:23.817627 [Byte1]: 49
7891 10:02:23.822046
7892 10:02:23.822507 Set Vref, RX VrefLevel [Byte0]: 50
7893 10:02:23.825488 [Byte1]: 50
7894 10:02:23.829542
7895 10:02:23.830115 Set Vref, RX VrefLevel [Byte0]: 51
7896 10:02:23.832983 [Byte1]: 51
7897 10:02:23.837364
7898 10:02:23.837964 Set Vref, RX VrefLevel [Byte0]: 52
7899 10:02:23.840332 [Byte1]: 52
7900 10:02:23.845003
7901 10:02:23.845590 Set Vref, RX VrefLevel [Byte0]: 53
7902 10:02:23.847992 [Byte1]: 53
7903 10:02:23.852594
7904 10:02:23.853204 Set Vref, RX VrefLevel [Byte0]: 54
7905 10:02:23.855753 [Byte1]: 54
7906 10:02:23.859961
7907 10:02:23.860536 Set Vref, RX VrefLevel [Byte0]: 55
7908 10:02:23.863053 [Byte1]: 55
7909 10:02:23.867605
7910 10:02:23.868103 Set Vref, RX VrefLevel [Byte0]: 56
7911 10:02:23.870938 [Byte1]: 56
7912 10:02:23.875178
7913 10:02:23.875652 Set Vref, RX VrefLevel [Byte0]: 57
7914 10:02:23.878434 [Byte1]: 57
7915 10:02:23.882377
7916 10:02:23.882855 Set Vref, RX VrefLevel [Byte0]: 58
7917 10:02:23.885629 [Byte1]: 58
7918 10:02:23.889903
7919 10:02:23.890417 Set Vref, RX VrefLevel [Byte0]: 59
7920 10:02:23.893677 [Byte1]: 59
7921 10:02:23.897425
7922 10:02:23.897787 Set Vref, RX VrefLevel [Byte0]: 60
7923 10:02:23.900551 [Byte1]: 60
7924 10:02:23.905476
7925 10:02:23.905613 Set Vref, RX VrefLevel [Byte0]: 61
7926 10:02:23.908124 [Byte1]: 61
7927 10:02:23.912469
7928 10:02:23.912587 Set Vref, RX VrefLevel [Byte0]: 62
7929 10:02:23.915690 [Byte1]: 62
7930 10:02:23.919790
7931 10:02:23.919867 Set Vref, RX VrefLevel [Byte0]: 63
7932 10:02:23.926469 [Byte1]: 63
7933 10:02:23.926574
7934 10:02:23.929617 Set Vref, RX VrefLevel [Byte0]: 64
7935 10:02:23.932695 [Byte1]: 64
7936 10:02:23.932801
7937 10:02:23.936414 Set Vref, RX VrefLevel [Byte0]: 65
7938 10:02:23.939312 [Byte1]: 65
7939 10:02:23.939403
7940 10:02:23.942833 Set Vref, RX VrefLevel [Byte0]: 66
7941 10:02:23.946388 [Byte1]: 66
7942 10:02:23.950522
7943 10:02:23.950625 Set Vref, RX VrefLevel [Byte0]: 67
7944 10:02:23.953746 [Byte1]: 67
7945 10:02:23.957960
7946 10:02:23.958165 Set Vref, RX VrefLevel [Byte0]: 68
7947 10:02:23.961253 [Byte1]: 68
7948 10:02:23.965169
7949 10:02:23.965373 Set Vref, RX VrefLevel [Byte0]: 69
7950 10:02:23.969323 [Byte1]: 69
7951 10:02:23.973238
7952 10:02:23.973416 Set Vref, RX VrefLevel [Byte0]: 70
7953 10:02:23.976713 [Byte1]: 70
7954 10:02:23.980423
7955 10:02:23.980721 Set Vref, RX VrefLevel [Byte0]: 71
7956 10:02:23.983859 [Byte1]: 71
7957 10:02:23.988503
7958 10:02:23.988933 Set Vref, RX VrefLevel [Byte0]: 72
7959 10:02:23.991703 [Byte1]: 72
7960 10:02:23.995853
7961 10:02:23.996298 Set Vref, RX VrefLevel [Byte0]: 73
7962 10:02:23.999386 [Byte1]: 73
7963 10:02:24.003477
7964 10:02:24.003971 Set Vref, RX VrefLevel [Byte0]: 74
7965 10:02:24.006948 [Byte1]: 74
7966 10:02:24.011241
7967 10:02:24.011794 Set Vref, RX VrefLevel [Byte0]: 75
7968 10:02:24.014334 [Byte1]: 75
7969 10:02:24.018577
7970 10:02:24.018958 Set Vref, RX VrefLevel [Byte0]: 76
7971 10:02:24.022379 [Byte1]: 76
7972 10:02:24.026355
7973 10:02:24.026737 Set Vref, RX VrefLevel [Byte0]: 77
7974 10:02:24.030097 [Byte1]: 77
7975 10:02:24.034162
7976 10:02:24.034730 Set Vref, RX VrefLevel [Byte0]: 78
7977 10:02:24.037038 [Byte1]: 78
7978 10:02:24.041325
7979 10:02:24.041752 Set Vref, RX VrefLevel [Byte0]: 79
7980 10:02:24.044845 [Byte1]: 79
7981 10:02:24.048804
7982 10:02:24.049224 Final RX Vref Byte 0 = 56 to rank0
7983 10:02:24.052313 Final RX Vref Byte 1 = 62 to rank0
7984 10:02:24.055489 Final RX Vref Byte 0 = 56 to rank1
7985 10:02:24.058617 Final RX Vref Byte 1 = 62 to rank1==
7986 10:02:24.062100 Dram Type= 6, Freq= 0, CH_0, rank 0
7987 10:02:24.068948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 10:02:24.069334 ==
7989 10:02:24.069637 DQS Delay:
7990 10:02:24.072025 DQS0 = 0, DQS1 = 0
7991 10:02:24.072409 DQM Delay:
7992 10:02:24.072706 DQM0 = 136, DQM1 = 124
7993 10:02:24.075645 DQ Delay:
7994 10:02:24.078797 DQ0 =136, DQ1 =140, DQ2 =132, DQ3 =132
7995 10:02:24.082175 DQ4 =140, DQ5 =124, DQ6 =142, DQ7 =144
7996 10:02:24.084954 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =118
7997 10:02:24.089147 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
7998 10:02:24.089538
7999 10:02:24.089843
8000 10:02:24.090128
8001 10:02:24.091669 [DramC_TX_OE_Calibration] TA2
8002 10:02:24.095090 Original DQ_B0 (3 6) =30, OEN = 27
8003 10:02:24.098287 Original DQ_B1 (3 6) =30, OEN = 27
8004 10:02:24.101882 24, 0x0, End_B0=24 End_B1=24
8005 10:02:24.104719 25, 0x0, End_B0=25 End_B1=25
8006 10:02:24.105152 26, 0x0, End_B0=26 End_B1=26
8007 10:02:24.108854 27, 0x0, End_B0=27 End_B1=27
8008 10:02:24.111318 28, 0x0, End_B0=28 End_B1=28
8009 10:02:24.114854 29, 0x0, End_B0=29 End_B1=29
8010 10:02:24.115275 30, 0x0, End_B0=30 End_B1=30
8011 10:02:24.118121 31, 0x4141, End_B0=30 End_B1=30
8012 10:02:24.121923 Byte0 end_step=30 best_step=27
8013 10:02:24.124918 Byte1 end_step=30 best_step=27
8014 10:02:24.128064 Byte0 TX OE(2T, 0.5T) = (3, 3)
8015 10:02:24.131328 Byte1 TX OE(2T, 0.5T) = (3, 3)
8016 10:02:24.131724
8017 10:02:24.132035
8018 10:02:24.138272 [DQSOSCAuto] RK0, (LSB)MR18= 0x201e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
8019 10:02:24.141519 CH0 RK0: MR19=303, MR18=201E
8020 10:02:24.147818 CH0_RK0: MR19=0x303, MR18=0x201E, DQSOSC=393, MR23=63, INC=23, DEC=15
8021 10:02:24.147927
8022 10:02:24.151234 ----->DramcWriteLeveling(PI) begin...
8023 10:02:24.151322 ==
8024 10:02:24.154359 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 10:02:24.157671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 10:02:24.157771 ==
8027 10:02:24.160617 Write leveling (Byte 0): 38 => 38
8028 10:02:24.164354 Write leveling (Byte 1): 31 => 31
8029 10:02:24.167438 DramcWriteLeveling(PI) end<-----
8030 10:02:24.167521
8031 10:02:24.167584 ==
8032 10:02:24.170660 Dram Type= 6, Freq= 0, CH_0, rank 1
8033 10:02:24.174075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8034 10:02:24.177304 ==
8035 10:02:24.177387 [Gating] SW mode calibration
8036 10:02:24.187478 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8037 10:02:24.190960 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8038 10:02:24.194425 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 10:02:24.201082 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 10:02:24.204003 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
8041 10:02:24.207401 1 4 12 | B1->B0 | 2626 3232 | 1 1 | (0 0) (0 0)
8042 10:02:24.214287 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8043 10:02:24.217103 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8044 10:02:24.220714 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 10:02:24.227150 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 10:02:24.230560 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 10:02:24.233902 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 10:02:24.240257 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
8049 10:02:24.243722 1 5 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
8050 10:02:24.246831 1 5 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8051 10:02:24.253509 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 10:02:24.256717 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 10:02:24.260251 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 10:02:24.267127 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 10:02:24.270064 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 10:02:24.273489 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8057 10:02:24.279994 1 6 12 | B1->B0 | 2d2d 4140 | 0 1 | (0 0) (0 0)
8058 10:02:24.283829 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 10:02:24.286532 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 10:02:24.293172 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 10:02:24.296543 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 10:02:24.300789 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 10:02:24.307089 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 10:02:24.309898 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 10:02:24.313427 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8066 10:02:24.320378 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8067 10:02:24.323571 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 10:02:24.326330 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 10:02:24.332932 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 10:02:24.336504 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 10:02:24.339431 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 10:02:24.346129 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 10:02:24.349762 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 10:02:24.353460 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 10:02:24.360280 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 10:02:24.363132 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 10:02:24.366470 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 10:02:24.369776 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 10:02:24.376602 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 10:02:24.379970 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8081 10:02:24.382869 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8082 10:02:24.389798 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 10:02:24.393319 Total UI for P1: 0, mck2ui 16
8084 10:02:24.396158 best dqsien dly found for B0: ( 1, 9, 10)
8085 10:02:24.399567 Total UI for P1: 0, mck2ui 16
8086 10:02:24.402613 best dqsien dly found for B1: ( 1, 9, 12)
8087 10:02:24.406189 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8088 10:02:24.408884 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8089 10:02:24.409578
8090 10:02:24.412702 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8091 10:02:24.415614 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8092 10:02:24.419231 [Gating] SW calibration Done
8093 10:02:24.419870 ==
8094 10:02:24.422367 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 10:02:24.426406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 10:02:24.426905 ==
8097 10:02:24.429046 RX Vref Scan: 0
8098 10:02:24.429546
8099 10:02:24.432511 RX Vref 0 -> 0, step: 1
8100 10:02:24.433005
8101 10:02:24.433369 RX Delay 0 -> 252, step: 8
8102 10:02:24.439265 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8103 10:02:24.442394 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8104 10:02:24.445643 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8105 10:02:24.449299 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8106 10:02:24.452822 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8107 10:02:24.459209 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8108 10:02:24.462731 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8109 10:02:24.465651 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8110 10:02:24.469285 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8111 10:02:24.472875 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8112 10:02:24.478895 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8113 10:02:24.482653 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8114 10:02:24.485808 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8115 10:02:24.489390 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8116 10:02:24.492388 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8117 10:02:24.499511 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8118 10:02:24.500079 ==
8119 10:02:24.502148 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 10:02:24.505335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 10:02:24.505939 ==
8122 10:02:24.506310 DQS Delay:
8123 10:02:24.508836 DQS0 = 0, DQS1 = 0
8124 10:02:24.509316 DQM Delay:
8125 10:02:24.511973 DQM0 = 136, DQM1 = 125
8126 10:02:24.512435 DQ Delay:
8127 10:02:24.515380 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8128 10:02:24.519376 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8129 10:02:24.522008 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8130 10:02:24.528717 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8131 10:02:24.529330
8132 10:02:24.529696
8133 10:02:24.530033 ==
8134 10:02:24.532133 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 10:02:24.535272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 10:02:24.535841 ==
8137 10:02:24.536214
8138 10:02:24.536550
8139 10:02:24.538915 TX Vref Scan disable
8140 10:02:24.539555 == TX Byte 0 ==
8141 10:02:24.545585 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8142 10:02:24.548504 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8143 10:02:24.549131 == TX Byte 1 ==
8144 10:02:24.555273 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8145 10:02:24.558796 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8146 10:02:24.559380 ==
8147 10:02:24.562346 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 10:02:24.564714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 10:02:24.565507 ==
8150 10:02:24.580184
8151 10:02:24.583235 TX Vref early break, caculate TX vref
8152 10:02:24.586692 TX Vref=16, minBit 8, minWin=22, winSum=387
8153 10:02:24.590347 TX Vref=18, minBit 1, minWin=24, winSum=399
8154 10:02:24.593548 TX Vref=20, minBit 0, minWin=24, winSum=407
8155 10:02:24.597549 TX Vref=22, minBit 8, minWin=24, winSum=413
8156 10:02:24.600585 TX Vref=24, minBit 0, minWin=25, winSum=425
8157 10:02:24.606833 TX Vref=26, minBit 0, minWin=26, winSum=430
8158 10:02:24.610463 TX Vref=28, minBit 0, minWin=26, winSum=432
8159 10:02:24.613620 TX Vref=30, minBit 0, minWin=26, winSum=428
8160 10:02:24.616845 TX Vref=32, minBit 0, minWin=25, winSum=417
8161 10:02:24.620200 TX Vref=34, minBit 0, minWin=25, winSum=412
8162 10:02:24.624283 TX Vref=36, minBit 2, minWin=24, winSum=401
8163 10:02:24.630255 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
8164 10:02:24.630434
8165 10:02:24.633458 Final TX Range 0 Vref 28
8166 10:02:24.633613
8167 10:02:24.633733 ==
8168 10:02:24.637115 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 10:02:24.639948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 10:02:24.640252 ==
8171 10:02:24.640434
8172 10:02:24.643618
8173 10:02:24.643912 TX Vref Scan disable
8174 10:02:24.650344 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8175 10:02:24.650752 == TX Byte 0 ==
8176 10:02:24.653157 u2DelayCellOfst[0]=13 cells (4 PI)
8177 10:02:24.656975 u2DelayCellOfst[1]=20 cells (6 PI)
8178 10:02:24.659982 u2DelayCellOfst[2]=13 cells (4 PI)
8179 10:02:24.663958 u2DelayCellOfst[3]=13 cells (4 PI)
8180 10:02:24.667171 u2DelayCellOfst[4]=10 cells (3 PI)
8181 10:02:24.670260 u2DelayCellOfst[5]=0 cells (0 PI)
8182 10:02:24.673434 u2DelayCellOfst[6]=20 cells (6 PI)
8183 10:02:24.676757 u2DelayCellOfst[7]=20 cells (6 PI)
8184 10:02:24.680118 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8185 10:02:24.683121 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8186 10:02:24.687143 == TX Byte 1 ==
8187 10:02:24.689837 u2DelayCellOfst[8]=3 cells (1 PI)
8188 10:02:24.693077 u2DelayCellOfst[9]=0 cells (0 PI)
8189 10:02:24.696592 u2DelayCellOfst[10]=6 cells (2 PI)
8190 10:02:24.700336 u2DelayCellOfst[11]=3 cells (1 PI)
8191 10:02:24.700835 u2DelayCellOfst[12]=13 cells (4 PI)
8192 10:02:24.703233 u2DelayCellOfst[13]=13 cells (4 PI)
8193 10:02:24.706310 u2DelayCellOfst[14]=16 cells (5 PI)
8194 10:02:24.709606 u2DelayCellOfst[15]=10 cells (3 PI)
8195 10:02:24.716193 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8196 10:02:24.719583 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8197 10:02:24.720162 DramC Write-DBI on
8198 10:02:24.722815 ==
8199 10:02:24.726851 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 10:02:24.729605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 10:02:24.730181 ==
8202 10:02:24.730553
8203 10:02:24.730895
8204 10:02:24.732977 TX Vref Scan disable
8205 10:02:24.733540 == TX Byte 0 ==
8206 10:02:24.739691 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8207 10:02:24.740270 == TX Byte 1 ==
8208 10:02:24.742831 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8209 10:02:24.746249 DramC Write-DBI off
8210 10:02:24.746822
8211 10:02:24.747195 [DATLAT]
8212 10:02:24.749325 Freq=1600, CH0 RK1
8213 10:02:24.749902
8214 10:02:24.750276 DATLAT Default: 0xf
8215 10:02:24.752638 0, 0xFFFF, sum = 0
8216 10:02:24.753256 1, 0xFFFF, sum = 0
8217 10:02:24.755996 2, 0xFFFF, sum = 0
8218 10:02:24.756577 3, 0xFFFF, sum = 0
8219 10:02:24.759642 4, 0xFFFF, sum = 0
8220 10:02:24.762516 5, 0xFFFF, sum = 0
8221 10:02:24.763093 6, 0xFFFF, sum = 0
8222 10:02:24.765914 7, 0xFFFF, sum = 0
8223 10:02:24.766498 8, 0xFFFF, sum = 0
8224 10:02:24.769202 9, 0xFFFF, sum = 0
8225 10:02:24.769784 10, 0xFFFF, sum = 0
8226 10:02:24.772603 11, 0xFFFF, sum = 0
8227 10:02:24.773218 12, 0xFFFF, sum = 0
8228 10:02:24.775841 13, 0xFFFF, sum = 0
8229 10:02:24.776423 14, 0x0, sum = 1
8230 10:02:24.779304 15, 0x0, sum = 2
8231 10:02:24.779906 16, 0x0, sum = 3
8232 10:02:24.782169 17, 0x0, sum = 4
8233 10:02:24.782644 best_step = 15
8234 10:02:24.783014
8235 10:02:24.783357 ==
8236 10:02:24.785535 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 10:02:24.789365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 10:02:24.792548 ==
8239 10:02:24.793159 RX Vref Scan: 0
8240 10:02:24.793536
8241 10:02:24.795758 RX Vref 0 -> 0, step: 1
8242 10:02:24.796331
8243 10:02:24.798901 RX Delay 11 -> 252, step: 4
8244 10:02:24.802066 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8245 10:02:24.805361 iDelay=191, Bit 1, Center 134 (87 ~ 182) 96
8246 10:02:24.808715 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8247 10:02:24.812317 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8248 10:02:24.818752 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8249 10:02:24.821964 iDelay=191, Bit 5, Center 122 (71 ~ 174) 104
8250 10:02:24.825509 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8251 10:02:24.828563 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8252 10:02:24.832150 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8253 10:02:24.838867 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8254 10:02:24.842180 iDelay=191, Bit 10, Center 126 (79 ~ 174) 96
8255 10:02:24.845271 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8256 10:02:24.848616 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8257 10:02:24.855136 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8258 10:02:24.858642 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8259 10:02:24.861682 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8260 10:02:24.862251 ==
8261 10:02:24.865351 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 10:02:24.868499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 10:02:24.869107 ==
8264 10:02:24.871961 DQS Delay:
8265 10:02:24.872526 DQS0 = 0, DQS1 = 0
8266 10:02:24.874777 DQM Delay:
8267 10:02:24.875343 DQM0 = 132, DQM1 = 123
8268 10:02:24.875721 DQ Delay:
8269 10:02:24.881371 DQ0 =132, DQ1 =134, DQ2 =130, DQ3 =130
8270 10:02:24.884946 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =140
8271 10:02:24.888453 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =120
8272 10:02:24.891292 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8273 10:02:24.891857
8274 10:02:24.892237
8275 10:02:24.892605
8276 10:02:24.894439 [DramC_TX_OE_Calibration] TA2
8277 10:02:24.897948 Original DQ_B0 (3 6) =30, OEN = 27
8278 10:02:24.901536 Original DQ_B1 (3 6) =30, OEN = 27
8279 10:02:24.902104 24, 0x0, End_B0=24 End_B1=24
8280 10:02:24.904755 25, 0x0, End_B0=25 End_B1=25
8281 10:02:24.908004 26, 0x0, End_B0=26 End_B1=26
8282 10:02:24.911084 27, 0x0, End_B0=27 End_B1=27
8283 10:02:24.914788 28, 0x0, End_B0=28 End_B1=28
8284 10:02:24.915265 29, 0x0, End_B0=29 End_B1=29
8285 10:02:24.917747 30, 0x0, End_B0=30 End_B1=30
8286 10:02:24.921454 31, 0x4141, End_B0=30 End_B1=30
8287 10:02:24.924499 Byte0 end_step=30 best_step=27
8288 10:02:24.927946 Byte1 end_step=30 best_step=27
8289 10:02:24.928418 Byte0 TX OE(2T, 0.5T) = (3, 3)
8290 10:02:24.931327 Byte1 TX OE(2T, 0.5T) = (3, 3)
8291 10:02:24.931794
8292 10:02:24.932159
8293 10:02:24.941086 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8294 10:02:24.944151 CH0 RK1: MR19=303, MR18=210E
8295 10:02:24.947817 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8296 10:02:24.951236 [RxdqsGatingPostProcess] freq 1600
8297 10:02:24.957920 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8298 10:02:24.961123 best DQS0 dly(2T, 0.5T) = (1, 1)
8299 10:02:24.964172 best DQS1 dly(2T, 0.5T) = (1, 1)
8300 10:02:24.967725 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8301 10:02:24.971118 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8302 10:02:24.974699 best DQS0 dly(2T, 0.5T) = (1, 1)
8303 10:02:24.977638 best DQS1 dly(2T, 0.5T) = (1, 1)
8304 10:02:24.981061 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8305 10:02:24.984668 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8306 10:02:24.985268 Pre-setting of DQS Precalculation
8307 10:02:24.990938 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8308 10:02:24.991498 ==
8309 10:02:24.993773 Dram Type= 6, Freq= 0, CH_1, rank 0
8310 10:02:24.997579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 10:02:24.998138 ==
8312 10:02:25.003598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 10:02:25.007095 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 10:02:25.013826 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 10:02:25.016730 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 10:02:25.026875 [CA 0] Center 42 (12~72) winsize 61
8317 10:02:25.030718 [CA 1] Center 42 (12~72) winsize 61
8318 10:02:25.034226 [CA 2] Center 38 (9~68) winsize 60
8319 10:02:25.037168 [CA 3] Center 37 (8~67) winsize 60
8320 10:02:25.039934 [CA 4] Center 37 (7~67) winsize 61
8321 10:02:25.043462 [CA 5] Center 37 (7~67) winsize 61
8322 10:02:25.043931
8323 10:02:25.046704 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8324 10:02:25.047269
8325 10:02:25.049913 [CATrainingPosCal] consider 1 rank data
8326 10:02:25.053369 u2DelayCellTimex100 = 290/100 ps
8327 10:02:25.059985 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8328 10:02:25.063153 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8329 10:02:25.066879 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8330 10:02:25.069919 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8331 10:02:25.073682 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
8332 10:02:25.076631 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8333 10:02:25.077231
8334 10:02:25.079867 CA PerBit enable=1, Macro0, CA PI delay=37
8335 10:02:25.080355
8336 10:02:25.083173 [CBTSetCACLKResult] CA Dly = 37
8337 10:02:25.086520 CS Dly: 8 (0~39)
8338 10:02:25.089683 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 10:02:25.092926 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 10:02:25.093485 ==
8341 10:02:25.097165 Dram Type= 6, Freq= 0, CH_1, rank 1
8342 10:02:25.099691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 10:02:25.102731 ==
8344 10:02:25.106205 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8345 10:02:25.109546 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8346 10:02:25.116145 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8347 10:02:25.122777 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8348 10:02:25.130000 [CA 0] Center 42 (13~72) winsize 60
8349 10:02:25.133666 [CA 1] Center 42 (12~72) winsize 61
8350 10:02:25.136693 [CA 2] Center 38 (9~68) winsize 60
8351 10:02:25.140319 [CA 3] Center 37 (8~67) winsize 60
8352 10:02:25.143265 [CA 4] Center 38 (9~67) winsize 59
8353 10:02:25.146922 [CA 5] Center 37 (8~67) winsize 60
8354 10:02:25.147492
8355 10:02:25.150106 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8356 10:02:25.150669
8357 10:02:25.153372 [CATrainingPosCal] consider 2 rank data
8358 10:02:25.156738 u2DelayCellTimex100 = 290/100 ps
8359 10:02:25.160293 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8360 10:02:25.166289 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8361 10:02:25.169580 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8362 10:02:25.173230 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8363 10:02:25.176321 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8364 10:02:25.179854 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8365 10:02:25.180314
8366 10:02:25.182908 CA PerBit enable=1, Macro0, CA PI delay=37
8367 10:02:25.183363
8368 10:02:25.186386 [CBTSetCACLKResult] CA Dly = 37
8369 10:02:25.189536 CS Dly: 9 (0~42)
8370 10:02:25.193157 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8371 10:02:25.196012 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8372 10:02:25.196467
8373 10:02:25.199265 ----->DramcWriteLeveling(PI) begin...
8374 10:02:25.199729 ==
8375 10:02:25.202895 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 10:02:25.209234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 10:02:25.209709 ==
8378 10:02:25.212524 Write leveling (Byte 0): 25 => 25
8379 10:02:25.213170 Write leveling (Byte 1): 30 => 30
8380 10:02:25.216129 DramcWriteLeveling(PI) end<-----
8381 10:02:25.216584
8382 10:02:25.217061 ==
8383 10:02:25.219031 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 10:02:25.225917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 10:02:25.226464 ==
8386 10:02:25.229544 [Gating] SW mode calibration
8387 10:02:25.236075 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8388 10:02:25.239108 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8389 10:02:25.246206 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 10:02:25.249394 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 10:02:25.252503 1 4 8 | B1->B0 | 2423 3333 | 1 0 | (0 0) (0 0)
8392 10:02:25.259200 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8393 10:02:25.262657 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 10:02:25.265651 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 10:02:25.272594 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 10:02:25.276162 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 10:02:25.278804 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 10:02:25.285419 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8399 10:02:25.288814 1 5 8 | B1->B0 | 3333 2929 | 1 0 | (1 0) (1 0)
8400 10:02:25.291942 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8401 10:02:25.298506 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8402 10:02:25.301904 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 10:02:25.305147 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 10:02:25.311452 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 10:02:25.315478 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 10:02:25.319083 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8407 10:02:25.324678 1 6 8 | B1->B0 | 3535 4545 | 0 0 | (0 0) (0 0)
8408 10:02:25.328283 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8409 10:02:25.331575 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 10:02:25.338440 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 10:02:25.341843 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 10:02:25.344807 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 10:02:25.351461 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 10:02:25.354473 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 10:02:25.358114 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8416 10:02:25.364930 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8417 10:02:25.368366 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8418 10:02:25.371563 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 10:02:25.377978 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 10:02:25.381523 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 10:02:25.384447 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 10:02:25.391111 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 10:02:25.394334 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 10:02:25.397801 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 10:02:25.404812 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 10:02:25.407401 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 10:02:25.410772 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 10:02:25.417241 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 10:02:25.420865 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 10:02:25.424444 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8431 10:02:25.431184 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8432 10:02:25.431762 Total UI for P1: 0, mck2ui 16
8433 10:02:25.433700 best dqsien dly found for B0: ( 1, 9, 4)
8434 10:02:25.440461 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8435 10:02:25.443806 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 10:02:25.447466 Total UI for P1: 0, mck2ui 16
8437 10:02:25.451245 best dqsien dly found for B1: ( 1, 9, 10)
8438 10:02:25.453651 best DQS0 dly(MCK, UI, PI) = (1, 9, 4)
8439 10:02:25.457603 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8440 10:02:25.458176
8441 10:02:25.460898 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 4)
8442 10:02:25.467302 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8443 10:02:25.467866 [Gating] SW calibration Done
8444 10:02:25.468243 ==
8445 10:02:25.470429 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 10:02:25.477624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 10:02:25.478188 ==
8448 10:02:25.478557 RX Vref Scan: 0
8449 10:02:25.478899
8450 10:02:25.480477 RX Vref 0 -> 0, step: 1
8451 10:02:25.481100
8452 10:02:25.483926 RX Delay 0 -> 252, step: 8
8453 10:02:25.487148 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8454 10:02:25.490499 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8455 10:02:25.493916 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8456 10:02:25.500989 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8457 10:02:25.503648 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8458 10:02:25.506504 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8459 10:02:25.509755 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8460 10:02:25.513410 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8461 10:02:25.520006 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8462 10:02:25.523384 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8463 10:02:25.526413 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8464 10:02:25.529482 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8465 10:02:25.532858 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8466 10:02:25.539769 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8467 10:02:25.542851 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8468 10:02:25.545986 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8469 10:02:25.546456 ==
8470 10:02:25.549299 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 10:02:25.552810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 10:02:25.553283 ==
8473 10:02:25.556324 DQS Delay:
8474 10:02:25.556942 DQS0 = 0, DQS1 = 0
8475 10:02:25.560024 DQM Delay:
8476 10:02:25.560598 DQM0 = 137, DQM1 = 130
8477 10:02:25.563240 DQ Delay:
8478 10:02:25.566157 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8479 10:02:25.569218 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8480 10:02:25.572799 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8481 10:02:25.576145 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8482 10:02:25.576717
8483 10:02:25.577124
8484 10:02:25.577467 ==
8485 10:02:25.579596 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 10:02:25.582158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 10:02:25.582629 ==
8488 10:02:25.582999
8489 10:02:25.586214
8490 10:02:25.586786 TX Vref Scan disable
8491 10:02:25.589317 == TX Byte 0 ==
8492 10:02:25.593152 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8493 10:02:25.595730 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8494 10:02:25.599210 == TX Byte 1 ==
8495 10:02:25.603060 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8496 10:02:25.605787 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8497 10:02:25.606359 ==
8498 10:02:25.608851 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 10:02:25.615376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 10:02:25.615952 ==
8501 10:02:25.627166
8502 10:02:25.630645 TX Vref early break, caculate TX vref
8503 10:02:25.633644 TX Vref=16, minBit 15, minWin=21, winSum=365
8504 10:02:25.636820 TX Vref=18, minBit 15, minWin=21, winSum=378
8505 10:02:25.640119 TX Vref=20, minBit 9, minWin=23, winSum=386
8506 10:02:25.643542 TX Vref=22, minBit 11, minWin=23, winSum=398
8507 10:02:25.649834 TX Vref=24, minBit 10, minWin=24, winSum=410
8508 10:02:25.653438 TX Vref=26, minBit 8, minWin=25, winSum=415
8509 10:02:25.657117 TX Vref=28, minBit 15, minWin=24, winSum=421
8510 10:02:25.659972 TX Vref=30, minBit 10, minWin=24, winSum=412
8511 10:02:25.663306 TX Vref=32, minBit 10, minWin=23, winSum=406
8512 10:02:25.670013 TX Vref=34, minBit 10, minWin=23, winSum=394
8513 10:02:25.673524 [TxChooseVref] Worse bit 8, Min win 25, Win sum 415, Final Vref 26
8514 10:02:25.674097
8515 10:02:25.676524 Final TX Range 0 Vref 26
8516 10:02:25.677141
8517 10:02:25.677512 ==
8518 10:02:25.679987 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 10:02:25.683362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 10:02:25.686749 ==
8521 10:02:25.687323
8522 10:02:25.687694
8523 10:02:25.688035 TX Vref Scan disable
8524 10:02:25.693288 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8525 10:02:25.693861 == TX Byte 0 ==
8526 10:02:25.697283 u2DelayCellOfst[0]=13 cells (4 PI)
8527 10:02:25.700316 u2DelayCellOfst[1]=6 cells (2 PI)
8528 10:02:25.703669 u2DelayCellOfst[2]=0 cells (0 PI)
8529 10:02:25.707071 u2DelayCellOfst[3]=3 cells (1 PI)
8530 10:02:25.709597 u2DelayCellOfst[4]=6 cells (2 PI)
8531 10:02:25.712627 u2DelayCellOfst[5]=16 cells (5 PI)
8532 10:02:25.716512 u2DelayCellOfst[6]=16 cells (5 PI)
8533 10:02:25.719852 u2DelayCellOfst[7]=3 cells (1 PI)
8534 10:02:25.723085 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8535 10:02:25.726127 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8536 10:02:25.729391 == TX Byte 1 ==
8537 10:02:25.733007 u2DelayCellOfst[8]=0 cells (0 PI)
8538 10:02:25.736373 u2DelayCellOfst[9]=3 cells (1 PI)
8539 10:02:25.739731 u2DelayCellOfst[10]=13 cells (4 PI)
8540 10:02:25.740310 u2DelayCellOfst[11]=6 cells (2 PI)
8541 10:02:25.742671 u2DelayCellOfst[12]=16 cells (5 PI)
8542 10:02:25.746375 u2DelayCellOfst[13]=16 cells (5 PI)
8543 10:02:25.749675 u2DelayCellOfst[14]=20 cells (6 PI)
8544 10:02:25.752910 u2DelayCellOfst[15]=16 cells (5 PI)
8545 10:02:25.759349 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8546 10:02:25.762617 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8547 10:02:25.763189 DramC Write-DBI on
8548 10:02:25.765996 ==
8549 10:02:25.766593 Dram Type= 6, Freq= 0, CH_1, rank 0
8550 10:02:25.772760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8551 10:02:25.773378 ==
8552 10:02:25.773752
8553 10:02:25.774095
8554 10:02:25.776173 TX Vref Scan disable
8555 10:02:25.776807 == TX Byte 0 ==
8556 10:02:25.782766 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8557 10:02:25.783357 == TX Byte 1 ==
8558 10:02:25.786072 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8559 10:02:25.789963 DramC Write-DBI off
8560 10:02:25.790536
8561 10:02:25.790905 [DATLAT]
8562 10:02:25.792345 Freq=1600, CH1 RK0
8563 10:02:25.792850
8564 10:02:25.793226 DATLAT Default: 0xf
8565 10:02:25.796121 0, 0xFFFF, sum = 0
8566 10:02:25.796701 1, 0xFFFF, sum = 0
8567 10:02:25.799490 2, 0xFFFF, sum = 0
8568 10:02:25.800071 3, 0xFFFF, sum = 0
8569 10:02:25.803061 4, 0xFFFF, sum = 0
8570 10:02:25.803644 5, 0xFFFF, sum = 0
8571 10:02:25.805904 6, 0xFFFF, sum = 0
8572 10:02:25.806481 7, 0xFFFF, sum = 0
8573 10:02:25.809270 8, 0xFFFF, sum = 0
8574 10:02:25.812696 9, 0xFFFF, sum = 0
8575 10:02:25.813223 10, 0xFFFF, sum = 0
8576 10:02:25.815573 11, 0xFFFF, sum = 0
8577 10:02:25.816045 12, 0xFFFF, sum = 0
8578 10:02:25.818957 13, 0xFFFF, sum = 0
8579 10:02:25.819536 14, 0x0, sum = 1
8580 10:02:25.822308 15, 0x0, sum = 2
8581 10:02:25.822888 16, 0x0, sum = 3
8582 10:02:25.825496 17, 0x0, sum = 4
8583 10:02:25.825971 best_step = 15
8584 10:02:25.826344
8585 10:02:25.826692 ==
8586 10:02:25.828751 Dram Type= 6, Freq= 0, CH_1, rank 0
8587 10:02:25.832249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8588 10:02:25.832871 ==
8589 10:02:25.835424 RX Vref Scan: 1
8590 10:02:25.835997
8591 10:02:25.838869 Set Vref Range= 24 -> 127
8592 10:02:25.839448
8593 10:02:25.839821 RX Vref 24 -> 127, step: 1
8594 10:02:25.841847
8595 10:02:25.842467 RX Delay 19 -> 252, step: 4
8596 10:02:25.842872
8597 10:02:25.845514 Set Vref, RX VrefLevel [Byte0]: 24
8598 10:02:25.848607 [Byte1]: 24
8599 10:02:25.852334
8600 10:02:25.852940 Set Vref, RX VrefLevel [Byte0]: 25
8601 10:02:25.855243 [Byte1]: 25
8602 10:02:25.859704
8603 10:02:25.860271 Set Vref, RX VrefLevel [Byte0]: 26
8604 10:02:25.863477 [Byte1]: 26
8605 10:02:25.867503
8606 10:02:25.868087 Set Vref, RX VrefLevel [Byte0]: 27
8607 10:02:25.870516 [Byte1]: 27
8608 10:02:25.874916
8609 10:02:25.875499 Set Vref, RX VrefLevel [Byte0]: 28
8610 10:02:25.878529 [Byte1]: 28
8611 10:02:25.882256
8612 10:02:25.882728 Set Vref, RX VrefLevel [Byte0]: 29
8613 10:02:25.886032 [Byte1]: 29
8614 10:02:25.890582
8615 10:02:25.891160 Set Vref, RX VrefLevel [Byte0]: 30
8616 10:02:25.893341 [Byte1]: 30
8617 10:02:25.897299
8618 10:02:25.897769 Set Vref, RX VrefLevel [Byte0]: 31
8619 10:02:25.901353 [Byte1]: 31
8620 10:02:25.905447
8621 10:02:25.906023 Set Vref, RX VrefLevel [Byte0]: 32
8622 10:02:25.911558 [Byte1]: 32
8623 10:02:25.912032
8624 10:02:25.914732 Set Vref, RX VrefLevel [Byte0]: 33
8625 10:02:25.918038 [Byte1]: 33
8626 10:02:25.918512
8627 10:02:25.921116 Set Vref, RX VrefLevel [Byte0]: 34
8628 10:02:25.924625 [Byte1]: 34
8629 10:02:25.927636
8630 10:02:25.928108 Set Vref, RX VrefLevel [Byte0]: 35
8631 10:02:25.931315 [Byte1]: 35
8632 10:02:25.935706
8633 10:02:25.936284 Set Vref, RX VrefLevel [Byte0]: 36
8634 10:02:25.938996 [Byte1]: 36
8635 10:02:25.943292
8636 10:02:25.943949 Set Vref, RX VrefLevel [Byte0]: 37
8637 10:02:25.946463 [Byte1]: 37
8638 10:02:25.950302
8639 10:02:25.950777 Set Vref, RX VrefLevel [Byte0]: 38
8640 10:02:25.954178 [Byte1]: 38
8641 10:02:25.958234
8642 10:02:25.958797 Set Vref, RX VrefLevel [Byte0]: 39
8643 10:02:25.961446 [Byte1]: 39
8644 10:02:25.966066
8645 10:02:25.966623 Set Vref, RX VrefLevel [Byte0]: 40
8646 10:02:25.969416 [Byte1]: 40
8647 10:02:25.973308
8648 10:02:25.973874 Set Vref, RX VrefLevel [Byte0]: 41
8649 10:02:25.976648 [Byte1]: 41
8650 10:02:25.981022
8651 10:02:25.981589 Set Vref, RX VrefLevel [Byte0]: 42
8652 10:02:25.984149 [Byte1]: 42
8653 10:02:25.988610
8654 10:02:25.989236 Set Vref, RX VrefLevel [Byte0]: 43
8655 10:02:25.991744 [Byte1]: 43
8656 10:02:25.996196
8657 10:02:25.996761 Set Vref, RX VrefLevel [Byte0]: 44
8658 10:02:25.999566 [Byte1]: 44
8659 10:02:26.003839
8660 10:02:26.004399 Set Vref, RX VrefLevel [Byte0]: 45
8661 10:02:26.006857 [Byte1]: 45
8662 10:02:26.010995
8663 10:02:26.011454 Set Vref, RX VrefLevel [Byte0]: 46
8664 10:02:26.014253 [Byte1]: 46
8665 10:02:26.018883
8666 10:02:26.019450 Set Vref, RX VrefLevel [Byte0]: 47
8667 10:02:26.022067 [Byte1]: 47
8668 10:02:26.026359
8669 10:02:26.026823 Set Vref, RX VrefLevel [Byte0]: 48
8670 10:02:26.029640 [Byte1]: 48
8671 10:02:26.033914
8672 10:02:26.034478 Set Vref, RX VrefLevel [Byte0]: 49
8673 10:02:26.037721 [Byte1]: 49
8674 10:02:26.041614
8675 10:02:26.042082 Set Vref, RX VrefLevel [Byte0]: 50
8676 10:02:26.044436 [Byte1]: 50
8677 10:02:26.049177
8678 10:02:26.049737 Set Vref, RX VrefLevel [Byte0]: 51
8679 10:02:26.052394 [Byte1]: 51
8680 10:02:26.056849
8681 10:02:26.057412 Set Vref, RX VrefLevel [Byte0]: 52
8682 10:02:26.060315 [Byte1]: 52
8683 10:02:26.064343
8684 10:02:26.064940 Set Vref, RX VrefLevel [Byte0]: 53
8685 10:02:26.067494 [Byte1]: 53
8686 10:02:26.071763
8687 10:02:26.072335 Set Vref, RX VrefLevel [Byte0]: 54
8688 10:02:26.075137 [Byte1]: 54
8689 10:02:26.079341
8690 10:02:26.079930 Set Vref, RX VrefLevel [Byte0]: 55
8691 10:02:26.082421 [Byte1]: 55
8692 10:02:26.086817
8693 10:02:26.087414 Set Vref, RX VrefLevel [Byte0]: 56
8694 10:02:26.090049 [Byte1]: 56
8695 10:02:26.094375
8696 10:02:26.094962 Set Vref, RX VrefLevel [Byte0]: 57
8697 10:02:26.097969 [Byte1]: 57
8698 10:02:26.102290
8699 10:02:26.102879 Set Vref, RX VrefLevel [Byte0]: 58
8700 10:02:26.105588 [Byte1]: 58
8701 10:02:26.109691
8702 10:02:26.110282 Set Vref, RX VrefLevel [Byte0]: 59
8703 10:02:26.112915 [Byte1]: 59
8704 10:02:26.117069
8705 10:02:26.117652 Set Vref, RX VrefLevel [Byte0]: 60
8706 10:02:26.120755 [Byte1]: 60
8707 10:02:26.124657
8708 10:02:26.125295 Set Vref, RX VrefLevel [Byte0]: 61
8709 10:02:26.127935 [Byte1]: 61
8710 10:02:26.132285
8711 10:02:26.132908 Set Vref, RX VrefLevel [Byte0]: 62
8712 10:02:26.135718 [Byte1]: 62
8713 10:02:26.140047
8714 10:02:26.140640 Set Vref, RX VrefLevel [Byte0]: 63
8715 10:02:26.143401 [Byte1]: 63
8716 10:02:26.147738
8717 10:02:26.148298 Set Vref, RX VrefLevel [Byte0]: 64
8718 10:02:26.150775 [Byte1]: 64
8719 10:02:26.155321
8720 10:02:26.155886 Set Vref, RX VrefLevel [Byte0]: 65
8721 10:02:26.158236 [Byte1]: 65
8722 10:02:26.162591
8723 10:02:26.163156 Set Vref, RX VrefLevel [Byte0]: 66
8724 10:02:26.165949 [Byte1]: 66
8725 10:02:26.170317
8726 10:02:26.170876 Set Vref, RX VrefLevel [Byte0]: 67
8727 10:02:26.176697 [Byte1]: 67
8728 10:02:26.177291
8729 10:02:26.180154 Set Vref, RX VrefLevel [Byte0]: 68
8730 10:02:26.183102 [Byte1]: 68
8731 10:02:26.183672
8732 10:02:26.186671 Set Vref, RX VrefLevel [Byte0]: 69
8733 10:02:26.190010 [Byte1]: 69
8734 10:02:26.190593
8735 10:02:26.193101 Set Vref, RX VrefLevel [Byte0]: 70
8736 10:02:26.196388 [Byte1]: 70
8737 10:02:26.200965
8738 10:02:26.201524 Set Vref, RX VrefLevel [Byte0]: 71
8739 10:02:26.203808 [Byte1]: 71
8740 10:02:26.208506
8741 10:02:26.209121 Set Vref, RX VrefLevel [Byte0]: 72
8742 10:02:26.211481 [Byte1]: 72
8743 10:02:26.215652
8744 10:02:26.216120 Set Vref, RX VrefLevel [Byte0]: 73
8745 10:02:26.219221 [Byte1]: 73
8746 10:02:26.223502
8747 10:02:26.224065 Set Vref, RX VrefLevel [Byte0]: 74
8748 10:02:26.226484 [Byte1]: 74
8749 10:02:26.230741
8750 10:02:26.231304 Final RX Vref Byte 0 = 57 to rank0
8751 10:02:26.234106 Final RX Vref Byte 1 = 66 to rank0
8752 10:02:26.238055 Final RX Vref Byte 0 = 57 to rank1
8753 10:02:26.240336 Final RX Vref Byte 1 = 66 to rank1==
8754 10:02:26.243872 Dram Type= 6, Freq= 0, CH_1, rank 0
8755 10:02:26.251032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8756 10:02:26.251601 ==
8757 10:02:26.251971 DQS Delay:
8758 10:02:26.254094 DQS0 = 0, DQS1 = 0
8759 10:02:26.254661 DQM Delay:
8760 10:02:26.255027 DQM0 = 134, DQM1 = 128
8761 10:02:26.258149 DQ Delay:
8762 10:02:26.260891 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8763 10:02:26.264201 DQ4 =134, DQ5 =146, DQ6 =146, DQ7 =132
8764 10:02:26.267115 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8765 10:02:26.270390 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8766 10:02:26.270902
8767 10:02:26.271455
8768 10:02:26.271982
8769 10:02:26.273341 [DramC_TX_OE_Calibration] TA2
8770 10:02:26.276412 Original DQ_B0 (3 6) =30, OEN = 27
8771 10:02:26.279826 Original DQ_B1 (3 6) =30, OEN = 27
8772 10:02:26.283210 24, 0x0, End_B0=24 End_B1=24
8773 10:02:26.283702 25, 0x0, End_B0=25 End_B1=25
8774 10:02:26.286974 26, 0x0, End_B0=26 End_B1=26
8775 10:02:26.289856 27, 0x0, End_B0=27 End_B1=27
8776 10:02:26.292911 28, 0x0, End_B0=28 End_B1=28
8777 10:02:26.296279 29, 0x0, End_B0=29 End_B1=29
8778 10:02:26.297012 30, 0x0, End_B0=30 End_B1=30
8779 10:02:26.299507 31, 0x4545, End_B0=30 End_B1=30
8780 10:02:26.303044 Byte0 end_step=30 best_step=27
8781 10:02:26.306673 Byte1 end_step=30 best_step=27
8782 10:02:26.309979 Byte0 TX OE(2T, 0.5T) = (3, 3)
8783 10:02:26.313161 Byte1 TX OE(2T, 0.5T) = (3, 3)
8784 10:02:26.313625
8785 10:02:26.313991
8786 10:02:26.319800 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b29, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8787 10:02:26.323123 CH1 RK0: MR19=303, MR18=1B29
8788 10:02:26.329302 CH1_RK0: MR19=0x303, MR18=0x1B29, DQSOSC=389, MR23=63, INC=24, DEC=16
8789 10:02:26.329492
8790 10:02:26.332715 ----->DramcWriteLeveling(PI) begin...
8791 10:02:26.332898 ==
8792 10:02:26.336074 Dram Type= 6, Freq= 0, CH_1, rank 1
8793 10:02:26.339498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8794 10:02:26.339634 ==
8795 10:02:26.342649 Write leveling (Byte 0): 24 => 24
8796 10:02:26.346015 Write leveling (Byte 1): 29 => 29
8797 10:02:26.349741 DramcWriteLeveling(PI) end<-----
8798 10:02:26.349846
8799 10:02:26.349928 ==
8800 10:02:26.352727 Dram Type= 6, Freq= 0, CH_1, rank 1
8801 10:02:26.356057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8802 10:02:26.356143 ==
8803 10:02:26.359867 [Gating] SW mode calibration
8804 10:02:26.365846 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8805 10:02:26.372397 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8806 10:02:26.375780 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 10:02:26.382428 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 10:02:26.385989 1 4 8 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
8809 10:02:26.389547 1 4 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
8810 10:02:26.395846 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 10:02:26.399180 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 10:02:26.402506 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 10:02:26.408923 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 10:02:26.412205 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 10:02:26.415581 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 10:02:26.422382 1 5 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 1) (1 0)
8817 10:02:26.426041 1 5 12 | B1->B0 | 2323 3232 | 0 0 | (1 0) (0 1)
8818 10:02:26.429015 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 10:02:26.436137 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 10:02:26.439095 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 10:02:26.442365 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 10:02:26.448874 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 10:02:26.452517 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 10:02:26.455378 1 6 8 | B1->B0 | 3737 2323 | 1 0 | (0 0) (0 0)
8825 10:02:26.462323 1 6 12 | B1->B0 | 4646 3d3d | 0 1 | (0 0) (0 0)
8826 10:02:26.465454 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 10:02:26.469260 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 10:02:26.475465 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 10:02:26.478568 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 10:02:26.482517 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 10:02:26.488517 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 10:02:26.491799 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8833 10:02:26.495080 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8834 10:02:26.501425 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 10:02:26.504760 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 10:02:26.508096 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 10:02:26.514788 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 10:02:26.518014 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 10:02:26.521899 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 10:02:26.528366 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 10:02:26.531236 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 10:02:26.534744 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 10:02:26.541143 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 10:02:26.544701 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 10:02:26.548121 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 10:02:26.554522 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 10:02:26.557700 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 10:02:26.561257 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8849 10:02:26.567937 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8850 10:02:26.571083 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 10:02:26.574226 Total UI for P1: 0, mck2ui 16
8852 10:02:26.577442 best dqsien dly found for B0: ( 1, 9, 10)
8853 10:02:26.580526 Total UI for P1: 0, mck2ui 16
8854 10:02:26.584402 best dqsien dly found for B1: ( 1, 9, 10)
8855 10:02:26.587470 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8856 10:02:26.590582 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8857 10:02:26.591057
8858 10:02:26.594447 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8859 10:02:26.597470 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8860 10:02:26.600271 [Gating] SW calibration Done
8861 10:02:26.600745 ==
8862 10:02:26.603762 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 10:02:26.607599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 10:02:26.610434 ==
8865 10:02:26.610904 RX Vref Scan: 0
8866 10:02:26.611280
8867 10:02:26.613935 RX Vref 0 -> 0, step: 1
8868 10:02:26.614535
8869 10:02:26.617126 RX Delay 0 -> 252, step: 8
8870 10:02:26.620072 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8871 10:02:26.623540 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8872 10:02:26.626761 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8873 10:02:26.630060 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8874 10:02:26.636479 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8875 10:02:26.640066 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8876 10:02:26.643695 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8877 10:02:26.646704 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8878 10:02:26.649994 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8879 10:02:26.653221 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8880 10:02:26.659852 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8881 10:02:26.663271 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8882 10:02:26.666817 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8883 10:02:26.669801 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8884 10:02:26.676379 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8885 10:02:26.679572 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8886 10:02:26.679992 ==
8887 10:02:26.683025 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 10:02:26.686619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 10:02:26.687044 ==
8890 10:02:26.689718 DQS Delay:
8891 10:02:26.690146 DQS0 = 0, DQS1 = 0
8892 10:02:26.690549 DQM Delay:
8893 10:02:26.693121 DQM0 = 138, DQM1 = 131
8894 10:02:26.693541 DQ Delay:
8895 10:02:26.696265 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8896 10:02:26.699426 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =139
8897 10:02:26.702956 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8898 10:02:26.709638 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8899 10:02:26.710076
8900 10:02:26.710408
8901 10:02:26.710714 ==
8902 10:02:26.713045 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 10:02:26.716111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 10:02:26.716597 ==
8905 10:02:26.716983
8906 10:02:26.717302
8907 10:02:26.719756 TX Vref Scan disable
8908 10:02:26.720178 == TX Byte 0 ==
8909 10:02:26.726199 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8910 10:02:26.729627 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8911 10:02:26.730053 == TX Byte 1 ==
8912 10:02:26.736459 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8913 10:02:26.739344 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8914 10:02:26.739771 ==
8915 10:02:26.742511 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 10:02:26.745978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 10:02:26.746401 ==
8918 10:02:26.760135
8919 10:02:26.763189 TX Vref early break, caculate TX vref
8920 10:02:26.766580 TX Vref=16, minBit 13, minWin=22, winSum=384
8921 10:02:26.770038 TX Vref=18, minBit 9, minWin=23, winSum=395
8922 10:02:26.773480 TX Vref=20, minBit 13, minWin=23, winSum=401
8923 10:02:26.776379 TX Vref=22, minBit 13, minWin=24, winSum=410
8924 10:02:26.783053 TX Vref=24, minBit 9, minWin=24, winSum=418
8925 10:02:26.786220 TX Vref=26, minBit 9, minWin=25, winSum=423
8926 10:02:26.789839 TX Vref=28, minBit 10, minWin=25, winSum=424
8927 10:02:26.792827 TX Vref=30, minBit 9, minWin=25, winSum=419
8928 10:02:26.796177 TX Vref=32, minBit 1, minWin=25, winSum=409
8929 10:02:26.799861 TX Vref=34, minBit 10, minWin=23, winSum=401
8930 10:02:26.805959 [TxChooseVref] Worse bit 10, Min win 25, Win sum 424, Final Vref 28
8931 10:02:26.806397
8932 10:02:26.809294 Final TX Range 0 Vref 28
8933 10:02:26.809720
8934 10:02:26.810051 ==
8935 10:02:26.812760 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 10:02:26.816023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 10:02:26.816507 ==
8938 10:02:26.819243
8939 10:02:26.819732
8940 10:02:26.820264 TX Vref Scan disable
8941 10:02:26.825921 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8942 10:02:26.826428 == TX Byte 0 ==
8943 10:02:26.829207 u2DelayCellOfst[0]=13 cells (4 PI)
8944 10:02:26.832624 u2DelayCellOfst[1]=10 cells (3 PI)
8945 10:02:26.835737 u2DelayCellOfst[2]=0 cells (0 PI)
8946 10:02:26.839267 u2DelayCellOfst[3]=3 cells (1 PI)
8947 10:02:26.842583 u2DelayCellOfst[4]=6 cells (2 PI)
8948 10:02:26.845838 u2DelayCellOfst[5]=16 cells (5 PI)
8949 10:02:26.849114 u2DelayCellOfst[6]=13 cells (4 PI)
8950 10:02:26.852189 u2DelayCellOfst[7]=3 cells (1 PI)
8951 10:02:26.855735 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8952 10:02:26.859055 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8953 10:02:26.862520 == TX Byte 1 ==
8954 10:02:26.865714 u2DelayCellOfst[8]=0 cells (0 PI)
8955 10:02:26.868857 u2DelayCellOfst[9]=3 cells (1 PI)
8956 10:02:26.872171 u2DelayCellOfst[10]=10 cells (3 PI)
8957 10:02:26.875450 u2DelayCellOfst[11]=3 cells (1 PI)
8958 10:02:26.878618 u2DelayCellOfst[12]=13 cells (4 PI)
8959 10:02:26.879041 u2DelayCellOfst[13]=13 cells (4 PI)
8960 10:02:26.881893 u2DelayCellOfst[14]=16 cells (5 PI)
8961 10:02:26.885325 u2DelayCellOfst[15]=13 cells (4 PI)
8962 10:02:26.891915 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8963 10:02:26.895458 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8964 10:02:26.896029 DramC Write-DBI on
8965 10:02:26.898928 ==
8966 10:02:26.902004 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 10:02:26.905351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 10:02:26.905825 ==
8969 10:02:26.906196
8970 10:02:26.906536
8971 10:02:26.908467 TX Vref Scan disable
8972 10:02:26.909007 == TX Byte 0 ==
8973 10:02:26.915208 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8974 10:02:26.915773 == TX Byte 1 ==
8975 10:02:26.918537 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8976 10:02:26.921671 DramC Write-DBI off
8977 10:02:26.922137
8978 10:02:26.922507 [DATLAT]
8979 10:02:26.925158 Freq=1600, CH1 RK1
8980 10:02:26.925622
8981 10:02:26.925986 DATLAT Default: 0xf
8982 10:02:26.928654 0, 0xFFFF, sum = 0
8983 10:02:26.929189 1, 0xFFFF, sum = 0
8984 10:02:26.931576 2, 0xFFFF, sum = 0
8985 10:02:26.932004 3, 0xFFFF, sum = 0
8986 10:02:26.935295 4, 0xFFFF, sum = 0
8987 10:02:26.935768 5, 0xFFFF, sum = 0
8988 10:02:26.938222 6, 0xFFFF, sum = 0
8989 10:02:26.938695 7, 0xFFFF, sum = 0
8990 10:02:26.941713 8, 0xFFFF, sum = 0
8991 10:02:26.944990 9, 0xFFFF, sum = 0
8992 10:02:26.945435 10, 0xFFFF, sum = 0
8993 10:02:26.948597 11, 0xFFFF, sum = 0
8994 10:02:26.949083 12, 0xFFFF, sum = 0
8995 10:02:26.951282 13, 0xFFFF, sum = 0
8996 10:02:26.951711 14, 0x0, sum = 1
8997 10:02:26.955047 15, 0x0, sum = 2
8998 10:02:26.955475 16, 0x0, sum = 3
8999 10:02:26.957949 17, 0x0, sum = 4
9000 10:02:26.958380 best_step = 15
9001 10:02:26.958710
9002 10:02:26.959018 ==
9003 10:02:26.961388 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 10:02:26.964883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 10:02:26.965312 ==
9006 10:02:26.968005 RX Vref Scan: 0
9007 10:02:26.968428
9008 10:02:26.971578 RX Vref 0 -> 0, step: 1
9009 10:02:26.972002
9010 10:02:26.972335 RX Delay 19 -> 252, step: 4
9011 10:02:26.978796 iDelay=191, Bit 0, Center 138 (95 ~ 182) 88
9012 10:02:26.982081 iDelay=191, Bit 1, Center 132 (87 ~ 178) 92
9013 10:02:26.985207 iDelay=191, Bit 2, Center 122 (75 ~ 170) 96
9014 10:02:26.988618 iDelay=191, Bit 3, Center 132 (83 ~ 182) 100
9015 10:02:26.991815 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
9016 10:02:26.998593 iDelay=191, Bit 5, Center 144 (99 ~ 190) 92
9017 10:02:27.001878 iDelay=191, Bit 6, Center 142 (95 ~ 190) 96
9018 10:02:27.005038 iDelay=191, Bit 7, Center 134 (87 ~ 182) 96
9019 10:02:27.008390 iDelay=191, Bit 8, Center 112 (63 ~ 162) 100
9020 10:02:27.011742 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
9021 10:02:27.018741 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
9022 10:02:27.021465 iDelay=191, Bit 11, Center 124 (71 ~ 178) 108
9023 10:02:27.024846 iDelay=191, Bit 12, Center 136 (87 ~ 186) 100
9024 10:02:27.028064 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
9025 10:02:27.031567 iDelay=191, Bit 14, Center 138 (91 ~ 186) 96
9026 10:02:27.038374 iDelay=191, Bit 15, Center 138 (87 ~ 190) 104
9027 10:02:27.038795 ==
9028 10:02:27.041724 Dram Type= 6, Freq= 0, CH_1, rank 1
9029 10:02:27.045037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9030 10:02:27.045594 ==
9031 10:02:27.046002 DQS Delay:
9032 10:02:27.048371 DQS0 = 0, DQS1 = 0
9033 10:02:27.048960 DQM Delay:
9034 10:02:27.051746 DQM0 = 134, DQM1 = 129
9035 10:02:27.052177 DQ Delay:
9036 10:02:27.054787 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =132
9037 10:02:27.057954 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134
9038 10:02:27.061491 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9039 10:02:27.064791 DQ12 =136, DQ13 =136, DQ14 =138, DQ15 =138
9040 10:02:27.065217
9041 10:02:27.068039
9042 10:02:27.068454
9043 10:02:27.068825 [DramC_TX_OE_Calibration] TA2
9044 10:02:27.071359 Original DQ_B0 (3 6) =30, OEN = 27
9045 10:02:27.074869 Original DQ_B1 (3 6) =30, OEN = 27
9046 10:02:27.078171 24, 0x0, End_B0=24 End_B1=24
9047 10:02:27.081390 25, 0x0, End_B0=25 End_B1=25
9048 10:02:27.084035 26, 0x0, End_B0=26 End_B1=26
9049 10:02:27.084118 27, 0x0, End_B0=27 End_B1=27
9050 10:02:27.087110 28, 0x0, End_B0=28 End_B1=28
9051 10:02:27.090845 29, 0x0, End_B0=29 End_B1=29
9052 10:02:27.094333 30, 0x0, End_B0=30 End_B1=30
9053 10:02:27.097235 31, 0x4141, End_B0=30 End_B1=30
9054 10:02:27.097308 Byte0 end_step=30 best_step=27
9055 10:02:27.100867 Byte1 end_step=30 best_step=27
9056 10:02:27.104167 Byte0 TX OE(2T, 0.5T) = (3, 3)
9057 10:02:27.107316 Byte1 TX OE(2T, 0.5T) = (3, 3)
9058 10:02:27.107412
9059 10:02:27.107500
9060 10:02:27.117234 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9061 10:02:27.117316 CH1 RK1: MR19=303, MR18=1E09
9062 10:02:27.123939 CH1_RK1: MR19=0x303, MR18=0x1E09, DQSOSC=394, MR23=63, INC=23, DEC=15
9063 10:02:27.126903 [RxdqsGatingPostProcess] freq 1600
9064 10:02:27.134260 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9065 10:02:27.137126 best DQS0 dly(2T, 0.5T) = (1, 1)
9066 10:02:27.140405 best DQS1 dly(2T, 0.5T) = (1, 1)
9067 10:02:27.143692 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9068 10:02:27.146951 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9069 10:02:27.147069 best DQS0 dly(2T, 0.5T) = (1, 1)
9070 10:02:27.151111 best DQS1 dly(2T, 0.5T) = (1, 1)
9071 10:02:27.153713 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9072 10:02:27.156894 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9073 10:02:27.160542 Pre-setting of DQS Precalculation
9074 10:02:27.166753 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9075 10:02:27.173969 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9076 10:02:27.180339 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9077 10:02:27.180565
9078 10:02:27.180755
9079 10:02:27.183323 [Calibration Summary] 3200 Mbps
9080 10:02:27.183557 CH 0, Rank 0
9081 10:02:27.186820 SW Impedance : PASS
9082 10:02:27.189881 DUTY Scan : NO K
9083 10:02:27.190191 ZQ Calibration : PASS
9084 10:02:27.193442 Jitter Meter : NO K
9085 10:02:27.196847 CBT Training : PASS
9086 10:02:27.197309 Write leveling : PASS
9087 10:02:27.200124 RX DQS gating : PASS
9088 10:02:27.203679 RX DQ/DQS(RDDQC) : PASS
9089 10:02:27.204084 TX DQ/DQS : PASS
9090 10:02:27.207173 RX DATLAT : PASS
9091 10:02:27.207611 RX DQ/DQS(Engine): PASS
9092 10:02:27.210291 TX OE : PASS
9093 10:02:27.210755 All Pass.
9094 10:02:27.211106
9095 10:02:27.213403 CH 0, Rank 1
9096 10:02:27.213846 SW Impedance : PASS
9097 10:02:27.216867 DUTY Scan : NO K
9098 10:02:27.220193 ZQ Calibration : PASS
9099 10:02:27.220726 Jitter Meter : NO K
9100 10:02:27.223325 CBT Training : PASS
9101 10:02:27.226640 Write leveling : PASS
9102 10:02:27.227060 RX DQS gating : PASS
9103 10:02:27.229957 RX DQ/DQS(RDDQC) : PASS
9104 10:02:27.233409 TX DQ/DQS : PASS
9105 10:02:27.233831 RX DATLAT : PASS
9106 10:02:27.236842 RX DQ/DQS(Engine): PASS
9107 10:02:27.240496 TX OE : PASS
9108 10:02:27.241061 All Pass.
9109 10:02:27.241520
9110 10:02:27.241846 CH 1, Rank 0
9111 10:02:27.243586 SW Impedance : PASS
9112 10:02:27.247009 DUTY Scan : NO K
9113 10:02:27.247469 ZQ Calibration : PASS
9114 10:02:27.249816 Jitter Meter : NO K
9115 10:02:27.253746 CBT Training : PASS
9116 10:02:27.254172 Write leveling : PASS
9117 10:02:27.256851 RX DQS gating : PASS
9118 10:02:27.259815 RX DQ/DQS(RDDQC) : PASS
9119 10:02:27.260242 TX DQ/DQS : PASS
9120 10:02:27.263112 RX DATLAT : PASS
9121 10:02:27.263543 RX DQ/DQS(Engine): PASS
9122 10:02:27.266538 TX OE : PASS
9123 10:02:27.266969 All Pass.
9124 10:02:27.267308
9125 10:02:27.269945 CH 1, Rank 1
9126 10:02:27.270374 SW Impedance : PASS
9127 10:02:27.273052 DUTY Scan : NO K
9128 10:02:27.276194 ZQ Calibration : PASS
9129 10:02:27.276622 Jitter Meter : NO K
9130 10:02:27.279896 CBT Training : PASS
9131 10:02:27.282946 Write leveling : PASS
9132 10:02:27.283372 RX DQS gating : PASS
9133 10:02:27.286571 RX DQ/DQS(RDDQC) : PASS
9134 10:02:27.289587 TX DQ/DQS : PASS
9135 10:02:27.290016 RX DATLAT : PASS
9136 10:02:27.292938 RX DQ/DQS(Engine): PASS
9137 10:02:27.296516 TX OE : PASS
9138 10:02:27.296974 All Pass.
9139 10:02:27.297311
9140 10:02:27.297622 DramC Write-DBI on
9141 10:02:27.299674 PER_BANK_REFRESH: Hybrid Mode
9142 10:02:27.303082 TX_TRACKING: ON
9143 10:02:27.309948 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9144 10:02:27.319358 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9145 10:02:27.325833 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9146 10:02:27.329259 [FAST_K] Save calibration result to emmc
9147 10:02:27.332492 sync common calibartion params.
9148 10:02:27.335800 sync cbt_mode0:1, 1:1
9149 10:02:27.336227 dram_init: ddr_geometry: 2
9150 10:02:27.339076 dram_init: ddr_geometry: 2
9151 10:02:27.342436 dram_init: ddr_geometry: 2
9152 10:02:27.345746 0:dram_rank_size:100000000
9153 10:02:27.346202 1:dram_rank_size:100000000
9154 10:02:27.352378 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9155 10:02:27.356034 DFS_SHUFFLE_HW_MODE: ON
9156 10:02:27.358998 dramc_set_vcore_voltage set vcore to 725000
9157 10:02:27.359425 Read voltage for 1600, 0
9158 10:02:27.362249 Vio18 = 0
9159 10:02:27.362731 Vcore = 725000
9160 10:02:27.363106 Vdram = 0
9161 10:02:27.365717 Vddq = 0
9162 10:02:27.366206 Vmddr = 0
9163 10:02:27.368914 switch to 3200 Mbps bootup
9164 10:02:27.369365 [DramcRunTimeConfig]
9165 10:02:27.372436 PHYPLL
9166 10:02:27.372881 DPM_CONTROL_AFTERK: ON
9167 10:02:27.375929 PER_BANK_REFRESH: ON
9168 10:02:27.378776 REFRESH_OVERHEAD_REDUCTION: ON
9169 10:02:27.379175 CMD_PICG_NEW_MODE: OFF
9170 10:02:27.382205 XRTWTW_NEW_MODE: ON
9171 10:02:27.382724 XRTRTR_NEW_MODE: ON
9172 10:02:27.385510 TX_TRACKING: ON
9173 10:02:27.385993 RDSEL_TRACKING: OFF
9174 10:02:27.388871 DQS Precalculation for DVFS: ON
9175 10:02:27.392114 RX_TRACKING: OFF
9176 10:02:27.392687 HW_GATING DBG: ON
9177 10:02:27.395917 ZQCS_ENABLE_LP4: ON
9178 10:02:27.396395 RX_PICG_NEW_MODE: ON
9179 10:02:27.398624 TX_PICG_NEW_MODE: ON
9180 10:02:27.399060 ENABLE_RX_DCM_DPHY: ON
9181 10:02:27.402423 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9182 10:02:27.405305 DUMMY_READ_FOR_TRACKING: OFF
9183 10:02:27.409085 !!! SPM_CONTROL_AFTERK: OFF
9184 10:02:27.411843 !!! SPM could not control APHY
9185 10:02:27.412352 IMPEDANCE_TRACKING: ON
9186 10:02:27.415322 TEMP_SENSOR: ON
9187 10:02:27.415810 HW_SAVE_FOR_SR: OFF
9188 10:02:27.418571 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9189 10:02:27.422080 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9190 10:02:27.425269 Read ODT Tracking: ON
9191 10:02:27.428596 Refresh Rate DeBounce: ON
9192 10:02:27.429138 DFS_NO_QUEUE_FLUSH: ON
9193 10:02:27.431829 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9194 10:02:27.435092 ENABLE_DFS_RUNTIME_MRW: OFF
9195 10:02:27.438615 DDR_RESERVE_NEW_MODE: ON
9196 10:02:27.439096 MR_CBT_SWITCH_FREQ: ON
9197 10:02:27.441646 =========================
9198 10:02:27.460846 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9199 10:02:27.463873 dram_init: ddr_geometry: 2
9200 10:02:27.482835 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9201 10:02:27.485287 dram_init: dram init end (result: 0)
9202 10:02:27.492695 DRAM-K: Full calibration passed in 24456 msecs
9203 10:02:27.495576 MRC: failed to locate region type 0.
9204 10:02:27.496181 DRAM rank0 size:0x100000000,
9205 10:02:27.498638 DRAM rank1 size=0x100000000
9206 10:02:27.508614 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9207 10:02:27.515038 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9208 10:02:27.522048 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9209 10:02:27.531879 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9210 10:02:27.532344 DRAM rank0 size:0x100000000,
9211 10:02:27.534876 DRAM rank1 size=0x100000000
9212 10:02:27.535338 CBMEM:
9213 10:02:27.538114 IMD: root @ 0xfffff000 254 entries.
9214 10:02:27.541586 IMD: root @ 0xffffec00 62 entries.
9215 10:02:27.544732 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9216 10:02:27.551498 WARNING: RO_VPD is uninitialized or empty.
9217 10:02:27.554776 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9218 10:02:27.562295 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9219 10:02:27.574876 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9220 10:02:27.586373 BS: romstage times (exec / console): total (unknown) / 23966 ms
9221 10:02:27.586796
9222 10:02:27.587162
9223 10:02:27.596314 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9224 10:02:27.599609 ARM64: Exception handlers installed.
9225 10:02:27.602840 ARM64: Testing exception
9226 10:02:27.605921 ARM64: Done test exception
9227 10:02:27.606359 Enumerating buses...
9228 10:02:27.609214 Show all devs... Before device enumeration.
9229 10:02:27.612720 Root Device: enabled 1
9230 10:02:27.616008 CPU_CLUSTER: 0: enabled 1
9231 10:02:27.616424 CPU: 00: enabled 1
9232 10:02:27.619267 Compare with tree...
9233 10:02:27.619707 Root Device: enabled 1
9234 10:02:27.622807 CPU_CLUSTER: 0: enabled 1
9235 10:02:27.625925 CPU: 00: enabled 1
9236 10:02:27.626341 Root Device scanning...
9237 10:02:27.629176 scan_static_bus for Root Device
9238 10:02:27.632899 CPU_CLUSTER: 0 enabled
9239 10:02:27.635782 scan_static_bus for Root Device done
9240 10:02:27.639773 scan_bus: bus Root Device finished in 8 msecs
9241 10:02:27.640191 done
9242 10:02:27.645823 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9243 10:02:27.648864 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9244 10:02:27.655611 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9245 10:02:27.658829 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9246 10:02:27.662274 Allocating resources...
9247 10:02:27.665199 Reading resources...
9248 10:02:27.668656 Root Device read_resources bus 0 link: 0
9249 10:02:27.672045 DRAM rank0 size:0x100000000,
9250 10:02:27.672521 DRAM rank1 size=0x100000000
9251 10:02:27.675270 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9252 10:02:27.678640 CPU: 00 missing read_resources
9253 10:02:27.685571 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9254 10:02:27.688406 Root Device read_resources bus 0 link: 0 done
9255 10:02:27.692163 Done reading resources.
9256 10:02:27.695083 Show resources in subtree (Root Device)...After reading.
9257 10:02:27.698266 Root Device child on link 0 CPU_CLUSTER: 0
9258 10:02:27.701701 CPU_CLUSTER: 0 child on link 0 CPU: 00
9259 10:02:27.711792 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9260 10:02:27.712191 CPU: 00
9261 10:02:27.718568 Root Device assign_resources, bus 0 link: 0
9262 10:02:27.719172 CPU_CLUSTER: 0 missing set_resources
9263 10:02:27.725020 Root Device assign_resources, bus 0 link: 0 done
9264 10:02:27.725440 Done setting resources.
9265 10:02:27.731602 Show resources in subtree (Root Device)...After assigning values.
9266 10:02:27.734959 Root Device child on link 0 CPU_CLUSTER: 0
9267 10:02:27.738528 CPU_CLUSTER: 0 child on link 0 CPU: 00
9268 10:02:27.747877 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9269 10:02:27.748398 CPU: 00
9270 10:02:27.750962 Done allocating resources.
9271 10:02:27.758001 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9272 10:02:27.758578 Enabling resources...
9273 10:02:27.761106 done.
9274 10:02:27.764601 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9275 10:02:27.768147 Initializing devices...
9276 10:02:27.768675 Root Device init
9277 10:02:27.771272 init hardware done!
9278 10:02:27.771735 0x00000018: ctrlr->caps
9279 10:02:27.774676 52.000 MHz: ctrlr->f_max
9280 10:02:27.777960 0.400 MHz: ctrlr->f_min
9281 10:02:27.778437 0x40ff8080: ctrlr->voltages
9282 10:02:27.781116 sclk: 390625
9283 10:02:27.781576 Bus Width = 1
9284 10:02:27.784567 sclk: 390625
9285 10:02:27.785190 Bus Width = 1
9286 10:02:27.787399 Early init status = 3
9287 10:02:27.791064 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9288 10:02:27.794126 in-header: 03 fc 00 00 01 00 00 00
9289 10:02:27.797669 in-data: 00
9290 10:02:27.800739 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9291 10:02:27.805092 in-header: 03 fd 00 00 00 00 00 00
9292 10:02:27.808285 in-data:
9293 10:02:27.811605 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9294 10:02:27.815278 in-header: 03 fc 00 00 01 00 00 00
9295 10:02:27.818677 in-data: 00
9296 10:02:27.821685 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9297 10:02:27.827056 in-header: 03 fd 00 00 00 00 00 00
9298 10:02:27.829956 in-data:
9299 10:02:27.833518 [SSUSB] Setting up USB HOST controller...
9300 10:02:27.836548 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9301 10:02:27.840389 [SSUSB] phy power-on done.
9302 10:02:27.843241 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9303 10:02:27.849820 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9304 10:02:27.853719 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9305 10:02:27.860008 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9306 10:02:27.866465 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9307 10:02:27.873756 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9308 10:02:27.879778 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9309 10:02:27.886154 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9310 10:02:27.889602 SPM: binary array size = 0x9dc
9311 10:02:27.892878 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9312 10:02:27.899698 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9313 10:02:27.906320 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9314 10:02:27.912547 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9315 10:02:27.916011 configure_display: Starting display init
9316 10:02:27.950519 anx7625_power_on_init: Init interface.
9317 10:02:27.953364 anx7625_disable_pd_protocol: Disabled PD feature.
9318 10:02:27.956482 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9319 10:02:27.984271 anx7625_start_dp_work: Secure OCM version=00
9320 10:02:27.987535 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9321 10:02:28.002669 sp_tx_get_edid_block: EDID Block = 1
9322 10:02:28.105236 Extracted contents:
9323 10:02:28.108552 header: 00 ff ff ff ff ff ff 00
9324 10:02:28.111894 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9325 10:02:28.115007 version: 01 04
9326 10:02:28.118673 basic params: 95 1f 11 78 0a
9327 10:02:28.121670 chroma info: 76 90 94 55 54 90 27 21 50 54
9328 10:02:28.124876 established: 00 00 00
9329 10:02:28.131190 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9330 10:02:28.134952 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9331 10:02:28.141298 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9332 10:02:28.148393 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9333 10:02:28.154857 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9334 10:02:28.158090 extensions: 00
9335 10:02:28.158509 checksum: fb
9336 10:02:28.158842
9337 10:02:28.161611 Manufacturer: IVO Model 57d Serial Number 0
9338 10:02:28.164657 Made week 0 of 2020
9339 10:02:28.165129 EDID version: 1.4
9340 10:02:28.167777 Digital display
9341 10:02:28.171554 6 bits per primary color channel
9342 10:02:28.171977 DisplayPort interface
9343 10:02:28.174582 Maximum image size: 31 cm x 17 cm
9344 10:02:28.177835 Gamma: 220%
9345 10:02:28.178256 Check DPMS levels
9346 10:02:28.181155 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9347 10:02:28.187869 First detailed timing is preferred timing
9348 10:02:28.188392 Established timings supported:
9349 10:02:28.191180 Standard timings supported:
9350 10:02:28.194785 Detailed timings
9351 10:02:28.197731 Hex of detail: 383680a07038204018303c0035ae10000019
9352 10:02:28.201404 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9353 10:02:28.208084 0780 0798 07c8 0820 hborder 0
9354 10:02:28.211315 0438 043b 0447 0458 vborder 0
9355 10:02:28.214707 -hsync -vsync
9356 10:02:28.215173 Did detailed timing
9357 10:02:28.221314 Hex of detail: 000000000000000000000000000000000000
9358 10:02:28.221786 Manufacturer-specified data, tag 0
9359 10:02:28.227431 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9360 10:02:28.231233 ASCII string: InfoVision
9361 10:02:28.234274 Hex of detail: 000000fe00523134304e574635205248200a
9362 10:02:28.237710 ASCII string: R140NWF5 RH
9363 10:02:28.238162 Checksum
9364 10:02:28.240933 Checksum: 0xfb (valid)
9365 10:02:28.244218 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9366 10:02:28.247515 DSI data_rate: 832800000 bps
9367 10:02:28.254298 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9368 10:02:28.257413 anx7625_parse_edid: pixelclock(138800).
9369 10:02:28.260439 hactive(1920), hsync(48), hfp(24), hbp(88)
9370 10:02:28.263836 vactive(1080), vsync(12), vfp(3), vbp(17)
9371 10:02:28.267096 anx7625_dsi_config: config dsi.
9372 10:02:28.273984 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9373 10:02:28.287511 anx7625_dsi_config: success to config DSI
9374 10:02:28.290722 anx7625_dp_start: MIPI phy setup OK.
9375 10:02:28.293987 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9376 10:02:28.296893 mtk_ddp_mode_set invalid vrefresh 60
9377 10:02:28.300899 main_disp_path_setup
9378 10:02:28.301460 ovl_layer_smi_id_en
9379 10:02:28.304141 ovl_layer_smi_id_en
9380 10:02:28.304807 ccorr_config
9381 10:02:28.305196 aal_config
9382 10:02:28.306885 gamma_config
9383 10:02:28.307342 postmask_config
9384 10:02:28.310475 dither_config
9385 10:02:28.313831 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9386 10:02:28.320191 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9387 10:02:28.323449 Root Device init finished in 551 msecs
9388 10:02:28.326921 CPU_CLUSTER: 0 init
9389 10:02:28.333212 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9390 10:02:28.340003 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9391 10:02:28.340478 APU_MBOX 0x190000b0 = 0x10001
9392 10:02:28.343369 APU_MBOX 0x190001b0 = 0x10001
9393 10:02:28.346993 APU_MBOX 0x190005b0 = 0x10001
9394 10:02:28.349867 APU_MBOX 0x190006b0 = 0x10001
9395 10:02:28.356375 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9396 10:02:28.366237 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9397 10:02:28.378892 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9398 10:02:28.385360 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9399 10:02:28.396895 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9400 10:02:28.405724 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9401 10:02:28.409164 CPU_CLUSTER: 0 init finished in 81 msecs
9402 10:02:28.412583 Devices initialized
9403 10:02:28.416280 Show all devs... After init.
9404 10:02:28.416744 Root Device: enabled 1
9405 10:02:28.419161 CPU_CLUSTER: 0: enabled 1
9406 10:02:28.422256 CPU: 00: enabled 1
9407 10:02:28.425953 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9408 10:02:28.428870 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9409 10:02:28.432214 ELOG: NV offset 0x57f000 size 0x1000
9410 10:02:28.439081 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9411 10:02:28.445497 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9412 10:02:28.449221 ELOG: Event(17) added with size 13 at 2023-06-10 10:02:27 UTC
9413 10:02:28.455394 out: cmd=0x121: 03 db 21 01 00 00 00 00
9414 10:02:28.459086 in-header: 03 63 00 00 2c 00 00 00
9415 10:02:28.468812 in-data: fd 67 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9416 10:02:28.475596 ELOG: Event(A1) added with size 10 at 2023-06-10 10:02:27 UTC
9417 10:02:28.482429 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9418 10:02:28.488985 ELOG: Event(A0) added with size 9 at 2023-06-10 10:02:27 UTC
9419 10:02:28.492179 elog_add_boot_reason: Logged dev mode boot
9420 10:02:28.498510 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9421 10:02:28.499083 Finalize devices...
9422 10:02:28.501765 Devices finalized
9423 10:02:28.505476 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9424 10:02:28.508301 Writing coreboot table at 0xffe64000
9425 10:02:28.511882 0. 000000000010a000-0000000000113fff: RAMSTAGE
9426 10:02:28.515070 1. 0000000040000000-00000000400fffff: RAM
9427 10:02:28.521436 2. 0000000040100000-000000004032afff: RAMSTAGE
9428 10:02:28.524877 3. 000000004032b000-00000000545fffff: RAM
9429 10:02:28.528141 4. 0000000054600000-000000005465ffff: BL31
9430 10:02:28.531298 5. 0000000054660000-00000000ffe63fff: RAM
9431 10:02:28.538002 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9432 10:02:28.541848 7. 0000000100000000-000000023fffffff: RAM
9433 10:02:28.544607 Passing 5 GPIOs to payload:
9434 10:02:28.548136 NAME | PORT | POLARITY | VALUE
9435 10:02:28.554776 EC in RW | 0x000000aa | low | undefined
9436 10:02:28.557866 EC interrupt | 0x00000005 | low | undefined
9437 10:02:28.560938 TPM interrupt | 0x000000ab | high | undefined
9438 10:02:28.568248 SD card detect | 0x00000011 | high | undefined
9439 10:02:28.571892 speaker enable | 0x00000093 | high | undefined
9440 10:02:28.574617 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9441 10:02:28.578011 in-header: 03 f9 00 00 02 00 00 00
9442 10:02:28.581665 in-data: 02 00
9443 10:02:28.584531 ADC[4]: Raw value=901770 ID=7
9444 10:02:28.585140 ADC[3]: Raw value=213179 ID=1
9445 10:02:28.588148 RAM Code: 0x71
9446 10:02:28.591084 ADC[6]: Raw value=74502 ID=0
9447 10:02:28.591661 ADC[5]: Raw value=212810 ID=1
9448 10:02:28.594362 SKU Code: 0x1
9449 10:02:28.601313 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9450 10:02:28.601898 coreboot table: 964 bytes.
9451 10:02:28.604469 IMD ROOT 0. 0xfffff000 0x00001000
9452 10:02:28.607885 IMD SMALL 1. 0xffffe000 0x00001000
9453 10:02:28.611268 RO MCACHE 2. 0xffffc000 0x00001104
9454 10:02:28.614741 CONSOLE 3. 0xfff7c000 0x00080000
9455 10:02:28.617860 FMAP 4. 0xfff7b000 0x00000452
9456 10:02:28.620950 TIME STAMP 5. 0xfff7a000 0x00000910
9457 10:02:28.624267 VBOOT WORK 6. 0xfff66000 0x00014000
9458 10:02:28.627652 RAMOOPS 7. 0xffe66000 0x00100000
9459 10:02:28.631193 COREBOOT 8. 0xffe64000 0x00002000
9460 10:02:28.634084 IMD small region:
9461 10:02:28.637504 IMD ROOT 0. 0xffffec00 0x00000400
9462 10:02:28.640924 VPD 1. 0xffffeba0 0x0000004c
9463 10:02:28.643899 MMC STATUS 2. 0xffffeb80 0x00000004
9464 10:02:28.647420 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9465 10:02:28.650719 Probing TPM: done!
9466 10:02:28.654235 Connected to device vid:did:rid of 1ae0:0028:00
9467 10:02:28.664747 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9468 10:02:28.667951 Initialized TPM device CR50 revision 0
9469 10:02:28.671543 Checking cr50 for pending updates
9470 10:02:28.675794 Reading cr50 TPM mode
9471 10:02:28.684326 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9472 10:02:28.690898 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9473 10:02:28.730951 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9474 10:02:28.734061 Checking segment from ROM address 0x40100000
9475 10:02:28.737956 Checking segment from ROM address 0x4010001c
9476 10:02:28.744236 Loading segment from ROM address 0x40100000
9477 10:02:28.744839 code (compression=0)
9478 10:02:28.754622 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9479 10:02:28.760693 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9480 10:02:28.761203 it's not compressed!
9481 10:02:28.767322 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9482 10:02:28.770813 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9483 10:02:28.791572 Loading segment from ROM address 0x4010001c
9484 10:02:28.792140 Entry Point 0x80000000
9485 10:02:28.794451 Loaded segments
9486 10:02:28.798357 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9487 10:02:28.804683 Jumping to boot code at 0x80000000(0xffe64000)
9488 10:02:28.811094 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9489 10:02:28.818016 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9490 10:02:28.825324 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9491 10:02:28.828827 Checking segment from ROM address 0x40100000
9492 10:02:28.832322 Checking segment from ROM address 0x4010001c
9493 10:02:28.839490 Loading segment from ROM address 0x40100000
9494 10:02:28.839958 code (compression=1)
9495 10:02:28.845603 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9496 10:02:28.855936 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9497 10:02:28.856534 using LZMA
9498 10:02:28.864230 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9499 10:02:28.870726 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9500 10:02:28.873751 Loading segment from ROM address 0x4010001c
9501 10:02:28.874174 Entry Point 0x54601000
9502 10:02:28.877090 Loaded segments
9503 10:02:28.880388 NOTICE: MT8192 bl31_setup
9504 10:02:28.887591 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9505 10:02:28.891386 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9506 10:02:28.894544 WARNING: region 0:
9507 10:02:28.897916 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 10:02:28.898340 WARNING: region 1:
9509 10:02:28.904311 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9510 10:02:28.907413 WARNING: region 2:
9511 10:02:28.911044 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9512 10:02:28.914297 WARNING: region 3:
9513 10:02:28.917698 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9514 10:02:28.920664 WARNING: region 4:
9515 10:02:28.927211 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9516 10:02:28.927851 WARNING: region 5:
9517 10:02:28.931134 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 10:02:28.933786 WARNING: region 6:
9519 10:02:28.937290 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9520 10:02:28.940456 WARNING: region 7:
9521 10:02:28.943831 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9522 10:02:28.950928 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9523 10:02:28.954014 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9524 10:02:28.957376 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9525 10:02:28.963883 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9526 10:02:28.967041 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9527 10:02:28.970524 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9528 10:02:28.976861 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9529 10:02:28.980508 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9530 10:02:28.987561 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9531 10:02:28.990500 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9532 10:02:28.993887 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9533 10:02:29.000664 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9534 10:02:29.003904 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9535 10:02:29.007253 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9536 10:02:29.013761 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9537 10:02:29.017117 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9538 10:02:29.023750 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9539 10:02:29.027200 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9540 10:02:29.030346 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9541 10:02:29.036994 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9542 10:02:29.040393 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9543 10:02:29.046932 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9544 10:02:29.050633 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9545 10:02:29.054001 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9546 10:02:29.060364 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9547 10:02:29.063566 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9548 10:02:29.070763 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9549 10:02:29.073913 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9550 10:02:29.077430 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9551 10:02:29.083855 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9552 10:02:29.086837 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9553 10:02:29.093475 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9554 10:02:29.096687 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9555 10:02:29.099950 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9556 10:02:29.103471 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9557 10:02:29.110140 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9558 10:02:29.113430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9559 10:02:29.116757 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9560 10:02:29.119791 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9561 10:02:29.123610 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9562 10:02:29.130657 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9563 10:02:29.133401 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9564 10:02:29.137314 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9565 10:02:29.143557 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9566 10:02:29.147132 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9567 10:02:29.150379 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9568 10:02:29.153302 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9569 10:02:29.159909 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9570 10:02:29.163777 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9571 10:02:29.167456 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9572 10:02:29.173468 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9573 10:02:29.176860 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9574 10:02:29.183435 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9575 10:02:29.186609 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9576 10:02:29.193165 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9577 10:02:29.196913 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9578 10:02:29.200151 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9579 10:02:29.206980 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9580 10:02:29.209733 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9581 10:02:29.216411 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9582 10:02:29.220200 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9583 10:02:29.226557 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9584 10:02:29.229873 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9585 10:02:29.236263 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9586 10:02:29.239571 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9587 10:02:29.243173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9588 10:02:29.250017 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9589 10:02:29.253154 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9590 10:02:29.259791 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9591 10:02:29.263369 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9592 10:02:29.269491 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9593 10:02:29.272861 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9594 10:02:29.276365 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9595 10:02:29.282667 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9596 10:02:29.286023 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9597 10:02:29.292827 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9598 10:02:29.295917 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9599 10:02:29.302524 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9600 10:02:29.306455 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9601 10:02:29.312697 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9602 10:02:29.316111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9603 10:02:29.319275 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9604 10:02:29.325852 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9605 10:02:29.329302 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9606 10:02:29.335598 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9607 10:02:29.339447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9608 10:02:29.346046 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9609 10:02:29.349328 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9610 10:02:29.352315 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9611 10:02:29.358935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9612 10:02:29.362718 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9613 10:02:29.369419 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9614 10:02:29.372546 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9615 10:02:29.379498 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9616 10:02:29.382000 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9617 10:02:29.388893 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9618 10:02:29.392276 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9619 10:02:29.395514 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9620 10:02:29.398790 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9621 10:02:29.405512 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9622 10:02:29.408891 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9623 10:02:29.412470 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9624 10:02:29.419253 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9625 10:02:29.422033 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9626 10:02:29.429107 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9627 10:02:29.431979 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9628 10:02:29.435532 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9629 10:02:29.441983 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9630 10:02:29.445827 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9631 10:02:29.452066 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9632 10:02:29.455255 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9633 10:02:29.458585 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9634 10:02:29.465283 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9635 10:02:29.468815 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9636 10:02:29.475506 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9637 10:02:29.479045 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9638 10:02:29.481952 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9639 10:02:29.485393 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9640 10:02:29.491748 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9641 10:02:29.494950 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9642 10:02:29.498459 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9643 10:02:29.501847 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9644 10:02:29.508248 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9645 10:02:29.511809 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9646 10:02:29.515226 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9647 10:02:29.522039 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9648 10:02:29.525123 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9649 10:02:29.531383 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9650 10:02:29.535289 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9651 10:02:29.538319 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9652 10:02:29.545586 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9653 10:02:29.547992 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9654 10:02:29.554941 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9655 10:02:29.558252 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9656 10:02:29.561249 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9657 10:02:29.568201 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9658 10:02:29.571698 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9659 10:02:29.574503 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9660 10:02:29.581199 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9661 10:02:29.584887 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9662 10:02:29.591495 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9663 10:02:29.594438 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9664 10:02:29.601300 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9665 10:02:29.604378 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9666 10:02:29.607812 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9667 10:02:29.614547 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9668 10:02:29.617512 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9669 10:02:29.621760 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9670 10:02:29.627651 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9671 10:02:29.631180 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9672 10:02:29.637387 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9673 10:02:29.641223 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9674 10:02:29.644685 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9675 10:02:29.651075 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9676 10:02:29.654586 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9677 10:02:29.661002 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9678 10:02:29.664742 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9679 10:02:29.667863 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9680 10:02:29.674573 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9681 10:02:29.677658 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9682 10:02:29.684267 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9683 10:02:29.688139 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9684 10:02:29.690897 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9685 10:02:29.697656 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9686 10:02:29.700916 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9687 10:02:29.703973 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9688 10:02:29.711065 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9689 10:02:29.714326 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9690 10:02:29.720301 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9691 10:02:29.723582 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9692 10:02:29.730322 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9693 10:02:29.733624 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9694 10:02:29.736909 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9695 10:02:29.743659 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9696 10:02:29.746755 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9697 10:02:29.750106 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9698 10:02:29.756806 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9699 10:02:29.760164 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9700 10:02:29.766588 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9701 10:02:29.770530 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9702 10:02:29.773999 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9703 10:02:29.779784 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9704 10:02:29.783343 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9705 10:02:29.790056 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9706 10:02:29.793295 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9707 10:02:29.799494 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9708 10:02:29.803270 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9709 10:02:29.806107 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9710 10:02:29.812842 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9711 10:02:29.816435 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9712 10:02:29.822881 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9713 10:02:29.826411 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9714 10:02:29.829266 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9715 10:02:29.835991 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9716 10:02:29.839125 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9717 10:02:29.845672 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9718 10:02:29.849529 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9719 10:02:29.855944 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9720 10:02:29.859057 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9721 10:02:29.862419 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9722 10:02:29.869190 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9723 10:02:29.873112 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9724 10:02:29.879259 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9725 10:02:29.883029 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9726 10:02:29.885695 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9727 10:02:29.892304 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9728 10:02:29.896315 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9729 10:02:29.902035 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9730 10:02:29.905509 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9731 10:02:29.912035 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9732 10:02:29.915559 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9733 10:02:29.918431 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9734 10:02:29.925139 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9735 10:02:29.928210 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9736 10:02:29.934832 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9737 10:02:29.938254 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9738 10:02:29.944947 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9739 10:02:29.948293 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9740 10:02:29.951538 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9741 10:02:29.958384 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9742 10:02:29.961681 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9743 10:02:29.968622 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9744 10:02:29.971125 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9745 10:02:29.974536 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9746 10:02:29.981486 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9747 10:02:29.984808 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9748 10:02:29.991753 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9749 10:02:29.994892 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9750 10:02:30.001873 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9751 10:02:30.004796 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9752 10:02:30.008210 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9753 10:02:30.011177 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9754 10:02:30.014277 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9755 10:02:30.021009 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9756 10:02:30.024152 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9757 10:02:30.031153 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9758 10:02:30.034230 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9759 10:02:30.037822 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9760 10:02:30.044226 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9761 10:02:30.048103 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9762 10:02:30.050870 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9763 10:02:30.057281 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9764 10:02:30.060799 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9765 10:02:30.064210 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9766 10:02:30.070691 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9767 10:02:30.074159 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9768 10:02:30.080518 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9769 10:02:30.084095 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9770 10:02:30.087660 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9771 10:02:30.094032 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9772 10:02:30.096936 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9773 10:02:30.103951 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9774 10:02:30.107293 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9775 10:02:30.110236 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9776 10:02:30.116751 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9777 10:02:30.119759 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9778 10:02:30.123396 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9779 10:02:30.130231 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9780 10:02:30.133250 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9781 10:02:30.136850 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9782 10:02:30.143729 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9783 10:02:30.147138 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9784 10:02:30.153206 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9785 10:02:30.156749 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9786 10:02:30.160002 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9787 10:02:30.166628 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9788 10:02:30.169847 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9789 10:02:30.176871 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9790 10:02:30.179401 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9791 10:02:30.183338 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9792 10:02:30.186098 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9793 10:02:30.189567 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9794 10:02:30.196332 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9795 10:02:30.199653 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9796 10:02:30.202741 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9797 10:02:30.206348 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9798 10:02:30.213339 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9799 10:02:30.216645 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9800 10:02:30.219248 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9801 10:02:30.222547 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9802 10:02:30.229263 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9803 10:02:30.232463 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9804 10:02:30.235587 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9805 10:02:30.242342 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9806 10:02:30.246154 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9807 10:02:30.252132 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9808 10:02:30.255660 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9809 10:02:30.262151 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9810 10:02:30.265335 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9811 10:02:30.268955 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9812 10:02:30.275040 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9813 10:02:30.278594 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9814 10:02:30.285702 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9815 10:02:30.288228 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9816 10:02:30.295115 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9817 10:02:30.298409 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9818 10:02:30.301650 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9819 10:02:30.308793 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9820 10:02:30.311540 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9821 10:02:30.318450 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9822 10:02:30.321524 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9823 10:02:30.324837 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9824 10:02:30.331358 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9825 10:02:30.334747 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9826 10:02:30.341421 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9827 10:02:30.344803 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9828 10:02:30.347795 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9829 10:02:30.354555 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9830 10:02:30.357810 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9831 10:02:30.364401 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9832 10:02:30.368016 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9833 10:02:30.374289 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9834 10:02:30.377470 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9835 10:02:30.380990 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9836 10:02:30.387979 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9837 10:02:30.390990 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9838 10:02:30.397347 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9839 10:02:30.401055 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9840 10:02:30.407970 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9841 10:02:30.410986 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9842 10:02:30.414344 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9843 10:02:30.420847 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9844 10:02:30.424109 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9845 10:02:30.430220 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9846 10:02:30.433753 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9847 10:02:30.440409 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9848 10:02:30.443637 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9849 10:02:30.446853 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9850 10:02:30.453439 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9851 10:02:30.456634 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9852 10:02:30.463506 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9853 10:02:30.466781 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9854 10:02:30.469782 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9855 10:02:30.476604 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9856 10:02:30.479494 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9857 10:02:30.486431 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9858 10:02:30.490136 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9859 10:02:30.493060 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9860 10:02:30.499725 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9861 10:02:30.502951 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9862 10:02:30.509981 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9863 10:02:30.512926 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9864 10:02:30.519676 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9865 10:02:30.522907 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9866 10:02:30.526124 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9867 10:02:30.532675 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9868 10:02:30.536428 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9869 10:02:30.542699 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9870 10:02:30.545768 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9871 10:02:30.549107 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9872 10:02:30.555727 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9873 10:02:30.558855 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9874 10:02:30.565646 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9875 10:02:30.568715 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9876 10:02:30.575216 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9877 10:02:30.578423 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9878 10:02:30.581910 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9879 10:02:30.588479 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9880 10:02:30.591532 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9881 10:02:30.598715 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9882 10:02:30.601568 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9883 10:02:30.608427 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9884 10:02:30.611784 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9885 10:02:30.614962 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9886 10:02:30.621356 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9887 10:02:30.625157 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9888 10:02:30.631740 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9889 10:02:30.634918 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9890 10:02:30.641066 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9891 10:02:30.644818 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9892 10:02:30.651101 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9893 10:02:30.654845 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9894 10:02:30.658031 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9895 10:02:30.664525 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9896 10:02:30.667711 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9897 10:02:30.674150 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9898 10:02:30.677735 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9899 10:02:30.684133 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9900 10:02:30.687649 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9901 10:02:30.694349 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9902 10:02:30.697269 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9903 10:02:30.700809 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9904 10:02:30.707755 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9905 10:02:30.710531 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9906 10:02:30.717496 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9907 10:02:30.720311 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9908 10:02:30.726746 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9909 10:02:30.730104 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9910 10:02:30.737034 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9911 10:02:30.740292 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9912 10:02:30.746836 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9913 10:02:30.750337 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9914 10:02:30.753936 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9915 10:02:30.759991 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9916 10:02:30.763033 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9917 10:02:30.769650 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9918 10:02:30.773198 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9919 10:02:30.779651 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9920 10:02:30.783436 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9921 10:02:30.789696 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9922 10:02:30.793135 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9923 10:02:30.796246 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9924 10:02:30.802733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9925 10:02:30.806532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9926 10:02:30.812647 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9927 10:02:30.815957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9928 10:02:30.822565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9929 10:02:30.826566 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9930 10:02:30.832540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9931 10:02:30.836153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9932 10:02:30.842305 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9933 10:02:30.846010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9934 10:02:30.849121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9935 10:02:30.855850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9936 10:02:30.859453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9937 10:02:30.866131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9938 10:02:30.868969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9939 10:02:30.875723 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9940 10:02:30.878852 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9941 10:02:30.885553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9942 10:02:30.888618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9943 10:02:30.895421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9944 10:02:30.898554 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9945 10:02:30.905256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9946 10:02:30.908348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9947 10:02:30.915399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9948 10:02:30.918436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9949 10:02:30.925120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9950 10:02:30.928301 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9951 10:02:30.935537 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9952 10:02:30.938294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9953 10:02:30.944687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9954 10:02:30.951350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9955 10:02:30.954850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9956 10:02:30.958535 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9957 10:02:30.961299 INFO: [APUAPC] vio 0
9958 10:02:30.964506 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9959 10:02:30.971204 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9960 10:02:30.974355 INFO: [APUAPC] D0_APC_0: 0x400510
9961 10:02:30.978309 INFO: [APUAPC] D0_APC_1: 0x0
9962 10:02:30.981095 INFO: [APUAPC] D0_APC_2: 0x1540
9963 10:02:30.981168 INFO: [APUAPC] D0_APC_3: 0x0
9964 10:02:30.988154 INFO: [APUAPC] D1_APC_0: 0xffffffff
9965 10:02:30.991359 INFO: [APUAPC] D1_APC_1: 0xffffffff
9966 10:02:30.994484 INFO: [APUAPC] D1_APC_2: 0x3fffff
9967 10:02:30.994564 INFO: [APUAPC] D1_APC_3: 0x0
9968 10:02:30.998036 INFO: [APUAPC] D2_APC_0: 0xffffffff
9969 10:02:31.000713 INFO: [APUAPC] D2_APC_1: 0xffffffff
9970 10:02:31.004282 INFO: [APUAPC] D2_APC_2: 0x3fffff
9971 10:02:31.007928 INFO: [APUAPC] D2_APC_3: 0x0
9972 10:02:31.010883 INFO: [APUAPC] D3_APC_0: 0xffffffff
9973 10:02:31.014022 INFO: [APUAPC] D3_APC_1: 0xffffffff
9974 10:02:31.017445 INFO: [APUAPC] D3_APC_2: 0x3fffff
9975 10:02:31.020800 INFO: [APUAPC] D3_APC_3: 0x0
9976 10:02:31.024205 INFO: [APUAPC] D4_APC_0: 0xffffffff
9977 10:02:31.027489 INFO: [APUAPC] D4_APC_1: 0xffffffff
9978 10:02:31.030649 INFO: [APUAPC] D4_APC_2: 0x3fffff
9979 10:02:31.034265 INFO: [APUAPC] D4_APC_3: 0x0
9980 10:02:31.037096 INFO: [APUAPC] D5_APC_0: 0xffffffff
9981 10:02:31.040424 INFO: [APUAPC] D5_APC_1: 0xffffffff
9982 10:02:31.043784 INFO: [APUAPC] D5_APC_2: 0x3fffff
9983 10:02:31.047190 INFO: [APUAPC] D5_APC_3: 0x0
9984 10:02:31.050348 INFO: [APUAPC] D6_APC_0: 0xffffffff
9985 10:02:31.053827 INFO: [APUAPC] D6_APC_1: 0xffffffff
9986 10:02:31.057051 INFO: [APUAPC] D6_APC_2: 0x3fffff
9987 10:02:31.060129 INFO: [APUAPC] D6_APC_3: 0x0
9988 10:02:31.063716 INFO: [APUAPC] D7_APC_0: 0xffffffff
9989 10:02:31.067070 INFO: [APUAPC] D7_APC_1: 0xffffffff
9990 10:02:31.070400 INFO: [APUAPC] D7_APC_2: 0x3fffff
9991 10:02:31.073720 INFO: [APUAPC] D7_APC_3: 0x0
9992 10:02:31.076713 INFO: [APUAPC] D8_APC_0: 0xffffffff
9993 10:02:31.080146 INFO: [APUAPC] D8_APC_1: 0xffffffff
9994 10:02:31.083344 INFO: [APUAPC] D8_APC_2: 0x3fffff
9995 10:02:31.086714 INFO: [APUAPC] D8_APC_3: 0x0
9996 10:02:31.090146 INFO: [APUAPC] D9_APC_0: 0xffffffff
9997 10:02:31.093303 INFO: [APUAPC] D9_APC_1: 0xffffffff
9998 10:02:31.096589 INFO: [APUAPC] D9_APC_2: 0x3fffff
9999 10:02:31.100113 INFO: [APUAPC] D9_APC_3: 0x0
10000 10:02:31.103168 INFO: [APUAPC] D10_APC_0: 0xffffffff
10001 10:02:31.106280 INFO: [APUAPC] D10_APC_1: 0xffffffff
10002 10:02:31.109588 INFO: [APUAPC] D10_APC_2: 0x3fffff
10003 10:02:31.112967 INFO: [APUAPC] D10_APC_3: 0x0
10004 10:02:31.116519 INFO: [APUAPC] D11_APC_0: 0xffffffff
10005 10:02:31.119883 INFO: [APUAPC] D11_APC_1: 0xffffffff
10006 10:02:31.122994 INFO: [APUAPC] D11_APC_2: 0x3fffff
10007 10:02:31.126216 INFO: [APUAPC] D11_APC_3: 0x0
10008 10:02:31.129720 INFO: [APUAPC] D12_APC_0: 0xffffffff
10009 10:02:31.132863 INFO: [APUAPC] D12_APC_1: 0xffffffff
10010 10:02:31.135834 INFO: [APUAPC] D12_APC_2: 0x3fffff
10011 10:02:31.139548 INFO: [APUAPC] D12_APC_3: 0x0
10012 10:02:31.143083 INFO: [APUAPC] D13_APC_0: 0xffffffff
10013 10:02:31.145778 INFO: [APUAPC] D13_APC_1: 0xffffffff
10014 10:02:31.149277 INFO: [APUAPC] D13_APC_2: 0x3fffff
10015 10:02:31.152511 INFO: [APUAPC] D13_APC_3: 0x0
10016 10:02:31.155758 INFO: [APUAPC] D14_APC_0: 0xffffffff
10017 10:02:31.158988 INFO: [APUAPC] D14_APC_1: 0xffffffff
10018 10:02:31.162361 INFO: [APUAPC] D14_APC_2: 0x3fffff
10019 10:02:31.165664 INFO: [APUAPC] D14_APC_3: 0x0
10020 10:02:31.168954 INFO: [APUAPC] D15_APC_0: 0xffffffff
10021 10:02:31.172043 INFO: [APUAPC] D15_APC_1: 0xffffffff
10022 10:02:31.175477 INFO: [APUAPC] D15_APC_2: 0x3fffff
10023 10:02:31.178920 INFO: [APUAPC] D15_APC_3: 0x0
10024 10:02:31.182063 INFO: [APUAPC] APC_CON: 0x4
10025 10:02:31.185563 INFO: [NOCDAPC] D0_APC_0: 0x0
10026 10:02:31.188782 INFO: [NOCDAPC] D0_APC_1: 0x0
10027 10:02:31.192078 INFO: [NOCDAPC] D1_APC_0: 0x0
10028 10:02:31.195407 INFO: [NOCDAPC] D1_APC_1: 0xfff
10029 10:02:31.198534 INFO: [NOCDAPC] D2_APC_0: 0x0
10030 10:02:31.202078 INFO: [NOCDAPC] D2_APC_1: 0xfff
10031 10:02:31.202149 INFO: [NOCDAPC] D3_APC_0: 0x0
10032 10:02:31.205099 INFO: [NOCDAPC] D3_APC_1: 0xfff
10033 10:02:31.208715 INFO: [NOCDAPC] D4_APC_0: 0x0
10034 10:02:31.211598 INFO: [NOCDAPC] D4_APC_1: 0xfff
10035 10:02:31.215143 INFO: [NOCDAPC] D5_APC_0: 0x0
10036 10:02:31.218657 INFO: [NOCDAPC] D5_APC_1: 0xfff
10037 10:02:31.222351 INFO: [NOCDAPC] D6_APC_0: 0x0
10038 10:02:31.225390 INFO: [NOCDAPC] D6_APC_1: 0xfff
10039 10:02:31.228673 INFO: [NOCDAPC] D7_APC_0: 0x0
10040 10:02:31.231908 INFO: [NOCDAPC] D7_APC_1: 0xfff
10041 10:02:31.235037 INFO: [NOCDAPC] D8_APC_0: 0x0
10042 10:02:31.235134 INFO: [NOCDAPC] D8_APC_1: 0xfff
10043 10:02:31.238549 INFO: [NOCDAPC] D9_APC_0: 0x0
10044 10:02:31.241712 INFO: [NOCDAPC] D9_APC_1: 0xfff
10045 10:02:31.245049 INFO: [NOCDAPC] D10_APC_0: 0x0
10046 10:02:31.248540 INFO: [NOCDAPC] D10_APC_1: 0xfff
10047 10:02:31.251827 INFO: [NOCDAPC] D11_APC_0: 0x0
10048 10:02:31.255048 INFO: [NOCDAPC] D11_APC_1: 0xfff
10049 10:02:31.258154 INFO: [NOCDAPC] D12_APC_0: 0x0
10050 10:02:31.262402 INFO: [NOCDAPC] D12_APC_1: 0xfff
10051 10:02:31.265030 INFO: [NOCDAPC] D13_APC_0: 0x0
10052 10:02:31.268509 INFO: [NOCDAPC] D13_APC_1: 0xfff
10053 10:02:31.271838 INFO: [NOCDAPC] D14_APC_0: 0x0
10054 10:02:31.274678 INFO: [NOCDAPC] D14_APC_1: 0xfff
10055 10:02:31.278311 INFO: [NOCDAPC] D15_APC_0: 0x0
10056 10:02:31.281514 INFO: [NOCDAPC] D15_APC_1: 0xfff
10057 10:02:31.281583 INFO: [NOCDAPC] APC_CON: 0x4
10058 10:02:31.284826 INFO: [APUAPC] set_apusys_apc done
10059 10:02:31.288066 INFO: [DEVAPC] devapc_init done
10060 10:02:31.295133 INFO: GICv3 without legacy support detected.
10061 10:02:31.297690 INFO: ARM GICv3 driver initialized in EL3
10062 10:02:31.301691 INFO: Maximum SPI INTID supported: 639
10063 10:02:31.304413 INFO: BL31: Initializing runtime services
10064 10:02:31.311057 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10065 10:02:31.314177 INFO: SPM: enable CPC mode
10066 10:02:31.317479 INFO: mcdi ready for mcusys-off-idle and system suspend
10067 10:02:31.323989 INFO: BL31: Preparing for EL3 exit to normal world
10068 10:02:31.327408 INFO: Entry point address = 0x80000000
10069 10:02:31.327510 INFO: SPSR = 0x8
10070 10:02:31.334775
10071 10:02:31.334884
10072 10:02:31.334981
10073 10:02:31.338527 Starting depthcharge on Spherion...
10074 10:02:31.338627
10075 10:02:31.338717 Wipe memory regions:
10076 10:02:31.338804
10077 10:02:31.339449 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10078 10:02:31.339554 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10079 10:02:31.339644 Setting prompt string to ['asurada:']
10080 10:02:31.339726 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10081 10:02:31.341950 [0x00000040000000, 0x00000054600000)
10082 10:02:31.464248
10083 10:02:31.464432 [0x00000054660000, 0x00000080000000)
10084 10:02:31.724600
10085 10:02:31.724841 [0x000000821a7280, 0x000000ffe64000)
10086 10:02:32.469072
10087 10:02:32.469618 [0x00000100000000, 0x00000240000000)
10088 10:02:34.358602
10089 10:02:34.362005 Initializing XHCI USB controller at 0x11200000.
10090 10:02:35.399411
10091 10:02:35.402889 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10092 10:02:35.402993
10093 10:02:35.403117
10094 10:02:35.403206
10095 10:02:35.403518 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10097 10:02:35.504211 asurada: tftpboot 192.168.201.1 10670651/tftp-deploy-ehdb4tg6/kernel/image.itb 10670651/tftp-deploy-ehdb4tg6/kernel/cmdline
10098 10:02:35.504912 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10099 10:02:35.505383 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10100 10:02:35.510136 tftpboot 192.168.201.1 10670651/tftp-deploy-ehdb4tg6/kernel/image.ittp-deploy-ehdb4tg6/kernel/cmdline
10101 10:02:35.510716
10102 10:02:35.511094 Waiting for link
10103 10:02:35.670478
10104 10:02:35.671043 R8152: Initializing
10105 10:02:35.671419
10106 10:02:35.674048 Version 9 (ocp_data = 6010)
10107 10:02:35.674620
10108 10:02:35.677107 R8152: Done initializing
10109 10:02:35.677622
10110 10:02:35.678013 Adding net device
10111 10:02:37.621560
10112 10:02:37.622090 done.
10113 10:02:37.622557
10114 10:02:37.623016 MAC: 00:e0:4c:72:2d:d6
10115 10:02:37.623597
10116 10:02:37.624733 Sending DHCP discover... done.
10117 10:02:37.625302
10118 10:02:37.629132 Waiting for reply... done.
10119 10:02:37.629807
10120 10:02:37.631237 Sending DHCP request... done.
10121 10:02:37.631772
10122 10:02:37.634740 Waiting for reply... done.
10123 10:02:37.635170
10124 10:02:37.635510 My ip is 192.168.201.21
10125 10:02:37.635865
10126 10:02:37.637949 The DHCP server ip is 192.168.201.1
10127 10:02:37.638422
10128 10:02:37.644712 TFTP server IP predefined by user: 192.168.201.1
10129 10:02:37.645323
10130 10:02:37.651735 Bootfile predefined by user: 10670651/tftp-deploy-ehdb4tg6/kernel/image.itb
10131 10:02:37.652200
10132 10:02:37.654521 Sending tftp read request... done.
10133 10:02:37.655060
10134 10:02:37.659040 Waiting for the transfer...
10135 10:02:37.659498
10136 10:02:37.918186 00000000 ################################################################
10137 10:02:37.918347
10138 10:02:38.170218 00080000 ################################################################
10139 10:02:38.170387
10140 10:02:38.450075 00100000 ################################################################
10141 10:02:38.450209
10142 10:02:38.718305 00180000 ################################################################
10143 10:02:38.718449
10144 10:02:38.977313 00200000 ################################################################
10145 10:02:38.977466
10146 10:02:39.253739 00280000 ################################################################
10147 10:02:39.253887
10148 10:02:39.519333 00300000 ################################################################
10149 10:02:39.519471
10150 10:02:39.794570 00380000 ################################################################
10151 10:02:39.794707
10152 10:02:40.084951 00400000 ################################################################
10153 10:02:40.085106
10154 10:02:40.393887 00480000 ################################################################
10155 10:02:40.394043
10156 10:02:40.676007 00500000 ################################################################
10157 10:02:40.676160
10158 10:02:40.929481 00580000 ################################################################
10159 10:02:40.929627
10160 10:02:41.181326 00600000 ################################################################
10161 10:02:41.181476
10162 10:02:41.431504 00680000 ################################################################
10163 10:02:41.431666
10164 10:02:41.683833 00700000 ################################################################
10165 10:02:41.683997
10166 10:02:41.932538 00780000 ################################################################
10167 10:02:41.932705
10168 10:02:42.202008 00800000 ################################################################
10169 10:02:42.202146
10170 10:02:42.494589 00880000 ################################################################
10171 10:02:42.494723
10172 10:02:42.788745 00900000 ################################################################
10173 10:02:42.788887
10174 10:02:43.081459 00980000 ################################################################
10175 10:02:43.081610
10176 10:02:43.379525 00a00000 ################################################################
10177 10:02:43.379698
10178 10:02:43.650363 00a80000 ################################################################
10179 10:02:43.650516
10180 10:02:43.951006 00b00000 ################################################################
10181 10:02:43.951160
10182 10:02:44.237016 00b80000 ################################################################
10183 10:02:44.237178
10184 10:02:44.525097 00c00000 ################################################################
10185 10:02:44.525232
10186 10:02:44.819105 00c80000 ################################################################
10187 10:02:44.819280
10188 10:02:45.113896 00d00000 ################################################################
10189 10:02:45.114058
10190 10:02:45.413294 00d80000 ################################################################
10191 10:02:45.413444
10192 10:02:45.713663 00e00000 ################################################################
10193 10:02:45.713815
10194 10:02:46.015945 00e80000 ################################################################
10195 10:02:46.016086
10196 10:02:46.319780 00f00000 ################################################################
10197 10:02:46.319929
10198 10:02:46.617648 00f80000 ################################################################
10199 10:02:46.617796
10200 10:02:46.918581 01000000 ################################################################
10201 10:02:46.918728
10202 10:02:47.183841 01080000 ################################################################
10203 10:02:47.183995
10204 10:02:47.467072 01100000 ################################################################
10205 10:02:47.467226
10206 10:02:47.746086 01180000 ################################################################
10207 10:02:47.746242
10208 10:02:47.995407 01200000 ################################################################
10209 10:02:47.995583
10210 10:02:48.244323 01280000 ################################################################
10211 10:02:48.244459
10212 10:02:48.495098 01300000 ################################################################
10213 10:02:48.495262
10214 10:02:48.757335 01380000 ################################################################
10215 10:02:48.757502
10216 10:02:49.029221 01400000 ################################################################
10217 10:02:49.029373
10218 10:02:49.325375 01480000 ################################################################
10219 10:02:49.325523
10220 10:02:49.600567 01500000 ################################################################
10221 10:02:49.600737
10222 10:02:49.895073 01580000 ################################################################
10223 10:02:49.895244
10224 10:02:50.192296 01600000 ################################################################
10225 10:02:50.192467
10226 10:02:50.485455 01680000 ################################################################
10227 10:02:50.485623
10228 10:02:50.781737 01700000 ################################################################
10229 10:02:50.781910
10230 10:02:51.066995 01780000 ################################################################
10231 10:02:51.067136
10232 10:02:51.349867 01800000 ################################################################
10233 10:02:51.350017
10234 10:02:51.634610 01880000 ################################################################
10235 10:02:51.634757
10236 10:02:51.931142 01900000 ################################################################
10237 10:02:51.931288
10238 10:02:52.217431 01980000 ################################################################
10239 10:02:52.217576
10240 10:02:52.501921 01a00000 ################################################################ done.
10241 10:02:52.502072
10242 10:02:52.505190 The bootfile was 27781590 bytes long.
10243 10:02:52.505274
10244 10:02:52.508320 Sending tftp read request... done.
10245 10:02:52.508409
10246 10:02:52.511951 Waiting for the transfer...
10247 10:02:52.512075
10248 10:02:52.512181 00000000 # done.
10249 10:02:52.512287
10250 10:02:52.522119 Command line loaded dynamically from TFTP file: 10670651/tftp-deploy-ehdb4tg6/kernel/cmdline
10251 10:02:52.522311
10252 10:02:52.541639 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10670651/extract-nfsrootfs-69r0vlv_,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10253 10:02:52.542126
10254 10:02:52.542420 Loading FIT.
10255 10:02:52.542692
10256 10:02:52.544978 Image ramdisk-1 has 17645313 bytes.
10257 10:02:52.545342
10258 10:02:52.548408 Image fdt-1 has 46924 bytes.
10259 10:02:52.548798
10260 10:02:52.551807 Image kernel-1 has 10087317 bytes.
10261 10:02:52.552445
10262 10:02:52.558191 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10263 10:02:52.558563
10264 10:02:52.578369 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10265 10:02:52.578950
10266 10:02:52.581788 Choosing best match conf-1 for compat google,spherion-rev2.
10267 10:02:52.586722
10268 10:02:52.590890 Connected to device vid:did:rid of 1ae0:0028:00
10269 10:02:52.598156
10270 10:02:52.601487 tpm_get_response: command 0x17b, return code 0x0
10271 10:02:52.601976
10272 10:02:52.604722 ec_init: CrosEC protocol v3 supported (256, 248)
10273 10:02:52.608713
10274 10:02:52.612205 tpm_cleanup: add release locality here.
10275 10:02:52.612692
10276 10:02:52.613037 Shutting down all USB controllers.
10277 10:02:52.615490
10278 10:02:52.615876 Removing current net device
10279 10:02:52.616182
10280 10:02:52.621838 Exiting depthcharge with code 4 at timestamp: 50537185
10281 10:02:52.622230
10282 10:02:52.625016 LZMA decompressing kernel-1 to 0x821a6718
10283 10:02:52.625403
10284 10:02:52.628476 LZMA decompressing kernel-1 to 0x40000000
10285 10:02:53.895855
10286 10:02:53.896013 jumping to kernel
10287 10:02:53.896420 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10288 10:02:53.896522 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10289 10:02:53.896598 Setting prompt string to ['Linux version [0-9]']
10290 10:02:53.896667 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10291 10:02:53.896737 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10292 10:02:53.977395
10293 10:02:53.981066 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10294 10:02:53.984323 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10295 10:02:53.984414 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10296 10:02:53.984497 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10297 10:02:53.984571 Using line separator: #'\n'#
10298 10:02:53.984632 No login prompt set.
10299 10:02:53.984693 Parsing kernel messages
10300 10:02:53.984749 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10301 10:02:53.984910 [login-action] Waiting for messages, (timeout 00:04:03)
10302 10:02:54.004592 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j19381-arm64-gcc-10-defconfig-arm64-chromebook-d6qsg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023
10303 10:02:54.007385 [ 0.000000] random: crng init done
10304 10:02:54.010600 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10305 10:02:54.013903 [ 0.000000] efi: UEFI not found.
10306 10:02:54.023844 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10307 10:02:54.030490 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10308 10:02:54.040367 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10309 10:02:54.050186 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10310 10:02:54.056947 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10311 10:02:54.060113 [ 0.000000] printk: bootconsole [mtk8250] enabled
10312 10:02:54.068963 [ 0.000000] NUMA: No NUMA configuration found
10313 10:02:54.075350 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10314 10:02:54.081864 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10315 10:02:54.081946 [ 0.000000] Zone ranges:
10316 10:02:54.088715 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10317 10:02:54.091894 [ 0.000000] DMA32 empty
10318 10:02:54.099243 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10319 10:02:54.102109 [ 0.000000] Movable zone start for each node
10320 10:02:54.105280 [ 0.000000] Early memory node ranges
10321 10:02:54.111968 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10322 10:02:54.118301 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10323 10:02:54.125107 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10324 10:02:54.131527 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10325 10:02:54.138326 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10326 10:02:54.144897 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10327 10:02:54.201453 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10328 10:02:54.208212 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10329 10:02:54.214552 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10330 10:02:54.217842 [ 0.000000] psci: probing for conduit method from DT.
10331 10:02:54.224196 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10332 10:02:54.227716 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10333 10:02:54.234228 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10334 10:02:54.237444 [ 0.000000] psci: SMC Calling Convention v1.2
10335 10:02:54.244126 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10336 10:02:54.247498 [ 0.000000] Detected VIPT I-cache on CPU0
10337 10:02:54.254095 [ 0.000000] CPU features: detected: GIC system register CPU interface
10338 10:02:54.260704 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10339 10:02:54.267270 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10340 10:02:54.273722 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10341 10:02:54.283812 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10342 10:02:54.291021 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10343 10:02:54.293625 [ 0.000000] alternatives: applying boot alternatives
10344 10:02:54.300416 [ 0.000000] Fallback order for Node 0: 0
10345 10:02:54.306873 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10346 10:02:54.310566 [ 0.000000] Policy zone: Normal
10347 10:02:54.330073 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10670651/extract-nfsrootfs-69r0vlv_,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10348 10:02:54.340050 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10349 10:02:54.351979 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10350 10:02:54.361946 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10351 10:02:54.368563 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10352 10:02:54.371605 <6>[ 0.000000] software IO TLB: area num 8.
10353 10:02:54.429612 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10354 10:02:54.578972 <6>[ 0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)
10355 10:02:54.585713 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10356 10:02:54.591913 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10357 10:02:54.595128 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10358 10:02:54.601955 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10359 10:02:54.608563 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10360 10:02:54.612219 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10361 10:02:54.621814 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10362 10:02:54.628460 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10363 10:02:54.635065 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10364 10:02:54.641503 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10365 10:02:54.644754 <6>[ 0.000000] GICv3: 608 SPIs implemented
10366 10:02:54.648041 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10367 10:02:54.655008 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10368 10:02:54.657840 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10369 10:02:54.664579 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10370 10:02:54.677795 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10371 10:02:54.691602 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10372 10:02:54.697923 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10373 10:02:54.705544 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10374 10:02:54.718558 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10375 10:02:54.725125 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10376 10:02:54.732096 <6>[ 0.009227] Console: colour dummy device 80x25
10377 10:02:54.741830 <6>[ 0.013953] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10378 10:02:54.747975 <6>[ 0.024395] pid_max: default: 32768 minimum: 301
10379 10:02:54.751695 <6>[ 0.029270] LSM: Security Framework initializing
10380 10:02:54.758553 <6>[ 0.034207] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10381 10:02:54.768173 <6>[ 0.042022] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10382 10:02:54.778268 <6>[ 0.051507] cblist_init_generic: Setting adjustable number of callback queues.
10383 10:02:54.781459 <6>[ 0.058961] cblist_init_generic: Setting shift to 3 and lim to 1.
10384 10:02:54.788645 <6>[ 0.065300] cblist_init_generic: Setting shift to 3 and lim to 1.
10385 10:02:54.794743 <6>[ 0.071707] rcu: Hierarchical SRCU implementation.
10386 10:02:54.801459 <6>[ 0.076721] rcu: Max phase no-delay instances is 1000.
10387 10:02:54.804396 <6>[ 0.083734] EFI services will not be available.
10388 10:02:54.811214 <6>[ 0.088738] smp: Bringing up secondary CPUs ...
10389 10:02:54.818815 <6>[ 0.093818] Detected VIPT I-cache on CPU1
10390 10:02:54.825321 <6>[ 0.093889] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10391 10:02:54.832195 <6>[ 0.093919] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10392 10:02:54.835239 <6>[ 0.094246] Detected VIPT I-cache on CPU2
10393 10:02:54.845089 <6>[ 0.094295] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10394 10:02:54.851676 <6>[ 0.094310] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10395 10:02:54.854815 <6>[ 0.094568] Detected VIPT I-cache on CPU3
10396 10:02:54.861767 <6>[ 0.094615] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10397 10:02:54.867956 <6>[ 0.094628] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10398 10:02:54.871447 <6>[ 0.094936] CPU features: detected: Spectre-v4
10399 10:02:54.878253 <6>[ 0.094943] CPU features: detected: Spectre-BHB
10400 10:02:54.881357 <6>[ 0.094949] Detected PIPT I-cache on CPU4
10401 10:02:54.888083 <6>[ 0.095006] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10402 10:02:54.894586 <6>[ 0.095023] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10403 10:02:54.902001 <6>[ 0.095317] Detected PIPT I-cache on CPU5
10404 10:02:54.908142 <6>[ 0.095381] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10405 10:02:54.914699 <6>[ 0.095398] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10406 10:02:54.917816 <6>[ 0.095684] Detected PIPT I-cache on CPU6
10407 10:02:54.924187 <6>[ 0.095749] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10408 10:02:54.930876 <6>[ 0.095765] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10409 10:02:54.937431 <6>[ 0.096060] Detected PIPT I-cache on CPU7
10410 10:02:54.944113 <6>[ 0.096125] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10411 10:02:54.951220 <6>[ 0.096141] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10412 10:02:54.954157 <6>[ 0.096187] smp: Brought up 1 node, 8 CPUs
10413 10:02:54.960897 <6>[ 0.237526] SMP: Total of 8 processors activated.
10414 10:02:54.964494 <6>[ 0.242447] CPU features: detected: 32-bit EL0 Support
10415 10:02:54.973873 <6>[ 0.247811] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10416 10:02:54.980466 <6>[ 0.256666] CPU features: detected: Common not Private translations
10417 10:02:54.987355 <6>[ 0.263141] CPU features: detected: CRC32 instructions
10418 10:02:54.993437 <6>[ 0.268493] CPU features: detected: RCpc load-acquire (LDAPR)
10419 10:02:54.997226 <6>[ 0.274452] CPU features: detected: LSE atomic instructions
10420 10:02:55.003994 <6>[ 0.280270] CPU features: detected: Privileged Access Never
10421 10:02:55.010247 <6>[ 0.286085] CPU features: detected: RAS Extension Support
10422 10:02:55.017265 <6>[ 0.291728] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10423 10:02:55.020669 <6>[ 0.298995] CPU: All CPU(s) started at EL2
10424 10:02:55.027172 <6>[ 0.303311] alternatives: applying system-wide alternatives
10425 10:02:55.037062 <6>[ 0.314033] devtmpfs: initialized
10426 10:02:55.052677 <6>[ 0.322996] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10427 10:02:55.059035 <6>[ 0.332958] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10428 10:02:55.065688 <6>[ 0.340822] pinctrl core: initialized pinctrl subsystem
10429 10:02:55.068827 <6>[ 0.347505] DMI not present or invalid.
10430 10:02:55.075662 <6>[ 0.351914] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10431 10:02:55.085197 <6>[ 0.358777] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10432 10:02:55.091848 <6>[ 0.366360] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10433 10:02:55.101745 <6>[ 0.374569] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10434 10:02:55.105002 <6>[ 0.382813] audit: initializing netlink subsys (disabled)
10435 10:02:55.115175 <5>[ 0.388510] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10436 10:02:55.122092 <6>[ 0.389218] thermal_sys: Registered thermal governor 'step_wise'
10437 10:02:55.128041 <6>[ 0.396477] thermal_sys: Registered thermal governor 'power_allocator'
10438 10:02:55.131449 <6>[ 0.402734] cpuidle: using governor menu
10439 10:02:55.137986 <6>[ 0.413696] NET: Registered PF_QIPCRTR protocol family
10440 10:02:55.144501 <6>[ 0.419186] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10441 10:02:55.150854 <6>[ 0.426289] ASID allocator initialised with 32768 entries
10442 10:02:55.154161 <6>[ 0.432861] Serial: AMBA PL011 UART driver
10443 10:02:55.164486 <4>[ 0.441585] Trying to register duplicate clock ID: 134
10444 10:02:55.219931 <6>[ 0.500889] KASLR enabled
10445 10:02:55.234359 <6>[ 0.508567] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10446 10:02:55.241173 <6>[ 0.515581] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10447 10:02:55.248130 <6>[ 0.522070] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10448 10:02:55.254407 <6>[ 0.529077] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10449 10:02:55.261364 <6>[ 0.535564] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10450 10:02:55.267609 <6>[ 0.542568] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10451 10:02:55.274299 <6>[ 0.549054] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10452 10:02:55.281168 <6>[ 0.556055] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10453 10:02:55.284505 <6>[ 0.563544] ACPI: Interpreter disabled.
10454 10:02:55.292753 <6>[ 0.569939] iommu: Default domain type: Translated
10455 10:02:55.299816 <6>[ 0.575102] iommu: DMA domain TLB invalidation policy: strict mode
10456 10:02:55.302788 <5>[ 0.581764] SCSI subsystem initialized
10457 10:02:55.309245 <6>[ 0.586001] usbcore: registered new interface driver usbfs
10458 10:02:55.315785 <6>[ 0.591733] usbcore: registered new interface driver hub
10459 10:02:55.319390 <6>[ 0.597284] usbcore: registered new device driver usb
10460 10:02:55.326308 <6>[ 0.603390] pps_core: LinuxPPS API ver. 1 registered
10461 10:02:55.336608 <6>[ 0.608584] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10462 10:02:55.339883 <6>[ 0.617925] PTP clock support registered
10463 10:02:55.342560 <6>[ 0.622166] EDAC MC: Ver: 3.0.0
10464 10:02:55.350003 <6>[ 0.627312] FPGA manager framework
10465 10:02:55.356468 <6>[ 0.630988] Advanced Linux Sound Architecture Driver Initialized.
10466 10:02:55.360227 <6>[ 0.637763] vgaarb: loaded
10467 10:02:55.366262 <6>[ 0.640930] clocksource: Switched to clocksource arch_sys_counter
10468 10:02:55.369605 <5>[ 0.647381] VFS: Disk quotas dquot_6.6.0
10469 10:02:55.376723 <6>[ 0.651566] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10470 10:02:55.379271 <6>[ 0.658758] pnp: PnP ACPI: disabled
10471 10:02:55.387842 <6>[ 0.665448] NET: Registered PF_INET protocol family
10472 10:02:55.398101 <6>[ 0.671027] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10473 10:02:55.409424 <6>[ 0.683330] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10474 10:02:55.418940 <6>[ 0.692147] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10475 10:02:55.425841 <6>[ 0.700115] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10476 10:02:55.435960 <6>[ 0.708813] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10477 10:02:55.442484 <6>[ 0.718555] TCP: Hash tables configured (established 65536 bind 65536)
10478 10:02:55.448791 <6>[ 0.725417] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10479 10:02:55.458496 <6>[ 0.732614] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10480 10:02:55.465292 <6>[ 0.740319] NET: Registered PF_UNIX/PF_LOCAL protocol family
10481 10:02:55.471661 <6>[ 0.746487] RPC: Registered named UNIX socket transport module.
10482 10:02:55.475021 <6>[ 0.752640] RPC: Registered udp transport module.
10483 10:02:55.481176 <6>[ 0.757574] RPC: Registered tcp transport module.
10484 10:02:55.488531 <6>[ 0.762506] RPC: Registered tcp NFSv4.1 backchannel transport module.
10485 10:02:55.491405 <6>[ 0.769175] PCI: CLS 0 bytes, default 64
10486 10:02:55.494960 <6>[ 0.773561] Unpacking initramfs...
10487 10:02:55.505322 <6>[ 0.777665] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10488 10:02:55.512132 <6>[ 0.786308] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10489 10:02:55.518687 <6>[ 0.795138] kvm [1]: IPA Size Limit: 40 bits
10490 10:02:55.521712 <6>[ 0.799661] kvm [1]: GICv3: no GICV resource entry
10491 10:02:55.528115 <6>[ 0.804683] kvm [1]: disabling GICv2 emulation
10492 10:02:55.535568 <6>[ 0.809369] kvm [1]: GIC system register CPU interface enabled
10493 10:02:55.538359 <6>[ 0.815530] kvm [1]: vgic interrupt IRQ18
10494 10:02:55.542098 <6>[ 0.819884] kvm [1]: VHE mode initialized successfully
10495 10:02:55.549535 <5>[ 0.826282] Initialise system trusted keyrings
10496 10:02:55.555854 <6>[ 0.831066] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10497 10:02:55.564022 <6>[ 0.841096] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10498 10:02:55.570558 <5>[ 0.847463] NFS: Registering the id_resolver key type
10499 10:02:55.574033 <5>[ 0.852764] Key type id_resolver registered
10500 10:02:55.581028 <5>[ 0.857178] Key type id_legacy registered
10501 10:02:55.587188 <6>[ 0.861473] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10502 10:02:55.594227 <6>[ 0.868398] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10503 10:02:55.600230 <6>[ 0.876117] 9p: Installing v9fs 9p2000 file system support
10504 10:02:55.637191 <5>[ 0.914276] Key type asymmetric registered
10505 10:02:55.640645 <5>[ 0.918606] Asymmetric key parser 'x509' registered
10506 10:02:55.650201 <6>[ 0.923746] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10507 10:02:55.655050 <6>[ 0.931358] io scheduler mq-deadline registered
10508 10:02:55.656712 <6>[ 0.936117] io scheduler kyber registered
10509 10:02:55.675674 <6>[ 0.952891] EINJ: ACPI disabled.
10510 10:02:55.707618 <4>[ 0.978188] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10511 10:02:55.717377 <4>[ 0.988821] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10512 10:02:55.732713 <6>[ 1.009837] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10513 10:02:55.740922 <6>[ 1.018042] printk: console [ttyS0] disabled
10514 10:02:55.768590 <6>[ 1.042716] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10515 10:02:55.775363 <6>[ 1.052196] printk: console [ttyS0] enabled
10516 10:02:55.779022 <6>[ 1.052196] printk: console [ttyS0] enabled
10517 10:02:55.785043 <6>[ 1.061093] printk: bootconsole [mtk8250] disabled
10518 10:02:55.788366 <6>[ 1.061093] printk: bootconsole [mtk8250] disabled
10519 10:02:55.795176 <6>[ 1.072310] SuperH (H)SCI(F) driver initialized
10520 10:02:55.798545 <6>[ 1.077575] msm_serial: driver initialized
10521 10:02:55.812811 <6>[ 1.086532] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10522 10:02:55.823219 <6>[ 1.095078] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10523 10:02:55.829937 <6>[ 1.103619] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10524 10:02:55.839629 <6>[ 1.112245] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10525 10:02:55.846152 <6>[ 1.120957] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10526 10:02:55.855930 <6>[ 1.129672] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10527 10:02:55.865460 <6>[ 1.138212] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10528 10:02:55.872231 <6>[ 1.147019] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10529 10:02:55.881990 <6>[ 1.155562] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10530 10:02:55.893383 <6>[ 1.171150] loop: module loaded
10531 10:02:55.900218 <6>[ 1.177497] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10532 10:02:55.923509 <4>[ 1.200882] mtk-pmic-keys: Failed to locate of_node [id: -1]
10533 10:02:55.930217 <6>[ 1.207730] megasas: 07.719.03.00-rc1
10534 10:02:55.939466 <6>[ 1.217265] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10535 10:02:55.950519 <6>[ 1.228309] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10536 10:02:55.967516 <6>[ 1.244856] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10537 10:02:56.029109 <6>[ 1.299099] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10538 10:02:56.270219 <6>[ 1.547471] Freeing initrd memory: 17228K
10539 10:02:56.280330 <6>[ 1.557630] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10540 10:02:56.291697 <6>[ 1.568384] tun: Universal TUN/TAP device driver, 1.6
10541 10:02:56.294424 <6>[ 1.574435] thunder_xcv, ver 1.0
10542 10:02:56.297829 <6>[ 1.577939] thunder_bgx, ver 1.0
10543 10:02:56.300789 <6>[ 1.581434] nicpf, ver 1.0
10544 10:02:56.311496 <6>[ 1.585444] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10545 10:02:56.315072 <6>[ 1.592920] hns3: Copyright (c) 2017 Huawei Corporation.
10546 10:02:56.321463 <6>[ 1.598507] hclge is initializing
10547 10:02:56.325081 <6>[ 1.602082] e1000: Intel(R) PRO/1000 Network Driver
10548 10:02:56.331301 <6>[ 1.607211] e1000: Copyright (c) 1999-2006 Intel Corporation.
10549 10:02:56.334527 <6>[ 1.613226] e1000e: Intel(R) PRO/1000 Network Driver
10550 10:02:56.341725 <6>[ 1.618441] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10551 10:02:56.348027 <6>[ 1.624626] igb: Intel(R) Gigabit Ethernet Network Driver
10552 10:02:56.354868 <6>[ 1.630276] igb: Copyright (c) 2007-2014 Intel Corporation.
10553 10:02:56.361614 <6>[ 1.636111] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10554 10:02:56.368358 <6>[ 1.642629] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10555 10:02:56.371578 <6>[ 1.649096] sky2: driver version 1.30
10556 10:02:56.378293 <6>[ 1.654075] VFIO - User Level meta-driver version: 0.3
10557 10:02:56.385285 <6>[ 1.662281] usbcore: registered new interface driver usb-storage
10558 10:02:56.391612 <6>[ 1.668727] usbcore: registered new device driver onboard-usb-hub
10559 10:02:56.400813 <6>[ 1.677848] mt6397-rtc mt6359-rtc: registered as rtc0
10560 10:02:56.410524 <6>[ 1.683323] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-10T10:02:55 UTC (1686391375)
10561 10:02:56.413688 <6>[ 1.692924] i2c_dev: i2c /dev entries driver
10562 10:02:56.430288 <6>[ 1.704510] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10563 10:02:56.437345 <6>[ 1.714715] sdhci: Secure Digital Host Controller Interface driver
10564 10:02:56.444193 <6>[ 1.721154] sdhci: Copyright(c) Pierre Ossman
10565 10:02:56.451141 <6>[ 1.726567] Synopsys Designware Multimedia Card Interface Driver
10566 10:02:56.454179 <6>[ 1.733252] mmc0: CQHCI version 5.10
10567 10:02:56.461074 <6>[ 1.733722] sdhci-pltfm: SDHCI platform and OF driver helper
10568 10:02:56.468038 <6>[ 1.745465] ledtrig-cpu: registered to indicate activity on CPUs
10569 10:02:56.478670 <6>[ 1.752818] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10570 10:02:56.481707 <6>[ 1.760231] usbcore: registered new interface driver usbhid
10571 10:02:56.488456 <6>[ 1.766072] usbhid: USB HID core driver
10572 10:02:56.495025 <6>[ 1.770326] spi_master spi0: will run message pump with realtime priority
10573 10:02:56.541171 <6>[ 1.811929] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10574 10:02:56.560377 <6>[ 1.828165] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10575 10:02:56.563621 <6>[ 1.841730] mmc0: Command Queue Engine enabled
10576 10:02:56.570398 <6>[ 1.846523] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10577 10:02:56.577100 <6>[ 1.853661] cros-ec-spi spi0.0: Chrome EC device registered
10578 10:02:56.580580 <6>[ 1.853988] mmcblk0: mmc0:0001 DA4128 116 GiB
10579 10:02:56.592728 <6>[ 1.869994] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10580 10:02:56.600146 <6>[ 1.877480] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10581 10:02:56.606797 <6>[ 1.883458] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10582 10:02:56.613789 <6>[ 1.889614] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10583 10:02:56.623494 <6>[ 1.897515] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10584 10:02:56.631652 <6>[ 1.909004] NET: Registered PF_PACKET protocol family
10585 10:02:56.634851 <6>[ 1.914452] 9pnet: Installing 9P2000 support
10586 10:02:56.641713 <5>[ 1.919050] Key type dns_resolver registered
10587 10:02:56.644614 <6>[ 1.924246] registered taskstats version 1
10588 10:02:56.651574 <5>[ 1.928651] Loading compiled-in X.509 certificates
10589 10:02:56.686061 <4>[ 1.956599] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10590 10:02:56.695837 <4>[ 1.967307] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10591 10:02:56.706194 <3>[ 1.979984] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10592 10:02:56.718360 <6>[ 1.995482] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10593 10:02:56.725440 <6>[ 2.002233] xhci-mtk 11200000.usb: xHCI Host Controller
10594 10:02:56.731948 <6>[ 2.007732] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10595 10:02:56.742464 <6>[ 2.015585] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10596 10:02:56.748695 <6>[ 2.025038] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10597 10:02:56.754724 <6>[ 2.031256] xhci-mtk 11200000.usb: xHCI Host Controller
10598 10:02:56.762032 <6>[ 2.036753] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10599 10:02:56.768004 <6>[ 2.044421] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10600 10:02:56.775495 <6>[ 2.052333] hub 1-0:1.0: USB hub found
10601 10:02:56.778711 <6>[ 2.056364] hub 1-0:1.0: 1 port detected
10602 10:02:56.788497 <6>[ 2.060721] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10603 10:02:56.792259 <6>[ 2.069524] hub 2-0:1.0: USB hub found
10604 10:02:56.794878 <6>[ 2.073557] hub 2-0:1.0: 1 port detected
10605 10:02:56.803561 <6>[ 2.080777] mtk-msdc 11f70000.mmc: Got CD GPIO
10606 10:02:56.821224 <6>[ 2.094635] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10607 10:02:56.827838 <6>[ 2.102661] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10608 10:02:56.837412 <4>[ 2.110634] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10609 10:02:56.847600 <6>[ 2.120289] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10610 10:02:56.853639 <6>[ 2.128370] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10611 10:02:56.860522 <6>[ 2.136394] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10612 10:02:56.870560 <6>[ 2.144309] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10613 10:02:56.877182 <6>[ 2.152131] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10614 10:02:56.887239 <6>[ 2.159957] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10615 10:02:56.896718 <6>[ 2.170609] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10616 10:02:56.903858 <6>[ 2.178979] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10617 10:02:56.913663 <6>[ 2.187332] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10618 10:02:56.923552 <6>[ 2.195676] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10619 10:02:56.930161 <6>[ 2.204019] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10620 10:02:56.939952 <6>[ 2.212362] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10621 10:02:56.947280 <6>[ 2.220705] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10622 10:02:56.956609 <6>[ 2.229048] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10623 10:02:56.963832 <6>[ 2.237393] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10624 10:02:56.972695 <6>[ 2.245736] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10625 10:02:56.979974 <6>[ 2.254086] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10626 10:02:56.989590 <6>[ 2.262429] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10627 10:02:56.995455 <6>[ 2.270773] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10628 10:02:57.005448 <6>[ 2.279117] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10629 10:02:57.012111 <6>[ 2.287461] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10630 10:02:57.019019 <6>[ 2.296396] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10631 10:02:57.026610 <6>[ 2.303911] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10632 10:02:57.033482 <6>[ 2.311025] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10633 10:02:57.044576 <6>[ 2.318153] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10634 10:02:57.050578 <6>[ 2.325453] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10635 10:02:57.060561 <6>[ 2.332365] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10636 10:02:57.067063 <6>[ 2.341505] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10637 10:02:57.076813 <6>[ 2.350633] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10638 10:02:57.086612 <6>[ 2.359935] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10639 10:02:57.096457 <6>[ 2.369411] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10640 10:02:57.107039 <6>[ 2.378885] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10641 10:02:57.113762 <6>[ 2.388012] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10642 10:02:57.123309 <6>[ 2.397489] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10643 10:02:57.133323 <6>[ 2.406615] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10644 10:02:57.143009 <6>[ 2.415928] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10645 10:02:57.153319 <6>[ 2.426096] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10646 10:02:57.163500 <6>[ 2.437613] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10647 10:02:57.170234 <6>[ 2.447546] Trying to probe devices needed for running init ...
10648 10:02:57.206815 <6>[ 2.481206] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10649 10:02:57.361292 <6>[ 2.638476] hub 1-1:1.0: USB hub found
10650 10:02:57.364705 <6>[ 2.642912] hub 1-1:1.0: 4 ports detected
10651 10:02:57.487349 <6>[ 2.761378] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10652 10:02:57.511937 <6>[ 2.789713] hub 2-1:1.0: USB hub found
10653 10:02:57.515493 <6>[ 2.794110] hub 2-1:1.0: 3 ports detected
10654 10:02:57.686892 <6>[ 2.961201] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10655 10:02:57.820267 <6>[ 3.097351] hub 1-1.4:1.0: USB hub found
10656 10:02:57.823320 <6>[ 3.102037] hub 1-1.4:1.0: 2 ports detected
10657 10:02:57.898947 <6>[ 3.173299] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10658 10:02:58.119072 <6>[ 3.393199] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10659 10:02:58.311341 <6>[ 3.585202] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10660 10:03:09.455537 <6>[ 14.737763] ALSA device list:
10661 10:03:09.462253 <6>[ 14.741021] No soundcards found.
10662 10:03:09.474343 <6>[ 14.753408] Freeing unused kernel memory: 8384K
10663 10:03:09.477703 <6>[ 14.758325] Run /init as init process
10664 10:03:09.488550 Loading, please wait...
10665 10:03:09.507641 Starting version 247.3-7+deb11u2
10666 10:03:09.831461 <6>[ 15.106665] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10667 10:03:09.846946 <6>[ 15.125557] remoteproc remoteproc0: scp is available
10668 10:03:09.857030 <4>[ 15.131313] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10669 10:03:09.863410 <6>[ 15.141170] remoteproc remoteproc0: powering up scp
10670 10:03:09.872970 <4>[ 15.146402] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10671 10:03:09.879893 <3>[ 15.147969] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10672 10:03:09.886656 <3>[ 15.156231] remoteproc remoteproc0: request_firmware failed: -2
10673 10:03:09.893045 <6>[ 15.163195] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10674 10:03:09.902677 <6>[ 15.164539] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10675 10:03:09.909468 <3>[ 15.169998] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 10:03:09.919805 <3>[ 15.170010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 10:03:09.926376 <3>[ 15.170071] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 10:03:09.936612 <3>[ 15.170080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 10:03:09.942784 <3>[ 15.170087] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 10:03:09.949718 <3>[ 15.170097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 10:03:09.960332 <3>[ 15.170104] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 10:03:09.966900 <3>[ 15.170141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 10:03:09.976610 <3>[ 15.170179] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10684 10:03:09.982715 <3>[ 15.170186] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10685 10:03:09.992983 <3>[ 15.170193] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 10:03:09.999272 <3>[ 15.170234] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 10:03:10.005573 <3>[ 15.170242] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10688 10:03:10.016173 <3>[ 15.170248] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 10:03:10.022784 <3>[ 15.170256] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 10:03:10.032809 <3>[ 15.170263] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 10:03:10.038945 <3>[ 15.170293] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 10:03:10.046041 <6>[ 15.174838] usbcore: registered new interface driver r8152
10693 10:03:10.052427 <6>[ 15.176168] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10694 10:03:10.062699 <6>[ 15.176209] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10695 10:03:10.068963 <4>[ 15.179134] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10696 10:03:10.079124 <4>[ 15.208526] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10697 10:03:10.082426 <4>[ 15.208526] Fallback method does not support PEC.
10698 10:03:10.089060 <6>[ 15.210592] mc: Linux media interface: v0.10
10699 10:03:10.096068 <4>[ 15.225564] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10700 10:03:10.105660 <3>[ 15.238454] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10701 10:03:10.112497 <6>[ 15.277187] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10702 10:03:10.122352 <6>[ 15.285423] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10703 10:03:10.128864 <6>[ 15.294425] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10704 10:03:10.138699 <6>[ 15.299749] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10705 10:03:10.142205 <6>[ 15.307293] pci_bus 0000:00: root bus resource [bus 00-ff]
10706 10:03:10.151987 <4>[ 15.318845] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10707 10:03:10.158264 <6>[ 15.323441] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10708 10:03:10.168563 <6>[ 15.323447] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10709 10:03:10.178491 <4>[ 15.329194] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10710 10:03:10.184758 <3>[ 15.333416] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10711 10:03:10.191500 <6>[ 15.337897] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10712 10:03:10.197734 <3>[ 15.341326] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10713 10:03:10.204658 <6>[ 15.369192] r8152 2-1.3:1.0 eth0: v1.12.13
10714 10:03:10.211248 <6>[ 15.372018] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10715 10:03:10.217458 <3>[ 15.441434] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10716 10:03:10.221079 <6>[ 15.443122] pci 0000:00:00.0: supports D1 D2
10717 10:03:10.227814 <6>[ 15.505261] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10718 10:03:10.238704 <6>[ 15.513995] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10719 10:03:10.245271 <6>[ 15.522377] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10720 10:03:10.252387 <6>[ 15.528664] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10721 10:03:10.258185 <6>[ 15.536169] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10722 10:03:10.268159 <6>[ 15.543657] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10723 10:03:10.271556 <6>[ 15.551238] pci 0000:01:00.0: supports D1 D2
10724 10:03:10.278314 <3>[ 15.553364] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10725 10:03:10.284938 <6>[ 15.555763] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10726 10:03:10.291514 <3>[ 15.562624] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10727 10:03:10.301012 <6>[ 15.575961] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10728 10:03:10.308260 <6>[ 15.585145] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10729 10:03:10.317268 <6>[ 15.592310] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10730 10:03:10.324515 <6>[ 15.600448] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10731 10:03:10.334173 <6>[ 15.608498] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10732 10:03:10.337497 <6>[ 15.609957] videodev: Linux video capture interface: v2.00
10733 10:03:10.341092 <6>[ 15.609979] Bluetooth: Core ver 2.22
10734 10:03:10.347405 <6>[ 15.610059] NET: Registered PF_BLUETOOTH protocol family
10735 10:03:10.354471 <6>[ 15.610062] Bluetooth: HCI device and connection manager initialized
10736 10:03:10.360705 <6>[ 15.610076] usbcore: registered new interface driver cdc_ether
10737 10:03:10.367338 <6>[ 15.610079] Bluetooth: HCI socket layer initialized
10738 10:03:10.370435 <6>[ 15.610087] Bluetooth: L2CAP socket layer initialized
10739 10:03:10.376683 <6>[ 15.610098] Bluetooth: SCO socket layer initialized
10740 10:03:10.384156 <6>[ 15.616511] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10741 10:03:10.390306 <6>[ 15.616864] usbcore: registered new interface driver r8153_ecm
10742 10:03:10.397074 <6>[ 15.625908] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10743 10:03:10.403304 <6>[ 15.626103] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10744 10:03:10.409905 <6>[ 15.656019] usbcore: registered new interface driver btusb
10745 10:03:10.419972 <4>[ 15.656445] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10746 10:03:10.426190 <3>[ 15.656454] Bluetooth: hci0: Failed to load firmware file (-2)
10747 10:03:10.433424 <3>[ 15.656458] Bluetooth: hci0: Failed to set up firmware (-2)
10748 10:03:10.442898 <4>[ 15.656461] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10749 10:03:10.449684 <6>[ 15.659936] pci 0000:00:00.0: PCI bridge to [bus 01]
10750 10:03:10.456577 <6>[ 15.680897] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10751 10:03:10.463187 <6>[ 15.688108] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10752 10:03:10.469263 <6>[ 15.688314] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10753 10:03:10.482457 <6>[ 15.695595] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10754 10:03:10.489174 <6>[ 15.705301] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10755 10:03:10.495731 <6>[ 15.705515] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10756 10:03:10.498944 <6>[ 15.706092] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10757 10:03:10.505783 <6>[ 15.710785] usbcore: registered new interface driver uvcvideo
10758 10:03:10.532124 <5>[ 15.807444] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10759 10:03:10.551558 <5>[ 15.826703] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10760 10:03:10.558220 <4>[ 15.833597] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10761 10:03:10.564553 <6>[ 15.842487] cfg80211: failed to load regulatory.db
10762 10:03:10.608754 <6>[ 15.883857] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10763 10:03:10.614915 <6>[ 15.891439] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10764 10:03:10.639512 <6>[ 15.918213] mt7921e 0000:01:00.0: ASIC revision: 79610010
10765 10:03:10.745695 <4>[ 16.017625] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10766 10:03:10.762035 Begin: Loading essential drivers ... done.
10767 10:03:10.765219 Begin: Running /scripts/init-premount ... done.
10768 10:03:10.772283 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10769 10:03:10.781701 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10770 10:03:10.784694 Device /sys/class/net/enx00e04c722dd6 found
10771 10:03:10.785213 done.
10772 10:03:10.853682 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10773 10:03:10.871549 <4>[ 16.143696] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 10:03:11.000885 <4>[ 16.273006] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 10:03:11.141513 <4>[ 16.412998] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 10:03:11.280484 <4>[ 16.553000] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 10:03:11.420841 <4>[ 16.693001] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 10:03:11.560319 <4>[ 16.832999] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 10:03:11.700664 <4>[ 16.973000] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 10:03:11.786198 <6>[ 17.065036] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10781 10:03:11.830137 <4>[ 17.102478] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 10:03:11.904461 IP-Config: no response after 2 secs - giving up
10783 10:03:11.947025 <4>[ 17.218779] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10784 10:03:11.953140 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10785 10:03:11.959874 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10786 10:03:11.966303 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10787 10:03:11.972894 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10788 10:03:11.979354 host : mt8192-asurada-spherion-r0-cbg-1
10789 10:03:11.986625 domain : lava-rack
10790 10:03:11.988903 rootserver: 192.168.201.1 rootpath:
10791 10:03:11.989377 filename :
10792 10:03:12.052105 done.
10793 10:03:12.055265 <3>[ 17.335339] mt7921e 0000:01:00.0: hardware init failed
10794 10:03:12.061981 Begin: Running /scripts/nfs-bottom ... done.
10795 10:03:12.080088 Begin: Running /scripts/init-bottom ... done.
10796 10:03:13.199341 <6>[ 18.478599] NET: Registered PF_INET6 protocol family
10797 10:03:13.205533 <6>[ 18.485180] Segment Routing with IPv6
10798 10:03:13.209595 <6>[ 18.489171] In-situ OAM (IOAM) with IPv6
10799 10:03:13.317885 <30>[ 18.577637] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10800 10:03:13.321218 <30>[ 18.601477] systemd[1]: Detected architecture arm64.
10801 10:03:13.339756
10802 10:03:13.343021 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10803 10:03:13.343134
10804 10:03:13.359717 <30>[ 18.639355] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10805 10:03:13.841014 <30>[ 19.117646] systemd[1]: Queued start job for default target Graphical Interface.
10806 10:03:13.882779 <30>[ 19.162266] systemd[1]: Created slice system-getty.slice.
10807 10:03:13.888724 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10808 10:03:13.905951 <30>[ 19.185917] systemd[1]: Created slice system-modprobe.slice.
10809 10:03:13.913353 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10810 10:03:13.930361 <30>[ 19.210299] systemd[1]: Created slice system-serial\x2dgetty.slice.
10811 10:03:13.940640 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10812 10:03:13.954688 <30>[ 19.233729] systemd[1]: Created slice User and Session Slice.
10813 10:03:13.960346 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10814 10:03:13.981292 <30>[ 19.257776] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10815 10:03:13.991495 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10816 10:03:14.009610 <30>[ 19.285353] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10817 10:03:14.015248 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10818 10:03:14.036481 <30>[ 19.309294] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10819 10:03:14.042775 <30>[ 19.321326] systemd[1]: Reached target Local Encrypted Volumes.
10820 10:03:14.049506 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10821 10:03:14.065872 <30>[ 19.345574] systemd[1]: Reached target Paths.
10822 10:03:14.069229 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10823 10:03:14.085582 <30>[ 19.365250] systemd[1]: Reached target Remote File Systems.
10824 10:03:14.091907 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10825 10:03:14.105521 <30>[ 19.385185] systemd[1]: Reached target Slices.
10826 10:03:14.109277 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10827 10:03:14.125439 <30>[ 19.405241] systemd[1]: Reached target Swap.
10828 10:03:14.128946 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10829 10:03:14.149240 <30>[ 19.425488] systemd[1]: Listening on initctl Compatibility Named Pipe.
10830 10:03:14.155890 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10831 10:03:14.161920 <30>[ 19.440747] systemd[1]: Listening on Journal Audit Socket.
10832 10:03:14.168584 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10833 10:03:14.182266 <30>[ 19.462106] systemd[1]: Listening on Journal Socket (/dev/log).
10834 10:03:14.188701 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10835 10:03:14.206362 <30>[ 19.486033] systemd[1]: Listening on Journal Socket.
10836 10:03:14.212909 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10837 10:03:14.229808 <30>[ 19.506313] systemd[1]: Listening on Network Service Netlink Socket.
10838 10:03:14.237045 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10839 10:03:14.255167 <30>[ 19.534631] systemd[1]: Listening on udev Control Socket.
10840 10:03:14.261648 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10841 10:03:14.277515 <30>[ 19.557282] systemd[1]: Listening on udev Kernel Socket.
10842 10:03:14.284150 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10843 10:03:14.309327 <30>[ 19.589213] systemd[1]: Mounting Huge Pages File System...
10844 10:03:14.315867 Mounting [0;1;39mHuge Pages File System[0m...
10845 10:03:14.331917 <30>[ 19.611783] systemd[1]: Mounting POSIX Message Queue File System...
10846 10:03:14.338893 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10847 10:03:14.356325 <30>[ 19.636240] systemd[1]: Mounting Kernel Debug File System...
10848 10:03:14.362906 Mounting [0;1;39mKernel Debug File System[0m...
10849 10:03:14.380906 <30>[ 19.657426] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10850 10:03:14.402184 <30>[ 19.678433] systemd[1]: Starting Create list of static device nodes for the current kernel...
10851 10:03:14.408541 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10852 10:03:14.427757 <30>[ 19.707789] systemd[1]: Starting Load Kernel Module configfs...
10853 10:03:14.434382 Starting [0;1;39mLoad Kernel Module configfs[0m...
10854 10:03:14.451675 <30>[ 19.731494] systemd[1]: Starting Load Kernel Module drm...
10855 10:03:14.458396 Starting [0;1;39mLoad Kernel Module drm[0m...
10856 10:03:14.475905 <30>[ 19.755622] systemd[1]: Starting Load Kernel Module fuse...
10857 10:03:14.482270 Starting [0;1;39mLoad Kernel Module fuse[0m...
10858 10:03:14.511553 <6>[ 19.791283] fuse: init (API version 7.37)
10859 10:03:14.521465 <30>[ 19.796200] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10860 10:03:14.530193 <30>[ 19.810064] systemd[1]: Starting Journal Service...
10861 10:03:14.536692 Starting [0;1;39mJournal Service[0m...
10862 10:03:14.555397 <30>[ 19.835450] systemd[1]: Starting Load Kernel Modules...
10863 10:03:14.561956 Starting [0;1;39mLoad Kernel Modules[0m...
10864 10:03:14.583530 <30>[ 19.859924] systemd[1]: Starting Remount Root and Kernel File Systems...
10865 10:03:14.589690 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10866 10:03:14.604902 <30>[ 19.884395] systemd[1]: Starting Coldplug All udev Devices...
10867 10:03:14.610944 Starting [0;1;39mColdplug All udev Devices[0m...
10868 10:03:14.628573 <30>[ 19.908290] systemd[1]: Mounted Huge Pages File System.
10869 10:03:14.635184 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10870 10:03:14.653464 <30>[ 19.933541] systemd[1]: Mounted POSIX Message Queue File System.
10871 10:03:14.660340 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10872 10:03:14.679887 <3>[ 19.955667] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10873 10:03:14.685895 <30>[ 19.964997] systemd[1]: Mounted Kernel Debug File System.
10874 10:03:14.692615 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10875 10:03:14.709950 <30>[ 19.986063] systemd[1]: Finished Create list of static device nodes for the current kernel.
10876 10:03:14.720131 <3>[ 19.990561] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 10:03:14.726488 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10878 10:03:14.743479 <30>[ 20.022540] systemd[1]: modprobe@configfs.service: Succeeded.
10879 10:03:14.750518 <30>[ 20.029658] systemd[1]: Finished Load Kernel Module configfs.
10880 10:03:14.756886 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10881 10:03:14.768676 <3>[ 20.044575] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 10:03:14.775168 <30>[ 20.054560] systemd[1]: modprobe@drm.service: Succeeded.
10883 10:03:14.781619 <30>[ 20.060883] systemd[1]: Finished Load Kernel Module drm.
10884 10:03:14.788534 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10885 10:03:14.800871 <3>[ 20.076672] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 10:03:14.807356 <30>[ 20.086736] systemd[1]: modprobe@fuse.service: Succeeded.
10887 10:03:14.814076 <30>[ 20.093096] systemd[1]: Finished Load Kernel Module fuse.
10888 10:03:14.820422 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10889 10:03:14.832319 <3>[ 20.108376] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 10:03:14.839161 <30>[ 20.118577] systemd[1]: Finished Load Kernel Modules.
10891 10:03:14.845547 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10892 10:03:14.863407 <30>[ 20.138689] systemd[1]: Finished Remount Root and Kernel File Systems.
10893 10:03:14.869210 <3>[ 20.140413] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 10:03:14.879180 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10895 10:03:14.903785 <3>[ 20.179769] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 10:03:14.935678 <3>[ 20.211925] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 10:03:14.946177 <30>[ 20.225745] systemd[1]: Mounting FUSE Control File System...
10898 10:03:14.952647 Mounting [0;1;39mFUSE Control File System[0m...
10899 10:03:14.968721 <3>[ 20.244512] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 10:03:14.980432 <30>[ 20.256660] systemd[1]: Mounting Kernel Configuration File System...
10901 10:03:14.983578 Mounting [0;1;39mKernel Configuration File System[0m...
10902 10:03:15.002470 <3>[ 20.278582] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 10:03:15.017349 <30>[ 20.293091] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10904 10:03:15.027052 <30>[ 20.302078] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10905 10:03:15.037088 <3>[ 20.309606] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 10:03:15.066614 <3>[ 20.342819] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 10:03:15.074513 <30>[ 20.354081] systemd[1]: Starting Load/Save Random Seed...
10908 10:03:15.081064 Starting [0;1;39mLoad/Save Random Seed[0m...
10909 10:03:15.096436 <30>[ 20.376128] systemd[1]: Starting Apply Kernel Variables...
10910 10:03:15.103231 Starting [0;1;39mApply Kernel Variables[0m...
10911 10:03:15.109825 <3>[ 20.387484] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 10:03:15.119596 <3>[ 20.390019] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10913 10:03:15.127411 <30>[ 20.407379] systemd[1]: Starting Create System Users...
10914 10:03:15.133950 Starting [0;1;39mCreate System Users[0m...
10915 10:03:15.149130 <3>[ 20.425848] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 10:03:15.157254 <30>[ 20.436652] systemd[1]: Mounted FUSE Control File System.
10917 10:03:15.163814 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10918 10:03:15.176198 <3>[ 20.452278] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 10:03:15.193124 <4>[ 20.461098] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10920 10:03:15.200204 <30>[ 20.461530] systemd[1]: Mounted Kernel Configuration File System.
10921 10:03:15.207537 <3>[ 20.469838] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 10:03:15.214170 <3>[ 20.476737] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10923 10:03:15.224555 <3>[ 20.491756] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 10:03:15.230925 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10925 10:03:15.250012 <29>[ 20.526068] systemd[1]: systemd-udev-trigger.service: Main process exited, code=exited, status=1/FAILURE
10926 10:03:15.260505 <28>[ 20.536365] systemd[1]: systemd-udev-trigger.service: Failed with result 'exit-code'.
10927 10:03:15.267040 <27>[ 20.545492] systemd[1]: Failed to start Coldplug All udev Devices.
10928 10:03:15.273708 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10929 10:03:15.289549 See 'systemctl status systemd-udev-trigger.service' for details.
10930 10:03:15.310561 <30>[ 20.590091] systemd[1]: Finished Load/Save Random Seed.
10931 10:03:15.317185 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10932 10:03:15.334553 <30>[ 20.614200] systemd[1]: Finished Apply Kernel Variables.
10933 10:03:15.340747 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10934 10:03:15.357796 <30>[ 20.637659] systemd[1]: Started Journal Service.
10935 10:03:15.364269 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10936 10:03:15.379210 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10937 10:03:15.430254 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10938 10:03:15.447912 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10939 10:03:15.482616 <46>[ 20.759273] systemd-journald[300]: Received client request to flush runtime journal.
10940 10:03:15.510442 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10941 10:03:15.522281 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10942 10:03:15.537683 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10943 10:03:15.581299 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10944 10:03:16.848346 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10945 10:03:16.902000 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10946 10:03:16.922279 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10947 10:03:16.946398 Starting [0;1;39mNetwork Service[0m...
10948 10:03:17.236413 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10949 10:03:17.253756 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10950 10:03:17.313585 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10951 10:03:17.470257 <6>[ 22.750572] remoteproc remoteproc0: powering up scp
10952 10:03:17.499472 <4>[ 22.776162] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10953 10:03:17.505785 <3>[ 22.786076] remoteproc remoteproc0: request_firmware failed: -2
10954 10:03:17.515963 <3>[ 22.792258] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10955 10:03:17.633351 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10956 10:03:17.652945 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10957 10:03:17.666066 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10958 10:03:17.685697 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10959 10:03:17.710646 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10960 10:03:17.773567 Starting [0;1;39mNetwork Name Resolution[0m...
10961 10:03:17.792364 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10962 10:03:17.818088 Starting [0;1;39mNetwork Time Synchronization[0m...
10963 10:03:17.835516 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10964 10:03:17.854464 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10965 10:03:17.881399 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10966 10:03:18.243836 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10967 10:03:18.265196 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10968 10:03:18.284605 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10969 10:03:18.297139 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10970 10:03:18.312985 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10971 10:03:18.343030 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10972 10:03:18.385535 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10973 10:03:18.849355 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10974 10:03:19.116773 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10975 10:03:19.129434 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10976 10:03:19.448643 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10977 10:03:19.460839 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10978 10:03:19.476928 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10979 10:03:19.513319 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10980 10:03:19.542854 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10981 10:03:19.609585 Starting [0;1;39mUser Login Management[0m...
10982 10:03:19.625842 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10983 10:03:19.646106 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10984 10:03:19.667832 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10985 10:03:19.718984 Starting [0;1;39mPermit User Sessions[0m...
10986 10:03:19.833186 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10987 10:03:19.854366 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10988 10:03:19.902375 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10989 10:03:19.920481 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10990 10:03:19.937160 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10991 10:03:19.954732 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10992 10:03:19.970170 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10993 10:03:19.985101 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10994 10:03:20.025200 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10995 10:03:20.088670 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10996 10:03:20.146919
10997 10:03:20.147062
10998 10:03:20.149935 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10999 10:03:20.150023
11000 10:03:20.153464 debian-bullseye-arm64 login: root (automatic login)
11001 10:03:20.153549
11002 10:03:20.153614
11003 10:03:20.429708 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023 aarch64
11004 10:03:20.429863
11005 10:03:20.436580 The programs included with the Debian GNU/Linux system are free software;
11006 10:03:20.443069 the exact distribution terms for each program are described in the
11007 10:03:20.445977 individual files in /usr/share/doc/*/copyright.
11008 10:03:20.446063
11009 10:03:20.452889 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11010 10:03:20.456384 permitted by applicable law.
11011 10:03:21.248336 Matched prompt #10: / #
11013 10:03:21.248626 Setting prompt string to ['/ #']
11014 10:03:21.248723 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11016 10:03:21.248933 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11017 10:03:21.249026 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
11018 10:03:21.249098 Setting prompt string to ['/ #']
11019 10:03:21.249160 Forcing a shell prompt, looking for ['/ #']
11021 10:03:21.299387 / #
11022 10:03:21.299538 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11023 10:03:21.299652 Waiting using forced prompt support (timeout 00:02:30)
11024 10:03:21.304667
11025 10:03:21.304955 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11026 10:03:21.305054 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
11028 10:03:21.405435 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10670651/extract-nfsrootfs-69r0vlv_'
11029 10:03:21.410639 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10670651/extract-nfsrootfs-69r0vlv_'
11031 10:03:21.511198 / # export NFS_SERVER_IP='192.168.201.1'
11032 10:03:21.516387 export NFS_SERVER_IP='192.168.201.1'
11033 10:03:21.516680 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11034 10:03:21.516822 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11035 10:03:21.516918 end: 2 depthcharge-action (duration 00:01:25) [common]
11036 10:03:21.517013 start: 3 lava-test-retry (timeout 00:07:56) [common]
11037 10:03:21.517102 start: 3.1 lava-test-shell (timeout 00:07:56) [common]
11038 10:03:21.517182 Using namespace: common
11040 10:03:21.617533 / # #
11041 10:03:21.617734 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11042 10:03:21.622678 #
11043 10:03:21.623004 Using /lava-10670651
11045 10:03:21.723384 / # export SHELL=/bin/bash
11046 10:03:21.728525 export SHELL=/bin/bash
11048 10:03:21.829142 / # . /lava-10670651/environment
11049 10:03:21.834141 . /lava-10670651/environment
11051 10:03:21.938779 / # /lava-10670651/bin/lava-test-runner /lava-10670651/0
11052 10:03:21.938949 Test shell timeout: 10s (minimum of the action and connection timeout)
11053 10:03:21.943715 /lava-10670651/bin/lava-test-runner /lava-10670651/0
11054 10:03:22.155364 + export TESTRUN_ID=0_timesync-off
11055 10:03:22.158263 + TESTRUN_ID=0_timesync-off
11056 10:03:22.161502 + cd /lava-10670651/0/tests/0_timesync-off
11057 10:03:22.164743 ++ cat uuid
11058 10:03:22.164839 + UUID=10670651_1.6.2.3.1
11059 10:03:22.168627 + set +x
11060 10:03:22.171465 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10670651_1.6.2.3.1>
11061 10:03:22.171735 Received signal: <STARTRUN> 0_timesync-off 10670651_1.6.2.3.1
11062 10:03:22.171820 Starting test lava.0_timesync-off (10670651_1.6.2.3.1)
11063 10:03:22.171930 Skipping test definition patterns.
11064 10:03:22.174755 + systemctl stop systemd-timesyncd
11065 10:03:22.199590 + set +x
11066 10:03:22.202943 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10670651_1.6.2.3.1>
11067 10:03:22.203205 Received signal: <ENDRUN> 0_timesync-off 10670651_1.6.2.3.1
11068 10:03:22.203298 Ending use of test pattern.
11069 10:03:22.203374 Ending test lava.0_timesync-off (10670651_1.6.2.3.1), duration 0.03
11071 10:03:22.246332 + export TESTRUN_ID=1_kselftest-tpm2
11072 10:03:22.249717 + TESTRUN_ID=1_kselftest-tpm2
11073 10:03:22.256282 + cd /lava-10670651/0/tests/1_kselftest-tpm2
11074 10:03:22.256398 ++ cat uuid
11075 10:03:22.259683 + UUID=10670651_1.6.2.3.5
11076 10:03:22.259771 + set +x
11077 10:03:22.262642 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 10670651_1.6.2.3.5>
11078 10:03:22.262905 Received signal: <STARTRUN> 1_kselftest-tpm2 10670651_1.6.2.3.5
11079 10:03:22.262984 Starting test lava.1_kselftest-tpm2 (10670651_1.6.2.3.5)
11080 10:03:22.263091 Skipping test definition patterns.
11081 10:03:22.265803 + cd ./automated/linux/kselftest/
11082 10:03:22.292392 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11083 10:03:22.303597 INFO: install_deps skipped
11084 10:03:22.401462 --2023-06-10 10:03:20-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11085 10:03:22.418794 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11086 10:03:22.547037 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11087 10:03:22.676911 HTTP request sent, awaiting response... 200 OK
11088 10:03:22.679540 Length: 2883260 (2.7M) [application/octet-stream]
11089 10:03:22.682635 Saving to: 'kselftest.tar.xz'
11090 10:03:22.682721
11091 10:03:22.682806
11092 10:03:22.933805 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11093 10:03:23.192552 kselftest.tar.xz 1%[ ] 44.98K 176KB/s
11094 10:03:23.497657 kselftest.tar.xz 7%[> ] 217.50K 423KB/s
11095 10:03:23.707576 kselftest.tar.xz 28%[====> ] 815.64K 994KB/s
11096 10:03:23.862237 kselftest.tar.xz 72%[=============> ] 1.98M 1.92MB/s
11097 10:03:23.868237 kselftest.tar.xz 100%[===================>] 2.75M 2.32MB/s in 1.2s
11098 10:03:23.868359
11099 10:03:24.116986 2023-06-10 10:03:21 (2.32 MB/s) - 'kselftest.tar.xz' saved [2883260/2883260]
11100 10:03:24.117124
11101 10:03:28.734264 skiplist:
11102 10:03:28.737654 ========================================
11103 10:03:28.741067 ========================================
11104 10:03:28.774881 tpm2:test_smoke.sh
11105 10:03:28.777767 tpm2:test_space.sh
11106 10:03:28.790133 ============== Tests to run ===============
11107 10:03:28.790216 tpm2:test_smoke.sh
11108 10:03:28.793626 tpm2:test_space.sh
11109 10:03:28.796589 ===========End Tests to run ===============
11110 10:03:28.880812 <12>[ 34.162182] kselftest: Running tests in tpm2
11111 10:03:28.890907 TAP version 13
11112 10:03:28.902968 1..2
11113 10:03:28.931921 # selftests: tpm2: test_smoke.sh
11114 10:03:30.084827 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11115 10:03:30.087815 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11116 10:03:30.094773 # Exception ignored in: <function Client.__del__ at 0xffff88ee5d30>
11117 10:03:30.098107 # Traceback (most recent call last):
11118 10:03:30.108038 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11119 10:03:30.108265 # if self.tpm:
11120 10:03:30.114552 # AttributeError: 'Client' object has no attribute 'tpm'
11121 10:03:30.117873 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11122 10:03:30.124635 # Exception ignored in: <function Client.__del__ at 0xffff88ee5d30>
11123 10:03:30.128358 # Traceback (most recent call last):
11124 10:03:30.138109 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11125 10:03:30.141693 # if self.tpm:
11126 10:03:30.144447 # AttributeError: 'Client' object has no attribute 'tpm'
11127 10:03:30.151339 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11128 10:03:30.157730 # Exception ignored in: <function Client.__del__ at 0xffff88ee5d30>
11129 10:03:30.161155 # Traceback (most recent call last):
11130 10:03:30.171043 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11131 10:03:30.171397 # if self.tpm:
11132 10:03:30.177800 # AttributeError: 'Client' object has no attribute 'tpm'
11133 10:03:30.181130 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11134 10:03:30.187997 # Exception ignored in: <function Client.__del__ at 0xffff88ee5d30>
11135 10:03:30.191118 # Traceback (most recent call last):
11136 10:03:30.201287 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11137 10:03:30.204627 # if self.tpm:
11138 10:03:30.207598 # AttributeError: 'Client' object has no attribute 'tpm'
11139 10:03:30.214297 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11140 10:03:30.217413 # Exception ignored in: <function Client.__del__ at 0xffff88ee5d30>
11141 10:03:30.220614 # Traceback (most recent call last):
11142 10:03:30.231158 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11143 10:03:30.234475 # if self.tpm:
11144 10:03:30.237669 # AttributeError: 'Client' object has no attribute 'tpm'
11145 10:03:30.244355 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11146 10:03:30.251129 # Exception ignored in: <function Client.__del__ at 0xffff88ee5d30>
11147 10:03:30.254114 # Traceback (most recent call last):
11148 10:03:30.263976 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11149 10:03:30.264494 # if self.tpm:
11150 10:03:30.271087 # AttributeError: 'Client' object has no attribute 'tpm'
11151 10:03:30.274273 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11152 10:03:30.280115 # Exception ignored in: <function Client.__del__ at 0xffff88ee5d30>
11153 10:03:30.283962 # Traceback (most recent call last):
11154 10:03:30.293641 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11155 10:03:30.297167 # if self.tpm:
11156 10:03:30.300032 # AttributeError: 'Client' object has no attribute 'tpm'
11157 10:03:30.307121 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11158 10:03:30.313972 # Exception ignored in: <function Client.__del__ at 0xffff88ee5d30>
11159 10:03:30.316762 # Traceback (most recent call last):
11160 10:03:30.326844 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11161 10:03:30.327031 # if self.tpm:
11162 10:03:30.333218 # AttributeError: 'Client' object has no attribute 'tpm'
11163 10:03:30.333378 #
11164 10:03:30.340232 # ======================================================================
11165 10:03:30.344127 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11166 10:03:30.353427 # ----------------------------------------------------------------------
11167 10:03:30.353867 # Traceback (most recent call last):
11168 10:03:30.363531 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11169 10:03:30.370576 # self.root_key = self.client.create_root_key()
11170 10:03:30.380007 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11171 10:03:30.383391 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11172 10:03:30.393936 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11173 10:03:30.396981 # raise ProtocolError(cc, rc)
11174 10:03:30.403615 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11175 10:03:30.404144 #
11176 10:03:30.409749 # ======================================================================
11177 10:03:30.416592 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11178 10:03:30.423056 # ----------------------------------------------------------------------
11179 10:03:30.426534 # Traceback (most recent call last):
11180 10:03:30.436734 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11181 10:03:30.439997 # self.client = tpm2.Client()
11182 10:03:30.450031 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11183 10:03:30.452972 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11184 10:03:30.459455 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11185 10:03:30.459797 #
11186 10:03:30.466191 # ======================================================================
11187 10:03:30.469318 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11188 10:03:30.476194 # ----------------------------------------------------------------------
11189 10:03:30.479325 # Traceback (most recent call last):
11190 10:03:30.489304 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11191 10:03:30.492832 # self.client = tpm2.Client()
11192 10:03:30.502478 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11193 10:03:30.505896 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11194 10:03:30.512477 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11195 10:03:30.512685 #
11196 10:03:30.519194 # ======================================================================
11197 10:03:30.522549 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11198 10:03:30.529267 # ----------------------------------------------------------------------
11199 10:03:30.532210 # Traceback (most recent call last):
11200 10:03:30.542426 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11201 10:03:30.545401 # self.client = tpm2.Client()
11202 10:03:30.556023 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11203 10:03:30.562317 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11204 10:03:30.566112 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11205 10:03:30.566394 #
11206 10:03:30.572176 # ======================================================================
11207 10:03:30.579191 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11208 10:03:30.585400 # ----------------------------------------------------------------------
11209 10:03:30.588583 # Traceback (most recent call last):
11210 10:03:30.598764 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11211 10:03:30.602070 # self.client = tpm2.Client()
11212 10:03:30.611777 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11213 10:03:30.615332 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11214 10:03:30.621666 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11215 10:03:30.622344 #
11216 10:03:30.628338 # ======================================================================
11217 10:03:30.631755 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11218 10:03:30.638163 # ----------------------------------------------------------------------
11219 10:03:30.641967 # Traceback (most recent call last):
11220 10:03:30.651629 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11221 10:03:30.655243 # self.client = tpm2.Client()
11222 10:03:30.664887 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11223 10:03:30.673058 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11224 10:03:30.676373 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11225 10:03:30.676666 #
11226 10:03:30.683347 # ======================================================================
11227 10:03:30.686687 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11228 10:03:30.695905 # ----------------------------------------------------------------------
11229 10:03:30.696437 # Traceback (most recent call last):
11230 10:03:30.707122 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11231 10:03:30.714947 # self.client = tpm2.Client()
11232 10:03:30.722441 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11233 10:03:30.725926 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11234 10:03:30.728692 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11235 10:03:30.729171 #
11236 10:03:30.735254 # ======================================================================
11237 10:03:30.742711 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11238 10:03:30.748729 # ----------------------------------------------------------------------
11239 10:03:30.751988 # Traceback (most recent call last):
11240 10:03:30.761637 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11241 10:03:30.765070 # self.client = tpm2.Client()
11242 10:03:30.775497 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11243 10:03:30.781739 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11244 10:03:30.784967 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11245 10:03:30.785052 #
11246 10:03:30.791445 # ======================================================================
11247 10:03:30.798353 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11248 10:03:30.804924 # ----------------------------------------------------------------------
11249 10:03:30.808241 # Traceback (most recent call last):
11250 10:03:30.817746 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11251 10:03:30.821586 # self.client = tpm2.Client()
11252 10:03:30.831410 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11253 10:03:30.834587 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11254 10:03:30.840974 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11255 10:03:30.841199 #
11256 10:03:30.847937 # ----------------------------------------------------------------------
11257 10:03:30.851206 # Ran 9 tests in 0.028s
11258 10:03:30.851307 #
11259 10:03:30.851373 # FAILED (errors=9)
11260 10:03:30.854622 # test_async (tpm2_tests.AsyncTest) ... ok
11261 10:03:30.860981 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11262 10:03:30.861121 #
11263 10:03:30.867449 # ----------------------------------------------------------------------
11264 10:03:30.870806 # Ran 2 tests in 0.031s
11265 10:03:30.870893 #
11266 10:03:30.870960 # OK
11267 10:03:30.874230 ok 1 selftests: tpm2: test_smoke.sh
11268 10:03:30.877398 # selftests: tpm2: test_space.sh
11269 10:03:30.881136 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11270 10:03:30.887376 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11271 10:03:30.890850 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11272 10:03:30.894793 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11273 10:03:30.894890 #
11274 10:03:30.901033 # ======================================================================
11275 10:03:30.907622 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11276 10:03:30.914515 # ----------------------------------------------------------------------
11277 10:03:30.917408 # Traceback (most recent call last):
11278 10:03:30.927419 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11279 10:03:30.930795 # root1 = space1.create_root_key()
11280 10:03:30.940757 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11281 10:03:30.946900 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11282 10:03:30.956901 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11283 10:03:30.960288 # raise ProtocolError(cc, rc)
11284 10:03:30.966870 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11285 10:03:30.966993 #
11286 10:03:30.973506 # ======================================================================
11287 10:03:30.976720 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11288 10:03:30.983254 # ----------------------------------------------------------------------
11289 10:03:30.986692 # Traceback (most recent call last):
11290 10:03:30.997139 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11291 10:03:31.000325 # space1.create_root_key()
11292 10:03:31.010140 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11293 10:03:31.016619 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11294 10:03:31.026439 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11295 10:03:31.029880 # raise ProtocolError(cc, rc)
11296 10:03:31.036299 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11297 10:03:31.036468 #
11298 10:03:31.042812 # ======================================================================
11299 10:03:31.046417 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11300 10:03:31.052941 # ----------------------------------------------------------------------
11301 10:03:31.056344 # Traceback (most recent call last):
11302 10:03:31.066089 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11303 10:03:31.069906 # root1 = space1.create_root_key()
11304 10:03:31.082663 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11305 10:03:31.086565 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11306 10:03:31.096289 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11307 10:03:31.099539 # raise ProtocolError(cc, rc)
11308 10:03:31.105751 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11309 10:03:31.105924 #
11310 10:03:31.113054 # ======================================================================
11311 10:03:31.116075 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11312 10:03:31.122412 # ----------------------------------------------------------------------
11313 10:03:31.125775 # Traceback (most recent call last):
11314 10:03:31.139769 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11315 10:03:31.142216 # root1 = space1.create_root_key()
11316 10:03:31.153031 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11317 10:03:31.159398 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11318 10:03:31.168700 # File "/lava-10670651/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11319 10:03:31.172325 # raise ProtocolError(cc, rc)
11320 10:03:31.175368 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11321 10:03:31.178661 #
11322 10:03:31.182307 # ----------------------------------------------------------------------
11323 10:03:31.185664 # Ran 4 tests in 0.062s
11324 10:03:31.185753 #
11325 10:03:31.188673 # FAILED (errors=4)
11326 10:03:31.192278 not ok 2 selftests: tpm2: test_space.sh # exit=1
11327 10:03:31.201090 tpm2_test_smoke_sh pass
11328 10:03:31.203870 tpm2_test_space_sh fail
11329 10:03:31.251849 + ../../utils/send-to-lava.sh ./output/result.txt
11330 10:03:31.372956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11331 10:03:31.373630 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11333 10:03:31.409132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11334 10:03:31.409455 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11336 10:03:31.412012 + set +x
11337 10:03:31.415671 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 10670651_1.6.2.3.5>
11338 10:03:31.415926 Received signal: <ENDRUN> 1_kselftest-tpm2 10670651_1.6.2.3.5
11339 10:03:31.416003 Ending use of test pattern.
11340 10:03:31.416067 Ending test lava.1_kselftest-tpm2 (10670651_1.6.2.3.5), duration 9.15
11342 10:03:31.501684 <LAVA_TEST_RUNNER EXIT>
11343 10:03:31.502451 ok: lava_test_shell seems to have completed
11344 10:03:31.502978 tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11345 10:03:31.503400 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11346 10:03:31.503820 end: 3 lava-test-retry (duration 00:00:10) [common]
11347 10:03:31.504241 start: 4 finalize (timeout 00:07:46) [common]
11348 10:03:31.504676 start: 4.1 power-off (timeout 00:00:30) [common]
11349 10:03:31.505491 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11350 10:03:31.610554 >> Command sent successfully.
11351 10:03:31.624400 Returned 0 in 0 seconds
11352 10:03:31.725469 end: 4.1 power-off (duration 00:00:00) [common]
11354 10:03:31.726236 start: 4.2 read-feedback (timeout 00:07:46) [common]
11355 10:03:31.726911 Listened to connection for namespace 'common' for up to 1s
11356 10:03:32.727640 Finalising connection for namespace 'common'
11357 10:03:32.727826 Disconnecting from shell: Finalise
11358 10:03:32.727914 / #
11359 10:03:32.828232 end: 4.2 read-feedback (duration 00:00:01) [common]
11360 10:03:32.828444 end: 4 finalize (duration 00:00:01) [common]
11361 10:03:32.828592 Cleaning after the job
11362 10:03:32.828725 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/ramdisk
11363 10:03:32.830984 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/kernel
11364 10:03:32.839724 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/dtb
11365 10:03:32.839936 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/nfsrootfs
11366 10:03:32.906918 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670651/tftp-deploy-ehdb4tg6/modules
11367 10:03:32.912439 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10670651
11368 10:03:33.443208 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10670651
11369 10:03:33.443395 Job finished correctly