Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 33
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 65
- Errors: 2
1 10:03:54.642748 lava-dispatcher, installed at version: 2023.05.1
2 10:03:54.642962 start: 0 validate
3 10:03:54.643094 Start time: 2023-06-10 10:03:54.643087+00:00 (UTC)
4 10:03:54.643217 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:03:54.643346 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 10:03:54.915490 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:03:54.915690 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:03:55.180654 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:03:55.180901 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:03:55.438610 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:03:55.438798 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-45-gce658d9231044%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:03:55.704587 validate duration: 1.06
14 10:03:55.704903 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:03:55.705005 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:03:55.705090 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:03:55.705219 Not decompressing ramdisk as can be used compressed.
18 10:03:55.705302 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 10:03:55.705368 saving as /var/lib/lava/dispatcher/tmp/10670678/tftp-deploy-rou30s_h/ramdisk/rootfs.cpio.gz
20 10:03:55.705428 total size: 27151647 (25MB)
21 10:03:55.706470 progress 0% (0MB)
22 10:03:55.713459 progress 5% (1MB)
23 10:03:55.720090 progress 10% (2MB)
24 10:03:55.726908 progress 15% (3MB)
25 10:03:55.733552 progress 20% (5MB)
26 10:03:55.740488 progress 25% (6MB)
27 10:03:55.747438 progress 30% (7MB)
28 10:03:55.754452 progress 35% (9MB)
29 10:03:55.761380 progress 40% (10MB)
30 10:03:55.768293 progress 45% (11MB)
31 10:03:55.777035 progress 50% (12MB)
32 10:03:55.783815 progress 55% (14MB)
33 10:03:55.790698 progress 60% (15MB)
34 10:03:55.797361 progress 65% (16MB)
35 10:03:55.804144 progress 70% (18MB)
36 10:03:55.810888 progress 75% (19MB)
37 10:03:55.817578 progress 80% (20MB)
38 10:03:55.824454 progress 85% (22MB)
39 10:03:55.831080 progress 90% (23MB)
40 10:03:55.837843 progress 95% (24MB)
41 10:03:55.844488 progress 100% (25MB)
42 10:03:55.844688 25MB downloaded in 0.14s (185.95MB/s)
43 10:03:55.844849 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:03:55.845087 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:03:55.845177 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:03:55.845261 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:03:55.845397 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:03:55.845473 saving as /var/lib/lava/dispatcher/tmp/10670678/tftp-deploy-rou30s_h/kernel/Image
50 10:03:55.845534 total size: 45746688 (43MB)
51 10:03:55.845596 No compression specified
52 10:03:55.846760 progress 0% (0MB)
53 10:03:55.858274 progress 5% (2MB)
54 10:03:55.870018 progress 10% (4MB)
55 10:03:55.881714 progress 15% (6MB)
56 10:03:55.893260 progress 20% (8MB)
57 10:03:55.905961 progress 25% (10MB)
58 10:03:55.917421 progress 30% (13MB)
59 10:03:55.928827 progress 35% (15MB)
60 10:03:55.940229 progress 40% (17MB)
61 10:03:55.951672 progress 45% (19MB)
62 10:03:55.963243 progress 50% (21MB)
63 10:03:55.974858 progress 55% (24MB)
64 10:03:55.986454 progress 60% (26MB)
65 10:03:55.998004 progress 65% (28MB)
66 10:03:56.009809 progress 70% (30MB)
67 10:03:56.021234 progress 75% (32MB)
68 10:03:56.032476 progress 80% (34MB)
69 10:03:56.043865 progress 85% (37MB)
70 10:03:56.055258 progress 90% (39MB)
71 10:03:56.066717 progress 95% (41MB)
72 10:03:56.078254 progress 100% (43MB)
73 10:03:56.078416 43MB downloaded in 0.23s (187.34MB/s)
74 10:03:56.078565 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:03:56.078794 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:03:56.078882 start: 1.3 download-retry (timeout 00:10:00) [common]
78 10:03:56.078973 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 10:03:56.079112 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:03:56.079187 saving as /var/lib/lava/dispatcher/tmp/10670678/tftp-deploy-rou30s_h/dtb/mt8192-asurada-spherion-r0.dtb
81 10:03:56.079249 total size: 46924 (0MB)
82 10:03:56.079308 No compression specified
83 10:03:56.080460 progress 69% (0MB)
84 10:03:56.080730 progress 100% (0MB)
85 10:03:56.080932 0MB downloaded in 0.00s (26.62MB/s)
86 10:03:56.081054 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:03:56.081274 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:03:56.081359 start: 1.4 download-retry (timeout 00:10:00) [common]
90 10:03:56.081441 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 10:03:56.081549 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:03:56.081617 saving as /var/lib/lava/dispatcher/tmp/10670678/tftp-deploy-rou30s_h/modules/modules.tar
93 10:03:56.081678 total size: 8540248 (8MB)
94 10:03:56.081738 Using unxz to decompress xz
95 10:03:56.085391 progress 0% (0MB)
96 10:03:56.107382 progress 5% (0MB)
97 10:03:56.131666 progress 10% (0MB)
98 10:03:56.155238 progress 15% (1MB)
99 10:03:56.180630 progress 20% (1MB)
100 10:03:56.205057 progress 25% (2MB)
101 10:03:56.227790 progress 30% (2MB)
102 10:03:56.252992 progress 35% (2MB)
103 10:03:56.277744 progress 40% (3MB)
104 10:03:56.301342 progress 45% (3MB)
105 10:03:56.328316 progress 50% (4MB)
106 10:03:56.352757 progress 55% (4MB)
107 10:03:56.378355 progress 60% (4MB)
108 10:03:56.404078 progress 65% (5MB)
109 10:03:56.429267 progress 70% (5MB)
110 10:03:56.453208 progress 75% (6MB)
111 10:03:56.476671 progress 80% (6MB)
112 10:03:56.500697 progress 85% (6MB)
113 10:03:56.529572 progress 90% (7MB)
114 10:03:56.554879 progress 95% (7MB)
115 10:03:56.579684 progress 100% (8MB)
116 10:03:56.585002 8MB downloaded in 0.50s (16.18MB/s)
117 10:03:56.585283 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:03:56.585542 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:03:56.585633 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:03:56.585730 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:03:56.585820 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:03:56.585905 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:03:56.586129 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0
125 10:03:56.586256 makedir: /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin
126 10:03:56.586357 makedir: /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/tests
127 10:03:56.586453 makedir: /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/results
128 10:03:56.586566 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-add-keys
129 10:03:56.586707 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-add-sources
130 10:03:56.586833 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-background-process-start
131 10:03:56.586961 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-background-process-stop
132 10:03:56.587081 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-common-functions
133 10:03:56.587199 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-echo-ipv4
134 10:03:56.587319 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-install-packages
135 10:03:56.587436 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-installed-packages
136 10:03:56.587553 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-os-build
137 10:03:56.587671 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-probe-channel
138 10:03:56.587791 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-probe-ip
139 10:03:56.587908 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-target-ip
140 10:03:56.588026 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-target-mac
141 10:03:56.588143 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-target-storage
142 10:03:56.588264 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-test-case
143 10:03:56.588386 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-test-event
144 10:03:56.588502 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-test-feedback
145 10:03:56.588622 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-test-raise
146 10:03:56.588741 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-test-reference
147 10:03:56.588905 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-test-runner
148 10:03:56.589024 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-test-set
149 10:03:56.589145 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-test-shell
150 10:03:56.589267 Updating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-install-packages (oe)
151 10:03:56.589419 Updating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/bin/lava-installed-packages (oe)
152 10:03:56.589552 Creating /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/environment
153 10:03:56.589650 LAVA metadata
154 10:03:56.589724 - LAVA_JOB_ID=10670678
155 10:03:56.589823 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:03:56.589943 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:03:56.590035 skipped lava-vland-overlay
158 10:03:56.590114 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:03:56.590198 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:03:56.590263 skipped lava-multinode-overlay
161 10:03:56.590339 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:03:56.590423 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:03:56.590499 Loading test definitions
164 10:03:56.590591 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 10:03:56.590664 Using /lava-10670678 at stage 0
166 10:03:56.590950 uuid=10670678_1.5.2.3.1 testdef=None
167 10:03:56.591037 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:03:56.591124 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 10:03:56.591631 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:03:56.591854 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 10:03:56.592472 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:03:56.592707 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 10:03:56.593358 runner path: /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 10670678_1.5.2.3.1
176 10:03:56.593512 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:03:56.593719 Creating lava-test-runner.conf files
179 10:03:56.593782 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10670678/lava-overlay-lxomehl0/lava-10670678/0 for stage 0
180 10:03:56.593869 - 0_v4l2-compliance-mtk-vcodec-enc
181 10:03:56.593964 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 10:03:56.594052 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 10:03:56.600580 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 10:03:56.600683 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 10:03:56.600774 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 10:03:56.600898 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 10:03:56.600990 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 10:03:57.293677 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 10:03:57.294046 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 10:03:57.294165 extracting modules file /var/lib/lava/dispatcher/tmp/10670678/tftp-deploy-rou30s_h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10670678/extract-overlay-ramdisk-jsql7rj6/ramdisk
191 10:03:57.496984 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 10:03:57.497156 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 10:03:57.497251 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670678/compress-overlay-tr5zbdan/overlay-1.5.2.4.tar.gz to ramdisk
194 10:03:57.497320 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10670678/compress-overlay-tr5zbdan/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10670678/extract-overlay-ramdisk-jsql7rj6/ramdisk
195 10:03:57.503453 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 10:03:57.503564 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 10:03:57.503653 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 10:03:57.503741 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 10:03:57.503822 Building ramdisk /var/lib/lava/dispatcher/tmp/10670678/extract-overlay-ramdisk-jsql7rj6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10670678/extract-overlay-ramdisk-jsql7rj6/ramdisk
200 10:03:58.078001 >> 230342 blocks
201 10:04:01.976189 rename /var/lib/lava/dispatcher/tmp/10670678/extract-overlay-ramdisk-jsql7rj6/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10670678/tftp-deploy-rou30s_h/ramdisk/ramdisk.cpio.gz
202 10:04:01.976584 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 10:04:01.976703 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 10:04:01.976826 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 10:04:01.976940 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10670678/tftp-deploy-rou30s_h/kernel/Image'
206 10:04:13.465035 Returned 0 in 11 seconds
207 10:04:13.565633 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10670678/tftp-deploy-rou30s_h/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10670678/tftp-deploy-rou30s_h/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10670678/tftp-deploy-rou30s_h/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10670678/tftp-deploy-rou30s_h/kernel/image.itb
208 10:04:14.142840 output: FIT description: Kernel Image image with one or more FDT blobs
209 10:04:14.143186 output: Created: Sat Jun 10 11:04:14 2023
210 10:04:14.143264 output: Image 0 (kernel-1)
211 10:04:14.143331 output: Description:
212 10:04:14.143396 output: Created: Sat Jun 10 11:04:14 2023
213 10:04:14.143460 output: Type: Kernel Image
214 10:04:14.143522 output: Compression: lzma compressed
215 10:04:14.143585 output: Data Size: 10087317 Bytes = 9850.90 KiB = 9.62 MiB
216 10:04:14.143646 output: Architecture: AArch64
217 10:04:14.143701 output: OS: Linux
218 10:04:14.143755 output: Load Address: 0x00000000
219 10:04:14.143811 output: Entry Point: 0x00000000
220 10:04:14.143866 output: Hash algo: crc32
221 10:04:14.143920 output: Hash value: c9e456fd
222 10:04:14.143976 output: Image 1 (fdt-1)
223 10:04:14.144044 output: Description: mt8192-asurada-spherion-r0
224 10:04:14.144098 output: Created: Sat Jun 10 11:04:14 2023
225 10:04:14.144151 output: Type: Flat Device Tree
226 10:04:14.144205 output: Compression: uncompressed
227 10:04:14.144257 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 10:04:14.144311 output: Architecture: AArch64
229 10:04:14.144364 output: Hash algo: crc32
230 10:04:14.144417 output: Hash value: 1df858fa
231 10:04:14.144469 output: Image 2 (ramdisk-1)
232 10:04:14.144522 output: Description: unavailable
233 10:04:14.144575 output: Created: Sat Jun 10 11:04:14 2023
234 10:04:14.144628 output: Type: RAMDisk Image
235 10:04:14.144681 output: Compression: Unknown Compression
236 10:04:14.144733 output: Data Size: 40132123 Bytes = 39191.53 KiB = 38.27 MiB
237 10:04:14.144791 output: Architecture: AArch64
238 10:04:14.144844 output: OS: Linux
239 10:04:14.144897 output: Load Address: unavailable
240 10:04:14.144950 output: Entry Point: unavailable
241 10:04:14.145003 output: Hash algo: crc32
242 10:04:14.145055 output: Hash value: 3fe47065
243 10:04:14.145108 output: Default Configuration: 'conf-1'
244 10:04:14.145160 output: Configuration 0 (conf-1)
245 10:04:14.145212 output: Description: mt8192-asurada-spherion-r0
246 10:04:14.145265 output: Kernel: kernel-1
247 10:04:14.145317 output: Init Ramdisk: ramdisk-1
248 10:04:14.145370 output: FDT: fdt-1
249 10:04:14.145422 output: Loadables: kernel-1
250 10:04:14.145474 output:
251 10:04:14.145655 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 10:04:14.145755 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 10:04:14.145863 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 10:04:14.145957 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
255 10:04:14.146056 No LXC device requested
256 10:04:14.146137 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 10:04:14.146227 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
258 10:04:14.146307 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 10:04:14.146378 Checking files for TFTP limit of 4294967296 bytes.
260 10:04:14.146861 end: 1 tftp-deploy (duration 00:00:18) [common]
261 10:04:14.146966 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 10:04:14.147058 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 10:04:14.147176 substitutions:
264 10:04:14.147244 - {DTB}: 10670678/tftp-deploy-rou30s_h/dtb/mt8192-asurada-spherion-r0.dtb
265 10:04:14.147308 - {INITRD}: 10670678/tftp-deploy-rou30s_h/ramdisk/ramdisk.cpio.gz
266 10:04:14.147367 - {KERNEL}: 10670678/tftp-deploy-rou30s_h/kernel/Image
267 10:04:14.147425 - {LAVA_MAC}: None
268 10:04:14.147482 - {PRESEED_CONFIG}: None
269 10:04:14.147537 - {PRESEED_LOCAL}: None
270 10:04:14.147592 - {RAMDISK}: 10670678/tftp-deploy-rou30s_h/ramdisk/ramdisk.cpio.gz
271 10:04:14.147647 - {ROOT_PART}: None
272 10:04:14.147702 - {ROOT}: None
273 10:04:14.147756 - {SERVER_IP}: 192.168.201.1
274 10:04:14.147810 - {TEE}: None
275 10:04:14.147864 Parsed boot commands:
276 10:04:14.147920 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 10:04:14.148124 Parsed boot commands: tftpboot 192.168.201.1 10670678/tftp-deploy-rou30s_h/kernel/image.itb 10670678/tftp-deploy-rou30s_h/kernel/cmdline
278 10:04:14.148232 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 10:04:14.148321 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 10:04:14.148417 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 10:04:14.148504 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 10:04:14.148578 Not connected, no need to disconnect.
283 10:04:14.148654 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 10:04:14.148732 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 10:04:14.148807 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
286 10:04:14.152036 Setting prompt string to ['lava-test: # ']
287 10:04:14.152352 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 10:04:14.152462 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 10:04:14.152592 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 10:04:14.152686 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 10:04:14.152919 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 10:04:19.284414 >> Command sent successfully.
293 10:04:19.286813 Returned 0 in 5 seconds
294 10:04:19.387189 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 10:04:19.387741 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 10:04:19.387845 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 10:04:19.387929 Setting prompt string to 'Starting depthcharge on Spherion...'
299 10:04:19.387995 Changing prompt to 'Starting depthcharge on Spherion...'
300 10:04:19.388066 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 10:04:19.388327 [Enter `^Ec?' for help]
302 10:04:19.562051
303 10:04:19.562188
304 10:04:19.562259 F0: 102B 0000
305 10:04:19.562323
306 10:04:19.562384 F3: 1001 0000 [0200]
307 10:04:19.562444
308 10:04:19.565811 F3: 1001 0000
309 10:04:19.565896
310 10:04:19.565962 F7: 102D 0000
311 10:04:19.566025
312 10:04:19.566085 F1: 0000 0000
313 10:04:19.566174
314 10:04:19.569093 V0: 0000 0000 [0001]
315 10:04:19.569176
316 10:04:19.569304 00: 0007 8000
317 10:04:19.569426
318 10:04:19.572625 01: 0000 0000
319 10:04:19.572734
320 10:04:19.572823 BP: 0C00 0209 [0000]
321 10:04:19.572887
322 10:04:19.576667 G0: 1182 0000
323 10:04:19.576755
324 10:04:19.576865 EC: 0000 0021 [4000]
325 10:04:19.576930
326 10:04:19.579916 S7: 0000 0000 [0000]
327 10:04:19.579987
328 10:04:19.580048 CC: 0000 0000 [0001]
329 10:04:19.580109
330 10:04:19.583578 T0: 0000 0040 [010F]
331 10:04:19.583705
332 10:04:19.583793 Jump to BL
333 10:04:19.583860
334 10:04:19.608675
335 10:04:19.608791
336 10:04:19.608875
337 10:04:19.615834 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 10:04:19.618998 ARM64: Exception handlers installed.
339 10:04:19.622984 ARM64: Testing exception
340 10:04:19.626288 ARM64: Done test exception
341 10:04:19.633332 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 10:04:19.643880 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 10:04:19.650496 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 10:04:19.660677 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 10:04:19.667259 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 10:04:19.673671 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 10:04:19.685326 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 10:04:19.691977 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 10:04:19.711246 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 10:04:19.714661 WDT: Last reset was cold boot
351 10:04:19.718230 SPI1(PAD0) initialized at 2873684 Hz
352 10:04:19.721069 SPI5(PAD0) initialized at 992727 Hz
353 10:04:19.724568 VBOOT: Loading verstage.
354 10:04:19.731247 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 10:04:19.734323 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 10:04:19.737616 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 10:04:19.740799 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 10:04:19.748728 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 10:04:19.755427 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 10:04:19.766389 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 10:04:19.766476
362 10:04:19.766542
363 10:04:19.776323 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 10:04:19.779618 ARM64: Exception handlers installed.
365 10:04:19.782570 ARM64: Testing exception
366 10:04:19.782655 ARM64: Done test exception
367 10:04:19.789352 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 10:04:19.792644 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 10:04:19.806964 Probing TPM: . done!
370 10:04:19.807051 TPM ready after 0 ms
371 10:04:19.813833 Connected to device vid:did:rid of 1ae0:0028:00
372 10:04:19.823894 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 10:04:19.879241 Initialized TPM device CR50 revision 0
374 10:04:19.891588 tlcl_send_startup: Startup return code is 0
375 10:04:19.891699 TPM: setup succeeded
376 10:04:19.902492 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 10:04:19.911646 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 10:04:19.921360 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 10:04:19.930650 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 10:04:19.934153 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 10:04:19.940677 in-header: 03 07 00 00 08 00 00 00
382 10:04:19.944176 in-data: aa e4 47 04 13 02 00 00
383 10:04:19.947694 Chrome EC: UHEPI supported
384 10:04:19.954693 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 10:04:19.958360 in-header: 03 ad 00 00 08 00 00 00
386 10:04:19.961929 in-data: 00 20 20 08 00 00 00 00
387 10:04:19.962042 Phase 1
388 10:04:19.965686 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 10:04:19.973140 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 10:04:19.976552 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 10:04:19.980224 Recovery requested (1009000e)
392 10:04:19.989970 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 10:04:19.994997 tlcl_extend: response is 0
394 10:04:20.004997 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 10:04:20.011110 tlcl_extend: response is 0
396 10:04:20.018258 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 10:04:20.038508 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 10:04:20.045602 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 10:04:20.045691
400 10:04:20.045784
401 10:04:20.055306 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 10:04:20.058648 ARM64: Exception handlers installed.
403 10:04:20.062062 ARM64: Testing exception
404 10:04:20.062150 ARM64: Done test exception
405 10:04:20.083788 pmic_efuse_setting: Set efuses in 11 msecs
406 10:04:20.087692 pmwrap_interface_init: Select PMIF_VLD_RDY
407 10:04:20.093981 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 10:04:20.097408 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 10:04:20.101051 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 10:04:20.107694 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 10:04:20.111488 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 10:04:20.118010 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 10:04:20.121941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 10:04:20.125780 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 10:04:20.132935 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 10:04:20.136373 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 10:04:20.139391 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 10:04:20.146282 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 10:04:20.149613 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 10:04:20.156613 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 10:04:20.163283 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 10:04:20.166711 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 10:04:20.174242 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 10:04:20.178151 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 10:04:20.185477 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 10:04:20.191630 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 10:04:20.195304 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 10:04:20.202407 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 10:04:20.205763 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 10:04:20.212573 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 10:04:20.215775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 10:04:20.222107 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 10:04:20.228761 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 10:04:20.232899 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 10:04:20.239156 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 10:04:20.242455 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 10:04:20.249284 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 10:04:20.252526 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 10:04:20.258858 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 10:04:20.262522 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 10:04:20.268900 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 10:04:20.272536 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 10:04:20.278650 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 10:04:20.282017 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 10:04:20.285677 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 10:04:20.292040 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 10:04:20.295472 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 10:04:20.298651 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 10:04:20.305523 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 10:04:20.309302 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 10:04:20.312698 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 10:04:20.318988 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 10:04:20.322490 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 10:04:20.325815 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 10:04:20.329494 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 10:04:20.335970 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 10:04:20.339096 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 10:04:20.345570 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 10:04:20.356068 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 10:04:20.358975 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 10:04:20.369172 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 10:04:20.375549 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 10:04:20.382079 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 10:04:20.385408 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 10:04:20.388962 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 10:04:20.396254 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x13
467 10:04:20.403020 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 10:04:20.406621 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 10:04:20.412758 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 10:04:20.421312 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 10:04:20.430734 [RTC]rtc_get_frequency_meter,154: input=23, output=955
472 10:04:20.439902 [RTC]rtc_get_frequency_meter,154: input=19, output=864
473 10:04:20.449300 [RTC]rtc_get_frequency_meter,154: input=17, output=818
474 10:04:20.459127 [RTC]rtc_get_frequency_meter,154: input=16, output=795
475 10:04:20.462123 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 10:04:20.468868 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 10:04:20.472238 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 10:04:20.475648 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 10:04:20.479051 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 10:04:20.482017 ADC[4]: Raw value=902876 ID=7
481 10:04:20.486008 ADC[3]: Raw value=213179 ID=1
482 10:04:20.486100 RAM Code: 0x71
483 10:04:20.492329 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 10:04:20.496058 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 10:04:20.506036 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 10:04:20.512337 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 10:04:20.515571 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 10:04:20.519147 in-header: 03 07 00 00 08 00 00 00
489 10:04:20.522301 in-data: aa e4 47 04 13 02 00 00
490 10:04:20.525451 Chrome EC: UHEPI supported
491 10:04:20.532624 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 10:04:20.535540 in-header: 03 ed 00 00 08 00 00 00
493 10:04:20.539389 in-data: 80 20 60 08 00 00 00 00
494 10:04:20.542203 MRC: failed to locate region type 0.
495 10:04:20.549001 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 10:04:20.549103 DRAM-K: Running full calibration
497 10:04:20.555598 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 10:04:20.559463 header.status = 0x0
499 10:04:20.562214 header.version = 0x6 (expected: 0x6)
500 10:04:20.565407 header.size = 0xd00 (expected: 0xd00)
501 10:04:20.569031 header.flags = 0x0
502 10:04:20.572295 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 10:04:20.590997 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
504 10:04:20.597979 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 10:04:20.601099 dram_init: ddr_geometry: 2
506 10:04:20.604567 [EMI] MDL number = 2
507 10:04:20.604652 [EMI] Get MDL freq = 0
508 10:04:20.607708 dram_init: ddr_type: 0
509 10:04:20.607793 is_discrete_lpddr4: 1
510 10:04:20.610812 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 10:04:20.610896
512 10:04:20.610963
513 10:04:20.614627 [Bian_co] ETT version 0.0.0.1
514 10:04:20.621500 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 10:04:20.621585
516 10:04:20.625549 dramc_set_vcore_voltage set vcore to 650000
517 10:04:20.625634 Read voltage for 800, 4
518 10:04:20.628968 Vio18 = 0
519 10:04:20.629052 Vcore = 650000
520 10:04:20.629119 Vdram = 0
521 10:04:20.629180 Vddq = 0
522 10:04:20.632477 Vmddr = 0
523 10:04:20.632587 dram_init: config_dvfs: 1
524 10:04:20.640239 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 10:04:20.643720 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 10:04:20.647279 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 10:04:20.650979 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 10:04:20.654389 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 10:04:20.658108 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 10:04:20.661867 MEM_TYPE=3, freq_sel=18
531 10:04:20.665309 sv_algorithm_assistance_LP4_1600
532 10:04:20.669293 ============ PULL DRAM RESETB DOWN ============
533 10:04:20.673227 ========== PULL DRAM RESETB DOWN end =========
534 10:04:20.676700 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 10:04:20.680026 ===================================
536 10:04:20.683540 LPDDR4 DRAM CONFIGURATION
537 10:04:20.686702 ===================================
538 10:04:20.686788 EX_ROW_EN[0] = 0x0
539 10:04:20.690084 EX_ROW_EN[1] = 0x0
540 10:04:20.693313 LP4Y_EN = 0x0
541 10:04:20.693400 WORK_FSP = 0x0
542 10:04:20.696610 WL = 0x2
543 10:04:20.696725 RL = 0x2
544 10:04:20.699818 BL = 0x2
545 10:04:20.699904 RPST = 0x0
546 10:04:20.703555 RD_PRE = 0x0
547 10:04:20.703641 WR_PRE = 0x1
548 10:04:20.706813 WR_PST = 0x0
549 10:04:20.706899 DBI_WR = 0x0
550 10:04:20.709780 DBI_RD = 0x0
551 10:04:20.709866 OTF = 0x1
552 10:04:20.713070 ===================================
553 10:04:20.717000 ===================================
554 10:04:20.719860 ANA top config
555 10:04:20.723379 ===================================
556 10:04:20.723466 DLL_ASYNC_EN = 0
557 10:04:20.726887 ALL_SLAVE_EN = 1
558 10:04:20.730465 NEW_RANK_MODE = 1
559 10:04:20.733894 DLL_IDLE_MODE = 1
560 10:04:20.733978 LP45_APHY_COMB_EN = 1
561 10:04:20.737485 TX_ODT_DIS = 1
562 10:04:20.741016 NEW_8X_MODE = 1
563 10:04:20.745054 ===================================
564 10:04:20.748488 ===================================
565 10:04:20.748574 data_rate = 1600
566 10:04:20.752429 CKR = 1
567 10:04:20.755992 DQ_P2S_RATIO = 8
568 10:04:20.759584 ===================================
569 10:04:20.759669 CA_P2S_RATIO = 8
570 10:04:20.763040 DQ_CA_OPEN = 0
571 10:04:20.766378 DQ_SEMI_OPEN = 0
572 10:04:20.769813 CA_SEMI_OPEN = 0
573 10:04:20.773459 CA_FULL_RATE = 0
574 10:04:20.776474 DQ_CKDIV4_EN = 1
575 10:04:20.776559 CA_CKDIV4_EN = 1
576 10:04:20.779634 CA_PREDIV_EN = 0
577 10:04:20.783310 PH8_DLY = 0
578 10:04:20.786584 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 10:04:20.789952 DQ_AAMCK_DIV = 4
580 10:04:20.793006 CA_AAMCK_DIV = 4
581 10:04:20.793090 CA_ADMCK_DIV = 4
582 10:04:20.796522 DQ_TRACK_CA_EN = 0
583 10:04:20.799619 CA_PICK = 800
584 10:04:20.803390 CA_MCKIO = 800
585 10:04:20.806869 MCKIO_SEMI = 0
586 10:04:20.810005 PLL_FREQ = 3068
587 10:04:20.812946 DQ_UI_PI_RATIO = 32
588 10:04:20.813030 CA_UI_PI_RATIO = 0
589 10:04:20.816494 ===================================
590 10:04:20.819598 ===================================
591 10:04:20.822826 memory_type:LPDDR4
592 10:04:20.826442 GP_NUM : 10
593 10:04:20.826520 SRAM_EN : 1
594 10:04:20.829416 MD32_EN : 0
595 10:04:20.833123 ===================================
596 10:04:20.836458 [ANA_INIT] >>>>>>>>>>>>>>
597 10:04:20.836545 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 10:04:20.840037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 10:04:20.843830 ===================================
600 10:04:20.847462 data_rate = 1600,PCW = 0X7600
601 10:04:20.850794 ===================================
602 10:04:20.854955 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 10:04:20.858311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 10:04:20.865392 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 10:04:20.869288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 10:04:20.872732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 10:04:20.876500 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 10:04:20.879585 [ANA_INIT] flow start
609 10:04:20.879671 [ANA_INIT] PLL >>>>>>>>
610 10:04:20.883475 [ANA_INIT] PLL <<<<<<<<
611 10:04:20.886140 [ANA_INIT] MIDPI >>>>>>>>
612 10:04:20.886227 [ANA_INIT] MIDPI <<<<<<<<
613 10:04:20.889473 [ANA_INIT] DLL >>>>>>>>
614 10:04:20.892892 [ANA_INIT] flow end
615 10:04:20.896392 ============ LP4 DIFF to SE enter ============
616 10:04:20.899546 ============ LP4 DIFF to SE exit ============
617 10:04:20.903279 [ANA_INIT] <<<<<<<<<<<<<
618 10:04:20.906460 [Flow] Enable top DCM control >>>>>
619 10:04:20.909644 [Flow] Enable top DCM control <<<<<
620 10:04:20.913255 Enable DLL master slave shuffle
621 10:04:20.916435 ==============================================================
622 10:04:20.919643 Gating Mode config
623 10:04:20.926510 ==============================================================
624 10:04:20.926597 Config description:
625 10:04:20.936588 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 10:04:20.943070 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 10:04:20.946729 SELPH_MODE 0: By rank 1: By Phase
628 10:04:20.953198 ==============================================================
629 10:04:20.956227 GAT_TRACK_EN = 1
630 10:04:20.959818 RX_GATING_MODE = 2
631 10:04:20.962920 RX_GATING_TRACK_MODE = 2
632 10:04:20.966235 SELPH_MODE = 1
633 10:04:20.969807 PICG_EARLY_EN = 1
634 10:04:20.973187 VALID_LAT_VALUE = 1
635 10:04:20.976402 ==============================================================
636 10:04:20.979966 Enter into Gating configuration >>>>
637 10:04:20.983404 Exit from Gating configuration <<<<
638 10:04:20.986824 Enter into DVFS_PRE_config >>>>>
639 10:04:20.997050 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 10:04:21.001004 Exit from DVFS_PRE_config <<<<<
641 10:04:21.003880 Enter into PICG configuration >>>>
642 10:04:21.007405 Exit from PICG configuration <<<<
643 10:04:21.011579 [RX_INPUT] configuration >>>>>
644 10:04:21.011667 [RX_INPUT] configuration <<<<<
645 10:04:21.018633 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 10:04:21.022141 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 10:04:21.029633 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 10:04:21.036889 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 10:04:21.043552 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 10:04:21.047510 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 10:04:21.050956 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 10:04:21.054583 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 10:04:21.062611 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 10:04:21.065829 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 10:04:21.069997 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 10:04:21.073501 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 10:04:21.077095 ===================================
658 10:04:21.080279 LPDDR4 DRAM CONFIGURATION
659 10:04:21.080364 ===================================
660 10:04:21.084234 EX_ROW_EN[0] = 0x0
661 10:04:21.087878 EX_ROW_EN[1] = 0x0
662 10:04:21.087962 LP4Y_EN = 0x0
663 10:04:21.091239 WORK_FSP = 0x0
664 10:04:21.091323 WL = 0x2
665 10:04:21.091390 RL = 0x2
666 10:04:21.094952 BL = 0x2
667 10:04:21.095036 RPST = 0x0
668 10:04:21.098986 RD_PRE = 0x0
669 10:04:21.099069 WR_PRE = 0x1
670 10:04:21.103026 WR_PST = 0x0
671 10:04:21.103110 DBI_WR = 0x0
672 10:04:21.106706 DBI_RD = 0x0
673 10:04:21.106790 OTF = 0x1
674 10:04:21.110115 ===================================
675 10:04:21.114251 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 10:04:21.118399 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 10:04:21.121390 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 10:04:21.125390 ===================================
679 10:04:21.129059 LPDDR4 DRAM CONFIGURATION
680 10:04:21.133028 ===================================
681 10:04:21.133114 EX_ROW_EN[0] = 0x10
682 10:04:21.136365 EX_ROW_EN[1] = 0x0
683 10:04:21.136449 LP4Y_EN = 0x0
684 10:04:21.140171 WORK_FSP = 0x0
685 10:04:21.140260 WL = 0x2
686 10:04:21.144092 RL = 0x2
687 10:04:21.144176 BL = 0x2
688 10:04:21.147377 RPST = 0x0
689 10:04:21.147466 RD_PRE = 0x0
690 10:04:21.151215 WR_PRE = 0x1
691 10:04:21.151301 WR_PST = 0x0
692 10:04:21.151368 DBI_WR = 0x0
693 10:04:21.155168 DBI_RD = 0x0
694 10:04:21.155252 OTF = 0x1
695 10:04:21.159188 ===================================
696 10:04:21.166314 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 10:04:21.169876 nWR fixed to 40
698 10:04:21.173483 [ModeRegInit_LP4] CH0 RK0
699 10:04:21.173577 [ModeRegInit_LP4] CH0 RK1
700 10:04:21.176858 [ModeRegInit_LP4] CH1 RK0
701 10:04:21.176942 [ModeRegInit_LP4] CH1 RK1
702 10:04:21.180870 match AC timing 13
703 10:04:21.184365 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 10:04:21.188005 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 10:04:21.192153 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 10:04:21.199300 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 10:04:21.203038 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 10:04:21.203123 [EMI DOE] emi_dcm 0
709 10:04:21.210346 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 10:04:21.210431 ==
711 10:04:21.214273 Dram Type= 6, Freq= 0, CH_0, rank 0
712 10:04:21.218072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 10:04:21.218157 ==
714 10:04:21.221818 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 10:04:21.228687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 10:04:21.237817 [CA 0] Center 38 (7~69) winsize 63
717 10:04:21.241593 [CA 1] Center 38 (7~69) winsize 63
718 10:04:21.244608 [CA 2] Center 35 (5~66) winsize 62
719 10:04:21.248345 [CA 3] Center 35 (5~66) winsize 62
720 10:04:21.251881 [CA 4] Center 34 (4~65) winsize 62
721 10:04:21.255723 [CA 5] Center 33 (3~64) winsize 62
722 10:04:21.255807
723 10:04:21.258779 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 10:04:21.258864
725 10:04:21.262912 [CATrainingPosCal] consider 1 rank data
726 10:04:21.266029 u2DelayCellTimex100 = 270/100 ps
727 10:04:21.269525 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
728 10:04:21.273141 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 10:04:21.276598 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 10:04:21.279870 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
731 10:04:21.283830 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
732 10:04:21.287133 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 10:04:21.287244
734 10:04:21.290613 CA PerBit enable=1, Macro0, CA PI delay=33
735 10:04:21.290697
736 10:04:21.293535 [CBTSetCACLKResult] CA Dly = 33
737 10:04:21.293619 CS Dly: 5 (0~36)
738 10:04:21.297120 ==
739 10:04:21.300243 Dram Type= 6, Freq= 0, CH_0, rank 1
740 10:04:21.303420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 10:04:21.303506 ==
742 10:04:21.306768 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 10:04:21.313684 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 10:04:21.323792 [CA 0] Center 38 (7~69) winsize 63
745 10:04:21.326890 [CA 1] Center 38 (7~69) winsize 63
746 10:04:21.330191 [CA 2] Center 36 (6~66) winsize 61
747 10:04:21.333358 [CA 3] Center 35 (5~66) winsize 62
748 10:04:21.337030 [CA 4] Center 35 (4~66) winsize 63
749 10:04:21.340453 [CA 5] Center 34 (4~65) winsize 62
750 10:04:21.340538
751 10:04:21.343373 [CmdBusTrainingLP45] Vref(ca) range 1: 32
752 10:04:21.343458
753 10:04:21.346952 [CATrainingPosCal] consider 2 rank data
754 10:04:21.350164 u2DelayCellTimex100 = 270/100 ps
755 10:04:21.353834 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 10:04:21.360311 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
757 10:04:21.363660 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 10:04:21.367121 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 10:04:21.370312 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 10:04:21.373351 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 10:04:21.373435
762 10:04:21.376843 CA PerBit enable=1, Macro0, CA PI delay=34
763 10:04:21.376927
764 10:04:21.380196 [CBTSetCACLKResult] CA Dly = 34
765 10:04:21.380280 CS Dly: 6 (0~38)
766 10:04:21.383272
767 10:04:21.386711 ----->DramcWriteLeveling(PI) begin...
768 10:04:21.386796 ==
769 10:04:21.390074 Dram Type= 6, Freq= 0, CH_0, rank 0
770 10:04:21.393444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 10:04:21.393529 ==
772 10:04:21.396909 Write leveling (Byte 0): 34 => 34
773 10:04:21.399912 Write leveling (Byte 1): 29 => 29
774 10:04:21.403622 DramcWriteLeveling(PI) end<-----
775 10:04:21.403706
776 10:04:21.403773 ==
777 10:04:21.406493 Dram Type= 6, Freq= 0, CH_0, rank 0
778 10:04:21.409852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 10:04:21.409937 ==
780 10:04:21.413283 [Gating] SW mode calibration
781 10:04:21.420426 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 10:04:21.424182 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 10:04:21.431224 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 10:04:21.434549 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
785 10:04:21.438180 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 10:04:21.441464 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 10:04:21.448383 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 10:04:21.451783 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 10:04:21.455123 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 10:04:21.458707 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 10:04:21.465316 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 10:04:21.468583 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 10:04:21.472075 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 10:04:21.478166 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 10:04:21.481625 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 10:04:21.485038 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 10:04:21.491942 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 10:04:21.495005 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 10:04:21.498631 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 10:04:21.504952 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
801 10:04:21.508190 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
802 10:04:21.511663 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 10:04:21.518259 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 10:04:21.521917 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 10:04:21.525110 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 10:04:21.531652 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 10:04:21.534776 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 10:04:21.538050 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
809 10:04:21.544824 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 10:04:21.547894 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 10:04:21.551417 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 10:04:21.558295 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 10:04:21.561523 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 10:04:21.564733 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 10:04:21.571539 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
816 10:04:21.574832 0 10 4 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
817 10:04:21.578119 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
818 10:04:21.584666 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 10:04:21.588103 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 10:04:21.591165 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 10:04:21.597761 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 10:04:21.601126 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 10:04:21.604531 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 10:04:21.611188 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
825 10:04:21.614535 0 11 8 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
826 10:04:21.618023 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
827 10:04:21.621196 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 10:04:21.628067 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 10:04:21.631365 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 10:04:21.634664 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 10:04:21.641495 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 10:04:21.644683 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 10:04:21.647994 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
834 10:04:21.654942 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 10:04:21.657805 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 10:04:21.661816 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 10:04:21.667897 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 10:04:21.671595 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 10:04:21.674408 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 10:04:21.681451 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 10:04:21.684701 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 10:04:21.687855 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 10:04:21.694839 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 10:04:21.697647 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 10:04:21.701322 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 10:04:21.707986 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 10:04:21.711262 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 10:04:21.714600 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
849 10:04:21.721620 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 10:04:21.722202 Total UI for P1: 0, mck2ui 16
851 10:04:21.724480 best dqsien dly found for B0: ( 0, 14, 4)
852 10:04:21.728235 Total UI for P1: 0, mck2ui 16
853 10:04:21.731495 best dqsien dly found for B1: ( 0, 14, 6)
854 10:04:21.735004 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
855 10:04:21.741290 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
856 10:04:21.741873
857 10:04:21.744721 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
858 10:04:21.747734 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
859 10:04:21.751542 [Gating] SW calibration Done
860 10:04:21.752133 ==
861 10:04:21.754927 Dram Type= 6, Freq= 0, CH_0, rank 0
862 10:04:21.757860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
863 10:04:21.758448 ==
864 10:04:21.758834 RX Vref Scan: 0
865 10:04:21.761414
866 10:04:21.762096 RX Vref 0 -> 0, step: 1
867 10:04:21.762490
868 10:04:21.764720 RX Delay -130 -> 252, step: 16
869 10:04:21.768270 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
870 10:04:21.771574 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
871 10:04:21.778018 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
872 10:04:21.781488 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
873 10:04:21.784660 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
874 10:04:21.788154 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
875 10:04:21.791314 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
876 10:04:21.797714 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
877 10:04:21.801173 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
878 10:04:21.804674 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
879 10:04:21.808077 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
880 10:04:21.811052 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
881 10:04:21.817991 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
882 10:04:21.821068 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
883 10:04:21.824699 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
884 10:04:21.828007 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
885 10:04:21.828596 ==
886 10:04:21.831189 Dram Type= 6, Freq= 0, CH_0, rank 0
887 10:04:21.837887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
888 10:04:21.838478 ==
889 10:04:21.838866 DQS Delay:
890 10:04:21.841200 DQS0 = 0, DQS1 = 0
891 10:04:21.841679 DQM Delay:
892 10:04:21.842059 DQM0 = 91, DQM1 = 80
893 10:04:21.844370 DQ Delay:
894 10:04:21.847659 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
895 10:04:21.851382 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =101
896 10:04:21.854367 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
897 10:04:21.857385 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
898 10:04:21.857863
899 10:04:21.858245
900 10:04:21.858595 ==
901 10:04:21.860826 Dram Type= 6, Freq= 0, CH_0, rank 0
902 10:04:21.864656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 10:04:21.865288 ==
904 10:04:21.865709
905 10:04:21.866185
906 10:04:21.867464 TX Vref Scan disable
907 10:04:21.871142 == TX Byte 0 ==
908 10:04:21.874186 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
909 10:04:21.878078 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
910 10:04:21.881150 == TX Byte 1 ==
911 10:04:21.884496 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
912 10:04:21.887652 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
913 10:04:21.888240 ==
914 10:04:21.891167 Dram Type= 6, Freq= 0, CH_0, rank 0
915 10:04:21.894018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 10:04:21.897722 ==
917 10:04:21.909416 TX Vref=22, minBit 11, minWin=26, winSum=438
918 10:04:21.912494 TX Vref=24, minBit 6, minWin=27, winSum=443
919 10:04:21.915958 TX Vref=26, minBit 10, minWin=27, winSum=449
920 10:04:21.919249 TX Vref=28, minBit 4, minWin=28, winSum=453
921 10:04:21.922760 TX Vref=30, minBit 10, minWin=27, winSum=454
922 10:04:21.929142 TX Vref=32, minBit 11, minWin=27, winSum=453
923 10:04:21.932917 [TxChooseVref] Worse bit 4, Min win 28, Win sum 453, Final Vref 28
924 10:04:21.933507
925 10:04:21.935781 Final TX Range 1 Vref 28
926 10:04:21.936263
927 10:04:21.936641 ==
928 10:04:21.939226 Dram Type= 6, Freq= 0, CH_0, rank 0
929 10:04:21.942721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 10:04:21.945888 ==
931 10:04:21.946365
932 10:04:21.946741
933 10:04:21.947092 TX Vref Scan disable
934 10:04:21.949479 == TX Byte 0 ==
935 10:04:21.952632 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
936 10:04:21.956345 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
937 10:04:21.959927 == TX Byte 1 ==
938 10:04:21.962922 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
939 10:04:21.969613 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
940 10:04:21.970187
941 10:04:21.970657 [DATLAT]
942 10:04:21.971021 Freq=800, CH0 RK0
943 10:04:21.971371
944 10:04:21.972717 DATLAT Default: 0xa
945 10:04:21.973218 0, 0xFFFF, sum = 0
946 10:04:21.976312 1, 0xFFFF, sum = 0
947 10:04:21.976989 2, 0xFFFF, sum = 0
948 10:04:21.979146 3, 0xFFFF, sum = 0
949 10:04:21.983213 4, 0xFFFF, sum = 0
950 10:04:21.983804 5, 0xFFFF, sum = 0
951 10:04:21.985858 6, 0xFFFF, sum = 0
952 10:04:21.986340 7, 0xFFFF, sum = 0
953 10:04:21.989057 8, 0xFFFF, sum = 0
954 10:04:21.989538 9, 0x0, sum = 1
955 10:04:21.992654 10, 0x0, sum = 2
956 10:04:21.993284 11, 0x0, sum = 3
957 10:04:21.993673 12, 0x0, sum = 4
958 10:04:21.996188 best_step = 10
959 10:04:21.996663
960 10:04:21.997093 ==
961 10:04:21.999181 Dram Type= 6, Freq= 0, CH_0, rank 0
962 10:04:22.002742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
963 10:04:22.003334 ==
964 10:04:22.006060 RX Vref Scan: 1
965 10:04:22.006647
966 10:04:22.009302 Set Vref Range= 32 -> 127
967 10:04:22.009781
968 10:04:22.010161 RX Vref 32 -> 127, step: 1
969 10:04:22.010517
970 10:04:22.012379 RX Delay -95 -> 252, step: 8
971 10:04:22.012884
972 10:04:22.016019 Set Vref, RX VrefLevel [Byte0]: 32
973 10:04:22.019374 [Byte1]: 32
974 10:04:22.020036
975 10:04:22.023046 Set Vref, RX VrefLevel [Byte0]: 33
976 10:04:22.025690 [Byte1]: 33
977 10:04:22.030023
978 10:04:22.030497 Set Vref, RX VrefLevel [Byte0]: 34
979 10:04:22.033023 [Byte1]: 34
980 10:04:22.037494
981 10:04:22.037966 Set Vref, RX VrefLevel [Byte0]: 35
982 10:04:22.041084 [Byte1]: 35
983 10:04:22.045336
984 10:04:22.045920 Set Vref, RX VrefLevel [Byte0]: 36
985 10:04:22.048084 [Byte1]: 36
986 10:04:22.052943
987 10:04:22.053516 Set Vref, RX VrefLevel [Byte0]: 37
988 10:04:22.055885 [Byte1]: 37
989 10:04:22.060468
990 10:04:22.061099 Set Vref, RX VrefLevel [Byte0]: 38
991 10:04:22.063969 [Byte1]: 38
992 10:04:22.068301
993 10:04:22.068823 Set Vref, RX VrefLevel [Byte0]: 39
994 10:04:22.071677 [Byte1]: 39
995 10:04:22.075472
996 10:04:22.076072 Set Vref, RX VrefLevel [Byte0]: 40
997 10:04:22.078872 [Byte1]: 40
998 10:04:22.083353
999 10:04:22.083932 Set Vref, RX VrefLevel [Byte0]: 41
1000 10:04:22.087536 [Byte1]: 41
1001 10:04:22.091169
1002 10:04:22.091788 Set Vref, RX VrefLevel [Byte0]: 42
1003 10:04:22.094323 [Byte1]: 42
1004 10:04:22.098334
1005 10:04:22.098848 Set Vref, RX VrefLevel [Byte0]: 43
1006 10:04:22.102318 [Byte1]: 43
1007 10:04:22.106396
1008 10:04:22.106990 Set Vref, RX VrefLevel [Byte0]: 44
1009 10:04:22.109487 [Byte1]: 44
1010 10:04:22.114256
1011 10:04:22.114729 Set Vref, RX VrefLevel [Byte0]: 45
1012 10:04:22.117201 [Byte1]: 45
1013 10:04:22.120971
1014 10:04:22.121445 Set Vref, RX VrefLevel [Byte0]: 46
1015 10:04:22.124505 [Byte1]: 46
1016 10:04:22.128642
1017 10:04:22.129278 Set Vref, RX VrefLevel [Byte0]: 47
1018 10:04:22.131985 [Byte1]: 47
1019 10:04:22.136426
1020 10:04:22.137057 Set Vref, RX VrefLevel [Byte0]: 48
1021 10:04:22.139771 [Byte1]: 48
1022 10:04:22.143909
1023 10:04:22.144489 Set Vref, RX VrefLevel [Byte0]: 49
1024 10:04:22.147424 [Byte1]: 49
1025 10:04:22.151924
1026 10:04:22.152500 Set Vref, RX VrefLevel [Byte0]: 50
1027 10:04:22.155101 [Byte1]: 50
1028 10:04:22.159564
1029 10:04:22.160163 Set Vref, RX VrefLevel [Byte0]: 51
1030 10:04:22.162643 [Byte1]: 51
1031 10:04:22.166591
1032 10:04:22.167170 Set Vref, RX VrefLevel [Byte0]: 52
1033 10:04:22.169894 [Byte1]: 52
1034 10:04:22.174370
1035 10:04:22.174942 Set Vref, RX VrefLevel [Byte0]: 53
1036 10:04:22.177319 [Byte1]: 53
1037 10:04:22.181906
1038 10:04:22.182477 Set Vref, RX VrefLevel [Byte0]: 54
1039 10:04:22.185038 [Byte1]: 54
1040 10:04:22.189318
1041 10:04:22.189904 Set Vref, RX VrefLevel [Byte0]: 55
1042 10:04:22.192657 [Byte1]: 55
1043 10:04:22.196986
1044 10:04:22.197460 Set Vref, RX VrefLevel [Byte0]: 56
1045 10:04:22.200153 [Byte1]: 56
1046 10:04:22.205005
1047 10:04:22.205577 Set Vref, RX VrefLevel [Byte0]: 57
1048 10:04:22.207839 [Byte1]: 57
1049 10:04:22.212384
1050 10:04:22.212993 Set Vref, RX VrefLevel [Byte0]: 58
1051 10:04:22.215449 [Byte1]: 58
1052 10:04:22.219776
1053 10:04:22.220262 Set Vref, RX VrefLevel [Byte0]: 59
1054 10:04:22.223077 [Byte1]: 59
1055 10:04:22.227635
1056 10:04:22.228205 Set Vref, RX VrefLevel [Byte0]: 60
1057 10:04:22.231145 [Byte1]: 60
1058 10:04:22.235462
1059 10:04:22.236033 Set Vref, RX VrefLevel [Byte0]: 61
1060 10:04:22.238396 [Byte1]: 61
1061 10:04:22.242947
1062 10:04:22.243521 Set Vref, RX VrefLevel [Byte0]: 62
1063 10:04:22.245800 [Byte1]: 62
1064 10:04:22.250353
1065 10:04:22.250924 Set Vref, RX VrefLevel [Byte0]: 63
1066 10:04:22.253618 [Byte1]: 63
1067 10:04:22.258119
1068 10:04:22.258683 Set Vref, RX VrefLevel [Byte0]: 64
1069 10:04:22.261180 [Byte1]: 64
1070 10:04:22.265803
1071 10:04:22.266374 Set Vref, RX VrefLevel [Byte0]: 65
1072 10:04:22.268653 [Byte1]: 65
1073 10:04:22.273180
1074 10:04:22.276223 Set Vref, RX VrefLevel [Byte0]: 66
1075 10:04:22.276827 [Byte1]: 66
1076 10:04:22.280760
1077 10:04:22.281361 Set Vref, RX VrefLevel [Byte0]: 67
1078 10:04:22.284006 [Byte1]: 67
1079 10:04:22.288613
1080 10:04:22.289219 Set Vref, RX VrefLevel [Byte0]: 68
1081 10:04:22.291407 [Byte1]: 68
1082 10:04:22.295874
1083 10:04:22.296445 Set Vref, RX VrefLevel [Byte0]: 69
1084 10:04:22.299536 [Byte1]: 69
1085 10:04:22.303699
1086 10:04:22.304272 Set Vref, RX VrefLevel [Byte0]: 70
1087 10:04:22.306867 [Byte1]: 70
1088 10:04:22.311016
1089 10:04:22.311586 Set Vref, RX VrefLevel [Byte0]: 71
1090 10:04:22.314186 [Byte1]: 71
1091 10:04:22.318715
1092 10:04:22.319330 Set Vref, RX VrefLevel [Byte0]: 72
1093 10:04:22.321793 [Byte1]: 72
1094 10:04:22.326221
1095 10:04:22.326793 Set Vref, RX VrefLevel [Byte0]: 73
1096 10:04:22.329628 [Byte1]: 73
1097 10:04:22.333765
1098 10:04:22.334311 Set Vref, RX VrefLevel [Byte0]: 74
1099 10:04:22.336844 [Byte1]: 74
1100 10:04:22.341112
1101 10:04:22.341584 Set Vref, RX VrefLevel [Byte0]: 75
1102 10:04:22.345071 [Byte1]: 75
1103 10:04:22.348832
1104 10:04:22.349361 Set Vref, RX VrefLevel [Byte0]: 76
1105 10:04:22.352861 [Byte1]: 76
1106 10:04:22.356948
1107 10:04:22.357525 Set Vref, RX VrefLevel [Byte0]: 77
1108 10:04:22.359910 [Byte1]: 77
1109 10:04:22.364454
1110 10:04:22.365071 Set Vref, RX VrefLevel [Byte0]: 78
1111 10:04:22.367476 [Byte1]: 78
1112 10:04:22.372060
1113 10:04:22.372655 Final RX Vref Byte 0 = 60 to rank0
1114 10:04:22.375341 Final RX Vref Byte 1 = 62 to rank0
1115 10:04:22.378585 Final RX Vref Byte 0 = 60 to rank1
1116 10:04:22.381840 Final RX Vref Byte 1 = 62 to rank1==
1117 10:04:22.385099 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 10:04:22.391844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 10:04:22.392426 ==
1120 10:04:22.392852 DQS Delay:
1121 10:04:22.395221 DQS0 = 0, DQS1 = 0
1122 10:04:22.395794 DQM Delay:
1123 10:04:22.396167 DQM0 = 93, DQM1 = 83
1124 10:04:22.397995 DQ Delay:
1125 10:04:22.401829 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1126 10:04:22.404730 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1127 10:04:22.407779 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1128 10:04:22.411595 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1129 10:04:22.412066
1130 10:04:22.412443
1131 10:04:22.417849 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1132 10:04:22.421278 CH0 RK0: MR19=606, MR18=3D38
1133 10:04:22.427929 CH0_RK0: MR19=0x606, MR18=0x3D38, DQSOSC=394, MR23=63, INC=95, DEC=63
1134 10:04:22.428405
1135 10:04:22.431075 ----->DramcWriteLeveling(PI) begin...
1136 10:04:22.431554 ==
1137 10:04:22.434491 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 10:04:22.438182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 10:04:22.438657 ==
1140 10:04:22.441461 Write leveling (Byte 0): 33 => 33
1141 10:04:22.444295 Write leveling (Byte 1): 30 => 30
1142 10:04:22.447799 DramcWriteLeveling(PI) end<-----
1143 10:04:22.448315
1144 10:04:22.448726 ==
1145 10:04:22.451082 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 10:04:22.454491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 10:04:22.455008 ==
1148 10:04:22.458111 [Gating] SW mode calibration
1149 10:04:22.464541 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 10:04:22.471276 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 10:04:22.474561 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 10:04:22.480605 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1153 10:04:22.483770 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1154 10:04:22.487674 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 10:04:22.531224 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 10:04:22.531746 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 10:04:22.531942 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 10:04:22.532205 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 10:04:22.532433 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 10:04:22.532604 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 10:04:22.532829 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 10:04:22.533002 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 10:04:22.533396 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 10:04:22.533569 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 10:04:22.562579 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 10:04:22.563446 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 10:04:22.563840 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 10:04:22.564194 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 10:04:22.564590 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1170 10:04:22.565198 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 10:04:22.566438 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 10:04:22.569567 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 10:04:22.573191 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 10:04:22.575817 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 10:04:22.579165 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 10:04:22.586082 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 10:04:22.589300 0 9 8 | B1->B0 | 2c2c 3434 | 1 0 | (1 1) (0 0)
1178 10:04:22.593088 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 10:04:22.599510 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 10:04:22.602653 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 10:04:22.605950 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 10:04:22.609317 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 10:04:22.616298 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 10:04:22.619731 0 10 4 | B1->B0 | 3434 2e2e | 1 1 | (0 0) (1 0)
1185 10:04:22.622610 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1186 10:04:22.629573 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 10:04:22.632506 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 10:04:22.636246 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 10:04:22.642516 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 10:04:22.645669 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 10:04:22.649369 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 10:04:22.656057 0 11 4 | B1->B0 | 2828 2f2f | 0 0 | (0 0) (0 0)
1193 10:04:22.659036 0 11 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1194 10:04:22.662365 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 10:04:22.669918 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 10:04:22.673122 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 10:04:22.677422 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 10:04:22.681020 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 10:04:22.683935 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 10:04:22.691152 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 10:04:22.695221 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 10:04:22.697802 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 10:04:22.704641 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 10:04:22.707726 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 10:04:22.711579 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 10:04:22.717962 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 10:04:22.721492 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 10:04:22.724542 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 10:04:22.731394 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 10:04:22.735300 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 10:04:22.738115 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 10:04:22.741580 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 10:04:22.748289 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 10:04:22.751689 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 10:04:22.754971 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 10:04:22.762027 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1217 10:04:22.764843 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 10:04:22.768639 Total UI for P1: 0, mck2ui 16
1219 10:04:22.771864 best dqsien dly found for B0: ( 0, 14, 4)
1220 10:04:22.775029 Total UI for P1: 0, mck2ui 16
1221 10:04:22.778142 best dqsien dly found for B1: ( 0, 14, 6)
1222 10:04:22.781474 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1223 10:04:22.784515 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1224 10:04:22.784597
1225 10:04:22.788447 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1226 10:04:22.791089 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1227 10:04:22.794206 [Gating] SW calibration Done
1228 10:04:22.794290 ==
1229 10:04:22.797452 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 10:04:22.804129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 10:04:22.804248 ==
1232 10:04:22.804349 RX Vref Scan: 0
1233 10:04:22.804444
1234 10:04:22.807838 RX Vref 0 -> 0, step: 1
1235 10:04:22.807934
1236 10:04:22.810972 RX Delay -130 -> 252, step: 16
1237 10:04:22.814195 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1238 10:04:22.817408 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1239 10:04:22.820758 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1240 10:04:22.823962 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1241 10:04:22.830908 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1242 10:04:22.834277 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1243 10:04:22.837691 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1244 10:04:22.840595 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1245 10:04:22.843952 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1246 10:04:22.850479 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1247 10:04:22.854218 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1248 10:04:22.857212 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1249 10:04:22.860714 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1250 10:04:22.867741 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1251 10:04:22.871322 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1252 10:04:22.874788 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1253 10:04:22.875354 ==
1254 10:04:22.878209 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 10:04:22.881111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 10:04:22.881582 ==
1257 10:04:22.884545 DQS Delay:
1258 10:04:22.885153 DQS0 = 0, DQS1 = 0
1259 10:04:22.887941 DQM Delay:
1260 10:04:22.888508 DQM0 = 89, DQM1 = 80
1261 10:04:22.888929 DQ Delay:
1262 10:04:22.891061 DQ0 =85, DQ1 =93, DQ2 =93, DQ3 =77
1263 10:04:22.894295 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1264 10:04:22.897158 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1265 10:04:22.900340 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
1266 10:04:22.900867
1267 10:04:22.901248
1268 10:04:22.904128 ==
1269 10:04:22.904591 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 10:04:22.910773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 10:04:22.911448 ==
1272 10:04:22.912051
1273 10:04:22.912628
1274 10:04:22.913572 TX Vref Scan disable
1275 10:04:22.914161 == TX Byte 0 ==
1276 10:04:22.917388 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1277 10:04:22.924204 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1278 10:04:22.924918 == TX Byte 1 ==
1279 10:04:22.927000 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1280 10:04:22.933879 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1281 10:04:22.934526 ==
1282 10:04:22.937505 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 10:04:22.940130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 10:04:22.940605 ==
1285 10:04:22.953759 TX Vref=22, minBit 3, minWin=27, winSum=444
1286 10:04:22.957166 TX Vref=24, minBit 8, minWin=27, winSum=448
1287 10:04:22.960652 TX Vref=26, minBit 8, minWin=27, winSum=450
1288 10:04:22.963979 TX Vref=28, minBit 8, minWin=27, winSum=453
1289 10:04:22.967341 TX Vref=30, minBit 8, minWin=27, winSum=453
1290 10:04:22.974172 TX Vref=32, minBit 8, minWin=27, winSum=454
1291 10:04:22.977344 [TxChooseVref] Worse bit 8, Min win 27, Win sum 454, Final Vref 32
1292 10:04:22.977884
1293 10:04:22.980706 Final TX Range 1 Vref 32
1294 10:04:22.981248
1295 10:04:22.981666 ==
1296 10:04:22.984333 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 10:04:22.987017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 10:04:22.987569 ==
1299 10:04:22.990451
1300 10:04:22.991043
1301 10:04:22.991539 TX Vref Scan disable
1302 10:04:22.994291 == TX Byte 0 ==
1303 10:04:22.997385 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1304 10:04:23.004112 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1305 10:04:23.004404 == TX Byte 1 ==
1306 10:04:23.007501 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1307 10:04:23.013689 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1308 10:04:23.013981
1309 10:04:23.014210 [DATLAT]
1310 10:04:23.014425 Freq=800, CH0 RK1
1311 10:04:23.014633
1312 10:04:23.017103 DATLAT Default: 0xa
1313 10:04:23.017459 0, 0xFFFF, sum = 0
1314 10:04:23.020511 1, 0xFFFF, sum = 0
1315 10:04:23.020939 2, 0xFFFF, sum = 0
1316 10:04:23.023644 3, 0xFFFF, sum = 0
1317 10:04:23.026887 4, 0xFFFF, sum = 0
1318 10:04:23.027202 5, 0xFFFF, sum = 0
1319 10:04:23.029927 6, 0xFFFF, sum = 0
1320 10:04:23.030230 7, 0xFFFF, sum = 0
1321 10:04:23.033435 8, 0xFFFF, sum = 0
1322 10:04:23.033745 9, 0x0, sum = 1
1323 10:04:23.037063 10, 0x0, sum = 2
1324 10:04:23.037366 11, 0x0, sum = 3
1325 10:04:23.037606 12, 0x0, sum = 4
1326 10:04:23.040245 best_step = 10
1327 10:04:23.040468
1328 10:04:23.040644 ==
1329 10:04:23.043499 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 10:04:23.046661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 10:04:23.046860 ==
1332 10:04:23.050316 RX Vref Scan: 0
1333 10:04:23.050478
1334 10:04:23.053058 RX Vref 0 -> 0, step: 1
1335 10:04:23.053211
1336 10:04:23.053363 RX Delay -79 -> 252, step: 8
1337 10:04:23.060635 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1338 10:04:23.063549 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1339 10:04:23.066950 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1340 10:04:23.070263 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1341 10:04:23.073679 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1342 10:04:23.080475 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1343 10:04:23.083715 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1344 10:04:23.086737 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1345 10:04:23.090309 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1346 10:04:23.093371 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1347 10:04:23.100255 iDelay=209, Bit 10, Center 84 (-15 ~ 184) 200
1348 10:04:23.103458 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1349 10:04:23.106800 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1350 10:04:23.110086 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1351 10:04:23.116847 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1352 10:04:23.120087 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1353 10:04:23.120238 ==
1354 10:04:23.123538 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 10:04:23.126651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 10:04:23.126802 ==
1357 10:04:23.130183 DQS Delay:
1358 10:04:23.130354 DQS0 = 0, DQS1 = 0
1359 10:04:23.130491 DQM Delay:
1360 10:04:23.133413 DQM0 = 90, DQM1 = 82
1361 10:04:23.133585 DQ Delay:
1362 10:04:23.136424 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1363 10:04:23.139986 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1364 10:04:23.143161 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1365 10:04:23.146510 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1366 10:04:23.146716
1367 10:04:23.146879
1368 10:04:23.156748 [DQSOSCAuto] RK1, (LSB)MR18= 0x461f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1369 10:04:23.156970 CH0 RK1: MR19=606, MR18=461F
1370 10:04:23.163364 CH0_RK1: MR19=0x606, MR18=0x461F, DQSOSC=392, MR23=63, INC=96, DEC=64
1371 10:04:23.166815 [RxdqsGatingPostProcess] freq 800
1372 10:04:23.173179 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 10:04:23.176458 Pre-setting of DQS Precalculation
1374 10:04:23.179406 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1375 10:04:23.179490 ==
1376 10:04:23.182912 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 10:04:23.189836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 10:04:23.189920 ==
1379 10:04:23.193072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 10:04:23.199555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 10:04:23.208875 [CA 0] Center 36 (6~67) winsize 62
1382 10:04:23.212176 [CA 1] Center 36 (6~67) winsize 62
1383 10:04:23.215633 [CA 2] Center 34 (4~65) winsize 62
1384 10:04:23.218958 [CA 3] Center 34 (4~65) winsize 62
1385 10:04:23.222277 [CA 4] Center 34 (4~65) winsize 62
1386 10:04:23.225684 [CA 5] Center 34 (3~65) winsize 63
1387 10:04:23.225767
1388 10:04:23.228891 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1389 10:04:23.228975
1390 10:04:23.231717 [CATrainingPosCal] consider 1 rank data
1391 10:04:23.235298 u2DelayCellTimex100 = 270/100 ps
1392 10:04:23.238742 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1393 10:04:23.241795 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1394 10:04:23.248537 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1395 10:04:23.252171 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1396 10:04:23.255309 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1397 10:04:23.258362 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1398 10:04:23.258445
1399 10:04:23.261481 CA PerBit enable=1, Macro0, CA PI delay=34
1400 10:04:23.261565
1401 10:04:23.264858 [CBTSetCACLKResult] CA Dly = 34
1402 10:04:23.264942 CS Dly: 5 (0~36)
1403 10:04:23.268297 ==
1404 10:04:23.271575 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 10:04:23.274884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 10:04:23.274968 ==
1407 10:04:23.281500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 10:04:23.284758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 10:04:23.294827 [CA 0] Center 37 (7~67) winsize 61
1410 10:04:23.298354 [CA 1] Center 37 (6~68) winsize 63
1411 10:04:23.301902 [CA 2] Center 35 (5~66) winsize 62
1412 10:04:23.305202 [CA 3] Center 34 (4~65) winsize 62
1413 10:04:23.308434 [CA 4] Center 34 (4~65) winsize 62
1414 10:04:23.312111 [CA 5] Center 34 (4~65) winsize 62
1415 10:04:23.312237
1416 10:04:23.315066 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1417 10:04:23.315204
1418 10:04:23.318118 [CATrainingPosCal] consider 2 rank data
1419 10:04:23.321667 u2DelayCellTimex100 = 270/100 ps
1420 10:04:23.324906 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1421 10:04:23.331870 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1422 10:04:23.335699 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1423 10:04:23.338846 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 10:04:23.342442 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 10:04:23.346375 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 10:04:23.346459
1427 10:04:23.350000 CA PerBit enable=1, Macro0, CA PI delay=34
1428 10:04:23.350084
1429 10:04:23.350151 [CBTSetCACLKResult] CA Dly = 34
1430 10:04:23.353434 CS Dly: 6 (0~38)
1431 10:04:23.353517
1432 10:04:23.357219 ----->DramcWriteLeveling(PI) begin...
1433 10:04:23.357310 ==
1434 10:04:23.360762 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 10:04:23.364470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 10:04:23.364576 ==
1437 10:04:23.368040 Write leveling (Byte 0): 24 => 24
1438 10:04:23.371631 Write leveling (Byte 1): 29 => 29
1439 10:04:23.374825 DramcWriteLeveling(PI) end<-----
1440 10:04:23.374950
1441 10:04:23.375049 ==
1442 10:04:23.378514 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 10:04:23.381462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 10:04:23.381601 ==
1445 10:04:23.384944 [Gating] SW mode calibration
1446 10:04:23.391172 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 10:04:23.397902 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 10:04:23.401810 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 10:04:23.404903 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1450 10:04:23.407974 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1451 10:04:23.414832 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 10:04:23.418219 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 10:04:23.421519 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 10:04:23.427763 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 10:04:23.431207 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 10:04:23.434737 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 10:04:23.441388 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 10:04:23.444456 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 10:04:23.447634 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 10:04:23.454639 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 10:04:23.457794 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 10:04:23.461101 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 10:04:23.467711 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 10:04:23.470976 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 10:04:23.474351 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1466 10:04:23.481325 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 10:04:23.484253 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 10:04:23.487707 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 10:04:23.494328 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 10:04:23.498060 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 10:04:23.500725 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 10:04:23.507256 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 10:04:23.510859 0 9 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1474 10:04:23.514005 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1475 10:04:23.520934 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 10:04:23.524341 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 10:04:23.527321 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 10:04:23.534330 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 10:04:23.537542 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 10:04:23.540813 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1481 10:04:23.544350 0 10 4 | B1->B0 | 3030 2a2a | 0 0 | (0 1) (1 0)
1482 10:04:23.550777 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1483 10:04:23.554211 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 10:04:23.557539 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 10:04:23.563965 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 10:04:23.568253 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 10:04:23.570943 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 10:04:23.577361 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 10:04:23.580898 0 11 4 | B1->B0 | 2e2e 3939 | 0 0 | (0 0) (0 0)
1490 10:04:23.584389 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1491 10:04:23.590859 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 10:04:23.594200 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 10:04:23.597424 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 10:04:23.604037 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 10:04:23.607981 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 10:04:23.611129 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 10:04:23.617241 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 10:04:23.620900 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 10:04:23.624045 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 10:04:23.630477 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 10:04:23.633984 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 10:04:23.637371 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 10:04:23.641121 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 10:04:23.647663 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 10:04:23.650716 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 10:04:23.654287 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 10:04:23.660600 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 10:04:23.664238 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 10:04:23.667019 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 10:04:23.674309 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 10:04:23.677545 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 10:04:23.681009 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1513 10:04:23.687288 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1514 10:04:23.690942 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1515 10:04:23.693992 Total UI for P1: 0, mck2ui 16
1516 10:04:23.697438 best dqsien dly found for B0: ( 0, 14, 2)
1517 10:04:23.700634 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 10:04:23.704346 Total UI for P1: 0, mck2ui 16
1519 10:04:23.707185 best dqsien dly found for B1: ( 0, 14, 6)
1520 10:04:23.710510 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1521 10:04:23.714294 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1522 10:04:23.714882
1523 10:04:23.720616 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1524 10:04:23.723980 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 10:04:23.724448 [Gating] SW calibration Done
1526 10:04:23.727575 ==
1527 10:04:23.730789 Dram Type= 6, Freq= 0, CH_1, rank 0
1528 10:04:23.734511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1529 10:04:23.735041 ==
1530 10:04:23.735378 RX Vref Scan: 0
1531 10:04:23.735693
1532 10:04:23.737444 RX Vref 0 -> 0, step: 1
1533 10:04:23.737892
1534 10:04:23.740842 RX Delay -130 -> 252, step: 16
1535 10:04:23.743989 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1536 10:04:23.747553 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1537 10:04:23.754000 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1538 10:04:23.757054 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1539 10:04:23.761015 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1540 10:04:23.764082 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1541 10:04:23.766713 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1542 10:04:23.770353 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1543 10:04:23.776966 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1544 10:04:23.780019 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1545 10:04:23.783409 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1546 10:04:23.786639 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1547 10:04:23.793455 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1548 10:04:23.796913 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1549 10:04:23.800322 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1550 10:04:23.803351 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1551 10:04:23.803468 ==
1552 10:04:23.806945 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 10:04:23.813416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 10:04:23.813520 ==
1555 10:04:23.813602 DQS Delay:
1556 10:04:23.813677 DQS0 = 0, DQS1 = 0
1557 10:04:23.816761 DQM Delay:
1558 10:04:23.816959 DQM0 = 91, DQM1 = 80
1559 10:04:23.820277 DQ Delay:
1560 10:04:23.823263 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1561 10:04:23.826656 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =93
1562 10:04:23.829927 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1563 10:04:23.833318 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1564 10:04:23.833492
1565 10:04:23.833617
1566 10:04:23.833750 ==
1567 10:04:23.836783 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 10:04:23.840133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 10:04:23.840428 ==
1570 10:04:23.840623
1571 10:04:23.840881
1572 10:04:23.843612 TX Vref Scan disable
1573 10:04:23.843858 == TX Byte 0 ==
1574 10:04:23.849931 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1575 10:04:23.853225 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1576 10:04:23.853578 == TX Byte 1 ==
1577 10:04:23.860160 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1578 10:04:23.863368 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1579 10:04:23.863833 ==
1580 10:04:23.866948 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 10:04:23.870153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 10:04:23.870623 ==
1583 10:04:23.884568 TX Vref=22, minBit 10, minWin=27, winSum=448
1584 10:04:23.887750 TX Vref=24, minBit 15, minWin=27, winSum=453
1585 10:04:23.891002 TX Vref=26, minBit 15, minWin=27, winSum=456
1586 10:04:23.894616 TX Vref=28, minBit 15, minWin=27, winSum=459
1587 10:04:23.897654 TX Vref=30, minBit 15, minWin=27, winSum=459
1588 10:04:23.904241 TX Vref=32, minBit 8, minWin=28, winSum=458
1589 10:04:23.907711 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
1590 10:04:23.908181
1591 10:04:23.911035 Final TX Range 1 Vref 32
1592 10:04:23.911504
1593 10:04:23.911872 ==
1594 10:04:23.914747 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 10:04:23.918444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 10:04:23.918871 ==
1597 10:04:23.919240
1598 10:04:23.919612
1599 10:04:23.921872 TX Vref Scan disable
1600 10:04:23.924833 == TX Byte 0 ==
1601 10:04:23.928184 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1602 10:04:23.931527 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1603 10:04:23.935352 == TX Byte 1 ==
1604 10:04:23.937999 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1605 10:04:23.944824 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1606 10:04:23.945406
1607 10:04:23.945944 [DATLAT]
1608 10:04:23.946471 Freq=800, CH1 RK0
1609 10:04:23.947004
1610 10:04:23.947971 DATLAT Default: 0xa
1611 10:04:23.948495 0, 0xFFFF, sum = 0
1612 10:04:23.951414 1, 0xFFFF, sum = 0
1613 10:04:23.951955 2, 0xFFFF, sum = 0
1614 10:04:23.954789 3, 0xFFFF, sum = 0
1615 10:04:23.955380 4, 0xFFFF, sum = 0
1616 10:04:23.957913 5, 0xFFFF, sum = 0
1617 10:04:23.961394 6, 0xFFFF, sum = 0
1618 10:04:23.961991 7, 0xFFFF, sum = 0
1619 10:04:23.964453 8, 0xFFFF, sum = 0
1620 10:04:23.965087 9, 0x0, sum = 1
1621 10:04:23.965648 10, 0x0, sum = 2
1622 10:04:23.968345 11, 0x0, sum = 3
1623 10:04:23.968804 12, 0x0, sum = 4
1624 10:04:23.971222 best_step = 10
1625 10:04:23.971820
1626 10:04:23.972353 ==
1627 10:04:23.974606 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 10:04:23.978135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 10:04:23.978723 ==
1630 10:04:23.981126 RX Vref Scan: 1
1631 10:04:23.981665
1632 10:04:23.984810 Set Vref Range= 32 -> 127
1633 10:04:23.985235
1634 10:04:23.985573 RX Vref 32 -> 127, step: 1
1635 10:04:23.985890
1636 10:04:23.988128 RX Delay -95 -> 252, step: 8
1637 10:04:23.988704
1638 10:04:23.991552 Set Vref, RX VrefLevel [Byte0]: 32
1639 10:04:23.994559 [Byte1]: 32
1640 10:04:23.994949
1641 10:04:23.997712 Set Vref, RX VrefLevel [Byte0]: 33
1642 10:04:24.000945 [Byte1]: 33
1643 10:04:24.005060
1644 10:04:24.005286 Set Vref, RX VrefLevel [Byte0]: 34
1645 10:04:24.008664 [Byte1]: 34
1646 10:04:24.012471
1647 10:04:24.012718 Set Vref, RX VrefLevel [Byte0]: 35
1648 10:04:24.015811 [Byte1]: 35
1649 10:04:24.020570
1650 10:04:24.020929 Set Vref, RX VrefLevel [Byte0]: 36
1651 10:04:24.023624 [Byte1]: 36
1652 10:04:24.027840
1653 10:04:24.028067 Set Vref, RX VrefLevel [Byte0]: 37
1654 10:04:24.031149 [Byte1]: 37
1655 10:04:24.035336
1656 10:04:24.035706 Set Vref, RX VrefLevel [Byte0]: 38
1657 10:04:24.039010 [Byte1]: 38
1658 10:04:24.043011
1659 10:04:24.043463 Set Vref, RX VrefLevel [Byte0]: 39
1660 10:04:24.046399 [Byte1]: 39
1661 10:04:24.051285
1662 10:04:24.051805 Set Vref, RX VrefLevel [Byte0]: 40
1663 10:04:24.054239 [Byte1]: 40
1664 10:04:24.058734
1665 10:04:24.059301 Set Vref, RX VrefLevel [Byte0]: 41
1666 10:04:24.061840 [Byte1]: 41
1667 10:04:24.066239
1668 10:04:24.066789 Set Vref, RX VrefLevel [Byte0]: 42
1669 10:04:24.069523 [Byte1]: 42
1670 10:04:24.073670
1671 10:04:24.074223 Set Vref, RX VrefLevel [Byte0]: 43
1672 10:04:24.076854 [Byte1]: 43
1673 10:04:24.081376
1674 10:04:24.081943 Set Vref, RX VrefLevel [Byte0]: 44
1675 10:04:24.084601 [Byte1]: 44
1676 10:04:24.089082
1677 10:04:24.089612 Set Vref, RX VrefLevel [Byte0]: 45
1678 10:04:24.092018 [Byte1]: 45
1679 10:04:24.096256
1680 10:04:24.096824 Set Vref, RX VrefLevel [Byte0]: 46
1681 10:04:24.099849 [Byte1]: 46
1682 10:04:24.104411
1683 10:04:24.104944 Set Vref, RX VrefLevel [Byte0]: 47
1684 10:04:24.107841 [Byte1]: 47
1685 10:04:24.111922
1686 10:04:24.112485 Set Vref, RX VrefLevel [Byte0]: 48
1687 10:04:24.115118 [Byte1]: 48
1688 10:04:24.119306
1689 10:04:24.122579 Set Vref, RX VrefLevel [Byte0]: 49
1690 10:04:24.125501 [Byte1]: 49
1691 10:04:24.125967
1692 10:04:24.128734 Set Vref, RX VrefLevel [Byte0]: 50
1693 10:04:24.132663 [Byte1]: 50
1694 10:04:24.133240
1695 10:04:24.135572 Set Vref, RX VrefLevel [Byte0]: 51
1696 10:04:24.138823 [Byte1]: 51
1697 10:04:24.139284
1698 10:04:24.142738 Set Vref, RX VrefLevel [Byte0]: 52
1699 10:04:24.145542 [Byte1]: 52
1700 10:04:24.149420
1701 10:04:24.149954 Set Vref, RX VrefLevel [Byte0]: 53
1702 10:04:24.153025 [Byte1]: 53
1703 10:04:24.157313
1704 10:04:24.157772 Set Vref, RX VrefLevel [Byte0]: 54
1705 10:04:24.160809 [Byte1]: 54
1706 10:04:24.165123
1707 10:04:24.165651 Set Vref, RX VrefLevel [Byte0]: 55
1708 10:04:24.168030 [Byte1]: 55
1709 10:04:24.172486
1710 10:04:24.172979 Set Vref, RX VrefLevel [Byte0]: 56
1711 10:04:24.176015 [Byte1]: 56
1712 10:04:24.180182
1713 10:04:24.180749 Set Vref, RX VrefLevel [Byte0]: 57
1714 10:04:24.183333 [Byte1]: 57
1715 10:04:24.187821
1716 10:04:24.188382 Set Vref, RX VrefLevel [Byte0]: 58
1717 10:04:24.190997 [Byte1]: 58
1718 10:04:24.195640
1719 10:04:24.196169 Set Vref, RX VrefLevel [Byte0]: 59
1720 10:04:24.198596 [Byte1]: 59
1721 10:04:24.202760
1722 10:04:24.203247 Set Vref, RX VrefLevel [Byte0]: 60
1723 10:04:24.206090 [Byte1]: 60
1724 10:04:24.210796
1725 10:04:24.211481 Set Vref, RX VrefLevel [Byte0]: 61
1726 10:04:24.213663 [Byte1]: 61
1727 10:04:24.217868
1728 10:04:24.218404 Set Vref, RX VrefLevel [Byte0]: 62
1729 10:04:24.221279 [Byte1]: 62
1730 10:04:24.225473
1731 10:04:24.226136 Set Vref, RX VrefLevel [Byte0]: 63
1732 10:04:24.228721 [Byte1]: 63
1733 10:04:24.233202
1734 10:04:24.233665 Set Vref, RX VrefLevel [Byte0]: 64
1735 10:04:24.236345 [Byte1]: 64
1736 10:04:24.240708
1737 10:04:24.241220 Set Vref, RX VrefLevel [Byte0]: 65
1738 10:04:24.243917 [Byte1]: 65
1739 10:04:24.248385
1740 10:04:24.248875 Set Vref, RX VrefLevel [Byte0]: 66
1741 10:04:24.251464 [Byte1]: 66
1742 10:04:24.255922
1743 10:04:24.256388 Set Vref, RX VrefLevel [Byte0]: 67
1744 10:04:24.259285 [Byte1]: 67
1745 10:04:24.263501
1746 10:04:24.263968 Set Vref, RX VrefLevel [Byte0]: 68
1747 10:04:24.266728 [Byte1]: 68
1748 10:04:24.271118
1749 10:04:24.271745 Set Vref, RX VrefLevel [Byte0]: 69
1750 10:04:24.274034 [Byte1]: 69
1751 10:04:24.278779
1752 10:04:24.279412 Set Vref, RX VrefLevel [Byte0]: 70
1753 10:04:24.281798 [Byte1]: 70
1754 10:04:24.286625
1755 10:04:24.287220 Set Vref, RX VrefLevel [Byte0]: 71
1756 10:04:24.289659 [Byte1]: 71
1757 10:04:24.293556
1758 10:04:24.294113 Set Vref, RX VrefLevel [Byte0]: 72
1759 10:04:24.297155 [Byte1]: 72
1760 10:04:24.301060
1761 10:04:24.301151 Set Vref, RX VrefLevel [Byte0]: 73
1762 10:04:24.304307 [Byte1]: 73
1763 10:04:24.308686
1764 10:04:24.308833 Set Vref, RX VrefLevel [Byte0]: 74
1765 10:04:24.311885 [Byte1]: 74
1766 10:04:24.316522
1767 10:04:24.316658 Set Vref, RX VrefLevel [Byte0]: 75
1768 10:04:24.319605 [Byte1]: 75
1769 10:04:24.323793
1770 10:04:24.323897 Set Vref, RX VrefLevel [Byte0]: 76
1771 10:04:24.327294 [Byte1]: 76
1772 10:04:24.331314
1773 10:04:24.331426 Set Vref, RX VrefLevel [Byte0]: 77
1774 10:04:24.334894 [Byte1]: 77
1775 10:04:24.339069
1776 10:04:24.339181 Final RX Vref Byte 0 = 52 to rank0
1777 10:04:24.342468 Final RX Vref Byte 1 = 63 to rank0
1778 10:04:24.345516 Final RX Vref Byte 0 = 52 to rank1
1779 10:04:24.349021 Final RX Vref Byte 1 = 63 to rank1==
1780 10:04:24.352355 Dram Type= 6, Freq= 0, CH_1, rank 0
1781 10:04:24.358886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 10:04:24.358991 ==
1783 10:04:24.359074 DQS Delay:
1784 10:04:24.359150 DQS0 = 0, DQS1 = 0
1785 10:04:24.362171 DQM Delay:
1786 10:04:24.362274 DQM0 = 93, DQM1 = 83
1787 10:04:24.366235 DQ Delay:
1788 10:04:24.368936 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1789 10:04:24.372506 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1790 10:04:24.376002 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1791 10:04:24.379140 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1792 10:04:24.379293
1793 10:04:24.379413
1794 10:04:24.385608 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1795 10:04:24.389328 CH1 RK0: MR19=606, MR18=2B48
1796 10:04:24.396024 CH1_RK0: MR19=0x606, MR18=0x2B48, DQSOSC=391, MR23=63, INC=96, DEC=64
1797 10:04:24.396454
1798 10:04:24.399166 ----->DramcWriteLeveling(PI) begin...
1799 10:04:24.399602 ==
1800 10:04:24.402810 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 10:04:24.406110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 10:04:24.406539 ==
1803 10:04:24.409287 Write leveling (Byte 0): 27 => 27
1804 10:04:24.412566 Write leveling (Byte 1): 29 => 29
1805 10:04:24.415625 DramcWriteLeveling(PI) end<-----
1806 10:04:24.416169
1807 10:04:24.416551 ==
1808 10:04:24.419556 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 10:04:24.422810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 10:04:24.423380 ==
1811 10:04:24.425816 [Gating] SW mode calibration
1812 10:04:24.432601 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1813 10:04:24.438915 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1814 10:04:24.442503 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1815 10:04:24.448877 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1816 10:04:24.452707 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 10:04:24.455570 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 10:04:24.458872 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 10:04:24.465619 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 10:04:24.468864 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 10:04:24.472198 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 10:04:24.478495 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 10:04:24.481987 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 10:04:24.485368 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 10:04:24.492180 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 10:04:24.495441 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 10:04:24.498736 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 10:04:24.504817 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 10:04:24.508352 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 10:04:24.511278 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 10:04:24.518281 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1832 10:04:24.521333 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1833 10:04:24.524756 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 10:04:24.531615 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 10:04:24.534685 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 10:04:24.538038 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 10:04:24.544925 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 10:04:24.547900 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 10:04:24.551583 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1840 10:04:24.558095 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 10:04:24.561283 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 10:04:24.564510 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 10:04:24.571588 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 10:04:24.574823 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 10:04:24.578423 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 10:04:24.584730 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1847 10:04:24.587812 0 10 4 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (1 0)
1848 10:04:24.591455 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 10:04:24.597820 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 10:04:24.601209 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 10:04:24.604317 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 10:04:24.611035 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 10:04:24.615026 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 10:04:24.617690 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 10:04:24.624437 0 11 4 | B1->B0 | 3838 3030 | 0 0 | (0 0) (0 0)
1856 10:04:24.628094 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1857 10:04:24.631353 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 10:04:24.635048 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 10:04:24.641118 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 10:04:24.644446 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 10:04:24.647811 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 10:04:24.655035 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 10:04:24.658052 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1864 10:04:24.661041 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1865 10:04:24.668023 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 10:04:24.671346 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 10:04:24.674670 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 10:04:24.681157 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 10:04:24.684683 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 10:04:24.687544 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 10:04:24.694233 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 10:04:24.697731 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 10:04:24.701134 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 10:04:24.707531 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 10:04:24.711039 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 10:04:24.714682 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 10:04:24.721064 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 10:04:24.724505 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 10:04:24.727778 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1880 10:04:24.734606 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 10:04:24.735041 Total UI for P1: 0, mck2ui 16
1882 10:04:24.740833 best dqsien dly found for B0: ( 0, 14, 4)
1883 10:04:24.741264 Total UI for P1: 0, mck2ui 16
1884 10:04:24.744737 best dqsien dly found for B1: ( 0, 14, 4)
1885 10:04:24.750977 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1886 10:04:24.754179 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1887 10:04:24.754606
1888 10:04:24.757541 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1889 10:04:24.760857 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1890 10:04:24.764099 [Gating] SW calibration Done
1891 10:04:24.764659 ==
1892 10:04:24.767407 Dram Type= 6, Freq= 0, CH_1, rank 1
1893 10:04:24.770785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1894 10:04:24.771256 ==
1895 10:04:24.773947 RX Vref Scan: 0
1896 10:04:24.774458
1897 10:04:24.774858 RX Vref 0 -> 0, step: 1
1898 10:04:24.775255
1899 10:04:24.777345 RX Delay -130 -> 252, step: 16
1900 10:04:24.781034 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1901 10:04:24.787543 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1902 10:04:24.790550 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1903 10:04:24.793929 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1904 10:04:24.797307 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1905 10:04:24.800624 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1906 10:04:24.804034 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1907 10:04:24.810735 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1908 10:04:24.814043 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1909 10:04:24.817356 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1910 10:04:24.820420 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1911 10:04:24.827027 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1912 10:04:24.830222 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1913 10:04:24.833765 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1914 10:04:24.837187 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1915 10:04:24.840467 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1916 10:04:24.843553 ==
1917 10:04:24.846784 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 10:04:24.850142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 10:04:24.850572 ==
1920 10:04:24.850910 DQS Delay:
1921 10:04:24.853821 DQS0 = 0, DQS1 = 0
1922 10:04:24.854260 DQM Delay:
1923 10:04:24.856848 DQM0 = 91, DQM1 = 83
1924 10:04:24.857269 DQ Delay:
1925 10:04:24.860416 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1926 10:04:24.863578 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1927 10:04:24.867237 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1928 10:04:24.870493 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1929 10:04:24.870916
1930 10:04:24.871250
1931 10:04:24.871562 ==
1932 10:04:24.873415 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 10:04:24.877040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 10:04:24.877566 ==
1935 10:04:24.877905
1936 10:04:24.878216
1937 10:04:24.879920 TX Vref Scan disable
1938 10:04:24.883901 == TX Byte 0 ==
1939 10:04:24.886705 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1940 10:04:24.889760 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1941 10:04:24.893291 == TX Byte 1 ==
1942 10:04:24.897200 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1943 10:04:24.899830 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1944 10:04:24.900281 ==
1945 10:04:24.903671 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 10:04:24.910288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 10:04:24.910714 ==
1948 10:04:24.921256 TX Vref=22, minBit 13, minWin=27, winSum=451
1949 10:04:24.924951 TX Vref=24, minBit 13, minWin=27, winSum=455
1950 10:04:24.928057 TX Vref=26, minBit 3, minWin=28, winSum=459
1951 10:04:24.931430 TX Vref=28, minBit 13, minWin=27, winSum=457
1952 10:04:24.934794 TX Vref=30, minBit 9, minWin=27, winSum=457
1953 10:04:24.941672 TX Vref=32, minBit 9, minWin=27, winSum=456
1954 10:04:24.944603 [TxChooseVref] Worse bit 3, Min win 28, Win sum 459, Final Vref 26
1955 10:04:24.945061
1956 10:04:24.947898 Final TX Range 1 Vref 26
1957 10:04:24.948325
1958 10:04:24.948663 ==
1959 10:04:24.951560 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 10:04:24.954729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 10:04:24.958505 ==
1962 10:04:24.959063
1963 10:04:24.959418
1964 10:04:24.959736 TX Vref Scan disable
1965 10:04:24.961445 == TX Byte 0 ==
1966 10:04:24.965381 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1967 10:04:24.968528 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1968 10:04:24.971879 == TX Byte 1 ==
1969 10:04:24.975545 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1970 10:04:24.978645 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1971 10:04:24.981923
1972 10:04:24.982458 [DATLAT]
1973 10:04:24.982801 Freq=800, CH1 RK1
1974 10:04:24.983124
1975 10:04:24.985063 DATLAT Default: 0xa
1976 10:04:24.985489 0, 0xFFFF, sum = 0
1977 10:04:24.988473 1, 0xFFFF, sum = 0
1978 10:04:24.988925 2, 0xFFFF, sum = 0
1979 10:04:24.992356 3, 0xFFFF, sum = 0
1980 10:04:24.992932 4, 0xFFFF, sum = 0
1981 10:04:24.995270 5, 0xFFFF, sum = 0
1982 10:04:24.995808 6, 0xFFFF, sum = 0
1983 10:04:24.998389 7, 0xFFFF, sum = 0
1984 10:04:25.001742 8, 0xFFFF, sum = 0
1985 10:04:25.002192 9, 0x0, sum = 1
1986 10:04:25.002540 10, 0x0, sum = 2
1987 10:04:25.005231 11, 0x0, sum = 3
1988 10:04:25.005773 12, 0x0, sum = 4
1989 10:04:25.008438 best_step = 10
1990 10:04:25.008901
1991 10:04:25.009248 ==
1992 10:04:25.011700 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 10:04:25.015194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 10:04:25.015734 ==
1995 10:04:25.018380 RX Vref Scan: 0
1996 10:04:25.018805
1997 10:04:25.019145 RX Vref 0 -> 0, step: 1
1998 10:04:25.019463
1999 10:04:25.021746 RX Delay -95 -> 252, step: 8
2000 10:04:25.028164 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2001 10:04:25.031574 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2002 10:04:25.034718 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2003 10:04:25.038075 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2004 10:04:25.041813 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2005 10:04:25.048463 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2006 10:04:25.051296 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2007 10:04:25.054435 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2008 10:04:25.058120 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2009 10:04:25.061333 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2010 10:04:25.068040 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2011 10:04:25.071668 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2012 10:04:25.074873 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2013 10:04:25.078545 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2014 10:04:25.081890 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2015 10:04:25.088662 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2016 10:04:25.089294 ==
2017 10:04:25.091793 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 10:04:25.094630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 10:04:25.095108 ==
2020 10:04:25.095518 DQS Delay:
2021 10:04:25.098048 DQS0 = 0, DQS1 = 0
2022 10:04:25.098563 DQM Delay:
2023 10:04:25.101448 DQM0 = 91, DQM1 = 84
2024 10:04:25.101955 DQ Delay:
2025 10:04:25.105122 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2026 10:04:25.108259 DQ4 =92, DQ5 =108, DQ6 =96, DQ7 =88
2027 10:04:25.111754 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2028 10:04:25.114842 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2029 10:04:25.115522
2030 10:04:25.116085
2031 10:04:25.124519 [DQSOSCAuto] RK1, (LSB)MR18= 0x360c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
2032 10:04:25.125145 CH1 RK1: MR19=606, MR18=360C
2033 10:04:25.130975 CH1_RK1: MR19=0x606, MR18=0x360C, DQSOSC=396, MR23=63, INC=94, DEC=62
2034 10:04:25.134400 [RxdqsGatingPostProcess] freq 800
2035 10:04:25.141321 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2036 10:04:25.144388 Pre-setting of DQS Precalculation
2037 10:04:25.147557 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2038 10:04:25.154176 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2039 10:04:25.161137 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2040 10:04:25.164607
2041 10:04:25.165095
2042 10:04:25.165532 [Calibration Summary] 1600 Mbps
2043 10:04:25.167754 CH 0, Rank 0
2044 10:04:25.168205 SW Impedance : PASS
2045 10:04:25.171123 DUTY Scan : NO K
2046 10:04:25.174471 ZQ Calibration : PASS
2047 10:04:25.174910 Jitter Meter : NO K
2048 10:04:25.178228 CBT Training : PASS
2049 10:04:25.181628 Write leveling : PASS
2050 10:04:25.182071 RX DQS gating : PASS
2051 10:04:25.184291 RX DQ/DQS(RDDQC) : PASS
2052 10:04:25.187829 TX DQ/DQS : PASS
2053 10:04:25.188276 RX DATLAT : PASS
2054 10:04:25.191483 RX DQ/DQS(Engine): PASS
2055 10:04:25.194620 TX OE : NO K
2056 10:04:25.195065 All Pass.
2057 10:04:25.195499
2058 10:04:25.195912 CH 0, Rank 1
2059 10:04:25.198084 SW Impedance : PASS
2060 10:04:25.200965 DUTY Scan : NO K
2061 10:04:25.201470 ZQ Calibration : PASS
2062 10:04:25.204611 Jitter Meter : NO K
2063 10:04:25.207876 CBT Training : PASS
2064 10:04:25.208414 Write leveling : PASS
2065 10:04:25.211164 RX DQS gating : PASS
2066 10:04:25.211705 RX DQ/DQS(RDDQC) : PASS
2067 10:04:25.214342 TX DQ/DQS : PASS
2068 10:04:25.217548 RX DATLAT : PASS
2069 10:04:25.217988 RX DQ/DQS(Engine): PASS
2070 10:04:25.220931 TX OE : NO K
2071 10:04:25.221418 All Pass.
2072 10:04:25.221848
2073 10:04:25.224258 CH 1, Rank 0
2074 10:04:25.224696 SW Impedance : PASS
2075 10:04:25.227316 DUTY Scan : NO K
2076 10:04:25.231055 ZQ Calibration : PASS
2077 10:04:25.231648 Jitter Meter : NO K
2078 10:04:25.234115 CBT Training : PASS
2079 10:04:25.237704 Write leveling : PASS
2080 10:04:25.238277 RX DQS gating : PASS
2081 10:04:25.240702 RX DQ/DQS(RDDQC) : PASS
2082 10:04:25.243868 TX DQ/DQS : PASS
2083 10:04:25.244443 RX DATLAT : PASS
2084 10:04:25.247303 RX DQ/DQS(Engine): PASS
2085 10:04:25.250565 TX OE : NO K
2086 10:04:25.251107 All Pass.
2087 10:04:25.251603
2088 10:04:25.252104 CH 1, Rank 1
2089 10:04:25.254411 SW Impedance : PASS
2090 10:04:25.257450 DUTY Scan : NO K
2091 10:04:25.257990 ZQ Calibration : PASS
2092 10:04:25.260451 Jitter Meter : NO K
2093 10:04:25.263869 CBT Training : PASS
2094 10:04:25.264429 Write leveling : PASS
2095 10:04:25.267019 RX DQS gating : PASS
2096 10:04:25.267611 RX DQ/DQS(RDDQC) : PASS
2097 10:04:25.270458 TX DQ/DQS : PASS
2098 10:04:25.273517 RX DATLAT : PASS
2099 10:04:25.273816 RX DQ/DQS(Engine): PASS
2100 10:04:25.276937 TX OE : NO K
2101 10:04:25.277237 All Pass.
2102 10:04:25.277474
2103 10:04:25.280530 DramC Write-DBI off
2104 10:04:25.283510 PER_BANK_REFRESH: Hybrid Mode
2105 10:04:25.283810 TX_TRACKING: ON
2106 10:04:25.286908 [GetDramInforAfterCalByMRR] Vendor 6.
2107 10:04:25.290360 [GetDramInforAfterCalByMRR] Revision 606.
2108 10:04:25.293739 [GetDramInforAfterCalByMRR] Revision 2 0.
2109 10:04:25.296841 MR0 0x3b3b
2110 10:04:25.297138 MR8 0x5151
2111 10:04:25.300341 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 10:04:25.300639
2113 10:04:25.303485 MR0 0x3b3b
2114 10:04:25.303794 MR8 0x5151
2115 10:04:25.306982 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 10:04:25.307280
2117 10:04:25.317298 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2118 10:04:25.320244 [FAST_K] Save calibration result to emmc
2119 10:04:25.323416 [FAST_K] Save calibration result to emmc
2120 10:04:25.326920 dram_init: config_dvfs: 1
2121 10:04:25.330103 dramc_set_vcore_voltage set vcore to 662500
2122 10:04:25.330552 Read voltage for 1200, 2
2123 10:04:25.333368 Vio18 = 0
2124 10:04:25.333814 Vcore = 662500
2125 10:04:25.334124 Vdram = 0
2126 10:04:25.336963 Vddq = 0
2127 10:04:25.337455 Vmddr = 0
2128 10:04:25.340581 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2129 10:04:25.346557 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2130 10:04:25.350333 MEM_TYPE=3, freq_sel=15
2131 10:04:25.353219 sv_algorithm_assistance_LP4_1600
2132 10:04:25.356639 ============ PULL DRAM RESETB DOWN ============
2133 10:04:25.359749 ========== PULL DRAM RESETB DOWN end =========
2134 10:04:25.366820 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2135 10:04:25.370061 ===================================
2136 10:04:25.370368 LPDDR4 DRAM CONFIGURATION
2137 10:04:25.373272 ===================================
2138 10:04:25.376512 EX_ROW_EN[0] = 0x0
2139 10:04:25.376595 EX_ROW_EN[1] = 0x0
2140 10:04:25.379838 LP4Y_EN = 0x0
2141 10:04:25.379921 WORK_FSP = 0x0
2142 10:04:25.383130 WL = 0x4
2143 10:04:25.383213 RL = 0x4
2144 10:04:25.386323 BL = 0x2
2145 10:04:25.389576 RPST = 0x0
2146 10:04:25.389659 RD_PRE = 0x0
2147 10:04:25.393044 WR_PRE = 0x1
2148 10:04:25.393127 WR_PST = 0x0
2149 10:04:25.396445 DBI_WR = 0x0
2150 10:04:25.396528 DBI_RD = 0x0
2151 10:04:25.399567 OTF = 0x1
2152 10:04:25.402928 ===================================
2153 10:04:25.406600 ===================================
2154 10:04:25.406684 ANA top config
2155 10:04:25.409451 ===================================
2156 10:04:25.412899 DLL_ASYNC_EN = 0
2157 10:04:25.416398 ALL_SLAVE_EN = 0
2158 10:04:25.416503 NEW_RANK_MODE = 1
2159 10:04:25.419361 DLL_IDLE_MODE = 1
2160 10:04:25.423393 LP45_APHY_COMB_EN = 1
2161 10:04:25.425867 TX_ODT_DIS = 1
2162 10:04:25.425951 NEW_8X_MODE = 1
2163 10:04:25.429448 ===================================
2164 10:04:25.432714 ===================================
2165 10:04:25.436322 data_rate = 2400
2166 10:04:25.439236 CKR = 1
2167 10:04:25.442615 DQ_P2S_RATIO = 8
2168 10:04:25.446099 ===================================
2169 10:04:25.449719 CA_P2S_RATIO = 8
2170 10:04:25.452900 DQ_CA_OPEN = 0
2171 10:04:25.456101 DQ_SEMI_OPEN = 0
2172 10:04:25.456200 CA_SEMI_OPEN = 0
2173 10:04:25.459387 CA_FULL_RATE = 0
2174 10:04:25.462571 DQ_CKDIV4_EN = 0
2175 10:04:25.466152 CA_CKDIV4_EN = 0
2176 10:04:25.469417 CA_PREDIV_EN = 0
2177 10:04:25.473082 PH8_DLY = 17
2178 10:04:25.473277 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2179 10:04:25.475932 DQ_AAMCK_DIV = 4
2180 10:04:25.479904 CA_AAMCK_DIV = 4
2181 10:04:25.483017 CA_ADMCK_DIV = 4
2182 10:04:25.486089 DQ_TRACK_CA_EN = 0
2183 10:04:25.489577 CA_PICK = 1200
2184 10:04:25.489815 CA_MCKIO = 1200
2185 10:04:25.492782 MCKIO_SEMI = 0
2186 10:04:25.496761 PLL_FREQ = 2366
2187 10:04:25.499915 DQ_UI_PI_RATIO = 32
2188 10:04:25.503209 CA_UI_PI_RATIO = 0
2189 10:04:25.506168 ===================================
2190 10:04:25.509854 ===================================
2191 10:04:25.513163 memory_type:LPDDR4
2192 10:04:25.513652 GP_NUM : 10
2193 10:04:25.516350 SRAM_EN : 1
2194 10:04:25.516861 MD32_EN : 0
2195 10:04:25.519833 ===================================
2196 10:04:25.522746 [ANA_INIT] >>>>>>>>>>>>>>
2197 10:04:25.526286 <<<<<< [CONFIGURE PHASE]: ANA_TX
2198 10:04:25.529878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2199 10:04:25.532519 ===================================
2200 10:04:25.536223 data_rate = 2400,PCW = 0X5b00
2201 10:04:25.539626 ===================================
2202 10:04:25.542911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2203 10:04:25.549629 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 10:04:25.552307 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 10:04:25.559102 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2206 10:04:25.562631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2207 10:04:25.565920 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2208 10:04:25.566497 [ANA_INIT] flow start
2209 10:04:25.569647 [ANA_INIT] PLL >>>>>>>>
2210 10:04:25.572548 [ANA_INIT] PLL <<<<<<<<
2211 10:04:25.572966 [ANA_INIT] MIDPI >>>>>>>>
2212 10:04:25.575589 [ANA_INIT] MIDPI <<<<<<<<
2213 10:04:25.578947 [ANA_INIT] DLL >>>>>>>>
2214 10:04:25.579029 [ANA_INIT] DLL <<<<<<<<
2215 10:04:25.582318 [ANA_INIT] flow end
2216 10:04:25.585699 ============ LP4 DIFF to SE enter ============
2217 10:04:25.588653 ============ LP4 DIFF to SE exit ============
2218 10:04:25.592151 [ANA_INIT] <<<<<<<<<<<<<
2219 10:04:25.595569 [Flow] Enable top DCM control >>>>>
2220 10:04:25.598712 [Flow] Enable top DCM control <<<<<
2221 10:04:25.602019 Enable DLL master slave shuffle
2222 10:04:25.608606 ==============================================================
2223 10:04:25.608715 Gating Mode config
2224 10:04:25.615276 ==============================================================
2225 10:04:25.618468 Config description:
2226 10:04:25.625414 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2227 10:04:25.631447 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2228 10:04:25.638312 SELPH_MODE 0: By rank 1: By Phase
2229 10:04:25.644728 ==============================================================
2230 10:04:25.648529 GAT_TRACK_EN = 1
2231 10:04:25.648604 RX_GATING_MODE = 2
2232 10:04:25.651438 RX_GATING_TRACK_MODE = 2
2233 10:04:25.655367 SELPH_MODE = 1
2234 10:04:25.658211 PICG_EARLY_EN = 1
2235 10:04:25.661757 VALID_LAT_VALUE = 1
2236 10:04:25.668371 ==============================================================
2237 10:04:25.671945 Enter into Gating configuration >>>>
2238 10:04:25.674785 Exit from Gating configuration <<<<
2239 10:04:25.678055 Enter into DVFS_PRE_config >>>>>
2240 10:04:25.688151 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2241 10:04:25.691610 Exit from DVFS_PRE_config <<<<<
2242 10:04:25.694845 Enter into PICG configuration >>>>
2243 10:04:25.698819 Exit from PICG configuration <<<<
2244 10:04:25.701730 [RX_INPUT] configuration >>>>>
2245 10:04:25.701831 [RX_INPUT] configuration <<<<<
2246 10:04:25.708319 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2247 10:04:25.715044 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2248 10:04:25.718227 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 10:04:25.725244 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 10:04:25.731480 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 10:04:25.738597 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 10:04:25.742106 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2253 10:04:25.745419 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2254 10:04:25.752053 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2255 10:04:25.754987 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2256 10:04:25.758423 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2257 10:04:25.764826 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 10:04:25.768243 ===================================
2259 10:04:25.768672 LPDDR4 DRAM CONFIGURATION
2260 10:04:25.771885 ===================================
2261 10:04:25.774949 EX_ROW_EN[0] = 0x0
2262 10:04:25.778041 EX_ROW_EN[1] = 0x0
2263 10:04:25.778480 LP4Y_EN = 0x0
2264 10:04:25.781353 WORK_FSP = 0x0
2265 10:04:25.781794 WL = 0x4
2266 10:04:25.784530 RL = 0x4
2267 10:04:25.785067 BL = 0x2
2268 10:04:25.788187 RPST = 0x0
2269 10:04:25.788612 RD_PRE = 0x0
2270 10:04:25.791249 WR_PRE = 0x1
2271 10:04:25.791675 WR_PST = 0x0
2272 10:04:25.794689 DBI_WR = 0x0
2273 10:04:25.795116 DBI_RD = 0x0
2274 10:04:25.797870 OTF = 0x1
2275 10:04:25.801301 ===================================
2276 10:04:25.804489 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2277 10:04:25.807704 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2278 10:04:25.814900 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 10:04:25.817711 ===================================
2280 10:04:25.818144 LPDDR4 DRAM CONFIGURATION
2281 10:04:25.821123 ===================================
2282 10:04:25.824725 EX_ROW_EN[0] = 0x10
2283 10:04:25.825224 EX_ROW_EN[1] = 0x0
2284 10:04:25.828074 LP4Y_EN = 0x0
2285 10:04:25.831097 WORK_FSP = 0x0
2286 10:04:25.831524 WL = 0x4
2287 10:04:25.834364 RL = 0x4
2288 10:04:25.834821 BL = 0x2
2289 10:04:25.837966 RPST = 0x0
2290 10:04:25.838489 RD_PRE = 0x0
2291 10:04:25.841058 WR_PRE = 0x1
2292 10:04:25.841475 WR_PST = 0x0
2293 10:04:25.844836 DBI_WR = 0x0
2294 10:04:25.845244 DBI_RD = 0x0
2295 10:04:25.847854 OTF = 0x1
2296 10:04:25.851130 ===================================
2297 10:04:25.857767 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2298 10:04:25.858176 ==
2299 10:04:25.861056 Dram Type= 6, Freq= 0, CH_0, rank 0
2300 10:04:25.864362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2301 10:04:25.864809 ==
2302 10:04:25.868095 [Duty_Offset_Calibration]
2303 10:04:25.868608 B0:2 B1:0 CA:1
2304 10:04:25.868986
2305 10:04:25.871203 [DutyScan_Calibration_Flow] k_type=0
2306 10:04:25.880330
2307 10:04:25.880892 ==CLK 0==
2308 10:04:25.883266 Final CLK duty delay cell = -4
2309 10:04:25.886517 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2310 10:04:25.890134 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2311 10:04:25.893073 [-4] AVG Duty = 4953%(X100)
2312 10:04:25.893483
2313 10:04:25.896652 CH0 CLK Duty spec in!! Max-Min= 156%
2314 10:04:25.899665 [DutyScan_Calibration_Flow] ====Done====
2315 10:04:25.900079
2316 10:04:25.902902 [DutyScan_Calibration_Flow] k_type=1
2317 10:04:25.919001
2318 10:04:25.919549 ==DQS 0 ==
2319 10:04:25.922326 Final DQS duty delay cell = 0
2320 10:04:25.925567 [0] MAX Duty = 5187%(X100), DQS PI = 30
2321 10:04:25.928910 [0] MIN Duty = 4938%(X100), DQS PI = 2
2322 10:04:25.929481 [0] AVG Duty = 5062%(X100)
2323 10:04:25.932579
2324 10:04:25.933315 ==DQS 1 ==
2325 10:04:25.935589 Final DQS duty delay cell = -4
2326 10:04:25.938466 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2327 10:04:25.942341 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2328 10:04:25.945223 [-4] AVG Duty = 5031%(X100)
2329 10:04:25.945674
2330 10:04:25.948684 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2331 10:04:25.949178
2332 10:04:25.951895 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2333 10:04:25.955668 [DutyScan_Calibration_Flow] ====Done====
2334 10:04:25.956114
2335 10:04:25.958386 [DutyScan_Calibration_Flow] k_type=3
2336 10:04:25.976034
2337 10:04:25.976589 ==DQM 0 ==
2338 10:04:25.978823 Final DQM duty delay cell = 0
2339 10:04:25.982204 [0] MAX Duty = 5062%(X100), DQS PI = 24
2340 10:04:25.985404 [0] MIN Duty = 4844%(X100), DQS PI = 0
2341 10:04:25.988581 [0] AVG Duty = 4953%(X100)
2342 10:04:25.989063
2343 10:04:25.989421 ==DQM 1 ==
2344 10:04:25.992542 Final DQM duty delay cell = 0
2345 10:04:25.995600 [0] MAX Duty = 5187%(X100), DQS PI = 48
2346 10:04:25.998956 [0] MIN Duty = 5000%(X100), DQS PI = 24
2347 10:04:26.002134 [0] AVG Duty = 5093%(X100)
2348 10:04:26.002592
2349 10:04:26.005569 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2350 10:04:26.006029
2351 10:04:26.008956 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2352 10:04:26.012069 [DutyScan_Calibration_Flow] ====Done====
2353 10:04:26.012708
2354 10:04:26.015150 [DutyScan_Calibration_Flow] k_type=2
2355 10:04:26.031663
2356 10:04:26.032209 ==DQ 0 ==
2357 10:04:26.034784 Final DQ duty delay cell = -4
2358 10:04:26.038468 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2359 10:04:26.041592 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2360 10:04:26.044718 [-4] AVG Duty = 4953%(X100)
2361 10:04:26.045321
2362 10:04:26.045685 ==DQ 1 ==
2363 10:04:26.048452 Final DQ duty delay cell = 0
2364 10:04:26.051635 [0] MAX Duty = 4938%(X100), DQS PI = 4
2365 10:04:26.055064 [0] MIN Duty = 4907%(X100), DQS PI = 0
2366 10:04:26.055617 [0] AVG Duty = 4922%(X100)
2367 10:04:26.058548
2368 10:04:26.061077 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2369 10:04:26.061585
2370 10:04:26.064160 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2371 10:04:26.068137 [DutyScan_Calibration_Flow] ====Done====
2372 10:04:26.068640 ==
2373 10:04:26.071201 Dram Type= 6, Freq= 0, CH_1, rank 0
2374 10:04:26.074819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 10:04:26.075344 ==
2376 10:04:26.077940 [Duty_Offset_Calibration]
2377 10:04:26.078483 B0:0 B1:-1 CA:2
2378 10:04:26.078956
2379 10:04:26.080981 [DutyScan_Calibration_Flow] k_type=0
2380 10:04:26.091299
2381 10:04:26.091706 ==CLK 0==
2382 10:04:26.094523 Final CLK duty delay cell = 0
2383 10:04:26.097942 [0] MAX Duty = 5156%(X100), DQS PI = 16
2384 10:04:26.101395 [0] MIN Duty = 4938%(X100), DQS PI = 44
2385 10:04:26.101987 [0] AVG Duty = 5047%(X100)
2386 10:04:26.104977
2387 10:04:26.107998 CH1 CLK Duty spec in!! Max-Min= 218%
2388 10:04:26.111770 [DutyScan_Calibration_Flow] ====Done====
2389 10:04:26.112299
2390 10:04:26.114512 [DutyScan_Calibration_Flow] k_type=1
2391 10:04:26.130964
2392 10:04:26.131539 ==DQS 0 ==
2393 10:04:26.134309 Final DQS duty delay cell = 0
2394 10:04:26.137441 [0] MAX Duty = 5093%(X100), DQS PI = 24
2395 10:04:26.141100 [0] MIN Duty = 4969%(X100), DQS PI = 0
2396 10:04:26.144299 [0] AVG Duty = 5031%(X100)
2397 10:04:26.144916
2398 10:04:26.145297 ==DQS 1 ==
2399 10:04:26.147947 Final DQS duty delay cell = 0
2400 10:04:26.151634 [0] MAX Duty = 5156%(X100), DQS PI = 0
2401 10:04:26.154088 [0] MIN Duty = 4844%(X100), DQS PI = 36
2402 10:04:26.157725 [0] AVG Duty = 5000%(X100)
2403 10:04:26.158193
2404 10:04:26.160939 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2405 10:04:26.161522
2406 10:04:26.164644 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2407 10:04:26.167624 [DutyScan_Calibration_Flow] ====Done====
2408 10:04:26.168168
2409 10:04:26.170801 [DutyScan_Calibration_Flow] k_type=3
2410 10:04:26.187725
2411 10:04:26.188299 ==DQM 0 ==
2412 10:04:26.190798 Final DQM duty delay cell = 4
2413 10:04:26.194191 [4] MAX Duty = 5093%(X100), DQS PI = 6
2414 10:04:26.197389 [4] MIN Duty = 4907%(X100), DQS PI = 46
2415 10:04:26.197970 [4] AVG Duty = 5000%(X100)
2416 10:04:26.200440
2417 10:04:26.200936 ==DQM 1 ==
2418 10:04:26.204248 Final DQM duty delay cell = -4
2419 10:04:26.207373 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2420 10:04:26.210410 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2421 10:04:26.213789 [-4] AVG Duty = 4875%(X100)
2422 10:04:26.214295
2423 10:04:26.217063 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2424 10:04:26.217631
2425 10:04:26.220671 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2426 10:04:26.223829 [DutyScan_Calibration_Flow] ====Done====
2427 10:04:26.224297
2428 10:04:26.227383 [DutyScan_Calibration_Flow] k_type=2
2429 10:04:26.243889
2430 10:04:26.244320 ==DQ 0 ==
2431 10:04:26.247544 Final DQ duty delay cell = 0
2432 10:04:26.251208 [0] MAX Duty = 5062%(X100), DQS PI = 20
2433 10:04:26.254154 [0] MIN Duty = 4938%(X100), DQS PI = 44
2434 10:04:26.254600 [0] AVG Duty = 5000%(X100)
2435 10:04:26.254995
2436 10:04:26.257624 ==DQ 1 ==
2437 10:04:26.260662 Final DQ duty delay cell = 0
2438 10:04:26.264254 [0] MAX Duty = 5031%(X100), DQS PI = 0
2439 10:04:26.267319 [0] MIN Duty = 4813%(X100), DQS PI = 34
2440 10:04:26.267748 [0] AVG Duty = 4922%(X100)
2441 10:04:26.268094
2442 10:04:26.270724 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2443 10:04:26.271168
2444 10:04:26.274200 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2445 10:04:26.280817 [DutyScan_Calibration_Flow] ====Done====
2446 10:04:26.284534 nWR fixed to 30
2447 10:04:26.285104 [ModeRegInit_LP4] CH0 RK0
2448 10:04:26.287633 [ModeRegInit_LP4] CH0 RK1
2449 10:04:26.290974 [ModeRegInit_LP4] CH1 RK0
2450 10:04:26.291542 [ModeRegInit_LP4] CH1 RK1
2451 10:04:26.294600 match AC timing 7
2452 10:04:26.297739 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2453 10:04:26.300746 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2454 10:04:26.307622 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2455 10:04:26.310741 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2456 10:04:26.317310 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2457 10:04:26.317882 ==
2458 10:04:26.320702 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 10:04:26.324181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2460 10:04:26.324752 ==
2461 10:04:26.330878 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2462 10:04:26.337140 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2463 10:04:26.344110 [CA 0] Center 38 (8~69) winsize 62
2464 10:04:26.347675 [CA 1] Center 38 (8~69) winsize 62
2465 10:04:26.350641 [CA 2] Center 35 (5~66) winsize 62
2466 10:04:26.353905 [CA 3] Center 35 (4~66) winsize 63
2467 10:04:26.357043 [CA 4] Center 34 (4~65) winsize 62
2468 10:04:26.360866 [CA 5] Center 33 (3~63) winsize 61
2469 10:04:26.361429
2470 10:04:26.364343 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2471 10:04:26.364950
2472 10:04:26.367493 [CATrainingPosCal] consider 1 rank data
2473 10:04:26.370695 u2DelayCellTimex100 = 270/100 ps
2474 10:04:26.374092 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2475 10:04:26.377931 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2476 10:04:26.384000 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2477 10:04:26.387390 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2478 10:04:26.390378 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2479 10:04:26.394176 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2480 10:04:26.394744
2481 10:04:26.397502 CA PerBit enable=1, Macro0, CA PI delay=33
2482 10:04:26.397977
2483 10:04:26.400593 [CBTSetCACLKResult] CA Dly = 33
2484 10:04:26.401205 CS Dly: 6 (0~37)
2485 10:04:26.401590 ==
2486 10:04:26.403934 Dram Type= 6, Freq= 0, CH_0, rank 1
2487 10:04:26.410510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2488 10:04:26.411092 ==
2489 10:04:26.414041 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2490 10:04:26.420261 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2491 10:04:26.429700 [CA 0] Center 39 (8~70) winsize 63
2492 10:04:26.433282 [CA 1] Center 38 (8~69) winsize 62
2493 10:04:26.436696 [CA 2] Center 35 (5~66) winsize 62
2494 10:04:26.440092 [CA 3] Center 35 (5~66) winsize 62
2495 10:04:26.443263 [CA 4] Center 34 (4~65) winsize 62
2496 10:04:26.446284 [CA 5] Center 34 (4~64) winsize 61
2497 10:04:26.446763
2498 10:04:26.450115 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2499 10:04:26.450680
2500 10:04:26.452794 [CATrainingPosCal] consider 2 rank data
2501 10:04:26.456103 u2DelayCellTimex100 = 270/100 ps
2502 10:04:26.459792 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2503 10:04:26.463354 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2504 10:04:26.469753 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 10:04:26.472977 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2506 10:04:26.476301 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2507 10:04:26.479964 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2508 10:04:26.480529
2509 10:04:26.483213 CA PerBit enable=1, Macro0, CA PI delay=33
2510 10:04:26.483778
2511 10:04:26.486730 [CBTSetCACLKResult] CA Dly = 33
2512 10:04:26.487306 CS Dly: 7 (0~39)
2513 10:04:26.487692
2514 10:04:26.489537 ----->DramcWriteLeveling(PI) begin...
2515 10:04:26.492960 ==
2516 10:04:26.496278 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 10:04:26.499798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 10:04:26.500366 ==
2519 10:04:26.502806 Write leveling (Byte 0): 34 => 34
2520 10:04:26.506284 Write leveling (Byte 1): 32 => 32
2521 10:04:26.509282 DramcWriteLeveling(PI) end<-----
2522 10:04:26.509754
2523 10:04:26.510130 ==
2524 10:04:26.512976 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 10:04:26.516356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 10:04:26.516955 ==
2527 10:04:26.519517 [Gating] SW mode calibration
2528 10:04:26.525728 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2529 10:04:26.532984 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2530 10:04:26.536001 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2531 10:04:26.539129 0 15 4 | B1->B0 | 2c2b 3434 | 1 1 | (1 1) (1 1)
2532 10:04:26.545985 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 10:04:26.549198 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 10:04:26.552468 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 10:04:26.556258 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 10:04:26.562988 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2537 10:04:26.566039 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
2538 10:04:26.569467 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
2539 10:04:26.575692 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2540 10:04:26.579179 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 10:04:26.582592 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 10:04:26.588819 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 10:04:26.592277 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 10:04:26.595501 1 0 24 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
2545 10:04:26.602258 1 0 28 | B1->B0 | 2524 4646 | 1 0 | (0 0) (0 0)
2546 10:04:26.605289 1 1 0 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
2547 10:04:26.608602 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 10:04:26.615079 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 10:04:26.618771 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 10:04:26.621674 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 10:04:26.628783 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 10:04:26.631874 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 10:04:26.635269 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2554 10:04:26.641801 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2555 10:04:26.645350 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 10:04:26.648542 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 10:04:26.655046 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 10:04:26.658644 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 10:04:26.661919 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 10:04:26.665559 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 10:04:26.671583 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 10:04:26.675133 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 10:04:26.681626 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 10:04:26.684909 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 10:04:26.688644 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 10:04:26.691729 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 10:04:26.698389 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 10:04:26.701799 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2569 10:04:26.704959 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2570 10:04:26.711409 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2571 10:04:26.715015 Total UI for P1: 0, mck2ui 16
2572 10:04:26.718058 best dqsien dly found for B0: ( 1, 3, 26)
2573 10:04:26.721651 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 10:04:26.724576 Total UI for P1: 0, mck2ui 16
2575 10:04:26.728202 best dqsien dly found for B1: ( 1, 4, 0)
2576 10:04:26.731304 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2577 10:04:26.734720 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2578 10:04:26.734819
2579 10:04:26.738214 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2580 10:04:26.741410 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2581 10:04:26.744988 [Gating] SW calibration Done
2582 10:04:26.745072 ==
2583 10:04:26.748225 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 10:04:26.751231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 10:04:26.754525 ==
2586 10:04:26.754607 RX Vref Scan: 0
2587 10:04:26.754674
2588 10:04:26.757937 RX Vref 0 -> 0, step: 1
2589 10:04:26.758019
2590 10:04:26.761605 RX Delay -40 -> 252, step: 8
2591 10:04:26.764745 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2592 10:04:26.767952 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2593 10:04:26.771471 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2594 10:04:26.774785 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2595 10:04:26.781847 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2596 10:04:26.785353 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2597 10:04:26.788501 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2598 10:04:26.791369 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2599 10:04:26.794910 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2600 10:04:26.801254 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2601 10:04:26.804641 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2602 10:04:26.808320 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2603 10:04:26.811592 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2604 10:04:26.814620 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2605 10:04:26.821276 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2606 10:04:26.824267 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2607 10:04:26.824439 ==
2608 10:04:26.828035 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 10:04:26.831225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 10:04:26.831417 ==
2611 10:04:26.834125 DQS Delay:
2612 10:04:26.834293 DQS0 = 0, DQS1 = 0
2613 10:04:26.834383 DQM Delay:
2614 10:04:26.838063 DQM0 = 122, DQM1 = 110
2615 10:04:26.838190 DQ Delay:
2616 10:04:26.840838 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2617 10:04:26.844596 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2618 10:04:26.848044 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2619 10:04:26.854515 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2620 10:04:26.854851
2621 10:04:26.855182
2622 10:04:26.855496 ==
2623 10:04:26.857891 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 10:04:26.861234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 10:04:26.861571 ==
2626 10:04:26.861904
2627 10:04:26.862217
2628 10:04:26.864877 TX Vref Scan disable
2629 10:04:26.865313 == TX Byte 0 ==
2630 10:04:26.871427 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2631 10:04:26.875048 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2632 10:04:26.875488 == TX Byte 1 ==
2633 10:04:26.881627 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2634 10:04:26.885116 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2635 10:04:26.885696 ==
2636 10:04:26.888180 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 10:04:26.891425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 10:04:26.892007 ==
2639 10:04:26.904397 TX Vref=22, minBit 3, minWin=24, winSum=404
2640 10:04:26.907283 TX Vref=24, minBit 0, minWin=25, winSum=411
2641 10:04:26.910874 TX Vref=26, minBit 1, minWin=24, winSum=414
2642 10:04:26.913979 TX Vref=28, minBit 1, minWin=25, winSum=414
2643 10:04:26.917730 TX Vref=30, minBit 3, minWin=25, winSum=417
2644 10:04:26.921048 TX Vref=32, minBit 1, minWin=25, winSum=413
2645 10:04:26.927729 [TxChooseVref] Worse bit 3, Min win 25, Win sum 417, Final Vref 30
2646 10:04:26.928311
2647 10:04:26.930697 Final TX Range 1 Vref 30
2648 10:04:26.931175
2649 10:04:26.931651 ==
2650 10:04:26.933949 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 10:04:26.937429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 10:04:26.938013 ==
2653 10:04:26.938495
2654 10:04:26.940877
2655 10:04:26.941355 TX Vref Scan disable
2656 10:04:26.944392 == TX Byte 0 ==
2657 10:04:26.947553 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2658 10:04:26.950902 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2659 10:04:26.954359 == TX Byte 1 ==
2660 10:04:26.957373 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2661 10:04:26.961066 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2662 10:04:26.961643
2663 10:04:26.964433 [DATLAT]
2664 10:04:26.965045 Freq=1200, CH0 RK0
2665 10:04:26.965537
2666 10:04:26.967341 DATLAT Default: 0xd
2667 10:04:26.967916 0, 0xFFFF, sum = 0
2668 10:04:26.970890 1, 0xFFFF, sum = 0
2669 10:04:26.971478 2, 0xFFFF, sum = 0
2670 10:04:26.974306 3, 0xFFFF, sum = 0
2671 10:04:26.974898 4, 0xFFFF, sum = 0
2672 10:04:26.977495 5, 0xFFFF, sum = 0
2673 10:04:26.978082 6, 0xFFFF, sum = 0
2674 10:04:26.980990 7, 0xFFFF, sum = 0
2675 10:04:26.984277 8, 0xFFFF, sum = 0
2676 10:04:26.984938 9, 0xFFFF, sum = 0
2677 10:04:26.987390 10, 0xFFFF, sum = 0
2678 10:04:26.987973 11, 0xFFFF, sum = 0
2679 10:04:26.990707 12, 0x0, sum = 1
2680 10:04:26.991197 13, 0x0, sum = 2
2681 10:04:26.993589 14, 0x0, sum = 3
2682 10:04:26.994068 15, 0x0, sum = 4
2683 10:04:26.994449 best_step = 13
2684 10:04:26.994798
2685 10:04:26.996944 ==
2686 10:04:27.000676 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 10:04:27.003943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 10:04:27.004419 ==
2689 10:04:27.004840 RX Vref Scan: 1
2690 10:04:27.005358
2691 10:04:27.007014 Set Vref Range= 32 -> 127
2692 10:04:27.007479
2693 10:04:27.010709 RX Vref 32 -> 127, step: 1
2694 10:04:27.011275
2695 10:04:27.013816 RX Delay -13 -> 252, step: 4
2696 10:04:27.014380
2697 10:04:27.017278 Set Vref, RX VrefLevel [Byte0]: 32
2698 10:04:27.020866 [Byte1]: 32
2699 10:04:27.021440
2700 10:04:27.024153 Set Vref, RX VrefLevel [Byte0]: 33
2701 10:04:27.027186 [Byte1]: 33
2702 10:04:27.027652
2703 10:04:27.030804 Set Vref, RX VrefLevel [Byte0]: 34
2704 10:04:27.033909 [Byte1]: 34
2705 10:04:27.038165
2706 10:04:27.038725 Set Vref, RX VrefLevel [Byte0]: 35
2707 10:04:27.041469 [Byte1]: 35
2708 10:04:27.046346
2709 10:04:27.046907 Set Vref, RX VrefLevel [Byte0]: 36
2710 10:04:27.049525 [Byte1]: 36
2711 10:04:27.053887
2712 10:04:27.054452 Set Vref, RX VrefLevel [Byte0]: 37
2713 10:04:27.057107 [Byte1]: 37
2714 10:04:27.061953
2715 10:04:27.062513 Set Vref, RX VrefLevel [Byte0]: 38
2716 10:04:27.065127 [Byte1]: 38
2717 10:04:27.070152
2718 10:04:27.070714 Set Vref, RX VrefLevel [Byte0]: 39
2719 10:04:27.073116 [Byte1]: 39
2720 10:04:27.077742
2721 10:04:27.078304 Set Vref, RX VrefLevel [Byte0]: 40
2722 10:04:27.080927 [Byte1]: 40
2723 10:04:27.085512
2724 10:04:27.086073 Set Vref, RX VrefLevel [Byte0]: 41
2725 10:04:27.089012 [Byte1]: 41
2726 10:04:27.093607
2727 10:04:27.094171 Set Vref, RX VrefLevel [Byte0]: 42
2728 10:04:27.096705 [Byte1]: 42
2729 10:04:27.101367
2730 10:04:27.101927 Set Vref, RX VrefLevel [Byte0]: 43
2731 10:04:27.104380 [Byte1]: 43
2732 10:04:27.109237
2733 10:04:27.109697 Set Vref, RX VrefLevel [Byte0]: 44
2734 10:04:27.112375 [Byte1]: 44
2735 10:04:27.117325
2736 10:04:27.117889 Set Vref, RX VrefLevel [Byte0]: 45
2737 10:04:27.120206 [Byte1]: 45
2738 10:04:27.125137
2739 10:04:27.125699 Set Vref, RX VrefLevel [Byte0]: 46
2740 10:04:27.128491 [Byte1]: 46
2741 10:04:27.133069
2742 10:04:27.133634 Set Vref, RX VrefLevel [Byte0]: 47
2743 10:04:27.136084 [Byte1]: 47
2744 10:04:27.140677
2745 10:04:27.141247 Set Vref, RX VrefLevel [Byte0]: 48
2746 10:04:27.143787 [Byte1]: 48
2747 10:04:27.148636
2748 10:04:27.149253 Set Vref, RX VrefLevel [Byte0]: 49
2749 10:04:27.151824 [Byte1]: 49
2750 10:04:27.156651
2751 10:04:27.157172 Set Vref, RX VrefLevel [Byte0]: 50
2752 10:04:27.160104 [Byte1]: 50
2753 10:04:27.164576
2754 10:04:27.165285 Set Vref, RX VrefLevel [Byte0]: 51
2755 10:04:27.167912 [Byte1]: 51
2756 10:04:27.172694
2757 10:04:27.173323 Set Vref, RX VrefLevel [Byte0]: 52
2758 10:04:27.175569 [Byte1]: 52
2759 10:04:27.180199
2760 10:04:27.180783 Set Vref, RX VrefLevel [Byte0]: 53
2761 10:04:27.183497 [Byte1]: 53
2762 10:04:27.188153
2763 10:04:27.188716 Set Vref, RX VrefLevel [Byte0]: 54
2764 10:04:27.191717 [Byte1]: 54
2765 10:04:27.196011
2766 10:04:27.196578 Set Vref, RX VrefLevel [Byte0]: 55
2767 10:04:27.202734 [Byte1]: 55
2768 10:04:27.203298
2769 10:04:27.205791 Set Vref, RX VrefLevel [Byte0]: 56
2770 10:04:27.208933 [Byte1]: 56
2771 10:04:27.209494
2772 10:04:27.212551 Set Vref, RX VrefLevel [Byte0]: 57
2773 10:04:27.215767 [Byte1]: 57
2774 10:04:27.219749
2775 10:04:27.220311 Set Vref, RX VrefLevel [Byte0]: 58
2776 10:04:27.223421 [Byte1]: 58
2777 10:04:27.227916
2778 10:04:27.228481 Set Vref, RX VrefLevel [Byte0]: 59
2779 10:04:27.230755 [Byte1]: 59
2780 10:04:27.235441
2781 10:04:27.236008 Set Vref, RX VrefLevel [Byte0]: 60
2782 10:04:27.238505 [Byte1]: 60
2783 10:04:27.242797
2784 10:04:27.243465 Set Vref, RX VrefLevel [Byte0]: 61
2785 10:04:27.246187 [Byte1]: 61
2786 10:04:27.251381
2787 10:04:27.251850 Set Vref, RX VrefLevel [Byte0]: 62
2788 10:04:27.254324 [Byte1]: 62
2789 10:04:27.258897
2790 10:04:27.259367 Set Vref, RX VrefLevel [Byte0]: 63
2791 10:04:27.262039 [Byte1]: 63
2792 10:04:27.266741
2793 10:04:27.267304 Set Vref, RX VrefLevel [Byte0]: 64
2794 10:04:27.270262 [Byte1]: 64
2795 10:04:27.275125
2796 10:04:27.275685 Set Vref, RX VrefLevel [Byte0]: 65
2797 10:04:27.278336 [Byte1]: 65
2798 10:04:27.282911
2799 10:04:27.283475 Set Vref, RX VrefLevel [Byte0]: 66
2800 10:04:27.286564 [Byte1]: 66
2801 10:04:27.290897
2802 10:04:27.291474 Set Vref, RX VrefLevel [Byte0]: 67
2803 10:04:27.294045 [Byte1]: 67
2804 10:04:27.298665
2805 10:04:27.301801 Set Vref, RX VrefLevel [Byte0]: 68
2806 10:04:27.304880 [Byte1]: 68
2807 10:04:27.305471
2808 10:04:27.308062 Set Vref, RX VrefLevel [Byte0]: 69
2809 10:04:27.311634 [Byte1]: 69
2810 10:04:27.312199
2811 10:04:27.314740 Final RX Vref Byte 0 = 57 to rank0
2812 10:04:27.318174 Final RX Vref Byte 1 = 48 to rank0
2813 10:04:27.321556 Final RX Vref Byte 0 = 57 to rank1
2814 10:04:27.324971 Final RX Vref Byte 1 = 48 to rank1==
2815 10:04:27.328341 Dram Type= 6, Freq= 0, CH_0, rank 0
2816 10:04:27.331902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2817 10:04:27.332477 ==
2818 10:04:27.334885 DQS Delay:
2819 10:04:27.335445 DQS0 = 0, DQS1 = 0
2820 10:04:27.337922 DQM Delay:
2821 10:04:27.338392 DQM0 = 122, DQM1 = 108
2822 10:04:27.341282 DQ Delay:
2823 10:04:27.344715 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2824 10:04:27.348322 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2825 10:04:27.351349 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =104
2826 10:04:27.354713 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =116
2827 10:04:27.355300
2828 10:04:27.355672
2829 10:04:27.361571 [DQSOSCAuto] RK0, (LSB)MR18= 0xa06, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2830 10:04:27.364666 CH0 RK0: MR19=404, MR18=A06
2831 10:04:27.371366 CH0_RK0: MR19=0x404, MR18=0xA06, DQSOSC=406, MR23=63, INC=39, DEC=26
2832 10:04:27.371931
2833 10:04:27.374642 ----->DramcWriteLeveling(PI) begin...
2834 10:04:27.375219 ==
2835 10:04:27.377675 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 10:04:27.380870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 10:04:27.381336 ==
2838 10:04:27.384878 Write leveling (Byte 0): 35 => 35
2839 10:04:27.388001 Write leveling (Byte 1): 30 => 30
2840 10:04:27.391135 DramcWriteLeveling(PI) end<-----
2841 10:04:27.391603
2842 10:04:27.391972 ==
2843 10:04:27.394716 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 10:04:27.398087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 10:04:27.401361 ==
2846 10:04:27.401925 [Gating] SW mode calibration
2847 10:04:27.410875 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2848 10:04:27.414448 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2849 10:04:27.418021 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2850 10:04:27.424442 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 10:04:27.427677 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 10:04:27.431453 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 10:04:27.437600 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 10:04:27.440937 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 10:04:27.444415 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 10:04:27.451001 0 15 28 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (0 1)
2857 10:04:27.454482 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 10:04:27.457499 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 10:04:27.464111 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 10:04:27.467042 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 10:04:27.470511 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 10:04:27.477352 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 10:04:27.480243 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2864 10:04:27.484066 1 0 28 | B1->B0 | 3333 3d3d | 0 1 | (0 0) (0 0)
2865 10:04:27.490562 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 10:04:27.494017 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 10:04:27.497177 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 10:04:27.504051 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 10:04:27.506942 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 10:04:27.510180 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 10:04:27.517056 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 10:04:27.520651 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2873 10:04:27.523568 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2874 10:04:27.530597 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 10:04:27.533694 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 10:04:27.536795 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 10:04:27.543775 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 10:04:27.546876 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 10:04:27.550515 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 10:04:27.553567 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 10:04:27.560110 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 10:04:27.563795 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 10:04:27.566889 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 10:04:27.573475 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 10:04:27.576947 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 10:04:27.580066 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 10:04:27.586664 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2888 10:04:27.590388 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2889 10:04:27.593590 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 10:04:27.596938 Total UI for P1: 0, mck2ui 16
2891 10:04:27.600520 best dqsien dly found for B0: ( 1, 3, 26)
2892 10:04:27.603770 Total UI for P1: 0, mck2ui 16
2893 10:04:27.606419 best dqsien dly found for B1: ( 1, 3, 28)
2894 10:04:27.610010 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2895 10:04:27.613488 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2896 10:04:27.614053
2897 10:04:27.620045 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2898 10:04:27.623098 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2899 10:04:27.626755 [Gating] SW calibration Done
2900 10:04:27.627319 ==
2901 10:04:27.630482 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 10:04:27.633374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 10:04:27.633941 ==
2904 10:04:27.634318 RX Vref Scan: 0
2905 10:04:27.634668
2906 10:04:27.636889 RX Vref 0 -> 0, step: 1
2907 10:04:27.637452
2908 10:04:27.640301 RX Delay -40 -> 252, step: 8
2909 10:04:27.643227 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2910 10:04:27.647038 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2911 10:04:27.653761 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2912 10:04:27.657221 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2913 10:04:27.659846 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2914 10:04:27.663258 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2915 10:04:27.666763 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2916 10:04:27.673034 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2917 10:04:27.676171 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2918 10:04:27.679468 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2919 10:04:27.683112 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2920 10:04:27.685989 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2921 10:04:27.692916 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2922 10:04:27.695944 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2923 10:04:27.699502 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2924 10:04:27.702866 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2925 10:04:27.703437 ==
2926 10:04:27.705918 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 10:04:27.712799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 10:04:27.713377 ==
2929 10:04:27.713748 DQS Delay:
2930 10:04:27.714090 DQS0 = 0, DQS1 = 0
2931 10:04:27.715998 DQM Delay:
2932 10:04:27.716557 DQM0 = 120, DQM1 = 108
2933 10:04:27.719370 DQ Delay:
2934 10:04:27.722836 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2935 10:04:27.726220 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2936 10:04:27.729193 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2937 10:04:27.732841 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2938 10:04:27.733405
2939 10:04:27.733775
2940 10:04:27.734113 ==
2941 10:04:27.736247 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 10:04:27.739386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 10:04:27.739966 ==
2944 10:04:27.740341
2945 10:04:27.742622
2946 10:04:27.743155 TX Vref Scan disable
2947 10:04:27.746117 == TX Byte 0 ==
2948 10:04:27.749225 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2949 10:04:27.753029 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2950 10:04:27.756162 == TX Byte 1 ==
2951 10:04:27.759883 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2952 10:04:27.762493 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2953 10:04:27.762964 ==
2954 10:04:27.765735 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 10:04:27.772723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 10:04:27.773328 ==
2957 10:04:27.783676 TX Vref=22, minBit 5, minWin=24, winSum=410
2958 10:04:27.787168 TX Vref=24, minBit 2, minWin=24, winSum=412
2959 10:04:27.790419 TX Vref=26, minBit 3, minWin=25, winSum=420
2960 10:04:27.793531 TX Vref=28, minBit 1, minWin=25, winSum=417
2961 10:04:27.796713 TX Vref=30, minBit 5, minWin=25, winSum=427
2962 10:04:27.803424 TX Vref=32, minBit 3, minWin=25, winSum=420
2963 10:04:27.806531 [TxChooseVref] Worse bit 5, Min win 25, Win sum 427, Final Vref 30
2964 10:04:27.807034
2965 10:04:27.809664 Final TX Range 1 Vref 30
2966 10:04:27.810136
2967 10:04:27.810508 ==
2968 10:04:27.813057 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 10:04:27.816955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 10:04:27.817543 ==
2971 10:04:27.819940
2972 10:04:27.820409
2973 10:04:27.820836 TX Vref Scan disable
2974 10:04:27.823106 == TX Byte 0 ==
2975 10:04:27.826763 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2976 10:04:27.833328 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2977 10:04:27.833905 == TX Byte 1 ==
2978 10:04:27.836684 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2979 10:04:27.843144 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2980 10:04:27.843649
2981 10:04:27.844028 [DATLAT]
2982 10:04:27.844378 Freq=1200, CH0 RK1
2983 10:04:27.844716
2984 10:04:27.846118 DATLAT Default: 0xd
2985 10:04:27.850117 0, 0xFFFF, sum = 0
2986 10:04:27.850705 1, 0xFFFF, sum = 0
2987 10:04:27.852689 2, 0xFFFF, sum = 0
2988 10:04:27.853200 3, 0xFFFF, sum = 0
2989 10:04:27.856546 4, 0xFFFF, sum = 0
2990 10:04:27.857194 5, 0xFFFF, sum = 0
2991 10:04:27.859400 6, 0xFFFF, sum = 0
2992 10:04:27.859877 7, 0xFFFF, sum = 0
2993 10:04:27.863329 8, 0xFFFF, sum = 0
2994 10:04:27.863911 9, 0xFFFF, sum = 0
2995 10:04:27.866268 10, 0xFFFF, sum = 0
2996 10:04:27.866850 11, 0xFFFF, sum = 0
2997 10:04:27.869567 12, 0x0, sum = 1
2998 10:04:27.870152 13, 0x0, sum = 2
2999 10:04:27.873226 14, 0x0, sum = 3
3000 10:04:27.873820 15, 0x0, sum = 4
3001 10:04:27.876355 best_step = 13
3002 10:04:27.876963
3003 10:04:27.877344 ==
3004 10:04:27.879352 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 10:04:27.883442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 10:04:27.884037 ==
3007 10:04:27.884421 RX Vref Scan: 0
3008 10:04:27.886545
3009 10:04:27.887121 RX Vref 0 -> 0, step: 1
3010 10:04:27.887503
3011 10:04:27.889792 RX Delay -21 -> 252, step: 4
3012 10:04:27.896195 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3013 10:04:27.899759 iDelay=195, Bit 1, Center 124 (59 ~ 190) 132
3014 10:04:27.902921 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3015 10:04:27.905859 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3016 10:04:27.909212 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3017 10:04:27.912802 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3018 10:04:27.919217 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3019 10:04:27.922535 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3020 10:04:27.925870 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3021 10:04:27.928955 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3022 10:04:27.932852 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3023 10:04:27.939334 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3024 10:04:27.942458 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3025 10:04:27.945499 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3026 10:04:27.948986 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3027 10:04:27.955681 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3028 10:04:27.956323 ==
3029 10:04:27.959085 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 10:04:27.962344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 10:04:27.962913 ==
3032 10:04:27.963398 DQS Delay:
3033 10:04:27.965493 DQS0 = 0, DQS1 = 0
3034 10:04:27.965957 DQM Delay:
3035 10:04:27.969321 DQM0 = 119, DQM1 = 107
3036 10:04:27.969884 DQ Delay:
3037 10:04:27.972570 DQ0 =118, DQ1 =124, DQ2 =116, DQ3 =114
3038 10:04:27.975644 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3039 10:04:27.978887 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3040 10:04:27.982253 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3041 10:04:27.982820
3042 10:04:27.983190
3043 10:04:27.992118 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 405 ps
3044 10:04:27.995674 CH0 RK1: MR19=403, MR18=DF5
3045 10:04:27.998803 CH0_RK1: MR19=0x403, MR18=0xDF5, DQSOSC=405, MR23=63, INC=39, DEC=26
3046 10:04:28.002032 [RxdqsGatingPostProcess] freq 1200
3047 10:04:28.008537 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3048 10:04:28.012080 best DQS0 dly(2T, 0.5T) = (0, 11)
3049 10:04:28.015187 best DQS1 dly(2T, 0.5T) = (0, 12)
3050 10:04:28.018653 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3051 10:04:28.021924 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3052 10:04:28.025478 best DQS0 dly(2T, 0.5T) = (0, 11)
3053 10:04:28.028870 best DQS1 dly(2T, 0.5T) = (0, 11)
3054 10:04:28.031903 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3055 10:04:28.035242 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3056 10:04:28.038615 Pre-setting of DQS Precalculation
3057 10:04:28.042617 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3058 10:04:28.043190 ==
3059 10:04:28.045131 Dram Type= 6, Freq= 0, CH_1, rank 0
3060 10:04:28.048728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 10:04:28.049327 ==
3062 10:04:28.055501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3063 10:04:28.061443 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3064 10:04:28.069384 [CA 0] Center 37 (7~68) winsize 62
3065 10:04:28.072980 [CA 1] Center 37 (7~68) winsize 62
3066 10:04:28.076248 [CA 2] Center 35 (5~65) winsize 61
3067 10:04:28.079440 [CA 3] Center 34 (4~65) winsize 62
3068 10:04:28.082871 [CA 4] Center 34 (4~64) winsize 61
3069 10:04:28.086152 [CA 5] Center 33 (3~64) winsize 62
3070 10:04:28.086717
3071 10:04:28.089860 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3072 10:04:28.090420
3073 10:04:28.092788 [CATrainingPosCal] consider 1 rank data
3074 10:04:28.096200 u2DelayCellTimex100 = 270/100 ps
3075 10:04:28.099426 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3076 10:04:28.102652 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3077 10:04:28.109410 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3078 10:04:28.112890 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3079 10:04:28.116070 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3080 10:04:28.119674 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3081 10:04:28.120240
3082 10:04:28.122798 CA PerBit enable=1, Macro0, CA PI delay=33
3083 10:04:28.123479
3084 10:04:28.125969 [CBTSetCACLKResult] CA Dly = 33
3085 10:04:28.126435 CS Dly: 5 (0~36)
3086 10:04:28.129131 ==
3087 10:04:28.132479 Dram Type= 6, Freq= 0, CH_1, rank 1
3088 10:04:28.135955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3089 10:04:28.136527 ==
3090 10:04:28.139452 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3091 10:04:28.145715 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3092 10:04:28.155095 [CA 0] Center 38 (8~68) winsize 61
3093 10:04:28.158343 [CA 1] Center 38 (7~69) winsize 63
3094 10:04:28.161758 [CA 2] Center 35 (5~66) winsize 62
3095 10:04:28.165454 [CA 3] Center 35 (5~65) winsize 61
3096 10:04:28.168339 [CA 4] Center 34 (4~64) winsize 61
3097 10:04:28.171931 [CA 5] Center 34 (4~64) winsize 61
3098 10:04:28.172501
3099 10:04:28.175021 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3100 10:04:28.175487
3101 10:04:28.178487 [CATrainingPosCal] consider 2 rank data
3102 10:04:28.181616 u2DelayCellTimex100 = 270/100 ps
3103 10:04:28.185154 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3104 10:04:28.191849 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3105 10:04:28.195115 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3106 10:04:28.198214 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3107 10:04:28.201535 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3108 10:04:28.205280 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3109 10:04:28.205854
3110 10:04:28.208217 CA PerBit enable=1, Macro0, CA PI delay=34
3111 10:04:28.208688
3112 10:04:28.211515 [CBTSetCACLKResult] CA Dly = 34
3113 10:04:28.212090 CS Dly: 6 (0~39)
3114 10:04:28.215003
3115 10:04:28.218011 ----->DramcWriteLeveling(PI) begin...
3116 10:04:28.218600 ==
3117 10:04:28.221688 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 10:04:28.224588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 10:04:28.225219 ==
3120 10:04:28.228977 Write leveling (Byte 0): 24 => 24
3121 10:04:28.231784 Write leveling (Byte 1): 27 => 27
3122 10:04:28.234562 DramcWriteLeveling(PI) end<-----
3123 10:04:28.235040
3124 10:04:28.235413 ==
3125 10:04:28.237783 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 10:04:28.241238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 10:04:28.241822 ==
3128 10:04:28.244448 [Gating] SW mode calibration
3129 10:04:28.251386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3130 10:04:28.258012 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3131 10:04:28.261406 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 10:04:28.264565 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 10:04:28.271557 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 10:04:28.274493 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 10:04:28.278169 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 10:04:28.284486 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 10:04:28.288004 0 15 24 | B1->B0 | 2828 2727 | 0 0 | (0 0) (1 0)
3138 10:04:28.291388 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3139 10:04:28.297934 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 10:04:28.301170 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 10:04:28.304748 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 10:04:28.307913 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 10:04:28.314621 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 10:04:28.317936 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 10:04:28.321210 1 0 24 | B1->B0 | 3434 4242 | 1 0 | (0 0) (0 0)
3146 10:04:28.327753 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 10:04:28.330929 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 10:04:28.334320 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 10:04:28.341025 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 10:04:28.344156 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 10:04:28.347231 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 10:04:28.354356 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3153 10:04:28.356963 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3154 10:04:28.360456 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3155 10:04:28.367301 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 10:04:28.370727 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 10:04:28.374378 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 10:04:28.380458 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 10:04:28.384194 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 10:04:28.387440 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 10:04:28.393855 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 10:04:28.397365 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 10:04:28.400608 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 10:04:28.407036 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 10:04:28.410200 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 10:04:28.413750 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 10:04:28.420260 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 10:04:28.423821 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 10:04:28.426932 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3170 10:04:28.433945 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 10:04:28.434518 Total UI for P1: 0, mck2ui 16
3172 10:04:28.440228 best dqsien dly found for B0: ( 1, 3, 24)
3173 10:04:28.440887 Total UI for P1: 0, mck2ui 16
3174 10:04:28.446914 best dqsien dly found for B1: ( 1, 3, 24)
3175 10:04:28.450191 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3176 10:04:28.453372 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3177 10:04:28.453840
3178 10:04:28.456869 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3179 10:04:28.460325 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3180 10:04:28.463621 [Gating] SW calibration Done
3181 10:04:28.464190 ==
3182 10:04:28.466941 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 10:04:28.469974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 10:04:28.470452 ==
3185 10:04:28.473553 RX Vref Scan: 0
3186 10:04:28.474018
3187 10:04:28.474388 RX Vref 0 -> 0, step: 1
3188 10:04:28.474735
3189 10:04:28.476793 RX Delay -40 -> 252, step: 8
3190 10:04:28.479975 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3191 10:04:28.486897 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3192 10:04:28.490224 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3193 10:04:28.493356 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3194 10:04:28.497202 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3195 10:04:28.499976 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3196 10:04:28.506898 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3197 10:04:28.510664 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3198 10:04:28.513698 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3199 10:04:28.516871 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3200 10:04:28.520132 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3201 10:04:28.523708 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3202 10:04:28.530281 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3203 10:04:28.533621 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3204 10:04:28.537099 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3205 10:04:28.540331 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3206 10:04:28.540960 ==
3207 10:04:28.543744 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 10:04:28.550423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 10:04:28.550996 ==
3210 10:04:28.551373 DQS Delay:
3211 10:04:28.553486 DQS0 = 0, DQS1 = 0
3212 10:04:28.553953 DQM Delay:
3213 10:04:28.556588 DQM0 = 119, DQM1 = 113
3214 10:04:28.557095 DQ Delay:
3215 10:04:28.560365 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3216 10:04:28.563283 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3217 10:04:28.566647 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =107
3218 10:04:28.569884 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3219 10:04:28.570356
3220 10:04:28.570727
3221 10:04:28.571073 ==
3222 10:04:28.573972 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 10:04:28.576699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 10:04:28.580236 ==
3225 10:04:28.580706
3226 10:04:28.581106
3227 10:04:28.581453 TX Vref Scan disable
3228 10:04:28.584061 == TX Byte 0 ==
3229 10:04:28.586939 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3230 10:04:28.590127 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3231 10:04:28.593675 == TX Byte 1 ==
3232 10:04:28.597350 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3233 10:04:28.600183 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3234 10:04:28.603423 ==
3235 10:04:28.606739 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 10:04:28.610075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 10:04:28.610572 ==
3238 10:04:28.621377 TX Vref=22, minBit 11, minWin=24, winSum=406
3239 10:04:28.624477 TX Vref=24, minBit 10, minWin=24, winSum=411
3240 10:04:28.627343 TX Vref=26, minBit 9, minWin=25, winSum=420
3241 10:04:28.630979 TX Vref=28, minBit 10, minWin=25, winSum=421
3242 10:04:28.634216 TX Vref=30, minBit 8, minWin=25, winSum=423
3243 10:04:28.641719 TX Vref=32, minBit 1, minWin=26, winSum=424
3244 10:04:28.644849 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 32
3245 10:04:28.645415
3246 10:04:28.647463 Final TX Range 1 Vref 32
3247 10:04:28.647936
3248 10:04:28.648311 ==
3249 10:04:28.650781 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 10:04:28.654512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 10:04:28.657580 ==
3252 10:04:28.658149
3253 10:04:28.658527
3254 10:04:28.658878 TX Vref Scan disable
3255 10:04:28.660699 == TX Byte 0 ==
3256 10:04:28.664380 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3257 10:04:28.667939 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3258 10:04:28.671446 == TX Byte 1 ==
3259 10:04:28.674394 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3260 10:04:28.677487 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3261 10:04:28.681158
3262 10:04:28.681720 [DATLAT]
3263 10:04:28.682096 Freq=1200, CH1 RK0
3264 10:04:28.682529
3265 10:04:28.684704 DATLAT Default: 0xd
3266 10:04:28.685406 0, 0xFFFF, sum = 0
3267 10:04:28.688091 1, 0xFFFF, sum = 0
3268 10:04:28.688667 2, 0xFFFF, sum = 0
3269 10:04:28.691054 3, 0xFFFF, sum = 0
3270 10:04:28.691620 4, 0xFFFF, sum = 0
3271 10:04:28.694598 5, 0xFFFF, sum = 0
3272 10:04:28.697799 6, 0xFFFF, sum = 0
3273 10:04:28.698534 7, 0xFFFF, sum = 0
3274 10:04:28.700533 8, 0xFFFF, sum = 0
3275 10:04:28.700994 9, 0xFFFF, sum = 0
3276 10:04:28.704451 10, 0xFFFF, sum = 0
3277 10:04:28.705063 11, 0xFFFF, sum = 0
3278 10:04:28.707815 12, 0x0, sum = 1
3279 10:04:28.708315 13, 0x0, sum = 2
3280 10:04:28.711196 14, 0x0, sum = 3
3281 10:04:28.711933 15, 0x0, sum = 4
3282 10:04:28.712331 best_step = 13
3283 10:04:28.714695
3284 10:04:28.715255 ==
3285 10:04:28.717680 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 10:04:28.721259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 10:04:28.721841 ==
3288 10:04:28.722423 RX Vref Scan: 1
3289 10:04:28.722805
3290 10:04:28.724451 Set Vref Range= 32 -> 127
3291 10:04:28.725044
3292 10:04:28.727402 RX Vref 32 -> 127, step: 1
3293 10:04:28.727864
3294 10:04:28.730896 RX Delay -5 -> 252, step: 4
3295 10:04:28.731357
3296 10:04:28.734139 Set Vref, RX VrefLevel [Byte0]: 32
3297 10:04:28.737525 [Byte1]: 32
3298 10:04:28.737985
3299 10:04:28.740573 Set Vref, RX VrefLevel [Byte0]: 33
3300 10:04:28.744036 [Byte1]: 33
3301 10:04:28.744574
3302 10:04:28.747491 Set Vref, RX VrefLevel [Byte0]: 34
3303 10:04:28.750461 [Byte1]: 34
3304 10:04:28.754846
3305 10:04:28.755169 Set Vref, RX VrefLevel [Byte0]: 35
3306 10:04:28.757883 [Byte1]: 35
3307 10:04:28.762468
3308 10:04:28.762731 Set Vref, RX VrefLevel [Byte0]: 36
3309 10:04:28.766087 [Byte1]: 36
3310 10:04:28.770887
3311 10:04:28.771158 Set Vref, RX VrefLevel [Byte0]: 37
3312 10:04:28.773694 [Byte1]: 37
3313 10:04:28.778173
3314 10:04:28.778382 Set Vref, RX VrefLevel [Byte0]: 38
3315 10:04:28.781361 [Byte1]: 38
3316 10:04:28.786414
3317 10:04:28.786603 Set Vref, RX VrefLevel [Byte0]: 39
3318 10:04:28.789098 [Byte1]: 39
3319 10:04:28.794212
3320 10:04:28.794436 Set Vref, RX VrefLevel [Byte0]: 40
3321 10:04:28.797074 [Byte1]: 40
3322 10:04:28.801788
3323 10:04:28.802089 Set Vref, RX VrefLevel [Byte0]: 41
3324 10:04:28.805758 [Byte1]: 41
3325 10:04:28.810035
3326 10:04:28.810493 Set Vref, RX VrefLevel [Byte0]: 42
3327 10:04:28.813451 [Byte1]: 42
3328 10:04:28.817939
3329 10:04:28.818490 Set Vref, RX VrefLevel [Byte0]: 43
3330 10:04:28.821139 [Byte1]: 43
3331 10:04:28.825652
3332 10:04:28.826205 Set Vref, RX VrefLevel [Byte0]: 44
3333 10:04:28.829433 [Byte1]: 44
3334 10:04:28.833999
3335 10:04:28.834547 Set Vref, RX VrefLevel [Byte0]: 45
3336 10:04:28.836850 [Byte1]: 45
3337 10:04:28.841449
3338 10:04:28.841991 Set Vref, RX VrefLevel [Byte0]: 46
3339 10:04:28.845190 [Byte1]: 46
3340 10:04:28.849447
3341 10:04:28.850075 Set Vref, RX VrefLevel [Byte0]: 47
3342 10:04:28.852317 [Byte1]: 47
3343 10:04:28.856968
3344 10:04:28.857426 Set Vref, RX VrefLevel [Byte0]: 48
3345 10:04:28.860651 [Byte1]: 48
3346 10:04:28.865068
3347 10:04:28.865616 Set Vref, RX VrefLevel [Byte0]: 49
3348 10:04:28.868222 [Byte1]: 49
3349 10:04:28.873350
3350 10:04:28.873901 Set Vref, RX VrefLevel [Byte0]: 50
3351 10:04:28.876080 [Byte1]: 50
3352 10:04:28.880811
3353 10:04:28.881377 Set Vref, RX VrefLevel [Byte0]: 51
3354 10:04:28.883807 [Byte1]: 51
3355 10:04:28.888503
3356 10:04:28.889107 Set Vref, RX VrefLevel [Byte0]: 52
3357 10:04:28.891981 [Byte1]: 52
3358 10:04:28.896543
3359 10:04:28.897197 Set Vref, RX VrefLevel [Byte0]: 53
3360 10:04:28.900048 [Byte1]: 53
3361 10:04:28.904312
3362 10:04:28.904911 Set Vref, RX VrefLevel [Byte0]: 54
3363 10:04:28.907390 [Byte1]: 54
3364 10:04:28.911836
3365 10:04:28.912362 Set Vref, RX VrefLevel [Byte0]: 55
3366 10:04:28.915258 [Byte1]: 55
3367 10:04:28.919836
3368 10:04:28.920392 Set Vref, RX VrefLevel [Byte0]: 56
3369 10:04:28.923265 [Byte1]: 56
3370 10:04:28.927595
3371 10:04:28.928066 Set Vref, RX VrefLevel [Byte0]: 57
3372 10:04:28.931070 [Byte1]: 57
3373 10:04:28.935557
3374 10:04:28.936116 Set Vref, RX VrefLevel [Byte0]: 58
3375 10:04:28.939104 [Byte1]: 58
3376 10:04:28.943581
3377 10:04:28.944132 Set Vref, RX VrefLevel [Byte0]: 59
3378 10:04:28.946780 [Byte1]: 59
3379 10:04:28.951376
3380 10:04:28.951932 Set Vref, RX VrefLevel [Byte0]: 60
3381 10:04:28.954553 [Byte1]: 60
3382 10:04:28.959032
3383 10:04:28.959586 Set Vref, RX VrefLevel [Byte0]: 61
3384 10:04:28.962668 [Byte1]: 61
3385 10:04:28.966953
3386 10:04:28.967542 Set Vref, RX VrefLevel [Byte0]: 62
3387 10:04:28.970693 [Byte1]: 62
3388 10:04:28.975047
3389 10:04:28.975605 Set Vref, RX VrefLevel [Byte0]: 63
3390 10:04:28.978118 [Byte1]: 63
3391 10:04:28.983270
3392 10:04:28.983827 Set Vref, RX VrefLevel [Byte0]: 64
3393 10:04:28.986092 [Byte1]: 64
3394 10:04:28.990684
3395 10:04:28.991257 Set Vref, RX VrefLevel [Byte0]: 65
3396 10:04:28.993751 [Byte1]: 65
3397 10:04:28.998782
3398 10:04:28.999477 Set Vref, RX VrefLevel [Byte0]: 66
3399 10:04:29.001975 [Byte1]: 66
3400 10:04:29.006287
3401 10:04:29.006850 Set Vref, RX VrefLevel [Byte0]: 67
3402 10:04:29.009562 [Byte1]: 67
3403 10:04:29.014297
3404 10:04:29.014858 Final RX Vref Byte 0 = 52 to rank0
3405 10:04:29.017388 Final RX Vref Byte 1 = 52 to rank0
3406 10:04:29.020725 Final RX Vref Byte 0 = 52 to rank1
3407 10:04:29.023812 Final RX Vref Byte 1 = 52 to rank1==
3408 10:04:29.027350 Dram Type= 6, Freq= 0, CH_1, rank 0
3409 10:04:29.034068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3410 10:04:29.034708 ==
3411 10:04:29.035091 DQS Delay:
3412 10:04:29.037319 DQS0 = 0, DQS1 = 0
3413 10:04:29.037882 DQM Delay:
3414 10:04:29.038257 DQM0 = 119, DQM1 = 112
3415 10:04:29.041001 DQ Delay:
3416 10:04:29.044116 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3417 10:04:29.047520 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =118
3418 10:04:29.050394 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3419 10:04:29.054058 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3420 10:04:29.054626
3421 10:04:29.055004
3422 10:04:29.063910 [DQSOSCAuto] RK0, (LSB)MR18= 0x216, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3423 10:04:29.064464 CH1 RK0: MR19=404, MR18=216
3424 10:04:29.070435 CH1_RK0: MR19=0x404, MR18=0x216, DQSOSC=401, MR23=63, INC=40, DEC=27
3425 10:04:29.071010
3426 10:04:29.073496 ----->DramcWriteLeveling(PI) begin...
3427 10:04:29.073968 ==
3428 10:04:29.077334 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 10:04:29.080466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 10:04:29.083690 ==
3431 10:04:29.086975 Write leveling (Byte 0): 25 => 25
3432 10:04:29.087442 Write leveling (Byte 1): 29 => 29
3433 10:04:29.091135 DramcWriteLeveling(PI) end<-----
3434 10:04:29.091700
3435 10:04:29.092072 ==
3436 10:04:29.093452 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 10:04:29.100498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 10:04:29.101125 ==
3439 10:04:29.104098 [Gating] SW mode calibration
3440 10:04:29.110053 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3441 10:04:29.113556 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3442 10:04:29.120139 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 10:04:29.123467 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 10:04:29.126708 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 10:04:29.133490 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 10:04:29.137061 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 10:04:29.140194 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 10:04:29.146763 0 15 24 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 0)
3449 10:04:29.150256 0 15 28 | B1->B0 | 2323 2727 | 0 1 | (1 0) (1 0)
3450 10:04:29.153251 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 10:04:29.156875 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 10:04:29.163384 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 10:04:29.166914 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 10:04:29.170412 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 10:04:29.177708 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3456 10:04:29.180155 1 0 24 | B1->B0 | 3f3f 2d2c | 0 1 | (0 0) (0 0)
3457 10:04:29.183474 1 0 28 | B1->B0 | 4646 3c3c | 0 1 | (0 0) (0 0)
3458 10:04:29.190573 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 10:04:29.193707 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 10:04:29.196542 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 10:04:29.203700 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 10:04:29.206932 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 10:04:29.209608 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 10:04:29.216602 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3465 10:04:29.219730 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3466 10:04:29.223322 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 10:04:29.229440 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 10:04:29.233090 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 10:04:29.236380 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 10:04:29.242588 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 10:04:29.246212 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 10:04:29.249492 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 10:04:29.256433 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 10:04:29.259694 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 10:04:29.262425 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 10:04:29.269034 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 10:04:29.272896 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 10:04:29.275973 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 10:04:29.282466 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 10:04:29.285826 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3481 10:04:29.289349 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3482 10:04:29.295992 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 10:04:29.296760 Total UI for P1: 0, mck2ui 16
3484 10:04:29.302440 best dqsien dly found for B0: ( 1, 3, 26)
3485 10:04:29.303031 Total UI for P1: 0, mck2ui 16
3486 10:04:29.309029 best dqsien dly found for B1: ( 1, 3, 26)
3487 10:04:29.312275 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3488 10:04:29.315613 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3489 10:04:29.316183
3490 10:04:29.318615 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3491 10:04:29.321839 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3492 10:04:29.325354 [Gating] SW calibration Done
3493 10:04:29.326003 ==
3494 10:04:29.328390 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 10:04:29.332293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 10:04:29.332920 ==
3497 10:04:29.334941 RX Vref Scan: 0
3498 10:04:29.335460
3499 10:04:29.335864 RX Vref 0 -> 0, step: 1
3500 10:04:29.336214
3501 10:04:29.338441 RX Delay -40 -> 252, step: 8
3502 10:04:29.345332 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3503 10:04:29.348741 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3504 10:04:29.351469 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3505 10:04:29.355301 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3506 10:04:29.358455 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3507 10:04:29.365063 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3508 10:04:29.368636 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3509 10:04:29.371558 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3510 10:04:29.375198 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3511 10:04:29.378163 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3512 10:04:29.384684 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3513 10:04:29.388264 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3514 10:04:29.391609 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3515 10:04:29.394725 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3516 10:04:29.397849 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3517 10:04:29.404450 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3518 10:04:29.405046 ==
3519 10:04:29.408033 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 10:04:29.410848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 10:04:29.411321 ==
3522 10:04:29.411691 DQS Delay:
3523 10:04:29.414394 DQS0 = 0, DQS1 = 0
3524 10:04:29.414860 DQM Delay:
3525 10:04:29.417853 DQM0 = 120, DQM1 = 113
3526 10:04:29.418422 DQ Delay:
3527 10:04:29.420918 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3528 10:04:29.425035 DQ4 =123, DQ5 =131, DQ6 =123, DQ7 =115
3529 10:04:29.427816 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3530 10:04:29.431053 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3531 10:04:29.434494
3532 10:04:29.434959
3533 10:04:29.435324 ==
3534 10:04:29.437481 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 10:04:29.440926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 10:04:29.441521 ==
3537 10:04:29.441900
3538 10:04:29.442241
3539 10:04:29.444316 TX Vref Scan disable
3540 10:04:29.444805 == TX Byte 0 ==
3541 10:04:29.450576 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3542 10:04:29.453791 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3543 10:04:29.454354 == TX Byte 1 ==
3544 10:04:29.461225 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3545 10:04:29.464315 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3546 10:04:29.464958 ==
3547 10:04:29.467414 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 10:04:29.470853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 10:04:29.471433 ==
3550 10:04:29.483257 TX Vref=22, minBit 1, minWin=25, winSum=416
3551 10:04:29.487070 TX Vref=24, minBit 1, minWin=25, winSum=424
3552 10:04:29.490078 TX Vref=26, minBit 1, minWin=26, winSum=428
3553 10:04:29.493357 TX Vref=28, minBit 3, minWin=26, winSum=430
3554 10:04:29.496980 TX Vref=30, minBit 3, minWin=26, winSum=426
3555 10:04:29.503352 TX Vref=32, minBit 9, minWin=25, winSum=427
3556 10:04:29.506565 [TxChooseVref] Worse bit 3, Min win 26, Win sum 430, Final Vref 28
3557 10:04:29.507138
3558 10:04:29.509417 Final TX Range 1 Vref 28
3559 10:04:29.510066
3560 10:04:29.510547 ==
3561 10:04:29.513124 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 10:04:29.516219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 10:04:29.520112 ==
3564 10:04:29.520685
3565 10:04:29.521115
3566 10:04:29.521527 TX Vref Scan disable
3567 10:04:29.522767 == TX Byte 0 ==
3568 10:04:29.526344 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3569 10:04:29.533351 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3570 10:04:29.533932 == TX Byte 1 ==
3571 10:04:29.536634 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3572 10:04:29.542626 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3573 10:04:29.543233
3574 10:04:29.543610 [DATLAT]
3575 10:04:29.543958 Freq=1200, CH1 RK1
3576 10:04:29.544297
3577 10:04:29.546475 DATLAT Default: 0xd
3578 10:04:29.549347 0, 0xFFFF, sum = 0
3579 10:04:29.549928 1, 0xFFFF, sum = 0
3580 10:04:29.552522 2, 0xFFFF, sum = 0
3581 10:04:29.553120 3, 0xFFFF, sum = 0
3582 10:04:29.556442 4, 0xFFFF, sum = 0
3583 10:04:29.557082 5, 0xFFFF, sum = 0
3584 10:04:29.559394 6, 0xFFFF, sum = 0
3585 10:04:29.559901 7, 0xFFFF, sum = 0
3586 10:04:29.562717 8, 0xFFFF, sum = 0
3587 10:04:29.563190 9, 0xFFFF, sum = 0
3588 10:04:29.565847 10, 0xFFFF, sum = 0
3589 10:04:29.566475 11, 0xFFFF, sum = 0
3590 10:04:29.569160 12, 0x0, sum = 1
3591 10:04:29.569728 13, 0x0, sum = 2
3592 10:04:29.572600 14, 0x0, sum = 3
3593 10:04:29.573089 15, 0x0, sum = 4
3594 10:04:29.576182 best_step = 13
3595 10:04:29.576757
3596 10:04:29.577162 ==
3597 10:04:29.579286 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 10:04:29.582217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 10:04:29.582689 ==
3600 10:04:29.585372 RX Vref Scan: 0
3601 10:04:29.585836
3602 10:04:29.586205 RX Vref 0 -> 0, step: 1
3603 10:04:29.586550
3604 10:04:29.589217 RX Delay -13 -> 252, step: 4
3605 10:04:29.595741 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3606 10:04:29.599321 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3607 10:04:29.602225 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3608 10:04:29.605516 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3609 10:04:29.609112 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3610 10:04:29.615743 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3611 10:04:29.618756 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3612 10:04:29.621792 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3613 10:04:29.625279 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3614 10:04:29.628685 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3615 10:04:29.635078 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3616 10:04:29.638868 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3617 10:04:29.641736 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3618 10:04:29.645323 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3619 10:04:29.651037 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3620 10:04:29.654589 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3621 10:04:29.655164 ==
3622 10:04:29.657684 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 10:04:29.661426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 10:04:29.661896 ==
3625 10:04:29.664170 DQS Delay:
3626 10:04:29.664651 DQS0 = 0, DQS1 = 0
3627 10:04:29.665136 DQM Delay:
3628 10:04:29.667509 DQM0 = 119, DQM1 = 113
3629 10:04:29.667975 DQ Delay:
3630 10:04:29.671334 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3631 10:04:29.675121 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3632 10:04:29.681157 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3633 10:04:29.684715 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3634 10:04:29.685301
3635 10:04:29.685673
3636 10:04:29.691328 [DQSOSCAuto] RK1, (LSB)MR18= 0x6ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 407 ps
3637 10:04:29.694293 CH1 RK1: MR19=403, MR18=6EA
3638 10:04:29.701183 CH1_RK1: MR19=0x403, MR18=0x6EA, DQSOSC=407, MR23=63, INC=39, DEC=26
3639 10:04:29.704559 [RxdqsGatingPostProcess] freq 1200
3640 10:04:29.707762 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3641 10:04:29.710732 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 10:04:29.713735 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 10:04:29.717695 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 10:04:29.720364 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 10:04:29.723940 best DQS0 dly(2T, 0.5T) = (0, 11)
3646 10:04:29.727262 best DQS1 dly(2T, 0.5T) = (0, 11)
3647 10:04:29.730383 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3648 10:04:29.734084 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3649 10:04:29.737316 Pre-setting of DQS Precalculation
3650 10:04:29.740811 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3651 10:04:29.750441 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3652 10:04:29.756867 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3653 10:04:29.757333
3654 10:04:29.757703
3655 10:04:29.760097 [Calibration Summary] 2400 Mbps
3656 10:04:29.760659 CH 0, Rank 0
3657 10:04:29.763081 SW Impedance : PASS
3658 10:04:29.766909 DUTY Scan : NO K
3659 10:04:29.767487 ZQ Calibration : PASS
3660 10:04:29.770133 Jitter Meter : NO K
3661 10:04:29.773228 CBT Training : PASS
3662 10:04:29.773699 Write leveling : PASS
3663 10:04:29.776420 RX DQS gating : PASS
3664 10:04:29.776941 RX DQ/DQS(RDDQC) : PASS
3665 10:04:29.779575 TX DQ/DQS : PASS
3666 10:04:29.782828 RX DATLAT : PASS
3667 10:04:29.783301 RX DQ/DQS(Engine): PASS
3668 10:04:29.786501 TX OE : NO K
3669 10:04:29.787073 All Pass.
3670 10:04:29.787446
3671 10:04:29.789495 CH 0, Rank 1
3672 10:04:29.789978 SW Impedance : PASS
3673 10:04:29.792942 DUTY Scan : NO K
3674 10:04:29.796254 ZQ Calibration : PASS
3675 10:04:29.796877 Jitter Meter : NO K
3676 10:04:29.800066 CBT Training : PASS
3677 10:04:29.802991 Write leveling : PASS
3678 10:04:29.803558 RX DQS gating : PASS
3679 10:04:29.806606 RX DQ/DQS(RDDQC) : PASS
3680 10:04:29.809635 TX DQ/DQS : PASS
3681 10:04:29.810231 RX DATLAT : PASS
3682 10:04:29.813163 RX DQ/DQS(Engine): PASS
3683 10:04:29.816511 TX OE : NO K
3684 10:04:29.817113 All Pass.
3685 10:04:29.817484
3686 10:04:29.817828 CH 1, Rank 0
3687 10:04:29.819509 SW Impedance : PASS
3688 10:04:29.822631 DUTY Scan : NO K
3689 10:04:29.823096 ZQ Calibration : PASS
3690 10:04:29.826607 Jitter Meter : NO K
3691 10:04:29.829305 CBT Training : PASS
3692 10:04:29.829920 Write leveling : PASS
3693 10:04:29.832730 RX DQS gating : PASS
3694 10:04:29.836020 RX DQ/DQS(RDDQC) : PASS
3695 10:04:29.836588 TX DQ/DQS : PASS
3696 10:04:29.839511 RX DATLAT : PASS
3697 10:04:29.840074 RX DQ/DQS(Engine): PASS
3698 10:04:29.842619 TX OE : NO K
3699 10:04:29.843186 All Pass.
3700 10:04:29.843556
3701 10:04:29.845936 CH 1, Rank 1
3702 10:04:29.846504 SW Impedance : PASS
3703 10:04:29.849431 DUTY Scan : NO K
3704 10:04:29.852973 ZQ Calibration : PASS
3705 10:04:29.853539 Jitter Meter : NO K
3706 10:04:29.855759 CBT Training : PASS
3707 10:04:29.859208 Write leveling : PASS
3708 10:04:29.859768 RX DQS gating : PASS
3709 10:04:29.862379 RX DQ/DQS(RDDQC) : PASS
3710 10:04:29.865814 TX DQ/DQS : PASS
3711 10:04:29.866279 RX DATLAT : PASS
3712 10:04:29.869249 RX DQ/DQS(Engine): PASS
3713 10:04:29.872436 TX OE : NO K
3714 10:04:29.873045 All Pass.
3715 10:04:29.873429
3716 10:04:29.873771 DramC Write-DBI off
3717 10:04:29.876005 PER_BANK_REFRESH: Hybrid Mode
3718 10:04:29.878921 TX_TRACKING: ON
3719 10:04:29.886080 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3720 10:04:29.892736 [FAST_K] Save calibration result to emmc
3721 10:04:29.895806 dramc_set_vcore_voltage set vcore to 650000
3722 10:04:29.896399 Read voltage for 600, 5
3723 10:04:29.899342 Vio18 = 0
3724 10:04:29.899898 Vcore = 650000
3725 10:04:29.900269 Vdram = 0
3726 10:04:29.902447 Vddq = 0
3727 10:04:29.903012 Vmddr = 0
3728 10:04:29.905915 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3729 10:04:29.912611 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3730 10:04:29.916025 MEM_TYPE=3, freq_sel=19
3731 10:04:29.919082 sv_algorithm_assistance_LP4_1600
3732 10:04:29.922384 ============ PULL DRAM RESETB DOWN ============
3733 10:04:29.925803 ========== PULL DRAM RESETB DOWN end =========
3734 10:04:29.932511 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3735 10:04:29.935651 ===================================
3736 10:04:29.936219 LPDDR4 DRAM CONFIGURATION
3737 10:04:29.939156 ===================================
3738 10:04:29.942393 EX_ROW_EN[0] = 0x0
3739 10:04:29.942955 EX_ROW_EN[1] = 0x0
3740 10:04:29.945716 LP4Y_EN = 0x0
3741 10:04:29.946286 WORK_FSP = 0x0
3742 10:04:29.949039 WL = 0x2
3743 10:04:29.949604 RL = 0x2
3744 10:04:29.952435 BL = 0x2
3745 10:04:29.953024 RPST = 0x0
3746 10:04:29.955271 RD_PRE = 0x0
3747 10:04:29.959255 WR_PRE = 0x1
3748 10:04:29.959814 WR_PST = 0x0
3749 10:04:29.962580 DBI_WR = 0x0
3750 10:04:29.963185 DBI_RD = 0x0
3751 10:04:29.965291 OTF = 0x1
3752 10:04:29.968584 ===================================
3753 10:04:29.971913 ===================================
3754 10:04:29.972469 ANA top config
3755 10:04:29.975533 ===================================
3756 10:04:29.978811 DLL_ASYNC_EN = 0
3757 10:04:29.982081 ALL_SLAVE_EN = 1
3758 10:04:29.982645 NEW_RANK_MODE = 1
3759 10:04:29.985329 DLL_IDLE_MODE = 1
3760 10:04:29.988858 LP45_APHY_COMB_EN = 1
3761 10:04:29.992119 TX_ODT_DIS = 1
3762 10:04:29.992685 NEW_8X_MODE = 1
3763 10:04:29.995214 ===================================
3764 10:04:29.998787 ===================================
3765 10:04:30.001797 data_rate = 1200
3766 10:04:30.005650 CKR = 1
3767 10:04:30.008582 DQ_P2S_RATIO = 8
3768 10:04:30.011668 ===================================
3769 10:04:30.015457 CA_P2S_RATIO = 8
3770 10:04:30.018547 DQ_CA_OPEN = 0
3771 10:04:30.021640 DQ_SEMI_OPEN = 0
3772 10:04:30.022201 CA_SEMI_OPEN = 0
3773 10:04:30.025304 CA_FULL_RATE = 0
3774 10:04:30.028521 DQ_CKDIV4_EN = 1
3775 10:04:30.031229 CA_CKDIV4_EN = 1
3776 10:04:30.034830 CA_PREDIV_EN = 0
3777 10:04:30.038273 PH8_DLY = 0
3778 10:04:30.038965 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3779 10:04:30.041776 DQ_AAMCK_DIV = 4
3780 10:04:30.045314 CA_AAMCK_DIV = 4
3781 10:04:30.048421 CA_ADMCK_DIV = 4
3782 10:04:30.051416 DQ_TRACK_CA_EN = 0
3783 10:04:30.054431 CA_PICK = 600
3784 10:04:30.055016 CA_MCKIO = 600
3785 10:04:30.058129 MCKIO_SEMI = 0
3786 10:04:30.061521 PLL_FREQ = 2288
3787 10:04:30.064904 DQ_UI_PI_RATIO = 32
3788 10:04:30.067842 CA_UI_PI_RATIO = 0
3789 10:04:30.071414 ===================================
3790 10:04:30.074764 ===================================
3791 10:04:30.077521 memory_type:LPDDR4
3792 10:04:30.077986 GP_NUM : 10
3793 10:04:30.081237 SRAM_EN : 1
3794 10:04:30.081696 MD32_EN : 0
3795 10:04:30.084472 ===================================
3796 10:04:30.087434 [ANA_INIT] >>>>>>>>>>>>>>
3797 10:04:30.091209 <<<<<< [CONFIGURE PHASE]: ANA_TX
3798 10:04:30.094077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3799 10:04:30.097762 ===================================
3800 10:04:30.100701 data_rate = 1200,PCW = 0X5800
3801 10:04:30.104166 ===================================
3802 10:04:30.107475 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3803 10:04:30.114319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3804 10:04:30.119263 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 10:04:30.124091 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3806 10:04:30.127222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3807 10:04:30.130525 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3808 10:04:30.130991 [ANA_INIT] flow start
3809 10:04:30.133737 [ANA_INIT] PLL >>>>>>>>
3810 10:04:30.137003 [ANA_INIT] PLL <<<<<<<<
3811 10:04:30.137557 [ANA_INIT] MIDPI >>>>>>>>
3812 10:04:30.140670 [ANA_INIT] MIDPI <<<<<<<<
3813 10:04:30.143793 [ANA_INIT] DLL >>>>>>>>
3814 10:04:30.144360 [ANA_INIT] flow end
3815 10:04:30.150216 ============ LP4 DIFF to SE enter ============
3816 10:04:30.153812 ============ LP4 DIFF to SE exit ============
3817 10:04:30.156929 [ANA_INIT] <<<<<<<<<<<<<
3818 10:04:30.160476 [Flow] Enable top DCM control >>>>>
3819 10:04:30.163322 [Flow] Enable top DCM control <<<<<
3820 10:04:30.166813 Enable DLL master slave shuffle
3821 10:04:30.169957 ==============================================================
3822 10:04:30.173308 Gating Mode config
3823 10:04:30.176455 ==============================================================
3824 10:04:30.179631 Config description:
3825 10:04:30.189639 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3826 10:04:30.196353 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3827 10:04:30.199795 SELPH_MODE 0: By rank 1: By Phase
3828 10:04:30.206420 ==============================================================
3829 10:04:30.209732 GAT_TRACK_EN = 1
3830 10:04:30.212870 RX_GATING_MODE = 2
3831 10:04:30.216328 RX_GATING_TRACK_MODE = 2
3832 10:04:30.219716 SELPH_MODE = 1
3833 10:04:30.223098 PICG_EARLY_EN = 1
3834 10:04:30.226536 VALID_LAT_VALUE = 1
3835 10:04:30.229566 ==============================================================
3836 10:04:30.232992 Enter into Gating configuration >>>>
3837 10:04:30.236155 Exit from Gating configuration <<<<
3838 10:04:30.239540 Enter into DVFS_PRE_config >>>>>
3839 10:04:30.252811 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3840 10:04:30.253384 Exit from DVFS_PRE_config <<<<<
3841 10:04:30.255970 Enter into PICG configuration >>>>
3842 10:04:30.259279 Exit from PICG configuration <<<<
3843 10:04:30.262771 [RX_INPUT] configuration >>>>>
3844 10:04:30.265845 [RX_INPUT] configuration <<<<<
3845 10:04:30.272827 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3846 10:04:30.276048 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3847 10:04:30.282484 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3848 10:04:30.289196 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3849 10:04:30.295784 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3850 10:04:30.302525 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3851 10:04:30.305626 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3852 10:04:30.308867 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3853 10:04:30.312234 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3854 10:04:30.318897 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3855 10:04:30.322676 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3856 10:04:30.325701 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3857 10:04:30.329017 ===================================
3858 10:04:30.332188 LPDDR4 DRAM CONFIGURATION
3859 10:04:30.335810 ===================================
3860 10:04:30.339060 EX_ROW_EN[0] = 0x0
3861 10:04:30.339628 EX_ROW_EN[1] = 0x0
3862 10:04:30.342403 LP4Y_EN = 0x0
3863 10:04:30.342970 WORK_FSP = 0x0
3864 10:04:30.345218 WL = 0x2
3865 10:04:30.345687 RL = 0x2
3866 10:04:30.348825 BL = 0x2
3867 10:04:30.349395 RPST = 0x0
3868 10:04:30.352341 RD_PRE = 0x0
3869 10:04:30.353051 WR_PRE = 0x1
3870 10:04:30.355285 WR_PST = 0x0
3871 10:04:30.355758 DBI_WR = 0x0
3872 10:04:30.358889 DBI_RD = 0x0
3873 10:04:30.359564 OTF = 0x1
3874 10:04:30.362157 ===================================
3875 10:04:30.368605 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3876 10:04:30.372345 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3877 10:04:30.375204 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3878 10:04:30.378720 ===================================
3879 10:04:30.381720 LPDDR4 DRAM CONFIGURATION
3880 10:04:30.384966 ===================================
3881 10:04:30.388477 EX_ROW_EN[0] = 0x10
3882 10:04:30.389021 EX_ROW_EN[1] = 0x0
3883 10:04:30.391677 LP4Y_EN = 0x0
3884 10:04:30.392137 WORK_FSP = 0x0
3885 10:04:30.394626 WL = 0x2
3886 10:04:30.395098 RL = 0x2
3887 10:04:30.398185 BL = 0x2
3888 10:04:30.398649 RPST = 0x0
3889 10:04:30.401389 RD_PRE = 0x0
3890 10:04:30.401856 WR_PRE = 0x1
3891 10:04:30.404756 WR_PST = 0x0
3892 10:04:30.405275 DBI_WR = 0x0
3893 10:04:30.408326 DBI_RD = 0x0
3894 10:04:30.408654 OTF = 0x1
3895 10:04:30.411508 ===================================
3896 10:04:30.417772 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3897 10:04:30.422428 nWR fixed to 30
3898 10:04:30.426027 [ModeRegInit_LP4] CH0 RK0
3899 10:04:30.426188 [ModeRegInit_LP4] CH0 RK1
3900 10:04:30.429284 [ModeRegInit_LP4] CH1 RK0
3901 10:04:30.432178 [ModeRegInit_LP4] CH1 RK1
3902 10:04:30.432314 match AC timing 17
3903 10:04:30.438753 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3904 10:04:30.441964 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3905 10:04:30.445619 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3906 10:04:30.452173 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3907 10:04:30.455421 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3908 10:04:30.455511 ==
3909 10:04:30.458767 Dram Type= 6, Freq= 0, CH_0, rank 0
3910 10:04:30.461787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3911 10:04:30.461880 ==
3912 10:04:30.468711 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3913 10:04:30.475035 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3914 10:04:30.478615 [CA 0] Center 36 (6~67) winsize 62
3915 10:04:30.481852 [CA 1] Center 36 (6~67) winsize 62
3916 10:04:30.485622 [CA 2] Center 34 (4~65) winsize 62
3917 10:04:30.488583 [CA 3] Center 34 (3~65) winsize 63
3918 10:04:30.492013 [CA 4] Center 33 (3~64) winsize 62
3919 10:04:30.495099 [CA 5] Center 33 (2~64) winsize 63
3920 10:04:30.495532
3921 10:04:30.498679 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3922 10:04:30.499113
3923 10:04:30.501987 [CATrainingPosCal] consider 1 rank data
3924 10:04:30.505189 u2DelayCellTimex100 = 270/100 ps
3925 10:04:30.508895 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3926 10:04:30.511945 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3927 10:04:30.515386 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3928 10:04:30.518605 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3929 10:04:30.525128 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3930 10:04:30.528477 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3931 10:04:30.528943
3932 10:04:30.531824 CA PerBit enable=1, Macro0, CA PI delay=33
3933 10:04:30.532256
3934 10:04:30.535081 [CBTSetCACLKResult] CA Dly = 33
3935 10:04:30.535517 CS Dly: 5 (0~36)
3936 10:04:30.535950 ==
3937 10:04:30.538226 Dram Type= 6, Freq= 0, CH_0, rank 1
3938 10:04:30.544920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3939 10:04:30.545359 ==
3940 10:04:30.548038 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3941 10:04:30.554834 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3942 10:04:30.558037 [CA 0] Center 36 (6~67) winsize 62
3943 10:04:30.561264 [CA 1] Center 36 (6~67) winsize 62
3944 10:04:30.564857 [CA 2] Center 34 (4~65) winsize 62
3945 10:04:30.567740 [CA 3] Center 34 (4~65) winsize 62
3946 10:04:30.571205 [CA 4] Center 34 (3~65) winsize 63
3947 10:04:30.574473 [CA 5] Center 33 (3~64) winsize 62
3948 10:04:30.574891
3949 10:04:30.577754 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3950 10:04:30.578170
3951 10:04:30.581098 [CATrainingPosCal] consider 2 rank data
3952 10:04:30.584418 u2DelayCellTimex100 = 270/100 ps
3953 10:04:30.587677 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3954 10:04:30.594100 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3955 10:04:30.597730 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3956 10:04:30.600886 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3957 10:04:30.604167 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3958 10:04:30.607270 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3959 10:04:30.607689
3960 10:04:30.611081 CA PerBit enable=1, Macro0, CA PI delay=33
3961 10:04:30.611540
3962 10:04:30.614415 [CBTSetCACLKResult] CA Dly = 33
3963 10:04:30.617627 CS Dly: 5 (0~37)
3964 10:04:30.618043
3965 10:04:30.620871 ----->DramcWriteLeveling(PI) begin...
3966 10:04:30.621295 ==
3967 10:04:30.623952 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 10:04:30.627274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 10:04:30.627695 ==
3970 10:04:30.630702 Write leveling (Byte 0): 33 => 33
3971 10:04:30.633918 Write leveling (Byte 1): 31 => 31
3972 10:04:30.636914 DramcWriteLeveling(PI) end<-----
3973 10:04:30.637333
3974 10:04:30.637662 ==
3975 10:04:30.640000 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 10:04:30.643845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 10:04:30.644266 ==
3978 10:04:30.646776 [Gating] SW mode calibration
3979 10:04:30.653550 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3980 10:04:30.660385 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3981 10:04:30.663074 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 10:04:30.666703 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 10:04:30.673143 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 10:04:30.676292 0 9 12 | B1->B0 | 3434 3030 | 0 0 | (0 0) (1 0)
3985 10:04:30.679519 0 9 16 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
3986 10:04:30.686315 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 10:04:30.689457 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 10:04:30.696640 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 10:04:30.699508 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 10:04:30.702843 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 10:04:30.709080 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3992 10:04:30.712577 0 10 12 | B1->B0 | 2424 3737 | 0 0 | (0 0) (1 1)
3993 10:04:30.715552 0 10 16 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
3994 10:04:30.722658 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 10:04:30.725841 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 10:04:30.728906 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 10:04:30.735576 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 10:04:30.739125 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 10:04:30.742287 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 10:04:30.748956 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4001 10:04:30.752465 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4002 10:04:30.755583 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 10:04:30.758821 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 10:04:30.765394 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 10:04:30.768636 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 10:04:30.771726 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 10:04:30.778531 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 10:04:30.782063 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 10:04:30.785044 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 10:04:30.791680 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 10:04:30.795123 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 10:04:30.801701 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 10:04:30.804816 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 10:04:30.808312 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 10:04:30.814755 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 10:04:30.817857 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4017 10:04:30.821371 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4018 10:04:30.824693 Total UI for P1: 0, mck2ui 16
4019 10:04:30.828019 best dqsien dly found for B0: ( 0, 13, 12)
4020 10:04:30.831217 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 10:04:30.834472 Total UI for P1: 0, mck2ui 16
4022 10:04:30.837748 best dqsien dly found for B1: ( 0, 13, 16)
4023 10:04:30.844850 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4024 10:04:30.847618 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4025 10:04:30.848041
4026 10:04:30.851085 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4027 10:04:30.854429 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4028 10:04:30.857461 [Gating] SW calibration Done
4029 10:04:30.857883 ==
4030 10:04:30.861051 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 10:04:30.863982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 10:04:30.864405 ==
4033 10:04:30.867644 RX Vref Scan: 0
4034 10:04:30.868063
4035 10:04:30.868398 RX Vref 0 -> 0, step: 1
4036 10:04:30.868710
4037 10:04:30.870811 RX Delay -230 -> 252, step: 16
4038 10:04:30.874325 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4039 10:04:30.880999 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4040 10:04:30.884154 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4041 10:04:30.887625 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4042 10:04:30.890775 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4043 10:04:30.897383 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4044 10:04:30.900794 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4045 10:04:30.903969 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4046 10:04:30.907096 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4047 10:04:30.913943 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4048 10:04:30.917070 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4049 10:04:30.920834 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4050 10:04:30.923762 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4051 10:04:30.930349 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4052 10:04:30.933640 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4053 10:04:30.936546 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4054 10:04:30.936654 ==
4055 10:04:30.939912 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 10:04:30.943289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 10:04:30.943372 ==
4058 10:04:30.946469 DQS Delay:
4059 10:04:30.946552 DQS0 = 0, DQS1 = 0
4060 10:04:30.949574 DQM Delay:
4061 10:04:30.949656 DQM0 = 51, DQM1 = 42
4062 10:04:30.949722 DQ Delay:
4063 10:04:30.953184 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4064 10:04:30.956395 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4065 10:04:30.959976 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4066 10:04:30.963474 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4067 10:04:30.963556
4068 10:04:30.966211
4069 10:04:30.966293 ==
4070 10:04:30.969656 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 10:04:30.972748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 10:04:30.972872 ==
4073 10:04:30.972939
4074 10:04:30.972998
4075 10:04:30.976261 TX Vref Scan disable
4076 10:04:30.976343 == TX Byte 0 ==
4077 10:04:30.982514 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4078 10:04:30.986052 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4079 10:04:30.986135 == TX Byte 1 ==
4080 10:04:30.992334 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4081 10:04:30.996041 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4082 10:04:30.996124 ==
4083 10:04:30.998982 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 10:04:31.002214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 10:04:31.002297 ==
4086 10:04:31.002363
4087 10:04:31.002422
4088 10:04:31.005943 TX Vref Scan disable
4089 10:04:31.009313 == TX Byte 0 ==
4090 10:04:31.012232 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4091 10:04:31.015882 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4092 10:04:31.018854 == TX Byte 1 ==
4093 10:04:31.022490 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4094 10:04:31.028961 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4095 10:04:31.029043
4096 10:04:31.029107 [DATLAT]
4097 10:04:31.029166 Freq=600, CH0 RK0
4098 10:04:31.029223
4099 10:04:31.032137 DATLAT Default: 0x9
4100 10:04:31.032217 0, 0xFFFF, sum = 0
4101 10:04:31.035367 1, 0xFFFF, sum = 0
4102 10:04:31.035449 2, 0xFFFF, sum = 0
4103 10:04:31.039289 3, 0xFFFF, sum = 0
4104 10:04:31.042052 4, 0xFFFF, sum = 0
4105 10:04:31.042135 5, 0xFFFF, sum = 0
4106 10:04:31.045223 6, 0xFFFF, sum = 0
4107 10:04:31.045305 7, 0xFFFF, sum = 0
4108 10:04:31.048687 8, 0x0, sum = 1
4109 10:04:31.048774 9, 0x0, sum = 2
4110 10:04:31.048854 10, 0x0, sum = 3
4111 10:04:31.052056 11, 0x0, sum = 4
4112 10:04:31.052138 best_step = 9
4113 10:04:31.052202
4114 10:04:31.052260 ==
4115 10:04:31.055423 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 10:04:31.061923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 10:04:31.062005 ==
4118 10:04:31.062069 RX Vref Scan: 1
4119 10:04:31.062129
4120 10:04:31.064964 RX Vref 0 -> 0, step: 1
4121 10:04:31.065045
4122 10:04:31.068695 RX Delay -163 -> 252, step: 8
4123 10:04:31.068852
4124 10:04:31.071533 Set Vref, RX VrefLevel [Byte0]: 57
4125 10:04:31.075007 [Byte1]: 48
4126 10:04:31.075088
4127 10:04:31.078030 Final RX Vref Byte 0 = 57 to rank0
4128 10:04:31.081335 Final RX Vref Byte 1 = 48 to rank0
4129 10:04:31.084898 Final RX Vref Byte 0 = 57 to rank1
4130 10:04:31.087913 Final RX Vref Byte 1 = 48 to rank1==
4131 10:04:31.092116 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 10:04:31.094986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 10:04:31.097953 ==
4134 10:04:31.098033 DQS Delay:
4135 10:04:31.098134 DQS0 = 0, DQS1 = 0
4136 10:04:31.101553 DQM Delay:
4137 10:04:31.101633 DQM0 = 49, DQM1 = 37
4138 10:04:31.104402 DQ Delay:
4139 10:04:31.104483 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4140 10:04:31.108014 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4141 10:04:31.111059 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4142 10:04:31.114839 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4143 10:04:31.117606
4144 10:04:31.117686
4145 10:04:31.124265 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c55, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4146 10:04:31.127532 CH0 RK0: MR19=808, MR18=5C55
4147 10:04:31.134086 CH0_RK0: MR19=0x808, MR18=0x5C55, DQSOSC=392, MR23=63, INC=170, DEC=113
4148 10:04:31.134168
4149 10:04:31.137629 ----->DramcWriteLeveling(PI) begin...
4150 10:04:31.137712 ==
4151 10:04:31.141332 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 10:04:31.144355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 10:04:31.144436 ==
4154 10:04:31.147540 Write leveling (Byte 0): 34 => 34
4155 10:04:31.150687 Write leveling (Byte 1): 30 => 30
4156 10:04:31.154321 DramcWriteLeveling(PI) end<-----
4157 10:04:31.154427
4158 10:04:31.154559 ==
4159 10:04:31.157289 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 10:04:31.160651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 10:04:31.160751 ==
4162 10:04:31.163817 [Gating] SW mode calibration
4163 10:04:31.170470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4164 10:04:31.176958 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4165 10:04:31.180392 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 10:04:31.187181 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 10:04:31.190370 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4168 10:04:31.193893 0 9 12 | B1->B0 | 3333 3131 | 0 0 | (0 1) (1 0)
4169 10:04:31.199955 0 9 16 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4170 10:04:31.203572 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 10:04:31.207095 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 10:04:31.213385 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 10:04:31.217014 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 10:04:31.219865 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 10:04:31.226491 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 10:04:31.230208 0 10 12 | B1->B0 | 3232 3737 | 0 0 | (0 0) (0 0)
4177 10:04:31.233683 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4178 10:04:31.236663 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 10:04:31.243456 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 10:04:31.246567 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 10:04:31.249927 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 10:04:31.256958 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 10:04:31.259987 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 10:04:31.263012 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4185 10:04:31.269477 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 10:04:31.273078 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 10:04:31.276229 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 10:04:31.282841 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 10:04:31.286260 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 10:04:31.289786 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 10:04:31.296712 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 10:04:31.299616 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 10:04:31.302921 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 10:04:31.309576 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 10:04:31.313079 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 10:04:31.316489 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 10:04:31.322895 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 10:04:31.326138 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 10:04:31.329909 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 10:04:31.336455 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4201 10:04:31.339406 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 10:04:31.343193 Total UI for P1: 0, mck2ui 16
4203 10:04:31.345821 best dqsien dly found for B0: ( 0, 13, 12)
4204 10:04:31.349340 Total UI for P1: 0, mck2ui 16
4205 10:04:31.352739 best dqsien dly found for B1: ( 0, 13, 12)
4206 10:04:31.356172 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4207 10:04:31.358920 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4208 10:04:31.359016
4209 10:04:31.362376 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4210 10:04:31.368773 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4211 10:04:31.368900 [Gating] SW calibration Done
4212 10:04:31.368967 ==
4213 10:04:31.372043 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 10:04:31.378840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 10:04:31.378979 ==
4216 10:04:31.379078 RX Vref Scan: 0
4217 10:04:31.379170
4218 10:04:31.382178 RX Vref 0 -> 0, step: 1
4219 10:04:31.382275
4220 10:04:31.385485 RX Delay -230 -> 252, step: 16
4221 10:04:31.388892 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4222 10:04:31.392082 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4223 10:04:31.395604 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4224 10:04:31.401959 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4225 10:04:31.405433 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4226 10:04:31.408812 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4227 10:04:31.411827 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4228 10:04:31.418334 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4229 10:04:31.421904 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4230 10:04:31.425093 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4231 10:04:31.428418 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4232 10:04:31.434972 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4233 10:04:31.438743 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4234 10:04:31.441690 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4235 10:04:31.445123 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4236 10:04:31.452004 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4237 10:04:31.452100 ==
4238 10:04:31.454725 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 10:04:31.458185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 10:04:31.458328 ==
4241 10:04:31.458454 DQS Delay:
4242 10:04:31.461453 DQS0 = 0, DQS1 = 0
4243 10:04:31.461638 DQM Delay:
4244 10:04:31.465043 DQM0 = 48, DQM1 = 42
4245 10:04:31.465169 DQ Delay:
4246 10:04:31.468089 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =49
4247 10:04:31.471565 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4248 10:04:31.475193 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4249 10:04:31.478101 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4250 10:04:31.478379
4251 10:04:31.478534
4252 10:04:31.478672 ==
4253 10:04:31.481196 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 10:04:31.484844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 10:04:31.485179 ==
4256 10:04:31.488096
4257 10:04:31.488371
4258 10:04:31.488563 TX Vref Scan disable
4259 10:04:31.491241 == TX Byte 0 ==
4260 10:04:31.494550 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4261 10:04:31.498285 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4262 10:04:31.501235 == TX Byte 1 ==
4263 10:04:31.504752 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4264 10:04:31.508112 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4265 10:04:31.508538 ==
4266 10:04:31.511716 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 10:04:31.517855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 10:04:31.518279 ==
4269 10:04:31.518616
4270 10:04:31.518928
4271 10:04:31.521284 TX Vref Scan disable
4272 10:04:31.521705 == TX Byte 0 ==
4273 10:04:31.527927 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4274 10:04:31.531450 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4275 10:04:31.531941 == TX Byte 1 ==
4276 10:04:31.537979 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4277 10:04:31.541033 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4278 10:04:31.541456
4279 10:04:31.541792 [DATLAT]
4280 10:04:31.544374 Freq=600, CH0 RK1
4281 10:04:31.544838
4282 10:04:31.545183 DATLAT Default: 0x9
4283 10:04:31.547583 0, 0xFFFF, sum = 0
4284 10:04:31.550896 1, 0xFFFF, sum = 0
4285 10:04:31.551325 2, 0xFFFF, sum = 0
4286 10:04:31.553967 3, 0xFFFF, sum = 0
4287 10:04:31.554394 4, 0xFFFF, sum = 0
4288 10:04:31.557249 5, 0xFFFF, sum = 0
4289 10:04:31.557333 6, 0xFFFF, sum = 0
4290 10:04:31.560456 7, 0xFFFF, sum = 0
4291 10:04:31.560543 8, 0x0, sum = 1
4292 10:04:31.563464 9, 0x0, sum = 2
4293 10:04:31.563546 10, 0x0, sum = 3
4294 10:04:31.566756 11, 0x0, sum = 4
4295 10:04:31.566837 best_step = 9
4296 10:04:31.566901
4297 10:04:31.566959 ==
4298 10:04:31.569849 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 10:04:31.573315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 10:04:31.573396 ==
4301 10:04:31.577075 RX Vref Scan: 0
4302 10:04:31.577156
4303 10:04:31.579902 RX Vref 0 -> 0, step: 1
4304 10:04:31.579988
4305 10:04:31.580053 RX Delay -163 -> 252, step: 8
4306 10:04:31.587722 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4307 10:04:31.590841 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4308 10:04:31.594436 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4309 10:04:31.597360 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4310 10:04:31.604444 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4311 10:04:31.607399 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4312 10:04:31.610897 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4313 10:04:31.614210 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4314 10:04:31.617166 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4315 10:04:31.623825 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4316 10:04:31.627154 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4317 10:04:31.630388 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4318 10:04:31.633908 iDelay=205, Bit 12, Center 44 (-99 ~ 188) 288
4319 10:04:31.640272 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4320 10:04:31.643906 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4321 10:04:31.646989 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4322 10:04:31.647069 ==
4323 10:04:31.650433 Dram Type= 6, Freq= 0, CH_0, rank 1
4324 10:04:31.653589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 10:04:31.653671 ==
4326 10:04:31.657116 DQS Delay:
4327 10:04:31.657196 DQS0 = 0, DQS1 = 0
4328 10:04:31.660472 DQM Delay:
4329 10:04:31.660553 DQM0 = 48, DQM1 = 41
4330 10:04:31.660617 DQ Delay:
4331 10:04:31.663356 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4332 10:04:31.666681 DQ4 =52, DQ5 =40, DQ6 =56, DQ7 =56
4333 10:04:31.670126 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4334 10:04:31.673187 DQ12 =44, DQ13 =44, DQ14 =52, DQ15 =52
4335 10:04:31.673267
4336 10:04:31.673331
4337 10:04:31.683274 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a37, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
4338 10:04:31.686592 CH0 RK1: MR19=808, MR18=6A37
4339 10:04:31.693566 CH0_RK1: MR19=0x808, MR18=0x6A37, DQSOSC=389, MR23=63, INC=173, DEC=115
4340 10:04:31.693652 [RxdqsGatingPostProcess] freq 600
4341 10:04:31.700237 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4342 10:04:31.703383 Pre-setting of DQS Precalculation
4343 10:04:31.706478 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4344 10:04:31.709837 ==
4345 10:04:31.713325 Dram Type= 6, Freq= 0, CH_1, rank 0
4346 10:04:31.716484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 10:04:31.716566 ==
4348 10:04:31.723201 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4349 10:04:31.726450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4350 10:04:31.730414 [CA 0] Center 35 (5~66) winsize 62
4351 10:04:31.733939 [CA 1] Center 35 (5~66) winsize 62
4352 10:04:31.736718 [CA 2] Center 34 (4~65) winsize 62
4353 10:04:31.740141 [CA 3] Center 34 (3~65) winsize 63
4354 10:04:31.743565 [CA 4] Center 34 (3~65) winsize 63
4355 10:04:31.746583 [CA 5] Center 34 (3~65) winsize 63
4356 10:04:31.746665
4357 10:04:31.750177 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4358 10:04:31.750257
4359 10:04:31.753871 [CATrainingPosCal] consider 1 rank data
4360 10:04:31.756708 u2DelayCellTimex100 = 270/100 ps
4361 10:04:31.760054 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4362 10:04:31.766531 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4363 10:04:31.770115 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4364 10:04:31.773065 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4365 10:04:31.776522 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
4366 10:04:31.779751 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4367 10:04:31.779836
4368 10:04:31.783236 CA PerBit enable=1, Macro0, CA PI delay=34
4369 10:04:31.783320
4370 10:04:31.786274 [CBTSetCACLKResult] CA Dly = 34
4371 10:04:31.789780 CS Dly: 4 (0~35)
4372 10:04:31.789864 ==
4373 10:04:31.793177 Dram Type= 6, Freq= 0, CH_1, rank 1
4374 10:04:31.796024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 10:04:31.796108 ==
4376 10:04:31.802593 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4377 10:04:31.806288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4378 10:04:31.810126 [CA 0] Center 35 (5~66) winsize 62
4379 10:04:31.813674 [CA 1] Center 35 (5~66) winsize 62
4380 10:04:31.816814 [CA 2] Center 34 (4~65) winsize 62
4381 10:04:31.820168 [CA 3] Center 34 (4~65) winsize 62
4382 10:04:31.823730 [CA 4] Center 34 (4~65) winsize 62
4383 10:04:31.826812 [CA 5] Center 34 (4~64) winsize 61
4384 10:04:31.826896
4385 10:04:31.830020 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4386 10:04:31.830104
4387 10:04:31.833266 [CATrainingPosCal] consider 2 rank data
4388 10:04:31.836661 u2DelayCellTimex100 = 270/100 ps
4389 10:04:31.839839 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4390 10:04:31.846665 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4391 10:04:31.849643 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4392 10:04:31.852953 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4393 10:04:31.856414 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4394 10:04:31.859778 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4395 10:04:31.859862
4396 10:04:31.863404 CA PerBit enable=1, Macro0, CA PI delay=34
4397 10:04:31.863489
4398 10:04:31.866208 [CBTSetCACLKResult] CA Dly = 34
4399 10:04:31.869834 CS Dly: 4 (0~36)
4400 10:04:31.869918
4401 10:04:31.873175 ----->DramcWriteLeveling(PI) begin...
4402 10:04:31.873261 ==
4403 10:04:31.876321 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 10:04:31.879294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 10:04:31.879379 ==
4406 10:04:31.882863 Write leveling (Byte 0): 29 => 29
4407 10:04:31.886639 Write leveling (Byte 1): 30 => 30
4408 10:04:31.889213 DramcWriteLeveling(PI) end<-----
4409 10:04:31.889297
4410 10:04:31.889381 ==
4411 10:04:31.892568 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 10:04:31.895890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 10:04:31.895975 ==
4414 10:04:31.899302 [Gating] SW mode calibration
4415 10:04:31.905862 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4416 10:04:31.912537 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4417 10:04:31.915665 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 10:04:31.919321 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 10:04:31.925638 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4420 10:04:31.929545 0 9 12 | B1->B0 | 2b2b 2d2d | 0 0 | (0 0) (1 1)
4421 10:04:31.932347 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 10:04:31.939254 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 10:04:31.942388 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 10:04:31.945565 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 10:04:31.952603 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 10:04:31.955789 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 10:04:31.959227 0 10 8 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
4428 10:04:31.965728 0 10 12 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
4429 10:04:31.969108 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 10:04:31.972320 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 10:04:31.978963 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 10:04:31.982288 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 10:04:31.985942 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 10:04:31.992066 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 10:04:31.995523 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 10:04:31.998788 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4437 10:04:32.005505 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 10:04:32.008754 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 10:04:32.012292 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 10:04:32.018977 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 10:04:32.022174 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 10:04:32.025534 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 10:04:32.032023 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 10:04:32.035271 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 10:04:32.038853 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 10:04:32.045616 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 10:04:32.048670 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 10:04:32.052084 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 10:04:32.058555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 10:04:32.061655 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 10:04:32.065260 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 10:04:32.068460 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 10:04:32.071956 Total UI for P1: 0, mck2ui 16
4454 10:04:32.075434 best dqsien dly found for B0: ( 0, 13, 10)
4455 10:04:32.078764 Total UI for P1: 0, mck2ui 16
4456 10:04:32.081981 best dqsien dly found for B1: ( 0, 13, 10)
4457 10:04:32.085028 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4458 10:04:32.092293 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4459 10:04:32.092911
4460 10:04:32.095080 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4461 10:04:32.098825 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4462 10:04:32.102049 [Gating] SW calibration Done
4463 10:04:32.102630 ==
4464 10:04:32.105188 Dram Type= 6, Freq= 0, CH_1, rank 0
4465 10:04:32.108433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 10:04:32.109051 ==
4467 10:04:32.111640 RX Vref Scan: 0
4468 10:04:32.112107
4469 10:04:32.112479 RX Vref 0 -> 0, step: 1
4470 10:04:32.112865
4471 10:04:32.115106 RX Delay -230 -> 252, step: 16
4472 10:04:32.118272 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4473 10:04:32.125061 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4474 10:04:32.127891 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4475 10:04:32.131525 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4476 10:04:32.134606 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4477 10:04:32.141221 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4478 10:04:32.145304 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4479 10:04:32.148186 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4480 10:04:32.151400 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4481 10:04:32.154885 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4482 10:04:32.161253 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4483 10:04:32.164605 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4484 10:04:32.167960 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4485 10:04:32.171149 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4486 10:04:32.178259 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4487 10:04:32.180879 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4488 10:04:32.181354 ==
4489 10:04:32.184471 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 10:04:32.187658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 10:04:32.188196 ==
4492 10:04:32.191020 DQS Delay:
4493 10:04:32.191492 DQS0 = 0, DQS1 = 0
4494 10:04:32.191867 DQM Delay:
4495 10:04:32.194232 DQM0 = 50, DQM1 = 39
4496 10:04:32.194703 DQ Delay:
4497 10:04:32.197749 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4498 10:04:32.201206 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4499 10:04:32.204308 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4500 10:04:32.207751 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4501 10:04:32.208315
4502 10:04:32.208689
4503 10:04:32.209067 ==
4504 10:04:32.211000 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 10:04:32.217529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 10:04:32.218067 ==
4507 10:04:32.218443
4508 10:04:32.218792
4509 10:04:32.219128 TX Vref Scan disable
4510 10:04:32.221982 == TX Byte 0 ==
4511 10:04:32.224462 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4512 10:04:32.231422 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4513 10:04:32.231892 == TX Byte 1 ==
4514 10:04:32.234747 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4515 10:04:32.241345 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4516 10:04:32.241874 ==
4517 10:04:32.244628 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 10:04:32.247775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 10:04:32.248253 ==
4520 10:04:32.248760
4521 10:04:32.249258
4522 10:04:32.251193 TX Vref Scan disable
4523 10:04:32.254308 == TX Byte 0 ==
4524 10:04:32.257539 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4525 10:04:32.261012 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4526 10:04:32.264226 == TX Byte 1 ==
4527 10:04:32.267538 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4528 10:04:32.270945 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4529 10:04:32.271634
4530 10:04:32.272211 [DATLAT]
4531 10:04:32.273986 Freq=600, CH1 RK0
4532 10:04:32.274629
4533 10:04:32.275176 DATLAT Default: 0x9
4534 10:04:32.277528 0, 0xFFFF, sum = 0
4535 10:04:32.281026 1, 0xFFFF, sum = 0
4536 10:04:32.281617 2, 0xFFFF, sum = 0
4537 10:04:32.284290 3, 0xFFFF, sum = 0
4538 10:04:32.284867 4, 0xFFFF, sum = 0
4539 10:04:32.287428 5, 0xFFFF, sum = 0
4540 10:04:32.287888 6, 0xFFFF, sum = 0
4541 10:04:32.290557 7, 0xFFFF, sum = 0
4542 10:04:32.290983 8, 0x0, sum = 1
4543 10:04:32.293708 9, 0x0, sum = 2
4544 10:04:32.294131 10, 0x0, sum = 3
4545 10:04:32.297273 11, 0x0, sum = 4
4546 10:04:32.297699 best_step = 9
4547 10:04:32.298034
4548 10:04:32.298345 ==
4549 10:04:32.300432 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 10:04:32.303508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 10:04:32.303938 ==
4552 10:04:32.306905 RX Vref Scan: 1
4553 10:04:32.307326
4554 10:04:32.310241 RX Vref 0 -> 0, step: 1
4555 10:04:32.310662
4556 10:04:32.310997 RX Delay -179 -> 252, step: 8
4557 10:04:32.311312
4558 10:04:32.313434 Set Vref, RX VrefLevel [Byte0]: 52
4559 10:04:32.317061 [Byte1]: 52
4560 10:04:32.321403
4561 10:04:32.321868 Final RX Vref Byte 0 = 52 to rank0
4562 10:04:32.324847 Final RX Vref Byte 1 = 52 to rank0
4563 10:04:32.327949 Final RX Vref Byte 0 = 52 to rank1
4564 10:04:32.331324 Final RX Vref Byte 1 = 52 to rank1==
4565 10:04:32.334830 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 10:04:32.341405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 10:04:32.341833 ==
4568 10:04:32.342173 DQS Delay:
4569 10:04:32.344726 DQS0 = 0, DQS1 = 0
4570 10:04:32.345188 DQM Delay:
4571 10:04:32.345528 DQM0 = 48, DQM1 = 40
4572 10:04:32.348272 DQ Delay:
4573 10:04:32.351109 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4574 10:04:32.354842 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4575 10:04:32.358111 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4576 10:04:32.361858 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4577 10:04:32.362364
4578 10:04:32.362825
4579 10:04:32.367754 [DQSOSCAuto] RK0, (LSB)MR18= 0x486f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4580 10:04:32.371073 CH1 RK0: MR19=808, MR18=486F
4581 10:04:32.378030 CH1_RK0: MR19=0x808, MR18=0x486F, DQSOSC=389, MR23=63, INC=173, DEC=115
4582 10:04:32.378556
4583 10:04:32.381077 ----->DramcWriteLeveling(PI) begin...
4584 10:04:32.381520 ==
4585 10:04:32.384528 Dram Type= 6, Freq= 0, CH_1, rank 1
4586 10:04:32.387625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 10:04:32.387709 ==
4588 10:04:32.390698 Write leveling (Byte 0): 28 => 28
4589 10:04:32.394048 Write leveling (Byte 1): 29 => 29
4590 10:04:32.397535 DramcWriteLeveling(PI) end<-----
4591 10:04:32.397618
4592 10:04:32.397683 ==
4593 10:04:32.400713 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 10:04:32.404040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 10:04:32.404123 ==
4596 10:04:32.407186 [Gating] SW mode calibration
4597 10:04:32.413836 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4598 10:04:32.420726 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4599 10:04:32.423689 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4600 10:04:32.431074 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 10:04:32.433766 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 10:04:32.437092 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 0) (0 0)
4603 10:04:32.443471 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4604 10:04:32.446894 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 10:04:32.450186 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 10:04:32.456956 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 10:04:32.459978 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 10:04:32.463571 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 10:04:32.470235 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 10:04:32.473369 0 10 12 | B1->B0 | 3e3e 3333 | 0 0 | (0 0) (0 0)
4611 10:04:32.476906 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 10:04:32.483629 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 10:04:32.487095 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 10:04:32.490133 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 10:04:32.496659 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 10:04:32.500350 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 10:04:32.503576 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 10:04:32.510183 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4619 10:04:32.513293 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 10:04:32.516564 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 10:04:32.523787 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 10:04:32.526600 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 10:04:32.529711 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 10:04:32.536638 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 10:04:32.539592 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 10:04:32.543024 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 10:04:32.549892 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 10:04:32.552920 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 10:04:32.556366 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 10:04:32.562753 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 10:04:32.566023 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 10:04:32.569329 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 10:04:32.575760 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 10:04:32.579296 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 10:04:32.582502 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 10:04:32.586050 Total UI for P1: 0, mck2ui 16
4637 10:04:32.589610 best dqsien dly found for B0: ( 0, 13, 14)
4638 10:04:32.592841 Total UI for P1: 0, mck2ui 16
4639 10:04:32.595845 best dqsien dly found for B1: ( 0, 13, 14)
4640 10:04:32.599294 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4641 10:04:32.602932 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4642 10:04:32.603573
4643 10:04:32.606177 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4644 10:04:32.612457 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4645 10:04:32.613055 [Gating] SW calibration Done
4646 10:04:32.615861 ==
4647 10:04:32.616342 Dram Type= 6, Freq= 0, CH_1, rank 1
4648 10:04:32.622893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 10:04:32.623472 ==
4650 10:04:32.623847 RX Vref Scan: 0
4651 10:04:32.624191
4652 10:04:32.626322 RX Vref 0 -> 0, step: 1
4653 10:04:32.626883
4654 10:04:32.629189 RX Delay -230 -> 252, step: 16
4655 10:04:32.632932 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4656 10:04:32.635845 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4657 10:04:32.642243 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4658 10:04:32.645340 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4659 10:04:32.648585 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4660 10:04:32.651948 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4661 10:04:32.655291 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4662 10:04:32.661860 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4663 10:04:32.665105 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4664 10:04:32.668386 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4665 10:04:32.671467 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4666 10:04:32.678345 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4667 10:04:32.681710 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4668 10:04:32.685247 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4669 10:04:32.688438 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4670 10:04:32.695033 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4671 10:04:32.695476 ==
4672 10:04:32.698345 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 10:04:32.701725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 10:04:32.702149 ==
4675 10:04:32.702490 DQS Delay:
4676 10:04:32.704852 DQS0 = 0, DQS1 = 0
4677 10:04:32.705274 DQM Delay:
4678 10:04:32.707963 DQM0 = 51, DQM1 = 43
4679 10:04:32.708385 DQ Delay:
4680 10:04:32.711379 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4681 10:04:32.714838 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4682 10:04:32.718059 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4683 10:04:32.721185 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =57
4684 10:04:32.721605
4685 10:04:32.721941
4686 10:04:32.722251 ==
4687 10:04:32.724217 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 10:04:32.727515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 10:04:32.731320 ==
4690 10:04:32.731743
4691 10:04:32.732079
4692 10:04:32.732392 TX Vref Scan disable
4693 10:04:32.734174 == TX Byte 0 ==
4694 10:04:32.737643 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4695 10:04:32.744717 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4696 10:04:32.745177 == TX Byte 1 ==
4697 10:04:32.747748 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4698 10:04:32.754067 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4699 10:04:32.754644 ==
4700 10:04:32.757574 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 10:04:32.760882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 10:04:32.761314 ==
4703 10:04:32.761657
4704 10:04:32.761971
4705 10:04:32.763855 TX Vref Scan disable
4706 10:04:32.767295 == TX Byte 0 ==
4707 10:04:32.770537 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4708 10:04:32.773601 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4709 10:04:32.777121 == TX Byte 1 ==
4710 10:04:32.780441 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4711 10:04:32.783655 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4712 10:04:32.783963
4713 10:04:32.784201 [DATLAT]
4714 10:04:32.786969 Freq=600, CH1 RK1
4715 10:04:32.787319
4716 10:04:32.790691 DATLAT Default: 0x9
4717 10:04:32.790992 0, 0xFFFF, sum = 0
4718 10:04:32.793426 1, 0xFFFF, sum = 0
4719 10:04:32.793733 2, 0xFFFF, sum = 0
4720 10:04:32.796876 3, 0xFFFF, sum = 0
4721 10:04:32.797182 4, 0xFFFF, sum = 0
4722 10:04:32.800140 5, 0xFFFF, sum = 0
4723 10:04:32.800444 6, 0xFFFF, sum = 0
4724 10:04:32.803426 7, 0xFFFF, sum = 0
4725 10:04:32.803732 8, 0x0, sum = 1
4726 10:04:32.806898 9, 0x0, sum = 2
4727 10:04:32.807201 10, 0x0, sum = 3
4728 10:04:32.809799 11, 0x0, sum = 4
4729 10:04:32.810104 best_step = 9
4730 10:04:32.810341
4731 10:04:32.810563 ==
4732 10:04:32.813265 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 10:04:32.816627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 10:04:32.816960 ==
4735 10:04:32.819772 RX Vref Scan: 0
4736 10:04:32.820071
4737 10:04:32.823538 RX Vref 0 -> 0, step: 1
4738 10:04:32.823839
4739 10:04:32.824077 RX Delay -179 -> 252, step: 8
4740 10:04:32.830997 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4741 10:04:32.834279 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4742 10:04:32.837634 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4743 10:04:32.841086 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4744 10:04:32.847375 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4745 10:04:32.851021 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4746 10:04:32.854187 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4747 10:04:32.857653 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4748 10:04:32.860795 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4749 10:04:32.867300 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4750 10:04:32.871207 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4751 10:04:32.873879 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4752 10:04:32.877554 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4753 10:04:32.880722 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4754 10:04:32.887135 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4755 10:04:32.890640 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4756 10:04:32.890943 ==
4757 10:04:32.893641 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 10:04:32.897119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 10:04:32.897422 ==
4760 10:04:32.900114 DQS Delay:
4761 10:04:32.900413 DQS0 = 0, DQS1 = 0
4762 10:04:32.903662 DQM Delay:
4763 10:04:32.903960 DQM0 = 48, DQM1 = 43
4764 10:04:32.904198 DQ Delay:
4765 10:04:32.906763 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4766 10:04:32.910301 DQ4 =48, DQ5 =60, DQ6 =52, DQ7 =48
4767 10:04:32.913402 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4768 10:04:32.916632 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4769 10:04:32.916964
4770 10:04:32.917204
4771 10:04:32.926830 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4772 10:04:32.930360 CH1 RK1: MR19=808, MR18=5B21
4773 10:04:32.936722 CH1_RK1: MR19=0x808, MR18=0x5B21, DQSOSC=392, MR23=63, INC=170, DEC=113
4774 10:04:32.937053 [RxdqsGatingPostProcess] freq 600
4775 10:04:32.943447 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4776 10:04:32.946685 Pre-setting of DQS Precalculation
4777 10:04:32.950182 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4778 10:04:32.959398 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4779 10:04:32.966184 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4780 10:04:32.966294
4781 10:04:32.966401
4782 10:04:32.969372 [Calibration Summary] 1200 Mbps
4783 10:04:32.969455 CH 0, Rank 0
4784 10:04:32.972928 SW Impedance : PASS
4785 10:04:32.973012 DUTY Scan : NO K
4786 10:04:32.976408 ZQ Calibration : PASS
4787 10:04:32.979257 Jitter Meter : NO K
4788 10:04:32.979339 CBT Training : PASS
4789 10:04:32.982888 Write leveling : PASS
4790 10:04:32.986186 RX DQS gating : PASS
4791 10:04:32.986269 RX DQ/DQS(RDDQC) : PASS
4792 10:04:32.989342 TX DQ/DQS : PASS
4793 10:04:32.992696 RX DATLAT : PASS
4794 10:04:32.992807 RX DQ/DQS(Engine): PASS
4795 10:04:32.996327 TX OE : NO K
4796 10:04:32.996410 All Pass.
4797 10:04:32.996476
4798 10:04:32.999390 CH 0, Rank 1
4799 10:04:32.999473 SW Impedance : PASS
4800 10:04:33.002832 DUTY Scan : NO K
4801 10:04:33.005898 ZQ Calibration : PASS
4802 10:04:33.005981 Jitter Meter : NO K
4803 10:04:33.009282 CBT Training : PASS
4804 10:04:33.012530 Write leveling : PASS
4805 10:04:33.012613 RX DQS gating : PASS
4806 10:04:33.015691 RX DQ/DQS(RDDQC) : PASS
4807 10:04:33.018962 TX DQ/DQS : PASS
4808 10:04:33.019049 RX DATLAT : PASS
4809 10:04:33.022269 RX DQ/DQS(Engine): PASS
4810 10:04:33.022354 TX OE : NO K
4811 10:04:33.025778 All Pass.
4812 10:04:33.025848
4813 10:04:33.025909 CH 1, Rank 0
4814 10:04:33.029080 SW Impedance : PASS
4815 10:04:33.032046 DUTY Scan : NO K
4816 10:04:33.032147 ZQ Calibration : PASS
4817 10:04:33.035890 Jitter Meter : NO K
4818 10:04:33.035991 CBT Training : PASS
4819 10:04:33.039130 Write leveling : PASS
4820 10:04:33.042511 RX DQS gating : PASS
4821 10:04:33.042606 RX DQ/DQS(RDDQC) : PASS
4822 10:04:33.045801 TX DQ/DQS : PASS
4823 10:04:33.048924 RX DATLAT : PASS
4824 10:04:33.048997 RX DQ/DQS(Engine): PASS
4825 10:04:33.052326 TX OE : NO K
4826 10:04:33.052395 All Pass.
4827 10:04:33.052460
4828 10:04:33.055437 CH 1, Rank 1
4829 10:04:33.055535 SW Impedance : PASS
4830 10:04:33.058737 DUTY Scan : NO K
4831 10:04:33.061959 ZQ Calibration : PASS
4832 10:04:33.062061 Jitter Meter : NO K
4833 10:04:33.065745 CBT Training : PASS
4834 10:04:33.068620 Write leveling : PASS
4835 10:04:33.068703 RX DQS gating : PASS
4836 10:04:33.072347 RX DQ/DQS(RDDQC) : PASS
4837 10:04:33.075268 TX DQ/DQS : PASS
4838 10:04:33.075351 RX DATLAT : PASS
4839 10:04:33.079455 RX DQ/DQS(Engine): PASS
4840 10:04:33.081869 TX OE : NO K
4841 10:04:33.081952 All Pass.
4842 10:04:33.082018
4843 10:04:33.082080 DramC Write-DBI off
4844 10:04:33.084979 PER_BANK_REFRESH: Hybrid Mode
4845 10:04:33.088527 TX_TRACKING: ON
4846 10:04:33.094982 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4847 10:04:33.098383 [FAST_K] Save calibration result to emmc
4848 10:04:33.104908 dramc_set_vcore_voltage set vcore to 662500
4849 10:04:33.104991 Read voltage for 933, 3
4850 10:04:33.108334 Vio18 = 0
4851 10:04:33.108417 Vcore = 662500
4852 10:04:33.108483 Vdram = 0
4853 10:04:33.111306 Vddq = 0
4854 10:04:33.111389 Vmddr = 0
4855 10:04:33.114837 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4856 10:04:33.121530 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4857 10:04:33.124873 MEM_TYPE=3, freq_sel=17
4858 10:04:33.128292 sv_algorithm_assistance_LP4_1600
4859 10:04:33.131275 ============ PULL DRAM RESETB DOWN ============
4860 10:04:33.134671 ========== PULL DRAM RESETB DOWN end =========
4861 10:04:33.138416 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4862 10:04:33.141345 ===================================
4863 10:04:33.144814 LPDDR4 DRAM CONFIGURATION
4864 10:04:33.147895 ===================================
4865 10:04:33.151355 EX_ROW_EN[0] = 0x0
4866 10:04:33.151442 EX_ROW_EN[1] = 0x0
4867 10:04:33.154529 LP4Y_EN = 0x0
4868 10:04:33.154613 WORK_FSP = 0x0
4869 10:04:33.157979 WL = 0x3
4870 10:04:33.158062 RL = 0x3
4871 10:04:33.160978 BL = 0x2
4872 10:04:33.164220 RPST = 0x0
4873 10:04:33.164304 RD_PRE = 0x0
4874 10:04:33.167519 WR_PRE = 0x1
4875 10:04:33.167602 WR_PST = 0x0
4876 10:04:33.170964 DBI_WR = 0x0
4877 10:04:33.171047 DBI_RD = 0x0
4878 10:04:33.174189 OTF = 0x1
4879 10:04:33.177396 ===================================
4880 10:04:33.181120 ===================================
4881 10:04:33.181204 ANA top config
4882 10:04:33.184052 ===================================
4883 10:04:33.187406 DLL_ASYNC_EN = 0
4884 10:04:33.190778 ALL_SLAVE_EN = 1
4885 10:04:33.190862 NEW_RANK_MODE = 1
4886 10:04:33.194054 DLL_IDLE_MODE = 1
4887 10:04:33.197939 LP45_APHY_COMB_EN = 1
4888 10:04:33.200457 TX_ODT_DIS = 1
4889 10:04:33.203888 NEW_8X_MODE = 1
4890 10:04:33.207046 ===================================
4891 10:04:33.210388 ===================================
4892 10:04:33.210464 data_rate = 1866
4893 10:04:33.213689 CKR = 1
4894 10:04:33.216924 DQ_P2S_RATIO = 8
4895 10:04:33.220358 ===================================
4896 10:04:33.223693 CA_P2S_RATIO = 8
4897 10:04:33.227121 DQ_CA_OPEN = 0
4898 10:04:33.230286 DQ_SEMI_OPEN = 0
4899 10:04:33.230359 CA_SEMI_OPEN = 0
4900 10:04:33.233460 CA_FULL_RATE = 0
4901 10:04:33.236778 DQ_CKDIV4_EN = 1
4902 10:04:33.240084 CA_CKDIV4_EN = 1
4903 10:04:33.243345 CA_PREDIV_EN = 0
4904 10:04:33.246558 PH8_DLY = 0
4905 10:04:33.246630 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4906 10:04:33.250010 DQ_AAMCK_DIV = 4
4907 10:04:33.253491 CA_AAMCK_DIV = 4
4908 10:04:33.256499 CA_ADMCK_DIV = 4
4909 10:04:33.259978 DQ_TRACK_CA_EN = 0
4910 10:04:33.263297 CA_PICK = 933
4911 10:04:33.266527 CA_MCKIO = 933
4912 10:04:33.266647 MCKIO_SEMI = 0
4913 10:04:33.269725 PLL_FREQ = 3732
4914 10:04:33.273293 DQ_UI_PI_RATIO = 32
4915 10:04:33.276568 CA_UI_PI_RATIO = 0
4916 10:04:33.279769 ===================================
4917 10:04:33.283556 ===================================
4918 10:04:33.286632 memory_type:LPDDR4
4919 10:04:33.286733 GP_NUM : 10
4920 10:04:33.289587 SRAM_EN : 1
4921 10:04:33.293039 MD32_EN : 0
4922 10:04:33.296205 ===================================
4923 10:04:33.296280 [ANA_INIT] >>>>>>>>>>>>>>
4924 10:04:33.299516 <<<<<< [CONFIGURE PHASE]: ANA_TX
4925 10:04:33.302901 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4926 10:04:33.306345 ===================================
4927 10:04:33.309312 data_rate = 1866,PCW = 0X8f00
4928 10:04:33.312772 ===================================
4929 10:04:33.316081 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4930 10:04:33.322573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4931 10:04:33.326237 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 10:04:33.332741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4933 10:04:33.335951 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4934 10:04:33.339323 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4935 10:04:33.342473 [ANA_INIT] flow start
4936 10:04:33.342546 [ANA_INIT] PLL >>>>>>>>
4937 10:04:33.345843 [ANA_INIT] PLL <<<<<<<<
4938 10:04:33.349123 [ANA_INIT] MIDPI >>>>>>>>
4939 10:04:33.349195 [ANA_INIT] MIDPI <<<<<<<<
4940 10:04:33.352640 [ANA_INIT] DLL >>>>>>>>
4941 10:04:33.355787 [ANA_INIT] flow end
4942 10:04:33.359343 ============ LP4 DIFF to SE enter ============
4943 10:04:33.362540 ============ LP4 DIFF to SE exit ============
4944 10:04:33.366118 [ANA_INIT] <<<<<<<<<<<<<
4945 10:04:33.368950 [Flow] Enable top DCM control >>>>>
4946 10:04:33.372368 [Flow] Enable top DCM control <<<<<
4947 10:04:33.375605 Enable DLL master slave shuffle
4948 10:04:33.378970 ==============================================================
4949 10:04:33.382385 Gating Mode config
4950 10:04:33.388763 ==============================================================
4951 10:04:33.388848 Config description:
4952 10:04:33.398561 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4953 10:04:33.405626 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4954 10:04:33.408584 SELPH_MODE 0: By rank 1: By Phase
4955 10:04:33.415111 ==============================================================
4956 10:04:33.418553 GAT_TRACK_EN = 1
4957 10:04:33.421697 RX_GATING_MODE = 2
4958 10:04:33.424941 RX_GATING_TRACK_MODE = 2
4959 10:04:33.428513 SELPH_MODE = 1
4960 10:04:33.431897 PICG_EARLY_EN = 1
4961 10:04:33.434848 VALID_LAT_VALUE = 1
4962 10:04:33.438374 ==============================================================
4963 10:04:33.441393 Enter into Gating configuration >>>>
4964 10:04:33.444971 Exit from Gating configuration <<<<
4965 10:04:33.448320 Enter into DVFS_PRE_config >>>>>
4966 10:04:33.461540 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4967 10:04:33.464706 Exit from DVFS_PRE_config <<<<<
4968 10:04:33.467705 Enter into PICG configuration >>>>
4969 10:04:33.467785 Exit from PICG configuration <<<<
4970 10:04:33.471397 [RX_INPUT] configuration >>>>>
4971 10:04:33.474464 [RX_INPUT] configuration <<<<<
4972 10:04:33.481218 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4973 10:04:33.484467 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4974 10:04:33.491029 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4975 10:04:33.497981 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4976 10:04:33.504410 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4977 10:04:33.511342 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4978 10:04:33.514555 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4979 10:04:33.517596 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4980 10:04:33.524255 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4981 10:04:33.527401 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4982 10:04:33.530588 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4983 10:04:33.534071 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4984 10:04:33.537379 ===================================
4985 10:04:33.540692 LPDDR4 DRAM CONFIGURATION
4986 10:04:33.544146 ===================================
4987 10:04:33.547396 EX_ROW_EN[0] = 0x0
4988 10:04:33.547475 EX_ROW_EN[1] = 0x0
4989 10:04:33.550582 LP4Y_EN = 0x0
4990 10:04:33.550652 WORK_FSP = 0x0
4991 10:04:33.554367 WL = 0x3
4992 10:04:33.554438 RL = 0x3
4993 10:04:33.557297 BL = 0x2
4994 10:04:33.557366 RPST = 0x0
4995 10:04:33.560599 RD_PRE = 0x0
4996 10:04:33.560668 WR_PRE = 0x1
4997 10:04:33.563853 WR_PST = 0x0
4998 10:04:33.563922 DBI_WR = 0x0
4999 10:04:33.567071 DBI_RD = 0x0
5000 10:04:33.570609 OTF = 0x1
5001 10:04:33.573821 ===================================
5002 10:04:33.577077 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5003 10:04:33.580594 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5004 10:04:33.584096 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5005 10:04:33.586978 ===================================
5006 10:04:33.590199 LPDDR4 DRAM CONFIGURATION
5007 10:04:33.593406 ===================================
5008 10:04:33.597165 EX_ROW_EN[0] = 0x10
5009 10:04:33.597238 EX_ROW_EN[1] = 0x0
5010 10:04:33.600289 LP4Y_EN = 0x0
5011 10:04:33.600367 WORK_FSP = 0x0
5012 10:04:33.603389 WL = 0x3
5013 10:04:33.603469 RL = 0x3
5014 10:04:33.607032 BL = 0x2
5015 10:04:33.607111 RPST = 0x0
5016 10:04:33.610354 RD_PRE = 0x0
5017 10:04:33.610433 WR_PRE = 0x1
5018 10:04:33.613881 WR_PST = 0x0
5019 10:04:33.613952 DBI_WR = 0x0
5020 10:04:33.617008 DBI_RD = 0x0
5021 10:04:33.619861 OTF = 0x1
5022 10:04:33.623219 ===================================
5023 10:04:33.626501 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5024 10:04:33.631910 nWR fixed to 30
5025 10:04:33.634912 [ModeRegInit_LP4] CH0 RK0
5026 10:04:33.634986 [ModeRegInit_LP4] CH0 RK1
5027 10:04:33.638182 [ModeRegInit_LP4] CH1 RK0
5028 10:04:33.641739 [ModeRegInit_LP4] CH1 RK1
5029 10:04:33.641823 match AC timing 9
5030 10:04:33.648281 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5031 10:04:33.651453 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5032 10:04:33.654855 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5033 10:04:33.661412 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5034 10:04:33.664754 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5035 10:04:33.664893 ==
5036 10:04:33.668193 Dram Type= 6, Freq= 0, CH_0, rank 0
5037 10:04:33.671154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5038 10:04:33.671237 ==
5039 10:04:33.678117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5040 10:04:33.684559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5041 10:04:33.687861 [CA 0] Center 38 (7~69) winsize 63
5042 10:04:33.691572 [CA 1] Center 38 (8~69) winsize 62
5043 10:04:33.694414 [CA 2] Center 35 (5~66) winsize 62
5044 10:04:33.697995 [CA 3] Center 35 (5~65) winsize 61
5045 10:04:33.701345 [CA 4] Center 34 (4~64) winsize 61
5046 10:04:33.704536 [CA 5] Center 33 (3~64) winsize 62
5047 10:04:33.704608
5048 10:04:33.708083 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5049 10:04:33.708155
5050 10:04:33.711178 [CATrainingPosCal] consider 1 rank data
5051 10:04:33.714814 u2DelayCellTimex100 = 270/100 ps
5052 10:04:33.717632 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5053 10:04:33.721214 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5054 10:04:33.724097 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5055 10:04:33.727578 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5056 10:04:33.734275 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5057 10:04:33.737478 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5058 10:04:33.737567
5059 10:04:33.741000 CA PerBit enable=1, Macro0, CA PI delay=33
5060 10:04:33.741071
5061 10:04:33.744095 [CBTSetCACLKResult] CA Dly = 33
5062 10:04:33.744162 CS Dly: 6 (0~37)
5063 10:04:33.744221 ==
5064 10:04:33.747402 Dram Type= 6, Freq= 0, CH_0, rank 1
5065 10:04:33.753885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5066 10:04:33.753986 ==
5067 10:04:33.757148 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5068 10:04:33.764137 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5069 10:04:33.767376 [CA 0] Center 38 (8~69) winsize 62
5070 10:04:33.770708 [CA 1] Center 38 (8~69) winsize 62
5071 10:04:33.773612 [CA 2] Center 36 (6~66) winsize 61
5072 10:04:33.777053 [CA 3] Center 35 (5~66) winsize 62
5073 10:04:33.780676 [CA 4] Center 34 (4~65) winsize 62
5074 10:04:33.783794 [CA 5] Center 34 (4~64) winsize 61
5075 10:04:33.783863
5076 10:04:33.787076 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5077 10:04:33.787144
5078 10:04:33.790613 [CATrainingPosCal] consider 2 rank data
5079 10:04:33.793509 u2DelayCellTimex100 = 270/100 ps
5080 10:04:33.797138 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5081 10:04:33.803507 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5082 10:04:33.807008 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5083 10:04:33.810213 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5084 10:04:33.813546 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5085 10:04:33.816930 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5086 10:04:33.817033
5087 10:04:33.820040 CA PerBit enable=1, Macro0, CA PI delay=34
5088 10:04:33.820123
5089 10:04:33.823531 [CBTSetCACLKResult] CA Dly = 34
5090 10:04:33.823614 CS Dly: 7 (0~39)
5091 10:04:33.826917
5092 10:04:33.829972 ----->DramcWriteLeveling(PI) begin...
5093 10:04:33.830057 ==
5094 10:04:33.833481 Dram Type= 6, Freq= 0, CH_0, rank 0
5095 10:04:33.836723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 10:04:33.836846 ==
5097 10:04:33.840215 Write leveling (Byte 0): 29 => 29
5098 10:04:33.843168 Write leveling (Byte 1): 27 => 27
5099 10:04:33.846676 DramcWriteLeveling(PI) end<-----
5100 10:04:33.846758
5101 10:04:33.846823 ==
5102 10:04:33.849973 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 10:04:33.853038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 10:04:33.853121 ==
5105 10:04:33.856247 [Gating] SW mode calibration
5106 10:04:33.863266 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5107 10:04:33.869747 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5108 10:04:33.873301 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5109 10:04:33.876306 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 10:04:33.882995 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 10:04:33.886608 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 10:04:33.889608 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 10:04:33.896152 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 10:04:33.899404 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5115 10:04:33.902638 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5116 10:04:33.909503 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5117 10:04:33.912696 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 10:04:33.915868 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 10:04:33.922637 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 10:04:33.925642 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 10:04:33.928948 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 10:04:33.935660 0 15 24 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
5123 10:04:33.939176 0 15 28 | B1->B0 | 2b2b 4646 | 1 0 | (1 1) (0 0)
5124 10:04:33.942967 1 0 0 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
5125 10:04:33.949172 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 10:04:33.952620 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 10:04:33.955552 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 10:04:33.962135 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 10:04:33.965373 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 10:04:33.968710 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 10:04:33.975470 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5132 10:04:33.978807 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5133 10:04:33.981789 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 10:04:33.988370 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 10:04:33.991677 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 10:04:33.994980 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 10:04:34.001895 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 10:04:34.004917 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 10:04:34.008442 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 10:04:34.014928 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 10:04:34.018344 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 10:04:34.021531 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 10:04:34.028043 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 10:04:34.031533 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 10:04:34.034646 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 10:04:34.041678 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 10:04:34.044756 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5148 10:04:34.048489 Total UI for P1: 0, mck2ui 16
5149 10:04:34.052023 best dqsien dly found for B0: ( 1, 2, 26)
5150 10:04:34.054742 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5151 10:04:34.057885 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 10:04:34.061349 Total UI for P1: 0, mck2ui 16
5153 10:04:34.064937 best dqsien dly found for B1: ( 1, 2, 30)
5154 10:04:34.068234 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5155 10:04:34.074457 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5156 10:04:34.074540
5157 10:04:34.078183 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5158 10:04:34.081328 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5159 10:04:34.084692 [Gating] SW calibration Done
5160 10:04:34.084796 ==
5161 10:04:34.087627 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 10:04:34.091255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 10:04:34.091339 ==
5164 10:04:34.094729 RX Vref Scan: 0
5165 10:04:34.094903
5166 10:04:34.094988 RX Vref 0 -> 0, step: 1
5167 10:04:34.095062
5168 10:04:34.097963 RX Delay -80 -> 252, step: 8
5169 10:04:34.100927 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5170 10:04:34.108072 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5171 10:04:34.111224 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5172 10:04:34.114377 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5173 10:04:34.117561 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5174 10:04:34.120937 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5175 10:04:34.124204 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5176 10:04:34.130776 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5177 10:04:34.134111 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5178 10:04:34.137420 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5179 10:04:34.140681 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5180 10:04:34.144277 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5181 10:04:34.150557 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5182 10:04:34.154263 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5183 10:04:34.157505 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5184 10:04:34.160526 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5185 10:04:34.160651 ==
5186 10:04:34.163751 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 10:04:34.167194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 10:04:34.167337 ==
5189 10:04:34.170712 DQS Delay:
5190 10:04:34.170871 DQS0 = 0, DQS1 = 0
5191 10:04:34.174136 DQM Delay:
5192 10:04:34.174309 DQM0 = 106, DQM1 = 90
5193 10:04:34.174467 DQ Delay:
5194 10:04:34.177333 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =103
5195 10:04:34.183957 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5196 10:04:34.184287 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5197 10:04:34.191054 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5198 10:04:34.191450
5199 10:04:34.191702
5200 10:04:34.191924 ==
5201 10:04:34.194253 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 10:04:34.197321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 10:04:34.197710 ==
5204 10:04:34.198017
5205 10:04:34.198367
5206 10:04:34.201191 TX Vref Scan disable
5207 10:04:34.201766 == TX Byte 0 ==
5208 10:04:34.207960 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5209 10:04:34.210731 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5210 10:04:34.211202 == TX Byte 1 ==
5211 10:04:34.217012 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5212 10:04:34.220198 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5213 10:04:34.220282 ==
5214 10:04:34.223670 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 10:04:34.226955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 10:04:34.227039 ==
5217 10:04:34.227104
5218 10:04:34.227163
5219 10:04:34.230053 TX Vref Scan disable
5220 10:04:34.233262 == TX Byte 0 ==
5221 10:04:34.236605 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5222 10:04:34.240233 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5223 10:04:34.243160 == TX Byte 1 ==
5224 10:04:34.246691 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5225 10:04:34.250138 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5226 10:04:34.253158
5227 10:04:34.253240 [DATLAT]
5228 10:04:34.253305 Freq=933, CH0 RK0
5229 10:04:34.253366
5230 10:04:34.256495 DATLAT Default: 0xd
5231 10:04:34.256577 0, 0xFFFF, sum = 0
5232 10:04:34.259611 1, 0xFFFF, sum = 0
5233 10:04:34.259694 2, 0xFFFF, sum = 0
5234 10:04:34.263116 3, 0xFFFF, sum = 0
5235 10:04:34.266374 4, 0xFFFF, sum = 0
5236 10:04:34.266459 5, 0xFFFF, sum = 0
5237 10:04:34.269607 6, 0xFFFF, sum = 0
5238 10:04:34.269693 7, 0xFFFF, sum = 0
5239 10:04:34.272863 8, 0xFFFF, sum = 0
5240 10:04:34.272947 9, 0xFFFF, sum = 0
5241 10:04:34.275974 10, 0x0, sum = 1
5242 10:04:34.276058 11, 0x0, sum = 2
5243 10:04:34.279453 12, 0x0, sum = 3
5244 10:04:34.279536 13, 0x0, sum = 4
5245 10:04:34.279603 best_step = 11
5246 10:04:34.279664
5247 10:04:34.282932 ==
5248 10:04:34.286260 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 10:04:34.289507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 10:04:34.289590 ==
5251 10:04:34.289656 RX Vref Scan: 1
5252 10:04:34.289717
5253 10:04:34.292742 RX Vref 0 -> 0, step: 1
5254 10:04:34.292833
5255 10:04:34.296189 RX Delay -53 -> 252, step: 4
5256 10:04:34.296271
5257 10:04:34.299376 Set Vref, RX VrefLevel [Byte0]: 57
5258 10:04:34.302354 [Byte1]: 48
5259 10:04:34.302437
5260 10:04:34.306049 Final RX Vref Byte 0 = 57 to rank0
5261 10:04:34.309294 Final RX Vref Byte 1 = 48 to rank0
5262 10:04:34.312621 Final RX Vref Byte 0 = 57 to rank1
5263 10:04:34.315985 Final RX Vref Byte 1 = 48 to rank1==
5264 10:04:34.318901 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 10:04:34.325414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 10:04:34.325500 ==
5267 10:04:34.325568 DQS Delay:
5268 10:04:34.325628 DQS0 = 0, DQS1 = 0
5269 10:04:34.329172 DQM Delay:
5270 10:04:34.329260 DQM0 = 107, DQM1 = 91
5271 10:04:34.332286 DQ Delay:
5272 10:04:34.335567 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5273 10:04:34.338845 DQ4 =106, DQ5 =98, DQ6 =116, DQ7 =116
5274 10:04:34.342268 DQ8 =86, DQ9 =76, DQ10 =90, DQ11 =90
5275 10:04:34.345574 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =100
5276 10:04:34.345686
5277 10:04:34.345774
5278 10:04:34.352110 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
5279 10:04:34.355336 CH0 RK0: MR19=505, MR18=2622
5280 10:04:34.362337 CH0_RK0: MR19=0x505, MR18=0x2622, DQSOSC=409, MR23=63, INC=64, DEC=43
5281 10:04:34.362491
5282 10:04:34.365761 ----->DramcWriteLeveling(PI) begin...
5283 10:04:34.365938 ==
5284 10:04:34.368778 Dram Type= 6, Freq= 0, CH_0, rank 1
5285 10:04:34.372153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 10:04:34.372357 ==
5287 10:04:34.375501 Write leveling (Byte 0): 34 => 34
5288 10:04:34.378886 Write leveling (Byte 1): 30 => 30
5289 10:04:34.382003 DramcWriteLeveling(PI) end<-----
5290 10:04:34.382302
5291 10:04:34.382540 ==
5292 10:04:34.385482 Dram Type= 6, Freq= 0, CH_0, rank 1
5293 10:04:34.391781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 10:04:34.391865 ==
5295 10:04:34.391929 [Gating] SW mode calibration
5296 10:04:34.401719 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5297 10:04:34.405236 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5298 10:04:34.408402 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 10:04:34.414991 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 10:04:34.418783 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 10:04:34.421608 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 10:04:34.428251 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 10:04:34.431909 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 10:04:34.434928 0 14 24 | B1->B0 | 3232 3232 | 0 0 | (0 0) (0 0)
5305 10:04:34.441578 0 14 28 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (1 0)
5306 10:04:34.444810 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5307 10:04:34.448151 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 10:04:34.454721 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 10:04:34.458645 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 10:04:34.461759 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 10:04:34.467960 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 10:04:34.471365 0 15 24 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
5313 10:04:34.474893 0 15 28 | B1->B0 | 3838 3f3f | 0 0 | (1 1) (0 0)
5314 10:04:34.481236 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 10:04:34.484545 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 10:04:34.487795 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 10:04:34.494895 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 10:04:34.497533 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 10:04:34.501137 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 10:04:34.507527 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 10:04:34.511053 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5322 10:04:34.514178 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 10:04:34.520810 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 10:04:34.524293 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 10:04:34.527848 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 10:04:34.534244 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 10:04:34.537370 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 10:04:34.541449 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 10:04:34.547577 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 10:04:34.550986 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 10:04:34.554081 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 10:04:34.560245 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 10:04:34.563901 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 10:04:34.566953 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 10:04:34.573547 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 10:04:34.576776 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5337 10:04:34.580541 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5338 10:04:34.586754 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 10:04:34.586838 Total UI for P1: 0, mck2ui 16
5340 10:04:34.593503 best dqsien dly found for B0: ( 1, 2, 26)
5341 10:04:34.593588 Total UI for P1: 0, mck2ui 16
5342 10:04:34.599885 best dqsien dly found for B1: ( 1, 2, 26)
5343 10:04:34.603275 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5344 10:04:34.606657 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5345 10:04:34.606741
5346 10:04:34.609989 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5347 10:04:34.613339 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5348 10:04:34.616922 [Gating] SW calibration Done
5349 10:04:34.617005 ==
5350 10:04:34.619744 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 10:04:34.623324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 10:04:34.623407 ==
5353 10:04:34.626518 RX Vref Scan: 0
5354 10:04:34.626601
5355 10:04:34.626669 RX Vref 0 -> 0, step: 1
5356 10:04:34.626730
5357 10:04:34.630024 RX Delay -80 -> 252, step: 8
5358 10:04:34.633277 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5359 10:04:34.639531 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5360 10:04:34.643532 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5361 10:04:34.646179 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5362 10:04:34.649522 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5363 10:04:34.652834 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5364 10:04:34.659790 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5365 10:04:34.663008 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5366 10:04:34.666018 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5367 10:04:34.669521 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5368 10:04:34.673233 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5369 10:04:34.676122 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5370 10:04:34.682666 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5371 10:04:34.685854 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5372 10:04:34.689421 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5373 10:04:34.692514 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5374 10:04:34.692597 ==
5375 10:04:34.695711 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 10:04:34.699231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 10:04:34.702489 ==
5378 10:04:34.702572 DQS Delay:
5379 10:04:34.702637 DQS0 = 0, DQS1 = 0
5380 10:04:34.706139 DQM Delay:
5381 10:04:34.706222 DQM0 = 103, DQM1 = 90
5382 10:04:34.708888 DQ Delay:
5383 10:04:34.712281 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5384 10:04:34.715909 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5385 10:04:34.718956 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5386 10:04:34.722398 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5387 10:04:34.722481
5388 10:04:34.722546
5389 10:04:34.722607 ==
5390 10:04:34.725621 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 10:04:34.728887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 10:04:34.728971 ==
5393 10:04:34.729036
5394 10:04:34.729095
5395 10:04:34.732116 TX Vref Scan disable
5396 10:04:34.732199 == TX Byte 0 ==
5397 10:04:34.739019 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5398 10:04:34.742374 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5399 10:04:34.742458 == TX Byte 1 ==
5400 10:04:34.748568 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5401 10:04:34.751996 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5402 10:04:34.752080 ==
5403 10:04:34.755158 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 10:04:34.758692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 10:04:34.758777 ==
5406 10:04:34.758844
5407 10:04:34.762277
5408 10:04:34.762359 TX Vref Scan disable
5409 10:04:34.765442 == TX Byte 0 ==
5410 10:04:34.768698 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5411 10:04:34.774994 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5412 10:04:34.775077 == TX Byte 1 ==
5413 10:04:34.778306 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5414 10:04:34.784939 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5415 10:04:34.785023
5416 10:04:34.785088 [DATLAT]
5417 10:04:34.785150 Freq=933, CH0 RK1
5418 10:04:34.785209
5419 10:04:34.788541 DATLAT Default: 0xb
5420 10:04:34.788650 0, 0xFFFF, sum = 0
5421 10:04:34.791844 1, 0xFFFF, sum = 0
5422 10:04:34.791928 2, 0xFFFF, sum = 0
5423 10:04:34.794931 3, 0xFFFF, sum = 0
5424 10:04:34.798487 4, 0xFFFF, sum = 0
5425 10:04:34.798572 5, 0xFFFF, sum = 0
5426 10:04:34.801904 6, 0xFFFF, sum = 0
5427 10:04:34.801989 7, 0xFFFF, sum = 0
5428 10:04:34.805191 8, 0xFFFF, sum = 0
5429 10:04:34.805276 9, 0xFFFF, sum = 0
5430 10:04:34.808047 10, 0x0, sum = 1
5431 10:04:34.808131 11, 0x0, sum = 2
5432 10:04:34.811481 12, 0x0, sum = 3
5433 10:04:34.811566 13, 0x0, sum = 4
5434 10:04:34.811632 best_step = 11
5435 10:04:34.814679
5436 10:04:34.814762 ==
5437 10:04:34.818265 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 10:04:34.821458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 10:04:34.821542 ==
5440 10:04:34.821607 RX Vref Scan: 0
5441 10:04:34.821668
5442 10:04:34.824740 RX Vref 0 -> 0, step: 1
5443 10:04:34.824874
5444 10:04:34.827780 RX Delay -53 -> 252, step: 4
5445 10:04:34.834492 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5446 10:04:34.838260 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5447 10:04:34.841426 iDelay=199, Bit 2, Center 102 (19 ~ 186) 168
5448 10:04:34.844354 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5449 10:04:34.847867 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5450 10:04:34.854256 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5451 10:04:34.857592 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5452 10:04:34.861000 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5453 10:04:34.864474 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5454 10:04:34.867465 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5455 10:04:34.870950 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5456 10:04:34.877537 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5457 10:04:34.880727 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5458 10:04:34.884034 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5459 10:04:34.887159 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5460 10:04:34.890554 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5461 10:04:34.893987 ==
5462 10:04:34.897354 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 10:04:34.900396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 10:04:34.900479 ==
5465 10:04:34.900545 DQS Delay:
5466 10:04:34.903981 DQS0 = 0, DQS1 = 0
5467 10:04:34.904065 DQM Delay:
5468 10:04:34.907002 DQM0 = 104, DQM1 = 92
5469 10:04:34.907085 DQ Delay:
5470 10:04:34.910398 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5471 10:04:34.913826 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =110
5472 10:04:34.917148 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =92
5473 10:04:34.920397 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5474 10:04:34.920480
5475 10:04:34.920546
5476 10:04:34.930180 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5477 10:04:34.930265 CH0 RK1: MR19=505, MR18=2D0D
5478 10:04:34.937029 CH0_RK1: MR19=0x505, MR18=0x2D0D, DQSOSC=407, MR23=63, INC=65, DEC=43
5479 10:04:34.940039 [RxdqsGatingPostProcess] freq 933
5480 10:04:34.946828 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5481 10:04:34.950011 best DQS0 dly(2T, 0.5T) = (0, 10)
5482 10:04:34.953481 best DQS1 dly(2T, 0.5T) = (0, 10)
5483 10:04:34.956451 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5484 10:04:34.959937 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5485 10:04:34.963119 best DQS0 dly(2T, 0.5T) = (0, 10)
5486 10:04:34.966182 best DQS1 dly(2T, 0.5T) = (0, 10)
5487 10:04:34.969721 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5488 10:04:34.973017 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5489 10:04:34.973101 Pre-setting of DQS Precalculation
5490 10:04:34.980216 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5491 10:04:34.980300 ==
5492 10:04:34.983000 Dram Type= 6, Freq= 0, CH_1, rank 0
5493 10:04:34.985999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5494 10:04:34.986083 ==
5495 10:04:34.992920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5496 10:04:34.999226 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5497 10:04:35.002717 [CA 0] Center 37 (7~68) winsize 62
5498 10:04:35.005898 [CA 1] Center 37 (7~68) winsize 62
5499 10:04:35.009673 [CA 2] Center 35 (5~66) winsize 62
5500 10:04:35.012519 [CA 3] Center 34 (4~65) winsize 62
5501 10:04:35.015889 [CA 4] Center 35 (4~66) winsize 63
5502 10:04:35.019232 [CA 5] Center 34 (4~65) winsize 62
5503 10:04:35.019315
5504 10:04:35.022599 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5505 10:04:35.022682
5506 10:04:35.025780 [CATrainingPosCal] consider 1 rank data
5507 10:04:35.029050 u2DelayCellTimex100 = 270/100 ps
5508 10:04:35.032185 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5509 10:04:35.035368 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5510 10:04:35.039258 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5511 10:04:35.042148 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5512 10:04:35.045360 CA4 delay=35 (4~66),Diff = 1 PI (6 cell)
5513 10:04:35.052248 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5514 10:04:35.052332
5515 10:04:35.055442 CA PerBit enable=1, Macro0, CA PI delay=34
5516 10:04:35.055547
5517 10:04:35.058529 [CBTSetCACLKResult] CA Dly = 34
5518 10:04:35.058641 CS Dly: 6 (0~37)
5519 10:04:35.058735 ==
5520 10:04:35.062275 Dram Type= 6, Freq= 0, CH_1, rank 1
5521 10:04:35.065298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 10:04:35.068426 ==
5523 10:04:35.072146 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5524 10:04:35.078919 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5525 10:04:35.082056 [CA 0] Center 38 (8~68) winsize 61
5526 10:04:35.085237 [CA 1] Center 38 (8~69) winsize 62
5527 10:04:35.088730 [CA 2] Center 36 (6~66) winsize 61
5528 10:04:35.091998 [CA 3] Center 35 (6~65) winsize 60
5529 10:04:35.094972 [CA 4] Center 35 (5~65) winsize 61
5530 10:04:35.098201 [CA 5] Center 34 (5~64) winsize 60
5531 10:04:35.098283
5532 10:04:35.101473 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5533 10:04:35.101553
5534 10:04:35.105256 [CATrainingPosCal] consider 2 rank data
5535 10:04:35.108300 u2DelayCellTimex100 = 270/100 ps
5536 10:04:35.111693 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5537 10:04:35.115119 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5538 10:04:35.118249 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5539 10:04:35.124893 CA3 delay=35 (6~65),Diff = 1 PI (6 cell)
5540 10:04:35.128541 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5541 10:04:35.131657 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5542 10:04:35.131829
5543 10:04:35.134746 CA PerBit enable=1, Macro0, CA PI delay=34
5544 10:04:35.134867
5545 10:04:35.138235 [CBTSetCACLKResult] CA Dly = 34
5546 10:04:35.138367 CS Dly: 7 (0~39)
5547 10:04:35.138495
5548 10:04:35.141432 ----->DramcWriteLeveling(PI) begin...
5549 10:04:35.145287 ==
5550 10:04:35.148023 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 10:04:35.151565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 10:04:35.151762 ==
5553 10:04:35.154591 Write leveling (Byte 0): 25 => 25
5554 10:04:35.158222 Write leveling (Byte 1): 30 => 30
5555 10:04:35.161195 DramcWriteLeveling(PI) end<-----
5556 10:04:35.161482
5557 10:04:35.161731 ==
5558 10:04:35.164883 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 10:04:35.168059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 10:04:35.168548 ==
5561 10:04:35.171030 [Gating] SW mode calibration
5562 10:04:35.178159 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5563 10:04:35.184688 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5564 10:04:35.187665 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 10:04:35.190876 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 10:04:35.197700 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 10:04:35.200700 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 10:04:35.204682 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 10:04:35.210947 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 10:04:35.214146 0 14 24 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 0)
5571 10:04:35.217485 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5572 10:04:35.223823 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 10:04:35.227344 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 10:04:35.230798 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 10:04:35.236920 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 10:04:35.240191 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 10:04:35.243412 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 10:04:35.249970 0 15 24 | B1->B0 | 2525 2c2c | 0 1 | (0 0) (0 0)
5579 10:04:35.253226 0 15 28 | B1->B0 | 3939 3d3d | 0 0 | (0 0) (1 1)
5580 10:04:35.256548 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 10:04:35.263132 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 10:04:35.266550 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 10:04:35.269964 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 10:04:35.276430 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 10:04:35.279862 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 10:04:35.283261 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5587 10:04:35.289778 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 10:04:35.292938 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 10:04:35.296599 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 10:04:35.302962 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 10:04:35.306370 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 10:04:35.309649 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 10:04:35.316157 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 10:04:35.319481 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 10:04:35.322944 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 10:04:35.326289 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 10:04:35.332642 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 10:04:35.336265 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 10:04:35.339524 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 10:04:35.346131 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 10:04:35.349229 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5602 10:04:35.352686 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5603 10:04:35.359312 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5604 10:04:35.362637 Total UI for P1: 0, mck2ui 16
5605 10:04:35.366031 best dqsien dly found for B0: ( 1, 2, 22)
5606 10:04:35.369059 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 10:04:35.372588 Total UI for P1: 0, mck2ui 16
5608 10:04:35.376287 best dqsien dly found for B1: ( 1, 2, 28)
5609 10:04:35.379203 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5610 10:04:35.382356 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5611 10:04:35.382439
5612 10:04:35.385693 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5613 10:04:35.392164 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5614 10:04:35.392247 [Gating] SW calibration Done
5615 10:04:35.392313 ==
5616 10:04:35.395655 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 10:04:35.401876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 10:04:35.401959 ==
5619 10:04:35.402024 RX Vref Scan: 0
5620 10:04:35.402084
5621 10:04:35.405421 RX Vref 0 -> 0, step: 1
5622 10:04:35.405503
5623 10:04:35.409116 RX Delay -80 -> 252, step: 8
5624 10:04:35.411944 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5625 10:04:35.415599 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5626 10:04:35.418720 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5627 10:04:35.421909 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5628 10:04:35.428226 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5629 10:04:35.431973 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5630 10:04:35.435094 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5631 10:04:35.438418 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5632 10:04:35.441803 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5633 10:04:35.448047 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5634 10:04:35.451392 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5635 10:04:35.455165 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5636 10:04:35.458109 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5637 10:04:35.461391 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5638 10:04:35.468324 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5639 10:04:35.471306 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5640 10:04:35.471388 ==
5641 10:04:35.474600 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 10:04:35.477905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 10:04:35.477988 ==
5644 10:04:35.478054 DQS Delay:
5645 10:04:35.481149 DQS0 = 0, DQS1 = 0
5646 10:04:35.481231 DQM Delay:
5647 10:04:35.484519 DQM0 = 101, DQM1 = 95
5648 10:04:35.484601 DQ Delay:
5649 10:04:35.487950 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5650 10:04:35.491124 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5651 10:04:35.494332 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5652 10:04:35.497649 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5653 10:04:35.497732
5654 10:04:35.497797
5655 10:04:35.497857 ==
5656 10:04:35.501020 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 10:04:35.507461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 10:04:35.507543 ==
5659 10:04:35.507609
5660 10:04:35.507668
5661 10:04:35.507726 TX Vref Scan disable
5662 10:04:35.511290 == TX Byte 0 ==
5663 10:04:35.514386 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5664 10:04:35.521389 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5665 10:04:35.521471 == TX Byte 1 ==
5666 10:04:35.524337 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5667 10:04:35.530946 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5668 10:04:35.531027 ==
5669 10:04:35.534545 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 10:04:35.538175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 10:04:35.538287 ==
5672 10:04:35.538351
5673 10:04:35.538434
5674 10:04:35.541285 TX Vref Scan disable
5675 10:04:35.541367 == TX Byte 0 ==
5676 10:04:35.547680 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5677 10:04:35.551294 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5678 10:04:35.551376 == TX Byte 1 ==
5679 10:04:35.557378 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5680 10:04:35.560587 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5681 10:04:35.560694
5682 10:04:35.560760 [DATLAT]
5683 10:04:35.564291 Freq=933, CH1 RK0
5684 10:04:35.564373
5685 10:04:35.564437 DATLAT Default: 0xd
5686 10:04:35.567298 0, 0xFFFF, sum = 0
5687 10:04:35.567380 1, 0xFFFF, sum = 0
5688 10:04:35.570955 2, 0xFFFF, sum = 0
5689 10:04:35.574338 3, 0xFFFF, sum = 0
5690 10:04:35.574435 4, 0xFFFF, sum = 0
5691 10:04:35.577680 5, 0xFFFF, sum = 0
5692 10:04:35.577763 6, 0xFFFF, sum = 0
5693 10:04:35.580671 7, 0xFFFF, sum = 0
5694 10:04:35.580755 8, 0xFFFF, sum = 0
5695 10:04:35.584071 9, 0xFFFF, sum = 0
5696 10:04:35.584154 10, 0x0, sum = 1
5697 10:04:35.587197 11, 0x0, sum = 2
5698 10:04:35.587280 12, 0x0, sum = 3
5699 10:04:35.590497 13, 0x0, sum = 4
5700 10:04:35.590579 best_step = 11
5701 10:04:35.590644
5702 10:04:35.590704 ==
5703 10:04:35.593764 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 10:04:35.597099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 10:04:35.597181 ==
5706 10:04:35.600712 RX Vref Scan: 1
5707 10:04:35.600833
5708 10:04:35.603835 RX Vref 0 -> 0, step: 1
5709 10:04:35.603916
5710 10:04:35.603981 RX Delay -53 -> 252, step: 4
5711 10:04:35.606915
5712 10:04:35.606996 Set Vref, RX VrefLevel [Byte0]: 52
5713 10:04:35.610497 [Byte1]: 52
5714 10:04:35.615332
5715 10:04:35.615413 Final RX Vref Byte 0 = 52 to rank0
5716 10:04:35.618715 Final RX Vref Byte 1 = 52 to rank0
5717 10:04:35.621782 Final RX Vref Byte 0 = 52 to rank1
5718 10:04:35.625122 Final RX Vref Byte 1 = 52 to rank1==
5719 10:04:35.628529 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 10:04:35.634786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 10:04:35.634868 ==
5722 10:04:35.634933 DQS Delay:
5723 10:04:35.638160 DQS0 = 0, DQS1 = 0
5724 10:04:35.638241 DQM Delay:
5725 10:04:35.638307 DQM0 = 104, DQM1 = 97
5726 10:04:35.641537 DQ Delay:
5727 10:04:35.644723 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5728 10:04:35.648405 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5729 10:04:35.651520 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =90
5730 10:04:35.654607 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =104
5731 10:04:35.654706
5732 10:04:35.654785
5733 10:04:35.661664 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5734 10:04:35.664878 CH1 RK0: MR19=505, MR18=1B32
5735 10:04:35.671173 CH1_RK0: MR19=0x505, MR18=0x1B32, DQSOSC=406, MR23=63, INC=65, DEC=43
5736 10:04:35.671256
5737 10:04:35.674640 ----->DramcWriteLeveling(PI) begin...
5738 10:04:35.674739 ==
5739 10:04:35.678199 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 10:04:35.684561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 10:04:35.684643 ==
5742 10:04:35.687792 Write leveling (Byte 0): 29 => 29
5743 10:04:35.687874 Write leveling (Byte 1): 30 => 30
5744 10:04:35.690949 DramcWriteLeveling(PI) end<-----
5745 10:04:35.691031
5746 10:04:35.694496 ==
5747 10:04:35.694578 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 10:04:35.700830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 10:04:35.700926 ==
5750 10:04:35.704216 [Gating] SW mode calibration
5751 10:04:35.710865 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5752 10:04:35.714231 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5753 10:04:35.720711 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5754 10:04:35.723965 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 10:04:35.727593 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 10:04:35.733902 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 10:04:35.737125 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 10:04:35.740712 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 10:04:35.747446 0 14 24 | B1->B0 | 2f2f 3232 | 0 0 | (0 0) (0 0)
5760 10:04:35.750461 0 14 28 | B1->B0 | 2323 2828 | 0 0 | (1 0) (0 0)
5761 10:04:35.754148 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5762 10:04:35.760646 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 10:04:35.763851 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 10:04:35.766956 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 10:04:35.773533 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 10:04:35.777021 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 10:04:35.780223 0 15 24 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5768 10:04:35.787078 0 15 28 | B1->B0 | 3c3c 3636 | 0 0 | (0 0) (0 0)
5769 10:04:35.790266 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 10:04:35.793672 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 10:04:35.800084 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 10:04:35.803430 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 10:04:35.806517 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 10:04:35.813227 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 10:04:35.816318 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5776 10:04:35.819675 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5777 10:04:35.826350 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 10:04:35.829737 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 10:04:35.832927 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 10:04:35.839595 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 10:04:35.843076 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 10:04:35.846140 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 10:04:35.852688 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 10:04:35.856162 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 10:04:35.859412 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 10:04:35.866087 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 10:04:35.869669 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 10:04:35.872741 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 10:04:35.879312 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 10:04:35.882738 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 10:04:35.886072 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5792 10:04:35.892300 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5793 10:04:35.892384 Total UI for P1: 0, mck2ui 16
5794 10:04:35.899076 best dqsien dly found for B1: ( 1, 2, 24)
5795 10:04:35.902393 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 10:04:35.905639 Total UI for P1: 0, mck2ui 16
5797 10:04:35.909028 best dqsien dly found for B0: ( 1, 2, 28)
5798 10:04:35.912296 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5799 10:04:35.915794 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5800 10:04:35.915877
5801 10:04:35.918675 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5802 10:04:35.921999 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5803 10:04:35.925541 [Gating] SW calibration Done
5804 10:04:35.925624 ==
5805 10:04:35.928476 Dram Type= 6, Freq= 0, CH_1, rank 1
5806 10:04:35.931872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5807 10:04:35.935058 ==
5808 10:04:35.935142 RX Vref Scan: 0
5809 10:04:35.935208
5810 10:04:35.938777 RX Vref 0 -> 0, step: 1
5811 10:04:35.938861
5812 10:04:35.941857 RX Delay -80 -> 252, step: 8
5813 10:04:35.945239 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5814 10:04:35.948319 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5815 10:04:35.951719 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5816 10:04:35.955054 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5817 10:04:35.961793 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5818 10:04:35.964798 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5819 10:04:35.968371 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5820 10:04:35.971660 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5821 10:04:35.975367 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5822 10:04:35.978330 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5823 10:04:35.985041 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5824 10:04:35.988099 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5825 10:04:35.991307 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5826 10:04:35.994624 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5827 10:04:35.998349 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5828 10:04:36.004924 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5829 10:04:36.005103 ==
5830 10:04:36.007904 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 10:04:36.011317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 10:04:36.011535 ==
5833 10:04:36.011656 DQS Delay:
5834 10:04:36.014769 DQS0 = 0, DQS1 = 0
5835 10:04:36.014999 DQM Delay:
5836 10:04:36.018141 DQM0 = 103, DQM1 = 97
5837 10:04:36.018318 DQ Delay:
5838 10:04:36.021303 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5839 10:04:36.024867 DQ4 =103, DQ5 =115, DQ6 =107, DQ7 =103
5840 10:04:36.027984 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5841 10:04:36.031238 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5842 10:04:36.031562
5843 10:04:36.031780
5844 10:04:36.034700 ==
5845 10:04:36.035080 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 10:04:36.041219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 10:04:36.041620 ==
5848 10:04:36.041930
5849 10:04:36.042224
5850 10:04:36.044444 TX Vref Scan disable
5851 10:04:36.044956 == TX Byte 0 ==
5852 10:04:36.048184 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5853 10:04:36.054702 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5854 10:04:36.055173 == TX Byte 1 ==
5855 10:04:36.061100 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5856 10:04:36.064573 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5857 10:04:36.065079 ==
5858 10:04:36.067942 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 10:04:36.071302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 10:04:36.071789 ==
5861 10:04:36.072244
5862 10:04:36.072859
5863 10:04:36.074176 TX Vref Scan disable
5864 10:04:36.077967 == TX Byte 0 ==
5865 10:04:36.080946 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5866 10:04:36.084035 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5867 10:04:36.087608 == TX Byte 1 ==
5868 10:04:36.090304 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5869 10:04:36.093532 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5870 10:04:36.093615
5871 10:04:36.096897 [DATLAT]
5872 10:04:36.096978 Freq=933, CH1 RK1
5873 10:04:36.097044
5874 10:04:36.100691 DATLAT Default: 0xb
5875 10:04:36.101294 0, 0xFFFF, sum = 0
5876 10:04:36.103895 1, 0xFFFF, sum = 0
5877 10:04:36.104403 2, 0xFFFF, sum = 0
5878 10:04:36.107170 3, 0xFFFF, sum = 0
5879 10:04:36.107647 4, 0xFFFF, sum = 0
5880 10:04:36.110504 5, 0xFFFF, sum = 0
5881 10:04:36.110980 6, 0xFFFF, sum = 0
5882 10:04:36.114127 7, 0xFFFF, sum = 0
5883 10:04:36.114600 8, 0xFFFF, sum = 0
5884 10:04:36.117120 9, 0xFFFF, sum = 0
5885 10:04:36.117593 10, 0x0, sum = 1
5886 10:04:36.120288 11, 0x0, sum = 2
5887 10:04:36.120791 12, 0x0, sum = 3
5888 10:04:36.123560 13, 0x0, sum = 4
5889 10:04:36.124033 best_step = 11
5890 10:04:36.124403
5891 10:04:36.124748 ==
5892 10:04:36.126822 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 10:04:36.133680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 10:04:36.134149 ==
5895 10:04:36.134520 RX Vref Scan: 0
5896 10:04:36.134864
5897 10:04:36.136818 RX Vref 0 -> 0, step: 1
5898 10:04:36.137286
5899 10:04:36.140227 RX Delay -53 -> 252, step: 4
5900 10:04:36.143652 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5901 10:04:36.149932 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5902 10:04:36.153440 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5903 10:04:36.156581 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5904 10:04:36.159935 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5905 10:04:36.163547 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5906 10:04:36.169887 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5907 10:04:36.173240 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5908 10:04:36.176126 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5909 10:04:36.179877 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5910 10:04:36.182935 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5911 10:04:36.186211 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5912 10:04:36.193214 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5913 10:04:36.196247 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5914 10:04:36.199376 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5915 10:04:36.202888 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5916 10:04:36.203470 ==
5917 10:04:36.205906 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 10:04:36.212902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 10:04:36.213491 ==
5920 10:04:36.213983 DQS Delay:
5921 10:04:36.215994 DQS0 = 0, DQS1 = 0
5922 10:04:36.216570 DQM Delay:
5923 10:04:36.219604 DQM0 = 104, DQM1 = 97
5924 10:04:36.220105 DQ Delay:
5925 10:04:36.222756 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5926 10:04:36.226197 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5927 10:04:36.229132 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =90
5928 10:04:36.232603 DQ12 =108, DQ13 =104, DQ14 =104, DQ15 =106
5929 10:04:36.233220
5930 10:04:36.233703
5931 10:04:36.242968 [DQSOSCAuto] RK1, (LSB)MR18= 0x2401, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
5932 10:04:36.243555 CH1 RK1: MR19=505, MR18=2401
5933 10:04:36.249631 CH1_RK1: MR19=0x505, MR18=0x2401, DQSOSC=410, MR23=63, INC=64, DEC=42
5934 10:04:36.252564 [RxdqsGatingPostProcess] freq 933
5935 10:04:36.259065 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5936 10:04:36.262201 best DQS0 dly(2T, 0.5T) = (0, 10)
5937 10:04:36.265545 best DQS1 dly(2T, 0.5T) = (0, 10)
5938 10:04:36.269204 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5939 10:04:36.271950 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5940 10:04:36.275789 best DQS0 dly(2T, 0.5T) = (0, 10)
5941 10:04:36.276372 best DQS1 dly(2T, 0.5T) = (0, 10)
5942 10:04:36.278780 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5943 10:04:36.282349 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5944 10:04:36.286054 Pre-setting of DQS Precalculation
5945 10:04:36.292438 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5946 10:04:36.298657 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5947 10:04:36.305191 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5948 10:04:36.305758
5949 10:04:36.306239
5950 10:04:36.308398 [Calibration Summary] 1866 Mbps
5951 10:04:36.312155 CH 0, Rank 0
5952 10:04:36.312738 SW Impedance : PASS
5953 10:04:36.315472 DUTY Scan : NO K
5954 10:04:36.316036 ZQ Calibration : PASS
5955 10:04:36.318847 Jitter Meter : NO K
5956 10:04:36.321814 CBT Training : PASS
5957 10:04:36.322279 Write leveling : PASS
5958 10:04:36.324945 RX DQS gating : PASS
5959 10:04:36.328482 RX DQ/DQS(RDDQC) : PASS
5960 10:04:36.328975 TX DQ/DQS : PASS
5961 10:04:36.332069 RX DATLAT : PASS
5962 10:04:36.335034 RX DQ/DQS(Engine): PASS
5963 10:04:36.335599 TX OE : NO K
5964 10:04:36.338688 All Pass.
5965 10:04:36.339248
5966 10:04:36.339623 CH 0, Rank 1
5967 10:04:36.341492 SW Impedance : PASS
5968 10:04:36.341959 DUTY Scan : NO K
5969 10:04:36.345154 ZQ Calibration : PASS
5970 10:04:36.348404 Jitter Meter : NO K
5971 10:04:36.349002 CBT Training : PASS
5972 10:04:36.351815 Write leveling : PASS
5973 10:04:36.355047 RX DQS gating : PASS
5974 10:04:36.355611 RX DQ/DQS(RDDQC) : PASS
5975 10:04:36.358474 TX DQ/DQS : PASS
5976 10:04:36.361515 RX DATLAT : PASS
5977 10:04:36.362075 RX DQ/DQS(Engine): PASS
5978 10:04:36.364865 TX OE : NO K
5979 10:04:36.365430 All Pass.
5980 10:04:36.365798
5981 10:04:36.368436 CH 1, Rank 0
5982 10:04:36.369028 SW Impedance : PASS
5983 10:04:36.371408 DUTY Scan : NO K
5984 10:04:36.374639 ZQ Calibration : PASS
5985 10:04:36.375108 Jitter Meter : NO K
5986 10:04:36.377844 CBT Training : PASS
5987 10:04:36.378311 Write leveling : PASS
5988 10:04:36.381450 RX DQS gating : PASS
5989 10:04:36.384671 RX DQ/DQS(RDDQC) : PASS
5990 10:04:36.385164 TX DQ/DQS : PASS
5991 10:04:36.387626 RX DATLAT : PASS
5992 10:04:36.391230 RX DQ/DQS(Engine): PASS
5993 10:04:36.391793 TX OE : NO K
5994 10:04:36.394979 All Pass.
5995 10:04:36.395542
5996 10:04:36.395913 CH 1, Rank 1
5997 10:04:36.398135 SW Impedance : PASS
5998 10:04:36.398601 DUTY Scan : NO K
5999 10:04:36.401014 ZQ Calibration : PASS
6000 10:04:36.404300 Jitter Meter : NO K
6001 10:04:36.404801 CBT Training : PASS
6002 10:04:36.407950 Write leveling : PASS
6003 10:04:36.411158 RX DQS gating : PASS
6004 10:04:36.411726 RX DQ/DQS(RDDQC) : PASS
6005 10:04:36.414486 TX DQ/DQS : PASS
6006 10:04:36.417990 RX DATLAT : PASS
6007 10:04:36.418555 RX DQ/DQS(Engine): PASS
6008 10:04:36.421160 TX OE : NO K
6009 10:04:36.421646 All Pass.
6010 10:04:36.422015
6011 10:04:36.424268 DramC Write-DBI off
6012 10:04:36.427587 PER_BANK_REFRESH: Hybrid Mode
6013 10:04:36.428049 TX_TRACKING: ON
6014 10:04:36.437739 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6015 10:04:36.440974 [FAST_K] Save calibration result to emmc
6016 10:04:36.444496 dramc_set_vcore_voltage set vcore to 650000
6017 10:04:36.447922 Read voltage for 400, 6
6018 10:04:36.448484 Vio18 = 0
6019 10:04:36.448908 Vcore = 650000
6020 10:04:36.450950 Vdram = 0
6021 10:04:36.451409 Vddq = 0
6022 10:04:36.451770 Vmddr = 0
6023 10:04:36.457662 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6024 10:04:36.460951 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6025 10:04:36.464186 MEM_TYPE=3, freq_sel=20
6026 10:04:36.467443 sv_algorithm_assistance_LP4_800
6027 10:04:36.470976 ============ PULL DRAM RESETB DOWN ============
6028 10:04:36.473385 ========== PULL DRAM RESETB DOWN end =========
6029 10:04:36.480892 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6030 10:04:36.483994 ===================================
6031 10:04:36.486883 LPDDR4 DRAM CONFIGURATION
6032 10:04:36.490310 ===================================
6033 10:04:36.490775 EX_ROW_EN[0] = 0x0
6034 10:04:36.494091 EX_ROW_EN[1] = 0x0
6035 10:04:36.494668 LP4Y_EN = 0x0
6036 10:04:36.496907 WORK_FSP = 0x0
6037 10:04:36.497371 WL = 0x2
6038 10:04:36.500450 RL = 0x2
6039 10:04:36.501063 BL = 0x2
6040 10:04:36.503796 RPST = 0x0
6041 10:04:36.504359 RD_PRE = 0x0
6042 10:04:36.507250 WR_PRE = 0x1
6043 10:04:36.507812 WR_PST = 0x0
6044 10:04:36.510125 DBI_WR = 0x0
6045 10:04:36.510588 DBI_RD = 0x0
6046 10:04:36.513088 OTF = 0x1
6047 10:04:36.516513 ===================================
6048 10:04:36.519951 ===================================
6049 10:04:36.520434 ANA top config
6050 10:04:36.523102 ===================================
6051 10:04:36.526425 DLL_ASYNC_EN = 0
6052 10:04:36.529554 ALL_SLAVE_EN = 1
6053 10:04:36.533281 NEW_RANK_MODE = 1
6054 10:04:36.536557 DLL_IDLE_MODE = 1
6055 10:04:36.537178 LP45_APHY_COMB_EN = 1
6056 10:04:36.539495 TX_ODT_DIS = 1
6057 10:04:36.542949 NEW_8X_MODE = 1
6058 10:04:36.546192 ===================================
6059 10:04:36.549705 ===================================
6060 10:04:36.553655 data_rate = 800
6061 10:04:36.556705 CKR = 1
6062 10:04:36.557298 DQ_P2S_RATIO = 4
6063 10:04:36.559921 ===================================
6064 10:04:36.563035 CA_P2S_RATIO = 4
6065 10:04:36.566391 DQ_CA_OPEN = 0
6066 10:04:36.569688 DQ_SEMI_OPEN = 1
6067 10:04:36.572915 CA_SEMI_OPEN = 1
6068 10:04:36.575933 CA_FULL_RATE = 0
6069 10:04:36.576423 DQ_CKDIV4_EN = 0
6070 10:04:36.579322 CA_CKDIV4_EN = 1
6071 10:04:36.582747 CA_PREDIV_EN = 0
6072 10:04:36.586199 PH8_DLY = 0
6073 10:04:36.589831 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6074 10:04:36.592934 DQ_AAMCK_DIV = 0
6075 10:04:36.593494 CA_AAMCK_DIV = 0
6076 10:04:36.596477 CA_ADMCK_DIV = 4
6077 10:04:36.599512 DQ_TRACK_CA_EN = 0
6078 10:04:36.603270 CA_PICK = 800
6079 10:04:36.606119 CA_MCKIO = 400
6080 10:04:36.609435 MCKIO_SEMI = 400
6081 10:04:36.612388 PLL_FREQ = 3016
6082 10:04:36.615869 DQ_UI_PI_RATIO = 32
6083 10:04:36.616488 CA_UI_PI_RATIO = 32
6084 10:04:36.619338 ===================================
6085 10:04:36.622402 ===================================
6086 10:04:36.625722 memory_type:LPDDR4
6087 10:04:36.629075 GP_NUM : 10
6088 10:04:36.629635 SRAM_EN : 1
6089 10:04:36.632167 MD32_EN : 0
6090 10:04:36.635551 ===================================
6091 10:04:36.638777 [ANA_INIT] >>>>>>>>>>>>>>
6092 10:04:36.642421 <<<<<< [CONFIGURE PHASE]: ANA_TX
6093 10:04:36.645276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6094 10:04:36.649425 ===================================
6095 10:04:36.650020 data_rate = 800,PCW = 0X7400
6096 10:04:36.652215 ===================================
6097 10:04:36.655749 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6098 10:04:36.661958 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6099 10:04:36.672072 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6100 10:04:36.678684 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6101 10:04:36.681991 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6102 10:04:36.685343 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6103 10:04:36.688327 [ANA_INIT] flow start
6104 10:04:36.688827 [ANA_INIT] PLL >>>>>>>>
6105 10:04:36.691930 [ANA_INIT] PLL <<<<<<<<
6106 10:04:36.695756 [ANA_INIT] MIDPI >>>>>>>>
6107 10:04:36.696328 [ANA_INIT] MIDPI <<<<<<<<
6108 10:04:36.698631 [ANA_INIT] DLL >>>>>>>>
6109 10:04:36.701788 [ANA_INIT] flow end
6110 10:04:36.705190 ============ LP4 DIFF to SE enter ============
6111 10:04:36.708364 ============ LP4 DIFF to SE exit ============
6112 10:04:36.711676 [ANA_INIT] <<<<<<<<<<<<<
6113 10:04:36.714996 [Flow] Enable top DCM control >>>>>
6114 10:04:36.718295 [Flow] Enable top DCM control <<<<<
6115 10:04:36.721436 Enable DLL master slave shuffle
6116 10:04:36.724896 ==============================================================
6117 10:04:36.728481 Gating Mode config
6118 10:04:36.735191 ==============================================================
6119 10:04:36.735626 Config description:
6120 10:04:36.744856 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6121 10:04:36.751629 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6122 10:04:36.758327 SELPH_MODE 0: By rank 1: By Phase
6123 10:04:36.761691 ==============================================================
6124 10:04:36.765531 GAT_TRACK_EN = 0
6125 10:04:36.768618 RX_GATING_MODE = 2
6126 10:04:36.771613 RX_GATING_TRACK_MODE = 2
6127 10:04:36.774640 SELPH_MODE = 1
6128 10:04:36.777820 PICG_EARLY_EN = 1
6129 10:04:36.781117 VALID_LAT_VALUE = 1
6130 10:04:36.784643 ==============================================================
6131 10:04:36.787987 Enter into Gating configuration >>>>
6132 10:04:36.791262 Exit from Gating configuration <<<<
6133 10:04:36.794576 Enter into DVFS_PRE_config >>>>>
6134 10:04:36.807845 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6135 10:04:36.811130 Exit from DVFS_PRE_config <<<<<
6136 10:04:36.814553 Enter into PICG configuration >>>>
6137 10:04:36.815130 Exit from PICG configuration <<<<
6138 10:04:36.818298 [RX_INPUT] configuration >>>>>
6139 10:04:36.820801 [RX_INPUT] configuration <<<<<
6140 10:04:36.827625 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6141 10:04:36.830864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6142 10:04:36.837391 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6143 10:04:36.844171 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6144 10:04:36.850652 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6145 10:04:36.857142 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6146 10:04:36.860537 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6147 10:04:36.863848 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6148 10:04:36.870319 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6149 10:04:36.874094 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6150 10:04:36.876737 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6151 10:04:36.880196 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6152 10:04:36.883387 ===================================
6153 10:04:36.886850 LPDDR4 DRAM CONFIGURATION
6154 10:04:36.890091 ===================================
6155 10:04:36.893672 EX_ROW_EN[0] = 0x0
6156 10:04:36.894243 EX_ROW_EN[1] = 0x0
6157 10:04:36.896921 LP4Y_EN = 0x0
6158 10:04:36.897487 WORK_FSP = 0x0
6159 10:04:36.900725 WL = 0x2
6160 10:04:36.901335 RL = 0x2
6161 10:04:36.903513 BL = 0x2
6162 10:04:36.906758 RPST = 0x0
6163 10:04:36.907329 RD_PRE = 0x0
6164 10:04:36.910169 WR_PRE = 0x1
6165 10:04:36.910744 WR_PST = 0x0
6166 10:04:36.913553 DBI_WR = 0x0
6167 10:04:36.914124 DBI_RD = 0x0
6168 10:04:36.916894 OTF = 0x1
6169 10:04:36.920363 ===================================
6170 10:04:36.923241 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6171 10:04:36.926656 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6172 10:04:36.929467 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6173 10:04:36.933213 ===================================
6174 10:04:36.936832 LPDDR4 DRAM CONFIGURATION
6175 10:04:36.939877 ===================================
6176 10:04:36.943112 EX_ROW_EN[0] = 0x10
6177 10:04:36.943699 EX_ROW_EN[1] = 0x0
6178 10:04:36.946204 LP4Y_EN = 0x0
6179 10:04:36.946741 WORK_FSP = 0x0
6180 10:04:36.949896 WL = 0x2
6181 10:04:36.950467 RL = 0x2
6182 10:04:36.952863 BL = 0x2
6183 10:04:36.953334 RPST = 0x0
6184 10:04:36.956308 RD_PRE = 0x0
6185 10:04:36.956808 WR_PRE = 0x1
6186 10:04:36.959934 WR_PST = 0x0
6187 10:04:36.962970 DBI_WR = 0x0
6188 10:04:36.963437 DBI_RD = 0x0
6189 10:04:36.966223 OTF = 0x1
6190 10:04:36.969461 ===================================
6191 10:04:36.973394 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6192 10:04:36.978268 nWR fixed to 30
6193 10:04:36.981523 [ModeRegInit_LP4] CH0 RK0
6194 10:04:36.982097 [ModeRegInit_LP4] CH0 RK1
6195 10:04:36.985044 [ModeRegInit_LP4] CH1 RK0
6196 10:04:36.988113 [ModeRegInit_LP4] CH1 RK1
6197 10:04:36.988684 match AC timing 19
6198 10:04:36.994555 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6199 10:04:36.997880 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6200 10:04:37.001338 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6201 10:04:37.007703 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6202 10:04:37.011143 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6203 10:04:37.011716 ==
6204 10:04:37.014713 Dram Type= 6, Freq= 0, CH_0, rank 0
6205 10:04:37.017435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6206 10:04:37.017913 ==
6207 10:04:37.024235 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6208 10:04:37.030997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6209 10:04:37.034275 [CA 0] Center 36 (8~64) winsize 57
6210 10:04:37.037675 [CA 1] Center 36 (8~64) winsize 57
6211 10:04:37.040898 [CA 2] Center 36 (8~64) winsize 57
6212 10:04:37.044313 [CA 3] Center 36 (8~64) winsize 57
6213 10:04:37.047369 [CA 4] Center 36 (8~64) winsize 57
6214 10:04:37.050853 [CA 5] Center 36 (8~64) winsize 57
6215 10:04:37.051558
6216 10:04:37.053878 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6217 10:04:37.054445
6218 10:04:37.057708 [CATrainingPosCal] consider 1 rank data
6219 10:04:37.060694 u2DelayCellTimex100 = 270/100 ps
6220 10:04:37.063711 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 10:04:37.067416 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 10:04:37.070583 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 10:04:37.073694 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 10:04:37.077224 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 10:04:37.080516 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 10:04:37.081078
6227 10:04:37.084078 CA PerBit enable=1, Macro0, CA PI delay=36
6228 10:04:37.087141
6229 10:04:37.087724 [CBTSetCACLKResult] CA Dly = 36
6230 10:04:37.090521 CS Dly: 1 (0~32)
6231 10:04:37.091091 ==
6232 10:04:37.093693 Dram Type= 6, Freq= 0, CH_0, rank 1
6233 10:04:37.097086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6234 10:04:37.097661 ==
6235 10:04:37.103495 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6236 10:04:37.110255 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6237 10:04:37.113706 [CA 0] Center 36 (8~64) winsize 57
6238 10:04:37.116960 [CA 1] Center 36 (8~64) winsize 57
6239 10:04:37.120099 [CA 2] Center 36 (8~64) winsize 57
6240 10:04:37.120686 [CA 3] Center 36 (8~64) winsize 57
6241 10:04:37.123215 [CA 4] Center 36 (8~64) winsize 57
6242 10:04:37.126972 [CA 5] Center 36 (8~64) winsize 57
6243 10:04:37.127541
6244 10:04:37.133200 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6245 10:04:37.133783
6246 10:04:37.136688 [CATrainingPosCal] consider 2 rank data
6247 10:04:37.139890 u2DelayCellTimex100 = 270/100 ps
6248 10:04:37.143158 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 10:04:37.146826 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 10:04:37.149987 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 10:04:37.153589 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 10:04:37.156700 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 10:04:37.159955 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 10:04:37.160529
6255 10:04:37.162834 CA PerBit enable=1, Macro0, CA PI delay=36
6256 10:04:37.163407
6257 10:04:37.166306 [CBTSetCACLKResult] CA Dly = 36
6258 10:04:37.169718 CS Dly: 1 (0~32)
6259 10:04:37.170308
6260 10:04:37.172747 ----->DramcWriteLeveling(PI) begin...
6261 10:04:37.173262 ==
6262 10:04:37.176720 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 10:04:37.179419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 10:04:37.179893 ==
6265 10:04:37.182818 Write leveling (Byte 0): 40 => 8
6266 10:04:37.186448 Write leveling (Byte 1): 32 => 0
6267 10:04:37.189449 DramcWriteLeveling(PI) end<-----
6268 10:04:37.189914
6269 10:04:37.190335 ==
6270 10:04:37.192858 Dram Type= 6, Freq= 0, CH_0, rank 0
6271 10:04:37.195943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 10:04:37.196412 ==
6273 10:04:37.199476 [Gating] SW mode calibration
6274 10:04:37.206324 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6275 10:04:37.212799 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6276 10:04:37.215967 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6277 10:04:37.219375 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6278 10:04:37.226010 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 10:04:37.229099 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 10:04:37.232556 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 10:04:37.239350 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 10:04:37.242560 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 10:04:37.245592 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 10:04:37.252119 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6285 10:04:37.256049 Total UI for P1: 0, mck2ui 16
6286 10:04:37.258794 best dqsien dly found for B0: ( 0, 14, 24)
6287 10:04:37.262364 Total UI for P1: 0, mck2ui 16
6288 10:04:37.265708 best dqsien dly found for B1: ( 0, 14, 24)
6289 10:04:37.269206 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6290 10:04:37.272475 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6291 10:04:37.273082
6292 10:04:37.275414 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6293 10:04:37.278481 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6294 10:04:37.281816 [Gating] SW calibration Done
6295 10:04:37.282270 ==
6296 10:04:37.285082 Dram Type= 6, Freq= 0, CH_0, rank 0
6297 10:04:37.288440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 10:04:37.288949 ==
6299 10:04:37.291675 RX Vref Scan: 0
6300 10:04:37.292127
6301 10:04:37.295054 RX Vref 0 -> 0, step: 1
6302 10:04:37.295509
6303 10:04:37.298238 RX Delay -410 -> 252, step: 16
6304 10:04:37.301735 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6305 10:04:37.304541 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6306 10:04:37.308452 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6307 10:04:37.315044 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6308 10:04:37.318078 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6309 10:04:37.321218 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6310 10:04:37.324669 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6311 10:04:37.330969 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6312 10:04:37.334422 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6313 10:04:37.338000 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6314 10:04:37.341274 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6315 10:04:37.347742 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6316 10:04:37.351098 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6317 10:04:37.354592 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6318 10:04:37.357723 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6319 10:04:37.364634 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6320 10:04:37.365080 ==
6321 10:04:37.367700 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 10:04:37.371279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 10:04:37.371696 ==
6324 10:04:37.372025 DQS Delay:
6325 10:04:37.374228 DQS0 = 27, DQS1 = 43
6326 10:04:37.374644 DQM Delay:
6327 10:04:37.377982 DQM0 = 12, DQM1 = 12
6328 10:04:37.378461 DQ Delay:
6329 10:04:37.380839 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6330 10:04:37.384607 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6331 10:04:37.387874 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6332 10:04:37.390948 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6333 10:04:37.391363
6334 10:04:37.391684
6335 10:04:37.391987 ==
6336 10:04:37.394195 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 10:04:37.397740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 10:04:37.398182 ==
6339 10:04:37.401087
6340 10:04:37.401521
6341 10:04:37.401855 TX Vref Scan disable
6342 10:04:37.404187 == TX Byte 0 ==
6343 10:04:37.407449 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 10:04:37.410598 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 10:04:37.413609 == TX Byte 1 ==
6346 10:04:37.416921 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6347 10:04:37.420276 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6348 10:04:37.420357 ==
6349 10:04:37.423322 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 10:04:37.430233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 10:04:37.430314 ==
6352 10:04:37.430378
6353 10:04:37.430438
6354 10:04:37.430495 TX Vref Scan disable
6355 10:04:37.433535 == TX Byte 0 ==
6356 10:04:37.437008 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 10:04:37.439985 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 10:04:37.443500 == TX Byte 1 ==
6359 10:04:37.446566 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6360 10:04:37.450170 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6361 10:04:37.450254
6362 10:04:37.453605 [DATLAT]
6363 10:04:37.453687 Freq=400, CH0 RK0
6364 10:04:37.453753
6365 10:04:37.456724 DATLAT Default: 0xf
6366 10:04:37.456849 0, 0xFFFF, sum = 0
6367 10:04:37.460012 1, 0xFFFF, sum = 0
6368 10:04:37.460096 2, 0xFFFF, sum = 0
6369 10:04:37.463299 3, 0xFFFF, sum = 0
6370 10:04:37.463384 4, 0xFFFF, sum = 0
6371 10:04:37.466970 5, 0xFFFF, sum = 0
6372 10:04:37.467055 6, 0xFFFF, sum = 0
6373 10:04:37.469934 7, 0xFFFF, sum = 0
6374 10:04:37.470027 8, 0xFFFF, sum = 0
6375 10:04:37.473232 9, 0xFFFF, sum = 0
6376 10:04:37.473316 10, 0xFFFF, sum = 0
6377 10:04:37.476859 11, 0xFFFF, sum = 0
6378 10:04:37.480058 12, 0xFFFF, sum = 0
6379 10:04:37.480143 13, 0x0, sum = 1
6380 10:04:37.480211 14, 0x0, sum = 2
6381 10:04:37.483104 15, 0x0, sum = 3
6382 10:04:37.483189 16, 0x0, sum = 4
6383 10:04:37.486671 best_step = 14
6384 10:04:37.486754
6385 10:04:37.486820 ==
6386 10:04:37.489910 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 10:04:37.493125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 10:04:37.493208 ==
6389 10:04:37.496560 RX Vref Scan: 1
6390 10:04:37.496643
6391 10:04:37.496710 RX Vref 0 -> 0, step: 1
6392 10:04:37.499667
6393 10:04:37.499750 RX Delay -327 -> 252, step: 8
6394 10:04:37.499816
6395 10:04:37.503286 Set Vref, RX VrefLevel [Byte0]: 57
6396 10:04:37.506127 [Byte1]: 48
6397 10:04:37.511387
6398 10:04:37.511469 Final RX Vref Byte 0 = 57 to rank0
6399 10:04:37.514565 Final RX Vref Byte 1 = 48 to rank0
6400 10:04:37.517952 Final RX Vref Byte 0 = 57 to rank1
6401 10:04:37.521515 Final RX Vref Byte 1 = 48 to rank1==
6402 10:04:37.524787 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 10:04:37.531285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 10:04:37.531368 ==
6405 10:04:37.531435 DQS Delay:
6406 10:04:37.534836 DQS0 = 24, DQS1 = 48
6407 10:04:37.534919 DQM Delay:
6408 10:04:37.534985 DQM0 = 8, DQM1 = 15
6409 10:04:37.537697 DQ Delay:
6410 10:04:37.541151 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6411 10:04:37.541234 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6412 10:04:37.544612 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6413 10:04:37.548484 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6414 10:04:37.548655
6415 10:04:37.548736
6416 10:04:37.557981 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6417 10:04:37.561360 CH0 RK0: MR19=C0C, MR18=B0A8
6418 10:04:37.568080 CH0_RK0: MR19=0xC0C, MR18=0xB0A8, DQSOSC=387, MR23=63, INC=394, DEC=262
6419 10:04:37.568288 ==
6420 10:04:37.571353 Dram Type= 6, Freq= 0, CH_0, rank 1
6421 10:04:37.574767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 10:04:37.575011 ==
6423 10:04:37.577859 [Gating] SW mode calibration
6424 10:04:37.585094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6425 10:04:37.591310 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6426 10:04:37.594551 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 10:04:37.597883 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6428 10:04:37.604427 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 10:04:37.608305 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 10:04:37.611202 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 10:04:37.617576 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 10:04:37.621033 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 10:04:37.624899 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 10:04:37.630944 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6435 10:04:37.631525 Total UI for P1: 0, mck2ui 16
6436 10:04:37.637605 best dqsien dly found for B0: ( 0, 14, 24)
6437 10:04:37.638182 Total UI for P1: 0, mck2ui 16
6438 10:04:37.640956 best dqsien dly found for B1: ( 0, 14, 24)
6439 10:04:37.647409 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6440 10:04:37.650956 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6441 10:04:37.651527
6442 10:04:37.654369 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6443 10:04:37.657336 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6444 10:04:37.660662 [Gating] SW calibration Done
6445 10:04:37.661162 ==
6446 10:04:37.663824 Dram Type= 6, Freq= 0, CH_0, rank 1
6447 10:04:37.667577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 10:04:37.668158 ==
6449 10:04:37.670672 RX Vref Scan: 0
6450 10:04:37.671247
6451 10:04:37.671621 RX Vref 0 -> 0, step: 1
6452 10:04:37.671972
6453 10:04:37.673964 RX Delay -410 -> 252, step: 16
6454 10:04:37.680232 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6455 10:04:37.684206 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6456 10:04:37.687197 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6457 10:04:37.690615 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6458 10:04:37.696862 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6459 10:04:37.699880 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6460 10:04:37.703266 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6461 10:04:37.706447 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6462 10:04:37.713509 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6463 10:04:37.716710 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6464 10:04:37.719768 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6465 10:04:37.723557 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6466 10:04:37.730023 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6467 10:04:37.733039 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6468 10:04:37.736352 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6469 10:04:37.743209 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6470 10:04:37.743762 ==
6471 10:04:37.746150 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 10:04:37.749682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 10:04:37.750116 ==
6474 10:04:37.750455 DQS Delay:
6475 10:04:37.752677 DQS0 = 27, DQS1 = 43
6476 10:04:37.753140 DQM Delay:
6477 10:04:37.756121 DQM0 = 9, DQM1 = 15
6478 10:04:37.756545 DQ Delay:
6479 10:04:37.759285 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6480 10:04:37.762556 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6481 10:04:37.765773 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6482 10:04:37.769188 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6483 10:04:37.769617
6484 10:04:37.769956
6485 10:04:37.770278 ==
6486 10:04:37.772738 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 10:04:37.775940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 10:04:37.776369 ==
6489 10:04:37.776708
6490 10:04:37.777069
6491 10:04:37.779155 TX Vref Scan disable
6492 10:04:37.779801 == TX Byte 0 ==
6493 10:04:37.785713 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6494 10:04:37.788860 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6495 10:04:37.789289 == TX Byte 1 ==
6496 10:04:37.795720 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6497 10:04:37.798742 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6498 10:04:37.799168 ==
6499 10:04:37.802080 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 10:04:37.805319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 10:04:37.805750 ==
6502 10:04:37.806089
6503 10:04:37.806405
6504 10:04:37.808829 TX Vref Scan disable
6505 10:04:37.812549 == TX Byte 0 ==
6506 10:04:37.815312 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6507 10:04:37.818707 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6508 10:04:37.822191 == TX Byte 1 ==
6509 10:04:37.825449 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6510 10:04:37.828978 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6511 10:04:37.829405
6512 10:04:37.829741 [DATLAT]
6513 10:04:37.831743 Freq=400, CH0 RK1
6514 10:04:37.832169
6515 10:04:37.832509 DATLAT Default: 0xe
6516 10:04:37.834996 0, 0xFFFF, sum = 0
6517 10:04:37.835080 1, 0xFFFF, sum = 0
6518 10:04:37.838395 2, 0xFFFF, sum = 0
6519 10:04:37.841456 3, 0xFFFF, sum = 0
6520 10:04:37.841540 4, 0xFFFF, sum = 0
6521 10:04:37.844752 5, 0xFFFF, sum = 0
6522 10:04:37.844873 6, 0xFFFF, sum = 0
6523 10:04:37.848289 7, 0xFFFF, sum = 0
6524 10:04:37.848374 8, 0xFFFF, sum = 0
6525 10:04:37.851323 9, 0xFFFF, sum = 0
6526 10:04:37.851408 10, 0xFFFF, sum = 0
6527 10:04:37.854678 11, 0xFFFF, sum = 0
6528 10:04:37.854761 12, 0xFFFF, sum = 0
6529 10:04:37.858488 13, 0x0, sum = 1
6530 10:04:37.858572 14, 0x0, sum = 2
6531 10:04:37.861363 15, 0x0, sum = 3
6532 10:04:37.861447 16, 0x0, sum = 4
6533 10:04:37.864879 best_step = 14
6534 10:04:37.864961
6535 10:04:37.865027 ==
6536 10:04:37.868043 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 10:04:37.871292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 10:04:37.871375 ==
6539 10:04:37.875106 RX Vref Scan: 0
6540 10:04:37.875278
6541 10:04:37.875360 RX Vref 0 -> 0, step: 1
6542 10:04:37.875432
6543 10:04:37.878167 RX Delay -327 -> 252, step: 8
6544 10:04:37.885178 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6545 10:04:37.888577 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6546 10:04:37.892277 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6547 10:04:37.898880 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6548 10:04:37.902087 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6549 10:04:37.905322 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6550 10:04:37.908667 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6551 10:04:37.915227 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6552 10:04:37.918903 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6553 10:04:37.922141 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6554 10:04:37.926107 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6555 10:04:37.931798 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6556 10:04:37.935256 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6557 10:04:37.938641 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6558 10:04:37.942074 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6559 10:04:37.948905 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6560 10:04:37.949464 ==
6561 10:04:37.951977 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 10:04:37.955018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 10:04:37.955493 ==
6564 10:04:37.955865 DQS Delay:
6565 10:04:37.958526 DQS0 = 28, DQS1 = 40
6566 10:04:37.959090 DQM Delay:
6567 10:04:37.962280 DQM0 = 10, DQM1 = 11
6568 10:04:37.962841 DQ Delay:
6569 10:04:37.965345 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6570 10:04:37.968510 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6571 10:04:37.971975 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6572 10:04:37.975035 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6573 10:04:37.975603
6574 10:04:37.975972
6575 10:04:37.981678 [DQSOSCAuto] RK1, (LSB)MR18= 0xb86c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6576 10:04:37.985170 CH0 RK1: MR19=C0C, MR18=B86C
6577 10:04:37.991290 CH0_RK1: MR19=0xC0C, MR18=0xB86C, DQSOSC=386, MR23=63, INC=396, DEC=264
6578 10:04:37.994904 [RxdqsGatingPostProcess] freq 400
6579 10:04:38.001456 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6580 10:04:38.004728 best DQS0 dly(2T, 0.5T) = (0, 10)
6581 10:04:38.007936 best DQS1 dly(2T, 0.5T) = (0, 10)
6582 10:04:38.011233 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6583 10:04:38.011702 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6584 10:04:38.014706 best DQS0 dly(2T, 0.5T) = (0, 10)
6585 10:04:38.017959 best DQS1 dly(2T, 0.5T) = (0, 10)
6586 10:04:38.021342 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6587 10:04:38.024482 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6588 10:04:38.027830 Pre-setting of DQS Precalculation
6589 10:04:38.034505 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6590 10:04:38.034945 ==
6591 10:04:38.037739 Dram Type= 6, Freq= 0, CH_1, rank 0
6592 10:04:38.040981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 10:04:38.041406 ==
6594 10:04:38.047503 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6595 10:04:38.054414 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6596 10:04:38.054839 [CA 0] Center 36 (8~64) winsize 57
6597 10:04:38.058111 [CA 1] Center 36 (8~64) winsize 57
6598 10:04:38.060790 [CA 2] Center 36 (8~64) winsize 57
6599 10:04:38.063968 [CA 3] Center 36 (8~64) winsize 57
6600 10:04:38.067322 [CA 4] Center 36 (8~64) winsize 57
6601 10:04:38.070463 [CA 5] Center 36 (8~64) winsize 57
6602 10:04:38.070883
6603 10:04:38.073995 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6604 10:04:38.074418
6605 10:04:38.080503 [CATrainingPosCal] consider 1 rank data
6606 10:04:38.081028 u2DelayCellTimex100 = 270/100 ps
6607 10:04:38.087176 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 10:04:38.090548 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 10:04:38.093928 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 10:04:38.096916 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 10:04:38.100816 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 10:04:38.103918 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 10:04:38.104338
6614 10:04:38.106948 CA PerBit enable=1, Macro0, CA PI delay=36
6615 10:04:38.107372
6616 10:04:38.110536 [CBTSetCACLKResult] CA Dly = 36
6617 10:04:38.113587 CS Dly: 1 (0~32)
6618 10:04:38.114007 ==
6619 10:04:38.117223 Dram Type= 6, Freq= 0, CH_1, rank 1
6620 10:04:38.120277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 10:04:38.120737 ==
6622 10:04:38.127584 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6623 10:04:38.130344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6624 10:04:38.133680 [CA 0] Center 36 (8~64) winsize 57
6625 10:04:38.136888 [CA 1] Center 36 (8~64) winsize 57
6626 10:04:38.140128 [CA 2] Center 36 (8~64) winsize 57
6627 10:04:38.143236 [CA 3] Center 36 (8~64) winsize 57
6628 10:04:38.146490 [CA 4] Center 36 (8~64) winsize 57
6629 10:04:38.149813 [CA 5] Center 36 (8~64) winsize 57
6630 10:04:38.150239
6631 10:04:38.153287 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6632 10:04:38.153728
6633 10:04:38.156467 [CATrainingPosCal] consider 2 rank data
6634 10:04:38.159555 u2DelayCellTimex100 = 270/100 ps
6635 10:04:38.163099 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 10:04:38.166405 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 10:04:38.173288 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 10:04:38.176421 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 10:04:38.179413 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 10:04:38.182794 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 10:04:38.183236
6642 10:04:38.186301 CA PerBit enable=1, Macro0, CA PI delay=36
6643 10:04:38.186738
6644 10:04:38.189583 [CBTSetCACLKResult] CA Dly = 36
6645 10:04:38.190021 CS Dly: 1 (0~32)
6646 10:04:38.190458
6647 10:04:38.193156 ----->DramcWriteLeveling(PI) begin...
6648 10:04:38.196513 ==
6649 10:04:38.199432 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 10:04:38.203107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 10:04:38.203551 ==
6652 10:04:38.205925 Write leveling (Byte 0): 40 => 8
6653 10:04:38.209427 Write leveling (Byte 1): 32 => 0
6654 10:04:38.212666 DramcWriteLeveling(PI) end<-----
6655 10:04:38.213148
6656 10:04:38.213579 ==
6657 10:04:38.216082 Dram Type= 6, Freq= 0, CH_1, rank 0
6658 10:04:38.219026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 10:04:38.219469 ==
6660 10:04:38.222528 [Gating] SW mode calibration
6661 10:04:38.229291 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6662 10:04:38.235604 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6663 10:04:38.239433 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6664 10:04:38.242987 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6665 10:04:38.249241 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 10:04:38.252301 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 10:04:38.255699 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 10:04:38.258845 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 10:04:38.265593 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 10:04:38.269124 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 10:04:38.272486 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6672 10:04:38.275245 Total UI for P1: 0, mck2ui 16
6673 10:04:38.278696 best dqsien dly found for B0: ( 0, 14, 24)
6674 10:04:38.281785 Total UI for P1: 0, mck2ui 16
6675 10:04:38.284996 best dqsien dly found for B1: ( 0, 14, 24)
6676 10:04:38.288627 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6677 10:04:38.295260 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6678 10:04:38.295412
6679 10:04:38.298807 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6680 10:04:38.301871 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6681 10:04:38.305161 [Gating] SW calibration Done
6682 10:04:38.305313 ==
6683 10:04:38.308405 Dram Type= 6, Freq= 0, CH_1, rank 0
6684 10:04:38.311491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 10:04:38.311645 ==
6686 10:04:38.314933 RX Vref Scan: 0
6687 10:04:38.315106
6688 10:04:38.315243 RX Vref 0 -> 0, step: 1
6689 10:04:38.315373
6690 10:04:38.318356 RX Delay -410 -> 252, step: 16
6691 10:04:38.325125 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6692 10:04:38.327980 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6693 10:04:38.331648 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6694 10:04:38.334840 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6695 10:04:38.341564 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6696 10:04:38.344724 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6697 10:04:38.348477 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6698 10:04:38.351515 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6699 10:04:38.357836 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6700 10:04:38.360742 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6701 10:04:38.364351 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6702 10:04:38.367499 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6703 10:04:38.373958 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6704 10:04:38.377259 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6705 10:04:38.380607 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6706 10:04:38.387218 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6707 10:04:38.387302 ==
6708 10:04:38.390491 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 10:04:38.394134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 10:04:38.394217 ==
6711 10:04:38.394282 DQS Delay:
6712 10:04:38.397539 DQS0 = 27, DQS1 = 43
6713 10:04:38.397621 DQM Delay:
6714 10:04:38.400632 DQM0 = 5, DQM1 = 15
6715 10:04:38.400740 DQ Delay:
6716 10:04:38.404143 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6717 10:04:38.407161 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6718 10:04:38.410550 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6719 10:04:38.414040 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6720 10:04:38.414122
6721 10:04:38.414187
6722 10:04:38.414247 ==
6723 10:04:38.417204 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 10:04:38.420741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 10:04:38.420841 ==
6726 10:04:38.420907
6727 10:04:38.420967
6728 10:04:38.424093 TX Vref Scan disable
6729 10:04:38.424175 == TX Byte 0 ==
6730 10:04:38.430409 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 10:04:38.433964 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 10:04:38.434046 == TX Byte 1 ==
6733 10:04:38.440537 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6734 10:04:38.444176 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6735 10:04:38.444259 ==
6736 10:04:38.447035 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 10:04:38.450415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 10:04:38.450497 ==
6739 10:04:38.450562
6740 10:04:38.450620
6741 10:04:38.453636 TX Vref Scan disable
6742 10:04:38.453717 == TX Byte 0 ==
6743 10:04:38.460368 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 10:04:38.464007 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 10:04:38.464089 == TX Byte 1 ==
6746 10:04:38.470131 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6747 10:04:38.473421 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6748 10:04:38.473503
6749 10:04:38.473567 [DATLAT]
6750 10:04:38.476916 Freq=400, CH1 RK0
6751 10:04:38.476998
6752 10:04:38.477062 DATLAT Default: 0xf
6753 10:04:38.480151 0, 0xFFFF, sum = 0
6754 10:04:38.480241 1, 0xFFFF, sum = 0
6755 10:04:38.483228 2, 0xFFFF, sum = 0
6756 10:04:38.486868 3, 0xFFFF, sum = 0
6757 10:04:38.486952 4, 0xFFFF, sum = 0
6758 10:04:38.489900 5, 0xFFFF, sum = 0
6759 10:04:38.489983 6, 0xFFFF, sum = 0
6760 10:04:38.493155 7, 0xFFFF, sum = 0
6761 10:04:38.493238 8, 0xFFFF, sum = 0
6762 10:04:38.496457 9, 0xFFFF, sum = 0
6763 10:04:38.496540 10, 0xFFFF, sum = 0
6764 10:04:38.499823 11, 0xFFFF, sum = 0
6765 10:04:38.499906 12, 0xFFFF, sum = 0
6766 10:04:38.503175 13, 0x0, sum = 1
6767 10:04:38.503258 14, 0x0, sum = 2
6768 10:04:38.506595 15, 0x0, sum = 3
6769 10:04:38.506678 16, 0x0, sum = 4
6770 10:04:38.509710 best_step = 14
6771 10:04:38.509791
6772 10:04:38.509856 ==
6773 10:04:38.513355 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 10:04:38.516390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 10:04:38.516471 ==
6776 10:04:38.519501 RX Vref Scan: 1
6777 10:04:38.519580
6778 10:04:38.519643 RX Vref 0 -> 0, step: 1
6779 10:04:38.519702
6780 10:04:38.522739 RX Delay -327 -> 252, step: 8
6781 10:04:38.522819
6782 10:04:38.526177 Set Vref, RX VrefLevel [Byte0]: 52
6783 10:04:38.529645 [Byte1]: 52
6784 10:04:38.533736
6785 10:04:38.533826 Final RX Vref Byte 0 = 52 to rank0
6786 10:04:38.537207 Final RX Vref Byte 1 = 52 to rank0
6787 10:04:38.540361 Final RX Vref Byte 0 = 52 to rank1
6788 10:04:38.543779 Final RX Vref Byte 1 = 52 to rank1==
6789 10:04:38.547197 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 10:04:38.553734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 10:04:38.553816 ==
6792 10:04:38.553880 DQS Delay:
6793 10:04:38.557255 DQS0 = 32, DQS1 = 40
6794 10:04:38.557334 DQM Delay:
6795 10:04:38.557398 DQM0 = 11, DQM1 = 12
6796 10:04:38.560452 DQ Delay:
6797 10:04:38.563557 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6798 10:04:38.563637 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6799 10:04:38.567062 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6800 10:04:38.570208 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6801 10:04:38.570288
6802 10:04:38.573516
6803 10:04:38.580243 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6804 10:04:38.583240 CH1 RK0: MR19=C0C, MR18=93CD
6805 10:04:38.590066 CH1_RK0: MR19=0xC0C, MR18=0x93CD, DQSOSC=384, MR23=63, INC=400, DEC=267
6806 10:04:38.590149 ==
6807 10:04:38.593181 Dram Type= 6, Freq= 0, CH_1, rank 1
6808 10:04:38.596899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 10:04:38.596981 ==
6810 10:04:38.600134 [Gating] SW mode calibration
6811 10:04:38.606430 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6812 10:04:38.613440 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6813 10:04:38.616664 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6814 10:04:38.619822 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6815 10:04:38.626436 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 10:04:38.629765 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 10:04:38.633145 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 10:04:38.639675 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 10:04:38.642759 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 10:04:38.646504 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 10:04:38.653200 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6822 10:04:38.653284 Total UI for P1: 0, mck2ui 16
6823 10:04:38.659585 best dqsien dly found for B0: ( 0, 14, 24)
6824 10:04:38.659668 Total UI for P1: 0, mck2ui 16
6825 10:04:38.662729 best dqsien dly found for B1: ( 0, 14, 24)
6826 10:04:38.669372 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6827 10:04:38.672890 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6828 10:04:38.672972
6829 10:04:38.675871 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6830 10:04:38.679351 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6831 10:04:38.682934 [Gating] SW calibration Done
6832 10:04:38.683017 ==
6833 10:04:38.686210 Dram Type= 6, Freq= 0, CH_1, rank 1
6834 10:04:38.689337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 10:04:38.689421 ==
6836 10:04:38.692685 RX Vref Scan: 0
6837 10:04:38.692826
6838 10:04:38.692894 RX Vref 0 -> 0, step: 1
6839 10:04:38.692955
6840 10:04:38.696285 RX Delay -410 -> 252, step: 16
6841 10:04:38.702424 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6842 10:04:38.705772 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6843 10:04:38.708882 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6844 10:04:38.712315 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6845 10:04:38.719124 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6846 10:04:38.722350 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6847 10:04:38.725365 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6848 10:04:38.729128 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6849 10:04:38.735416 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6850 10:04:38.738984 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6851 10:04:38.742201 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6852 10:04:38.745180 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6853 10:04:38.752060 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6854 10:04:38.755151 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6855 10:04:38.758613 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6856 10:04:38.762187 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6857 10:04:38.765128 ==
6858 10:04:38.768428 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 10:04:38.771766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 10:04:38.771849 ==
6861 10:04:38.771914 DQS Delay:
6862 10:04:38.775384 DQS0 = 35, DQS1 = 43
6863 10:04:38.775466 DQM Delay:
6864 10:04:38.778539 DQM0 = 16, DQM1 = 19
6865 10:04:38.778621 DQ Delay:
6866 10:04:38.782244 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6867 10:04:38.784918 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6868 10:04:38.788246 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6869 10:04:38.791406 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6870 10:04:38.791488
6871 10:04:38.791553
6872 10:04:38.791612 ==
6873 10:04:38.794976 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 10:04:38.798204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 10:04:38.798287 ==
6876 10:04:38.798352
6877 10:04:38.798411
6878 10:04:38.801613 TX Vref Scan disable
6879 10:04:38.805163 == TX Byte 0 ==
6880 10:04:38.808272 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6881 10:04:38.811356 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6882 10:04:38.814891 == TX Byte 1 ==
6883 10:04:38.818273 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6884 10:04:38.821420 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6885 10:04:38.821503 ==
6886 10:04:38.824594 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 10:04:38.827860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 10:04:38.827944 ==
6889 10:04:38.831340
6890 10:04:38.831422
6891 10:04:38.831487 TX Vref Scan disable
6892 10:04:38.834692 == TX Byte 0 ==
6893 10:04:38.838239 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6894 10:04:38.841062 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6895 10:04:38.844704 == TX Byte 1 ==
6896 10:04:38.847714 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6897 10:04:38.851582 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6898 10:04:38.851665
6899 10:04:38.851730 [DATLAT]
6900 10:04:38.854212 Freq=400, CH1 RK1
6901 10:04:38.854295
6902 10:04:38.854359 DATLAT Default: 0xe
6903 10:04:38.857594 0, 0xFFFF, sum = 0
6904 10:04:38.861373 1, 0xFFFF, sum = 0
6905 10:04:38.861458 2, 0xFFFF, sum = 0
6906 10:04:38.864363 3, 0xFFFF, sum = 0
6907 10:04:38.864447 4, 0xFFFF, sum = 0
6908 10:04:38.867700 5, 0xFFFF, sum = 0
6909 10:04:38.867784 6, 0xFFFF, sum = 0
6910 10:04:38.870859 7, 0xFFFF, sum = 0
6911 10:04:38.870943 8, 0xFFFF, sum = 0
6912 10:04:38.874327 9, 0xFFFF, sum = 0
6913 10:04:38.874410 10, 0xFFFF, sum = 0
6914 10:04:38.877769 11, 0xFFFF, sum = 0
6915 10:04:38.877853 12, 0xFFFF, sum = 0
6916 10:04:38.880773 13, 0x0, sum = 1
6917 10:04:38.880869 14, 0x0, sum = 2
6918 10:04:38.884219 15, 0x0, sum = 3
6919 10:04:38.884304 16, 0x0, sum = 4
6920 10:04:38.887475 best_step = 14
6921 10:04:38.887558
6922 10:04:38.887623 ==
6923 10:04:38.890689 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 10:04:38.894216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 10:04:38.894300 ==
6926 10:04:38.897370 RX Vref Scan: 0
6927 10:04:38.897452
6928 10:04:38.897517 RX Vref 0 -> 0, step: 1
6929 10:04:38.897577
6930 10:04:38.900567 RX Delay -327 -> 252, step: 8
6931 10:04:38.908483 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6932 10:04:38.911930 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6933 10:04:38.914893 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6934 10:04:38.921570 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6935 10:04:38.924732 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6936 10:04:38.928033 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6937 10:04:38.931490 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6938 10:04:38.934833 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6939 10:04:38.941612 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6940 10:04:38.944663 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6941 10:04:38.947975 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6942 10:04:38.954402 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6943 10:04:38.957898 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6944 10:04:38.961109 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6945 10:04:38.964331 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6946 10:04:38.970986 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6947 10:04:38.971068 ==
6948 10:04:38.974810 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 10:04:38.977801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 10:04:38.977884 ==
6951 10:04:38.977949 DQS Delay:
6952 10:04:38.980936 DQS0 = 32, DQS1 = 36
6953 10:04:38.981018 DQM Delay:
6954 10:04:38.984260 DQM0 = 14, DQM1 = 11
6955 10:04:38.984343 DQ Delay:
6956 10:04:38.987549 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =16
6957 10:04:38.990828 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =12
6958 10:04:38.994180 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6959 10:04:38.997705 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6960 10:04:38.997788
6961 10:04:38.997853
6962 10:04:39.007423 [DQSOSCAuto] RK1, (LSB)MR18= 0xab53, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6963 10:04:39.007507 CH1 RK1: MR19=C0C, MR18=AB53
6964 10:04:39.013861 CH1_RK1: MR19=0xC0C, MR18=0xAB53, DQSOSC=388, MR23=63, INC=392, DEC=261
6965 10:04:39.017195 [RxdqsGatingPostProcess] freq 400
6966 10:04:39.023905 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6967 10:04:39.027064 best DQS0 dly(2T, 0.5T) = (0, 10)
6968 10:04:39.030398 best DQS1 dly(2T, 0.5T) = (0, 10)
6969 10:04:39.033836 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6970 10:04:39.037066 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6971 10:04:39.040266 best DQS0 dly(2T, 0.5T) = (0, 10)
6972 10:04:39.040349 best DQS1 dly(2T, 0.5T) = (0, 10)
6973 10:04:39.043639 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6974 10:04:39.046927 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6975 10:04:39.050142 Pre-setting of DQS Precalculation
6976 10:04:39.056698 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6977 10:04:39.063210 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6978 10:04:39.069894 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6979 10:04:39.069978
6980 10:04:39.070042
6981 10:04:39.073351 [Calibration Summary] 800 Mbps
6982 10:04:39.076960 CH 0, Rank 0
6983 10:04:39.077042 SW Impedance : PASS
6984 10:04:39.080252 DUTY Scan : NO K
6985 10:04:39.080334 ZQ Calibration : PASS
6986 10:04:39.083407 Jitter Meter : NO K
6987 10:04:39.086501 CBT Training : PASS
6988 10:04:39.086585 Write leveling : PASS
6989 10:04:39.089879 RX DQS gating : PASS
6990 10:04:39.093116 RX DQ/DQS(RDDQC) : PASS
6991 10:04:39.093200 TX DQ/DQS : PASS
6992 10:04:39.096789 RX DATLAT : PASS
6993 10:04:39.099861 RX DQ/DQS(Engine): PASS
6994 10:04:39.099944 TX OE : NO K
6995 10:04:39.103138 All Pass.
6996 10:04:39.103221
6997 10:04:39.103287 CH 0, Rank 1
6998 10:04:39.106624 SW Impedance : PASS
6999 10:04:39.106707 DUTY Scan : NO K
7000 10:04:39.110214 ZQ Calibration : PASS
7001 10:04:39.113204 Jitter Meter : NO K
7002 10:04:39.113286 CBT Training : PASS
7003 10:04:39.116426 Write leveling : NO K
7004 10:04:39.119467 RX DQS gating : PASS
7005 10:04:39.119551 RX DQ/DQS(RDDQC) : PASS
7006 10:04:39.123216 TX DQ/DQS : PASS
7007 10:04:39.126104 RX DATLAT : PASS
7008 10:04:39.126187 RX DQ/DQS(Engine): PASS
7009 10:04:39.130244 TX OE : NO K
7010 10:04:39.130327 All Pass.
7011 10:04:39.130394
7012 10:04:39.132947 CH 1, Rank 0
7013 10:04:39.133030 SW Impedance : PASS
7014 10:04:39.136131 DUTY Scan : NO K
7015 10:04:39.136215 ZQ Calibration : PASS
7016 10:04:39.139296 Jitter Meter : NO K
7017 10:04:39.142689 CBT Training : PASS
7018 10:04:39.142772 Write leveling : PASS
7019 10:04:39.145918 RX DQS gating : PASS
7020 10:04:39.149265 RX DQ/DQS(RDDQC) : PASS
7021 10:04:39.149355 TX DQ/DQS : PASS
7022 10:04:39.152746 RX DATLAT : PASS
7023 10:04:39.156207 RX DQ/DQS(Engine): PASS
7024 10:04:39.156289 TX OE : NO K
7025 10:04:39.159295 All Pass.
7026 10:04:39.159377
7027 10:04:39.159442 CH 1, Rank 1
7028 10:04:39.162524 SW Impedance : PASS
7029 10:04:39.162607 DUTY Scan : NO K
7030 10:04:39.166086 ZQ Calibration : PASS
7031 10:04:39.169123 Jitter Meter : NO K
7032 10:04:39.169205 CBT Training : PASS
7033 10:04:39.172548 Write leveling : NO K
7034 10:04:39.175980 RX DQS gating : PASS
7035 10:04:39.176062 RX DQ/DQS(RDDQC) : PASS
7036 10:04:39.179072 TX DQ/DQS : PASS
7037 10:04:39.182405 RX DATLAT : PASS
7038 10:04:39.182488 RX DQ/DQS(Engine): PASS
7039 10:04:39.185802 TX OE : NO K
7040 10:04:39.185885 All Pass.
7041 10:04:39.185960
7042 10:04:39.189291 DramC Write-DBI off
7043 10:04:39.193040 PER_BANK_REFRESH: Hybrid Mode
7044 10:04:39.193123 TX_TRACKING: ON
7045 10:04:39.202440 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7046 10:04:39.205938 [FAST_K] Save calibration result to emmc
7047 10:04:39.209181 dramc_set_vcore_voltage set vcore to 725000
7048 10:04:39.212580 Read voltage for 1600, 0
7049 10:04:39.212681 Vio18 = 0
7050 10:04:39.212805 Vcore = 725000
7051 10:04:39.215639 Vdram = 0
7052 10:04:39.215735 Vddq = 0
7053 10:04:39.215828 Vmddr = 0
7054 10:04:39.222482 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7055 10:04:39.225492 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7056 10:04:39.228914 MEM_TYPE=3, freq_sel=13
7057 10:04:39.232472 sv_algorithm_assistance_LP4_3733
7058 10:04:39.235335 ============ PULL DRAM RESETB DOWN ============
7059 10:04:39.239148 ========== PULL DRAM RESETB DOWN end =========
7060 10:04:39.245341 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7061 10:04:39.248516 ===================================
7062 10:04:39.248590 LPDDR4 DRAM CONFIGURATION
7063 10:04:39.251918 ===================================
7064 10:04:39.255723 EX_ROW_EN[0] = 0x0
7065 10:04:39.258873 EX_ROW_EN[1] = 0x0
7066 10:04:39.258947 LP4Y_EN = 0x0
7067 10:04:39.261911 WORK_FSP = 0x1
7068 10:04:39.261982 WL = 0x5
7069 10:04:39.265110 RL = 0x5
7070 10:04:39.265180 BL = 0x2
7071 10:04:39.268425 RPST = 0x0
7072 10:04:39.268494 RD_PRE = 0x0
7073 10:04:39.271699 WR_PRE = 0x1
7074 10:04:39.271798 WR_PST = 0x1
7075 10:04:39.275002 DBI_WR = 0x0
7076 10:04:39.275073 DBI_RD = 0x0
7077 10:04:39.278449 OTF = 0x1
7078 10:04:39.281517 ===================================
7079 10:04:39.285113 ===================================
7080 10:04:39.285196 ANA top config
7081 10:04:39.288239 ===================================
7082 10:04:39.291392 DLL_ASYNC_EN = 0
7083 10:04:39.295298 ALL_SLAVE_EN = 0
7084 10:04:39.298258 NEW_RANK_MODE = 1
7085 10:04:39.298342 DLL_IDLE_MODE = 1
7086 10:04:39.301645 LP45_APHY_COMB_EN = 1
7087 10:04:39.304894 TX_ODT_DIS = 0
7088 10:04:39.308032 NEW_8X_MODE = 1
7089 10:04:39.311474 ===================================
7090 10:04:39.314581 ===================================
7091 10:04:39.317777 data_rate = 3200
7092 10:04:39.321254 CKR = 1
7093 10:04:39.321427 DQ_P2S_RATIO = 8
7094 10:04:39.324799 ===================================
7095 10:04:39.327902 CA_P2S_RATIO = 8
7096 10:04:39.331382 DQ_CA_OPEN = 0
7097 10:04:39.334423 DQ_SEMI_OPEN = 0
7098 10:04:39.338143 CA_SEMI_OPEN = 0
7099 10:04:39.341992 CA_FULL_RATE = 0
7100 10:04:39.342202 DQ_CKDIV4_EN = 0
7101 10:04:39.344917 CA_CKDIV4_EN = 0
7102 10:04:39.347561 CA_PREDIV_EN = 0
7103 10:04:39.351185 PH8_DLY = 12
7104 10:04:39.354431 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7105 10:04:39.358056 DQ_AAMCK_DIV = 4
7106 10:04:39.361296 CA_AAMCK_DIV = 4
7107 10:04:39.361594 CA_ADMCK_DIV = 4
7108 10:04:39.364536 DQ_TRACK_CA_EN = 0
7109 10:04:39.367865 CA_PICK = 1600
7110 10:04:39.371213 CA_MCKIO = 1600
7111 10:04:39.374356 MCKIO_SEMI = 0
7112 10:04:39.377625 PLL_FREQ = 3068
7113 10:04:39.381366 DQ_UI_PI_RATIO = 32
7114 10:04:39.381948 CA_UI_PI_RATIO = 0
7115 10:04:39.384528 ===================================
7116 10:04:39.388012 ===================================
7117 10:04:39.390819 memory_type:LPDDR4
7118 10:04:39.394132 GP_NUM : 10
7119 10:04:39.394609 SRAM_EN : 1
7120 10:04:39.397641 MD32_EN : 0
7121 10:04:39.400935 ===================================
7122 10:04:39.403876 [ANA_INIT] >>>>>>>>>>>>>>
7123 10:04:39.407577 <<<<<< [CONFIGURE PHASE]: ANA_TX
7124 10:04:39.410794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7125 10:04:39.414434 ===================================
7126 10:04:39.415012 data_rate = 3200,PCW = 0X7600
7127 10:04:39.417446 ===================================
7128 10:04:39.420676 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7129 10:04:39.427438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7130 10:04:39.434343 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7131 10:04:39.437433 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7132 10:04:39.441103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7133 10:04:39.443828 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7134 10:04:39.447699 [ANA_INIT] flow start
7135 10:04:39.450653 [ANA_INIT] PLL >>>>>>>>
7136 10:04:39.451123 [ANA_INIT] PLL <<<<<<<<
7137 10:04:39.453659 [ANA_INIT] MIDPI >>>>>>>>
7138 10:04:39.457086 [ANA_INIT] MIDPI <<<<<<<<
7139 10:04:39.457558 [ANA_INIT] DLL >>>>>>>>
7140 10:04:39.460236 [ANA_INIT] DLL <<<<<<<<
7141 10:04:39.464347 [ANA_INIT] flow end
7142 10:04:39.467332 ============ LP4 DIFF to SE enter ============
7143 10:04:39.470377 ============ LP4 DIFF to SE exit ============
7144 10:04:39.474014 [ANA_INIT] <<<<<<<<<<<<<
7145 10:04:39.476864 [Flow] Enable top DCM control >>>>>
7146 10:04:39.480240 [Flow] Enable top DCM control <<<<<
7147 10:04:39.483644 Enable DLL master slave shuffle
7148 10:04:39.486570 ==============================================================
7149 10:04:39.490066 Gating Mode config
7150 10:04:39.496843 ==============================================================
7151 10:04:39.497332 Config description:
7152 10:04:39.506364 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7153 10:04:39.513232 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7154 10:04:39.519725 SELPH_MODE 0: By rank 1: By Phase
7155 10:04:39.523135 ==============================================================
7156 10:04:39.526190 GAT_TRACK_EN = 1
7157 10:04:39.529823 RX_GATING_MODE = 2
7158 10:04:39.532713 RX_GATING_TRACK_MODE = 2
7159 10:04:39.535861 SELPH_MODE = 1
7160 10:04:39.539170 PICG_EARLY_EN = 1
7161 10:04:39.543004 VALID_LAT_VALUE = 1
7162 10:04:39.545870 ==============================================================
7163 10:04:39.549431 Enter into Gating configuration >>>>
7164 10:04:39.552713 Exit from Gating configuration <<<<
7165 10:04:39.556119 Enter into DVFS_PRE_config >>>>>
7166 10:04:39.569463 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7167 10:04:39.572412 Exit from DVFS_PRE_config <<<<<
7168 10:04:39.575777 Enter into PICG configuration >>>>
7169 10:04:39.575873 Exit from PICG configuration <<<<
7170 10:04:39.579316 [RX_INPUT] configuration >>>>>
7171 10:04:39.582153 [RX_INPUT] configuration <<<<<
7172 10:04:39.588793 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7173 10:04:39.592127 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7174 10:04:39.598824 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7175 10:04:39.605401 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7176 10:04:39.611831 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7177 10:04:39.618390 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7178 10:04:39.621693 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7179 10:04:39.625242 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7180 10:04:39.631482 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7181 10:04:39.635295 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7182 10:04:39.638358 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7183 10:04:39.641841 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7184 10:04:39.644945 ===================================
7185 10:04:39.648616 LPDDR4 DRAM CONFIGURATION
7186 10:04:39.651735 ===================================
7187 10:04:39.654998 EX_ROW_EN[0] = 0x0
7188 10:04:39.655337 EX_ROW_EN[1] = 0x0
7189 10:04:39.658381 LP4Y_EN = 0x0
7190 10:04:39.658775 WORK_FSP = 0x1
7191 10:04:39.662448 WL = 0x5
7192 10:04:39.662931 RL = 0x5
7193 10:04:39.665314 BL = 0x2
7194 10:04:39.665823 RPST = 0x0
7195 10:04:39.668493 RD_PRE = 0x0
7196 10:04:39.671678 WR_PRE = 0x1
7197 10:04:39.672247 WR_PST = 0x1
7198 10:04:39.674963 DBI_WR = 0x0
7199 10:04:39.675528 DBI_RD = 0x0
7200 10:04:39.678312 OTF = 0x1
7201 10:04:39.681553 ===================================
7202 10:04:39.685366 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7203 10:04:39.688318 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7204 10:04:39.691270 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7205 10:04:39.694607 ===================================
7206 10:04:39.698081 LPDDR4 DRAM CONFIGURATION
7207 10:04:39.701516 ===================================
7208 10:04:39.704546 EX_ROW_EN[0] = 0x10
7209 10:04:39.705050 EX_ROW_EN[1] = 0x0
7210 10:04:39.707995 LP4Y_EN = 0x0
7211 10:04:39.708457 WORK_FSP = 0x1
7212 10:04:39.711561 WL = 0x5
7213 10:04:39.712144 RL = 0x5
7214 10:04:39.714779 BL = 0x2
7215 10:04:39.715393 RPST = 0x0
7216 10:04:39.718158 RD_PRE = 0x0
7217 10:04:39.721341 WR_PRE = 0x1
7218 10:04:39.721843 WR_PST = 0x1
7219 10:04:39.724505 DBI_WR = 0x0
7220 10:04:39.725009 DBI_RD = 0x0
7221 10:04:39.727760 OTF = 0x1
7222 10:04:39.731326 ===================================
7223 10:04:39.734018 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7224 10:04:39.737923 ==
7225 10:04:39.741182 Dram Type= 6, Freq= 0, CH_0, rank 0
7226 10:04:39.744241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7227 10:04:39.744669 ==
7228 10:04:39.747209 [Duty_Offset_Calibration]
7229 10:04:39.747634 B0:2 B1:0 CA:1
7230 10:04:39.747970
7231 10:04:39.750697 [DutyScan_Calibration_Flow] k_type=0
7232 10:04:39.759799
7233 10:04:39.760219 ==CLK 0==
7234 10:04:39.763231 Final CLK duty delay cell = -4
7235 10:04:39.766301 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7236 10:04:39.769720 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7237 10:04:39.773316 [-4] AVG Duty = 4906%(X100)
7238 10:04:39.773736
7239 10:04:39.776370 CH0 CLK Duty spec in!! Max-Min= 187%
7240 10:04:39.779858 [DutyScan_Calibration_Flow] ====Done====
7241 10:04:39.780410
7242 10:04:39.783671 [DutyScan_Calibration_Flow] k_type=1
7243 10:04:39.799558
7244 10:04:39.800059 ==DQS 0 ==
7245 10:04:39.802713 Final DQS duty delay cell = 0
7246 10:04:39.806233 [0] MAX Duty = 5218%(X100), DQS PI = 32
7247 10:04:39.809580 [0] MIN Duty = 4969%(X100), DQS PI = 0
7248 10:04:39.810114 [0] AVG Duty = 5093%(X100)
7249 10:04:39.812825
7250 10:04:39.813302 ==DQS 1 ==
7251 10:04:39.816103 Final DQS duty delay cell = -4
7252 10:04:39.819329 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7253 10:04:39.822706 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7254 10:04:39.826124 [-4] AVG Duty = 5000%(X100)
7255 10:04:39.826725
7256 10:04:39.829145 CH0 DQS 0 Duty spec in!! Max-Min= 249%
7257 10:04:39.829570
7258 10:04:39.832582 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7259 10:04:39.836005 [DutyScan_Calibration_Flow] ====Done====
7260 10:04:39.836428
7261 10:04:39.839129 [DutyScan_Calibration_Flow] k_type=3
7262 10:04:39.856142
7263 10:04:39.856442 ==DQM 0 ==
7264 10:04:39.859166 Final DQM duty delay cell = 0
7265 10:04:39.862635 [0] MAX Duty = 5124%(X100), DQS PI = 26
7266 10:04:39.865928 [0] MIN Duty = 4813%(X100), DQS PI = 50
7267 10:04:39.869437 [0] AVG Duty = 4968%(X100)
7268 10:04:39.869709
7269 10:04:39.869940 ==DQM 1 ==
7270 10:04:39.872666 Final DQM duty delay cell = -4
7271 10:04:39.875939 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7272 10:04:39.879113 [-4] MIN Duty = 4751%(X100), DQS PI = 10
7273 10:04:39.882305 [-4] AVG Duty = 4875%(X100)
7274 10:04:39.882711
7275 10:04:39.885745 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7276 10:04:39.886166
7277 10:04:39.889767 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7278 10:04:39.892729 [DutyScan_Calibration_Flow] ====Done====
7279 10:04:39.893172
7280 10:04:39.895952 [DutyScan_Calibration_Flow] k_type=2
7281 10:04:39.913677
7282 10:04:39.913976 ==DQ 0 ==
7283 10:04:39.917039 Final DQ duty delay cell = 0
7284 10:04:39.920381 [0] MAX Duty = 5156%(X100), DQS PI = 36
7285 10:04:39.923814 [0] MIN Duty = 5000%(X100), DQS PI = 0
7286 10:04:39.924220 [0] AVG Duty = 5078%(X100)
7287 10:04:39.926595
7288 10:04:39.926998 ==DQ 1 ==
7289 10:04:39.929866 Final DQ duty delay cell = 0
7290 10:04:39.933502 [0] MAX Duty = 4969%(X100), DQS PI = 42
7291 10:04:39.936828 [0] MIN Duty = 4875%(X100), DQS PI = 10
7292 10:04:39.937230 [0] AVG Duty = 4922%(X100)
7293 10:04:39.939810
7294 10:04:39.943439 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7295 10:04:39.943734
7296 10:04:39.946472 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7297 10:04:39.949921 [DutyScan_Calibration_Flow] ====Done====
7298 10:04:39.950212 ==
7299 10:04:39.953074 Dram Type= 6, Freq= 0, CH_1, rank 0
7300 10:04:39.956697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7301 10:04:39.957026 ==
7302 10:04:39.960078 [Duty_Offset_Calibration]
7303 10:04:39.960370 B0:0 B1:-1 CA:2
7304 10:04:39.960601
7305 10:04:39.963345 [DutyScan_Calibration_Flow] k_type=0
7306 10:04:39.973791
7307 10:04:39.974084 ==CLK 0==
7308 10:04:39.977333 Final CLK duty delay cell = 0
7309 10:04:39.980549 [0] MAX Duty = 5156%(X100), DQS PI = 10
7310 10:04:39.983605 [0] MIN Duty = 4906%(X100), DQS PI = 46
7311 10:04:39.983898 [0] AVG Duty = 5031%(X100)
7312 10:04:39.987319
7313 10:04:39.990694 CH1 CLK Duty spec in!! Max-Min= 250%
7314 10:04:39.993645 [DutyScan_Calibration_Flow] ====Done====
7315 10:04:39.994100
7316 10:04:39.996802 [DutyScan_Calibration_Flow] k_type=1
7317 10:04:40.013655
7318 10:04:40.014215 ==DQS 0 ==
7319 10:04:40.017170 Final DQS duty delay cell = 0
7320 10:04:40.020873 [0] MAX Duty = 5124%(X100), DQS PI = 26
7321 10:04:40.024074 [0] MIN Duty = 4969%(X100), DQS PI = 2
7322 10:04:40.026818 [0] AVG Duty = 5046%(X100)
7323 10:04:40.027274
7324 10:04:40.027629 ==DQS 1 ==
7325 10:04:40.030844 Final DQS duty delay cell = 0
7326 10:04:40.033626 [0] MAX Duty = 5187%(X100), DQS PI = 0
7327 10:04:40.036859 [0] MIN Duty = 4844%(X100), DQS PI = 32
7328 10:04:40.040107 [0] AVG Duty = 5015%(X100)
7329 10:04:40.040563
7330 10:04:40.043923 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7331 10:04:40.044378
7332 10:04:40.046437 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7333 10:04:40.049949 [DutyScan_Calibration_Flow] ====Done====
7334 10:04:40.050402
7335 10:04:40.053358 [DutyScan_Calibration_Flow] k_type=3
7336 10:04:40.071472
7337 10:04:40.071928 ==DQM 0 ==
7338 10:04:40.074519 Final DQM duty delay cell = 4
7339 10:04:40.077772 [4] MAX Duty = 5125%(X100), DQS PI = 22
7340 10:04:40.081286 [4] MIN Duty = 5000%(X100), DQS PI = 30
7341 10:04:40.084523 [4] AVG Duty = 5062%(X100)
7342 10:04:40.085112
7343 10:04:40.085493 ==DQM 1 ==
7344 10:04:40.087551 Final DQM duty delay cell = 0
7345 10:04:40.091544 [0] MAX Duty = 5281%(X100), DQS PI = 58
7346 10:04:40.094809 [0] MIN Duty = 4876%(X100), DQS PI = 34
7347 10:04:40.097783 [0] AVG Duty = 5078%(X100)
7348 10:04:40.098412
7349 10:04:40.100932 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7350 10:04:40.101570
7351 10:04:40.104258 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7352 10:04:40.107577 [DutyScan_Calibration_Flow] ====Done====
7353 10:04:40.108201
7354 10:04:40.110883 [DutyScan_Calibration_Flow] k_type=2
7355 10:04:40.128007
7356 10:04:40.128496 ==DQ 0 ==
7357 10:04:40.131279 Final DQ duty delay cell = 0
7358 10:04:40.134782 [0] MAX Duty = 5093%(X100), DQS PI = 22
7359 10:04:40.137941 [0] MIN Duty = 4969%(X100), DQS PI = 0
7360 10:04:40.138621 [0] AVG Duty = 5031%(X100)
7361 10:04:40.141837
7362 10:04:40.142471 ==DQ 1 ==
7363 10:04:40.144437 Final DQ duty delay cell = 0
7364 10:04:40.147863 [0] MAX Duty = 5062%(X100), DQS PI = 2
7365 10:04:40.151138 [0] MIN Duty = 4813%(X100), DQS PI = 34
7366 10:04:40.151794 [0] AVG Duty = 4937%(X100)
7367 10:04:40.154692
7368 10:04:40.157891 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7369 10:04:40.158330
7370 10:04:40.161086 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7371 10:04:40.164342 [DutyScan_Calibration_Flow] ====Done====
7372 10:04:40.167485 nWR fixed to 30
7373 10:04:40.167911 [ModeRegInit_LP4] CH0 RK0
7374 10:04:40.170536 [ModeRegInit_LP4] CH0 RK1
7375 10:04:40.174001 [ModeRegInit_LP4] CH1 RK0
7376 10:04:40.177291 [ModeRegInit_LP4] CH1 RK1
7377 10:04:40.177373 match AC timing 5
7378 10:04:40.183967 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7379 10:04:40.187397 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7380 10:04:40.190895 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7381 10:04:40.197196 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7382 10:04:40.200466 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7383 10:04:40.200569 [MiockJmeterHQA]
7384 10:04:40.200650
7385 10:04:40.203672 [DramcMiockJmeter] u1RxGatingPI = 0
7386 10:04:40.207156 0 : 4252, 4026
7387 10:04:40.207271 4 : 4253, 4026
7388 10:04:40.210601 8 : 4252, 4027
7389 10:04:40.210726 12 : 4253, 4026
7390 10:04:40.213782 16 : 4363, 4137
7391 10:04:40.213907 20 : 4252, 4027
7392 10:04:40.214005 24 : 4250, 4027
7393 10:04:40.217101 28 : 4253, 4026
7394 10:04:40.217239 32 : 4255, 4030
7395 10:04:40.219990 36 : 4362, 4137
7396 10:04:40.220145 40 : 4252, 4027
7397 10:04:40.223440 44 : 4253, 4027
7398 10:04:40.223595 48 : 4253, 4026
7399 10:04:40.226466 52 : 4255, 4029
7400 10:04:40.226642 56 : 4252, 4027
7401 10:04:40.226783 60 : 4361, 4137
7402 10:04:40.230062 64 : 4360, 4138
7403 10:04:40.230281 68 : 4250, 4026
7404 10:04:40.233482 72 : 4255, 4029
7405 10:04:40.233687 76 : 4249, 4027
7406 10:04:40.237107 80 : 4250, 4026
7407 10:04:40.237352 84 : 4252, 4030
7408 10:04:40.240186 88 : 4360, 3664
7409 10:04:40.240489 92 : 4250, 0
7410 10:04:40.240736 96 : 4250, 0
7411 10:04:40.243620 100 : 4250, 0
7412 10:04:40.243922 104 : 4360, 0
7413 10:04:40.244217 108 : 4250, 0
7414 10:04:40.246966 112 : 4250, 0
7415 10:04:40.247359 116 : 4249, 0
7416 10:04:40.250323 120 : 4252, 0
7417 10:04:40.250751 124 : 4250, 0
7418 10:04:40.251093 128 : 4249, 0
7419 10:04:40.253457 132 : 4253, 0
7420 10:04:40.253918 136 : 4361, 0
7421 10:04:40.256868 140 : 4250, 0
7422 10:04:40.257295 144 : 4361, 0
7423 10:04:40.257638 148 : 4250, 0
7424 10:04:40.260270 152 : 4250, 0
7425 10:04:40.260698 156 : 4249, 0
7426 10:04:40.261089 160 : 4250, 0
7427 10:04:40.263378 164 : 4250, 0
7428 10:04:40.263804 168 : 4249, 0
7429 10:04:40.267139 172 : 4252, 0
7430 10:04:40.267567 176 : 4250, 0
7431 10:04:40.267910 180 : 4249, 0
7432 10:04:40.270119 184 : 4252, 0
7433 10:04:40.270548 188 : 4250, 0
7434 10:04:40.273457 192 : 4360, 0
7435 10:04:40.273886 196 : 4250, 0
7436 10:04:40.274227 200 : 4250, 7
7437 10:04:40.276574 204 : 4250, 2517
7438 10:04:40.277058 208 : 4361, 4137
7439 10:04:40.280125 212 : 4250, 4027
7440 10:04:40.280552 216 : 4360, 4138
7441 10:04:40.283146 220 : 4361, 4137
7442 10:04:40.283573 224 : 4250, 4026
7443 10:04:40.286412 228 : 4250, 4027
7444 10:04:40.286840 232 : 4363, 4140
7445 10:04:40.289971 236 : 4250, 4027
7446 10:04:40.290399 240 : 4250, 4026
7447 10:04:40.293091 244 : 4250, 4027
7448 10:04:40.293517 248 : 4250, 4027
7449 10:04:40.293861 252 : 4250, 4027
7450 10:04:40.296724 256 : 4250, 4026
7451 10:04:40.297199 260 : 4361, 4137
7452 10:04:40.299811 264 : 4250, 4027
7453 10:04:40.300238 268 : 4249, 4027
7454 10:04:40.303266 272 : 4361, 4137
7455 10:04:40.303696 276 : 4250, 4026
7456 10:04:40.306886 280 : 4250, 4027
7457 10:04:40.307312 284 : 4363, 4140
7458 10:04:40.309901 288 : 4250, 4027
7459 10:04:40.310328 292 : 4250, 4026
7460 10:04:40.312849 296 : 4250, 4027
7461 10:04:40.313280 300 : 4252, 4030
7462 10:04:40.316475 304 : 4249, 4027
7463 10:04:40.317003 308 : 4250, 4026
7464 10:04:40.319708 312 : 4361, 4074
7465 10:04:40.320136 316 : 4250, 1860
7466 10:04:40.320475
7467 10:04:40.322832 MIOCK jitter meter ch=0
7468 10:04:40.323253
7469 10:04:40.325985 1T = (316-92) = 224 dly cells
7470 10:04:40.329440 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7471 10:04:40.329866 ==
7472 10:04:40.332915 Dram Type= 6, Freq= 0, CH_0, rank 0
7473 10:04:40.339554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7474 10:04:40.339979 ==
7475 10:04:40.343126 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7476 10:04:40.349413 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7477 10:04:40.352522 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7478 10:04:40.359440 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7479 10:04:40.366785 [CA 0] Center 42 (12~73) winsize 62
7480 10:04:40.370048 [CA 1] Center 43 (13~73) winsize 61
7481 10:04:40.373384 [CA 2] Center 38 (8~68) winsize 61
7482 10:04:40.376661 [CA 3] Center 37 (8~67) winsize 60
7483 10:04:40.379799 [CA 4] Center 36 (6~66) winsize 61
7484 10:04:40.383199 [CA 5] Center 35 (5~65) winsize 61
7485 10:04:40.383301
7486 10:04:40.386561 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7487 10:04:40.386664
7488 10:04:40.390078 [CATrainingPosCal] consider 1 rank data
7489 10:04:40.392945 u2DelayCellTimex100 = 290/100 ps
7490 10:04:40.396473 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7491 10:04:40.402908 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7492 10:04:40.406162 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7493 10:04:40.409755 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7494 10:04:40.412683 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7495 10:04:40.416136 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7496 10:04:40.416243
7497 10:04:40.419523 CA PerBit enable=1, Macro0, CA PI delay=35
7498 10:04:40.419636
7499 10:04:40.422872 [CBTSetCACLKResult] CA Dly = 35
7500 10:04:40.426113 CS Dly: 9 (0~40)
7501 10:04:40.429513 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7502 10:04:40.432665 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7503 10:04:40.432778 ==
7504 10:04:40.435806 Dram Type= 6, Freq= 0, CH_0, rank 1
7505 10:04:40.442780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7506 10:04:40.442888 ==
7507 10:04:40.445693 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7508 10:04:40.452367 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7509 10:04:40.455760 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7510 10:04:40.462058 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7511 10:04:40.469742 [CA 0] Center 43 (13~74) winsize 62
7512 10:04:40.473087 [CA 1] Center 43 (13~73) winsize 61
7513 10:04:40.476321 [CA 2] Center 38 (9~68) winsize 60
7514 10:04:40.479881 [CA 3] Center 38 (9~68) winsize 60
7515 10:04:40.483132 [CA 4] Center 37 (7~67) winsize 61
7516 10:04:40.486721 [CA 5] Center 36 (6~66) winsize 61
7517 10:04:40.486820
7518 10:04:40.490062 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7519 10:04:40.490149
7520 10:04:40.493177 [CATrainingPosCal] consider 2 rank data
7521 10:04:40.496426 u2DelayCellTimex100 = 290/100 ps
7522 10:04:40.499720 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7523 10:04:40.506323 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7524 10:04:40.510022 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7525 10:04:40.513207 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7526 10:04:40.516531 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7527 10:04:40.519671 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7528 10:04:40.519753
7529 10:04:40.523034 CA PerBit enable=1, Macro0, CA PI delay=35
7530 10:04:40.523116
7531 10:04:40.526201 [CBTSetCACLKResult] CA Dly = 35
7532 10:04:40.529680 CS Dly: 10 (0~43)
7533 10:04:40.533046 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7534 10:04:40.536595 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7535 10:04:40.536679
7536 10:04:40.539475 ----->DramcWriteLeveling(PI) begin...
7537 10:04:40.539559 ==
7538 10:04:40.542905 Dram Type= 6, Freq= 0, CH_0, rank 0
7539 10:04:40.549408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7540 10:04:40.549491 ==
7541 10:04:40.552613 Write leveling (Byte 0): 35 => 35
7542 10:04:40.555822 Write leveling (Byte 1): 32 => 32
7543 10:04:40.555904 DramcWriteLeveling(PI) end<-----
7544 10:04:40.559039
7545 10:04:40.559122 ==
7546 10:04:40.562613 Dram Type= 6, Freq= 0, CH_0, rank 0
7547 10:04:40.565967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7548 10:04:40.566050 ==
7549 10:04:40.569130 [Gating] SW mode calibration
7550 10:04:40.575544 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7551 10:04:40.579073 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7552 10:04:40.585695 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7553 10:04:40.589099 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 10:04:40.592042 1 4 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
7555 10:04:40.598829 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7556 10:04:40.601947 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7557 10:04:40.605401 1 4 20 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7558 10:04:40.612204 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 10:04:40.615382 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 10:04:40.618677 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 10:04:40.625053 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7562 10:04:40.628566 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7563 10:04:40.631763 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7564 10:04:40.638390 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7565 10:04:40.642047 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7566 10:04:40.645143 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 10:04:40.651698 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 10:04:40.654868 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 10:04:40.658268 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7570 10:04:40.664846 1 6 8 | B1->B0 | 2323 4141 | 0 1 | (0 0) (0 0)
7571 10:04:40.668321 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7572 10:04:40.671378 1 6 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
7573 10:04:40.678634 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7574 10:04:40.681266 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 10:04:40.684695 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 10:04:40.691230 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 10:04:40.694944 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 10:04:40.698079 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7579 10:04:40.704635 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7580 10:04:40.707867 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7581 10:04:40.711042 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7582 10:04:40.717880 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 10:04:40.720843 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 10:04:40.724440 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 10:04:40.730804 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 10:04:40.734006 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 10:04:40.737466 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 10:04:40.744177 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 10:04:40.747283 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 10:04:40.750640 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 10:04:40.757307 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 10:04:40.760451 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 10:04:40.763772 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 10:04:40.770323 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7595 10:04:40.773712 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7596 10:04:40.777084 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7597 10:04:40.780540 Total UI for P1: 0, mck2ui 16
7598 10:04:40.783566 best dqsien dly found for B0: ( 1, 9, 10)
7599 10:04:40.790159 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 10:04:40.790244 Total UI for P1: 0, mck2ui 16
7601 10:04:40.796538 best dqsien dly found for B1: ( 1, 9, 16)
7602 10:04:40.799990 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7603 10:04:40.803270 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7604 10:04:40.803353
7605 10:04:40.806528 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7606 10:04:40.809907 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7607 10:04:40.813253 [Gating] SW calibration Done
7608 10:04:40.813335 ==
7609 10:04:40.816511 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 10:04:40.819835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 10:04:40.819918 ==
7612 10:04:40.823478 RX Vref Scan: 0
7613 10:04:40.823561
7614 10:04:40.826462 RX Vref 0 -> 0, step: 1
7615 10:04:40.826544
7616 10:04:40.826609 RX Delay 0 -> 252, step: 8
7617 10:04:40.829793 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7618 10:04:40.836444 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7619 10:04:40.839640 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7620 10:04:40.843091 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7621 10:04:40.846519 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7622 10:04:40.849800 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7623 10:04:40.856186 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7624 10:04:40.859518 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7625 10:04:40.862917 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7626 10:04:40.866184 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7627 10:04:40.869474 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7628 10:04:40.876622 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7629 10:04:40.879740 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7630 10:04:40.882813 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7631 10:04:40.886020 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7632 10:04:40.892554 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7633 10:04:40.892637 ==
7634 10:04:40.895924 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 10:04:40.899414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 10:04:40.899497 ==
7637 10:04:40.899563 DQS Delay:
7638 10:04:40.902337 DQS0 = 0, DQS1 = 0
7639 10:04:40.902420 DQM Delay:
7640 10:04:40.905946 DQM0 = 137, DQM1 = 126
7641 10:04:40.906029 DQ Delay:
7642 10:04:40.909222 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7643 10:04:40.912426 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7644 10:04:40.915887 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7645 10:04:40.919274 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7646 10:04:40.919357
7647 10:04:40.919422
7648 10:04:40.922453 ==
7649 10:04:40.925769 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 10:04:40.928884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 10:04:40.928967 ==
7652 10:04:40.929032
7653 10:04:40.929092
7654 10:04:40.932404 TX Vref Scan disable
7655 10:04:40.932487 == TX Byte 0 ==
7656 10:04:40.935573 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7657 10:04:40.942319 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7658 10:04:40.942401 == TX Byte 1 ==
7659 10:04:40.945542 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7660 10:04:40.952448 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7661 10:04:40.952531 ==
7662 10:04:40.955493 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 10:04:40.958914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 10:04:40.958997 ==
7665 10:04:40.971760
7666 10:04:40.975110 TX Vref early break, caculate TX vref
7667 10:04:40.978582 TX Vref=16, minBit 12, minWin=22, winSum=381
7668 10:04:40.981825 TX Vref=18, minBit 6, minWin=23, winSum=388
7669 10:04:40.985100 TX Vref=20, minBit 4, minWin=24, winSum=396
7670 10:04:40.988283 TX Vref=22, minBit 7, minWin=24, winSum=409
7671 10:04:40.991935 TX Vref=24, minBit 6, minWin=25, winSum=416
7672 10:04:40.998580 TX Vref=26, minBit 12, minWin=25, winSum=423
7673 10:04:41.001726 TX Vref=28, minBit 0, minWin=26, winSum=428
7674 10:04:41.004739 TX Vref=30, minBit 2, minWin=25, winSum=418
7675 10:04:41.008236 TX Vref=32, minBit 1, minWin=25, winSum=412
7676 10:04:41.011637 TX Vref=34, minBit 2, minWin=24, winSum=401
7677 10:04:41.018168 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
7678 10:04:41.018251
7679 10:04:41.021734 Final TX Range 0 Vref 28
7680 10:04:41.021823
7681 10:04:41.021894 ==
7682 10:04:41.024828 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 10:04:41.028448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 10:04:41.028906 ==
7685 10:04:41.029254
7686 10:04:41.029573
7687 10:04:41.031630 TX Vref Scan disable
7688 10:04:41.038189 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7689 10:04:41.038613 == TX Byte 0 ==
7690 10:04:41.041536 u2DelayCellOfst[0]=13 cells (4 PI)
7691 10:04:41.044853 u2DelayCellOfst[1]=16 cells (5 PI)
7692 10:04:41.047817 u2DelayCellOfst[2]=10 cells (3 PI)
7693 10:04:41.051059 u2DelayCellOfst[3]=13 cells (4 PI)
7694 10:04:41.054700 u2DelayCellOfst[4]=6 cells (2 PI)
7695 10:04:41.058030 u2DelayCellOfst[5]=0 cells (0 PI)
7696 10:04:41.061703 u2DelayCellOfst[6]=16 cells (5 PI)
7697 10:04:41.064817 u2DelayCellOfst[7]=16 cells (5 PI)
7698 10:04:41.068167 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7699 10:04:41.071525 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7700 10:04:41.074403 == TX Byte 1 ==
7701 10:04:41.077845 u2DelayCellOfst[8]=0 cells (0 PI)
7702 10:04:41.081002 u2DelayCellOfst[9]=0 cells (0 PI)
7703 10:04:41.084617 u2DelayCellOfst[10]=6 cells (2 PI)
7704 10:04:41.087639 u2DelayCellOfst[11]=3 cells (1 PI)
7705 10:04:41.088112 u2DelayCellOfst[12]=13 cells (4 PI)
7706 10:04:41.091502 u2DelayCellOfst[13]=10 cells (3 PI)
7707 10:04:41.094503 u2DelayCellOfst[14]=13 cells (4 PI)
7708 10:04:41.097822 u2DelayCellOfst[15]=10 cells (3 PI)
7709 10:04:41.104259 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7710 10:04:41.108017 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7711 10:04:41.108584 DramC Write-DBI on
7712 10:04:41.111518 ==
7713 10:04:41.114623 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 10:04:41.117895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 10:04:41.118467 ==
7716 10:04:41.118838
7717 10:04:41.119178
7718 10:04:41.120489 TX Vref Scan disable
7719 10:04:41.121004 == TX Byte 0 ==
7720 10:04:41.127274 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7721 10:04:41.127831 == TX Byte 1 ==
7722 10:04:41.130895 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7723 10:04:41.134275 DramC Write-DBI off
7724 10:04:41.134738
7725 10:04:41.135113 [DATLAT]
7726 10:04:41.137651 Freq=1600, CH0 RK0
7727 10:04:41.138214
7728 10:04:41.138584 DATLAT Default: 0xf
7729 10:04:41.140708 0, 0xFFFF, sum = 0
7730 10:04:41.141210 1, 0xFFFF, sum = 0
7731 10:04:41.144199 2, 0xFFFF, sum = 0
7732 10:04:41.144800 3, 0xFFFF, sum = 0
7733 10:04:41.147193 4, 0xFFFF, sum = 0
7734 10:04:41.147668 5, 0xFFFF, sum = 0
7735 10:04:41.150307 6, 0xFFFF, sum = 0
7736 10:04:41.154288 7, 0xFFFF, sum = 0
7737 10:04:41.154857 8, 0xFFFF, sum = 0
7738 10:04:41.157121 9, 0xFFFF, sum = 0
7739 10:04:41.157695 10, 0xFFFF, sum = 0
7740 10:04:41.160295 11, 0xFFFF, sum = 0
7741 10:04:41.160901 12, 0xFFFF, sum = 0
7742 10:04:41.163428 13, 0xFFFF, sum = 0
7743 10:04:41.163908 14, 0x0, sum = 1
7744 10:04:41.167531 15, 0x0, sum = 2
7745 10:04:41.168004 16, 0x0, sum = 3
7746 10:04:41.170347 17, 0x0, sum = 4
7747 10:04:41.170942 best_step = 15
7748 10:04:41.171445
7749 10:04:41.171804 ==
7750 10:04:41.173642 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 10:04:41.176920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 10:04:41.177392 ==
7753 10:04:41.180377 RX Vref Scan: 1
7754 10:04:41.181100
7755 10:04:41.183801 Set Vref Range= 24 -> 127
7756 10:04:41.184418
7757 10:04:41.185014 RX Vref 24 -> 127, step: 1
7758 10:04:41.186845
7759 10:04:41.187482 RX Delay 19 -> 252, step: 4
7760 10:04:41.188027
7761 10:04:41.190200 Set Vref, RX VrefLevel [Byte0]: 24
7762 10:04:41.193206 [Byte1]: 24
7763 10:04:41.197019
7764 10:04:41.197489 Set Vref, RX VrefLevel [Byte0]: 25
7765 10:04:41.200327 [Byte1]: 25
7766 10:04:41.204577
7767 10:04:41.205189 Set Vref, RX VrefLevel [Byte0]: 26
7768 10:04:41.207703 [Byte1]: 26
7769 10:04:41.211794
7770 10:04:41.211883 Set Vref, RX VrefLevel [Byte0]: 27
7771 10:04:41.215348 [Byte1]: 27
7772 10:04:41.219312
7773 10:04:41.222611 Set Vref, RX VrefLevel [Byte0]: 28
7774 10:04:41.225907 [Byte1]: 28
7775 10:04:41.226007
7776 10:04:41.228901 Set Vref, RX VrefLevel [Byte0]: 29
7777 10:04:41.232239 [Byte1]: 29
7778 10:04:41.232323
7779 10:04:41.236106 Set Vref, RX VrefLevel [Byte0]: 30
7780 10:04:41.239417 [Byte1]: 30
7781 10:04:41.239582
7782 10:04:41.242886 Set Vref, RX VrefLevel [Byte0]: 31
7783 10:04:41.245806 [Byte1]: 31
7784 10:04:41.250023
7785 10:04:41.250216 Set Vref, RX VrefLevel [Byte0]: 32
7786 10:04:41.253251 [Byte1]: 32
7787 10:04:41.257551
7788 10:04:41.257737 Set Vref, RX VrefLevel [Byte0]: 33
7789 10:04:41.260659 [Byte1]: 33
7790 10:04:41.265395
7791 10:04:41.265600 Set Vref, RX VrefLevel [Byte0]: 34
7792 10:04:41.268546 [Byte1]: 34
7793 10:04:41.272328
7794 10:04:41.272543 Set Vref, RX VrefLevel [Byte0]: 35
7795 10:04:41.275581 [Byte1]: 35
7796 10:04:41.280041
7797 10:04:41.280214 Set Vref, RX VrefLevel [Byte0]: 36
7798 10:04:41.283532 [Byte1]: 36
7799 10:04:41.287517
7800 10:04:41.287725 Set Vref, RX VrefLevel [Byte0]: 37
7801 10:04:41.291487 [Byte1]: 37
7802 10:04:41.295332
7803 10:04:41.295747 Set Vref, RX VrefLevel [Byte0]: 38
7804 10:04:41.298645 [Byte1]: 38
7805 10:04:41.303348
7806 10:04:41.303753 Set Vref, RX VrefLevel [Byte0]: 39
7807 10:04:41.306597 [Byte1]: 39
7808 10:04:41.310668
7809 10:04:41.311234 Set Vref, RX VrefLevel [Byte0]: 40
7810 10:04:41.313942 [Byte1]: 40
7811 10:04:41.317872
7812 10:04:41.321372 Set Vref, RX VrefLevel [Byte0]: 41
7813 10:04:41.324643 [Byte1]: 41
7814 10:04:41.325275
7815 10:04:41.327991 Set Vref, RX VrefLevel [Byte0]: 42
7816 10:04:41.331782 [Byte1]: 42
7817 10:04:41.332247
7818 10:04:41.334492 Set Vref, RX VrefLevel [Byte0]: 43
7819 10:04:41.338468 [Byte1]: 43
7820 10:04:41.339035
7821 10:04:41.341485 Set Vref, RX VrefLevel [Byte0]: 44
7822 10:04:41.345174 [Byte1]: 44
7823 10:04:41.348534
7824 10:04:41.349139 Set Vref, RX VrefLevel [Byte0]: 45
7825 10:04:41.351858 [Byte1]: 45
7826 10:04:41.356022
7827 10:04:41.356481 Set Vref, RX VrefLevel [Byte0]: 46
7828 10:04:41.359640 [Byte1]: 46
7829 10:04:41.364242
7830 10:04:41.364845 Set Vref, RX VrefLevel [Byte0]: 47
7831 10:04:41.367223 [Byte1]: 47
7832 10:04:41.371478
7833 10:04:41.372043 Set Vref, RX VrefLevel [Byte0]: 48
7834 10:04:41.374865 [Byte1]: 48
7835 10:04:41.379215
7836 10:04:41.379770 Set Vref, RX VrefLevel [Byte0]: 49
7837 10:04:41.382520 [Byte1]: 49
7838 10:04:41.386327
7839 10:04:41.386789 Set Vref, RX VrefLevel [Byte0]: 50
7840 10:04:41.389919 [Byte1]: 50
7841 10:04:41.394295
7842 10:04:41.394756 Set Vref, RX VrefLevel [Byte0]: 51
7843 10:04:41.397212 [Byte1]: 51
7844 10:04:41.401668
7845 10:04:41.402270 Set Vref, RX VrefLevel [Byte0]: 52
7846 10:04:41.404738 [Byte1]: 52
7847 10:04:41.409339
7848 10:04:41.409919 Set Vref, RX VrefLevel [Byte0]: 53
7849 10:04:41.412581 [Byte1]: 53
7850 10:04:41.416620
7851 10:04:41.417151 Set Vref, RX VrefLevel [Byte0]: 54
7852 10:04:41.420307 [Byte1]: 54
7853 10:04:41.425055
7854 10:04:41.425615 Set Vref, RX VrefLevel [Byte0]: 55
7855 10:04:41.427484 [Byte1]: 55
7856 10:04:41.431983
7857 10:04:41.432548 Set Vref, RX VrefLevel [Byte0]: 56
7858 10:04:41.435421 [Byte1]: 56
7859 10:04:41.439534
7860 10:04:41.440095 Set Vref, RX VrefLevel [Byte0]: 57
7861 10:04:41.443212 [Byte1]: 57
7862 10:04:41.447245
7863 10:04:41.447807 Set Vref, RX VrefLevel [Byte0]: 58
7864 10:04:41.450691 [Byte1]: 58
7865 10:04:41.454736
7866 10:04:41.455299 Set Vref, RX VrefLevel [Byte0]: 59
7867 10:04:41.458100 [Byte1]: 59
7868 10:04:41.462339
7869 10:04:41.462992 Set Vref, RX VrefLevel [Byte0]: 60
7870 10:04:41.465596 [Byte1]: 60
7871 10:04:41.469764
7872 10:04:41.470321 Set Vref, RX VrefLevel [Byte0]: 61
7873 10:04:41.473425 [Byte1]: 61
7874 10:04:41.477716
7875 10:04:41.478278 Set Vref, RX VrefLevel [Byte0]: 62
7876 10:04:41.480865 [Byte1]: 62
7877 10:04:41.485015
7878 10:04:41.485622 Set Vref, RX VrefLevel [Byte0]: 63
7879 10:04:41.488223 [Byte1]: 63
7880 10:04:41.492469
7881 10:04:41.493075 Set Vref, RX VrefLevel [Byte0]: 64
7882 10:04:41.496039 [Byte1]: 64
7883 10:04:41.500162
7884 10:04:41.500837 Set Vref, RX VrefLevel [Byte0]: 65
7885 10:04:41.503257 [Byte1]: 65
7886 10:04:41.507327
7887 10:04:41.507796 Set Vref, RX VrefLevel [Byte0]: 66
7888 10:04:41.510805 [Byte1]: 66
7889 10:04:41.515192
7890 10:04:41.515657 Set Vref, RX VrefLevel [Byte0]: 67
7891 10:04:41.518229 [Byte1]: 67
7892 10:04:41.522834
7893 10:04:41.523451 Set Vref, RX VrefLevel [Byte0]: 68
7894 10:04:41.525880 [Byte1]: 68
7895 10:04:41.530219
7896 10:04:41.530717 Set Vref, RX VrefLevel [Byte0]: 69
7897 10:04:41.533383 [Byte1]: 69
7898 10:04:41.537937
7899 10:04:41.538509 Set Vref, RX VrefLevel [Byte0]: 70
7900 10:04:41.541398 [Byte1]: 70
7901 10:04:41.545309
7902 10:04:41.545775 Set Vref, RX VrefLevel [Byte0]: 71
7903 10:04:41.549139 [Byte1]: 71
7904 10:04:41.553075
7905 10:04:41.553647 Set Vref, RX VrefLevel [Byte0]: 72
7906 10:04:41.556412 [Byte1]: 72
7907 10:04:41.561018
7908 10:04:41.561593 Set Vref, RX VrefLevel [Byte0]: 73
7909 10:04:41.564220 [Byte1]: 73
7910 10:04:41.568283
7911 10:04:41.568894 Set Vref, RX VrefLevel [Byte0]: 74
7912 10:04:41.571432 [Byte1]: 74
7913 10:04:41.575965
7914 10:04:41.576544 Set Vref, RX VrefLevel [Byte0]: 75
7915 10:04:41.579250 [Byte1]: 75
7916 10:04:41.583436
7917 10:04:41.584011 Set Vref, RX VrefLevel [Byte0]: 76
7918 10:04:41.586442 [Byte1]: 76
7919 10:04:41.590985
7920 10:04:41.591575 Set Vref, RX VrefLevel [Byte0]: 77
7921 10:04:41.594331 [Byte1]: 77
7922 10:04:41.598620
7923 10:04:41.599198 Set Vref, RX VrefLevel [Byte0]: 78
7924 10:04:41.601580 [Byte1]: 78
7925 10:04:41.606256
7926 10:04:41.606831 Set Vref, RX VrefLevel [Byte0]: 79
7927 10:04:41.609494 [Byte1]: 79
7928 10:04:41.613700
7929 10:04:41.614273 Set Vref, RX VrefLevel [Byte0]: 80
7930 10:04:41.617170 [Byte1]: 80
7931 10:04:41.621725
7932 10:04:41.622298 Set Vref, RX VrefLevel [Byte0]: 81
7933 10:04:41.624267 [Byte1]: 81
7934 10:04:41.629062
7935 10:04:41.629684 Final RX Vref Byte 0 = 59 to rank0
7936 10:04:41.631907 Final RX Vref Byte 1 = 62 to rank0
7937 10:04:41.635547 Final RX Vref Byte 0 = 59 to rank1
7938 10:04:41.638592 Final RX Vref Byte 1 = 62 to rank1==
7939 10:04:41.642092 Dram Type= 6, Freq= 0, CH_0, rank 0
7940 10:04:41.648600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 10:04:41.649237 ==
7942 10:04:41.649623 DQS Delay:
7943 10:04:41.649977 DQS0 = 0, DQS1 = 0
7944 10:04:41.651956 DQM Delay:
7945 10:04:41.652429 DQM0 = 136, DQM1 = 124
7946 10:04:41.655431 DQ Delay:
7947 10:04:41.659013 DQ0 =136, DQ1 =140, DQ2 =132, DQ3 =132
7948 10:04:41.662173 DQ4 =140, DQ5 =124, DQ6 =142, DQ7 =144
7949 10:04:41.665447 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7950 10:04:41.669317 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =134
7951 10:04:41.669894
7952 10:04:41.670266
7953 10:04:41.670614
7954 10:04:41.671858 [DramC_TX_OE_Calibration] TA2
7955 10:04:41.675109 Original DQ_B0 (3 6) =30, OEN = 27
7956 10:04:41.678518 Original DQ_B1 (3 6) =30, OEN = 27
7957 10:04:41.681724 24, 0x0, End_B0=24 End_B1=24
7958 10:04:41.682310 25, 0x0, End_B0=25 End_B1=25
7959 10:04:41.685352 26, 0x0, End_B0=26 End_B1=26
7960 10:04:41.688737 27, 0x0, End_B0=27 End_B1=27
7961 10:04:41.691861 28, 0x0, End_B0=28 End_B1=28
7962 10:04:41.695591 29, 0x0, End_B0=29 End_B1=29
7963 10:04:41.696173 30, 0x0, End_B0=30 End_B1=30
7964 10:04:41.698338 31, 0x4141, End_B0=30 End_B1=30
7965 10:04:41.701924 Byte0 end_step=30 best_step=27
7966 10:04:41.705181 Byte1 end_step=30 best_step=27
7967 10:04:41.708335 Byte0 TX OE(2T, 0.5T) = (3, 3)
7968 10:04:41.711865 Byte1 TX OE(2T, 0.5T) = (3, 3)
7969 10:04:41.712445
7970 10:04:41.712848
7971 10:04:41.718552 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7972 10:04:41.721492 CH0 RK0: MR19=303, MR18=1D1B
7973 10:04:41.728185 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
7974 10:04:41.728927
7975 10:04:41.731626 ----->DramcWriteLeveling(PI) begin...
7976 10:04:41.732215 ==
7977 10:04:41.734816 Dram Type= 6, Freq= 0, CH_0, rank 1
7978 10:04:41.737950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 10:04:41.738595 ==
7980 10:04:41.741542 Write leveling (Byte 0): 38 => 38
7981 10:04:41.744762 Write leveling (Byte 1): 30 => 30
7982 10:04:41.748322 DramcWriteLeveling(PI) end<-----
7983 10:04:41.749094
7984 10:04:41.749482 ==
7985 10:04:41.751047 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 10:04:41.755048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 10:04:41.755632 ==
7988 10:04:41.758387 [Gating] SW mode calibration
7989 10:04:41.764761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7990 10:04:41.771290 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7991 10:04:41.774442 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 10:04:41.781442 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 10:04:41.784343 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7994 10:04:41.787472 1 4 12 | B1->B0 | 2525 3434 | 0 0 | (1 1) (0 0)
7995 10:04:41.794069 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 10:04:41.797340 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 10:04:41.801029 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 10:04:41.807489 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 10:04:41.810974 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 10:04:41.814113 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 10:04:41.820729 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 10:04:41.824493 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 0)
8003 10:04:41.827125 1 5 16 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8004 10:04:41.833857 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 10:04:41.836887 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 10:04:41.840718 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 10:04:41.847250 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 10:04:41.850333 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 10:04:41.853326 1 6 8 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
8010 10:04:41.860049 1 6 12 | B1->B0 | 2b2b 4343 | 0 0 | (0 0) (0 0)
8011 10:04:41.863703 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 10:04:41.867070 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 10:04:41.873395 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 10:04:41.876549 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 10:04:41.880015 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 10:04:41.886642 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 10:04:41.889615 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 10:04:41.893148 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8019 10:04:41.899428 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8020 10:04:41.902902 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 10:04:41.906418 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 10:04:41.912817 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 10:04:41.916286 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 10:04:41.919504 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 10:04:41.925618 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 10:04:41.928910 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 10:04:41.932350 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 10:04:41.939051 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 10:04:41.942343 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 10:04:41.945611 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 10:04:41.952017 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 10:04:41.955568 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 10:04:41.958685 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8034 10:04:41.965349 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8035 10:04:41.968510 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 10:04:41.971579 Total UI for P1: 0, mck2ui 16
8037 10:04:41.974888 best dqsien dly found for B0: ( 1, 9, 10)
8038 10:04:41.978388 Total UI for P1: 0, mck2ui 16
8039 10:04:41.981512 best dqsien dly found for B1: ( 1, 9, 12)
8040 10:04:41.985035 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8041 10:04:41.988194 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8042 10:04:41.988310
8043 10:04:41.991442 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8044 10:04:41.995389 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8045 10:04:41.997956 [Gating] SW calibration Done
8046 10:04:41.998071 ==
8047 10:04:42.001534 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 10:04:42.005092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 10:04:42.008067 ==
8050 10:04:42.008160 RX Vref Scan: 0
8051 10:04:42.008234
8052 10:04:42.011589 RX Vref 0 -> 0, step: 1
8053 10:04:42.011681
8054 10:04:42.011755 RX Delay 0 -> 252, step: 8
8055 10:04:42.018235 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8056 10:04:42.022237 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8057 10:04:42.025099 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8058 10:04:42.027884 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8059 10:04:42.034652 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8060 10:04:42.038070 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8061 10:04:42.041573 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8062 10:04:42.044694 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8063 10:04:42.048556 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8064 10:04:42.054639 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8065 10:04:42.058307 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8066 10:04:42.061655 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8067 10:04:42.064535 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8068 10:04:42.068141 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8069 10:04:42.075174 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8070 10:04:42.077711 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8071 10:04:42.078222 ==
8072 10:04:42.081339 Dram Type= 6, Freq= 0, CH_0, rank 1
8073 10:04:42.084658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8074 10:04:42.085265 ==
8075 10:04:42.087583 DQS Delay:
8076 10:04:42.088081 DQS0 = 0, DQS1 = 0
8077 10:04:42.088457 DQM Delay:
8078 10:04:42.091232 DQM0 = 135, DQM1 = 125
8079 10:04:42.091701 DQ Delay:
8080 10:04:42.094421 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8081 10:04:42.098192 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8082 10:04:42.104735 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8083 10:04:42.107959 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8084 10:04:42.108525
8085 10:04:42.108943
8086 10:04:42.109291 ==
8087 10:04:42.111165 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 10:04:42.114596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 10:04:42.115170 ==
8090 10:04:42.115548
8091 10:04:42.115899
8092 10:04:42.117499 TX Vref Scan disable
8093 10:04:42.117968 == TX Byte 0 ==
8094 10:04:42.124552 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8095 10:04:42.127902 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8096 10:04:42.130942 == TX Byte 1 ==
8097 10:04:42.134156 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8098 10:04:42.137655 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8099 10:04:42.138230 ==
8100 10:04:42.141054 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 10:04:42.144734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 10:04:42.145328 ==
8103 10:04:42.159577
8104 10:04:42.162891 TX Vref early break, caculate TX vref
8105 10:04:42.165989 TX Vref=16, minBit 0, minWin=23, winSum=390
8106 10:04:42.169887 TX Vref=18, minBit 8, minWin=23, winSum=401
8107 10:04:42.172391 TX Vref=20, minBit 0, minWin=24, winSum=406
8108 10:04:42.175597 TX Vref=22, minBit 0, minWin=24, winSum=414
8109 10:04:42.179227 TX Vref=24, minBit 2, minWin=25, winSum=422
8110 10:04:42.186086 TX Vref=26, minBit 0, minWin=26, winSum=429
8111 10:04:42.189072 TX Vref=28, minBit 2, minWin=26, winSum=434
8112 10:04:42.192169 TX Vref=30, minBit 0, minWin=25, winSum=425
8113 10:04:42.195533 TX Vref=32, minBit 0, minWin=25, winSum=417
8114 10:04:42.198568 TX Vref=34, minBit 0, minWin=25, winSum=410
8115 10:04:42.205507 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 28
8116 10:04:42.206076
8117 10:04:42.208823 Final TX Range 0 Vref 28
8118 10:04:42.209342
8119 10:04:42.209757 ==
8120 10:04:42.211830 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 10:04:42.215310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 10:04:42.215767 ==
8123 10:04:42.216139
8124 10:04:42.216481
8125 10:04:42.218702 TX Vref Scan disable
8126 10:04:42.224831 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8127 10:04:42.225275 == TX Byte 0 ==
8128 10:04:42.228505 u2DelayCellOfst[0]=13 cells (4 PI)
8129 10:04:42.231887 u2DelayCellOfst[1]=20 cells (6 PI)
8130 10:04:42.235112 u2DelayCellOfst[2]=13 cells (4 PI)
8131 10:04:42.238630 u2DelayCellOfst[3]=13 cells (4 PI)
8132 10:04:42.241786 u2DelayCellOfst[4]=10 cells (3 PI)
8133 10:04:42.245329 u2DelayCellOfst[5]=0 cells (0 PI)
8134 10:04:42.248128 u2DelayCellOfst[6]=20 cells (6 PI)
8135 10:04:42.251860 u2DelayCellOfst[7]=20 cells (6 PI)
8136 10:04:42.254656 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8137 10:04:42.258087 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8138 10:04:42.261587 == TX Byte 1 ==
8139 10:04:42.264990 u2DelayCellOfst[8]=0 cells (0 PI)
8140 10:04:42.268094 u2DelayCellOfst[9]=0 cells (0 PI)
8141 10:04:42.268520 u2DelayCellOfst[10]=6 cells (2 PI)
8142 10:04:42.271444 u2DelayCellOfst[11]=3 cells (1 PI)
8143 10:04:42.274580 u2DelayCellOfst[12]=13 cells (4 PI)
8144 10:04:42.278208 u2DelayCellOfst[13]=13 cells (4 PI)
8145 10:04:42.281629 u2DelayCellOfst[14]=13 cells (4 PI)
8146 10:04:42.284796 u2DelayCellOfst[15]=10 cells (3 PI)
8147 10:04:42.291202 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8148 10:04:42.294281 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8149 10:04:42.294862 DramC Write-DBI on
8150 10:04:42.297859 ==
8151 10:04:42.300753 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 10:04:42.304195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 10:04:42.304750 ==
8154 10:04:42.305162
8155 10:04:42.305522
8156 10:04:42.307334 TX Vref Scan disable
8157 10:04:42.307878 == TX Byte 0 ==
8158 10:04:42.314418 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8159 10:04:42.314971 == TX Byte 1 ==
8160 10:04:42.317347 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8161 10:04:42.320632 DramC Write-DBI off
8162 10:04:42.321125
8163 10:04:42.321505 [DATLAT]
8164 10:04:42.323948 Freq=1600, CH0 RK1
8165 10:04:42.324354
8166 10:04:42.324691 DATLAT Default: 0xf
8167 10:04:42.326949 0, 0xFFFF, sum = 0
8168 10:04:42.327376 1, 0xFFFF, sum = 0
8169 10:04:42.330767 2, 0xFFFF, sum = 0
8170 10:04:42.331227 3, 0xFFFF, sum = 0
8171 10:04:42.333909 4, 0xFFFF, sum = 0
8172 10:04:42.337303 5, 0xFFFF, sum = 0
8173 10:04:42.337882 6, 0xFFFF, sum = 0
8174 10:04:42.340294 7, 0xFFFF, sum = 0
8175 10:04:42.340747 8, 0xFFFF, sum = 0
8176 10:04:42.343652 9, 0xFFFF, sum = 0
8177 10:04:42.344082 10, 0xFFFF, sum = 0
8178 10:04:42.346894 11, 0xFFFF, sum = 0
8179 10:04:42.347362 12, 0xFFFF, sum = 0
8180 10:04:42.350443 13, 0xFFFF, sum = 0
8181 10:04:42.350975 14, 0x0, sum = 1
8182 10:04:42.353781 15, 0x0, sum = 2
8183 10:04:42.354276 16, 0x0, sum = 3
8184 10:04:42.357090 17, 0x0, sum = 4
8185 10:04:42.357561 best_step = 15
8186 10:04:42.357936
8187 10:04:42.358293 ==
8188 10:04:42.360408 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 10:04:42.363448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 10:04:42.366987 ==
8191 10:04:42.367485 RX Vref Scan: 0
8192 10:04:42.367877
8193 10:04:42.370263 RX Vref 0 -> 0, step: 1
8194 10:04:42.370720
8195 10:04:42.373630 RX Delay 11 -> 252, step: 4
8196 10:04:42.376822 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8197 10:04:42.379922 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8198 10:04:42.383256 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8199 10:04:42.389939 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8200 10:04:42.393071 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8201 10:04:42.396824 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8202 10:04:42.399666 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8203 10:04:42.402998 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8204 10:04:42.409898 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8205 10:04:42.412929 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8206 10:04:42.416386 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8207 10:04:42.419656 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8208 10:04:42.423229 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8209 10:04:42.429556 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8210 10:04:42.432841 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8211 10:04:42.435981 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8212 10:04:42.436409 ==
8213 10:04:42.439122 Dram Type= 6, Freq= 0, CH_0, rank 1
8214 10:04:42.442713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8215 10:04:42.446392 ==
8216 10:04:42.446820 DQS Delay:
8217 10:04:42.447246 DQS0 = 0, DQS1 = 0
8218 10:04:42.449487 DQM Delay:
8219 10:04:42.449917 DQM0 = 132, DQM1 = 123
8220 10:04:42.452526 DQ Delay:
8221 10:04:42.456146 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8222 10:04:42.459423 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8223 10:04:42.462381 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8224 10:04:42.465710 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8225 10:04:42.466141
8226 10:04:42.466568
8227 10:04:42.466964
8228 10:04:42.469236 [DramC_TX_OE_Calibration] TA2
8229 10:04:42.472265 Original DQ_B0 (3 6) =30, OEN = 27
8230 10:04:42.476132 Original DQ_B1 (3 6) =30, OEN = 27
8231 10:04:42.479413 24, 0x0, End_B0=24 End_B1=24
8232 10:04:42.479847 25, 0x0, End_B0=25 End_B1=25
8233 10:04:42.482306 26, 0x0, End_B0=26 End_B1=26
8234 10:04:42.485702 27, 0x0, End_B0=27 End_B1=27
8235 10:04:42.489079 28, 0x0, End_B0=28 End_B1=28
8236 10:04:42.489665 29, 0x0, End_B0=29 End_B1=29
8237 10:04:42.492185 30, 0x0, End_B0=30 End_B1=30
8238 10:04:42.495769 31, 0x4141, End_B0=30 End_B1=30
8239 10:04:42.499417 Byte0 end_step=30 best_step=27
8240 10:04:42.502190 Byte1 end_step=30 best_step=27
8241 10:04:42.505584 Byte0 TX OE(2T, 0.5T) = (3, 3)
8242 10:04:42.506024 Byte1 TX OE(2T, 0.5T) = (3, 3)
8243 10:04:42.508673
8244 10:04:42.509134
8245 10:04:42.515162 [DQSOSCAuto] RK1, (LSB)MR18= 0x2310, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8246 10:04:42.518571 CH0 RK1: MR19=303, MR18=2310
8247 10:04:42.525518 CH0_RK1: MR19=0x303, MR18=0x2310, DQSOSC=392, MR23=63, INC=24, DEC=16
8248 10:04:42.528625 [RxdqsGatingPostProcess] freq 1600
8249 10:04:42.531594 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8250 10:04:42.534850 best DQS0 dly(2T, 0.5T) = (1, 1)
8251 10:04:42.538064 best DQS1 dly(2T, 0.5T) = (1, 1)
8252 10:04:42.541905 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8253 10:04:42.544640 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8254 10:04:42.548039 best DQS0 dly(2T, 0.5T) = (1, 1)
8255 10:04:42.551439 best DQS1 dly(2T, 0.5T) = (1, 1)
8256 10:04:42.554965 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8257 10:04:42.557874 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8258 10:04:42.561525 Pre-setting of DQS Precalculation
8259 10:04:42.564580 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8260 10:04:42.564688 ==
8261 10:04:42.567939 Dram Type= 6, Freq= 0, CH_1, rank 0
8262 10:04:42.571657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 10:04:42.571742 ==
8264 10:04:42.578346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8265 10:04:42.581227 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8266 10:04:42.587751 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8267 10:04:42.591103 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8268 10:04:42.601404 [CA 0] Center 40 (11~70) winsize 60
8269 10:04:42.604744 [CA 1] Center 41 (11~71) winsize 61
8270 10:04:42.607972 [CA 2] Center 37 (8~67) winsize 60
8271 10:04:42.611388 [CA 3] Center 36 (7~66) winsize 60
8272 10:04:42.614917 [CA 4] Center 36 (6~66) winsize 61
8273 10:04:42.618003 [CA 5] Center 36 (6~66) winsize 61
8274 10:04:42.618087
8275 10:04:42.621243 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8276 10:04:42.621326
8277 10:04:42.624994 [CATrainingPosCal] consider 1 rank data
8278 10:04:42.627823 u2DelayCellTimex100 = 290/100 ps
8279 10:04:42.630971 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8280 10:04:42.637822 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8281 10:04:42.641383 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8282 10:04:42.644317 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8283 10:04:42.647573 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
8284 10:04:42.650897 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8285 10:04:42.650982
8286 10:04:42.654263 CA PerBit enable=1, Macro0, CA PI delay=36
8287 10:04:42.654347
8288 10:04:42.657612 [CBTSetCACLKResult] CA Dly = 36
8289 10:04:42.661649 CS Dly: 8 (0~39)
8290 10:04:42.664496 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8291 10:04:42.667611 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8292 10:04:42.667697 ==
8293 10:04:42.670833 Dram Type= 6, Freq= 0, CH_1, rank 1
8294 10:04:42.677794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8295 10:04:42.677877 ==
8296 10:04:42.680935 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8297 10:04:42.683785 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8298 10:04:42.690613 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8299 10:04:42.696816 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8300 10:04:42.704590 [CA 0] Center 42 (13~72) winsize 60
8301 10:04:42.707659 [CA 1] Center 42 (12~72) winsize 61
8302 10:04:42.711260 [CA 2] Center 37 (8~67) winsize 60
8303 10:04:42.714220 [CA 3] Center 37 (8~66) winsize 59
8304 10:04:42.717550 [CA 4] Center 37 (8~67) winsize 60
8305 10:04:42.720692 [CA 5] Center 36 (7~66) winsize 60
8306 10:04:42.720798
8307 10:04:42.724284 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8308 10:04:42.724365
8309 10:04:42.727747 [CATrainingPosCal] consider 2 rank data
8310 10:04:42.731083 u2DelayCellTimex100 = 290/100 ps
8311 10:04:42.737479 CA0 delay=41 (13~70),Diff = 5 PI (16 cell)
8312 10:04:42.741095 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8313 10:04:42.744406 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8314 10:04:42.747606 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8315 10:04:42.750788 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8316 10:04:42.754389 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8317 10:04:42.754470
8318 10:04:42.757308 CA PerBit enable=1, Macro0, CA PI delay=36
8319 10:04:42.757389
8320 10:04:42.760775 [CBTSetCACLKResult] CA Dly = 36
8321 10:04:42.763978 CS Dly: 10 (0~43)
8322 10:04:42.767677 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8323 10:04:42.770471 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8324 10:04:42.770557
8325 10:04:42.774138 ----->DramcWriteLeveling(PI) begin...
8326 10:04:42.774231 ==
8327 10:04:42.777533 Dram Type= 6, Freq= 0, CH_1, rank 0
8328 10:04:42.784059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 10:04:42.784169 ==
8330 10:04:42.787312 Write leveling (Byte 0): 24 => 24
8331 10:04:42.787432 Write leveling (Byte 1): 28 => 28
8332 10:04:42.790961 DramcWriteLeveling(PI) end<-----
8333 10:04:42.791103
8334 10:04:42.794170 ==
8335 10:04:42.794307 Dram Type= 6, Freq= 0, CH_1, rank 0
8336 10:04:42.800356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8337 10:04:42.800508 ==
8338 10:04:42.803921 [Gating] SW mode calibration
8339 10:04:42.810522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8340 10:04:42.813697 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8341 10:04:42.820361 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 10:04:42.823853 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 10:04:42.827441 1 4 8 | B1->B0 | 2626 3131 | 0 1 | (0 0) (1 1)
8344 10:04:42.833999 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 10:04:42.837432 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 10:04:42.840863 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 10:04:42.847261 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 10:04:42.850657 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 10:04:42.854263 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 10:04:42.860113 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8351 10:04:42.863549 1 5 8 | B1->B0 | 3333 2a2a | 1 1 | (1 1) (1 0)
8352 10:04:42.866915 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8353 10:04:42.873513 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 10:04:42.876997 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 10:04:42.880484 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 10:04:42.886898 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 10:04:42.890321 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 10:04:42.893235 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8359 10:04:42.900307 1 6 8 | B1->B0 | 3939 4444 | 0 0 | (1 1) (0 0)
8360 10:04:42.903362 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 10:04:42.906541 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 10:04:42.913674 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 10:04:42.916917 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 10:04:42.920270 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 10:04:42.926848 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 10:04:42.929800 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8367 10:04:42.932877 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8368 10:04:42.939793 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8369 10:04:42.943130 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8370 10:04:42.946312 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 10:04:42.952929 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 10:04:42.956286 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 10:04:42.959674 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 10:04:42.966036 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 10:04:42.968857 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 10:04:42.972429 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 10:04:42.979316 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 10:04:42.982084 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 10:04:42.985497 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 10:04:42.992215 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 10:04:42.995395 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 10:04:42.998708 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 10:04:43.002735 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8384 10:04:43.008987 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8385 10:04:43.012975 Total UI for P1: 0, mck2ui 16
8386 10:04:43.015487 best dqsien dly found for B0: ( 1, 9, 8)
8387 10:04:43.018653 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 10:04:43.022084 Total UI for P1: 0, mck2ui 16
8389 10:04:43.025633 best dqsien dly found for B1: ( 1, 9, 12)
8390 10:04:43.028731 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8391 10:04:43.032203 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8392 10:04:43.032366
8393 10:04:43.035184 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8394 10:04:43.041811 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8395 10:04:43.041965 [Gating] SW calibration Done
8396 10:04:43.042090 ==
8397 10:04:43.045161 Dram Type= 6, Freq= 0, CH_1, rank 0
8398 10:04:43.052365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 10:04:43.052572 ==
8400 10:04:43.052736 RX Vref Scan: 0
8401 10:04:43.052909
8402 10:04:43.055574 RX Vref 0 -> 0, step: 1
8403 10:04:43.055788
8404 10:04:43.058746 RX Delay 0 -> 252, step: 8
8405 10:04:43.061998 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8406 10:04:43.065176 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8407 10:04:43.068468 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8408 10:04:43.072022 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8409 10:04:43.078695 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8410 10:04:43.082163 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8411 10:04:43.085878 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8412 10:04:43.088549 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8413 10:04:43.092247 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8414 10:04:43.098441 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8415 10:04:43.101945 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8416 10:04:43.105194 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8417 10:04:43.108348 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8418 10:04:43.111679 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8419 10:04:43.118776 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8420 10:04:43.121643 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8421 10:04:43.122070 ==
8422 10:04:43.125042 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 10:04:43.128464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 10:04:43.128946 ==
8425 10:04:43.131899 DQS Delay:
8426 10:04:43.132324 DQS0 = 0, DQS1 = 0
8427 10:04:43.132661 DQM Delay:
8428 10:04:43.135082 DQM0 = 137, DQM1 = 130
8429 10:04:43.135512 DQ Delay:
8430 10:04:43.138275 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8431 10:04:43.141252 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8432 10:04:43.148229 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8433 10:04:43.151538 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8434 10:04:43.151963
8435 10:04:43.152301
8436 10:04:43.152618 ==
8437 10:04:43.154655 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 10:04:43.158009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 10:04:43.158441 ==
8440 10:04:43.158780
8441 10:04:43.159096
8442 10:04:43.161267 TX Vref Scan disable
8443 10:04:43.161691 == TX Byte 0 ==
8444 10:04:43.167926 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8445 10:04:43.171496 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8446 10:04:43.174799 == TX Byte 1 ==
8447 10:04:43.177897 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8448 10:04:43.181281 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8449 10:04:43.181709 ==
8450 10:04:43.184652 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 10:04:43.188164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 10:04:43.188593 ==
8453 10:04:43.201902
8454 10:04:43.205169 TX Vref early break, caculate TX vref
8455 10:04:43.208785 TX Vref=16, minBit 1, minWin=22, winSum=372
8456 10:04:43.211623 TX Vref=18, minBit 15, minWin=22, winSum=385
8457 10:04:43.214808 TX Vref=20, minBit 15, minWin=23, winSum=392
8458 10:04:43.218560 TX Vref=22, minBit 9, minWin=24, winSum=402
8459 10:04:43.224728 TX Vref=24, minBit 15, minWin=24, winSum=414
8460 10:04:43.228259 TX Vref=26, minBit 15, minWin=25, winSum=419
8461 10:04:43.231482 TX Vref=28, minBit 10, minWin=26, winSum=429
8462 10:04:43.234825 TX Vref=30, minBit 10, minWin=25, winSum=420
8463 10:04:43.238179 TX Vref=32, minBit 10, minWin=24, winSum=416
8464 10:04:43.241589 TX Vref=34, minBit 13, minWin=23, winSum=402
8465 10:04:43.248074 [TxChooseVref] Worse bit 10, Min win 26, Win sum 429, Final Vref 28
8466 10:04:43.248504
8467 10:04:43.251722 Final TX Range 0 Vref 28
8468 10:04:43.252151
8469 10:04:43.252492 ==
8470 10:04:43.254645 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 10:04:43.258151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 10:04:43.258581 ==
8473 10:04:43.261668
8474 10:04:43.262090
8475 10:04:43.262426 TX Vref Scan disable
8476 10:04:43.267954 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8477 10:04:43.268384 == TX Byte 0 ==
8478 10:04:43.271210 u2DelayCellOfst[0]=16 cells (5 PI)
8479 10:04:43.274510 u2DelayCellOfst[1]=10 cells (3 PI)
8480 10:04:43.277675 u2DelayCellOfst[2]=0 cells (0 PI)
8481 10:04:43.281399 u2DelayCellOfst[3]=6 cells (2 PI)
8482 10:04:43.284331 u2DelayCellOfst[4]=6 cells (2 PI)
8483 10:04:43.287895 u2DelayCellOfst[5]=16 cells (5 PI)
8484 10:04:43.291435 u2DelayCellOfst[6]=16 cells (5 PI)
8485 10:04:43.294293 u2DelayCellOfst[7]=3 cells (1 PI)
8486 10:04:43.297762 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8487 10:04:43.301124 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8488 10:04:43.304261 == TX Byte 1 ==
8489 10:04:43.307521 u2DelayCellOfst[8]=0 cells (0 PI)
8490 10:04:43.311149 u2DelayCellOfst[9]=0 cells (0 PI)
8491 10:04:43.314221 u2DelayCellOfst[10]=6 cells (2 PI)
8492 10:04:43.317519 u2DelayCellOfst[11]=3 cells (1 PI)
8493 10:04:43.321055 u2DelayCellOfst[12]=13 cells (4 PI)
8494 10:04:43.321590 u2DelayCellOfst[13]=13 cells (4 PI)
8495 10:04:43.323961 u2DelayCellOfst[14]=13 cells (4 PI)
8496 10:04:43.327424 u2DelayCellOfst[15]=10 cells (3 PI)
8497 10:04:43.333678 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8498 10:04:43.337659 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8499 10:04:43.338090 DramC Write-DBI on
8500 10:04:43.340552 ==
8501 10:04:43.343908 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 10:04:43.347085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 10:04:43.347616 ==
8504 10:04:43.347956
8505 10:04:43.348273
8506 10:04:43.350589 TX Vref Scan disable
8507 10:04:43.351016 == TX Byte 0 ==
8508 10:04:43.357020 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8509 10:04:43.357449 == TX Byte 1 ==
8510 10:04:43.360176 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8511 10:04:43.363586 DramC Write-DBI off
8512 10:04:43.364016
8513 10:04:43.364355 [DATLAT]
8514 10:04:43.367047 Freq=1600, CH1 RK0
8515 10:04:43.367503
8516 10:04:43.367849 DATLAT Default: 0xf
8517 10:04:43.370546 0, 0xFFFF, sum = 0
8518 10:04:43.370980 1, 0xFFFF, sum = 0
8519 10:04:43.373873 2, 0xFFFF, sum = 0
8520 10:04:43.374306 3, 0xFFFF, sum = 0
8521 10:04:43.376825 4, 0xFFFF, sum = 0
8522 10:04:43.380197 5, 0xFFFF, sum = 0
8523 10:04:43.380629 6, 0xFFFF, sum = 0
8524 10:04:43.383437 7, 0xFFFF, sum = 0
8525 10:04:43.383872 8, 0xFFFF, sum = 0
8526 10:04:43.386710 9, 0xFFFF, sum = 0
8527 10:04:43.387143 10, 0xFFFF, sum = 0
8528 10:04:43.390059 11, 0xFFFF, sum = 0
8529 10:04:43.390512 12, 0xFFFF, sum = 0
8530 10:04:43.393644 13, 0xFFFF, sum = 0
8531 10:04:43.394077 14, 0x0, sum = 1
8532 10:04:43.396616 15, 0x0, sum = 2
8533 10:04:43.397080 16, 0x0, sum = 3
8534 10:04:43.400031 17, 0x0, sum = 4
8535 10:04:43.400467 best_step = 15
8536 10:04:43.400849
8537 10:04:43.401179 ==
8538 10:04:43.403568 Dram Type= 6, Freq= 0, CH_1, rank 0
8539 10:04:43.406578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8540 10:04:43.410111 ==
8541 10:04:43.410538 RX Vref Scan: 1
8542 10:04:43.410875
8543 10:04:43.413451 Set Vref Range= 24 -> 127
8544 10:04:43.413875
8545 10:04:43.416356 RX Vref 24 -> 127, step: 1
8546 10:04:43.416812
8547 10:04:43.417159 RX Delay 19 -> 252, step: 4
8548 10:04:43.417475
8549 10:04:43.419955 Set Vref, RX VrefLevel [Byte0]: 24
8550 10:04:43.422980 [Byte1]: 24
8551 10:04:43.426965
8552 10:04:43.427504 Set Vref, RX VrefLevel [Byte0]: 25
8553 10:04:43.430472 [Byte1]: 25
8554 10:04:43.434924
8555 10:04:43.435351 Set Vref, RX VrefLevel [Byte0]: 26
8556 10:04:43.438098 [Byte1]: 26
8557 10:04:43.442349
8558 10:04:43.442807 Set Vref, RX VrefLevel [Byte0]: 27
8559 10:04:43.445451 [Byte1]: 27
8560 10:04:43.449575
8561 10:04:43.450003 Set Vref, RX VrefLevel [Byte0]: 28
8562 10:04:43.452917 [Byte1]: 28
8563 10:04:43.456875
8564 10:04:43.457301 Set Vref, RX VrefLevel [Byte0]: 29
8565 10:04:43.460337 [Byte1]: 29
8566 10:04:43.464467
8567 10:04:43.464934 Set Vref, RX VrefLevel [Byte0]: 30
8568 10:04:43.467984 [Byte1]: 30
8569 10:04:43.472364
8570 10:04:43.472819 Set Vref, RX VrefLevel [Byte0]: 31
8571 10:04:43.476109 [Byte1]: 31
8572 10:04:43.479678
8573 10:04:43.480119 Set Vref, RX VrefLevel [Byte0]: 32
8574 10:04:43.483308 [Byte1]: 32
8575 10:04:43.487624
8576 10:04:43.488048 Set Vref, RX VrefLevel [Byte0]: 33
8577 10:04:43.490758 [Byte1]: 33
8578 10:04:43.495047
8579 10:04:43.495472 Set Vref, RX VrefLevel [Byte0]: 34
8580 10:04:43.498287 [Byte1]: 34
8581 10:04:43.502551
8582 10:04:43.503067 Set Vref, RX VrefLevel [Byte0]: 35
8583 10:04:43.506198 [Byte1]: 35
8584 10:04:43.510104
8585 10:04:43.510586 Set Vref, RX VrefLevel [Byte0]: 36
8586 10:04:43.513150 [Byte1]: 36
8587 10:04:43.517918
8588 10:04:43.518343 Set Vref, RX VrefLevel [Byte0]: 37
8589 10:04:43.521021 [Byte1]: 37
8590 10:04:43.525301
8591 10:04:43.525744 Set Vref, RX VrefLevel [Byte0]: 38
8592 10:04:43.529052 [Byte1]: 38
8593 10:04:43.532564
8594 10:04:43.536456 Set Vref, RX VrefLevel [Byte0]: 39
8595 10:04:43.536921 [Byte1]: 39
8596 10:04:43.540406
8597 10:04:43.540865 Set Vref, RX VrefLevel [Byte0]: 40
8598 10:04:43.543823 [Byte1]: 40
8599 10:04:43.548571
8600 10:04:43.549136 Set Vref, RX VrefLevel [Byte0]: 41
8601 10:04:43.551695 [Byte1]: 41
8602 10:04:43.556081
8603 10:04:43.556576 Set Vref, RX VrefLevel [Byte0]: 42
8604 10:04:43.559040 [Byte1]: 42
8605 10:04:43.563324
8606 10:04:43.563889 Set Vref, RX VrefLevel [Byte0]: 43
8607 10:04:43.566395 [Byte1]: 43
8608 10:04:43.570611
8609 10:04:43.571075 Set Vref, RX VrefLevel [Byte0]: 44
8610 10:04:43.574343 [Byte1]: 44
8611 10:04:43.578304
8612 10:04:43.578897 Set Vref, RX VrefLevel [Byte0]: 45
8613 10:04:43.581689 [Byte1]: 45
8614 10:04:43.586074
8615 10:04:43.586640 Set Vref, RX VrefLevel [Byte0]: 46
8616 10:04:43.589047 [Byte1]: 46
8617 10:04:43.593837
8618 10:04:43.594305 Set Vref, RX VrefLevel [Byte0]: 47
8619 10:04:43.596929 [Byte1]: 47
8620 10:04:43.601205
8621 10:04:43.601791 Set Vref, RX VrefLevel [Byte0]: 48
8622 10:04:43.604579 [Byte1]: 48
8623 10:04:43.609174
8624 10:04:43.609734 Set Vref, RX VrefLevel [Byte0]: 49
8625 10:04:43.611915 [Byte1]: 49
8626 10:04:43.616389
8627 10:04:43.616988 Set Vref, RX VrefLevel [Byte0]: 50
8628 10:04:43.619761 [Byte1]: 50
8629 10:04:43.623932
8630 10:04:43.624486 Set Vref, RX VrefLevel [Byte0]: 51
8631 10:04:43.627151 [Byte1]: 51
8632 10:04:43.631301
8633 10:04:43.631882 Set Vref, RX VrefLevel [Byte0]: 52
8634 10:04:43.634713 [Byte1]: 52
8635 10:04:43.638941
8636 10:04:43.639411 Set Vref, RX VrefLevel [Byte0]: 53
8637 10:04:43.642214 [Byte1]: 53
8638 10:04:43.646852
8639 10:04:43.647319 Set Vref, RX VrefLevel [Byte0]: 54
8640 10:04:43.649859 [Byte1]: 54
8641 10:04:43.654063
8642 10:04:43.654693 Set Vref, RX VrefLevel [Byte0]: 55
8643 10:04:43.657441 [Byte1]: 55
8644 10:04:43.661448
8645 10:04:43.661938 Set Vref, RX VrefLevel [Byte0]: 56
8646 10:04:43.664874 [Byte1]: 56
8647 10:04:43.669233
8648 10:04:43.669744 Set Vref, RX VrefLevel [Byte0]: 57
8649 10:04:43.672573 [Byte1]: 57
8650 10:04:43.678239
8651 10:04:43.678669 Set Vref, RX VrefLevel [Byte0]: 58
8652 10:04:43.680143 [Byte1]: 58
8653 10:04:43.684646
8654 10:04:43.685100 Set Vref, RX VrefLevel [Byte0]: 59
8655 10:04:43.687659 [Byte1]: 59
8656 10:04:43.692067
8657 10:04:43.692536 Set Vref, RX VrefLevel [Byte0]: 60
8658 10:04:43.695173 [Byte1]: 60
8659 10:04:43.699633
8660 10:04:43.700087 Set Vref, RX VrefLevel [Byte0]: 61
8661 10:04:43.702918 [Byte1]: 61
8662 10:04:43.707057
8663 10:04:43.707478 Set Vref, RX VrefLevel [Byte0]: 62
8664 10:04:43.710297 [Byte1]: 62
8665 10:04:43.714459
8666 10:04:43.714875 Set Vref, RX VrefLevel [Byte0]: 63
8667 10:04:43.718116 [Byte1]: 63
8668 10:04:43.722117
8669 10:04:43.722534 Set Vref, RX VrefLevel [Byte0]: 64
8670 10:04:43.725459 [Byte1]: 64
8671 10:04:43.730320
8672 10:04:43.730736 Set Vref, RX VrefLevel [Byte0]: 65
8673 10:04:43.733056 [Byte1]: 65
8674 10:04:43.737298
8675 10:04:43.737715 Set Vref, RX VrefLevel [Byte0]: 66
8676 10:04:43.740545 [Byte1]: 66
8677 10:04:43.744890
8678 10:04:43.745307 Set Vref, RX VrefLevel [Byte0]: 67
8679 10:04:43.748688 [Byte1]: 67
8680 10:04:43.752389
8681 10:04:43.752835 Set Vref, RX VrefLevel [Byte0]: 68
8682 10:04:43.756009 [Byte1]: 68
8683 10:04:43.760169
8684 10:04:43.760618 Set Vref, RX VrefLevel [Byte0]: 69
8685 10:04:43.763541 [Byte1]: 69
8686 10:04:43.767543
8687 10:04:43.767960 Set Vref, RX VrefLevel [Byte0]: 70
8688 10:04:43.771199 [Byte1]: 70
8689 10:04:43.775613
8690 10:04:43.776041 Set Vref, RX VrefLevel [Byte0]: 71
8691 10:04:43.778775 [Byte1]: 71
8692 10:04:43.783024
8693 10:04:43.783443 Set Vref, RX VrefLevel [Byte0]: 72
8694 10:04:43.786283 [Byte1]: 72
8695 10:04:43.790628
8696 10:04:43.791109 Set Vref, RX VrefLevel [Byte0]: 73
8697 10:04:43.793592 [Byte1]: 73
8698 10:04:43.798255
8699 10:04:43.798808 Set Vref, RX VrefLevel [Byte0]: 74
8700 10:04:43.801251 [Byte1]: 74
8701 10:04:43.805410
8702 10:04:43.805876 Set Vref, RX VrefLevel [Byte0]: 75
8703 10:04:43.808906 [Byte1]: 75
8704 10:04:43.813082
8705 10:04:43.813642 Final RX Vref Byte 0 = 59 to rank0
8706 10:04:43.816479 Final RX Vref Byte 1 = 62 to rank0
8707 10:04:43.819521 Final RX Vref Byte 0 = 59 to rank1
8708 10:04:43.822760 Final RX Vref Byte 1 = 62 to rank1==
8709 10:04:43.826185 Dram Type= 6, Freq= 0, CH_1, rank 0
8710 10:04:43.832723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8711 10:04:43.833237 ==
8712 10:04:43.833645 DQS Delay:
8713 10:04:43.836166 DQS0 = 0, DQS1 = 0
8714 10:04:43.836584 DQM Delay:
8715 10:04:43.837020 DQM0 = 135, DQM1 = 129
8716 10:04:43.839679 DQ Delay:
8717 10:04:43.842922 DQ0 =138, DQ1 =130, DQ2 =124, DQ3 =132
8718 10:04:43.846083 DQ4 =134, DQ5 =146, DQ6 =146, DQ7 =132
8719 10:04:43.849374 DQ8 =114, DQ9 =118, DQ10 =134, DQ11 =124
8720 10:04:43.852570 DQ12 =140, DQ13 =134, DQ14 =134, DQ15 =134
8721 10:04:43.853036
8722 10:04:43.853373
8723 10:04:43.853681
8724 10:04:43.855961 [DramC_TX_OE_Calibration] TA2
8725 10:04:43.859125 Original DQ_B0 (3 6) =30, OEN = 27
8726 10:04:43.862864 Original DQ_B1 (3 6) =30, OEN = 27
8727 10:04:43.866064 24, 0x0, End_B0=24 End_B1=24
8728 10:04:43.869272 25, 0x0, End_B0=25 End_B1=25
8729 10:04:43.869809 26, 0x0, End_B0=26 End_B1=26
8730 10:04:43.872887 27, 0x0, End_B0=27 End_B1=27
8731 10:04:43.876009 28, 0x0, End_B0=28 End_B1=28
8732 10:04:43.879129 29, 0x0, End_B0=29 End_B1=29
8733 10:04:43.879694 30, 0x0, End_B0=30 End_B1=30
8734 10:04:43.882981 31, 0x4141, End_B0=30 End_B1=30
8735 10:04:43.885542 Byte0 end_step=30 best_step=27
8736 10:04:43.889173 Byte1 end_step=30 best_step=27
8737 10:04:43.892680 Byte0 TX OE(2T, 0.5T) = (3, 3)
8738 10:04:43.895716 Byte1 TX OE(2T, 0.5T) = (3, 3)
8739 10:04:43.896141
8740 10:04:43.896475
8741 10:04:43.901942 [DQSOSCAuto] RK0, (LSB)MR18= 0x1825, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
8742 10:04:43.905310 CH1 RK0: MR19=303, MR18=1825
8743 10:04:43.912036 CH1_RK0: MR19=0x303, MR18=0x1825, DQSOSC=391, MR23=63, INC=24, DEC=16
8744 10:04:43.912466
8745 10:04:43.915792 ----->DramcWriteLeveling(PI) begin...
8746 10:04:43.916263 ==
8747 10:04:43.918656 Dram Type= 6, Freq= 0, CH_1, rank 1
8748 10:04:43.922185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 10:04:43.922825 ==
8750 10:04:43.925514 Write leveling (Byte 0): 25 => 25
8751 10:04:43.928513 Write leveling (Byte 1): 28 => 28
8752 10:04:43.931625 DramcWriteLeveling(PI) end<-----
8753 10:04:43.932165
8754 10:04:43.932640 ==
8755 10:04:43.935092 Dram Type= 6, Freq= 0, CH_1, rank 1
8756 10:04:43.938647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8757 10:04:43.942013 ==
8758 10:04:43.942498 [Gating] SW mode calibration
8759 10:04:43.952265 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8760 10:04:43.955326 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8761 10:04:43.958827 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 10:04:43.965057 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 10:04:43.968394 1 4 8 | B1->B0 | 2625 2323 | 1 0 | (0 0) (0 0)
8764 10:04:43.971653 1 4 12 | B1->B0 | 3434 2424 | 1 1 | (1 1) (0 0)
8765 10:04:43.978288 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 10:04:43.981650 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 10:04:43.984821 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 10:04:43.991642 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 10:04:43.994780 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 10:04:43.998145 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 10:04:44.004490 1 5 8 | B1->B0 | 3232 3434 | 0 1 | (0 1) (1 0)
8772 10:04:44.007980 1 5 12 | B1->B0 | 2323 3333 | 0 0 | (1 0) (0 1)
8773 10:04:44.011423 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 10:04:44.017699 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 10:04:44.021077 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 10:04:44.024542 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 10:04:44.031157 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 10:04:44.034212 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 10:04:44.037624 1 6 8 | B1->B0 | 3535 2323 | 0 0 | (0 0) (0 0)
8780 10:04:44.044388 1 6 12 | B1->B0 | 4646 3a3a | 0 0 | (0 0) (0 0)
8781 10:04:44.047379 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 10:04:44.050559 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 10:04:44.057152 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 10:04:44.060573 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 10:04:44.064151 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 10:04:44.070518 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 10:04:44.073657 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8788 10:04:44.076988 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8789 10:04:44.084174 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8790 10:04:44.087660 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 10:04:44.090517 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 10:04:44.096849 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 10:04:44.100401 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 10:04:44.103473 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 10:04:44.109824 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 10:04:44.113767 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 10:04:44.116735 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 10:04:44.123295 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 10:04:44.126416 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 10:04:44.130032 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 10:04:44.136715 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 10:04:44.140093 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 10:04:44.143335 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8804 10:04:44.149736 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8805 10:04:44.152984 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 10:04:44.156550 Total UI for P1: 0, mck2ui 16
8807 10:04:44.159686 best dqsien dly found for B0: ( 1, 9, 10)
8808 10:04:44.162693 Total UI for P1: 0, mck2ui 16
8809 10:04:44.167270 best dqsien dly found for B1: ( 1, 9, 10)
8810 10:04:44.169481 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8811 10:04:44.172886 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8812 10:04:44.173449
8813 10:04:44.175717 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8814 10:04:44.182486 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8815 10:04:44.183059 [Gating] SW calibration Done
8816 10:04:44.183438 ==
8817 10:04:44.185682 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 10:04:44.192209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 10:04:44.192855 ==
8820 10:04:44.193368 RX Vref Scan: 0
8821 10:04:44.193734
8822 10:04:44.196006 RX Vref 0 -> 0, step: 1
8823 10:04:44.196475
8824 10:04:44.199580 RX Delay 0 -> 252, step: 8
8825 10:04:44.202677 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8826 10:04:44.205830 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8827 10:04:44.208888 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8828 10:04:44.212450 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8829 10:04:44.218822 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8830 10:04:44.222394 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8831 10:04:44.225495 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8832 10:04:44.229013 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8833 10:04:44.232381 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8834 10:04:44.238987 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8835 10:04:44.241991 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8836 10:04:44.245346 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8837 10:04:44.248741 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8838 10:04:44.255061 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8839 10:04:44.258541 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8840 10:04:44.262140 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8841 10:04:44.262706 ==
8842 10:04:44.265202 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 10:04:44.268741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 10:04:44.269346 ==
8845 10:04:44.272076 DQS Delay:
8846 10:04:44.272646 DQS0 = 0, DQS1 = 0
8847 10:04:44.275268 DQM Delay:
8848 10:04:44.275832 DQM0 = 138, DQM1 = 130
8849 10:04:44.278885 DQ Delay:
8850 10:04:44.281794 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8851 10:04:44.284954 DQ4 =139, DQ5 =151, DQ6 =147, DQ7 =135
8852 10:04:44.288443 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =127
8853 10:04:44.292015 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8854 10:04:44.292533
8855 10:04:44.292955
8856 10:04:44.293301 ==
8857 10:04:44.294632 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 10:04:44.298149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 10:04:44.298615 ==
8860 10:04:44.298979
8861 10:04:44.299319
8862 10:04:44.301630 TX Vref Scan disable
8863 10:04:44.304880 == TX Byte 0 ==
8864 10:04:44.308002 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8865 10:04:44.311936 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8866 10:04:44.314751 == TX Byte 1 ==
8867 10:04:44.318241 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8868 10:04:44.321602 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8869 10:04:44.322087 ==
8870 10:04:44.324884 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 10:04:44.330972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 10:04:44.331394 ==
8873 10:04:44.342701
8874 10:04:44.345874 TX Vref early break, caculate TX vref
8875 10:04:44.349166 TX Vref=16, minBit 13, minWin=22, winSum=387
8876 10:04:44.352603 TX Vref=18, minBit 0, minWin=24, winSum=397
8877 10:04:44.355668 TX Vref=20, minBit 13, minWin=24, winSum=404
8878 10:04:44.358700 TX Vref=22, minBit 13, minWin=24, winSum=415
8879 10:04:44.365416 TX Vref=24, minBit 13, minWin=25, winSum=422
8880 10:04:44.369052 TX Vref=26, minBit 12, minWin=25, winSum=431
8881 10:04:44.372484 TX Vref=28, minBit 0, minWin=26, winSum=430
8882 10:04:44.375378 TX Vref=30, minBit 9, minWin=25, winSum=421
8883 10:04:44.378732 TX Vref=32, minBit 0, minWin=25, winSum=411
8884 10:04:44.385259 TX Vref=34, minBit 0, minWin=24, winSum=406
8885 10:04:44.388421 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8886 10:04:44.388932
8887 10:04:44.392066 Final TX Range 0 Vref 28
8888 10:04:44.392615
8889 10:04:44.393115 ==
8890 10:04:44.395099 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 10:04:44.398429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 10:04:44.398954 ==
8893 10:04:44.401896
8894 10:04:44.402326
8895 10:04:44.402761 TX Vref Scan disable
8896 10:04:44.408098 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8897 10:04:44.408517 == TX Byte 0 ==
8898 10:04:44.411398 u2DelayCellOfst[0]=13 cells (4 PI)
8899 10:04:44.414611 u2DelayCellOfst[1]=10 cells (3 PI)
8900 10:04:44.418045 u2DelayCellOfst[2]=0 cells (0 PI)
8901 10:04:44.421529 u2DelayCellOfst[3]=3 cells (1 PI)
8902 10:04:44.424417 u2DelayCellOfst[4]=3 cells (1 PI)
8903 10:04:44.427722 u2DelayCellOfst[5]=16 cells (5 PI)
8904 10:04:44.431047 u2DelayCellOfst[6]=16 cells (5 PI)
8905 10:04:44.434639 u2DelayCellOfst[7]=3 cells (1 PI)
8906 10:04:44.437771 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8907 10:04:44.441048 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8908 10:04:44.444590 == TX Byte 1 ==
8909 10:04:44.447763 u2DelayCellOfst[8]=0 cells (0 PI)
8910 10:04:44.451303 u2DelayCellOfst[9]=0 cells (0 PI)
8911 10:04:44.454502 u2DelayCellOfst[10]=6 cells (2 PI)
8912 10:04:44.457830 u2DelayCellOfst[11]=3 cells (1 PI)
8913 10:04:44.461203 u2DelayCellOfst[12]=13 cells (4 PI)
8914 10:04:44.461625 u2DelayCellOfst[13]=10 cells (3 PI)
8915 10:04:44.464864 u2DelayCellOfst[14]=16 cells (5 PI)
8916 10:04:44.468405 u2DelayCellOfst[15]=13 cells (4 PI)
8917 10:04:44.474597 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8918 10:04:44.477767 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8919 10:04:44.478238 DramC Write-DBI on
8920 10:04:44.480921 ==
8921 10:04:44.484371 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 10:04:44.487550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 10:04:44.488020 ==
8924 10:04:44.488390
8925 10:04:44.488734
8926 10:04:44.491229 TX Vref Scan disable
8927 10:04:44.491694 == TX Byte 0 ==
8928 10:04:44.497743 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8929 10:04:44.498210 == TX Byte 1 ==
8930 10:04:44.500696 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8931 10:04:44.504105 DramC Write-DBI off
8932 10:04:44.504576
8933 10:04:44.504995 [DATLAT]
8934 10:04:44.507321 Freq=1600, CH1 RK1
8935 10:04:44.507788
8936 10:04:44.508158 DATLAT Default: 0xf
8937 10:04:44.510910 0, 0xFFFF, sum = 0
8938 10:04:44.511367 1, 0xFFFF, sum = 0
8939 10:04:44.513927 2, 0xFFFF, sum = 0
8940 10:04:44.514355 3, 0xFFFF, sum = 0
8941 10:04:44.517867 4, 0xFFFF, sum = 0
8942 10:04:44.518413 5, 0xFFFF, sum = 0
8943 10:04:44.521052 6, 0xFFFF, sum = 0
8944 10:04:44.523976 7, 0xFFFF, sum = 0
8945 10:04:44.524428 8, 0xFFFF, sum = 0
8946 10:04:44.527674 9, 0xFFFF, sum = 0
8947 10:04:44.528207 10, 0xFFFF, sum = 0
8948 10:04:44.530798 11, 0xFFFF, sum = 0
8949 10:04:44.531384 12, 0xFFFF, sum = 0
8950 10:04:44.533948 13, 0xFFFF, sum = 0
8951 10:04:44.534427 14, 0x0, sum = 1
8952 10:04:44.537073 15, 0x0, sum = 2
8953 10:04:44.537584 16, 0x0, sum = 3
8954 10:04:44.540546 17, 0x0, sum = 4
8955 10:04:44.541113 best_step = 15
8956 10:04:44.541520
8957 10:04:44.541872 ==
8958 10:04:44.543683 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 10:04:44.546954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 10:04:44.550422 ==
8961 10:04:44.550950 RX Vref Scan: 0
8962 10:04:44.551293
8963 10:04:44.553556 RX Vref 0 -> 0, step: 1
8964 10:04:44.554006
8965 10:04:44.554449 RX Delay 11 -> 252, step: 4
8966 10:04:44.561213 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8967 10:04:44.564303 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8968 10:04:44.567548 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
8969 10:04:44.571054 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8970 10:04:44.574343 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8971 10:04:44.580834 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8972 10:04:44.583978 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8973 10:04:44.587366 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8974 10:04:44.590608 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8975 10:04:44.593991 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8976 10:04:44.600612 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8977 10:04:44.603923 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8978 10:04:44.607040 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8979 10:04:44.610829 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8980 10:04:44.613985 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8981 10:04:44.620418 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8982 10:04:44.620883 ==
8983 10:04:44.623702 Dram Type= 6, Freq= 0, CH_1, rank 1
8984 10:04:44.626904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8985 10:04:44.627345 ==
8986 10:04:44.627791 DQS Delay:
8987 10:04:44.630041 DQS0 = 0, DQS1 = 0
8988 10:04:44.630479 DQM Delay:
8989 10:04:44.633535 DQM0 = 134, DQM1 = 129
8990 10:04:44.633973 DQ Delay:
8991 10:04:44.637123 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =132
8992 10:04:44.640295 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8993 10:04:44.644465 DQ8 =112, DQ9 =118, DQ10 =128, DQ11 =124
8994 10:04:44.649649 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =140
8995 10:04:44.650320
8996 10:04:44.650677
8997 10:04:44.650995
8998 10:04:44.651352 [DramC_TX_OE_Calibration] TA2
8999 10:04:44.653117 Original DQ_B0 (3 6) =30, OEN = 27
9000 10:04:44.656585 Original DQ_B1 (3 6) =30, OEN = 27
9001 10:04:44.659661 24, 0x0, End_B0=24 End_B1=24
9002 10:04:44.663417 25, 0x0, End_B0=25 End_B1=25
9003 10:04:44.666444 26, 0x0, End_B0=26 End_B1=26
9004 10:04:44.669914 27, 0x0, End_B0=27 End_B1=27
9005 10:04:44.670443 28, 0x0, End_B0=28 End_B1=28
9006 10:04:44.673412 29, 0x0, End_B0=29 End_B1=29
9007 10:04:44.676241 30, 0x0, End_B0=30 End_B1=30
9008 10:04:44.679818 31, 0x4545, End_B0=30 End_B1=30
9009 10:04:44.683245 Byte0 end_step=30 best_step=27
9010 10:04:44.683831 Byte1 end_step=30 best_step=27
9011 10:04:44.686300 Byte0 TX OE(2T, 0.5T) = (3, 3)
9012 10:04:44.689634 Byte1 TX OE(2T, 0.5T) = (3, 3)
9013 10:04:44.690102
9014 10:04:44.690469
9015 10:04:44.699453 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b05, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
9016 10:04:44.699927 CH1 RK1: MR19=303, MR18=1B05
9017 10:04:44.706131 CH1_RK1: MR19=0x303, MR18=0x1B05, DQSOSC=396, MR23=63, INC=23, DEC=15
9018 10:04:44.709330 [RxdqsGatingPostProcess] freq 1600
9019 10:04:44.716122 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9020 10:04:44.719544 best DQS0 dly(2T, 0.5T) = (1, 1)
9021 10:04:44.722582 best DQS1 dly(2T, 0.5T) = (1, 1)
9022 10:04:44.726195 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9023 10:04:44.729517 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9024 10:04:44.732380 best DQS0 dly(2T, 0.5T) = (1, 1)
9025 10:04:44.732967 best DQS1 dly(2T, 0.5T) = (1, 1)
9026 10:04:44.735667 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9027 10:04:44.739589 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9028 10:04:44.743215 Pre-setting of DQS Precalculation
9029 10:04:44.748846 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9030 10:04:44.755914 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9031 10:04:44.762342 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9032 10:04:44.762972
9033 10:04:44.763505
9034 10:04:44.765409 [Calibration Summary] 3200 Mbps
9035 10:04:44.765880 CH 0, Rank 0
9036 10:04:44.769196 SW Impedance : PASS
9037 10:04:44.772146 DUTY Scan : NO K
9038 10:04:44.772615 ZQ Calibration : PASS
9039 10:04:44.775342 Jitter Meter : NO K
9040 10:04:44.778613 CBT Training : PASS
9041 10:04:44.779291 Write leveling : PASS
9042 10:04:44.782267 RX DQS gating : PASS
9043 10:04:44.785809 RX DQ/DQS(RDDQC) : PASS
9044 10:04:44.786267 TX DQ/DQS : PASS
9045 10:04:44.789152 RX DATLAT : PASS
9046 10:04:44.792322 RX DQ/DQS(Engine): PASS
9047 10:04:44.792976 TX OE : PASS
9048 10:04:44.795423 All Pass.
9049 10:04:44.795846
9050 10:04:44.796183 CH 0, Rank 1
9051 10:04:44.798623 SW Impedance : PASS
9052 10:04:44.799045 DUTY Scan : NO K
9053 10:04:44.802357 ZQ Calibration : PASS
9054 10:04:44.805457 Jitter Meter : NO K
9055 10:04:44.806050 CBT Training : PASS
9056 10:04:44.808760 Write leveling : PASS
9057 10:04:44.811937 RX DQS gating : PASS
9058 10:04:44.812356 RX DQ/DQS(RDDQC) : PASS
9059 10:04:44.814813 TX DQ/DQS : PASS
9060 10:04:44.814896 RX DATLAT : PASS
9061 10:04:44.818178 RX DQ/DQS(Engine): PASS
9062 10:04:44.821614 TX OE : PASS
9063 10:04:44.821697 All Pass.
9064 10:04:44.821763
9065 10:04:44.825030 CH 1, Rank 0
9066 10:04:44.825113 SW Impedance : PASS
9067 10:04:44.828028 DUTY Scan : NO K
9068 10:04:44.828110 ZQ Calibration : PASS
9069 10:04:44.831433 Jitter Meter : NO K
9070 10:04:44.834583 CBT Training : PASS
9071 10:04:44.834665 Write leveling : PASS
9072 10:04:44.837803 RX DQS gating : PASS
9073 10:04:44.841145 RX DQ/DQS(RDDQC) : PASS
9074 10:04:44.841261 TX DQ/DQS : PASS
9075 10:04:44.844319 RX DATLAT : PASS
9076 10:04:44.848041 RX DQ/DQS(Engine): PASS
9077 10:04:44.848144 TX OE : PASS
9078 10:04:44.851616 All Pass.
9079 10:04:44.851794
9080 10:04:44.851888 CH 1, Rank 1
9081 10:04:44.854301 SW Impedance : PASS
9082 10:04:44.854448 DUTY Scan : NO K
9083 10:04:44.857869 ZQ Calibration : PASS
9084 10:04:44.861191 Jitter Meter : NO K
9085 10:04:44.861315 CBT Training : PASS
9086 10:04:44.864447 Write leveling : PASS
9087 10:04:44.867717 RX DQS gating : PASS
9088 10:04:44.867852 RX DQ/DQS(RDDQC) : PASS
9089 10:04:44.871037 TX DQ/DQS : PASS
9090 10:04:44.874008 RX DATLAT : PASS
9091 10:04:44.874164 RX DQ/DQS(Engine): PASS
9092 10:04:44.877470 TX OE : PASS
9093 10:04:44.877627 All Pass.
9094 10:04:44.877776
9095 10:04:44.880810 DramC Write-DBI on
9096 10:04:44.884218 PER_BANK_REFRESH: Hybrid Mode
9097 10:04:44.884403 TX_TRACKING: ON
9098 10:04:44.894194 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9099 10:04:44.900905 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9100 10:04:44.907371 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9101 10:04:44.914321 [FAST_K] Save calibration result to emmc
9102 10:04:44.914750 sync common calibartion params.
9103 10:04:44.917181 sync cbt_mode0:1, 1:1
9104 10:04:44.920676 dram_init: ddr_geometry: 2
9105 10:04:44.921147 dram_init: ddr_geometry: 2
9106 10:04:44.923885 dram_init: ddr_geometry: 2
9107 10:04:44.927546 0:dram_rank_size:100000000
9108 10:04:44.930593 1:dram_rank_size:100000000
9109 10:04:44.933549 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9110 10:04:44.937128 DFS_SHUFFLE_HW_MODE: ON
9111 10:04:44.941273 dramc_set_vcore_voltage set vcore to 725000
9112 10:04:44.943768 Read voltage for 1600, 0
9113 10:04:44.944295 Vio18 = 0
9114 10:04:44.947380 Vcore = 725000
9115 10:04:44.947811 Vdram = 0
9116 10:04:44.948153 Vddq = 0
9117 10:04:44.948472 Vmddr = 0
9118 10:04:44.950475 switch to 3200 Mbps bootup
9119 10:04:44.953677 [DramcRunTimeConfig]
9120 10:04:44.954096 PHYPLL
9121 10:04:44.954434 DPM_CONTROL_AFTERK: ON
9122 10:04:44.956985 PER_BANK_REFRESH: ON
9123 10:04:44.960109 REFRESH_OVERHEAD_REDUCTION: ON
9124 10:04:44.963623 CMD_PICG_NEW_MODE: OFF
9125 10:04:44.964215 XRTWTW_NEW_MODE: ON
9126 10:04:44.966994 XRTRTR_NEW_MODE: ON
9127 10:04:44.967423 TX_TRACKING: ON
9128 10:04:44.970127 RDSEL_TRACKING: OFF
9129 10:04:44.970554 DQS Precalculation for DVFS: ON
9130 10:04:44.973379 RX_TRACKING: OFF
9131 10:04:44.973806 HW_GATING DBG: ON
9132 10:04:44.976804 ZQCS_ENABLE_LP4: ON
9133 10:04:44.980154 RX_PICG_NEW_MODE: ON
9134 10:04:44.980577 TX_PICG_NEW_MODE: ON
9135 10:04:44.983357 ENABLE_RX_DCM_DPHY: ON
9136 10:04:44.986529 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9137 10:04:44.987075 DUMMY_READ_FOR_TRACKING: OFF
9138 10:04:44.989906 !!! SPM_CONTROL_AFTERK: OFF
9139 10:04:44.993246 !!! SPM could not control APHY
9140 10:04:44.996895 IMPEDANCE_TRACKING: ON
9141 10:04:44.997422 TEMP_SENSOR: ON
9142 10:04:44.999996 HW_SAVE_FOR_SR: OFF
9143 10:04:45.002980 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9144 10:04:45.006413 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9145 10:04:45.006843 Read ODT Tracking: ON
9146 10:04:45.010082 Refresh Rate DeBounce: ON
9147 10:04:45.013093 DFS_NO_QUEUE_FLUSH: ON
9148 10:04:45.016176 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9149 10:04:45.016685 ENABLE_DFS_RUNTIME_MRW: OFF
9150 10:04:45.019763 DDR_RESERVE_NEW_MODE: ON
9151 10:04:45.023224 MR_CBT_SWITCH_FREQ: ON
9152 10:04:45.023744 =========================
9153 10:04:45.042879 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9154 10:04:45.046126 dram_init: ddr_geometry: 2
9155 10:04:45.064509 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9156 10:04:45.067381 dram_init: dram init end (result: 0)
9157 10:04:45.074788 DRAM-K: Full calibration passed in 24511 msecs
9158 10:04:45.077505 MRC: failed to locate region type 0.
9159 10:04:45.077945 DRAM rank0 size:0x100000000,
9160 10:04:45.080789 DRAM rank1 size=0x100000000
9161 10:04:45.091100 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9162 10:04:45.097886 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9163 10:04:45.104078 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9164 10:04:45.113834 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9165 10:04:45.114301 DRAM rank0 size:0x100000000,
9166 10:04:45.117057 DRAM rank1 size=0x100000000
9167 10:04:45.117510 CBMEM:
9168 10:04:45.120828 IMD: root @ 0xfffff000 254 entries.
9169 10:04:45.123837 IMD: root @ 0xffffec00 62 entries.
9170 10:04:45.127075 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9171 10:04:45.133921 WARNING: RO_VPD is uninitialized or empty.
9172 10:04:45.136969 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9173 10:04:45.144429 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9174 10:04:45.157426 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9175 10:04:45.168860 BS: romstage times (exec / console): total (unknown) / 24010 ms
9176 10:04:45.169399
9177 10:04:45.169748
9178 10:04:45.178390 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9179 10:04:45.181929 ARM64: Exception handlers installed.
9180 10:04:45.185467 ARM64: Testing exception
9181 10:04:45.188752 ARM64: Done test exception
9182 10:04:45.189213 Enumerating buses...
9183 10:04:45.191764 Show all devs... Before device enumeration.
9184 10:04:45.194987 Root Device: enabled 1
9185 10:04:45.198634 CPU_CLUSTER: 0: enabled 1
9186 10:04:45.199196 CPU: 00: enabled 1
9187 10:04:45.202157 Compare with tree...
9188 10:04:45.202687 Root Device: enabled 1
9189 10:04:45.205224 CPU_CLUSTER: 0: enabled 1
9190 10:04:45.208483 CPU: 00: enabled 1
9191 10:04:45.209092 Root Device scanning...
9192 10:04:45.211881 scan_static_bus for Root Device
9193 10:04:45.215485 CPU_CLUSTER: 0 enabled
9194 10:04:45.218323 scan_static_bus for Root Device done
9195 10:04:45.221760 scan_bus: bus Root Device finished in 8 msecs
9196 10:04:45.222194 done
9197 10:04:45.228675 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9198 10:04:45.232213 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9199 10:04:45.238179 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9200 10:04:45.241550 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9201 10:04:45.245053 Allocating resources...
9202 10:04:45.248233 Reading resources...
9203 10:04:45.251425 Root Device read_resources bus 0 link: 0
9204 10:04:45.254812 DRAM rank0 size:0x100000000,
9205 10:04:45.255427 DRAM rank1 size=0x100000000
9206 10:04:45.257676 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9207 10:04:45.261136 CPU: 00 missing read_resources
9208 10:04:45.268091 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9209 10:04:45.271132 Root Device read_resources bus 0 link: 0 done
9210 10:04:45.271605 Done reading resources.
9211 10:04:45.277832 Show resources in subtree (Root Device)...After reading.
9212 10:04:45.281108 Root Device child on link 0 CPU_CLUSTER: 0
9213 10:04:45.284649 CPU_CLUSTER: 0 child on link 0 CPU: 00
9214 10:04:45.294358 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9215 10:04:45.294927 CPU: 00
9216 10:04:45.297653 Root Device assign_resources, bus 0 link: 0
9217 10:04:45.301164 CPU_CLUSTER: 0 missing set_resources
9218 10:04:45.307800 Root Device assign_resources, bus 0 link: 0 done
9219 10:04:45.308236 Done setting resources.
9220 10:04:45.314163 Show resources in subtree (Root Device)...After assigning values.
9221 10:04:45.317738 Root Device child on link 0 CPU_CLUSTER: 0
9222 10:04:45.321017 CPU_CLUSTER: 0 child on link 0 CPU: 00
9223 10:04:45.330745 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9224 10:04:45.331166 CPU: 00
9225 10:04:45.333767 Done allocating resources.
9226 10:04:45.340967 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9227 10:04:45.341390 Enabling resources...
9228 10:04:45.341724 done.
9229 10:04:45.347603 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9230 10:04:45.350786 Initializing devices...
9231 10:04:45.351206 Root Device init
9232 10:04:45.353697 init hardware done!
9233 10:04:45.354115 0x00000018: ctrlr->caps
9234 10:04:45.357441 52.000 MHz: ctrlr->f_max
9235 10:04:45.360179 0.400 MHz: ctrlr->f_min
9236 10:04:45.360620 0x40ff8080: ctrlr->voltages
9237 10:04:45.363528 sclk: 390625
9238 10:04:45.363953 Bus Width = 1
9239 10:04:45.364294 sclk: 390625
9240 10:04:45.367115 Bus Width = 1
9241 10:04:45.370448 Early init status = 3
9242 10:04:45.373659 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9243 10:04:45.376704 in-header: 03 fc 00 00 01 00 00 00
9244 10:04:45.380487 in-data: 00
9245 10:04:45.383524 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9246 10:04:45.387681 in-header: 03 fd 00 00 00 00 00 00
9247 10:04:45.390877 in-data:
9248 10:04:45.394161 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9249 10:04:45.397306 in-header: 03 fc 00 00 01 00 00 00
9250 10:04:45.400863 in-data: 00
9251 10:04:45.404412 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9252 10:04:45.408525 in-header: 03 fd 00 00 00 00 00 00
9253 10:04:45.412138 in-data:
9254 10:04:45.415873 [SSUSB] Setting up USB HOST controller...
9255 10:04:45.418825 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9256 10:04:45.422022 [SSUSB] phy power-on done.
9257 10:04:45.425245 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9258 10:04:45.431999 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9259 10:04:45.435014 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9260 10:04:45.441614 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9261 10:04:45.448517 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9262 10:04:45.454941 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9263 10:04:45.461786 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9264 10:04:45.468326 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9265 10:04:45.471406 SPM: binary array size = 0x9dc
9266 10:04:45.474974 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9267 10:04:45.481428 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9268 10:04:45.488041 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9269 10:04:45.494891 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9270 10:04:45.498041 configure_display: Starting display init
9271 10:04:45.532040 anx7625_power_on_init: Init interface.
9272 10:04:45.535529 anx7625_disable_pd_protocol: Disabled PD feature.
9273 10:04:45.538270 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9274 10:04:45.566297 anx7625_start_dp_work: Secure OCM version=00
9275 10:04:45.569520 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9276 10:04:45.584372 sp_tx_get_edid_block: EDID Block = 1
9277 10:04:45.686736 Extracted contents:
9278 10:04:45.690190 header: 00 ff ff ff ff ff ff 00
9279 10:04:45.693783 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9280 10:04:45.697345 version: 01 04
9281 10:04:45.700137 basic params: 95 1f 11 78 0a
9282 10:04:45.703583 chroma info: 76 90 94 55 54 90 27 21 50 54
9283 10:04:45.706807 established: 00 00 00
9284 10:04:45.713905 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9285 10:04:45.716812 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9286 10:04:45.723501 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9287 10:04:45.730510 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9288 10:04:45.736422 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9289 10:04:45.739920 extensions: 00
9290 10:04:45.740382 checksum: fb
9291 10:04:45.740723
9292 10:04:45.742868 Manufacturer: IVO Model 57d Serial Number 0
9293 10:04:45.746624 Made week 0 of 2020
9294 10:04:45.749895 EDID version: 1.4
9295 10:04:45.750334 Digital display
9296 10:04:45.753395 6 bits per primary color channel
9297 10:04:45.753819 DisplayPort interface
9298 10:04:45.756184 Maximum image size: 31 cm x 17 cm
9299 10:04:45.759662 Gamma: 220%
9300 10:04:45.760076 Check DPMS levels
9301 10:04:45.763287 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9302 10:04:45.769291 First detailed timing is preferred timing
9303 10:04:45.769517 Established timings supported:
9304 10:04:45.772821 Standard timings supported:
9305 10:04:45.776248 Detailed timings
9306 10:04:45.779100 Hex of detail: 383680a07038204018303c0035ae10000019
9307 10:04:45.785764 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9308 10:04:45.789307 0780 0798 07c8 0820 hborder 0
9309 10:04:45.792958 0438 043b 0447 0458 vborder 0
9310 10:04:45.795611 -hsync -vsync
9311 10:04:45.795689 Did detailed timing
9312 10:04:45.802004 Hex of detail: 000000000000000000000000000000000000
9313 10:04:45.805384 Manufacturer-specified data, tag 0
9314 10:04:45.809012 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9315 10:04:45.811863 ASCII string: InfoVision
9316 10:04:45.815236 Hex of detail: 000000fe00523134304e574635205248200a
9317 10:04:45.818836 ASCII string: R140NWF5 RH
9318 10:04:45.818907 Checksum
9319 10:04:45.822207 Checksum: 0xfb (valid)
9320 10:04:45.825261 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9321 10:04:45.828406 DSI data_rate: 832800000 bps
9322 10:04:45.835157 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9323 10:04:45.838607 anx7625_parse_edid: pixelclock(138800).
9324 10:04:45.841853 hactive(1920), hsync(48), hfp(24), hbp(88)
9325 10:04:45.844907 vactive(1080), vsync(12), vfp(3), vbp(17)
9326 10:04:45.848036 anx7625_dsi_config: config dsi.
9327 10:04:45.854947 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9328 10:04:45.868605 anx7625_dsi_config: success to config DSI
9329 10:04:45.872148 anx7625_dp_start: MIPI phy setup OK.
9330 10:04:45.875431 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9331 10:04:45.878884 mtk_ddp_mode_set invalid vrefresh 60
9332 10:04:45.882297 main_disp_path_setup
9333 10:04:45.882381 ovl_layer_smi_id_en
9334 10:04:45.885443 ovl_layer_smi_id_en
9335 10:04:45.885535 ccorr_config
9336 10:04:45.885608 aal_config
9337 10:04:45.888325 gamma_config
9338 10:04:45.888416 postmask_config
9339 10:04:45.891519 dither_config
9340 10:04:45.895310 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9341 10:04:45.901771 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9342 10:04:45.905093 Root Device init finished in 551 msecs
9343 10:04:45.908574 CPU_CLUSTER: 0 init
9344 10:04:45.915009 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9345 10:04:45.922056 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9346 10:04:45.922269 APU_MBOX 0x190000b0 = 0x10001
9347 10:04:45.924949 APU_MBOX 0x190001b0 = 0x10001
9348 10:04:45.928286 APU_MBOX 0x190005b0 = 0x10001
9349 10:04:45.931737 APU_MBOX 0x190006b0 = 0x10001
9350 10:04:45.938527 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9351 10:04:45.948318 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9352 10:04:45.960355 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9353 10:04:45.967277 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9354 10:04:45.979154 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9355 10:04:45.988231 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9356 10:04:45.991374 CPU_CLUSTER: 0 init finished in 81 msecs
9357 10:04:45.994894 Devices initialized
9358 10:04:45.997919 Show all devs... After init.
9359 10:04:45.998472 Root Device: enabled 1
9360 10:04:46.001692 CPU_CLUSTER: 0: enabled 1
9361 10:04:46.004835 CPU: 00: enabled 1
9362 10:04:46.008078 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9363 10:04:46.011244 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9364 10:04:46.014476 ELOG: NV offset 0x57f000 size 0x1000
9365 10:04:46.021265 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9366 10:04:46.027654 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9367 10:04:46.030692 ELOG: Event(17) added with size 13 at 2023-06-10 10:04:43 UTC
9368 10:04:46.034319 out: cmd=0x121: 03 db 21 01 00 00 00 00
9369 10:04:46.038131 in-header: 03 2a 00 00 2c 00 00 00
9370 10:04:46.051324 in-data: 35 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9371 10:04:46.057639 ELOG: Event(A1) added with size 10 at 2023-06-10 10:04:43 UTC
9372 10:04:46.064498 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9373 10:04:46.071146 ELOG: Event(A0) added with size 9 at 2023-06-10 10:04:43 UTC
9374 10:04:46.074379 elog_add_boot_reason: Logged dev mode boot
9375 10:04:46.077675 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9376 10:04:46.080864 Finalize devices...
9377 10:04:46.081304 Devices finalized
9378 10:04:46.087395 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9379 10:04:46.091014 Writing coreboot table at 0xffe64000
9380 10:04:46.094031 0. 000000000010a000-0000000000113fff: RAMSTAGE
9381 10:04:46.097459 1. 0000000040000000-00000000400fffff: RAM
9382 10:04:46.104174 2. 0000000040100000-000000004032afff: RAMSTAGE
9383 10:04:46.107710 3. 000000004032b000-00000000545fffff: RAM
9384 10:04:46.110531 4. 0000000054600000-000000005465ffff: BL31
9385 10:04:46.113985 5. 0000000054660000-00000000ffe63fff: RAM
9386 10:04:46.120988 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9387 10:04:46.124013 7. 0000000100000000-000000023fffffff: RAM
9388 10:04:46.127364 Passing 5 GPIOs to payload:
9389 10:04:46.130422 NAME | PORT | POLARITY | VALUE
9390 10:04:46.133886 EC in RW | 0x000000aa | low | undefined
9391 10:04:46.140510 EC interrupt | 0x00000005 | low | undefined
9392 10:04:46.143809 TPM interrupt | 0x000000ab | high | undefined
9393 10:04:46.150204 SD card detect | 0x00000011 | high | undefined
9394 10:04:46.153585 speaker enable | 0x00000093 | high | undefined
9395 10:04:46.157014 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9396 10:04:46.160006 in-header: 03 f9 00 00 02 00 00 00
9397 10:04:46.163517 in-data: 02 00
9398 10:04:46.163944 ADC[4]: Raw value=900663 ID=7
9399 10:04:46.166781 ADC[3]: Raw value=213179 ID=1
9400 10:04:46.169925 RAM Code: 0x71
9401 10:04:46.170208 ADC[6]: Raw value=74502 ID=0
9402 10:04:46.173075 ADC[5]: Raw value=212441 ID=1
9403 10:04:46.176694 SKU Code: 0x1
9404 10:04:46.180530 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9405 10:04:46.183395 coreboot table: 964 bytes.
9406 10:04:46.186284 IMD ROOT 0. 0xfffff000 0x00001000
9407 10:04:46.189660 IMD SMALL 1. 0xffffe000 0x00001000
9408 10:04:46.193425 RO MCACHE 2. 0xffffc000 0x00001104
9409 10:04:46.196595 CONSOLE 3. 0xfff7c000 0x00080000
9410 10:04:46.199301 FMAP 4. 0xfff7b000 0x00000452
9411 10:04:46.202664 TIME STAMP 5. 0xfff7a000 0x00000910
9412 10:04:46.205977 VBOOT WORK 6. 0xfff66000 0x00014000
9413 10:04:46.210124 RAMOOPS 7. 0xffe66000 0x00100000
9414 10:04:46.212728 COREBOOT 8. 0xffe64000 0x00002000
9415 10:04:46.212834 IMD small region:
9416 10:04:46.219231 IMD ROOT 0. 0xffffec00 0x00000400
9417 10:04:46.223209 VPD 1. 0xffffeba0 0x0000004c
9418 10:04:46.225740 MMC STATUS 2. 0xffffeb80 0x00000004
9419 10:04:46.229471 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9420 10:04:46.232750 Probing TPM: done!
9421 10:04:46.236231 Connected to device vid:did:rid of 1ae0:0028:00
9422 10:04:46.246235 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9423 10:04:46.249797 Initialized TPM device CR50 revision 0
9424 10:04:46.253029 Checking cr50 for pending updates
9425 10:04:46.257276 Reading cr50 TPM mode
9426 10:04:46.265694 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9427 10:04:46.272478 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9428 10:04:46.312547 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9429 10:04:46.316188 Checking segment from ROM address 0x40100000
9430 10:04:46.319102 Checking segment from ROM address 0x4010001c
9431 10:04:46.326094 Loading segment from ROM address 0x40100000
9432 10:04:46.326178 code (compression=0)
9433 10:04:46.335521 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9434 10:04:46.342195 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9435 10:04:46.342280 it's not compressed!
9436 10:04:46.348909 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9437 10:04:46.355408 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9438 10:04:46.372724 Loading segment from ROM address 0x4010001c
9439 10:04:46.372846 Entry Point 0x80000000
9440 10:04:46.376294 Loaded segments
9441 10:04:46.379641 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9442 10:04:46.386163 Jumping to boot code at 0x80000000(0xffe64000)
9443 10:04:46.392784 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9444 10:04:46.399668 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9445 10:04:46.407158 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9446 10:04:46.410795 Checking segment from ROM address 0x40100000
9447 10:04:46.413917 Checking segment from ROM address 0x4010001c
9448 10:04:46.420624 Loading segment from ROM address 0x40100000
9449 10:04:46.420709 code (compression=1)
9450 10:04:46.427801 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9451 10:04:46.436956 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9452 10:04:46.437041 using LZMA
9453 10:04:46.445571 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9454 10:04:46.452341 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9455 10:04:46.455546 Loading segment from ROM address 0x4010001c
9456 10:04:46.455630 Entry Point 0x54601000
9457 10:04:46.458959 Loaded segments
9458 10:04:46.462360 NOTICE: MT8192 bl31_setup
9459 10:04:46.469453 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9460 10:04:46.472785 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9461 10:04:46.475975 WARNING: region 0:
9462 10:04:46.479134 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9463 10:04:46.479218 WARNING: region 1:
9464 10:04:46.486054 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9465 10:04:46.489338 WARNING: region 2:
9466 10:04:46.492638 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9467 10:04:46.495729 WARNING: region 3:
9468 10:04:46.499304 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9469 10:04:46.502473 WARNING: region 4:
9470 10:04:46.509285 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9471 10:04:46.509369 WARNING: region 5:
9472 10:04:46.512467 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 10:04:46.515858 WARNING: region 6:
9474 10:04:46.519640 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 10:04:46.522350 WARNING: region 7:
9476 10:04:46.525954 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 10:04:46.532371 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9478 10:04:46.535661 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9479 10:04:46.539054 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9480 10:04:46.545393 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9481 10:04:46.548963 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9482 10:04:46.552402 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9483 10:04:46.559253 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9484 10:04:46.562211 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9485 10:04:46.569228 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9486 10:04:46.572118 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9487 10:04:46.575659 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9488 10:04:46.582132 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9489 10:04:46.585600 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9490 10:04:46.588665 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9491 10:04:46.595794 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9492 10:04:46.598715 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9493 10:04:46.605178 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9494 10:04:46.608980 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9495 10:04:46.611913 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9496 10:04:46.618734 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9497 10:04:46.621616 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9498 10:04:46.628692 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9499 10:04:46.632135 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9500 10:04:46.635149 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9501 10:04:46.641873 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9502 10:04:46.645215 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9503 10:04:46.651617 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9504 10:04:46.655135 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9505 10:04:46.658738 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9506 10:04:46.665055 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9507 10:04:46.668385 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9508 10:04:46.674869 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9509 10:04:46.678466 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9510 10:04:46.681841 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9511 10:04:46.685109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9512 10:04:46.691766 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9513 10:04:46.695326 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9514 10:04:46.698667 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9515 10:04:46.701889 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9516 10:04:46.704895 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9517 10:04:46.711660 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9518 10:04:46.715165 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9519 10:04:46.718172 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9520 10:04:46.724798 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9521 10:04:46.728139 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9522 10:04:46.731757 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9523 10:04:46.735049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9524 10:04:46.741639 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9525 10:04:46.744995 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9526 10:04:46.748281 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9527 10:04:46.754662 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9528 10:04:46.758439 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9529 10:04:46.764562 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9530 10:04:46.768668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9531 10:04:46.775011 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9532 10:04:46.778349 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9533 10:04:46.781419 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9534 10:04:46.788242 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9535 10:04:46.791322 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9536 10:04:46.798100 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9537 10:04:46.801498 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9538 10:04:46.807822 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9539 10:04:46.811485 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9540 10:04:46.818000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9541 10:04:46.821328 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9542 10:04:46.824455 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9543 10:04:46.831165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9544 10:04:46.834330 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9545 10:04:46.841247 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9546 10:04:46.844516 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9547 10:04:46.851057 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9548 10:04:46.854209 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9549 10:04:46.857591 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9550 10:04:46.864129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9551 10:04:46.867857 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9552 10:04:46.874355 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9553 10:04:46.877508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9554 10:04:46.884054 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9555 10:04:46.887831 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9556 10:04:46.894132 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9557 10:04:46.897809 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9558 10:04:46.901121 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9559 10:04:46.908069 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9560 10:04:46.911170 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9561 10:04:46.917363 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9562 10:04:46.920716 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9563 10:04:46.927238 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9564 10:04:46.930885 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9565 10:04:46.934589 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9566 10:04:46.940807 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9567 10:04:46.944641 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9568 10:04:46.950886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9569 10:04:46.953994 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9570 10:04:46.960947 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9571 10:04:46.964497 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9572 10:04:46.970899 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9573 10:04:46.974091 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9574 10:04:46.977230 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9575 10:04:46.980887 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9576 10:04:46.987162 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9577 10:04:46.990819 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9578 10:04:46.994279 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9579 10:04:47.000690 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9580 10:04:47.004241 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9581 10:04:47.010395 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9582 10:04:47.013769 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9583 10:04:47.017312 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9584 10:04:47.023729 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9585 10:04:47.026905 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9586 10:04:47.033924 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9587 10:04:47.037682 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9588 10:04:47.040623 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9589 10:04:47.046880 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9590 10:04:47.050533 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9591 10:04:47.057506 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9592 10:04:47.060358 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9593 10:04:47.063892 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9594 10:04:47.068046 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9595 10:04:47.073734 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9596 10:04:47.076961 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9597 10:04:47.080295 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9598 10:04:47.083533 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9599 10:04:47.090065 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9600 10:04:47.093895 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9601 10:04:47.096784 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9602 10:04:47.103791 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9603 10:04:47.106962 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9604 10:04:47.113281 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9605 10:04:47.116567 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9606 10:04:47.120438 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9607 10:04:47.126443 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9608 10:04:47.129873 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9609 10:04:47.136748 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9610 10:04:47.140018 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9611 10:04:47.143564 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9612 10:04:47.150185 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9613 10:04:47.153051 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9614 10:04:47.159855 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9615 10:04:47.163238 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9616 10:04:47.166657 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9617 10:04:47.173287 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9618 10:04:47.176742 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9619 10:04:47.183103 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9620 10:04:47.186422 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9621 10:04:47.189841 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9622 10:04:47.196567 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9623 10:04:47.199858 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9624 10:04:47.203999 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9625 10:04:47.209529 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9626 10:04:47.212825 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9627 10:04:47.219560 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9628 10:04:47.222701 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9629 10:04:47.226146 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9630 10:04:47.232971 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9631 10:04:47.236431 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9632 10:04:47.242741 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9633 10:04:47.246402 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9634 10:04:47.249444 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9635 10:04:47.256270 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9636 10:04:47.260166 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9637 10:04:47.266380 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9638 10:04:47.269527 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9639 10:04:47.272938 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9640 10:04:47.279415 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9641 10:04:47.282891 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9642 10:04:47.289384 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9643 10:04:47.292658 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9644 10:04:47.296073 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9645 10:04:47.302941 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9646 10:04:47.306202 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9647 10:04:47.312256 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9648 10:04:47.315426 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9649 10:04:47.318726 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9650 10:04:47.325160 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9651 10:04:47.328481 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9652 10:04:47.335067 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9653 10:04:47.338278 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9654 10:04:47.341614 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9655 10:04:47.348577 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9656 10:04:47.351556 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9657 10:04:47.357957 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9658 10:04:47.361437 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9659 10:04:47.364738 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9660 10:04:47.371517 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9661 10:04:47.374745 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9662 10:04:47.381335 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9663 10:04:47.384826 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9664 10:04:47.388131 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9665 10:04:47.394711 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9666 10:04:47.397885 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9667 10:04:47.405136 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9668 10:04:47.407891 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9669 10:04:47.411307 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9670 10:04:47.418168 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9671 10:04:47.421361 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9672 10:04:47.427782 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9673 10:04:47.430999 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9674 10:04:47.434406 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9675 10:04:47.441106 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9676 10:04:47.444635 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9677 10:04:47.451111 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9678 10:04:47.454280 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9679 10:04:47.460736 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9680 10:04:47.464282 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9681 10:04:47.467709 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9682 10:04:47.474357 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9683 10:04:47.477463 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9684 10:04:47.484087 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9685 10:04:47.487572 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9686 10:04:47.494020 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9687 10:04:47.498109 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9688 10:04:47.500615 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9689 10:04:47.507419 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9690 10:04:47.510706 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9691 10:04:47.517067 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9692 10:04:47.520279 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9693 10:04:47.524062 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9694 10:04:47.530629 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9695 10:04:47.533796 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9696 10:04:47.540424 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9697 10:04:47.543923 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9698 10:04:47.550445 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9699 10:04:47.553692 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9700 10:04:47.557056 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9701 10:04:47.563877 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9702 10:04:47.567138 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9703 10:04:47.573341 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9704 10:04:47.576592 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9705 10:04:47.580342 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9706 10:04:47.587116 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9707 10:04:47.590193 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9708 10:04:47.593849 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9709 10:04:47.596888 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9710 10:04:47.603764 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9711 10:04:47.606967 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9712 10:04:47.610009 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9713 10:04:47.616951 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9714 10:04:47.619866 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9715 10:04:47.626712 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9716 10:04:47.629960 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9717 10:04:47.633331 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9718 10:04:47.639714 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9719 10:04:47.643345 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9720 10:04:47.646306 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9721 10:04:47.653613 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9722 10:04:47.656626 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9723 10:04:47.662868 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9724 10:04:47.666411 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9725 10:04:47.669469 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9726 10:04:47.675961 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9727 10:04:47.679652 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9728 10:04:47.682792 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9729 10:04:47.689647 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9730 10:04:47.692828 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9731 10:04:47.699146 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9732 10:04:47.702464 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9733 10:04:47.706184 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9734 10:04:47.712987 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9735 10:04:47.715745 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9736 10:04:47.719193 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9737 10:04:47.725818 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9738 10:04:47.729056 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9739 10:04:47.735618 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9740 10:04:47.738879 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9741 10:04:47.742739 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9742 10:04:47.749062 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9743 10:04:47.752602 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9744 10:04:47.755471 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9745 10:04:47.761946 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9746 10:04:47.765331 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9747 10:04:47.768645 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9748 10:04:47.772106 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9749 10:04:47.779085 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9750 10:04:47.781738 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9751 10:04:47.785174 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9752 10:04:47.788299 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9753 10:04:47.795395 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9754 10:04:47.799101 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9755 10:04:47.802090 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9756 10:04:47.804659 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9757 10:04:47.811572 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9758 10:04:47.814789 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9759 10:04:47.818865 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9760 10:04:47.824881 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9761 10:04:47.828062 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9762 10:04:47.835171 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9763 10:04:47.837854 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9764 10:04:47.845211 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9765 10:04:47.848292 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9766 10:04:47.851820 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9767 10:04:47.858496 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9768 10:04:47.861049 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9769 10:04:47.867548 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9770 10:04:47.871188 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9771 10:04:47.874189 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9772 10:04:47.880828 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9773 10:04:47.883688 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9774 10:04:47.890278 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9775 10:04:47.893975 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9776 10:04:47.897345 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9777 10:04:47.903798 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9778 10:04:47.907268 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9779 10:04:47.913797 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9780 10:04:47.917716 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9781 10:04:47.924137 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9782 10:04:47.927212 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9783 10:04:47.930770 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9784 10:04:47.937411 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9785 10:04:47.940557 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9786 10:04:47.947186 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9787 10:04:47.950547 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9788 10:04:47.953573 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9789 10:04:47.960371 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9790 10:04:47.963440 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9791 10:04:47.970515 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9792 10:04:47.973677 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9793 10:04:47.977072 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9794 10:04:47.983365 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9795 10:04:47.986543 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9796 10:04:47.993125 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9797 10:04:47.996640 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9798 10:04:48.003049 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9799 10:04:48.006679 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9800 10:04:48.010010 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9801 10:04:48.016814 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9802 10:04:48.020119 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9803 10:04:48.026253 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9804 10:04:48.029885 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9805 10:04:48.036217 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9806 10:04:48.039683 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9807 10:04:48.043135 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9808 10:04:48.049526 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9809 10:04:48.052513 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9810 10:04:48.059164 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9811 10:04:48.062836 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9812 10:04:48.065859 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9813 10:04:48.072613 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9814 10:04:48.075870 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9815 10:04:48.082768 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9816 10:04:48.085774 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9817 10:04:48.089032 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9818 10:04:48.095595 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9819 10:04:48.098959 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9820 10:04:48.105412 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9821 10:04:48.108568 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9822 10:04:48.115228 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9823 10:04:48.118566 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9824 10:04:48.121878 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9825 10:04:48.128252 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9826 10:04:48.131842 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9827 10:04:48.138219 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9828 10:04:48.141493 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9829 10:04:48.148020 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9830 10:04:48.151574 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9831 10:04:48.154831 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9832 10:04:48.161641 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9833 10:04:48.164795 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9834 10:04:48.171372 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9835 10:04:48.174918 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9836 10:04:48.181563 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9837 10:04:48.184272 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9838 10:04:48.187570 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9839 10:04:48.194278 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9840 10:04:48.197484 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9841 10:04:48.204280 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9842 10:04:48.207638 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9843 10:04:48.214253 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9844 10:04:48.217368 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9845 10:04:48.224436 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9846 10:04:48.227800 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9847 10:04:48.231396 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9848 10:04:48.237442 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9849 10:04:48.241205 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9850 10:04:48.247606 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9851 10:04:48.250841 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9852 10:04:48.257427 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9853 10:04:48.260681 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9854 10:04:48.264146 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9855 10:04:48.270575 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9856 10:04:48.273867 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9857 10:04:48.280978 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9858 10:04:48.283754 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9859 10:04:48.290075 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9860 10:04:48.294058 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9861 10:04:48.300211 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9862 10:04:48.303950 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9863 10:04:48.306896 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9864 10:04:48.313431 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9865 10:04:48.317296 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9866 10:04:48.323719 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9867 10:04:48.326738 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9868 10:04:48.333632 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9869 10:04:48.336723 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9870 10:04:48.340222 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9871 10:04:48.346791 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9872 10:04:48.350112 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9873 10:04:48.356867 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9874 10:04:48.360727 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9875 10:04:48.367109 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9876 10:04:48.370368 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9877 10:04:48.376511 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9878 10:04:48.379927 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9879 10:04:48.383758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9880 10:04:48.389714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9881 10:04:48.393340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9882 10:04:48.399660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9883 10:04:48.403304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9884 10:04:48.409745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9885 10:04:48.413105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9886 10:04:48.419863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9887 10:04:48.423165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9888 10:04:48.429614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9889 10:04:48.432756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9890 10:04:48.439681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9891 10:04:48.442714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9892 10:04:48.446344 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9893 10:04:48.452587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9894 10:04:48.456014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9895 10:04:48.462524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9896 10:04:48.465898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9897 10:04:48.472403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9898 10:04:48.475985 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9899 10:04:48.482722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9900 10:04:48.485935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9901 10:04:48.492320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9902 10:04:48.495894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9903 10:04:48.502380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9904 10:04:48.506079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9905 10:04:48.512059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9906 10:04:48.515917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9907 10:04:48.522527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9908 10:04:48.525529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9909 10:04:48.532526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9910 10:04:48.538716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9911 10:04:48.542212 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9912 10:04:48.542686 INFO: [APUAPC] vio 0
9913 10:04:48.549645 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9914 10:04:48.552729 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9915 10:04:48.556499 INFO: [APUAPC] D0_APC_0: 0x400510
9916 10:04:48.559335 INFO: [APUAPC] D0_APC_1: 0x0
9917 10:04:48.562439 INFO: [APUAPC] D0_APC_2: 0x1540
9918 10:04:48.565729 INFO: [APUAPC] D0_APC_3: 0x0
9919 10:04:48.569069 INFO: [APUAPC] D1_APC_0: 0xffffffff
9920 10:04:48.572577 INFO: [APUAPC] D1_APC_1: 0xffffffff
9921 10:04:48.575578 INFO: [APUAPC] D1_APC_2: 0x3fffff
9922 10:04:48.578910 INFO: [APUAPC] D1_APC_3: 0x0
9923 10:04:48.582486 INFO: [APUAPC] D2_APC_0: 0xffffffff
9924 10:04:48.585438 INFO: [APUAPC] D2_APC_1: 0xffffffff
9925 10:04:48.588904 INFO: [APUAPC] D2_APC_2: 0x3fffff
9926 10:04:48.592181 INFO: [APUAPC] D2_APC_3: 0x0
9927 10:04:48.595534 INFO: [APUAPC] D3_APC_0: 0xffffffff
9928 10:04:48.598641 INFO: [APUAPC] D3_APC_1: 0xffffffff
9929 10:04:48.601942 INFO: [APUAPC] D3_APC_2: 0x3fffff
9930 10:04:48.605037 INFO: [APUAPC] D3_APC_3: 0x0
9931 10:04:48.608553 INFO: [APUAPC] D4_APC_0: 0xffffffff
9932 10:04:48.611984 INFO: [APUAPC] D4_APC_1: 0xffffffff
9933 10:04:48.615542 INFO: [APUAPC] D4_APC_2: 0x3fffff
9934 10:04:48.618265 INFO: [APUAPC] D4_APC_3: 0x0
9935 10:04:48.621628 INFO: [APUAPC] D5_APC_0: 0xffffffff
9936 10:04:48.624751 INFO: [APUAPC] D5_APC_1: 0xffffffff
9937 10:04:48.628264 INFO: [APUAPC] D5_APC_2: 0x3fffff
9938 10:04:48.631471 INFO: [APUAPC] D5_APC_3: 0x0
9939 10:04:48.634712 INFO: [APUAPC] D6_APC_0: 0xffffffff
9940 10:04:48.638109 INFO: [APUAPC] D6_APC_1: 0xffffffff
9941 10:04:48.641484 INFO: [APUAPC] D6_APC_2: 0x3fffff
9942 10:04:48.645035 INFO: [APUAPC] D6_APC_3: 0x0
9943 10:04:48.648255 INFO: [APUAPC] D7_APC_0: 0xffffffff
9944 10:04:48.651530 INFO: [APUAPC] D7_APC_1: 0xffffffff
9945 10:04:48.655195 INFO: [APUAPC] D7_APC_2: 0x3fffff
9946 10:04:48.655630 INFO: [APUAPC] D7_APC_3: 0x0
9947 10:04:48.661132 INFO: [APUAPC] D8_APC_0: 0xffffffff
9948 10:04:48.664297 INFO: [APUAPC] D8_APC_1: 0xffffffff
9949 10:04:48.667816 INFO: [APUAPC] D8_APC_2: 0x3fffff
9950 10:04:48.668273 INFO: [APUAPC] D8_APC_3: 0x0
9951 10:04:48.670957 INFO: [APUAPC] D9_APC_0: 0xffffffff
9952 10:04:48.677623 INFO: [APUAPC] D9_APC_1: 0xffffffff
9953 10:04:48.681148 INFO: [APUAPC] D9_APC_2: 0x3fffff
9954 10:04:48.681576 INFO: [APUAPC] D9_APC_3: 0x0
9955 10:04:48.684089 INFO: [APUAPC] D10_APC_0: 0xffffffff
9956 10:04:48.690823 INFO: [APUAPC] D10_APC_1: 0xffffffff
9957 10:04:48.694143 INFO: [APUAPC] D10_APC_2: 0x3fffff
9958 10:04:48.694254 INFO: [APUAPC] D10_APC_3: 0x0
9959 10:04:48.701047 INFO: [APUAPC] D11_APC_0: 0xffffffff
9960 10:04:48.703666 INFO: [APUAPC] D11_APC_1: 0xffffffff
9961 10:04:48.707390 INFO: [APUAPC] D11_APC_2: 0x3fffff
9962 10:04:48.707474 INFO: [APUAPC] D11_APC_3: 0x0
9963 10:04:48.713683 INFO: [APUAPC] D12_APC_0: 0xffffffff
9964 10:04:48.717793 INFO: [APUAPC] D12_APC_1: 0xffffffff
9965 10:04:48.720195 INFO: [APUAPC] D12_APC_2: 0x3fffff
9966 10:04:48.720280 INFO: [APUAPC] D12_APC_3: 0x0
9967 10:04:48.726966 INFO: [APUAPC] D13_APC_0: 0xffffffff
9968 10:04:48.730291 INFO: [APUAPC] D13_APC_1: 0xffffffff
9969 10:04:48.733539 INFO: [APUAPC] D13_APC_2: 0x3fffff
9970 10:04:48.736890 INFO: [APUAPC] D13_APC_3: 0x0
9971 10:04:48.740071 INFO: [APUAPC] D14_APC_0: 0xffffffff
9972 10:04:48.743716 INFO: [APUAPC] D14_APC_1: 0xffffffff
9973 10:04:48.747191 INFO: [APUAPC] D14_APC_2: 0x3fffff
9974 10:04:48.750372 INFO: [APUAPC] D14_APC_3: 0x0
9975 10:04:48.753787 INFO: [APUAPC] D15_APC_0: 0xffffffff
9976 10:04:48.757118 INFO: [APUAPC] D15_APC_1: 0xffffffff
9977 10:04:48.760462 INFO: [APUAPC] D15_APC_2: 0x3fffff
9978 10:04:48.763403 INFO: [APUAPC] D15_APC_3: 0x0
9979 10:04:48.763486 INFO: [APUAPC] APC_CON: 0x4
9980 10:04:48.766888 INFO: [NOCDAPC] D0_APC_0: 0x0
9981 10:04:48.770255 INFO: [NOCDAPC] D0_APC_1: 0x0
9982 10:04:48.773540 INFO: [NOCDAPC] D1_APC_0: 0x0
9983 10:04:48.776679 INFO: [NOCDAPC] D1_APC_1: 0xfff
9984 10:04:48.780222 INFO: [NOCDAPC] D2_APC_0: 0x0
9985 10:04:48.783223 INFO: [NOCDAPC] D2_APC_1: 0xfff
9986 10:04:48.786541 INFO: [NOCDAPC] D3_APC_0: 0x0
9987 10:04:48.789908 INFO: [NOCDAPC] D3_APC_1: 0xfff
9988 10:04:48.792954 INFO: [NOCDAPC] D4_APC_0: 0x0
9989 10:04:48.793039 INFO: [NOCDAPC] D4_APC_1: 0xfff
9990 10:04:48.797029 INFO: [NOCDAPC] D5_APC_0: 0x0
9991 10:04:48.799667 INFO: [NOCDAPC] D5_APC_1: 0xfff
9992 10:04:48.803031 INFO: [NOCDAPC] D6_APC_0: 0x0
9993 10:04:48.806396 INFO: [NOCDAPC] D6_APC_1: 0xfff
9994 10:04:48.809683 INFO: [NOCDAPC] D7_APC_0: 0x0
9995 10:04:48.813006 INFO: [NOCDAPC] D7_APC_1: 0xfff
9996 10:04:48.816336 INFO: [NOCDAPC] D8_APC_0: 0x0
9997 10:04:48.819668 INFO: [NOCDAPC] D8_APC_1: 0xfff
9998 10:04:48.822821 INFO: [NOCDAPC] D9_APC_0: 0x0
9999 10:04:48.826211 INFO: [NOCDAPC] D9_APC_1: 0xfff
10000 10:04:48.829834 INFO: [NOCDAPC] D10_APC_0: 0x0
10001 10:04:48.829917 INFO: [NOCDAPC] D10_APC_1: 0xfff
10002 10:04:48.832704 INFO: [NOCDAPC] D11_APC_0: 0x0
10003 10:04:48.836714 INFO: [NOCDAPC] D11_APC_1: 0xfff
10004 10:04:48.839765 INFO: [NOCDAPC] D12_APC_0: 0x0
10005 10:04:48.842801 INFO: [NOCDAPC] D12_APC_1: 0xfff
10006 10:04:48.845984 INFO: [NOCDAPC] D13_APC_0: 0x0
10007 10:04:48.849552 INFO: [NOCDAPC] D13_APC_1: 0xfff
10008 10:04:48.852552 INFO: [NOCDAPC] D14_APC_0: 0x0
10009 10:04:48.856049 INFO: [NOCDAPC] D14_APC_1: 0xfff
10010 10:04:48.859408 INFO: [NOCDAPC] D15_APC_0: 0x0
10011 10:04:48.862588 INFO: [NOCDAPC] D15_APC_1: 0xfff
10012 10:04:48.865885 INFO: [NOCDAPC] APC_CON: 0x4
10013 10:04:48.869288 INFO: [APUAPC] set_apusys_apc done
10014 10:04:48.872368 INFO: [DEVAPC] devapc_init done
10015 10:04:48.876024 INFO: GICv3 without legacy support detected.
10016 10:04:48.878994 INFO: ARM GICv3 driver initialized in EL3
10017 10:04:48.882283 INFO: Maximum SPI INTID supported: 639
10018 10:04:48.885761 INFO: BL31: Initializing runtime services
10019 10:04:48.892629 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10020 10:04:48.895998 INFO: SPM: enable CPC mode
10021 10:04:48.902517 INFO: mcdi ready for mcusys-off-idle and system suspend
10022 10:04:48.905963 INFO: BL31: Preparing for EL3 exit to normal world
10023 10:04:48.909047 INFO: Entry point address = 0x80000000
10024 10:04:48.912000 INFO: SPSR = 0x8
10025 10:04:48.917077
10026 10:04:48.917168
10027 10:04:48.917278
10028 10:04:48.920331 Starting depthcharge on Spherion...
10029 10:04:48.920431
10030 10:04:48.920530 Wipe memory regions:
10031 10:04:48.920625
10032 10:04:48.921343 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10033 10:04:48.921470 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10034 10:04:48.921581 Setting prompt string to ['asurada:']
10035 10:04:48.921716 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10036 10:04:48.923657 [0x00000040000000, 0x00000054600000)
10037 10:04:49.046626
10038 10:04:49.047131 [0x00000054660000, 0x00000080000000)
10039 10:04:49.306647
10040 10:04:49.306810 [0x000000821a7280, 0x000000ffe64000)
10041 10:04:50.052419
10042 10:04:50.053024 [0x00000100000000, 0x00000240000000)
10043 10:04:51.942407
10044 10:04:51.945269 Initializing XHCI USB controller at 0x11200000.
10045 10:04:52.983585
10046 10:04:52.986584 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10047 10:04:52.986746
10048 10:04:52.986823
10049 10:04:52.986892
10050 10:04:52.987208 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10052 10:04:53.087751 asurada: tftpboot 192.168.201.1 10670678/tftp-deploy-rou30s_h/kernel/image.itb 10670678/tftp-deploy-rou30s_h/kernel/cmdline
10053 10:04:53.088430 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10054 10:04:53.089014 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10055 10:04:53.093217 tftpboot 192.168.201.1 10670678/tftp-deploy-rou30s_h/kernel/image.itp-deploy-rou30s_h/kernel/cmdline
10056 10:04:53.093701
10057 10:04:53.094166 Waiting for link
10058 10:04:53.254345
10059 10:04:53.254881 R8152: Initializing
10060 10:04:53.255263
10061 10:04:53.256945 Version 9 (ocp_data = 6010)
10062 10:04:53.257416
10063 10:04:53.260624 R8152: Done initializing
10064 10:04:53.261246
10065 10:04:53.261628 Adding net device
10066 10:04:55.204287
10067 10:04:55.204489 done.
10068 10:04:55.204600
10069 10:04:55.204698 MAC: 00:e0:4c:72:2d:d6
10070 10:04:55.204805
10071 10:04:55.207519 Sending DHCP discover... done.
10072 10:04:55.207703
10073 10:04:55.210755 Waiting for reply... done.
10074 10:04:55.210942
10075 10:04:55.214930 Sending DHCP request... done.
10076 10:04:55.215115
10077 10:04:55.215252 Waiting for reply... done.
10078 10:04:55.215349
10079 10:04:55.217711 My ip is 192.168.201.21
10080 10:04:55.217853
10081 10:04:55.220863 The DHCP server ip is 192.168.201.1
10082 10:04:55.220981
10083 10:04:55.224215 TFTP server IP predefined by user: 192.168.201.1
10084 10:04:55.224373
10085 10:04:55.230554 Bootfile predefined by user: 10670678/tftp-deploy-rou30s_h/kernel/image.itb
10086 10:04:55.230729
10087 10:04:55.234831 Sending tftp read request... done.
10088 10:04:55.235006
10089 10:04:55.237269 Waiting for the transfer...
10090 10:04:55.237393
10091 10:04:55.504957 00000000 ################################################################
10092 10:04:55.505117
10093 10:04:55.765153 00080000 ################################################################
10094 10:04:55.765366
10095 10:04:56.025349 00100000 ################################################################
10096 10:04:56.025513
10097 10:04:56.291323 00180000 ################################################################
10098 10:04:56.291493
10099 10:04:56.552333 00200000 ################################################################
10100 10:04:56.552554
10101 10:04:56.812046 00280000 ################################################################
10102 10:04:56.812267
10103 10:04:57.080269 00300000 ################################################################
10104 10:04:57.080480
10105 10:04:57.330578 00380000 ################################################################
10106 10:04:57.330782
10107 10:04:57.595528 00400000 ################################################################
10108 10:04:57.595717
10109 10:04:57.858052 00480000 ################################################################
10110 10:04:57.858255
10111 10:04:58.130450 00500000 ################################################################
10112 10:04:58.130665
10113 10:04:58.401753 00580000 ################################################################
10114 10:04:58.401965
10115 10:04:58.664822 00600000 ################################################################
10116 10:04:58.665069
10117 10:04:58.931287 00680000 ################################################################
10118 10:04:58.931441
10119 10:04:59.189998 00700000 ################################################################
10120 10:04:59.190227
10121 10:04:59.459511 00780000 ################################################################
10122 10:04:59.459752
10123 10:04:59.718928 00800000 ################################################################
10124 10:04:59.719102
10125 10:04:59.984283 00880000 ################################################################
10126 10:04:59.984457
10127 10:05:00.697897 00900000 ################################################################
10128 10:05:00.698479
10129 10:05:00.698811 00980000 ################################################################
10130 10:05:00.699112
10131 10:05:00.908402 00a00000 ################################################################
10132 10:05:00.908634
10133 10:05:01.163931 00a80000 ################################################################
10134 10:05:01.164134
10135 10:05:01.413337 00b00000 ################################################################
10136 10:05:01.413517
10137 10:05:01.667111 00b80000 ################################################################
10138 10:05:01.667341
10139 10:05:01.913923 00c00000 ################################################################
10140 10:05:01.914139
10141 10:05:02.169746 00c80000 ################################################################
10142 10:05:02.170000
10143 10:05:02.425057 00d00000 ################################################################
10144 10:05:02.425213
10145 10:05:02.669161 00d80000 ################################################################
10146 10:05:02.669319
10147 10:05:02.924933 00e00000 ################################################################
10148 10:05:02.925108
10149 10:05:03.181323 00e80000 ################################################################
10150 10:05:03.181493
10151 10:05:03.437856 00f00000 ################################################################
10152 10:05:03.438018
10153 10:05:03.715346 00f80000 ################################################################
10154 10:05:03.715517
10155 10:05:03.997455 01000000 ################################################################
10156 10:05:03.997603
10157 10:05:04.267162 01080000 ################################################################
10158 10:05:04.267344
10159 10:05:04.524161 01100000 ################################################################
10160 10:05:04.524305
10161 10:05:04.784891 01180000 ################################################################
10162 10:05:04.785055
10163 10:05:05.057570 01200000 ################################################################
10164 10:05:05.057722
10165 10:05:05.318163 01280000 ################################################################
10166 10:05:05.318369
10167 10:05:05.575218 01300000 ################################################################
10168 10:05:05.575423
10169 10:05:09.109016 01380000 ################################################################
10170 10:05:09.109236
10171 10:05:09.109387 01400000 ################################################################
10172 10:05:09.109513
10173 10:05:09.109638 01480000 ################################################################
10174 10:05:09.109761
10175 10:05:09.109882 01500000 ################################################################
10176 10:05:09.110001
10177 10:05:09.110151 01580000 ################################################################
10178 10:05:09.110268
10179 10:05:09.110386 01600000 ################################################################
10180 10:05:09.110508
10181 10:05:09.110626 01680000 ################################################################
10182 10:05:09.110744
10183 10:05:09.110862 01700000 ################################################################
10184 10:05:09.110980
10185 10:05:09.111096 01780000 ################################################################
10186 10:05:09.111211
10187 10:05:09.111321 01800000 ################################################################
10188 10:05:09.111452
10189 10:05:09.111578 01880000 ################################################################
10190 10:05:09.111707
10191 10:05:09.111830 01900000 ################################################################
10192 10:05:09.111956
10193 10:05:09.146693 01980000 ################################################################
10194 10:05:09.146924
10195 10:05:09.404382 01a00000 ################################################################
10196 10:05:09.404555
10197 10:05:09.663339 01a80000 ################################################################
10198 10:05:09.663521
10199 10:05:09.922499 01b00000 ################################################################
10200 10:05:09.922653
10201 10:05:10.184692 01b80000 ################################################################
10202 10:05:10.184900
10203 10:05:10.422400 01c00000 ################################################################
10204 10:05:10.422593
10205 10:05:10.681536 01c80000 ################################################################
10206 10:05:10.681700
10207 10:05:10.931891 01d00000 ################################################################
10208 10:05:10.932069
10209 10:05:11.172975 01d80000 ################################################################
10210 10:05:11.173130
10211 10:05:11.411884 01e00000 ################################################################
10212 10:05:11.412084
10213 10:05:11.661229 01e80000 ################################################################
10214 10:05:11.661400
10215 10:05:11.902852 01f00000 ################################################################
10216 10:05:11.903035
10217 10:05:12.152709 01f80000 ################################################################
10218 10:05:12.152880
10219 10:05:12.388527 02000000 ################################################################
10220 10:05:12.388710
10221 10:05:12.622293 02080000 ################################################################
10222 10:05:12.622524
10223 10:05:12.865495 02100000 ################################################################
10224 10:05:12.865677
10225 10:05:13.112779 02180000 ################################################################
10226 10:05:13.112963
10227 10:05:13.354683 02200000 ################################################################
10228 10:05:13.354841
10229 10:05:13.599041 02280000 ################################################################
10230 10:05:13.599205
10231 10:05:13.842043 02300000 ################################################################
10232 10:05:13.842202
10233 10:05:14.089691 02380000 ################################################################
10234 10:05:14.089865
10235 10:05:14.338630 02400000 ################################################################
10236 10:05:14.338783
10237 10:05:14.588619 02480000 ################################################################
10238 10:05:14.588875
10239 10:05:14.833144 02500000 ################################################################
10240 10:05:14.833397
10241 10:05:15.079333 02580000 ################################################################
10242 10:05:15.079499
10243 10:05:15.322575 02600000 ################################################################
10244 10:05:15.322734
10245 10:05:15.563476 02680000 ################################################################
10246 10:05:15.563723
10247 10:05:15.807042 02700000 ################################################################
10248 10:05:15.807233
10249 10:05:16.058783 02780000 ################################################################
10250 10:05:16.058979
10251 10:05:16.303468 02800000 ################################################################
10252 10:05:16.303618
10253 10:05:16.566196 02880000 ################################################################
10254 10:05:16.566386
10255 10:05:16.813690 02900000 ################################################################
10256 10:05:16.813844
10257 10:05:17.051972 02980000 ################################################################
10258 10:05:17.052122
10259 10:05:17.300350 02a00000 ################################################################
10260 10:05:17.300504
10261 10:05:17.535171 02a80000 ################################################################
10262 10:05:17.535322
10263 10:05:17.770946 02b00000 ################################################################
10264 10:05:17.771099
10265 10:05:18.007745 02b80000 ################################################################
10266 10:05:18.007926
10267 10:05:18.244340 02c00000 ################################################################
10268 10:05:18.244566
10269 10:05:18.482507 02c80000 ################################################################
10270 10:05:18.482693
10271 10:05:18.719103 02d00000 ################################################################
10272 10:05:18.719258
10273 10:05:18.962559 02d80000 ################################################################
10274 10:05:18.962709
10275 10:05:19.207361 02e00000 ################################################################
10276 10:05:19.207513
10277 10:05:19.459538 02e80000 ################################################################
10278 10:05:19.459690
10279 10:05:19.698003 02f00000 ################################################################
10280 10:05:19.698196
10281 10:05:19.926416 02f80000 ######################################################### done.
10282 10:05:19.926594
10283 10:05:19.929530 The bootfile was 50268398 bytes long.
10284 10:05:19.929616
10285 10:05:19.933053 Sending tftp read request... done.
10286 10:05:19.933139
10287 10:05:19.936255 Waiting for the transfer...
10288 10:05:19.936340
10289 10:05:19.936406 00000000 # done.
10290 10:05:19.936469
10291 10:05:19.945890 Command line loaded dynamically from TFTP file: 10670678/tftp-deploy-rou30s_h/kernel/cmdline
10292 10:05:19.945978
10293 10:05:19.955868 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10294 10:05:19.955961
10295 10:05:19.956028 Loading FIT.
10296 10:05:19.959292
10297 10:05:19.959376 Image ramdisk-1 has 40132123 bytes.
10298 10:05:19.959442
10299 10:05:19.962728 Image fdt-1 has 46924 bytes.
10300 10:05:19.962811
10301 10:05:19.966088 Image kernel-1 has 10087317 bytes.
10302 10:05:19.966171
10303 10:05:19.975704 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10304 10:05:19.975833
10305 10:05:19.992122 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10306 10:05:19.992311
10307 10:05:19.998798 Choosing best match conf-1 for compat google,spherion-rev2.
10308 10:05:20.002286
10309 10:05:20.006452 Connected to device vid:did:rid of 1ae0:0028:00
10310 10:05:20.013653
10311 10:05:20.017286 tpm_get_response: command 0x17b, return code 0x0
10312 10:05:20.017396
10313 10:05:20.020180 ec_init: CrosEC protocol v3 supported (256, 248)
10314 10:05:20.025035
10315 10:05:20.028263 tpm_cleanup: add release locality here.
10316 10:05:20.028366
10317 10:05:20.028466 Shutting down all USB controllers.
10318 10:05:20.031505
10319 10:05:20.031589 Removing current net device
10320 10:05:20.031656
10321 10:05:20.038254 Exiting depthcharge with code 4 at timestamp: 60426316
10322 10:05:20.038401
10323 10:05:20.041475 LZMA decompressing kernel-1 to 0x821a6718
10324 10:05:20.041560
10325 10:05:20.044735 LZMA decompressing kernel-1 to 0x40000000
10326 10:05:21.312465
10327 10:05:21.313037 jumping to kernel
10328 10:05:21.314421 end: 2.2.4 bootloader-commands (duration 00:00:32) [common]
10329 10:05:21.314934 start: 2.2.5 auto-login-action (timeout 00:03:53) [common]
10330 10:05:21.315319 Setting prompt string to ['Linux version [0-9]']
10331 10:05:21.315675 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10332 10:05:21.316031 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10333 10:05:21.394075
10334 10:05:21.397188 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10335 10:05:21.400600 start: 2.2.5.1 login-action (timeout 00:03:53) [common]
10336 10:05:21.400715 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10337 10:05:21.400831 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10338 10:05:21.400921 Using line separator: #'\n'#
10339 10:05:21.400993 No login prompt set.
10340 10:05:21.401065 Parsing kernel messages
10341 10:05:21.401131 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10342 10:05:21.401247 [login-action] Waiting for messages, (timeout 00:03:53)
10343 10:05:21.420290 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j19381-arm64-gcc-10-defconfig-arm64-chromebook-d6qsg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023
10344 10:05:21.423876 [ 0.000000] random: crng init done
10345 10:05:21.427075 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10346 10:05:21.429770 [ 0.000000] efi: UEFI not found.
10347 10:05:21.440154 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10348 10:05:21.447108 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10349 10:05:21.457129 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10350 10:05:21.466466 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10351 10:05:21.472832 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10352 10:05:21.479756 [ 0.000000] printk: bootconsole [mtk8250] enabled
10353 10:05:21.483037 [ 0.000000] NUMA: No NUMA configuration found
10354 10:05:21.492618 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10355 10:05:21.496541 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10356 10:05:21.499589 [ 0.000000] Zone ranges:
10357 10:05:21.506045 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10358 10:05:21.509401 [ 0.000000] DMA32 empty
10359 10:05:21.516421 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10360 10:05:21.519502 [ 0.000000] Movable zone start for each node
10361 10:05:21.522964 [ 0.000000] Early memory node ranges
10362 10:05:21.529431 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10363 10:05:21.536091 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10364 10:05:21.542926 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10365 10:05:21.549059 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10366 10:05:21.552870 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10367 10:05:21.562220 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10368 10:05:21.617641 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10369 10:05:21.624139 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10370 10:05:21.630617 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10371 10:05:21.634348 [ 0.000000] psci: probing for conduit method from DT.
10372 10:05:21.640853 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10373 10:05:21.643995 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10374 10:05:21.651060 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10375 10:05:21.653904 [ 0.000000] psci: SMC Calling Convention v1.2
10376 10:05:21.660606 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10377 10:05:21.663883 [ 0.000000] Detected VIPT I-cache on CPU0
10378 10:05:21.670812 [ 0.000000] CPU features: detected: GIC system register CPU interface
10379 10:05:21.677172 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10380 10:05:21.683587 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10381 10:05:21.690287 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10382 10:05:21.700519 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10383 10:05:21.706788 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10384 10:05:21.710033 [ 0.000000] alternatives: applying boot alternatives
10385 10:05:21.717031 [ 0.000000] Fallback order for Node 0: 0
10386 10:05:21.723460 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10387 10:05:21.726986 [ 0.000000] Policy zone: Normal
10388 10:05:21.740303 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10389 10:05:21.749894 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10390 10:05:21.759979 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10391 10:05:21.770055 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10392 10:05:21.776448 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10393 10:05:21.779686 <6>[ 0.000000] software IO TLB: area num 8.
10394 10:05:21.836696 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10395 10:05:21.985319 <6>[ 0.000000] Memory: 7933748K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419020K reserved, 32768K cma-reserved)
10396 10:05:21.992089 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10397 10:05:21.998322 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10398 10:05:22.002050 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10399 10:05:22.008584 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10400 10:05:22.015119 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10401 10:05:22.018271 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10402 10:05:22.028298 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10403 10:05:22.034820 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10404 10:05:22.041911 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10405 10:05:22.048185 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10406 10:05:22.051795 <6>[ 0.000000] GICv3: 608 SPIs implemented
10407 10:05:22.054626 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10408 10:05:22.061335 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10409 10:05:22.064632 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10410 10:05:22.071226 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10411 10:05:22.084882 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10412 10:05:22.097528 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10413 10:05:22.104304 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10414 10:05:22.112307 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10415 10:05:22.124723 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10416 10:05:22.131258 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10417 10:05:22.138129 <6>[ 0.009223] Console: colour dummy device 80x25
10418 10:05:22.148234 <6>[ 0.013978] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10419 10:05:22.154583 <6>[ 0.024419] pid_max: default: 32768 minimum: 301
10420 10:05:22.157978 <6>[ 0.029322] LSM: Security Framework initializing
10421 10:05:22.164409 <6>[ 0.034222] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10422 10:05:22.174572 <6>[ 0.042085] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10423 10:05:22.184743 <6>[ 0.051412] cblist_init_generic: Setting adjustable number of callback queues.
10424 10:05:22.188022 <6>[ 0.058864] cblist_init_generic: Setting shift to 3 and lim to 1.
10425 10:05:22.194543 <6>[ 0.065203] cblist_init_generic: Setting shift to 3 and lim to 1.
10426 10:05:22.201277 <6>[ 0.071646] rcu: Hierarchical SRCU implementation.
10427 10:05:22.207582 <6>[ 0.076691] rcu: Max phase no-delay instances is 1000.
10428 10:05:22.214168 <6>[ 0.083748] EFI services will not be available.
10429 10:05:22.217832 <6>[ 0.088719] smp: Bringing up secondary CPUs ...
10430 10:05:22.225693 <6>[ 0.093773] Detected VIPT I-cache on CPU1
10431 10:05:22.232009 <6>[ 0.093847] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10432 10:05:22.238487 <6>[ 0.093877] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10433 10:05:22.241734 <6>[ 0.094207] Detected VIPT I-cache on CPU2
10434 10:05:22.251687 <6>[ 0.094256] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10435 10:05:22.258186 <6>[ 0.094271] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10436 10:05:22.261228 <6>[ 0.094528] Detected VIPT I-cache on CPU3
10437 10:05:22.267939 <6>[ 0.094576] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10438 10:05:22.274521 <6>[ 0.094589] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10439 10:05:22.280924 <6>[ 0.094894] CPU features: detected: Spectre-v4
10440 10:05:22.284431 <6>[ 0.094901] CPU features: detected: Spectre-BHB
10441 10:05:22.287515 <6>[ 0.094906] Detected PIPT I-cache on CPU4
10442 10:05:22.294005 <6>[ 0.094965] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10443 10:05:22.300663 <6>[ 0.094981] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10444 10:05:22.307739 <6>[ 0.095272] Detected PIPT I-cache on CPU5
10445 10:05:22.314409 <6>[ 0.095335] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10446 10:05:22.321098 <6>[ 0.095352] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10447 10:05:22.324589 <6>[ 0.095635] Detected PIPT I-cache on CPU6
10448 10:05:22.330996 <6>[ 0.095701] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10449 10:05:22.340538 <6>[ 0.095717] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10450 10:05:22.343911 <6>[ 0.096019] Detected PIPT I-cache on CPU7
10451 10:05:22.350181 <6>[ 0.096084] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10452 10:05:22.357343 <6>[ 0.096100] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10453 10:05:22.360611 <6>[ 0.096147] smp: Brought up 1 node, 8 CPUs
10454 10:05:22.367079 <6>[ 0.237529] SMP: Total of 8 processors activated.
10455 10:05:22.373944 <6>[ 0.242450] CPU features: detected: 32-bit EL0 Support
10456 10:05:22.380144 <6>[ 0.247813] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10457 10:05:22.387118 <6>[ 0.256614] CPU features: detected: Common not Private translations
10458 10:05:22.393323 <6>[ 0.263130] CPU features: detected: CRC32 instructions
10459 10:05:22.400192 <6>[ 0.268514] CPU features: detected: RCpc load-acquire (LDAPR)
10460 10:05:22.403413 <6>[ 0.274511] CPU features: detected: LSE atomic instructions
10461 10:05:22.410110 <6>[ 0.280292] CPU features: detected: Privileged Access Never
10462 10:05:22.416647 <6>[ 0.286107] CPU features: detected: RAS Extension Support
10463 10:05:22.423639 <6>[ 0.291716] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10464 10:05:22.426907 <6>[ 0.298936] CPU: All CPU(s) started at EL2
10465 10:05:22.433446 <6>[ 0.303252] alternatives: applying system-wide alternatives
10466 10:05:22.443415 <6>[ 0.313971] devtmpfs: initialized
10467 10:05:22.459035 <6>[ 0.322866] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10468 10:05:22.465595 <6>[ 0.332828] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10469 10:05:22.472320 <6>[ 0.340934] pinctrl core: initialized pinctrl subsystem
10470 10:05:22.475422 <6>[ 0.347600] DMI not present or invalid.
10471 10:05:22.482220 <6>[ 0.352005] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10472 10:05:22.492023 <6>[ 0.358868] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10473 10:05:22.498569 <6>[ 0.366449] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10474 10:05:22.508448 <6>[ 0.374677] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10475 10:05:22.511598 <6>[ 0.382924] audit: initializing netlink subsys (disabled)
10476 10:05:22.521511 <5>[ 0.388619] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10477 10:05:22.528114 <6>[ 0.389334] thermal_sys: Registered thermal governor 'step_wise'
10478 10:05:22.534864 <6>[ 0.396586] thermal_sys: Registered thermal governor 'power_allocator'
10479 10:05:22.538163 <6>[ 0.402838] cpuidle: using governor menu
10480 10:05:22.545170 <6>[ 0.413799] NET: Registered PF_QIPCRTR protocol family
10481 10:05:22.551230 <6>[ 0.419271] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10482 10:05:22.557742 <6>[ 0.426376] ASID allocator initialised with 32768 entries
10483 10:05:22.560995 <6>[ 0.432955] Serial: AMBA PL011 UART driver
10484 10:05:22.571449 <4>[ 0.441664] Trying to register duplicate clock ID: 134
10485 10:05:22.626798 <6>[ 0.501006] KASLR enabled
10486 10:05:22.641227 <6>[ 0.508742] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10487 10:05:22.647702 <6>[ 0.515755] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10488 10:05:22.654169 <6>[ 0.522243] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10489 10:05:22.660692 <6>[ 0.529249] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10490 10:05:22.667570 <6>[ 0.535735] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10491 10:05:22.674356 <6>[ 0.542740] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10492 10:05:22.681359 <6>[ 0.549226] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10493 10:05:22.687876 <6>[ 0.556229] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10494 10:05:22.690915 <6>[ 0.563726] ACPI: Interpreter disabled.
10495 10:05:22.699517 <6>[ 0.570126] iommu: Default domain type: Translated
10496 10:05:22.705806 <6>[ 0.575290] iommu: DMA domain TLB invalidation policy: strict mode
10497 10:05:22.709193 <5>[ 0.581950] SCSI subsystem initialized
10498 10:05:22.715671 <6>[ 0.586188] usbcore: registered new interface driver usbfs
10499 10:05:22.722535 <6>[ 0.591916] usbcore: registered new interface driver hub
10500 10:05:22.725727 <6>[ 0.597470] usbcore: registered new device driver usb
10501 10:05:22.733114 <6>[ 0.603586] pps_core: LinuxPPS API ver. 1 registered
10502 10:05:22.743033 <6>[ 0.608777] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10503 10:05:22.745834 <6>[ 0.618120] PTP clock support registered
10504 10:05:22.749094 <6>[ 0.622358] EDAC MC: Ver: 3.0.0
10505 10:05:22.756907 <6>[ 0.627542] FPGA manager framework
10506 10:05:22.763261 <6>[ 0.631221] Advanced Linux Sound Architecture Driver Initialized.
10507 10:05:22.766423 <6>[ 0.637968] vgaarb: loaded
10508 10:05:22.773358 <6>[ 0.641123] clocksource: Switched to clocksource arch_sys_counter
10509 10:05:22.776450 <5>[ 0.647566] VFS: Disk quotas dquot_6.6.0
10510 10:05:22.782991 <6>[ 0.651750] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10511 10:05:22.786151 <6>[ 0.658939] pnp: PnP ACPI: disabled
10512 10:05:22.794487 <6>[ 0.665629] NET: Registered PF_INET protocol family
10513 10:05:22.801033 <6>[ 0.670908] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10514 10:05:22.815441 <6>[ 0.683203] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10515 10:05:22.825814 <6>[ 0.692018] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10516 10:05:22.831783 <6>[ 0.699988] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10517 10:05:22.842245 <6>[ 0.708690] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10518 10:05:22.848613 <6>[ 0.718435] TCP: Hash tables configured (established 65536 bind 65536)
10519 10:05:22.855025 <6>[ 0.725298] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10520 10:05:22.864886 <6>[ 0.732493] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10521 10:05:22.871759 <6>[ 0.740201] NET: Registered PF_UNIX/PF_LOCAL protocol family
10522 10:05:22.878410 <6>[ 0.746371] RPC: Registered named UNIX socket transport module.
10523 10:05:22.881627 <6>[ 0.752522] RPC: Registered udp transport module.
10524 10:05:22.888008 <6>[ 0.757455] RPC: Registered tcp transport module.
10525 10:05:22.894921 <6>[ 0.762386] RPC: Registered tcp NFSv4.1 backchannel transport module.
10526 10:05:22.898090 <6>[ 0.769056] PCI: CLS 0 bytes, default 64
10527 10:05:22.901227 <6>[ 0.773397] Unpacking initramfs...
10528 10:05:22.922504 <6>[ 0.789819] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10529 10:05:22.932340 <6>[ 0.798505] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10530 10:05:22.935830 <6>[ 0.807360] kvm [1]: IPA Size Limit: 40 bits
10531 10:05:22.942331 <6>[ 0.811902] kvm [1]: GICv3: no GICV resource entry
10532 10:05:22.945512 <6>[ 0.816927] kvm [1]: disabling GICv2 emulation
10533 10:05:22.952309 <6>[ 0.821609] kvm [1]: GIC system register CPU interface enabled
10534 10:05:22.955750 <6>[ 0.827770] kvm [1]: vgic interrupt IRQ18
10535 10:05:22.962128 <6>[ 0.832127] kvm [1]: VHE mode initialized successfully
10536 10:05:22.968913 <5>[ 0.838506] Initialise system trusted keyrings
10537 10:05:22.975177 <6>[ 0.843294] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10538 10:05:22.982709 <6>[ 0.853381] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10539 10:05:22.989323 <5>[ 0.859766] NFS: Registering the id_resolver key type
10540 10:05:22.992721 <5>[ 0.865066] Key type id_resolver registered
10541 10:05:22.999483 <5>[ 0.869482] Key type id_legacy registered
10542 10:05:23.005918 <6>[ 0.873759] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10543 10:05:23.012520 <6>[ 0.880683] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10544 10:05:23.018732 <6>[ 0.888444] 9p: Installing v9fs 9p2000 file system support
10545 10:05:23.054697 <5>[ 0.925718] Key type asymmetric registered
10546 10:05:23.058460 <5>[ 0.930050] Asymmetric key parser 'x509' registered
10547 10:05:23.068313 <6>[ 0.935213] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10548 10:05:23.071589 <6>[ 0.942830] io scheduler mq-deadline registered
10549 10:05:23.075165 <6>[ 0.947605] io scheduler kyber registered
10550 10:05:23.093545 <6>[ 0.964347] EINJ: ACPI disabled.
10551 10:05:23.125432 <4>[ 0.989857] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10552 10:05:23.135351 <4>[ 1.000507] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10553 10:05:23.150219 <6>[ 1.021259] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10554 10:05:23.158066 <6>[ 1.029205] printk: console [ttyS0] disabled
10555 10:05:23.186320 <6>[ 1.053867] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10556 10:05:23.192786 <6>[ 1.063341] printk: console [ttyS0] enabled
10557 10:05:23.195981 <6>[ 1.063341] printk: console [ttyS0] enabled
10558 10:05:23.202773 <6>[ 1.072236] printk: bootconsole [mtk8250] disabled
10559 10:05:23.206307 <6>[ 1.072236] printk: bootconsole [mtk8250] disabled
10560 10:05:23.212634 <6>[ 1.083481] SuperH (H)SCI(F) driver initialized
10561 10:05:23.215741 <6>[ 1.088756] msm_serial: driver initialized
10562 10:05:23.229856 <6>[ 1.097649] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10563 10:05:23.240096 <6>[ 1.106193] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10564 10:05:23.246729 <6>[ 1.114735] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10565 10:05:23.256377 <6>[ 1.123364] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10566 10:05:23.266670 <6>[ 1.132070] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10567 10:05:23.272823 <6>[ 1.140790] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10568 10:05:23.282782 <6>[ 1.149331] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10569 10:05:23.289499 <6>[ 1.158134] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10570 10:05:23.299446 <6>[ 1.166678] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10571 10:05:23.311551 <6>[ 1.182244] loop: module loaded
10572 10:05:23.317928 <6>[ 1.188342] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10573 10:05:23.340939 <4>[ 1.211957] mtk-pmic-keys: Failed to locate of_node [id: -1]
10574 10:05:23.347982 <6>[ 1.218784] megasas: 07.719.03.00-rc1
10575 10:05:23.357355 <6>[ 1.228246] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10576 10:05:23.369527 <6>[ 1.240510] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10577 10:05:23.386507 <6>[ 1.257223] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10578 10:05:23.446943 <6>[ 1.311273] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10579 10:05:24.555720 <6>[ 2.426738] Freeing initrd memory: 39188K
10580 10:05:24.566025 <6>[ 2.436959] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10581 10:05:24.576975 <6>[ 2.447825] tun: Universal TUN/TAP device driver, 1.6
10582 10:05:24.580544 <6>[ 2.453878] thunder_xcv, ver 1.0
10583 10:05:24.583654 <6>[ 2.457384] thunder_bgx, ver 1.0
10584 10:05:24.586828 <6>[ 2.460877] nicpf, ver 1.0
10585 10:05:24.597136 <6>[ 2.464893] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10586 10:05:24.600567 <6>[ 2.472370] hns3: Copyright (c) 2017 Huawei Corporation.
10587 10:05:24.606896 <6>[ 2.477956] hclge is initializing
10588 10:05:24.610565 <6>[ 2.481536] e1000: Intel(R) PRO/1000 Network Driver
10589 10:05:24.617364 <6>[ 2.486665] e1000: Copyright (c) 1999-2006 Intel Corporation.
10590 10:05:24.623550 <6>[ 2.492681] e1000e: Intel(R) PRO/1000 Network Driver
10591 10:05:24.626846 <6>[ 2.497898] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10592 10:05:24.633336 <6>[ 2.504083] igb: Intel(R) Gigabit Ethernet Network Driver
10593 10:05:24.640207 <6>[ 2.509732] igb: Copyright (c) 2007-2014 Intel Corporation.
10594 10:05:24.646708 <6>[ 2.515568] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10595 10:05:24.653368 <6>[ 2.522087] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10596 10:05:24.656425 <6>[ 2.528548] sky2: driver version 1.30
10597 10:05:24.662854 <6>[ 2.533541] VFIO - User Level meta-driver version: 0.3
10598 10:05:24.670702 <6>[ 2.541734] usbcore: registered new interface driver usb-storage
10599 10:05:24.677019 <6>[ 2.548174] usbcore: registered new device driver onboard-usb-hub
10600 10:05:24.686148 <6>[ 2.557263] mt6397-rtc mt6359-rtc: registered as rtc0
10601 10:05:24.695932 <6>[ 2.562728] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-10T10:05:22 UTC (1686391522)
10602 10:05:24.699217 <6>[ 2.572291] i2c_dev: i2c /dev entries driver
10603 10:05:24.716306 <6>[ 2.584043] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10604 10:05:24.723248 <6>[ 2.594282] sdhci: Secure Digital Host Controller Interface driver
10605 10:05:24.729934 <6>[ 2.600718] sdhci: Copyright(c) Pierre Ossman
10606 10:05:24.736281 <6>[ 2.606109] Synopsys Designware Multimedia Card Interface Driver
10607 10:05:24.739919 <6>[ 2.612682] mmc0: CQHCI version 5.10
10608 10:05:24.746142 <6>[ 2.613270] sdhci-pltfm: SDHCI platform and OF driver helper
10609 10:05:24.753689 <6>[ 2.624540] ledtrig-cpu: registered to indicate activity on CPUs
10610 10:05:24.763966 <6>[ 2.631846] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10611 10:05:24.770960 <6>[ 2.639239] usbcore: registered new interface driver usbhid
10612 10:05:24.774101 <6>[ 2.645074] usbhid: USB HID core driver
10613 10:05:24.780829 <6>[ 2.649324] spi_master spi0: will run message pump with realtime priority
10614 10:05:24.828667 <6>[ 2.693309] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10615 10:05:24.847785 <6>[ 2.708623] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10616 10:05:24.851168 <6>[ 2.722207] mmc0: Command Queue Engine enabled
10617 10:05:24.858324 <6>[ 2.723879] cros-ec-spi spi0.0: Chrome EC device registered
10618 10:05:24.865105 <6>[ 2.726956] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10619 10:05:24.868382 <6>[ 2.740019] mmcblk0: mmc0:0001 DA4128 116 GiB
10620 10:05:24.882009 <6>[ 2.749758] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10621 10:05:24.888536 <6>[ 2.754192] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10622 10:05:24.895248 <6>[ 2.761271] NET: Registered PF_PACKET protocol family
10623 10:05:24.898806 <6>[ 2.766454] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10624 10:05:24.905444 <6>[ 2.770432] 9pnet: Installing 9P2000 support
10625 10:05:24.908539 <6>[ 2.776168] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10626 10:05:24.914942 <5>[ 2.780087] Key type dns_resolver registered
10627 10:05:24.921783 <6>[ 2.785919] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10628 10:05:24.925107 <6>[ 2.790398] registered taskstats version 1
10629 10:05:24.928052 <5>[ 2.800691] Loading compiled-in X.509 certificates
10630 10:05:24.964258 <4>[ 2.828594] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10631 10:05:24.974040 <4>[ 2.839297] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10632 10:05:24.984505 <3>[ 2.852049] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10633 10:05:24.996413 <6>[ 2.867604] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10634 10:05:25.003404 <6>[ 2.874499] xhci-mtk 11200000.usb: xHCI Host Controller
10635 10:05:25.010215 <6>[ 2.880007] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10636 10:05:25.020283 <6>[ 2.887861] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10637 10:05:25.026925 <6>[ 2.897297] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10638 10:05:25.033490 <6>[ 2.903378] xhci-mtk 11200000.usb: xHCI Host Controller
10639 10:05:25.040094 <6>[ 2.908865] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10640 10:05:25.046863 <6>[ 2.916518] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10641 10:05:25.053304 <6>[ 2.924243] hub 1-0:1.0: USB hub found
10642 10:05:25.056529 <6>[ 2.928270] hub 1-0:1.0: 1 port detected
10643 10:05:25.066192 <6>[ 2.932606] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10644 10:05:25.069916 <6>[ 2.941406] hub 2-0:1.0: USB hub found
10645 10:05:25.072826 <6>[ 2.945436] hub 2-0:1.0: 1 port detected
10646 10:05:25.081181 <6>[ 2.952513] mtk-msdc 11f70000.mmc: Got CD GPIO
10647 10:05:25.100340 <6>[ 2.968348] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10648 10:05:25.106903 <6>[ 2.976403] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10649 10:05:25.116755 <4>[ 2.984413] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10650 10:05:25.126567 <6>[ 2.994080] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10651 10:05:25.133675 <6>[ 3.002162] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10652 10:05:25.143334 <6>[ 3.010181] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10653 10:05:25.150287 <6>[ 3.018097] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10654 10:05:25.156640 <6>[ 3.025917] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10655 10:05:25.167021 <6>[ 3.033738] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10656 10:05:25.176790 <6>[ 3.044516] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10657 10:05:25.186810 <6>[ 3.052884] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10658 10:05:25.193618 <6>[ 3.061237] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10659 10:05:25.203067 <6>[ 3.069581] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10660 10:05:25.209832 <6>[ 3.077925] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10661 10:05:25.219895 <6>[ 3.086275] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10662 10:05:25.226199 <6>[ 3.094619] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10663 10:05:25.236224 <6>[ 3.102963] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10664 10:05:25.242806 <6>[ 3.111306] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10665 10:05:25.252876 <6>[ 3.119650] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10666 10:05:25.259435 <6>[ 3.127993] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10667 10:05:25.269404 <6>[ 3.136337] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10668 10:05:25.275946 <6>[ 3.144680] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10669 10:05:25.286037 <6>[ 3.153023] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10670 10:05:25.292255 <6>[ 3.161369] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10671 10:05:25.299374 <6>[ 3.170323] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10672 10:05:25.307053 <6>[ 3.177827] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10673 10:05:25.313852 <6>[ 3.184922] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10674 10:05:25.324295 <6>[ 3.192083] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10675 10:05:25.330925 <6>[ 3.199409] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10676 10:05:25.340662 <6>[ 3.206351] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10677 10:05:25.347720 <6>[ 3.215492] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10678 10:05:25.357399 <6>[ 3.224619] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10679 10:05:25.367094 <6>[ 3.233921] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10680 10:05:25.377128 <6>[ 3.243396] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10681 10:05:25.387214 <6>[ 3.252872] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10682 10:05:25.397245 <6>[ 3.262001] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10683 10:05:25.403430 <6>[ 3.271475] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10684 10:05:25.413709 <6>[ 3.280602] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10685 10:05:25.423459 <6>[ 3.289904] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10686 10:05:25.433277 <6>[ 3.300070] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10687 10:05:25.443557 <6>[ 3.311479] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10688 10:05:25.481763 <6>[ 3.349370] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10689 10:05:25.634182 <6>[ 3.505269] hub 1-1:1.0: USB hub found
10690 10:05:25.637419 <6>[ 3.509625] hub 1-1:1.0: 4 ports detected
10691 10:05:25.762006 <6>[ 3.629601] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10692 10:05:25.786899 <6>[ 3.657834] hub 2-1:1.0: USB hub found
10693 10:05:25.790081 <6>[ 3.662231] hub 2-1:1.0: 3 ports detected
10694 10:05:25.957292 <6>[ 3.825401] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10695 10:05:26.090758 <6>[ 3.961726] hub 1-1.4:1.0: USB hub found
10696 10:05:26.093766 <6>[ 3.966402] hub 1-1.4:1.0: 2 ports detected
10697 10:05:26.169813 <6>[ 4.037668] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10698 10:05:26.393423 <6>[ 4.261396] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10699 10:05:26.585640 <6>[ 4.453398] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10700 10:05:37.725882 <6>[ 15.601944] ALSA device list:
10701 10:05:37.732198 <6>[ 15.605201] No soundcards found.
10702 10:05:37.744657 <6>[ 15.617615] Freeing unused kernel memory: 8384K
10703 10:05:37.747874 <6>[ 15.622546] Run /init as init process
10704 10:05:37.778529 <6>[ 15.651567] NET: Registered PF_INET6 protocol family
10705 10:05:37.785534 <6>[ 15.658195] Segment Routing with IPv6
10706 10:05:37.788699 <6>[ 15.662177] In-situ OAM (IOAM) with IPv6
10707 10:05:37.823439 <30>[ 15.676570] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10708 10:05:37.827101 <30>[ 15.700350] systemd[1]: Detected architecture arm64.
10709 10:05:37.827220
10710 10:05:37.833493 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10711 10:05:37.833570
10712 10:05:37.852479 <30>[ 15.725480] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10713 10:05:37.996171 <30>[ 15.865979] systemd[1]: Queued start job for default target Graphical Interface.
10714 10:05:38.029761 <30>[ 15.902576] systemd[1]: Created slice system-getty.slice.
10715 10:05:38.036234 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10716 10:05:38.057333 <30>[ 15.930002] systemd[1]: Created slice system-modprobe.slice.
10717 10:05:38.063922 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10718 10:05:38.081895 <30>[ 15.954536] systemd[1]: Created slice system-serial\x2dgetty.slice.
10719 10:05:38.091783 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10720 10:05:38.104868 <30>[ 15.977890] systemd[1]: Created slice User and Session Slice.
10721 10:05:38.111226 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10722 10:05:38.132224 <30>[ 16.001973] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10723 10:05:38.142442 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10724 10:05:38.159789 <30>[ 16.029571] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10725 10:05:38.166643 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10726 10:05:38.187131 <30>[ 16.053476] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10727 10:05:38.193612 <30>[ 16.065504] systemd[1]: Reached target Local Encrypted Volumes.
10728 10:05:38.200098 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10729 10:05:38.216362 <30>[ 16.089490] systemd[1]: Reached target Paths.
10730 10:05:38.219683 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10731 10:05:38.236584 <30>[ 16.109429] systemd[1]: Reached target Remote File Systems.
10732 10:05:38.243275 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10733 10:05:38.256397 <30>[ 16.129416] systemd[1]: Reached target Slices.
10734 10:05:38.259705 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10735 10:05:38.276353 <30>[ 16.149431] systemd[1]: Reached target Swap.
10736 10:05:38.279499 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10737 10:05:38.299899 <30>[ 16.169677] systemd[1]: Listening on initctl Compatibility Named Pipe.
10738 10:05:38.306775 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10739 10:05:38.313229 <30>[ 16.184386] systemd[1]: Listening on Journal Audit Socket.
10740 10:05:38.320018 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10741 10:05:38.332672 <30>[ 16.205687] systemd[1]: Listening on Journal Socket (/dev/log).
10742 10:05:38.339105 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10743 10:05:38.357110 <30>[ 16.230189] systemd[1]: Listening on Journal Socket.
10744 10:05:38.363660 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10745 10:05:38.379973 <30>[ 16.249820] systemd[1]: Listening on Network Service Netlink Socket.
10746 10:05:38.386654 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10747 10:05:38.401259 <30>[ 16.274179] systemd[1]: Listening on udev Control Socket.
10748 10:05:38.407687 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10749 10:05:38.424972 <30>[ 16.298126] systemd[1]: Listening on udev Kernel Socket.
10750 10:05:38.431780 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10751 10:05:38.464591 <30>[ 16.337544] systemd[1]: Mounting Huge Pages File System...
10752 10:05:38.470878 Mounting [0;1;39mHuge Pages File System[0m...
10753 10:05:38.486657 <30>[ 16.359506] systemd[1]: Mounting POSIX Message Queue File System...
10754 10:05:38.493597 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10755 10:05:38.510720 <30>[ 16.383486] systemd[1]: Mounting Kernel Debug File System...
10756 10:05:38.517065 Mounting [0;1;39mKernel Debug File System[0m...
10757 10:05:38.536002 <30>[ 16.405672] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10758 10:05:38.568178 <30>[ 16.437927] systemd[1]: Starting Create list of static device nodes for the current kernel...
10759 10:05:38.574587 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10760 10:05:38.595154 <30>[ 16.468061] systemd[1]: Starting Load Kernel Module configfs...
10761 10:05:38.601578 Starting [0;1;39mLoad Kernel Module configfs[0m...
10762 10:05:38.619024 <30>[ 16.491747] systemd[1]: Starting Load Kernel Module drm...
10763 10:05:38.625559 Starting [0;1;39mLoad Kernel Module drm[0m...
10764 10:05:38.644140 <30>[ 16.513647] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10765 10:05:38.654226 <30>[ 16.527436] systemd[1]: Starting Journal Service...
10766 10:05:38.657615 Starting [0;1;39mJournal Service[0m...
10767 10:05:38.675136 <30>[ 16.548149] systemd[1]: Starting Load Kernel Modules...
10768 10:05:38.681884 Starting [0;1;39mLoad Kernel Modules[0m...
10769 10:05:38.702204 <30>[ 16.572071] systemd[1]: Starting Remount Root and Kernel File Systems...
10770 10:05:38.708554 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10771 10:05:38.723204 <30>[ 16.596190] systemd[1]: Starting Coldplug All udev Devices...
10772 10:05:38.729456 Starting [0;1;39mColdplug All udev Devices[0m...
10773 10:05:38.747198 <30>[ 16.620152] systemd[1]: Mounted Huge Pages File System.
10774 10:05:38.753752 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10775 10:05:38.768871 <30>[ 16.641752] systemd[1]: Started Journal Service.
10776 10:05:38.775186 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10777 10:05:38.789876 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10778 10:05:38.805184 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10779 10:05:38.824793 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10780 10:05:38.841791 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10781 10:05:38.857846 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10782 10:05:38.873582 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10783 10:05:38.893008 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10784 10:05:38.908580 See 'systemctl status systemd-remount-fs.service' for details.
10785 10:05:38.953999 Mounting [0;1;39mKernel Configuration File System[0m...
10786 10:05:38.975312 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10787 10:05:38.992760 <46>[ 16.862608] systemd-journald[175]: Received client request to flush runtime journal.
10788 10:05:39.029170 Starting [0;1;39mLoad/Save Random Seed[0m...
10789 10:05:39.047533 Starting [0;1;39mApply Kernel Variables[0m...
10790 10:05:39.063697 Starting [0;1;39mCreate System Users[0m...
10791 10:05:39.079065 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10792 10:05:39.100927 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10793 10:05:39.114196 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10794 10:05:39.129595 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10795 10:05:39.145354 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10796 10:05:39.161745 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10797 10:05:39.205160 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10798 10:05:39.228064 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10799 10:05:39.241099 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10800 10:05:39.260516 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10801 10:05:39.300803 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10802 10:05:39.324653 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10803 10:05:39.345337 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10804 10:05:39.364672 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10805 10:05:39.418073 Starting [0;1;39mNetwork Service[0m...
10806 10:05:39.440898 Starting [0;1;39mNetwork Time Synchronization[0m...
10807 10:05:39.462904 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10808 10:05:39.516552 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10809 10:05:39.537580 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10810 10:05:39.559748 <6>[ 17.429441] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10811 10:05:39.572597 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronizatio<6>[ 17.442241] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10812 10:05:39.572708 n[0m.
10813 10:05:39.582571 <6>[ 17.450704] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10814 10:05:39.589467 <6>[ 17.460387] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10815 10:05:39.596219 <6>[ 17.465786] remoteproc remoteproc0: scp is available
10816 10:05:39.602730 [[0;32m OK [<6>[ 17.475678] remoteproc remoteproc0: powering up scp
10817 10:05:39.612662 0m] Found device<6>[ 17.481384] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10818 10:05:39.619070 [0;1;39m/dev/t<6>[ 17.487338] usbcore: registered new interface driver r8152
10819 10:05:39.622210 tyS0[0m.
10820 10:05:39.625500 <6>[ 17.491177] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10821 10:05:39.635056 <6>[ 17.507905] mc: Linux media interface: v0.10
10822 10:05:39.650643 <4>[ 17.520631] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10823 10:05:39.660710 <4>[ 17.530466] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10824 10:05:39.663964 <6>[ 17.537686] videodev: Linux video capture interface: v2.00
10825 10:05:39.673810 [[0;32m OK [<6>[ 17.544970] usbcore: registered new interface driver cdc_ether
10826 10:05:39.680598 0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10827 10:05:39.696336 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10828 10:05:39.707874 <3>[ 17.577653] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10829 10:05:39.717808 <3>[ 17.586490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10830 10:05:39.724267 <3>[ 17.594747] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10831 10:05:39.731046 <6>[ 17.598994] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10832 10:05:39.737739 [[0;32m OK [<6>[ 17.609770] pci_bus 0000:00: root bus resource [bus 00-ff]
10833 10:05:39.747644 0m] Reached targ<6>[ 17.610037] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10834 10:05:39.757497 et [0;1;39mSyst<3>[ 17.613416] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10835 10:05:39.767059 em Time Synchron<3>[ 17.613442] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10836 10:05:39.767147 ized[0m.
10837 10:05:39.773994 <3>[ 17.613450] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10838 10:05:39.783882 <3>[ 17.613461] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10839 10:05:39.790370 <3>[ 17.613471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10840 10:05:39.800412 <3>[ 17.613599] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10841 10:05:39.807208 <3>[ 17.613682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10842 10:05:39.817146 <3>[ 17.613691] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10843 10:05:39.823684 <3>[ 17.613698] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10844 10:05:39.833678 <3>[ 17.616504] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10845 10:05:39.840347 <3>[ 17.616523] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10846 10:05:39.850322 <3>[ 17.616531] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10847 10:05:39.857043 <3>[ 17.616542] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10848 10:05:39.866866 <3>[ 17.616550] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10849 10:05:39.873867 <6>[ 17.616852] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10850 10:05:39.880949 <3>[ 17.618404] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10851 10:05:39.887400 <6>[ 17.629175] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10852 10:05:39.897531 <6>[ 17.630205] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10853 10:05:39.903806 <6>[ 17.630213] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10854 10:05:39.910809 <6>[ 17.630216] remoteproc remoteproc0: remote processor scp is now up
10855 10:05:39.920423 <6>[ 17.634824] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10856 10:05:39.927261 <6>[ 17.634921] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10857 10:05:39.934075 <3>[ 17.649667] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10858 10:05:39.940172 <6>[ 17.653453] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10859 10:05:39.944175 <6>[ 17.653606] pci 0000:00:00.0: supports D1 D2
10860 10:05:39.950599 <6>[ 17.653616] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10861 10:05:39.960494 <6>[ 17.657508] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10862 10:05:39.970421 <4>[ 17.664789] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10863 10:05:39.973821 <6>[ 17.670277] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10864 10:05:39.984200 <4>[ 17.670487] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10865 10:05:39.987864 <4>[ 17.670487] Fallback method does not support PEC.
10866 10:05:39.997485 <4>[ 17.678497] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10867 10:05:40.007570 <3>[ 17.687529] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10868 10:05:40.013939 <6>[ 17.689320] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10869 10:05:40.020691 <6>[ 17.689348] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10870 10:05:40.027128 <6>[ 17.689367] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10871 10:05:40.033644 <6>[ 17.689516] pci 0000:01:00.0: supports D1 D2
10872 10:05:40.040340 <6>[ 17.689521] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10873 10:05:40.047186 <6>[ 17.705344] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10874 10:05:40.056862 <6>[ 17.712633] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10875 10:05:40.063658 <6>[ 17.719096] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10876 10:05:40.073353 <6>[ 17.720624] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10877 10:05:40.080014 <6>[ 17.724057] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10878 10:05:40.090129 <6>[ 17.727803] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10879 10:05:40.100004 <6>[ 17.735519] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10880 10:05:40.107230 <3>[ 17.757410] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 10:05:40.113801 <6>[ 17.758879] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10882 10:05:40.120711 <6>[ 17.766568] r8152 2-1.3:1.0 eth0: v1.12.13
10883 10:05:40.127303 <3>[ 17.766757] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10884 10:05:40.134030 <3>[ 17.773374] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10885 10:05:40.140550 <6>[ 17.774908] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10886 10:05:40.150800 <3>[ 17.793487] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 10:05:40.160878 <6>[ 17.798288] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10888 10:05:40.164054 <6>[ 17.798304] pci 0000:00:00.0: PCI bridge to [bus 01]
10889 10:05:40.174020 <3>[ 17.828638] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 10:05:40.180699 <6>[ 17.829844] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10891 10:05:40.187157 <6>[ 17.830037] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10892 10:05:40.197051 <3>[ 17.862521] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 10:05:40.203460 <6>[ 17.867978] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10894 10:05:40.209996 <3>[ 17.873348] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10895 10:05:40.216922 <3>[ 17.873640] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10896 10:05:40.223864 <6>[ 17.873749] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10897 10:05:40.230071 <6>[ 17.891772] usbcore: registered new interface driver r8153_ecm
10898 10:05:40.237278 <6>[ 17.899479] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10899 10:05:40.240049 <6>[ 17.919108] Bluetooth: Core ver 2.22
10900 10:05:40.246626 <6>[ 17.921201] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10901 10:05:40.253579 <6>[ 17.935071] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10902 10:05:40.259883 <6>[ 17.943236] NET: Registered PF_BLUETOOTH protocol family
10903 10:05:40.266868 <6>[ 17.952429] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10904 10:05:40.273684 <6>[ 17.959776] Bluetooth: HCI device and connection manager initialized
10905 10:05:40.284267 <6>[ 17.960959] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10906 10:05:40.291642 <6>[ 17.961146] usbcore: registered new interface driver uvcvideo
10907 10:05:40.297781 <5>[ 17.973342] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10908 10:05:40.304743 <6>[ 17.976910] Bluetooth: HCI socket layer initialized
10909 10:05:40.314804 <3>[ 17.991729] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 10:05:40.321375 <3>[ 17.992512] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10911 10:05:40.328327 <6>[ 17.993512] Bluetooth: L2CAP socket layer initialized
10912 10:05:40.331509 <6>[ 17.993546] Bluetooth: SCO socket layer initialized
10913 10:05:40.338643 <5>[ 17.997099] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10914 10:05:40.348863 <4>[ 18.001296] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10915 10:05:40.358231 <3>[ 18.006133] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 10:05:40.361870 <6>[ 18.012359] cfg80211: failed to load regulatory.db
10917 10:05:40.368095 <6>[ 18.067098] usbcore: registered new interface driver btusb
10918 10:05:40.378199 <4>[ 18.067771] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10919 10:05:40.384552 <3>[ 18.067782] Bluetooth: hci0: Failed to load firmware file (-2)
10920 10:05:40.391058 <3>[ 18.067786] Bluetooth: hci0: Failed to set up firmware (-2)
10921 10:05:40.401061 <4>[ 18.067790] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10922 10:05:40.407599 <3>[ 18.097615] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 10:05:40.417745 <6>[ 18.102333] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10924 10:05:40.420854 <6>[ 18.102438] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10925 10:05:40.427499 <6>[ 18.121316] mt7921e 0000:01:00.0: ASIC revision: 79610010
10926 10:05:40.434359 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10927 10:05:40.485011 Starting [0;1;39mNetwork Name Resolution[0m...
10928 10:05:40.505083 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10929 10:05:40.535358 <4>[ 18.401625] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10930 10:05:40.607958 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10931 10:05:40.657095 <4>[ 18.523562] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10932 10:05:40.701118 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10933 10:05:40.716973 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10934 10:05:40.736071 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10935 10:05:40.752799 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10936 10:05:40.776738 [[0;32m OK [<4>[ 18.644061] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10937 10:05:40.783263 0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10938 10:05:40.801154 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10939 10:05:40.816704 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10940 10:05:40.836530 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10941 10:05:40.848818 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10942 10:05:40.864615 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10943 10:05:40.885594 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10944 10:05:40.898694 <4>[ 18.764007] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10945 10:05:40.937208 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10946 10:05:40.963439 Starting [0;1;39mUser Login Management[0m...
10947 10:05:40.979088 Starting [0;1;39mPermit User Sessions[0m...
10948 10:05:40.996636 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10949 10:05:41.008613 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10950 10:05:41.021482 <4>[ 18.886166] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10951 10:05:41.021916
10952 10:05:41.031666 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10953 10:05:41.085464 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10954 10:05:41.107402 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10955 10:05:41.130631 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10956 10:05:41.143374 <4>[ 19.008333] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10957 10:05:41.152522 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10958 10:05:41.161304 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10959 10:05:41.176645 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10960 10:05:41.228575 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10961 10:05:41.266956 [[0;32m OK [0m] Finished [0;1;39mUpdate UTM<4>[ 19.133522] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10962 10:05:41.270103 P about System Runlevel Changes[0m.
10963 10:05:41.290090
10964 10:05:41.290541
10965 10:05:41.293218 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10966 10:05:41.293670
10967 10:05:41.296838 debian-bullseye-arm64 login: root (automatic login)
10968 10:05:41.297346
10969 10:05:41.297755
10970 10:05:41.313186 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 10 09:51:11 UTC 2023 aarch64
10971 10:05:41.313641
10972 10:05:41.319937 The programs included with the Debian GNU/Linux system are free software;
10973 10:05:41.326193 the exact distribution terms for each program are described in the
10974 10:05:41.329407 individual files in /usr/share/doc/*/copyright.
10975 10:05:41.329831
10976 10:05:41.336518 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10977 10:05:41.339142 permitted by applicable law.
10978 10:05:41.340238 Matched prompt #10: / #
10980 10:05:41.341270 Setting prompt string to ['/ #']
10981 10:05:41.341709 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10983 10:05:41.342689 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10984 10:05:41.343142 start: 2.2.6 expect-shell-connection (timeout 00:03:33) [common]
10985 10:05:41.343502 Setting prompt string to ['/ #']
10986 10:05:41.343813 Forcing a shell prompt, looking for ['/ #']
10988 10:05:41.394559 / #
10989 10:05:41.395075 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10990 10:05:41.395526 Waiting using forced prompt support (timeout 00:02:30)
10991 10:05:41.396042 <4>[ 19.255718] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10992 10:05:41.400743
10993 10:05:41.401572 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10994 10:05:41.402117 start: 2.2.7 export-device-env (timeout 00:03:33) [common]
10995 10:05:41.402634 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10996 10:05:41.403121 end: 2.2 depthcharge-retry (duration 00:01:27) [common]
10997 10:05:41.403560 end: 2 depthcharge-action (duration 00:01:27) [common]
10998 10:05:41.404051 start: 3 lava-test-retry (timeout 00:08:14) [common]
10999 10:05:41.404561 start: 3.1 lava-test-shell (timeout 00:08:14) [common]
11000 10:05:41.405016 Using namespace: common
11002 10:05:41.505984 / # #
11003 10:05:41.506137 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11004 10:05:41.508547 #<4>[ 19.375303] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11005 10:05:41.508633
11006 10:05:41.553126 Using /lava-10670678
11008 10:05:41.653459 / # export SHELL=/bin/sh
11009 10:05:41.653610 <6>[ 19.441353] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11010 10:05:41.653684 <6>[ 19.449253] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11011 10:05:41.653748 export SHELL=/bin/sh<4>[ 19.495491] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11012 10:05:41.658524
11014 10:05:41.759090 / # . /lava-10670678/environment
11015 10:05:41.759236 . /lava-10670678/environment<3>[ 19.612990] mt7921e 0000:01:00.0: hardware init failed
11016 10:05:41.764171
11018 10:05:41.864740 / # /lava-10670678/bin/lava-test-runner /lava-10670678/0
11019 10:05:41.864902 Test shell timeout: 10s (minimum of the action and connection timeout)
11020 10:05:41.869937 /lava-10670678/bin/lava-test-runner /lava-10670678/0
11021 10:05:41.893114 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11022 10:05:41.899855 + cd /lava-10670678/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11023 10:05:41.899943 + cat uuid
11024 10:05:41.903427 + UUID=10670678_1.5.2.3.1
11025 10:05:41.903544 + set +x
11026 10:05:41.909816 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 10670678_1.5.2.3.1>
11027 10:05:41.910109 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 10670678_1.5.2.3.1
11028 10:05:41.910193 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (10670678_1.5.2.3.1)
11029 10:05:41.910279 Skipping test definition patterns.
11030 10:05:41.913044 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11031 10:05:41.916408 Received signal: <TESTCASE> TEST_CASE_ID=device-presence<4
11032 10:05:41.916511 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'device-presence<4', 'result': 'unknown'}
11033 10:05:41.926024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence<4>[ 19.795568] use of bytesused == 0 is deprecated and will be removed in the future,
11034 10:05:41.926110 RESULT=pass>
11035 10:05:41.929544 d<4>[ 19.803522] use the actual size instead.
11036 10:05:41.932996 evice: /dev/video2
11037 10:05:41.935862 <4>[ 19.810983] ------------[ cut here ]------------
11038 10:05:41.942951 <4>[ 19.815867] get_vaddr_frames() cannot follow VM_IO mapping
11039 10:05:41.955798 <4>[ 19.816006] WARNING: CPU: 0 PID: 304 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11040 10:05:42.005432 <4>[ 19.834108] Modules linked in: mt7921e mt7921_common btusb mt76_connac_lib btintel mt76 btmtk btrtl mac80211 btbcm libarc4 mtk_vcodec_enc mtk_vcodec_common cfg80211 mtk_vpu v4l2_mem2mem uvcvideo bluetooth videobuf2_dma_contig videobuf2_vmalloc videobuf2_memops ecdh_generic r8153_ecm ecc videobuf2_v4l2 cros_ec_rpmsg cros_ec_chardev rfkill crct10dif_ce videobuf2_common sbs_battery cros_ec_typec elan_i2c videodev cdc_ether hid_google_hammer hid_vivaldi_common elants_i2c usbnet mc r8152 pcie_mediatek_gen3 mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11041 10:05:42.012361 <4>[ 19.883490] CPU: 0 PID: 304 Comm: v4l2-compliance Not tainted 6.1.31 #1
11042 10:05:42.018670 <4>[ 19.890354] Hardware name: Google Spherion (rev0 - 3) (DT)
11043 10:05:42.025153 <4>[ 19.896089] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11044 10:05:42.031895 <4>[ 19.903300] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11045 10:05:42.038557 <4>[ 19.909391] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11046 10:05:42.041685 <4>[ 19.915482] sp : ffff80000919b850
11047 10:05:42.048141 <4>[ 19.919045] x29: ffff80000919b850 x28: ffffa7b0cf757000 x27: ffffa7b0cf753238
11048 10:05:42.055034 <4>[ 19.926432] x26: 0000000000000000 x25: ffffa7b12b0db3b8 x24: ffff468c8e6f1298
11049 10:05:42.061777 <4>[ 19.933819] x23: ffff468c8a5f0000 x22: ffff468c80d48010 x21: 0000000000000000
11050 10:05:42.071508 <4>[ 19.941206] x20: 00000000fffffff2 x19: ffff468c8b273d00 x18: fffffffffffe96b8
11051 10:05:42.078075 <4>[ 19.948594] x17: 0000000000000000 x16: ffffa7b12928bb60 x15: 0000000000000038
11052 10:05:42.084899 <4>[ 19.955981] x14: ffffa7b12b9c34a8 x13: 0000000000000648 x12: 0000000000000218
11053 10:05:42.091261 <4>[ 19.963368] x11: fffffffffffe96b8 x10: fffffffffffe9680 x9 : 00000000fffff218
11054 10:05:42.100958 <4>[ 19.970755] x8 : ffffa7b12b9c34a8 x7 : ffffa7b12ba1b4a8 x6 : 0000000000001920
11055 10:05:42.107711 <4>[ 19.978141] x5 : ffff468dbef12a18 x4 : 00000000fffff218 x3 : ffff9edc93c0f000
11056 10:05:42.114509 <4>[ 19.985527] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff468c8e288000
11057 10:05:42.117680 <4>[ 19.992914] Call trace:
11058 10:05:42.124246 <4>[ 19.995611] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11059 10:05:42.127625 <4>[ 20.001354] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11060 10:05:42.134369 <4>[ 20.007359] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11061 10:05:42.140720 <4>[ 20.013710] __prepare_userptr+0x280/0x410 [videobuf2_common]
11062 10:05:42.147303 <4>[ 20.019713] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11063 10:05:42.153947 <4>[ 20.025369] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11064 10:05:42.157357 <4>[ 20.031546] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11065 10:05:42.164031 <4>[ 20.037046] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11066 10:05:42.170513 <4>[ 20.042821] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11067 10:05:42.177285 <4>[ 20.049086] v4l_prepare_buf+0x48/0x60 [videodev]
11068 10:05:42.180535 <4>[ 20.054109] __video_do_ioctl+0x184/0x3d0 [videodev]
11069 10:05:42.186981 <4>[ 20.059353] video_usercopy+0x358/0x680 [videodev]
11070 10:05:42.190346 <4>[ 20.064423] video_ioctl2+0x18/0x30 [videodev]
11071 10:05:42.194002 <4>[ 20.069147] v4l2_ioctl+0x40/0x60 [videodev]
11072 10:05:42.200240 <4>[ 20.073697] __arm64_sys_ioctl+0xa8/0xf0
11073 10:05:42.203378 <4>[ 20.077879] invoke_syscall+0x48/0x114
11074 10:05:42.206997 <4>[ 20.081884] el0_svc_common.constprop.0+0x44/0xec
11075 10:05:42.213717 <4>[ 20.086839] do_el0_svc+0x2c/0xd0
11076 10:05:42.216853 <4>[ 20.090405] el0_svc+0x2c/0x84
11077 10:05:42.220108 <4>[ 20.093715] el0t_64_sync_handler+0xb8/0xc0
11078 10:05:42.223514 <4>[ 20.098149] el0t_64_sync+0x18c/0x190
11079 10:05:42.230032 <4>[ 20.102062] ---[ end trace 0000000000000000 ]---
11080 10:05:42.241842 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11081 10:05:42.251602 v4l2-compliance SHA: 52926c1f2f03 2023-05-25 13:56:39
11082 10:05:42.257048
11083 10:05:42.268974 Compliance test for mtk-vcodec-enc device /dev/video2:
11084 10:05:42.274722
11085 10:05:42.284048 Driver Info:
11086 10:05:42.293312 Driver name : mtk-vcodec-enc
11087 10:05:42.306423 Card type : MT8192 video encoder
11088 10:05:42.315726 Bus info : platform:17020000.vcodec
11089 10:05:42.322617 Driver version : 6.1.31
11090 10:05:42.332906 Capabilities : 0x84204000
11091 10:05:42.343041 Video Memory-to-Memory Multiplanar
11092 10:05:42.352888 Streaming
11093 10:05:42.363955 Extended Pix Format
11094 10:05:42.373704 Device Capabilities
11095 10:05:42.384425 Device Caps : 0x04204000
11096 10:05:42.394295 Video Memory-to-Memory Multiplanar
11097 10:05:42.404427 Streaming
11098 10:05:42.415031 Extended Pix Format
11099 10:05:42.425052 Detected Stateful Encoder
11100 10:05:42.434420
11101 10:05:42.445449 Required ioctls:
11102 10:05:42.460074 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11103 10:05:42.460181 test VIDIOC_QUERYCAP: OK
11104 10:05:42.460475 Received signal: <TESTSET> START Required-ioctls
11105 10:05:42.460557 Starting test_set Required-ioctls
11106 10:05:42.483256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11107 10:05:42.483514 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11109 10:05:42.486210 test invalid ioctls: OK
11110 10:05:42.505633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11111 10:05:42.505717
11112 10:05:42.505951 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11114 10:05:42.515034 Allow for multiple opens:
11115 10:05:42.520825 <LAVA_SIGNAL_TESTSET STOP>
11116 10:05:42.521100 Received signal: <TESTSET> STOP
11117 10:05:42.521200 Closing test_set Required-ioctls
11118 10:05:42.530514 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11119 10:05:42.530759 Received signal: <TESTSET> START Allow-for-multiple-opens
11120 10:05:42.530826 Starting test_set Allow-for-multiple-opens
11121 10:05:42.533837 test second /dev/video2 open: OK
11122 10:05:42.553668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11123 10:05:42.553917 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11125 10:05:42.556896 test VIDIOC_QUERYCAP: OK
11126 10:05:42.577113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11127 10:05:42.577367 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11129 10:05:42.580313 test VIDIOC_G/S_PRIORITY: OK
11130 10:05:42.600003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11131 10:05:42.600252 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11133 10:05:42.603218 test for unlimited opens: OK
11134 10:05:42.623348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11135 10:05:42.623432
11136 10:05:42.623665 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11138 10:05:42.631877 Debug ioctls:
11139 10:05:42.638363 <LAVA_SIGNAL_TESTSET STOP>
11140 10:05:42.638613 Received signal: <TESTSET> STOP
11141 10:05:42.638681 Closing test_set Allow-for-multiple-opens
11142 10:05:42.647239 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11143 10:05:42.647491 Received signal: <TESTSET> START Debug-ioctls
11144 10:05:42.647563 Starting test_set Debug-ioctls
11145 10:05:42.650454 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11146 10:05:42.670696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11147 10:05:42.670949 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11149 10:05:42.677339 test VIDIOC_LOG_STATUS: OK (Not Supported)
11150 10:05:42.694554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11151 10:05:42.694637
11152 10:05:42.694900 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11154 10:05:42.704964 Input ioctls:
11155 10:05:42.711836 <LAVA_SIGNAL_TESTSET STOP>
11156 10:05:42.712087 Received signal: <TESTSET> STOP
11157 10:05:42.712156 Closing test_set Debug-ioctls
11158 10:05:42.720381 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11159 10:05:42.720643 Received signal: <TESTSET> START Input-ioctls
11160 10:05:42.720712 Starting test_set Input-ioctls
11161 10:05:42.723677 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11162 10:05:42.748070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11163 10:05:42.748322 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11165 10:05:42.751261 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11166 10:05:42.767126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11167 10:05:42.767386 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11169 10:05:42.773541 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11170 10:05:42.790888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11171 10:05:42.791138 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11173 10:05:42.797486 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11174 10:05:42.814621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11175 10:05:42.814872 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11177 10:05:42.817574 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11178 10:05:42.837503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11179 10:05:42.837754 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11181 10:05:42.840690 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11182 10:05:42.861552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11183 10:05:42.861801 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11185 10:05:42.864928 Inputs: 0 Audio Inputs: 0 Tuners: 0
11186 10:05:42.872188
11187 10:05:42.888129 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11188 10:05:42.909301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11189 10:05:42.909554 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11191 10:05:42.915738 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11192 10:05:42.933771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11193 10:05:42.934021 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11195 10:05:42.940221 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11196 10:05:42.958064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11197 10:05:42.958346 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11199 10:05:42.964314 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11200 10:05:42.982551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11201 10:05:42.982803 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11203 10:05:42.989012 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11204 10:05:43.006592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11205 10:05:43.006676
11206 10:05:43.006909 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11208 10:05:43.025294 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11209 10:05:43.045288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11210 10:05:43.045547 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11212 10:05:43.051706 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11213 10:05:43.073727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11214 10:05:43.074015 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11216 10:05:43.077004 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11217 10:05:43.094277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11218 10:05:43.094527 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11220 10:05:43.097548 test VIDIOC_G/S_EDID: OK (Not Supported)
11221 10:05:43.117771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11222 10:05:43.117878
11223 10:05:43.118142 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11225 10:05:43.127759 Control ioctls:
11226 10:05:43.134790 <LAVA_SIGNAL_TESTSET STOP>
11227 10:05:43.135035 Received signal: <TESTSET> STOP
11228 10:05:43.135108 Closing test_set Input-ioctls
11229 10:05:43.144716 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11230 10:05:43.144971 Received signal: <TESTSET> START Control-ioctls
11231 10:05:43.145068 Starting test_set Control-ioctls
11232 10:05:43.147738 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11233 10:05:43.171600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11234 10:05:43.171684 test VIDIOC_QUERYCTRL: OK
11235 10:05:43.171919 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11237 10:05:43.193089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11238 10:05:43.193365 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11240 10:05:43.196586 test VIDIOC_G/S_CTRL: OK
11241 10:05:43.218257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11242 10:05:43.218538 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11244 10:05:43.221440 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11245 10:05:43.242056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11246 10:05:43.242313 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11248 10:05:43.252115 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11249 10:05:43.255151 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11250 10:05:43.283033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11251 10:05:43.283291 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11253 10:05:43.286249 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11254 10:05:43.306251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11255 10:05:43.306525 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11257 10:05:43.309816 Standard Controls: 16 Private Controls: 0
11258 10:05:43.315522
11259 10:05:43.327554 Format ioctls:
11260 10:05:43.334579 <LAVA_SIGNAL_TESTSET STOP>
11261 10:05:43.334824 Received signal: <TESTSET> STOP
11262 10:05:43.334892 Closing test_set Control-ioctls
11263 10:05:43.343298 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11264 10:05:43.343544 Received signal: <TESTSET> START Format-ioctls
11265 10:05:43.343641 Starting test_set Format-ioctls
11266 10:05:43.346313 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11267 10:05:43.369464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11268 10:05:43.369735 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11270 10:05:43.372866 test VIDIOC_G/S_PARM: OK
11271 10:05:43.389969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11272 10:05:43.390216 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11274 10:05:43.393299 test VIDIOC_G_FBUF: OK (Not Supported)
11275 10:05:43.414199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11276 10:05:43.414475 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11278 10:05:43.417652 test VIDIOC_G_FMT: OK
11279 10:05:43.437626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11280 10:05:43.437874 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11282 10:05:43.441140 test VIDIOC_TRY_FMT: OK
11283 10:05:43.460667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11284 10:05:43.460962 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11286 10:05:43.470405 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11287 10:05:43.473665 test VIDIOC_S_FMT: FAIL
11288 10:05:43.495781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11289 10:05:43.496030 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11291 10:05:43.499382 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11292 10:05:43.519502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11293 10:05:43.519782 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11295 10:05:43.523093 test Cropping: OK
11296 10:05:43.542543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11297 10:05:43.542799 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11299 10:05:43.545830 test Composing: OK (Not Supported)
11300 10:05:43.565014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11301 10:05:43.565290 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11303 10:05:43.568692 test Scaling: OK (Not Supported)
11304 10:05:43.588720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11305 10:05:43.588863
11306 10:05:43.589110 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11308 10:05:43.596919 Codec ioctls:
11309 10:05:43.603712 <LAVA_SIGNAL_TESTSET STOP>
11310 10:05:43.603955 Received signal: <TESTSET> STOP
11311 10:05:43.604023 Closing test_set Format-ioctls
11312 10:05:43.613008 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11313 10:05:43.613284 Received signal: <TESTSET> START Codec-ioctls
11314 10:05:43.613379 Starting test_set Codec-ioctls
11315 10:05:43.616096 test VIDIOC_(TRY_)ENCODER_CMD: OK
11316 10:05:43.637853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11317 10:05:43.638102 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11319 10:05:43.644424 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11320 10:05:43.663242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11321 10:05:43.663491 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11323 10:05:43.669689 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11324 10:05:43.687286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11325 10:05:43.687371
11326 10:05:43.687607 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11328 10:05:43.698165 Buffer ioctls:
11329 10:05:43.704880 <LAVA_SIGNAL_TESTSET STOP>
11330 10:05:43.705136 Received signal: <TESTSET> STOP
11331 10:05:43.705204 Closing test_set Codec-ioctls
11332 10:05:43.714836 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11333 10:05:43.715088 Received signal: <TESTSET> START Buffer-ioctls
11334 10:05:43.715158 Starting test_set Buffer-ioctls
11335 10:05:43.717918 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11336 10:05:43.742497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11337 10:05:43.742584 test VIDIOC_EXPBUF: OK
11338 10:05:43.742818 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11340 10:05:43.764028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11341 10:05:43.764284 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11343 10:05:43.767341 test Requests: OK (Not Supported)
11344 10:05:43.786887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11345 10:05:43.786973
11346 10:05:43.787209 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11348 10:05:43.796706 Test input 0:
11349 10:05:43.806720
11350 10:05:43.817833 Streaming ioctls:
11351 10:05:43.824972 <LAVA_SIGNAL_TESTSET STOP>
11352 10:05:43.825223 Received signal: <TESTSET> STOP
11353 10:05:43.825292 Closing test_set Buffer-ioctls
11354 10:05:43.834434 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11355 10:05:43.834687 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11356 10:05:43.834760 Starting test_set Streaming-ioctls_Test-input-0
11357 10:05:43.837980 test read/write: OK (Not Supported)
11358 10:05:43.858997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11359 10:05:43.859248 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11361 10:05:43.865836 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2778): node->streamon(q.g_type())
11362 10:05:43.876266 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2825): testBlockingDQBuf(node, q)
11363 10:05:43.879848 test blocking wait: FAIL
11364 10:05:43.903968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11365 10:05:43.904222 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11367 10:05:43.914269 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11368 10:05:43.917033 test MMAP (select): FAIL
11369 10:05:43.940819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11370 10:05:43.941074 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11372 10:05:43.947414 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11373 10:05:43.950740 test MMAP (epoll): FAIL
11374 10:05:43.974691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11375 10:05:43.974950 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11377 10:05:43.984292 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11378 10:05:43.990867 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11379 10:05:43.995165 test USERPTR (select): FAIL
11380 10:05:44.020492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11381 10:05:44.021317 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11383 10:05:44.026761 test DMABUF: Cannot test, specify --expbuf-device
11384 10:05:44.027240
11385 10:05:44.046550 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11386 10:05:44.050033 <LAVA_TEST_RUNNER EXIT>
11387 10:05:44.050761 ok: lava_test_shell seems to have completed
11388 10:05:44.051164 Marking unfinished test run as failed
11390 10:05:44.056671 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11391 10:05:44.057435 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11392 10:05:44.057941 end: 3 lava-test-retry (duration 00:00:03) [common]
11393 10:05:44.058438 start: 4 finalize (timeout 00:08:12) [common]
11394 10:05:44.058951 start: 4.1 power-off (timeout 00:00:30) [common]
11395 10:05:44.059765 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11396 10:05:44.172865 >> Command sent successfully.
11397 10:05:44.175953 Returned 0 in 0 seconds
11398 10:05:44.276826 end: 4.1 power-off (duration 00:00:00) [common]
11400 10:05:44.278382 start: 4.2 read-feedback (timeout 00:08:11) [common]
11401 10:05:44.279624 Listened to connection for namespace 'common' for up to 1s
11402 10:05:45.280267 Finalising connection for namespace 'common'
11403 10:05:45.280956 Disconnecting from shell: Finalise
11404 10:05:45.281366 / #
11405 10:05:45.382274 end: 4.2 read-feedback (duration 00:00:01) [common]
11406 10:05:45.382877 end: 4 finalize (duration 00:00:01) [common]
11407 10:05:45.383515 Cleaning after the job
11408 10:05:45.383988 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670678/tftp-deploy-rou30s_h/ramdisk
11409 10:05:45.403167 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670678/tftp-deploy-rou30s_h/kernel
11410 10:05:45.419080 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670678/tftp-deploy-rou30s_h/dtb
11411 10:05:45.419487 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10670678/tftp-deploy-rou30s_h/modules
11412 10:05:45.428366 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10670678
11413 10:05:45.486095 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10670678
11414 10:05:45.486268 Job finished correctly